[ { "path": ".gitignore", "content": "\nFirmware/FirmwareSource/Remora-OS6/TARGET_SKRV1_4/drivers/comms/MODDMA.lib\nFirmware/FirmwareSource/Remora-OS6/TARGET_SKRV1_4/drivers/comms/MODDMA/ChangeLog.c\nFirmware/FirmwareSource/Remora-OS6/TARGET_SKRV1_4/drivers/comms/MODDMA/CONFIG.h\nFirmware/FirmwareSource/Remora-OS6/TARGET_SKRV1_4/drivers/comms/MODDMA/DATALUTS.cpp\nFirmware/FirmwareSource/Remora-OS6/TARGET_SKRV1_4/drivers/comms/MODDMA/example1.h\nFirmware/FirmwareSource/Remora-OS6/TARGET_SKRV1_4/drivers/comms/MODDMA/example2.h\nFirmware/FirmwareSource/Remora-OS6/TARGET_SKRV1_4/drivers/comms/MODDMA/example3.h\nFirmware/FirmwareSource/Remora-OS6/TARGET_SKRV1_4/drivers/comms/MODDMA/example4.h\nFirmware/FirmwareSource/Remora-OS6/TARGET_SKRV1_4/drivers/comms/MODDMA/INIT.cpp\nFirmware/FirmwareSource/Remora-OS6/TARGET_SKRV1_4/drivers/comms/MODDMA/iomacros.h\nFirmware/FirmwareSource/Remora-OS6/TARGET_SKRV1_4/drivers/comms/MODDMA/MODDMA.cpp\nFirmware/FirmwareSource/Remora-OS6/TARGET_SKRV1_4/drivers/comms/MODDMA/MODDMA.h\nFirmware/FirmwareSource/Remora-OS6/TARGET_SKRV1_4/drivers/comms/MODDMA/SETUP.cpp\nFirmware/FirmwareSource/Remora-OS6/.mbed\n" }, { "path": "Firmware/ConfigSamples/BTT_Octopus/OCTOPUS_ENDER3/config.txt", "content": "{\r\n\t\"Board\": \"BIGTREETECH OCTOPUS\",\r\n\t\"Modules\":[\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Reset Pin\",\r\n\t\t\"Comment\":\t\t\t\"Reset pin\",\r\n\t\t\"Pin\":\t\t\t\t\"PC_15\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"X DRIVER0 - Joint 0 step generator\",\r\n\t\t\"Joint Number\":\t\t0,\r\n\t\t\"Step Pin\": \t\t\"PF_13\",\r\n\t\t\"Direction Pin\": \t\"PF_12\",\r\n\t\t\"Enable Pin\": \t\t\"PF_14\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Y DRIVER1 - Joint 1 step generator\",\r\n\t\t\"Joint Number\":\t\t1,\r\n\t\t\"Step Pin\": \t\t\"PG_0\",\r\n\t\t\"Direction Pin\": \t\"PG_1\",\r\n\t\t\"Enable Pin\": \t\t\"PF_15\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Z DRIVER2 - Joint 2 step generator\",\r\n\t\t\"Joint Number\":\t\t2,\r\n\t\t\"Step Pin\": \t\t\"PF_11\",\r\n\t\t\"Direction Pin\": \t\"PG_3\",\r\n\t\t\"Enable Pin\": \t\t\"PG_5\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"E0 DRIVER3 - Joint 3 step generator\",\r\n\t\t\"Joint Number\":\t\t3,\r\n\t\t\"Step Pin\": \t\t\"PG_4\",\r\n\t\t\"Direction Pin\": \t\"PC_1\",\r\n\t\t\"Enable Pin\": \t\t\"PA_0\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"X min DIAG0\",\r\n\t\t\"Pin\":\t\t\t\t\"PG_6\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t0\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"X max DIAG4\",\r\n\t\t\"Pin\":\t\t\t\t\"PG_12\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t1\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Y min DIAG1\",\r\n\t\t\"Pin\":\t\t\t\t\"PG_9\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t2\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Y max DIAG5\",\r\n\t\t\"Pin\":\t\t\t\t\"PG_13\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t3\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Z min DIAG2\",\r\n\t\t\"Pin\":\t\t\t\t\"PG_10\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t4\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Z max DIAG6\",\r\n\t\t\"Pin\":\t\t\t\t\"PG_14\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t5\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Temperature\",\r\n\t\t\"Comment\": \t\t\t\"Heated Bed tenperature sensor\",\r\n\t\t\"PV[i]\": \t\t\t0,\r\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\r\n\t\t\t\"Thermistor\":\r\n\t\t\t{\r\n\t\t\t\t\"Pin\": \t\t\"PF_3\",\r\n\t\t\t\t\"beta\": \t3990,\r\n\t\t\t\t\"r0\": \t\t100000,\r\n\t\t\t\t\"t0\": \t\t25\r\n\t\t\t}\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"PWM\",\r\n\t\t\"Comment\": \t\t\t\"Bed heater PWM\",\r\n\t\t\"SP[i]\": \t\t\t0,\r\n\t\t\"PWM Pin\": \t\t\t\"PA_1\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Temperature\",\r\n\t\t\"Comment\": \t\t\t\"Ext 0 temperature sensor\",\r\n\t\t\"PV[i]\": \t\t\t1,\r\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\r\n\t\t\t\"Thermistor\":\r\n\t\t\t{\r\n\t\t\t\t\"Pin\": \t\t\"PF_4\",\r\n\t\t\t\t\"beta\": \t3990,\r\n\t\t\t\t\"r0\": \t\t100000,\r\n\t\t\t\t\"t0\": \t\t25\r\n\t\t\t}\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"PWM\",\r\n\t\t\"Comment\": \t\t\t\"Ext0 heater PWM\",\r\n\t\t\"SP[i]\": \t\t\t1,\r\n\t\t\"PWM Pin\": \t\t\t\"PA_2\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"PWM\",\r\n\t\t\"Comment\": \t\t\t\"Ext0 part cooling fan PWM FAN0\",\r\n\t\t\"SP[i]\": \t\t\t2,\r\n\t\t\"PWM Max\":\t\t\t128,\r\n\t\t\"PWM Pin\": \t\t\t\"PA_8\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"RCServo\",\r\n\t\t\"Comment\": \t\t\t\"RC servo for probe bltouch according to marlin\",\r\n\t\t\"SP[i]\": \t\t\t3,\r\n\t\t\"Servo Pin\": \t\t\"PB_6\"\r\n\t}\r\n\t]\r\n}" }, { "path": "Firmware/ConfigSamples/BTT_Octopus/OCTOPUS_xyz/config.txt", "content": "{\r\n\t\"Board\": \"BIGTREETECH OCTOPUS\",\r\n\t\"Modules\":[\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Reset Pin\",\r\n\t\t\"Comment\":\t\t\t\"Reset pin\",\r\n\t\t\"Pin\":\t\t\t\t\"PC_15\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"X - Joint 0 step generator\",\r\n\t\t\"Joint Number\":\t\t0,\r\n\t\t\"Step Pin\": \t\t\"PF_13\",\r\n\t\t\"Direction Pin\": \t\"PF_12\",\r\n\t\t\"Enable Pin\": \t\t\"PF_14\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 step generator\",\r\n\t\t\"Joint Number\":\t\t1,\r\n\t\t\"Step Pin\": \t\t\"PG_0\",\r\n\t\t\"Direction Pin\": \t\"PG_1\",\r\n\t\t\"Enable Pin\": \t\t\"PF_15\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 step generator\",\r\n\t\t\"Joint Number\":\t\t2,\r\n\t\t\"Step Pin\": \t\t\"PF_11\",\r\n\t\t\"Direction Pin\": \t\"PG_3\",\r\n\t\t\"Enable Pin\": \t\t\"PG_5\"\r\n\t}\r\n\t]\r\n}\r\n" }, { "path": "Firmware/ConfigSamples/BTT_SKRv13/config.txt", "content": "{\n\t\"Board\": \"BIGTREETECH SKR v1.3 & v1.4\",\n\t\"Modules\":[\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Reset Pin\",\n\t\t\"Comment\":\t\t\t\"Reset pin\",\n\t\t\"Pin\":\t\t\t\t\"1.31\"\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"X - Joint 0 step generator\",\n\t\t\"Joint Number\":\t\t0,\n\t\t\"Step Pin\": \t\t\"2.2\",\n\t\t\"Direction Pin\": \t\"2.6\",\n\t\t\"Enable Pin\": \t\t\"2.1\"\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 step generator\",\n\t\t\"Joint Number\":\t\t1,\n\t\t\"Step Pin\": \t\t\"0.19\",\n\t\t\"Direction Pin\": \t\"0.20\",\n\t\t\"Enable Pin\": \t\t\"2.08\"\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 step generator\",\n\t\t\"Joint Number\":\t\t2,\n\t\t\"Step Pin\": \t\t\"0.22\",\n\t\t\"Direction Pin\": \t\"2.11\",\n\t\t\"Enable Pin\": \t\t\"0.21\"\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"E0 - Joint 3 step generator\",\n\t\t\"Joint Number\":\t\t3,\n\t\t\"Step Pin\": \t\t\"2.13\",\n\t\t\"Direction Pin\": \t\"0.11\",\n\t\t\"Enable Pin\": \t\t\"2.12\"\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Temperature\",\n\t\t\"Comment\": \t\t\t\"Extruder tenperature sensor\",\n\t\t\"PV[i]\": \t\t\t0,\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\n\t\t\t\"Thermistor\":\n\t\t\t{\n\t\t\t\t\"Pin\": \t\t\"0.23\",\n\t\t\t\t\"beta\": \t3990,\n\t\t\t\t\"r0\": \t\t100000,\n\t\t\t\t\"t0\": \t\t25\n\t\t\t}\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"RCServo\",\n\t\t\"Comment\": \t\t\t\"RC servo for probe\",\n\t\t\"SP[i]\": \t\t\t3,\n\t\t\"Servo Pin\": \t\t\"2.0\"\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Encoder\",\n\t\t\"Comment\":\t\t\t\"Encoder\",\n\t\t\"PV[i]\":\t\t\t2,\n\t\t\"ChA Pin\":\t\t\t\"1.20\",\n\t\t\"ChB Pin\":\t\t\t\"1.22\"\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"X min\",\n\t\t\"Pin\":\t\t\t\t\"1.29\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t0\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"X max\",\n\t\t\"Pin\":\t\t\t\t\"1.28\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t1\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Y min\",\n\t\t\"Pin\":\t\t\t\t\"1.27\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t2\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Y max\",\n\t\t\"Pin\":\t\t\t\t\"1.26\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t3\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Z min\",\n\t\t\"Pin\":\t\t\t\t\"1.25\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t4\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Z max\",\n\t\t\"Pin\":\t\t\t\t\"1.24\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t5\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Switch\",\n\t\t\"Comment\":\t\t\t\"Extruder fan switch\",\n\t\t\"Pin\":\t\t\t\t\"0.0\",\n\t\t\"Mode\":\t\t\t\t\"On\",\n\t\t\"PV[i]\":\t\t\t0,\n\t\t\"SP\":\t\t\t\t25.5\n\t}\n\t]\n}\n" }, { "path": "Firmware/ConfigSamples/BTT_SKRv14/SKRv14_3dp/config.txt", "content": "{\n\t\"Board\": \"BIGTREETECH SKR v1.4\",\n\t\"Modules\":[\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Reset Pin\",\n\t\t\"Comment\":\t\t\t\"Reset pin\",\n\t\t\"Pin\":\t\t\t\t\"1.31\"\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"X - Joint 0 step generator\",\n\t\t\"Joint Number\":\t\t0,\n\t\t\"Step Pin\": \t\t\"2.2\",\n\t\t\"Direction Pin\": \t\"2.6\",\n\t\t\"Enable Pin\": \t\t\"2.1\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"X - Joint 0 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"1.10\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 step generator\",\n\t\t\"Joint Number\":\t\t1,\n\t\t\"Step Pin\": \t\t\"0.19\",\n\t\t\"Direction Pin\": \t\"0.20\",\n\t\t\"Enable Pin\": \t\t\"2.08\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"1.9\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 step generator\",\n\t\t\"Joint Number\":\t\t2,\n\t\t\"Step Pin\": \t\t\"0.22\",\n\t\t\"Direction Pin\": \t\"2.11\",\n\t\t\"Enable Pin\": \t\t\"0.21\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"1.8\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"E0 - Joint 3 step generator\",\n\t\t\"Joint Number\":\t\t3,\n\t\t\"Step Pin\": \t\t\"2.13\",\n\t\t\"Direction Pin\": \t\"0.11\",\n\t\t\"Enable Pin\": \t\t\"2.12\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"E0 - Joint 3 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"1.4\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"E1 - Joint 4 step generator\",\n\t\t\"Joint Number\":\t\t4,\n\t\t\"Step Pin\": \t\t\"1.15\",\n\t\t\"Direction Pin\": \t\"1.14\",\n\t\t\"Enable Pin\": \t\t\"1.16\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"E1 - Joint 4 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"1.1\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"PWM\",\n\t\t\"Comment\": \t\t\t\"Bed heater PWM\",\n\t\t\"SP[i]\": \t\t\t0,\n\t\t\"PWM Pin\": \t\t\t\"2.5\"\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Temperature\",\n\t\t\"Comment\": \t\t\t\"Bed tenperature sensor\",\n\t\t\"PV[i]\": \t\t\t0,\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\n\t\t\t\"Thermistor\":\n\t\t\t{\n\t\t\t\t\"Pin\": \t\t\"0.25\",\n\t\t\t\t\"beta\": \t3990,\n\t\t\t\t\"r0\": \t\t100000,\n\t\t\t\t\"t0\": \t\t25\n\t\t\t}\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"PWM\",\n\t\t\"Comment\": \t\t\t\"Hotend 0 heater PWM\",\n\t\t\"SP[i]\": \t\t\t1,\n\t\t\"PWM Pin\": \t\t\t\"2.7\"\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Temperature\",\n\t\t\"Comment\": \t\t\t\"Hotend 0 tenperature sensor\",\n\t\t\"PV[i]\": \t\t\t1,\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\n\t\t\t\"Thermistor\":\n\t\t\t{\n\t\t\t\t\"Pin\": \t\t\"0.24\",\n\t\t\t\t\"beta\": \t3990,\n\t\t\t\t\"r0\": \t\t100000,\n\t\t\t\t\"t0\": \t\t25\n\t\t\t}\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"PWM\",\n\t\t\"Comment\": \t\t\t\"Hotend 1 heater PWM\",\n\t\t\"SP[i]\": \t\t\t2,\n\t\t\"PWM Pin\": \t\t\t\"2.4\"\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Temperature\",\n\t\t\"Comment\": \t\t\t\"Hotend 1 tenperature sensor\",\n\t\t\"PV[i]\": \t\t\t2,\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\n\t\t\t\"Thermistor\":\n\t\t\t{\n\t\t\t\t\"Pin\": \t\t\"0.23\",\n\t\t\t\t\"beta\": \t3990,\n\t\t\t\t\"r0\": \t\t100000,\n\t\t\t\t\"t0\": \t\t25\n\t\t\t}\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"X min\",\n\t\t\"Pin\":\t\t\t\t\"1.29\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t0\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Y min\",\n\t\t\"Pin\":\t\t\t\t\"1.28\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t1\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Z min\",\n\t\t\"Pin\":\t\t\t\t\"1.27\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t2\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"E0DET\",\n\t\t\"Pin\":\t\t\t\t\"1.26\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t3\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"E1DET\",\n\t\t\"Pin\":\t\t\t\t\"1.25\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t4\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"PWRDET\",\n\t\t\"Pin\":\t\t\t\t\"1.0\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t5\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Probe\",\n\t\t\"Pin\":\t\t\t\t\"0.10\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t6\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"RCServo\",\n\t\t\"Comment\": \t\t\t\"RC servo for probe\",\n\t\t\"SP[i]\": \t\t\t3,\n\t\t\"Servo Pin\": \t\t\"2.0\"\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Switch\",\n\t\t\"Comment\":\t\t\t\"Extruder fan switch\",\n\t\t\"Pin\":\t\t\t\t\"0.0\",\n\t\t\"Mode\":\t\t\t\t\"On\",\n\t\t\"PV[i]\":\t\t\t1,\n\t\t\"SP\":\t\t\t\t25.5\n\t}\n\t]\n}\n" }, { "path": "Firmware/ConfigSamples/BTT_SKRv14/SKRv14_TMC2209/config.txt", "content": "{\n\t\"Board\": \"BIGTREETECH SKR v1.4\",\n\t\"Modules\":[\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Reset Pin\",\n\t\t\"Comment\":\t\t\t\"Reset pin\",\n\t\t\"Pin\":\t\t\t\t\"1.31\"\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"X - Joint 0 step generator\",\n\t\t\"Joint Number\":\t\t0,\n\t\t\"Step Pin\": \t\t\"2.2\",\n\t\t\"Direction Pin\": \t\"2.6\",\n\t\t\"Enable Pin\": \t\t\"2.1\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"X - Joint 0 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"1.10\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 step generator\",\n\t\t\"Joint Number\":\t\t1,\n\t\t\"Step Pin\": \t\t\"0.19\",\n\t\t\"Direction Pin\": \t\"0.20\",\n\t\t\"Enable Pin\": \t\t\"2.08\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"1.9\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 step generator\",\n\t\t\"Joint Number\":\t\t2,\n\t\t\"Step Pin\": \t\t\"0.22\",\n\t\t\"Direction Pin\": \t\"2.11\",\n\t\t\"Enable Pin\": \t\t\"0.21\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"1.8\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"E0 - Joint 3 step generator\",\n\t\t\"Joint Number\":\t\t3,\n\t\t\"Step Pin\": \t\t\"2.13\",\n\t\t\"Direction Pin\": \t\"0.11\",\n\t\t\"Enable Pin\": \t\t\"2.12\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"E0 - Joint 3 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"1.4\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"E1 - Joint 4 step generator\",\n\t\t\"Joint Number\":\t\t4,\n\t\t\"Step Pin\": \t\t\"1.15\",\n\t\t\"Direction Pin\": \t\"1.14\",\n\t\t\"Enable Pin\": \t\t\"1.16\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"E1 - Joint 4 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"1.1\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"PWM\",\n\t\t\"Comment\": \t\t\t\"Bed heater PWM\",\n\t\t\"SP[i]\": \t\t\t0,\n\t\t\"PWM Pin\": \t\t\t\"2.5\"\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Temperature\",\n\t\t\"Comment\": \t\t\t\"Bed tenperature sensor\",\n\t\t\"PV[i]\": \t\t\t0,\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\n\t\t\t\"Thermistor\":\n\t\t\t{\n\t\t\t\t\"Pin\": \t\t\"0.25\",\n\t\t\t\t\"beta\": \t3990,\n\t\t\t\t\"r0\": \t\t100000,\n\t\t\t\t\"t0\": \t\t25\n\t\t\t}\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"PWM\",\n\t\t\"Comment\": \t\t\t\"Hotend 0 heater PWM\",\n\t\t\"SP[i]\": \t\t\t1,\n\t\t\"PWM Pin\": \t\t\t\"2.7\"\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Temperature\",\n\t\t\"Comment\": \t\t\t\"Hotend 0 tenperature sensor\",\n\t\t\"PV[i]\": \t\t\t1,\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\n\t\t\t\"Thermistor\":\n\t\t\t{\n\t\t\t\t\"Pin\": \t\t\"0.24\",\n\t\t\t\t\"beta\": \t3990,\n\t\t\t\t\"r0\": \t\t100000,\n\t\t\t\t\"t0\": \t\t25\n\t\t\t}\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"PWM\",\n\t\t\"Comment\": \t\t\t\"Hotend 1 heater PWM\",\n\t\t\"SP[i]\": \t\t\t2,\n\t\t\"PWM Pin\": \t\t\t\"2.4\"\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Temperature\",\n\t\t\"Comment\": \t\t\t\"Hotend 1 tenperature sensor\",\n\t\t\"PV[i]\": \t\t\t2,\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\n\t\t\t\"Thermistor\":\n\t\t\t{\n\t\t\t\t\"Pin\": \t\t\"0.23\",\n\t\t\t\t\"beta\": \t3990,\n\t\t\t\t\"r0\": \t\t100000,\n\t\t\t\t\"t0\": \t\t25\n\t\t\t}\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"X min\",\n\t\t\"Pin\":\t\t\t\t\"1.29\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t0\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Y min\",\n\t\t\"Pin\":\t\t\t\t\"1.28\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t1\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Z min\",\n\t\t\"Pin\":\t\t\t\t\"1.27\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t2\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"E0DET\",\n\t\t\"Pin\":\t\t\t\t\"1.26\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t3\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"E1DET\",\n\t\t\"Pin\":\t\t\t\t\"1.25\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t4\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"PWRDET\",\n\t\t\"Pin\":\t\t\t\t\"1.0\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t5\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Probe\",\n\t\t\"Pin\":\t\t\t\t\"0.10\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t6\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"RCServo\",\n\t\t\"Comment\": \t\t\t\"RC servo for probe\",\n\t\t\"SP[i]\": \t\t\t3,\n\t\t\"Servo Pin\": \t\t\"2.0\"\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Switch\",\n\t\t\"Comment\":\t\t\t\"Extruder fan switch\",\n\t\t\"Pin\":\t\t\t\t\"0.0\",\n\t\t\"Mode\":\t\t\t\t\"On\",\n\t\t\"PV[i]\":\t\t\t1,\n\t\t\"SP\":\t\t\t\t25.5\n\t}\n\t]\n}\n" }, { "path": "Firmware/ConfigSamples/BTT_SKRv14/SKRv14_xyz/config.txt", "content": "{\r\n\t\"Board\": \"BIGTREETECH SKR v1.3 & v1.4\",\r\n\t\"Modules\":[\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Reset Pin\",\r\n\t\t\"Comment\":\t\t\t\"Reset pin\",\r\n\t\t\"Pin\":\t\t\t\t\"1.31\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"X - Joint 0 step generator\",\r\n\t\t\"Joint Number\":\t\t0,\r\n\t\t\"Step Pin\": \t\t\"2.2\",\r\n\t\t\"Direction Pin\": \t\"2.6\",\r\n\t\t\"Enable Pin\": \t\t\"2.1\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 step generator\",\r\n\t\t\"Joint Number\":\t\t1,\r\n\t\t\"Step Pin\": \t\t\"0.19\",\r\n\t\t\"Direction Pin\": \t\"0.20\",\r\n\t\t\"Enable Pin\": \t\t\"2.08\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 step generator\",\r\n\t\t\"Joint Number\":\t\t2,\r\n\t\t\"Step Pin\": \t\t\"0.22\",\r\n\t\t\"Direction Pin\": \t\"2.11\",\r\n\t\t\"Enable Pin\": \t\t\"0.21\"\r\n\t}\r\n\t]\r\n}\r\n" }, { "path": "Firmware/ConfigSamples/BTT_SKRv2/SKRv2_TMC2209/config.txt", "content": "{\n\t\"Board\": \"BIGTREETECH SKR v2\",\n\t\"Modules\":[\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Reset Pin\",\n\t\t\"Comment\":\t\t\t\"Reset pin\",\n\t\t\"Pin\":\t\t\t\t\"PC_4\"\n\t},\n\t\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"Motor Power\",\n\t\t\"Comment\": \"Enable motor power SKR2\",\n\t\t\"Pin\":\t\t\t\t\t \"PC_13\"\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"X - Joint 0 step generator\",\n\t\t\"Joint Number\":\t\t0,\n\t\t\"Step Pin\": \t\t\"PE_2\",\n\t\t\"Direction Pin\": \t\"PE_1\",\n\t\t\"Enable Pin\": \t\t\"PE_3\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"X - Joint 0 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"PE_0\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 step generator\",\n\t\t\"Joint Number\":\t\t1,\n\t\t\"Step Pin\": \t\t\"PD_5\",\n\t\t\"Direction Pin\": \t\"PD_4\",\n\t\t\"Enable Pin\": \t\t\"PD_6\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"PD_3\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 step generator\",\n\t\t\"Joint Number\":\t\t2,\n\t\t\"Step Pin\": \t\t\"PA_15\",\n\t\t\"Direction Pin\": \t\"PA_8\",\n\t\t\"Enable Pin\": \t\t\"PD_1\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"PD_0\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"E0 - Joint 3 step generator\",\n\t\t\"Joint Number\":\t\t3,\n\t\t\"Step Pin\": \t\t\"PD_15\",\n\t\t\"Direction Pin\": \t\"PD_14\",\n\t\t\"Enable Pin\": \t\t\"PC_7\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"E0 - Joint 3 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"PC_6\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"E1 - Joint 4 step generator\",\n\t\t\"Joint Number\":\t\t4,\n\t\t\"Step Pin\": \t\t\"PD_11\",\n\t\t\"Direction Pin\": \t\"PD_10\",\n\t\t\"Enable Pin\": \t\t\"PD_13\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"E1 - Joint 4 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"PD_12\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"X min\",\n\t\t\"Pin\":\t\t\t\t\"PC_1\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t0\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"X max\",\n\t\t\"Pin\":\t\t\t\t\"PC_2\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t1\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Y min\",\n\t\t\"Pin\":\t\t\t\t\"PC_3\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t2\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Y max\",\n\t\t\"Pin\":\t\t\t\t\"PA_0\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t3\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Z min\",\n\t\t\"Pin\":\t\t\t\t\"PC_0\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t4\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Z max\",\n\t\t\"Pin\":\t\t\t\t\"PC_15\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t5\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Switch\",\n\t\t\"Comment\":\t\t\t\"Extruder fan switch\",\n\t\t\"Pin\":\t\t\t\t\"PB_7\",\n\t\t\"Mode\":\t\t\t\t\"On\",\n\t\t\"PV[i]\":\t\t\t0,\n\t\t\"SP\":\t\t\t\t25.5\n\t}\n\t]\n}\n" }, { "path": "Firmware/ConfigSamples/BTT_SKRv2/SKRv2_ender3/config.txt", "content": "{\r\n\t\"Board\": \"BIGTREETECH SKR v2\",\r\n\t\"Modules\":[\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Reset Pin\",\r\n\t\t\"Comment\":\t\t\t\"Reset pin\",\r\n\t\t\"Pin\":\t\t\t\t\"PC_4\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"On load\",\r\n\t\"Type\": \"Motor Power\",\r\n\t\"Comment\": \"Enable motor power SKR2\",\r\n\t\"Pin\":\t\t\t\t\t \"PC_13\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"X - Joint 0 step generator\",\r\n\t\t\"Joint Number\":\t\t0,\r\n\t\t\"Step Pin\": \t\t\"PE_2\",\r\n\t\t\"Direction Pin\": \t\"PE_1\",\r\n\t\t\"Enable Pin\": \t\t\"PE_3\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 step generator\",\r\n\t\t\"Joint Number\":\t\t1,\r\n\t\t\"Step Pin\": \t\t\"PD_5\",\r\n\t\t\"Direction Pin\": \t\"PD_4\",\r\n\t\t\"Enable Pin\": \t\t\"PD_6\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 step generator\",\r\n\t\t\"Joint Number\":\t\t2,\r\n\t\t\"Step Pin\": \t\t\"PA_15\",\r\n\t\t\"Direction Pin\": \t\"PA_8\",\r\n\t\t\"Enable Pin\": \t\t\"PD_1\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"E0 - Joint 3 step generator\",\r\n\t\t\"Joint Number\":\t\t3,\r\n\t\t\"Step Pin\": \t\t\"PD_15\",\r\n\t\t\"Direction Pin\": \t\"PD_14\",\r\n\t\t\"Enable Pin\": \t\t\"PC_7\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"X min\",\r\n\t\t\"Pin\":\t\t\t\t\"PC_1\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t0\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"X max\",\r\n\t\t\"Pin\":\t\t\t\t\"PC_2\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t1\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Y min\",\r\n\t\t\"Pin\":\t\t\t\t\"PC_3\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t2\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Y max\",\r\n\t\t\"Pin\":\t\t\t\t\"PA_0\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t3\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Z min\",\r\n\t\t\"Pin\":\t\t\t\t\"PC_0\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t4\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Z max\",\r\n\t\t\"Pin\":\t\t\t\t\"PC_15\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t5\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Temperature\",\r\n\t\t\"Comment\": \t\t\t\"Heated Bed tenperature sensor\",\r\n\t\t\"PV[i]\": \t\t\t0,\r\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\r\n\t\t\t\"Thermistor\":\r\n\t\t\t{\r\n\t\t\t\t\"Pin\": \t\t\"PA_1\",\r\n\t\t\t\t\"beta\": \t3990,\r\n\t\t\t\t\"r0\": \t\t100000,\r\n\t\t\t\t\"t0\": \t\t25\r\n\t\t\t}\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"PWM\",\r\n\t\t\"Comment\": \t\t\t\"Bed heater PWM\",\r\n\t\t\"SP[i]\": \t\t\t0,\r\n\t\t\"PWM Pin\": \t\t\t\"PD_7\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Temperature\",\r\n\t\t\"Comment\": \t\t\t\"Ext 0 temperature sensor\",\r\n\t\t\"PV[i]\": \t\t\t1,\r\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\r\n\t\t\t\"Thermistor\":\r\n\t\t\t{\r\n\t\t\t\t\"Pin\": \t\t\"PA_2\",\r\n\t\t\t\t\"beta\": \t3990,\r\n\t\t\t\t\"r0\": \t\t100000,\r\n\t\t\t\t\"t0\": \t\t25\r\n\t\t\t}\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"PWM\",\r\n\t\t\"Comment\": \t\t\t\"Ext0 heater PWM\",\r\n\t\t\"SP[i]\": \t\t\t1,\r\n\t\t\"PWM Pin\": \t\t\t\"PB_3\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"PWM\",\r\n\t\t\"Comment\": \t\t\t\"Ext0 part cooling fan PWM FAN0\",\r\n\t\t\"SP[i]\": \t\t\t2,\r\n\t\t\"PWM Max\":\t\t\t128,\r\n\t\t\"PWM Pin\": \t\t\t\"PB_7\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"RCServo\",\r\n\t\t\"Comment\": \t\t\t\"RC servo for probe bltouch according to marlin\",\r\n\t\t\"SP[i]\": \t\t\t3,\r\n\t\t\"Servo Pin\": \t\t\"PE_5\"\r\n\t}\r\n\t]\r\n}\r\n" }, { "path": "Firmware/ConfigSamples/BTT_SKRv2/SKRv2_xyz/config.txt", "content": "{\n\t\"Board\": \"BIGTREETECH SKR v2\",\n\t\"Modules\":[\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Reset Pin\",\n\t\t\"Comment\":\t\t\t\"Reset pin\",\n\t\t\"Pin\":\t\t\t\t\"PC_4\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"Motor Power\",\n\t\t\"Comment\": \"Enable motor power SKR2\",\n\t\t\"Pin\":\t\t\t\t\t \"PC_13\"\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"X - Joint 0 step generator\",\n\t\t\"Joint Number\":\t\t0,\n\t\t\"Step Pin\": \t\t\"PE_2\",\n\t\t\"Direction Pin\": \t\"PE_1\",\n\t\t\"Enable Pin\": \t\t\"PE_3\"\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 step generator\",\n\t\t\"Joint Number\":\t\t1,\n\t\t\"Step Pin\": \t\t\"PD_5\",\n\t\t\"Direction Pin\": \t\"PD_4\",\n\t\t\"Enable Pin\": \t\t\"PD_6\"\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 step generator\",\n\t\t\"Joint Number\":\t\t2,\n\t\t\"Step Pin\": \t\t\"PA_15\",\n\t\t\"Direction Pin\": \t\"PA_8\",\n\t\t\"Enable Pin\": \t\t\"PD_1\"\n\t},\n\t\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"X min\",\n\t\t\"Pin\":\t\t\t\t\"PC_1\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t0\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"X max\",\n\t\t\"Pin\":\t\t\t\t\"PC_2\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t1\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Y min\",\n\t\t\"Pin\":\t\t\t\t\"PC_3\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t2\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Y max\",\n\t\t\"Pin\":\t\t\t\t\"PA_0\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t3\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Z min\",\n\t\t\"Pin\":\t\t\t\t\"PC_0\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t4\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Z max\",\n\t\t\"Pin\":\t\t\t\t\"PC_15\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t5\n\n\t}\n\t]\n}\n" }, { "path": "Firmware/ConfigSamples/Fysetc_Spider/config.txt", "content": "{\r\n\t\"Board\": \"FYSETC SPIDER\",\r\n\t\"Modules\":[\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Reset Pin\",\r\n\t\t\"Comment\":\t\t\t\"Reset pin\",\r\n\t\t\"Pin\":\t\t\t\t\"PC_7\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"X M1 - Joint 0 step generator\",\r\n\t\t\"Joint Number\":\t\t0,\r\n\t\t\"Step Pin\": \t\t\"PE_11\",\r\n\t\t\"Direction Pin\": \t\"PE_10\",\r\n\t\t\"Enable Pin\": \t\t\"PE_9\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Y M2 - Joint 1 step generator\",\r\n\t\t\"Joint Number\":\t\t1,\r\n\t\t\"Step Pin\": \t\t\"PD_8\",\r\n\t\t\"Direction Pin\": \t\"PB_12\",\r\n\t\t\"Enable Pin\": \t\t\"PD_9\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Z M3 - Joint 2 step generator\",\r\n\t\t\"Joint Number\":\t\t2,\r\n\t\t\"Step Pin\": \t\t\"PD_14\",\r\n\t\t\"Direction Pin\": \t\"PD_13\",\r\n\t\t\"Enable Pin\": \t\t\"PD_15\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"E0 M4 - Joint 3 step generator\",\r\n\t\t\"Joint Number\":\t\t3,\r\n\t\t\"Step Pin\": \t\t\"PD_5\",\r\n\t\t\"Direction Pin\": \t\"PD_6\",\r\n\t\t\"Enable Pin\": \t\t\"PD_4\"\r\n\t},\r\n\t\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"E1 M5 - Joint 4 step generator\",\r\n\t\t\"Joint Number\":\t\t4,\r\n\t\t\"Step Pin\": \t\t\"PE_6\",\r\n\t\t\"Direction Pin\": \t\"PC_13\",\r\n\t\t\"Enable Pin\": \t\t\"PE_5\"\r\n\t},\r\n\t\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"E2 M6 - Joint 5 step generator\",\r\n\t\t\"Joint Number\":\t\t5,\r\n\t\t\"Step Pin\": \t\t\"PE_2\",\r\n\t\t\"Direction Pin\": \t\"PE_4\",\r\n\t\t\"Enable Pin\": \t\t\"PE_3\"\r\n\t},\r\n\t\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"E3 M7 - Joint 6 step generator\",\r\n\t\t\"Joint Number\":\t\t6,\r\n\t\t\"Step Pin\": \t\t\"PD_12\",\r\n\t\t\"Direction Pin\": \t\"PC_4\",\r\n\t\t\"Enable Pin\": \t\t\"PE_8\"\r\n\t},\r\n\t\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"E4 M8 - Joint 7 step generator\",\r\n\t\t\"Joint Number\":\t\t7,\r\n\t\t\"Step Pin\": \t\t\"PE_1\",\r\n\t\t\"Direction Pin\": \t\"PE_0\",\r\n\t\t\"Enable Pin\": \t\t\"PC_5\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Temperature\",\r\n\t\t\"Comment\": \t\t\t\"Extruder tenperature sensor\",\r\n\t\t\"PV[i]\": \t\t\t0,\r\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\r\n\t\t\t\"Thermistor\":\r\n\t\t\t{\r\n\t\t\t\t\"Pin\": \t\t\"PC_0\",\r\n\t\t\t\t\"beta\": \t3990,\r\n\t\t\t\t\"r0\": \t\t100000,\r\n\t\t\t\t\"t0\": \t\t25\r\n\t\t\t}\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"X min X-DIAG\",\r\n\t\t\"Pin\":\t\t\t\t\"PB_14\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t0\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"X max E0-DIAG\",\r\n\t\t\"Pin\":\t\t\t\t\"PA_1\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t1\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Y min Y-DIAG\",\r\n\t\t\"Pin\":\t\t\t\t\"PB_13\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t2\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Y max E1-DIAG\",\r\n\t\t\"Pin\":\t\t\t\t\"PA_2\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t3\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Z min Z-DIAG\",\r\n\t\t\"Pin\":\t\t\t\t\"PA_0\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t4\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Z max E2-DIAG\",\r\n\t\t\"Pin\":\t\t\t\t\"PA_3\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t5\r\n\t}\r\n\t]\r\n}" }, { "path": "Firmware/ConfigSamples/Fysetc_Spider_King/config.txt", "content": "{\r\n\t\"Board\": \"FYSETC SPIDER KING\",\r\n\t\"Modules\":[\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Reset Pin\",\r\n\t\t\"Comment\":\t\t\t\"Reset pin\",\r\n\t\t\"Pin\":\t\t\t\t\"PB_11\"\r\n\t}\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"X - Joint 0 step generator\",\r\n\t\t\"Joint Number\":\t\t0,\r\n\t\t\"Step Pin\": \t\t\"PE_2\",\r\n\t\t\"Direction Pin\": \t\"PE_1\",\r\n\t\t\"Enable Pin\": \t\t\"PE_3\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"On load\",\r\n\t\"Type\": \"TMC stepper\",\r\n\t\t\"Comment\":\t\t\t\"X - Joint 0 TMC driver\",\r\n\t\t\"Driver\": \t\t\t\"2209\",\r\n\t\t\"RX pin\": \t\t\t\"PE_0\",\r\n\t\t\"RSense\":\t\t\t0.11,\r\n\t\t\"Current\":\t\t\t800,\r\n\t\t\"Microsteps\":\t\t16,\r\n\t\t\"Stealth chop\":\t\t\"on\",\r\n\t\t\"Stall sensitivity\":0\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 step generator\",\r\n\t\t\"Joint Number\":\t\t1,\r\n\t\t\"Step Pin\": \t\t\"PD_5\",\r\n\t\t\"Direction Pin\": \t\"PD_4\",\r\n\t\t\"Enable Pin\": \t\t\"PD_6\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"On load\",\r\n\t\"Type\": \"TMC stepper\",\r\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 TMC driver\",\r\n\t\t\"Driver\": \t\t\t\"2209\",\r\n\t\t\"RX pin\": \t\t\t\"PD_3\",\r\n\t\t\"RSense\":\t\t\t0.11,\r\n\t\t\"Current\":\t\t\t800,\r\n\t\t\"Microsteps\":\t\t16,\r\n\t\t\"Stealth chop\":\t\t\"on\",\r\n\t\t\"Stall sensitivity\":0\r\n\t}\r\n\t\r\n\t]\r\n}\r\n" }, { "path": "Firmware/ConfigSamples/Hypercube-evolution/config.txt", "content": "{\r\n\t\"Board\": \"MKS SBASE v1.3\",\r\n\t\"Modules\":[\r\n\t{\r\n\t\"Thread\": \"On load\",\r\n\t\"Type\": \"MCP4451\",\r\n\t\t\"Comment\":\t\t\t\"Digipot for joints 0 - 3\",\r\n\t\t\"I2C SDA pin\":\t\t\"0.0\",\r\n\t\t\"I2C SCL pin\":\t\t\"0.1\",\r\n\t\t\"I2C address\":\t\t0,\r\n\t\t\"Max current\":\t\t2.0,\r\n\t\t\"Factor\":\t\t\t113.33,\r\n\t\t\"Current 0\":\t\t0.8,\r\n\t\t\"Current 1\":\t\t0.8,\r\n\t\t\"Current 2\":\t\t0.8,\r\n\t\t\"Current 3\":\t\t0.8\r\n\t},\r\n\t{\r\n\t\"Thread\": \"On load\",\r\n\t\"Type\": \"MCP4451\",\r\n\t\t\"Comment\":\t\t\t\"Digipot for joints 4 - 7\",\r\n\t\t\"I2C SDA pin\":\t\t\"0.0\",\r\n\t\t\"I2C SCL pin\":\t\t\"0.1\",\r\n\t\t\"I2C address\":\t\t2,\r\n\t\t\"Max current\":\t\t2.0,\r\n\t\t\"Factor\":\t\t\t113.33,\r\n\t\t\"Current 0\":\t\t0.8,\r\n\t\t\"Current 1\":\t\t0.8,\r\n\t\t\"Current 2\":\t\t0.8,\r\n\t\t\"Current 3\":\t\t0.8\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"X - Joint 0 step generator\",\r\n\t\t\"Joint Number\":\t\t0,\r\n\t\t\"Step Pin\": \t\t\"2.0\",\r\n\t\t\"Direction Pin\": \t\"0.5\",\r\n\t\t\"Enable Pin\": \t\t\"0.4\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 step generator\",\r\n\t\t\"Joint Number\":\t\t1,\r\n\t\t\"Step Pin\": \t\t\"2.1\",\r\n\t\t\"Direction Pin\": \t\"0.11\",\r\n\t\t\"Enable Pin\": \t\t\"0.10\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Z1 - Joint 2 step generator\",\r\n\t\t\"Joint Number\":\t\t2,\r\n\t\t\"Step Pin\": \t\t\"2.2\",\r\n\t\t\"Direction Pin\": \t\"0.20\",\r\n\t\t\"Enable Pin\": \t\t\"0.19\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Z2 - Joint 2 step generator\",\r\n\t\t\"Joint Number\":\t\t3,\r\n\t\t\"Step Pin\": \t\t\"2.3\",\r\n\t\t\"Direction Pin\": \t\"0.22\",\r\n\t\t\"Enable Pin\": \t\t\"0.21\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"E - Joint 3 step generator\",\r\n\t\t\"Joint Number\":\t\t4,\r\n\t\t\"Step Pin\": \t\t\"2.8\",\r\n\t\t\"Direction Pin\": \t\"2.13\",\r\n\t\t\"Enable Pin\": \t\t\"4.29\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Blink\",\r\n\t\t\"Pin\":\t\t\t\t\"1.18\",\r\n\t\t\"Frequency\":\t\t2\r\n\t},\t\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"X min\",\r\n\t\t\"Pin\":\t\t\t\t\"1.24\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t0\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"X max\",\r\n\t\t\"Pin\":\t\t\t\t\"1.25\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t1\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Y min\",\r\n\t\t\"Pin\":\t\t\t\t\"1.26\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t2\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Y max\",\r\n\t\t\"Pin\":\t\t\t\t\"1.27\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t3\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Z min\",\r\n\t\t\"Pin\":\t\t\t\t\"1.28\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t4\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Z max\",\r\n\t\t\"Pin\":\t\t\t\t\"1.29\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t5\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Temperature\",\r\n\t\t\"Comment\": \t\t\t\"Heated Bed tenperature sensor\",\r\n\t\t\"PV[i]\": \t\t\t0,\r\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\r\n\t\t\t\"Thermistor\":\r\n\t\t\t{\r\n\t\t\t\t\"Pin\": \t\t\"0.23\",\r\n\t\t\t\t\"beta\": \t3990,\r\n\t\t\t\t\"r0\": \t\t100000,\r\n\t\t\t\t\"t0\": \t\t25\r\n\t\t\t}\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"PWM\",\r\n\t\t\"Comment\": \t\t\t\"Bed heater PWM\",\r\n\t\t\"SP[i]\": \t\t\t0,\r\n\t\t\"PWM Pin\": \t\t\t\"2.5\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Temperature\",\r\n\t\t\"Comment\": \t\t\t\"Ext 0 temperature sensor\",\r\n\t\t\"PV[i]\": \t\t\t1,\r\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\r\n\t\t\t\"Thermistor\":\r\n\t\t\t{\r\n\t\t\t\t\"Pin\": \t\t\"0.24\",\r\n\t\t\t\t\"beta\": \t3990,\r\n\t\t\t\t\"r0\": \t\t100000,\r\n\t\t\t\t\"t0\": \t\t25\r\n\t\t\t}\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"PWM\",\r\n\t\t\"Comment\": \t\t\t\"Ext0 heater PWM\",\r\n\t\t\"SP[i]\": \t\t\t1,\r\n\t\t\"PWM Pin\": \t\t\t\"2.7\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"PWM\",\r\n\t\t\"Comment\": \t\t\t\"Ext0 part cooling fan PWM\",\r\n\t\t\"SP[i]\": \t\t\t2,\r\n\t\t\"PWM Max\":\t\t\t128,\r\n\t\t\"PWM Pin\": \t\t\t\"2.4\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"RCServo\",\r\n\t\t\"Comment\": \t\t\t\"RC servo for probe\",\r\n\t\t\"SP[i]\": \t\t\t3,\r\n\t\t\"Servo Pin\": \t\t\"1.23\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Switch\",\r\n\t\t\"Comment\":\t\t\t\"Extruder fan switch\",\r\n\t\t\"Pin\":\t\t\t\t\"1.22\",\r\n\t\t\"Mode\":\t\t\t\t\"On\",\r\n\t\t\"PV[i]\":\t\t\t1,\r\n\t\t\"SP\":\t\t\t\t35.0\r\n\t}\r\n\t]\r\n}\r\n" }, { "path": "Firmware/ConfigSamples/MKS_Monster8/config.txt", "content": "{\r\n\t\"Board\": \"MKS MONSTER8\",\r\n\t\"Modules\":[\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Reset Pin\",\r\n\t\t\"Comment\":\t\t\t\"Reset pin USE BTN_EN2\",\r\n\t\t\"Pin\":\t\t\t\t\"PE_8\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"X - Joint 0 step generator\",\r\n\t\t\"Joint Number\":\t\t0,\r\n\t\t\"Step Pin\": \t\t\"PC_14\",\r\n\t\t\"Direction Pin\": \t\"PC_13\",\r\n\t\t\"Enable Pin\": \t\t\"PC_15\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 step generator\",\r\n\t\t\"Joint Number\":\t\t1,\r\n\t\t\"Step Pin\": \t\t\"PE_5\",\r\n\t\t\"Direction Pin\": \t\"PE_4\",\r\n\t\t\"Enable Pin\": \t\t\"PC_15\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 step generator\",\r\n\t\t\"Joint Number\":\t\t2,\r\n\t\t\"Step Pin\": \t\t\"PE_1\",\r\n\t\t\"Direction Pin\": \t\"PE_0\",\r\n\t\t\"Enable Pin\": \t\t\"PE_2\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"E0 DRIVER3 - Joint 3 step generator\",\r\n\t\t\"Joint Number\":\t\t3,\r\n\t\t\"Step Pin\": \t\t\"PB_5\",\r\n\t\t\"Direction Pin\": \t\"PB_4\",\r\n\t\t\"Enable Pin\": \t\t\"PB_6\"\r\n\t},\r\n\t\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"E1 DRIVER4 - Joint 4 step generator\",\r\n\t\t\"Joint Number\":\t\t4,\r\n\t\t\"Step Pin\": \t\t\"PD_6\",\r\n\t\t\"Direction Pin\": \t\"PD_5\",\r\n\t\t\"Enable Pin\": \t\t\"PD_7\"\r\n\t},\r\n\t\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"E2 DRIVER5 - Joint 5 step generator\",\r\n\t\t\"Joint Number\":\t\t5,\r\n\t\t\"Step Pin\": \t\t\"PD_2\",\r\n\t\t\"Direction Pin\": \t\"PD_1\",\r\n\t\t\"Enable Pin\": \t\t\"PD_3\"\r\n\t},\r\n\t\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"E3 DRIVER6 - Joint 6 step generator\",\r\n\t\t\"Joint Number\":\t\t6,\r\n\t\t\"Step Pin\": \t\t\"PC_7\",\r\n\t\t\"Direction Pin\": \t\"PC_6\",\r\n\t\t\"Enable Pin\": \t\t\"PC_8\"\r\n\t},\r\n\t\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"E4 DRIVER7 - Joint 7 step generator\",\r\n\t\t\"Joint Number\":\t\t7,\r\n\t\t\"Step Pin\": \t\t\"PD_13\",\r\n\t\t\"Direction Pin\": \t\"PD_12\",\r\n\t\t\"Enable Pin\": \t\t\"PD_14\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Temperature\",\r\n\t\t\"Comment\": \t\t\t\"Extruder tenperature sensor\",\r\n\t\t\"PV[i]\": \t\t\t0,\r\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\r\n\t\t\t\"Thermistor\":\r\n\t\t\t{\r\n\t\t\t\t\"Pin\": \t\t\"PC_1\",\r\n\t\t\t\t\"beta\": \t3990,\r\n\t\t\t\t\"r0\": \t\t100000,\r\n\t\t\t\t\"t0\": \t\t25\r\n\t\t\t}\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"RCServo\",\r\n\t\t\"Comment\": \t\t\t\"RC servo for probe bltouch according to marlin\",\r\n\t\t\"SP[i]\": \t\t\t3,\r\n\t\t\"Servo Pin\": \t\t\"PB_6\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"X min \",\r\n\t\t\"Pin\":\t\t\t\t\"PA_14\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t0\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"X max \",\r\n\t\t\"Pin\":\t\t\t\t\"PA_13\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t1\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Y min \",\r\n\t\t\"Pin\":\t\t\t\t\"PA_15\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t2\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Y max \",\r\n\t\t\"Pin\":\t\t\t\t\"PC_5\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t3\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Z min \",\r\n\t\t\"Pin\":\t\t\t\t\"PB_13\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t4\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Z max \",\r\n\t\t\"Pin\":\t\t\t\t\"PB_12\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t5\r\n\t}\r\n\t]\r\n}" }, { "path": "Firmware/ConfigSamples/MKS_Robin_E3/Robin_E3/config.txt", "content": "{\n\t\"Board\": \"Mks Robin E3\",\n\t\"Modules\":[\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Reset Pin\",\n\t\t\"Comment\":\t\t\t\"Reset pin\",\n\t\t\"Pin\":\t\t\t\t\"PC_5\"\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"X - Joint 0 step generator\",\n\t\t\"Joint Number\":\t\t0,\n\t\t\"Step Pin\": \t\t\"PC_0\",\n\t\t\"Direction Pin\": \t\"PB_2\",\n\t\t\"Enable Pin\": \t\t\"PC_13\"\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 step generator\",\n\t\t\"Joint Number\":\t\t1,\n\t\t\"Step Pin\": \t\t\"PC_2\",\n\t\t\"Direction Pin\": \t\"PB_9\",\n\t\t\"Enable Pin\": \t\t\"PB_12\"\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 step generator\",\n\t\t\"Joint Number\":\t\t2,\n\t\t\"Step Pin\": \t\t\"PC_14\",\n\t\t\"Direction Pin\": \t\"PC_15\",\n\t\t\"Enable Pin\": \t\t\"PB_8\"\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"E0 - Joint 3 step generator\",\n\t\t\"Joint Number\":\t\t3,\n\t\t\"Step Pin\": \t\t\"PB_4\",\n\t\t\"Direction Pin\": \t\"PB_3\",\n\t\t\"Enable Pin\": \t\t\"PB_5\"\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Temperature\",\n\t\t\"Comment\": \t\t\t\"Extruder tenperature sensor\",\n\t\t\"PV[i]\": \t\t\t0,\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\n\t\t\t\"Thermistor\":\n\t\t\t{\n\t\t\t\t\"Pin\": \t\t\"PA_0\",\n\t\t\t\t\"beta\": \t3990,\n\t\t\t\t\"r0\": \t\t100000,\n\t\t\t\t\"t0\": \t\t25\n\t\t\t}\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"RCServo\",\n\t\t\"Comment\": \t\t\t\"RC servo for probe\",\n\t\t\"SP[i]\": \t\t\t3,\n\t\t\"Servo Pin\": \t\t\"PA_3\"\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"X min\",\n\t\t\"Pin\":\t\t\t\t\"PA_12\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t0\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Y min\",\n\t\t\"Pin\":\t\t\t\t\"PA_11\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t2\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Z min\",\n\t\t\"Pin\":\t\t\t\t\"PC_6\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t4\n\t}\n\t]\n}\n" }, { "path": "Firmware/ConfigSamples/MKS_Sbase/MKS Sbase/Ender3/config.txt-Ender3", "content": "{\r\n\t\"Board\": \"MKS SBASE v1.3\",\r\n\t\"Modules\":[\r\n\t{\r\n\t\"Thread\": \"On load\",\r\n\t\"Type\": \"MCP4451\",\r\n\t\t\"Comment\":\t\t\t\"Digipot for joints 0 - 3\",\r\n\t\t\"I2C SDA pin\":\t\t\"0.0\",\r\n\t\t\"I2C SCL pin\":\t\t\"0.1\",\r\n\t\t\"I2C address\":\t\t0,\r\n\t\t\"Max current\":\t\t2.0,\r\n\t\t\"Factor\":\t\t\t113.33,\r\n\t\t\"Current 0\":\t\t0.8,\r\n\t\t\"Current 1\":\t\t0.8,\r\n\t\t\"Current 2\":\t\t0.8,\r\n\t\t\"Current 3\":\t\t0.8\r\n\t},\r\n\t{\r\n\t\"Thread\": \"On load\",\r\n\t\"Type\": \"MCP4451\",\r\n\t\t\"Comment\":\t\t\t\"Digipot for joints 4 - 7\",\r\n\t\t\"I2C SDA pin\":\t\t\"0.0\",\r\n\t\t\"I2C SCL pin\":\t\t\"0.1\",\r\n\t\t\"I2C address\":\t\t2,\r\n\t\t\"Max current\":\t\t2.0,\r\n\t\t\"Factor\":\t\t\t113.33,\r\n\t\t\"Current 0\":\t\t0.8,\r\n\t\t\"Current 1\":\t\t0.8,\r\n\t\t\"Current 2\":\t\t0.8,\r\n\t\t\"Current 3\":\t\t0.8\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"X - Joint 0 step generator\",\r\n\t\t\"Joint Number\":\t\t0,\r\n\t\t\"Step Pin\": \t\t\"2.0\",\r\n\t\t\"Direction Pin\": \t\"0.5\",\r\n\t\t\"Enable Pin\": \t\t\"0.4\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 step generator\",\r\n\t\t\"Joint Number\":\t\t1,\r\n\t\t\"Step Pin\": \t\t\"2.1\",\r\n\t\t\"Direction Pin\": \t\"0.11\",\r\n\t\t\"Enable Pin\": \t\t\"0.10\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 step generator\",\r\n\t\t\"Joint Number\":\t\t2,\r\n\t\t\"Step Pin\": \t\t\"2.2\",\r\n\t\t\"Direction Pin\": \t\"0.20\",\r\n\t\t\"Enable Pin\": \t\t\"0.19\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"E - Joint 3 step generator\",\r\n\t\t\"Joint Number\":\t\t3,\r\n\t\t\"Step Pin\": \t\t\"2.3\",\r\n\t\t\"Direction Pin\": \t\"0.22\",\r\n\t\t\"Enable Pin\": \t\t\"0.21\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Blink\",\r\n\t\t\"Pin\":\t\t\t\t\"1.18\",\r\n\t\t\"Frequency\":\t\t2\r\n\t},\t\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"X min\",\r\n\t\t\"Pin\":\t\t\t\t\"1.24\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t0\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"X max\",\r\n\t\t\"Pin\":\t\t\t\t\"1.25\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t1\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Y min\",\r\n\t\t\"Pin\":\t\t\t\t\"1.26\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t2\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Y max\",\r\n\t\t\"Pin\":\t\t\t\t\"1.27\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t3\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Z min\",\r\n\t\t\"Pin\":\t\t\t\t\"1.28\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t4\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Z max\",\r\n\t\t\"Pin\":\t\t\t\t\"1.29\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t5\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Temperature\",\r\n\t\t\"Comment\": \t\t\t\"Heated Bed tenperature sensor\",\r\n\t\t\"PV[i]\": \t\t\t0,\r\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\r\n\t\t\t\"Thermistor\":\r\n\t\t\t{\r\n\t\t\t\t\"Pin\": \t\t\"0.23\",\r\n\t\t\t\t\"beta\": \t3990,\r\n\t\t\t\t\"r0\": \t\t100000,\r\n\t\t\t\t\"t0\": \t\t25\r\n\t\t\t}\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"PWM\",\r\n\t\t\"Comment\": \t\t\t\"Bed heater PWM\",\r\n\t\t\"SP[i]\": \t\t\t0,\r\n\t\t\"PWM Pin\": \t\t\t\"2.5\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Temperature\",\r\n\t\t\"Comment\": \t\t\t\"Ext 0 temperature sensor\",\r\n\t\t\"PV[i]\": \t\t\t1,\r\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\r\n\t\t\t\"Thermistor\":\r\n\t\t\t{\r\n\t\t\t\t\"Pin\": \t\t\"0.24\",\r\n\t\t\t\t\"beta\": \t3990,\r\n\t\t\t\t\"r0\": \t\t100000,\r\n\t\t\t\t\"t0\": \t\t25\r\n\t\t\t}\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"PWM\",\r\n\t\t\"Comment\": \t\t\t\"Ext0 heater PWM\",\r\n\t\t\"SP[i]\": \t\t\t1,\r\n\t\t\"PWM Pin\": \t\t\t\"2.7\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"PWM\",\r\n\t\t\"Comment\": \t\t\t\"Ext0 part cooling fan PWM on FAN\",\r\n\t\t\"SP[i]\": \t\t\t2,\r\n\t\t\"PWM Max\":\t\t\t128,\r\n\t\t\"PWM Pin\": \t\t\t\"2.4\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"RCServo\",\r\n\t\t\"Comment\": \t\t\t\"RC servo for probe\",\r\n\t\t\"SP[i]\": \t\t\t3,\r\n\t\t\"Servo Pin\": \t\t\"1.23\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Switch\",\r\n\t\t\"Comment\":\t\t\t\"Extruder fan switch on E2\",\r\n\t\t\"Pin\":\t\t\t\t\"2.6\",\r\n\t\t\"Mode\":\t\t\t\t\"On\",\r\n\t\t\"PV[i]\":\t\t\t1,\r\n\t\t\"SP\":\t\t\t\t35.0\r\n\t}\r\n\t]\r\n}\r\n" }, { "path": "Firmware/ConfigSamples/MKS_Sbase/MKS Sbase/config.txt", "content": "{\r\n\t\"Board\": \"MKS SBASE v1.3\",\r\n\t\"Modules\":[\r\n\t{\r\n\t\"Thread\": \"On load\",\r\n\t\"Type\": \"MCP4451\",\r\n\t\t\"Comment\":\t\t\t\"Digipot for joints 0 - 3\",\r\n\t\t\"I2C SDA pin\":\t\t\"0.0\",\r\n\t\t\"I2C SCL pin\":\t\t\"0.1\",\r\n\t\t\"I2C address\":\t\t0,\r\n\t\t\"Max current\":\t\t2.0,\r\n\t\t\"Factor\":\t\t\t113.33,\r\n\t\t\"Current 0\":\t\t0.8,\r\n\t\t\"Current 1\":\t\t0.8,\r\n\t\t\"Current 2\":\t\t0.8,\r\n\t\t\"Current 3\":\t\t0.8\r\n\t},\r\n\t{\r\n\t\"Thread\": \"On load\",\r\n\t\"Type\": \"MCP4451\",\r\n\t\t\"Comment\":\t\t\t\"Digipot for joints 4 - 7\",\r\n\t\t\"I2C SDA pin\":\t\t\"0.0\",\r\n\t\t\"I2C SCL pin\":\t\t\"0.1\",\r\n\t\t\"I2C address\":\t\t2,\r\n\t\t\"Max current\":\t\t2.0,\r\n\t\t\"Factor\":\t\t\t113.33,\r\n\t\t\"Current 0\":\t\t0.8,\r\n\t\t\"Current 1\":\t\t0.8,\r\n\t\t\"Current 2\":\t\t0.8,\r\n\t\t\"Current 3\":\t\t0.8\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"X - Joint 0 step generator\",\r\n\t\t\"Joint Number\":\t\t0,\r\n\t\t\"Step Pin\": \t\t\"2.0\",\r\n\t\t\"Direction Pin\": \t\"0.5\",\r\n\t\t\"Enable Pin\": \t\t\"0.4\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 step generator\",\r\n\t\t\"Joint Number\":\t\t1,\r\n\t\t\"Step Pin\": \t\t\"2.1\",\r\n\t\t\"Direction Pin\": \t\"0.11\",\r\n\t\t\"Enable Pin\": \t\t\"0.10\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 step generator\",\r\n\t\t\"Joint Number\":\t\t2,\r\n\t\t\"Step Pin\": \t\t\"2.2\",\r\n\t\t\"Direction Pin\": \t\"0.20\",\r\n\t\t\"Enable Pin\": \t\t\"0.19\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"E0 - Joint 3 step generator\",\r\n\t\t\"Joint Number\":\t\t3,\r\n\t\t\"Step Pin\": \t\t\"2.3\",\r\n\t\t\"Direction Pin\": \t\"0.22\",\r\n\t\t\"Enable Pin\": \t\t\"0.21\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"Stepgen\",\r\n\t\t\"Comment\":\t\t\t\"E1 - Joint 4 step generator\",\r\n\t\t\"Joint Number\":\t\t4,\r\n\t\t\"Step Pin\": \t\t\"2.8\",\r\n\t\t\"Direction Pin\": \t\"2.13\",\r\n\t\t\"Enable Pin\": \t\t\"4.29\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Blink\",\r\n\t\t\"Pin\":\t\t\t\t\"1.18\",\r\n\t\t\"Frequency\":\t\t2\r\n\t},\t\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"X min\",\r\n\t\t\"Pin\":\t\t\t\t\"1.24\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t0\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"X max\",\r\n\t\t\"Pin\":\t\t\t\t\"1.25\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t1\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Y min\",\r\n\t\t\"Pin\":\t\t\t\t\"1.26\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t2\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Y max\",\r\n\t\t\"Pin\":\t\t\t\t\"1.27\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t3\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Z min\",\r\n\t\t\"Pin\":\t\t\t\t\"1.28\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t4\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Digital Pin\",\r\n\t\t\"Comment\":\t\t\t\"Z max\",\r\n\t\t\"Pin\":\t\t\t\t\"1.29\",\r\n\t\t\"Mode\":\t\t\t\t\"Input\",\r\n\t\t\"Data Bit\":\t\t\t5\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Temperature\",\r\n\t\t\"Comment\": \t\t\t\"Heated Bed tenperature sensor\",\r\n\t\t\"PV[i]\": \t\t\t0,\r\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\r\n\t\t\t\"Thermistor\":\r\n\t\t\t{\r\n\t\t\t\t\"Pin\": \t\t\"0.23\",\r\n\t\t\t\t\"beta\": \t3990,\r\n\t\t\t\t\"r0\": \t\t100000,\r\n\t\t\t\t\"t0\": \t\t25\r\n\t\t\t}\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"PWM\",\r\n\t\t\"Comment\": \t\t\t\"Bed heater PWM\",\r\n\t\t\"SP[i]\": \t\t\t0,\r\n\t\t\"PWM Pin\": \t\t\t\"2.5\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Temperature\",\r\n\t\t\"Comment\": \t\t\t\"Ext 0 temperature sensor\",\r\n\t\t\"PV[i]\": \t\t\t1,\r\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\r\n\t\t\t\"Thermistor\":\r\n\t\t\t{\r\n\t\t\t\t\"Pin\": \t\t\"0.24\",\r\n\t\t\t\t\"beta\": \t3990,\r\n\t\t\t\t\"r0\": \t\t100000,\r\n\t\t\t\t\"t0\": \t\t25\r\n\t\t\t}\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"PWM\",\r\n\t\t\"Comment\": \t\t\t\"Ext0 heater PWM\",\r\n\t\t\"SP[i]\": \t\t\t1,\r\n\t\t\"PWM Pin\": \t\t\t\"2.7\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"PWM\",\r\n\t\t\"Comment\": \t\t\t\"Ext0 part cooling fan PWM on FAN\",\r\n\t\t\"SP[i]\": \t\t\t2,\r\n\t\t\"PWM Max\":\t\t\t128,\r\n\t\t\"PWM Pin\": \t\t\t\"2.4\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Base\",\r\n\t\"Type\": \"RCServo\",\r\n\t\t\"Comment\": \t\t\t\"RC servo for probe\",\r\n\t\t\"SP[i]\": \t\t\t3,\r\n\t\t\"Servo Pin\": \t\t\"1.23\"\r\n\t},\r\n\t{\r\n\t\"Thread\": \"Servo\",\r\n\t\"Type\": \"Switch\",\r\n\t\t\"Comment\":\t\t\t\"Extruder fan switch on E2\",\r\n\t\t\"Pin\":\t\t\t\t\"2.6\",\r\n\t\t\"Mode\":\t\t\t\t\"On\",\r\n\t\t\"PV[i]\":\t\t\t1,\r\n\t\t\"SP\":\t\t\t\t35.0\r\n\t}\r\n\t]\r\n}\r\n" }, { "path": "Firmware/ConfigSamples/TMC2209 Example/SKRv14_TMC2209/config.txt", "content": "{\n\t\"Board\": \"BIGTREETECH SKR v1.4\",\n\t\"Modules\":[\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Reset Pin\",\n\t\t\"Comment\":\t\t\t\"Reset pin\",\n\t\t\"Pin\":\t\t\t\t\"1.31\"\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"X - Joint 0 step generator\",\n\t\t\"Joint Number\":\t\t0,\n\t\t\"Step Pin\": \t\t\"2.2\",\n\t\t\"Direction Pin\": \t\"2.6\",\n\t\t\"Enable Pin\": \t\t\"2.1\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"X - Joint 0 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"1.10\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 step generator\",\n\t\t\"Joint Number\":\t\t1,\n\t\t\"Step Pin\": \t\t\"0.19\",\n\t\t\"Direction Pin\": \t\"0.20\",\n\t\t\"Enable Pin\": \t\t\"2.08\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"1.9\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 step generator\",\n\t\t\"Joint Number\":\t\t2,\n\t\t\"Step Pin\": \t\t\"0.22\",\n\t\t\"Direction Pin\": \t\"2.11\",\n\t\t\"Enable Pin\": \t\t\"0.21\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"1.8\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"E0 - Joint 3 step generator\",\n\t\t\"Joint Number\":\t\t3,\n\t\t\"Step Pin\": \t\t\"2.13\",\n\t\t\"Direction Pin\": \t\"0.11\",\n\t\t\"Enable Pin\": \t\t\"2.12\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"E0 - Joint 3 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"1.4\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"E1 - Joint 4 step generator\",\n\t\t\"Joint Number\":\t\t4,\n\t\t\"Step Pin\": \t\t\"1.15\",\n\t\t\"Direction Pin\": \t\"1.14\",\n\t\t\"Enable Pin\": \t\t\"1.16\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"E1 - Joint 4 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"1.1\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"PWM\",\n\t\t\"Comment\": \t\t\t\"Bed heater PWM\",\n\t\t\"SP[i]\": \t\t\t0,\n\t\t\"PWM Pin\": \t\t\t\"2.5\"\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Temperature\",\n\t\t\"Comment\": \t\t\t\"Bed tenperature sensor\",\n\t\t\"PV[i]\": \t\t\t0,\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\n\t\t\t\"Thermistor\":\n\t\t\t{\n\t\t\t\t\"Pin\": \t\t\"0.25\",\n\t\t\t\t\"beta\": \t3990,\n\t\t\t\t\"r0\": \t\t100000,\n\t\t\t\t\"t0\": \t\t25\n\t\t\t}\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"PWM\",\n\t\t\"Comment\": \t\t\t\"Hotend 0 heater PWM\",\n\t\t\"SP[i]\": \t\t\t1,\n\t\t\"PWM Pin\": \t\t\t\"2.7\"\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Temperature\",\n\t\t\"Comment\": \t\t\t\"Hotend 0 tenperature sensor\",\n\t\t\"PV[i]\": \t\t\t1,\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\n\t\t\t\"Thermistor\":\n\t\t\t{\n\t\t\t\t\"Pin\": \t\t\"0.24\",\n\t\t\t\t\"beta\": \t3990,\n\t\t\t\t\"r0\": \t\t100000,\n\t\t\t\t\"t0\": \t\t25\n\t\t\t}\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"PWM\",\n\t\t\"Comment\": \t\t\t\"Hotend 1 heater PWM\",\n\t\t\"SP[i]\": \t\t\t2,\n\t\t\"PWM Pin\": \t\t\t\"2.4\"\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Temperature\",\n\t\t\"Comment\": \t\t\t\"Hotend 1 tenperature sensor\",\n\t\t\"PV[i]\": \t\t\t2,\n\t\t\"Sensor\": \t\t\t\"Thermistor\",\n\t\t\t\"Thermistor\":\n\t\t\t{\n\t\t\t\t\"Pin\": \t\t\"0.23\",\n\t\t\t\t\"beta\": \t3990,\n\t\t\t\t\"r0\": \t\t100000,\n\t\t\t\t\"t0\": \t\t25\n\t\t\t}\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"X min\",\n\t\t\"Pin\":\t\t\t\t\"1.29\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t0\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Y min\",\n\t\t\"Pin\":\t\t\t\t\"1.28\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t1\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Z min\",\n\t\t\"Pin\":\t\t\t\t\"1.27\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t2\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"E0DET\",\n\t\t\"Pin\":\t\t\t\t\"1.26\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t3\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"E1DET\",\n\t\t\"Pin\":\t\t\t\t\"1.25\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t4\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"PWRDET\",\n\t\t\"Pin\":\t\t\t\t\"1.0\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t5\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Probe\",\n\t\t\"Pin\":\t\t\t\t\"0.10\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t6\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"RCServo\",\n\t\t\"Comment\": \t\t\t\"RC servo for probe\",\n\t\t\"SP[i]\": \t\t\t3,\n\t\t\"Servo Pin\": \t\t\"2.0\"\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Switch\",\n\t\t\"Comment\":\t\t\t\"Extruder fan switch\",\n\t\t\"Pin\":\t\t\t\t\"0.0\",\n\t\t\"Mode\":\t\t\t\t\"On\",\n\t\t\"PV[i]\":\t\t\t1,\n\t\t\"SP\":\t\t\t\t25.5\n\t}\n\t]\n}\n" }, { "path": "Firmware/ConfigSamples/TMC2209 Example/SKRv2_TMC2209/config.txt", "content": "{\n\t\"Board\": \"BIGTREETECH SKR v2\",\n\t\"Modules\":[\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Reset Pin\",\n\t\t\"Comment\":\t\t\t\"Reset pin\",\n\t\t\"Pin\":\t\t\t\t\"PC_4\"\n\t},\n\t\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"Motor Power\",\n\t\t\"Comment\": \"Enable motor power SKR2\",\n\t\t\"Pin\":\t\t\t\t\t \"PC_13\"\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"X - Joint 0 step generator\",\n\t\t\"Joint Number\":\t\t0,\n\t\t\"Step Pin\": \t\t\"PE_2\",\n\t\t\"Direction Pin\": \t\"PE_1\",\n\t\t\"Enable Pin\": \t\t\"PE_3\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"X - Joint 0 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"PE_0\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 step generator\",\n\t\t\"Joint Number\":\t\t1,\n\t\t\"Step Pin\": \t\t\"PD_5\",\n\t\t\"Direction Pin\": \t\"PD_4\",\n\t\t\"Enable Pin\": \t\t\"PD_6\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"Y - Joint 1 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"PD_3\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 step generator\",\n\t\t\"Joint Number\":\t\t2,\n\t\t\"Step Pin\": \t\t\"PA_15\",\n\t\t\"Direction Pin\": \t\"PA_8\",\n\t\t\"Enable Pin\": \t\t\"PD_1\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"Z - Joint 2 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"PD_0\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"E0 - Joint 3 step generator\",\n\t\t\"Joint Number\":\t\t3,\n\t\t\"Step Pin\": \t\t\"PD_15\",\n\t\t\"Direction Pin\": \t\"PD_14\",\n\t\t\"Enable Pin\": \t\t\"PC_7\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"E0 - Joint 3 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"PC_6\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Base\",\n\t\"Type\": \"Stepgen\",\n\t\t\"Comment\":\t\t\t\"E1 - Joint 4 step generator\",\n\t\t\"Joint Number\":\t\t4,\n\t\t\"Step Pin\": \t\t\"PD_11\",\n\t\t\"Direction Pin\": \t\"PD_10\",\n\t\t\"Enable Pin\": \t\t\"PD_13\"\n\t},\n\t{\n\t\"Thread\": \"On load\",\n\t\"Type\": \"TMC2209\",\n\t\t\"Comment\":\t\t\t\"E1 - Joint 4 TMC driver\",\n\t\t\"RX pin\": \t\t\t\"PD_12\",\n\t\t\"RSense\":\t\t\t0.11,\n\t\t\"Current\":\t\t\t800,\n\t\t\"Microsteps\":\t\t16,\n\t\t\"Stealth chop\":\t\t\"on\",\n\t\t\"Stall sensitivity\":0\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"X min\",\n\t\t\"Pin\":\t\t\t\t\"PC_1\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t0\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"X max\",\n\t\t\"Pin\":\t\t\t\t\"PC_2\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t1\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Y min\",\n\t\t\"Pin\":\t\t\t\t\"PC_3\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t2\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Y max\",\n\t\t\"Pin\":\t\t\t\t\"PA_0\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t3\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Z min\",\n\t\t\"Pin\":\t\t\t\t\"PC_0\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t4\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Digital Pin\",\n\t\t\"Comment\":\t\t\t\"Z max\",\n\t\t\"Pin\":\t\t\t\t\"PC_15\",\n\t\t\"Mode\":\t\t\t\t\"Input\",\n\t\t\"Data Bit\":\t\t\t5\n\t},\n\t{\n\t\"Thread\": \"Servo\",\n\t\"Type\": \"Switch\",\n\t\t\"Comment\":\t\t\t\"Extruder fan switch\",\n\t\t\"Pin\":\t\t\t\t\"PB_7\",\n\t\t\"Mode\":\t\t\t\t\"On\",\n\t\t\"PV[i]\":\t\t\t0,\n\t\t\"SP\":\t\t\t\t25.5\n\t}\n\t]\n}\n" }, { "path": "Firmware/FirmwareSource/.gitignore", "content": "/Remora-OS5/mbed-os\n/Remora-OS5/BUILD\n/Remora-OS6/mbed-os\n/Remora-OS6/BUILD" }, { "path": "Firmware/FirmwareSource/Remora-OS5/.gitignore", "content": "/BUILD\n/mbed-os" }, { "path": "Firmware/FirmwareSource/Remora-OS5/.mbed", "content": "ROOT=.\n<<<<<<< refs/remotes/origin/main=undefined\n<<<<<<< Updated upstream=undefined\n=\n>>>>>>> Stashed changes=undefined\n>>>>>>> update=undefined\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/MODDMA.lib", "content": "https://os.mbed.com/users/AjK/code/MODDMA/#97a16bf2ff439853ed01edd65a382207e203c733" }, { "path": "Firmware/FirmwareSource/Remora-OS5/README.md", "content": "Remora OS5 firmware\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/SoftwareSerial/SoftwareSerial.cpp", "content": "\n#include \"SoftwareSerial.h\"\n#include \n\n\n\nSoftwareSerial::SoftwareSerial(std::string tx, std::string rx)\n{\n if (!tx.empty()) TXportAndPin = tx;\n if (!rx.empty()) RXportAndPin = rx;\n halfDuplex = !TXportAndPin.compare(RXportAndPin);\n\n if(halfDuplex)\n {\n this->rxpin = new Pin(RXportAndPin,1);\n this->txpin = this->rxpin;\n setTX();\n }\n else\n {\n this->txpin = new Pin(TXportAndPin,0);\n setTX();\n\n this->rxpin = new Pin(RXportAndPin,1);\n setRX();\n }\n \n qin = 0;\n qout = 0;\n activeTx = false;\n activeRx = false;\n}\n\n\nvoid SoftwareSerial::begin(int baudrate)\n{\n #ifdef FORCE_BAUD_RATE\n baudrate = FORCE_BAUD_RATE; // 19200 fastest stable baud rate\n #endif\n baudRate = baudrate;\n //ticker.attach_us(callback(this, &SoftwareSerial::tickerHandler), 1000000.0 / (baudRate * 3.0));\n}\n\nvoid SoftwareSerial::setSpeed(int baudrate)\n{\n //ticker.detach();\n \n //ticker.attach_us(callback(this, &SoftwareSerial::tickerHandler), 1000000.0 / (baudrate * 3.0));\n this->baudRate = baudrate;\n}\n\nvoid SoftwareSerial::setTX(void)\n{\n // First write, then set output. If we do this the other way around,\n // the pin would be output low for a short while before switching to\n // output hihg. Now, it is input with pullup for a short while, which\n // is fine. With inverse logic, either order is fine.\n\n //this->txpin->set(1); // works for LPC1768 but not STM32\n this->txpin->setAsOutput();\n this->txpin->set(1);\n}\n\nvoid SoftwareSerial::setRX(void)\n{\n\n this->rxpin->setAsInput();\n this->rxpin->pull_up();\n}\n\nvoid SoftwareSerial::setRXTX(bool input)\n{\n if (halfDuplex)\n {\n if (input)\n {\n setRX();\n rxBitCnt = -1;\n rxTickCnt = 2;\n activeRx = true;\n }\n else\n {\n if (activeRx)\n {\n setTX();\n activeRx = false;\n }\n }\n }\n}\n\nbool SoftwareSerial::listen()\n{\n if (rxpin != nullptr)\n {\n setRXTX(true);\n return true;\n }\n return false;\n}\n\nvoid SoftwareSerial::end(void)\n{\n \n}\n\nvoid SoftwareSerial::tickerHandler(void)\n{\n if (activeTx) this->send();\n if (activeRx) this->receive();\n}\n\nvoid SoftwareSerial::send(void)\n{\n if (--txTickCnt <= 0)\n {\n if (txBitCnt++ < TX_BITS) // count out the bits in the txBuffer\n {\n this->txpin->set(txBuffer & 0x01); // set output equal to the LSB in txBuffer\n txBuffer >>= 1; // shift txBuffer to right\n txTickCnt = OVERSAMPLE; // reset the tick counter\n }\n else // transmit finished, stay active or wait for a period before swapping to Rx mode if half duplex mode\n {\n txTickCnt = 1;\n if (outputPending)\n {\n activeTx = false; // output pending allow new byte to be written to txBuffer from write()\n }\n else if (txBitCnt > 10 + OVERSAMPLE*5)\n {\n if (halfDuplex)\n {\n setRXTX(true); // switch to receive mode\n }\n activeTx = false;\n }\n }\n }\n}\n\nvoid SoftwareSerial::receive()\n{\n if (--rxTickCnt <= 0)\n {\n uint8_t inbit = this->rxpin->get(); // read the rx line\n if (rxBitCnt == -1) // waiting for start bit\n {\n if (!inbit)\n {\n // got a start bit\n rxBitCnt = 0;\n rxTickCnt = OVERSAMPLE + 1;\n rxBuffer = 0;\n }\n else\n {\n rxTickCnt = 1;\n }\n }\n else if (rxBitCnt >= RX_BITS) // full byte has been read\n {\n // add stop bit to buffer\n inbuf[qin] = rxBuffer;\n\t\t\tif ( ++qin >= IN_BUF_SIZE )\n {\n\t\t\t // overflow - reset inbuf-index\n\t\t\t\tqin = 0;\n\t\t\t}\n rxTickCnt = 1;\n rxBitCnt = -1; // flag waiting for start bit\n }\n else // read data bits\n {\n rxBuffer >>= 1;\n if (inbit) rxBuffer |= 0x80;\n rxBitCnt++;\n rxTickCnt = OVERSAMPLE;\n }\n }\n}\n\n\nint SoftwareSerial::available()\n{\n return (qout - qin);\n}\n\n\nvoid SoftwareSerial::printStr(char* str)\n{\n int i = 0;\n int len = strlen(str); \n for(i = 0; i= IN_BUF_SIZE ) {qout = 0;}\n \n return d;\n}" }, { "path": "Firmware/FirmwareSource/Remora-OS5/SoftwareSerial/SoftwareSerial.h", "content": "#ifndef SOFTWARESERIAL_H\n#define SOFTWARESERIAL_H\n\n//#include \"LPC17xx.h\"\n#include \"mbed.h\"\n#include \n#include \n#include \"configuration.h\"\n#include \"pin.h\"\n\n\n#define FORCE_BAUD_RATE 19600 //9600\n#define IN_BUF_SIZE 64\n#define TX_BITS 10 // 1 Startbit, 8 Databits, 1 Stopbit = 10 Bits/Frame\n#define RX_BITS 8 // startbit and stopbit parsed internally (see ISR)\n//#define OVERSAMPLE 3\n\n\nclass SoftwareSerial\n{\n private:\n\n //static SoftwareSerial* instance; // there can only be one\n //void (*_rit_isr)(void); // storage for an appended isr function\n //void ritisr(void); // the default (instance) isr\n //static void _ritisr(void); // the actual static isr\n\n std::string TXportAndPin;\n std::string RXportAndPin;\n Pin* txpin;\n Pin* rxpin;\n\n //Ticker ticker;\n \n unsigned char inbuf[IN_BUF_SIZE];\n unsigned char qin;\n unsigned char qout;\n \n int32_t baudRate;\n \n bool activeTx;\n bool activeRx;\n bool halfDuplex;\n bool outputPending;\n\n int32_t rxTickCnt;\n int32_t txTickCnt;\n int32_t txBitCnt;\n int32_t rxBitCnt;\n int32_t txBuffer;\n int32_t rxBuffer;\n\n public:\n\n SoftwareSerial(std::string, std::string);\n\n void begin(int);\n void setSpeed(int);\n void end(void);\n void setTX(void);\n void setRX(void);\n void setRXTX(bool);\n void send(void);\n void receive(void);\n void write(int);\n int16_t read(void);\n bool listen(void);\n void tickerHandler(void);\n\n void enableTx(void);\n void enableRx(void);\n void idle() {__NOP();}\n \n\n int available();\n\n void flush_input_buffer();\n void printStr(char*);\n};\n\n\n#endif" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_OCTOPUS_429/PeripheralNames.h", "content": "/* mbed Microcontroller Library\r\n *******************************************************************************\r\n * Copyright (c) 2015, STMicroelectronics\r\n * All rights reserved.\r\n *\r\n * Redistribution and use in source and binary forms, with or without\r\n * modification, are permitted provided that the following conditions are met:\r\n *\r\n * 1. Redistributions of source code must retain the above copyright notice,\r\n * this list of conditions and the following disclaimer.\r\n * 2. Redistributions in binary form must reproduce the above copyright notice,\r\n * this list of conditions and the following disclaimer in the documentation\r\n * and/or other materials provided with the distribution.\r\n * 3. Neither the name of STMicroelectronics nor the names of its contributors\r\n * may be used to endorse or promote products derived from this software\r\n * without specific prior written permission.\r\n *\r\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n *******************************************************************************\r\n */\r\n#ifndef MBED_PERIPHERALNAMES_H\r\n#define MBED_PERIPHERALNAMES_H\r\n\r\n#include \"cmsis.h\"\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\ntypedef enum {\r\n ADC_1 = (int)ADC1_BASE,\r\n ADC_2 = (int)ADC2_BASE,\r\n ADC_3 = (int)ADC3_BASE\r\n} ADCName;\r\n\r\ntypedef enum {\r\n DAC_1 = (int)DAC_BASE\r\n} DACName;\r\n\r\ntypedef enum {\r\n UART_1 = (int)USART1_BASE,\r\n UART_2 = (int)USART2_BASE,\r\n UART_3 = (int)USART3_BASE,\r\n UART_4 = (int)UART4_BASE,\r\n UART_5 = (int)UART5_BASE,\r\n UART_6 = (int)USART6_BASE,\r\n UART_7 = (int)UART7_BASE,\r\n UART_8 = (int)UART8_BASE\r\n} UARTName;\r\n\r\n#define DEVICE_SPI_COUNT 6\r\ntypedef enum {\r\n SPI_1 = (int)SPI1_BASE,\r\n SPI_2 = (int)SPI2_BASE,\r\n SPI_3 = (int)SPI3_BASE,\r\n SPI_4 = (int)SPI4_BASE,\r\n SPI_5 = (int)SPI5_BASE,\r\n SPI_6 = (int)SPI6_BASE\r\n} SPIName;\r\n\r\ntypedef enum {\r\n I2C_1 = (int)I2C1_BASE,\r\n I2C_2 = (int)I2C2_BASE,\r\n I2C_3 = (int)I2C3_BASE\r\n} I2CName;\r\n\r\ntypedef enum {\r\n PWM_1 = (int)TIM1_BASE,\r\n PWM_2 = (int)TIM2_BASE,\r\n PWM_3 = (int)TIM3_BASE,\r\n PWM_4 = (int)TIM4_BASE,\r\n PWM_5 = (int)TIM5_BASE,\r\n PWM_8 = (int)TIM8_BASE,\r\n PWM_9 = (int)TIM9_BASE,\r\n PWM_10 = (int)TIM10_BASE,\r\n PWM_11 = (int)TIM11_BASE,\r\n PWM_12 = (int)TIM12_BASE,\r\n PWM_13 = (int)TIM13_BASE,\r\n PWM_14 = (int)TIM14_BASE\r\n} PWMName;\r\n\r\ntypedef enum {\r\n CAN_1 = (int)CAN1_BASE,\r\n CAN_2 = (int)CAN2_BASE\r\n} CANName;\r\n\r\ntypedef enum {\r\n USB_FS = (int)USB_OTG_FS_PERIPH_BASE,\r\n USB_HS = (int)USB_OTG_HS_PERIPH_BASE\r\n} USBName;\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif\r\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_OCTOPUS_429/PeripheralPins.c", "content": "/* mbed Microcontroller Library\r\n *******************************************************************************\r\n * Copyright (c) 2018, STMicroelectronics\r\n * All rights reserved.\r\n *\r\n * Redistribution and use in source and binary forms, with or without\r\n * modification, are permitted provided that the following conditions are met:\r\n *\r\n * 1. Redistributions of source code must retain the above copyright notice,\r\n * this list of conditions and the following disclaimer.\r\n * 2. Redistributions in binary form must reproduce the above copyright notice,\r\n * this list of conditions and the following disclaimer in the documentation\r\n * and/or other materials provided with the distribution.\r\n * 3. Neither the name of STMicroelectronics nor the names of its contributors\r\n * may be used to endorse or promote products derived from this software\r\n * without specific prior written permission.\r\n *\r\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n *******************************************************************************\r\n */\r\n\r\n#include \"PeripheralPins.h\"\r\n#include \"mbed_toolchain.h\"\r\n\r\n//==============================================================================\r\n// Notes\r\n//\r\n// - The pins mentioned Px_y_ALTz are alternative possibilities which use other\r\n// HW peripheral instances. You can use them the same way as any other \"normal\"\r\n// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board\r\n// pinout image on mbed.org.\r\n//\r\n// - The pins which are connected to other components present on the board have\r\n// the comment \"Connected to xxx\". The pin function may not work properly in this\r\n// case. These pins may not be displayed on the board pinout image on mbed.org.\r\n// Please read the board reference manual and schematic for more information.\r\n//\r\n// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented\r\n// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.\r\n//\r\n//==============================================================================\r\n\r\n\r\n//*** ADC ***\r\n\r\nMBED_WEAK const PinMap PinMap_ADC[] = {\r\n {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 // Connected to B1 [Blue PushButton]\r\n {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0 // Connected to B1 [Blue PushButton]\r\n {PA_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0 // Connected to B1 [Blue PushButton]\r\n {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 // Connected to MEMS_INT1 [L3GD20_INT1]\r\n {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 // Connected to MEMS_INT1 [L3GD20_INT1]\r\n {PA_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 // Connected to MEMS_INT1 [L3GD20_INT1]\r\n {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to MEMS_INT2 [L3GD20_INT2]\r\n {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 // Connected to MEMS_INT2 [L3GD20_INT2]\r\n {PA_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 // Connected to MEMS_INT2 [L3GD20_INT2]\r\n {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to B5\r\n {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 // Connected to B5\r\n {PA_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 // Connected to B5\r\n {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // Connected to VSYNC\r\n {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 // Connected to VSYNC\r\n {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5\r\n {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5\r\n {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 // Connected to G2\r\n {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 // Connected to G2\r\n {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // Connected to ACP_RST\r\n {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 // Connected to ACP_RST\r\n {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // Connected to R3\r\n {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 // Connected to R3\r\n {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 // Connected to R6\r\n {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 // Connected to R6\r\n {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // Connected to SDNWE\r\n {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 // Connected to SDNWE\r\n {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10 // Connected to SDNWE\r\n {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // Connected to NCS_MEMS_SPI [L3GD20_CS_I2C/SPI]\r\n {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 // Connected to NCS_MEMS_SPI [L3GD20_CS_I2C/SPI]\r\n {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11 // Connected to NCS_MEMS_SPI [L3GD20_CS_I2C/SPI]\r\n {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 // Connected to CSX [LCD-RGB_CSX]\r\n {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 // Connected to CSX [LCD-RGB_CSX]\r\n {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12 // Connected to CSX [LCD-RGB_CSX]\r\n {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13\r\n {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13\r\n {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13\r\n {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 // Connected to OTG_FS_PSO [OTG_FS_PowerSwitchOn]\r\n {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 // Connected to OTG_FS_PSO [OTG_FS_PowerSwitchOn]\r\n {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 // Connected to OTG_FS_OC [OTG_FS_OverCurrent]\r\n {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 // Connected to OTG_FS_OC [OTG_FS_OverCurrent]\r\n {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9 // Connected to A3\r\n {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14 // Connected to A4\r\n {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15 // Connected to A5\r\n {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4\r\n {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5 // Connected to SPI5_SCK [L3GD20_SCL/SPC]\r\n {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 // Connected to SPI5_MISO [L3GD20_SDO]\r\n {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 // Connected to SPI5_MOSI [L3GD20_SDA/SDI/SDO]\r\n {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 // Connected to ENABLE [LCD-RGB_ENABLE]\r\n {NC, NC, 0}\r\n};\r\n\r\nMBED_WEAK const PinMap PinMap_ADC_Internal[] = {\r\n {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},\r\n {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},\r\n {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},\r\n {NC, NC, 0}\r\n};\r\n\r\n//*** DAC ***\r\n\r\nMBED_WEAK const PinMap PinMap_DAC[] = {\r\n {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 // Connected to VSYNC\r\n {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2\r\n {NC, NC, 0}\r\n};\r\n\r\n//*** I2C ***\r\n\r\nMBED_WEAK const PinMap PinMap_I2C_SDA[] = {\r\n {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},\r\n {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to B7\r\n {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to G5\r\n {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to I2C3_SDA [ACP/RF_SDA]\r\n {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to A0\r\n {NC, NC, 0}\r\n};\r\n\r\nMBED_WEAK const PinMap PinMap_I2C_SCL[] = {\r\n {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to I2C3_SCL [ACP/RF_SCL]\r\n {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to SDNE1 [SDRAM_CS]\r\n {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to B6\r\n {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to G4\r\n {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to A1\r\n {NC, NC, 0}\r\n};\r\n\r\n//*** PWM ***\r\n\r\n// TIM5 cannot be used because already used by the us_ticker\r\nMBED_WEAK const PinMap PinMap_PWM[] = {\r\n {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to B1 [Blue PushButton]\r\n// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to B1 [Blue PushButton]\r\n {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to MEMS_INT1 [L3GD20_INT1]\r\n// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to MEMS_INT1 [L3GD20_INT1]\r\n {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to MEMS_INT2 [L3GD20_INT2]\r\n// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to MEMS_INT2 [L3GD20_INT2]\r\n {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 // Connected to MEMS_INT2 [L3GD20_INT2]\r\n {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to B5\r\n// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to B5\r\n {PA_3_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 // Connected to B5\r\n {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1\r\n {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N\r\n {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to G2\r\n {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 // Connected to G2\r\n {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to ACP_RST\r\n {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to ACP_RST\r\n {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to ACP_RST\r\n {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to ACP_RST\r\n {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to I2C3_SCL [ACP/RF_SCL]\r\n// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to STDIO_UART_TX\r\n// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to STDIO_UART_RX\r\n {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to R4\r\n {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to TP_INT1 [Touch Panel]\r\n {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to R3\r\n {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to R3\r\n {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to R3\r\n {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to R6\r\n {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to R6\r\n {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to R6\r\n {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2\r\n {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1\r\n {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to SDCKE1\r\n {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to SDNE1 [SDRAM_CS]\r\n {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2\r\n {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to B6\r\n {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 // Connected to B6\r\n {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to B7\r\n {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 // Connected to B7\r\n {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to G4\r\n {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to G5\r\n {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to VBUS_HS\r\n {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to OTG_HS_DM\r\n {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to OTG_HS_DM\r\n {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 // Connected to OTG_HS_DM\r\n {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to OTG_HS_DP\r\n {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N // Connected to OTG_HS_DP\r\n {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 // Connected to OTG_HS_DP\r\n {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to HSYNC\r\n {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 // Connected to HSYNC\r\n {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to G6\r\n {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // Connected to G6\r\n {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3\r\n {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3\r\n {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 // Connected to I2C3_SDA [ACP/RF_SDA]\r\n {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 // Connected to I2C3_SDA [ACP/RF_SDA]\r\n {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to RDX [LDC-RGB_RDX]\r\n {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to WRX_DCX [LCD-RGB_WRX_DCX]\r\n {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to D0\r\n {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to D1\r\n {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1\r\n {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2\r\n {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to D5\r\n {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to D6\r\n {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to D7\r\n {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to D8\r\n {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N // Connected to D9\r\n {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to D10\r\n {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to D11\r\n {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1\r\n {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 // Connected to SPI5_SCK [L3GD20_SCL/SPC]\r\n {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 // Connected to SPI5_MISO [L3GD20_SDO]\r\n {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to SPI5_MOSI [L3GD20_SDA/SDI/SDO]\r\n {NC, NC, 0}\r\n};\r\n\r\n//*** SERIAL ***\r\n\r\nMBED_WEAK const PinMap PinMap_UART_TX[] = {\r\n {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to B1 [Blue PushButton]\r\n {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to MEMS_INT2 [L3GD20_INT2]\r\n {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX\r\n {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to SDNE1 [SDRAM_CS]\r\n {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to G4\r\n {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to HSYNC\r\n {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to R2\r\n {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to R2\r\n {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},\r\n {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},\r\n {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to D13\r\n {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to NBL1 [SDRAM_UDQM]\r\n {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to D5\r\n {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to SPI5_SCK [L3GD20_SCL/SPC]\r\n {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to LD4 [Red Led]\r\n {NC, NC, 0}\r\n};\r\n\r\nMBED_WEAK const PinMap PinMap_UART_RX[] = {\r\n {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to MEMS_INT1 [L3GD20_INT1]\r\n {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to B5\r\n {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX\r\n {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},\r\n {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to G5\r\n {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to G6\r\n {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},\r\n {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},\r\n {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},\r\n {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to B2\r\n {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to D14\r\n {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to NBL0 [SDRAM_LDQM]\r\n {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)}, // Connected to D4\r\n {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART7)},\r\n {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},\r\n {NC, NC, 0}\r\n};\r\n\r\nMBED_WEAK const PinMap PinMap_UART_RTS[] = {\r\n {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to MEMS_INT1 [L3GD20_INT1]\r\n {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to R5\r\n {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to OTG_HS_DM\r\n {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},\r\n {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to RDX [LDC-RGB_RDX]\r\n {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to SDCLK\r\n {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to B4\r\n {NC, NC, 0}\r\n};\r\n\r\nMBED_WEAK const PinMap PinMap_UART_CTS[] = {\r\n {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to B1 [Blue PushButton]\r\n {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to R4\r\n {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to VBUS_HS\r\n {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to G7\r\n {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to TE [LCD-RGB_TE]\r\n {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to LD3 [Green Led]\r\n {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to SDNCAS\r\n {NC, NC, 0}\r\n};\r\n\r\n//*** SPI ***\r\n\r\nMBED_WEAK const PinMap PinMap_SPI_MOSI[] = {\r\n {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to ACP_RST\r\n {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SDCKE1\r\n {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SDCKE1\r\n {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to OTG_HS_DP\r\n {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},\r\n {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},\r\n {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to B2\r\n {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},\r\n {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to D11\r\n {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to SPI5_MOSI [L3GD20_SDA/SDI/SDO]\r\n {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to SDNRAS\r\n {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to LD4 [Red Led]\r\n {NC, NC, 0}\r\n};\r\n\r\nMBED_WEAK const PinMap PinMap_SPI_MISO[] = {\r\n {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to G2\r\n {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},\r\n {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},\r\n {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to OTG_HS_DM\r\n {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to CSX [LCD-RGB_CSX]\r\n {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},\r\n {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},\r\n {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to D10\r\n {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to SPI5_MISO [L3GD20_SDO]\r\n {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to B4\r\n {NC, NC, 0}\r\n};\r\n\r\nMBED_WEAK const PinMap PinMap_SPI_SCLK[] = {\r\n {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},\r\n {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},\r\n {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},\r\n {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to G4\r\n {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to VBUS_HS\r\n {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to R2\r\n {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to G7\r\n {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},\r\n {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to D9\r\n {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, // Connected to SPI5_SCK [L3GD20_SCL/SPC]\r\n {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to LD3 [Green Led]\r\n {NC, NC, 0}\r\n};\r\n\r\nMBED_WEAK const PinMap PinMap_SPI_SSEL[] = {\r\n {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to VSYNC\r\n {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to VSYNC\r\n {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to TP_INT1 [Touch Panel]\r\n {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to TP_INT1 [Touch Panel]\r\n {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to B7\r\n {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to OTG_HS_ID\r\n {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},\r\n {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, // Connected to D8\r\n {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)},\r\n {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, // Connected to SDCLK\r\n {NC, NC, 0}\r\n};\r\n\r\n//*** CAN ***\r\n\r\nMBED_WEAK const PinMap PinMap_CAN_RD[] = {\r\n {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to R4\r\n {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to SDCKE1\r\n {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to B6\r\n {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to OTG_HS_ID\r\n {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to D2\r\n {NC, NC, 0}\r\n};\r\n\r\nMBED_WEAK const PinMap PinMap_CAN_TD[] = {\r\n {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to R5\r\n {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to SDNE1 [SDRAM_CS]\r\n {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to B7\r\n {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to VBUS_HS\r\n {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to D3\r\n {NC, NC, 0}\r\n};\r\n\r\n//*** USBDEVICE ***\r\n\r\nMBED_WEAK const PinMap PinMap_USB_FS[] = {\r\n// {PA_8, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF // Connected to I2C3_SCL [ACP/RF_SCL]\r\n// {PA_9, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS // Connected to STDIO_UART_TX\r\n// {PA_10, USB_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_ID // Connected to STDIO_UART_RX\r\n {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DM // Connected to R4\r\n {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DP // Connected to R5\r\n {NC, NC, 0}\r\n};\r\n\r\n//*** USBDEVICE ***\r\n\r\nMBED_WEAK const PinMap PinMap_USB_HS[] = {\r\n#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_HS_IN_FS)\r\n// {PA_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_SOF // Connected to VSYNC\r\n {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_ID // Connected to OTG_HS_ID\r\n {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS // Connected to VBUS_HS\r\n {PB_14, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DM // Connected to OTG_HS_DM\r\n {PB_15, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DP // Connected to OTG_HS_DP\r\n#else /* MBED_CONF_TARGET_USB_SPEED */\r\n {PA_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D0 // Connected to B5\r\n {PA_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_CK\r\n {PB_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D1 // Connected to R3\r\n {PB_1, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D2 // Connected to R6\r\n {PB_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D7 // Connected to SDCKE1\r\n {PB_10, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D3 // Connected to G4\r\n {PB_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D4 // Connected to G5\r\n {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D5 // Connected to OTG_HS_ID\r\n {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D6 // Connected to VBUS_HS\r\n {PC_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_STP // Connected to SDNWE\r\n {PC_2, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_DIR // Connected to CSX [LCD-RGB_CSX]\r\n {PC_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_NXT\r\n#endif /* MBED_CONF_TARGET_USB_SPEED */\r\n {NC, NC, 0}\r\n};\r\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_OCTOPUS_429/PinNames.h", "content": "/* mbed Microcontroller Library\r\n *******************************************************************************\r\n * Copyright (c) 2018, STMicroelectronics\r\n * All rights reserved.\r\n *\r\n * Redistribution and use in source and binary forms, with or without\r\n * modification, are permitted provided that the following conditions are met:\r\n *\r\n * 1. Redistributions of source code must retain the above copyright notice,\r\n * this list of conditions and the following disclaimer.\r\n * 2. Redistributions in binary form must reproduce the above copyright notice,\r\n * this list of conditions and the following disclaimer in the documentation\r\n * and/or other materials provided with the distribution.\r\n * 3. Neither the name of STMicroelectronics nor the names of its contributors\r\n * may be used to endorse or promote products derived from this software\r\n * without specific prior written permission.\r\n *\r\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\r\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\r\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\r\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\r\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\r\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\r\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r\n *******************************************************************************\r\n */\r\n\r\n#ifndef MBED_PINNAMES_H\r\n#define MBED_PINNAMES_H\r\n\r\n#include \"cmsis.h\"\r\n#include \"PinNamesTypes.h\"\r\n\r\n#ifdef __cplusplus\r\nextern \"C\" {\r\n#endif\r\n\r\ntypedef enum {\r\n ALT0 = 0x100,\r\n ALT1 = 0x200,\r\n ALT2 = 0x300,\r\n ALT3 = 0x400\r\n} ALTx;\r\n\r\ntypedef enum {\r\n PA_0 = 0x00,\r\n PA_0_ALT0 = PA_0 | ALT0,\r\n PA_0_ALT1 = PA_0 | ALT1,\r\n PA_1 = 0x01,\r\n PA_1_ALT0 = PA_1 | ALT0,\r\n PA_1_ALT1 = PA_1 | ALT1,\r\n PA_2 = 0x02,\r\n PA_2_ALT0 = PA_2 | ALT0,\r\n PA_2_ALT1 = PA_2 | ALT1,\r\n PA_3 = 0x03,\r\n PA_3_ALT0 = PA_3 | ALT0,\r\n PA_3_ALT1 = PA_3 | ALT1,\r\n PA_4 = 0x04,\r\n PA_4_ALT0 = PA_4 | ALT0,\r\n PA_5 = 0x05,\r\n PA_5_ALT0 = PA_5 | ALT0,\r\n PA_5_ALT1 = PA_5 | ALT1,\r\n PA_6 = 0x06,\r\n PA_6_ALT0 = PA_6 | ALT0,\r\n PA_7 = 0x07,\r\n PA_7_ALT0 = PA_7 | ALT0,\r\n PA_7_ALT1 = PA_7 | ALT1,\r\n PA_7_ALT2 = PA_7 | ALT2,\r\n PA_8 = 0x08,\r\n PA_9 = 0x09,\r\n PA_10 = 0x0A,\r\n PA_11 = 0x0B,\r\n PA_12 = 0x0C,\r\n PA_13 = 0x0D,\r\n PA_14 = 0x0E,\r\n PA_15 = 0x0F,\r\n PA_15_ALT0 = PA_15 | ALT0,\r\n\r\n PB_0 = 0x10,\r\n PB_0_ALT0 = PB_0 | ALT0,\r\n PB_0_ALT1 = PB_0 | ALT1,\r\n PB_1 = 0x11,\r\n PB_1_ALT0 = PB_1 | ALT0,\r\n PB_1_ALT1 = PB_1 | ALT1,\r\n PB_2 = 0x12,\r\n PB_3 = 0x13,\r\n PB_3_ALT0 = PB_3 | ALT0,\r\n PB_4 = 0x14,\r\n PB_4_ALT0 = PB_4 | ALT0,\r\n PB_5 = 0x15,\r\n PB_5_ALT0 = PB_5 | ALT0,\r\n PB_6 = 0x16,\r\n PB_7 = 0x17,\r\n PB_8 = 0x18,\r\n PB_8_ALT0 = PB_8 | ALT0,\r\n PB_9 = 0x19,\r\n PB_9_ALT0 = PB_9 | ALT0,\r\n PB_10 = 0x1A,\r\n PB_11 = 0x1B,\r\n PB_12 = 0x1C,\r\n PB_13 = 0x1D,\r\n PB_14 = 0x1E,\r\n PB_14_ALT0 = PB_14 | ALT0,\r\n PB_14_ALT1 = PB_14 | ALT1,\r\n PB_15 = 0x1F,\r\n PB_15_ALT0 = PB_15 | ALT0,\r\n PB_15_ALT1 = PB_15 | ALT1,\r\n\r\n PC_0 = 0x20,\r\n PC_0_ALT0 = PC_0 | ALT0,\r\n PC_0_ALT1 = PC_0 | ALT1,\r\n PC_1 = 0x21,\r\n PC_1_ALT0 = PC_1 | ALT0,\r\n PC_1_ALT1 = PC_1 | ALT1,\r\n PC_2 = 0x22,\r\n PC_2_ALT0 = PC_2 | ALT0,\r\n PC_2_ALT1 = PC_2 | ALT1,\r\n PC_3 = 0x23,\r\n PC_3_ALT0 = PC_3 | ALT0,\r\n PC_3_ALT1 = PC_3 | ALT1,\r\n PC_4 = 0x24,\r\n PC_4_ALT0 = PC_4 | ALT0,\r\n PC_5 = 0x25,\r\n PC_5_ALT0 = PC_5 | ALT0,\r\n PC_6 = 0x26,\r\n PC_6_ALT0 = PC_6 | ALT0,\r\n PC_7 = 0x27,\r\n PC_7_ALT0 = PC_7 | ALT0,\r\n PC_8 = 0x28,\r\n PC_8_ALT0 = PC_8 | ALT0,\r\n PC_9 = 0x29,\r\n PC_9_ALT0 = PC_9 | ALT0,\r\n PC_10 = 0x2A,\r\n PC_10_ALT0 = PC_10 | ALT0,\r\n PC_11 = 0x2B,\r\n PC_11_ALT0 = PC_11 | ALT0,\r\n PC_12 = 0x2C,\r\n PC_13 = 0x2D,\r\n PC_14 = 0x2E,\r\n PC_15 = 0x2F,\r\n\r\n PD_0 = 0x30,\r\n PD_1 = 0x31,\r\n PD_2 = 0x32,\r\n PD_3 = 0x33,\r\n PD_4 = 0x34,\r\n PD_5 = 0x35,\r\n PD_6 = 0x36,\r\n PD_7 = 0x37,\r\n PD_8 = 0x38,\r\n PD_9 = 0x39,\r\n PD_10 = 0x3A,\r\n PD_11 = 0x3B,\r\n PD_12 = 0x3C,\r\n PD_13 = 0x3D,\r\n PD_14 = 0x3E,\r\n PD_15 = 0x3F,\r\n\r\n PE_0 = 0x40,\r\n PE_1 = 0x41,\r\n PE_2 = 0x42,\r\n PE_3 = 0x43,\r\n PE_4 = 0x44,\r\n PE_5 = 0x45,\r\n PE_6 = 0x46,\r\n PE_7 = 0x47,\r\n PE_8 = 0x48,\r\n PE_9 = 0x49,\r\n PE_10 = 0x4A,\r\n PE_11 = 0x4B,\r\n PE_12 = 0x4C,\r\n PE_13 = 0x4D,\r\n PE_14 = 0x4E,\r\n PE_15 = 0x4F,\r\n\r\n PF_0 = 0x50,\r\n PF_1 = 0x51,\r\n PF_2 = 0x52,\r\n PF_3 = 0x53,\r\n PF_4 = 0x54,\r\n PF_5 = 0x55,\r\n PF_6 = 0x56,\r\n PF_7 = 0x57,\r\n PF_8 = 0x58,\r\n PF_9 = 0x59,\r\n PF_10 = 0x5A,\r\n PF_11 = 0x5B,\r\n PF_12 = 0x5C,\r\n PF_13 = 0x5D,\r\n PF_14 = 0x5E,\r\n PF_15 = 0x5F,\r\n\r\n PG_0 = 0x60,\r\n PG_1 = 0x61,\r\n PG_2 = 0x62,\r\n PG_3 = 0x63,\r\n PG_4 = 0x64,\r\n PG_5 = 0x65,\r\n PG_6 = 0x66,\r\n PG_7 = 0x67,\r\n PG_8 = 0x68,\r\n PG_9 = 0x69,\r\n PG_10 = 0x6A,\r\n PG_11 = 0x6B,\r\n PG_12 = 0x6C,\r\n PG_13 = 0x6D,\r\n PG_14 = 0x6E,\r\n PG_15 = 0x6F,\r\n\r\n PH_0 = 0x70,\r\n PH_1 = 0x71,\r\n\r\n // ADC internal channels\r\n ADC_TEMP = 0xF0,\r\n ADC_VREF = 0xF1,\r\n ADC_VBAT = 0xF2,\r\n\r\n // STDIO for console print\r\n#ifdef MBED_CONF_TARGET_STDIO_UART_TX\r\n STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,\r\n#else\r\n STDIO_UART_TX = PA_9,\r\n#endif\r\n#ifdef MBED_CONF_TARGET_STDIO_UART_RX\r\n STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,\r\n#else\r\n STDIO_UART_RX = PA_10,\r\n#endif\r\n\r\n // Generic signals namings\r\n LED1 = PG_13, // Corresponds to LD3 on MB1075B\r\n LED2 = PG_14, // Corresponds to LD4 on MB1075B\r\n LED3 = PG_13,\r\n LED4 = PG_14,\r\n LED_RED = LED2,\r\n USER_BUTTON = PA_0,\r\n // Standardized button names\r\n BUTTON1 = USER_BUTTON,\r\n SERIAL_TX = STDIO_UART_TX,\r\n SERIAL_RX = STDIO_UART_RX,\r\n USBTX = STDIO_UART_TX,\r\n USBRX = STDIO_UART_RX,\r\n SPI_MOSI = PA_7,\r\n SPI_MISO = PA_6,\r\n SPI_SCK = PA_5,\r\n SPI_CS = PB_6,\r\n\r\n /**** USB FS pins ****/\r\n USB_OTG_FS_DM = PA_11,\r\n USB_OTG_FS_DP = PA_12,\r\n USB_OTG_FS_ID = PA_10,\r\n USB_OTG_FS_SOF = PA_8,\r\n USB_OTG_FS_VBUS = PA_9,\r\n\r\n /**** USB HS pins ****/\r\n USB_OTG_HS_DM = PB_14,\r\n USB_OTG_HS_DP = PB_15,\r\n USB_OTG_HS_ID = PB_12,\r\n USB_OTG_HS_SOF = PA_4,\r\n USB_OTG_HS_ULPI_CK = PA_5,\r\n USB_OTG_HS_ULPI_D0 = PA_3,\r\n USB_OTG_HS_ULPI_D1 = PB_0,\r\n USB_OTG_HS_ULPI_D2 = PB_1,\r\n USB_OTG_HS_ULPI_D3 = PB_10,\r\n USB_OTG_HS_ULPI_D4 = PB_11,\r\n USB_OTG_HS_ULPI_D5 = PB_12,\r\n USB_OTG_HS_ULPI_D6 = PB_13,\r\n USB_OTG_HS_ULPI_D7 = PB_5,\r\n USB_OTG_HS_ULPI_DIR = PC_2,\r\n USB_OTG_HS_ULPI_NXT = PC_3,\r\n USB_OTG_HS_ULPI_STP = PC_0,\r\n USB_OTG_HS_VBUS = PB_13,\r\n\r\n /**** ETHERNET pins ****/\r\n ETH_COL = PA_3,\r\n ETH_CRS = PA_0,\r\n ETH_CRS_DV = PA_7,\r\n ETH_MDC = PC_1,\r\n ETH_MDIO = PA_2,\r\n ETH_PPS_OUT = PG_8,\r\n ETH_PPS_OUT_ALT0 = PB_5,\r\n ETH_REF_CLK = PA_1,\r\n ETH_RXD0 = PC_4,\r\n ETH_RXD1 = PC_5,\r\n ETH_RXD2 = PB_0,\r\n ETH_RXD3 = PB_1,\r\n ETH_RX_CLK = PA_1,\r\n ETH_RX_DV = PA_7,\r\n ETH_RX_ER = PB_10,\r\n ETH_TXD0 = PB_12,\r\n ETH_TXD0_ALT0 = PG_13,\r\n ETH_TXD1 = PB_13,\r\n ETH_TXD1_ALT0 = PG_14,\r\n ETH_TXD2 = PC_2,\r\n ETH_TXD3 = PE_2,\r\n ETH_TXD3_ALT0 = PB_8,\r\n ETH_TX_CLK = PC_3,\r\n ETH_TX_EN = PB_11,\r\n ETH_TX_EN_ALT0 = PG_11,\r\n\r\n /**** OSCILLATOR pins ****/\r\n RCC_OSC32_IN = PC_14,\r\n RCC_OSC32_OUT = PC_15,\r\n RCC_OSC_IN = PH_0,\r\n RCC_OSC_OUT = PH_1,\r\n\r\n /**** DEBUG pins ****/\r\n SYS_JTCK_SWCLK = PA_14,\r\n SYS_JTDI = PA_15,\r\n SYS_JTDO_SWO = PB_3,\r\n SYS_JTMS_SWDIO = PA_13,\r\n SYS_JTRST = PB_4,\r\n SYS_TRACECLK = PE_2,\r\n SYS_TRACED0 = PE_3,\r\n SYS_TRACED1 = PE_4,\r\n SYS_TRACED2 = PE_5,\r\n SYS_TRACED3 = PE_6,\r\n SYS_WKUP = PA_0,\r\n\r\n // Not connected\r\n NC = (int)0xFFFFFFFF\r\n} PinName;\r\n\r\n#ifdef __cplusplus\r\n}\r\n#endif\r\n\r\n#endif\r\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_OCTOPUS_429/system_clock.c", "content": "/* mbed Microcontroller Library\r\n* Copyright (c) 2006-2017 ARM Limited\r\n*\r\n* Licensed under the Apache License, Version 2.0 (the \"License\");\r\n* you may not use this file except in compliance with the License.\r\n* You may obtain a copy of the License at\r\n*\r\n* http://www.apache.org/licenses/LICENSE-2.0\r\n*\r\n* Unless required by applicable law or agreed to in writing, software\r\n* distributed under the License is distributed on an \"AS IS\" BASIS,\r\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r\n* See the License for the specific language governing permissions and\r\n* limitations under the License.\r\n*/\r\n\r\n/**\r\n * This file configures the system clock as follows:\r\n *-----------------------------------------------------------------------------------\r\n * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) |\r\n * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) | DEVICE_USBDEVICE=1\r\n * | 3- USE_PLL_HSI (internal 16 MHz clock) |\r\n *-----------------------------------------------------------------------------------\r\n * SYSCLK(MHz) | 180 | 168\r\n * AHBCLK (MHz) | 180 | 168\r\n * APB1CLK (MHz) | 45 | 42\r\n * APB2CLK (MHz) | 90 | 84\r\n * USB capable (48 MHz) | NO | YES (HSI calibration needed)\r\n *-----------------------------------------------------------------------------------\r\n**/\r\n\r\n#include \"stm32f4xx.h\"\r\n//#include \"nvic_addr.h\" original\r\n#include \"mbed_error.h\"\r\n\r\n/*!< COPIED FROM SKR2 Uncomment the following line if you need to relocate your vector Table in\r\n Internal SRAM. */\r\n/* #define VECT_TAB_SRAM */\r\n#define VECT_TAB_OFFSET 0x8000 /*!< Vector Table base offset field.\r\n This value must be a multiple of 0x200. */\r\n\r\n\r\n// clock source is selected with CLOCK_SOURCE in json config\r\n#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)\r\n#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)\r\n#define USE_PLL_HSI 0x2 // Use HSI internal clock\r\n\r\n\r\n#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )\r\nuint8_t SetSysClock_PLL_HSE(uint8_t bypass);\r\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */\r\n\r\n#if ((CLOCK_SOURCE) & USE_PLL_HSI)\r\nuint8_t SetSysClock_PLL_HSI(void);\r\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */\r\n\r\n\r\n/**\r\n * @brief Setup the microcontroller system\r\n * Initialize the FPU setting, vector table location and External memory\r\n * configuration.\r\n * @param None\r\n * @retval None\r\n */\r\nvoid SystemInit(void)\r\n{\r\n /* FPU settings ------------------------------------------------------------*/\r\n#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r\n SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */\r\n#endif\r\n /* Reset the RCC clock configuration to the default reset state ------------*/\r\n /* Set HSION bit */\r\n RCC->CR |= (uint32_t)0x00000001;\r\n\r\n /* Reset CFGR register */\r\n RCC->CFGR = 0x00000000;\r\n\r\n /* Reset HSEON, CSSON and PLLON bits */\r\n RCC->CR &= (uint32_t)0xFEF6FFFF;\r\n\r\n /* Reset PLLCFGR register */\r\n RCC->PLLCFGR = 0x24003010;\r\n\r\n /* Reset HSEBYP bit */\r\n RCC->CR &= (uint32_t)0xFFFBFFFF;\r\n\r\n /* Disable all interrupts */\r\n RCC->CIR = 0x00000000;\r\n\r\n#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)\r\n SystemInit_ExtMemCtl();\r\n#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */\r\n\r\n /* Configure the Vector Table location add offset address ------------------*/\r\n#ifdef VECT_TAB_SRAM\r\n SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\r\n#else\r\n // original line \r\n \r\n //SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */\r\n // copied from SKR2\r\n SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\r\n#endif\r\n\r\n}\r\n\r\n/**\r\n * @brief Configures the System clock source, PLL Multiplier and Divider factors,\r\n * AHB/APBx prescalers and Flash settings\r\n * @note This function should be called only once the RCC clock configuration\r\n * is reset to the default reset state (done in SystemInit() function).\r\n * @param None\r\n * @retval None\r\n */\r\n\r\nvoid SetSysClock(void)\r\n{\r\n#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)\r\n /* 1- Try to start with HSE and external clock */\r\n if (SetSysClock_PLL_HSE(1) == 0)\r\n#endif\r\n {\r\n#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)\r\n /* 2- If fail try to start with HSE and external xtal */\r\n if (SetSysClock_PLL_HSE(0) == 0)\r\n#endif\r\n {\r\n#if ((CLOCK_SOURCE) & USE_PLL_HSI)\r\n /* 3- If fail start with HSI clock */\r\n if (SetSysClock_PLL_HSI() == 0)\r\n#endif\r\n {\r\n {\r\n error(\"SetSysClock failed\\n\");\r\n }\r\n }\r\n }\r\n }\r\n}\r\n\r\n#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )\r\n/******************************************************************************/\r\n/* PLL (clocked by HSE) used as System clock source */\r\n/******************************************************************************/\r\nuint8_t SetSysClock_PLL_HSE(uint8_t bypass)\r\n{\r\n RCC_OscInitTypeDef RCC_OscInitStruct;\r\n RCC_ClkInitTypeDef RCC_ClkInitStruct;\r\n\r\n /* The voltage scaling allows optimizing the power consumption when the device is\r\n clocked below the maximum system frequency, to update the voltage scaling value\r\n regarding system frequency refer to product datasheet. */\r\n __HAL_RCC_PWR_CLK_ENABLE();\r\n __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);\r\n\r\n // Enable HSE oscillator and activate PLL with HSE as source\r\n RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;\r\n if (bypass == 0) {\r\n RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT\r\n } else {\r\n RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN\r\n }\r\n\r\n RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\r\n RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;\r\n RCC_OscInitStruct.PLL.PLLM = 8;\r\n#if (DEVICE_USBDEVICE)\r\n RCC_OscInitStruct.PLL.PLLN = 336;\r\n#else\r\n RCC_OscInitStruct.PLL.PLLN = 360;\r\n#endif\r\n RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // 180 MHz or 168 MHz if DEVICE_USBDEVICE defined\r\n RCC_OscInitStruct.PLL.PLLQ = 7; // 48 MHz if DEVICE_USBDEVICE defined\r\n if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {\r\n return 0; // FAIL\r\n }\r\n\r\n // Activate the OverDrive to reach the 180 MHz Frequency\r\n if (HAL_PWREx_EnableOverDrive() != HAL_OK) {\r\n return 0; // FAIL\r\n }\r\n\r\n // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers\r\n RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;\r\n RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;\r\n RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 or 168 MHz\r\n RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 or 42 MHz\r\n RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 or 84 MHz\r\n if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {\r\n return 0; // FAIL\r\n }\r\n\r\n // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);\r\n\r\n return 1;\r\n}\r\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */\r\n\r\n#if ((CLOCK_SOURCE) & USE_PLL_HSI)\r\n/******************************************************************************/\r\n/* PLL (clocked by HSI) used as System clock source */\r\n/******************************************************************************/\r\nuint8_t SetSysClock_PLL_HSI(void)\r\n{\r\n RCC_OscInitTypeDef RCC_OscInitStruct;\r\n RCC_ClkInitTypeDef RCC_ClkInitStruct;\r\n\r\n /* The voltage scaling allows optimizing the power consumption when the device is\r\n clocked below the maximum system frequency, to update the voltage scaling value\r\n regarding system frequency refer to product datasheet. */\r\n __HAL_RCC_PWR_CLK_ENABLE();\r\n __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);\r\n\r\n // Enable HSI oscillator and activate PLL with HSI as source\r\n RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;\r\n RCC_OscInitStruct.HSIState = RCC_HSI_ON;\r\n RCC_OscInitStruct.HSEState = RCC_HSE_OFF;\r\n RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;\r\n RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\r\n RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;\r\n RCC_OscInitStruct.PLL.PLLM = 8;\r\n#if (DEVICE_USBDEVICE)\r\n RCC_OscInitStruct.PLL.PLLN = 168;\r\n#else\r\n RCC_OscInitStruct.PLL.PLLN = 180;\r\n#endif\r\n RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // 180 MHz or 168 MHz if DEVICE_USBDEVICE defined\r\n RCC_OscInitStruct.PLL.PLLQ = 7; // 48 MHz if DEVICE_USBDEVICE defined\r\n if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {\r\n return 0; // FAIL\r\n }\r\n\r\n // Activate the OverDrive to reach the 180 MHz Frequency\r\n if (HAL_PWREx_EnableOverDrive() != HAL_OK) {\r\n return 0; // FAIL\r\n }\r\n\r\n /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */\r\n RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);\r\n RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;\r\n RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 or 168 MHz\r\n RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 or 42 MHz\r\n RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 or 84 MHz\r\n if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {\r\n return 0; // FAIL\r\n }\r\n\r\n // HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_3);\r\n\r\n return 1;\r\n}\r\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */\r\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_OCTOPUS_446/PeripheralNames.h", "content": "/* mbed Microcontroller Library\n *******************************************************************************\n * Copyright (c) 2014, STMicroelectronics\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and/or other materials provided with the distribution.\n * 3. Neither the name of STMicroelectronics nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *******************************************************************************\n */\n#ifndef MBED_PERIPHERALNAMES_H\n#define MBED_PERIPHERALNAMES_H\n\n#include \"cmsis.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\ntypedef enum {\n ADC_1 = (int)ADC1_BASE,\n ADC_2 = (int)ADC2_BASE,\n ADC_3 = (int)ADC3_BASE\n} ADCName;\n\ntypedef enum {\n DAC_1 = (int)DAC_BASE\n} DACName;\n\ntypedef enum {\n UART_1 = (int)USART1_BASE,\n UART_2 = (int)USART2_BASE,\n UART_3 = (int)USART3_BASE,\n UART_4 = (int)UART4_BASE,\n UART_5 = (int)UART5_BASE,\n UART_6 = (int)USART6_BASE\n} UARTName;\n\n#define DEVICE_SPI_COUNT 4\ntypedef enum {\n SPI_1 = (int)SPI1_BASE,\n SPI_2 = (int)SPI2_BASE,\n SPI_3 = (int)SPI3_BASE,\n SPI_4 = (int)SPI4_BASE\n} SPIName;\n\ntypedef enum {\n I2C_1 = (int)I2C1_BASE,\n I2C_2 = (int)I2C2_BASE,\n I2C_3 = (int)I2C3_BASE,\n FMPI2C_1 = (int)FMPI2C1_BASE\n} I2CName;\n\ntypedef enum {\n PWM_1 = (int)TIM1_BASE,\n PWM_2 = (int)TIM2_BASE,\n PWM_3 = (int)TIM3_BASE,\n PWM_4 = (int)TIM4_BASE,\n PWM_5 = (int)TIM5_BASE,\n PWM_8 = (int)TIM8_BASE,\n PWM_9 = (int)TIM9_BASE,\n PWM_10 = (int)TIM10_BASE,\n PWM_11 = (int)TIM11_BASE,\n PWM_12 = (int)TIM12_BASE,\n PWM_13 = (int)TIM13_BASE,\n PWM_14 = (int)TIM14_BASE\n} PWMName;\n\ntypedef enum {\n CAN_1 = (int)CAN1_BASE,\n CAN_2 = (int)CAN2_BASE\n} CANName;\n\ntypedef enum {\n QSPI_1 = (int)QSPI_R_BASE,\n} QSPIName;\n\ntypedef enum {\n USB_FS = (int)USB_OTG_FS_PERIPH_BASE,\n USB_HS = (int)USB_OTG_HS_PERIPH_BASE\n} USBName;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_OCTOPUS_446/PeripheralPins.c", "content": "/* mbed Microcontroller Library\n *******************************************************************************\n * Copyright (c) 2018, STMicroelectronics\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and/or other materials provided with the distribution.\n * 3. Neither the name of STMicroelectronics nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *******************************************************************************\n */\n\n#include \"PeripheralPins.h\"\n#include \"mbed_toolchain.h\"\n\n//==============================================================================\n// Notes\n//\n// - The pins mentioned Px_y_ALTz are alternative possibilities which use other\n// HW peripheral instances. You can use them the same way as any other \"normal\"\n// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board\n// pinout image on mbed.org.\n//\n// - The pins which are connected to other components present on the board have\n// the comment \"Connected to xxx\". The pin function may not work properly in this\n// case. These pins may not be displayed on the board pinout image on mbed.org.\n// Please read the board reference manual and schematic for more information.\n//\n// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented\n// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.\n//\n//==============================================================================\n\n\n//*** ADC ***\n\nMBED_WEAK const PinMap PinMap_ADC[] = {\n {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0\n {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0\n {PA_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0\n {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1\n {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1\n {PA_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1\n {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2\n {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2\n {PA_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2\n {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3\n {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3\n {PA_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3\n {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4\n {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4\n {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5\n {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5\n {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6\n {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6\n {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7\n {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7\n {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 // Connected to LD1\n {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 // Connected to LD1\n {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9\n {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9\n {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10\n {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10\n {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10\n {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11\n {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11\n {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11\n {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12\n {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12\n {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12\n {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13\n {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13\n {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13\n {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14\n {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14\n {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15\n {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15\n {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9\n {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14\n {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15\n {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4\n {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5\n {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6\n {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7\n {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_ADC_Internal[] = {\n {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},\n {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},\n {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},\n {NC, NC, 0}\n};\n\n//*** DAC ***\n\nMBED_WEAK const PinMap PinMap_DAC[] = {\n {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1\n {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2\n {NC, NC, 0}\n};\n\n//*** I2C ***\n\nMBED_WEAK const PinMap PinMap_I2C_SDA[] = {\n {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},\n {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},\n {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to LD2 [Blue]\n {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},\n {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},\n {PC_7, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},\n {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},\n {PC_12, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},\n {PD_13, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},\n {PD_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},\n {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},\n {PF_15, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_I2C_SCL[] = {\n {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // Connected to USB_SOF [TP1]\n {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},\n {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},\n {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},\n {PC_6, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},\n {PD_12, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},\n {PD_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},\n {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},\n {PF_14, FMPI2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_FMPI2C1)},\n {NC, NC, 0}\n};\n\n//*** PWM ***\n\n// TIM5 cannot be used because already used by the us_ticker\nMBED_WEAK const PinMap PinMap_PWM[] = {\n {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1\n// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1\n {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2\n// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2\n {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3\n// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3\n {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1\n {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4\n// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4\n {PA_3_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2\n {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1\n {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N\n {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1\n {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1\n {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N\n {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2\n {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N\n {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1\n {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 // Connected to USB_SOF [TP1]\n {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to USB_VBUS\n {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to USB_ID\n {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_DM\n {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1\n {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LD1\n {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 // Connected to LD1\n {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LD1\n {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N\n {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4\n {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N\n {PB_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4\n {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2\n {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1\n {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2\n {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1\n {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to LD2 [Blue]\n {PB_8, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1\n {PB_8_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3\n {PB_8_ALT1, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1\n {PB_9, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2\n {PB_9_ALT0, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4\n {PB_9_ALT1, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1\n {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3\n {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4\n {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N\n {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N // Connected to LD3 [Red]\n {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N // Connected to LD3 [Red]\n {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 // Connected to LD3 [Red]\n {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N\n {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N\n {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2\n {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1\n {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1\n {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2\n {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2\n {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3\n {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3\n {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4\n {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4\n {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1\n {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2\n {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3\n {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4\n {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1\n {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2\n {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N\n {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1\n {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N\n {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2\n {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N\n {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3\n {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4\n {PF_6, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1\n {PF_7, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1\n {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1\n {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1\n {NC, NC, 0}\n};\n\n//*** SERIAL ***\n\nMBED_WEAK const PinMap PinMap_UART_TX[] = {\n {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},\n {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},\n {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_VBUS\n {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},\n// {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // STDIO UART\n {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},\n// {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // STDIO UART\n {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},\n {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},\n {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},\n {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX\n {PE_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},\n {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_UART_RX[] = {\n {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},\n {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},\n {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_ID\n {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to LD2 [Blue]\n// {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // STDIO UART\n {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},\n {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},\n// {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // STDIO UART\n {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},\n {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},\n {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},\n {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX\n {PE_7, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},\n {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_UART_RTS[] = {\n {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},\n {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DP\n {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},\n {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LD3 [Red]\n {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)},\n {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},\n {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},\n {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},\n {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_UART_CTS[] = {\n {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},\n {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DM\n {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to LD1\n {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},\n {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART5)},\n {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},\n {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},\n {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},\n {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},\n {NC, NC, 0}\n};\n\n//*** SPI ***\n\nMBED_WEAK const PinMap PinMap_SPI_MOSI[] = {\n {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},\n {PB_0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, // Connected to LD1\n {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)},\n {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},\n {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},\n {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},\n {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)},\n {PC_1_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)},\n {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},\n {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},\n {PD_0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},\n {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)},\n {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},\n {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},\n {PG_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_SPI_MISO[] = {\n {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},\n {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},\n {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},\n {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LD3 [Red]\n {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},\n {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},\n {PD_0, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},\n {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},\n {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},\n {PG_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_SPI_SCLK[] = {\n {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},\n {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to USB_VBUS\n {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},\n {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},\n {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},\n {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},\n {PC_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},\n {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},\n {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},\n {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},\n {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},\n {PG_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_SPI_SSEL[] = {\n {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},\n {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},\n {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},\n {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},\n {PB_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)},\n {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},\n {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},\n {PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)},\n {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},\n {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},\n {PG_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI4)},\n {NC, NC, 0}\n};\n\n//*** CAN ***\n\nMBED_WEAK const PinMap PinMap_CAN_RD[] = {\n {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DM\n {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},\n {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},\n {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},\n {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_CAN_TD[] = {\n {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to USB_DP\n {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},\n {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},\n {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},\n {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},\n {NC, NC, 0}\n};\n\n//*** QUADSPI ***\n\nMBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {\n {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0\n {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO0\n {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO0\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {\n {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1\n {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO1\n {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_IO1\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {\n {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2\n {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO2\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {\n {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3\n {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3\n {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_BK1_IO3\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {\n {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_CLK\n {PD_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)}, // QUADSPI_CLK\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {\n {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS\n {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)}, // QUADSPI_BK1_NCS // Connected to USB_PowerSwitchOn [STMPS2151STR_EN]\n {NC, NC, 0}\n};\n\n//*** USBDEVICE ***\n\nMBED_WEAK const PinMap PinMap_USB_FS[] = {\n// {PA_8, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF // Connected to USB_SOF [TP1]\n {PA_9, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS // Connected to USB_VBUS\n {PA_10, USB_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_ID // Connected to USB_ID\n {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DM // Connected to USB_DM\n {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DP // Connected to USB_DP\n {NC, NC, 0}\n};\n\n//*** USBDEVICE ***\n\nMBED_WEAK const PinMap PinMap_USB_HS[] = {\n#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_HS_IN_FS)\n// {PA_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_SOF\n {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_ID\n {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS\n {PB_14, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DM // Connected to LD3 [Red]\n {PB_15, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DP\n#else /* MBED_CONF_TARGET_USB_SPEED */\n {PA_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D0\n {PA_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_CK\n {PB_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D1\n {PB_1, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D2\n {PB_2, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D4\n {PB_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D7\n {PB_10, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D3\n {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D5\n {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D6\n {PC_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_STP\n {PC_2, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_DIR\n {PC_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_NXT\n#endif /* MBED_CONF_TARGET_USB_SPEED */\n {NC, NC, 0}\n};\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_OCTOPUS_446/PinNames.h", "content": "/* mbed Microcontroller Library\n *******************************************************************************\n * Copyright (c) 2018, STMicroelectronics\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and/or other materials provided with the distribution.\n * 3. Neither the name of STMicroelectronics nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *******************************************************************************\n */\n\n#ifndef MBED_PINNAMES_H\n#define MBED_PINNAMES_H\n\n#include \"cmsis.h\"\n#include \"PinNamesTypes.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\ntypedef enum {\n ALT0 = 0x100,\n ALT1 = 0x200,\n ALT2 = 0x300,\n ALT3 = 0x400\n} ALTx;\n\ntypedef enum {\n PA_0 = 0x00,\n PA_0_ALT0 = PA_0 | ALT0,\n PA_0_ALT1 = PA_0 | ALT1,\n PA_1 = 0x01,\n PA_1_ALT0 = PA_1 | ALT0,\n PA_1_ALT1 = PA_1 | ALT1,\n PA_2 = 0x02,\n PA_2_ALT0 = PA_2 | ALT0,\n PA_2_ALT1 = PA_2 | ALT1,\n PA_3 = 0x03,\n PA_3_ALT0 = PA_3 | ALT0,\n PA_3_ALT1 = PA_3 | ALT1,\n PA_4 = 0x04,\n PA_4_ALT0 = PA_4 | ALT0,\n PA_5 = 0x05,\n PA_5_ALT0 = PA_5 | ALT0,\n PA_6 = 0x06,\n PA_6_ALT0 = PA_6 | ALT0,\n PA_7 = 0x07,\n PA_7_ALT0 = PA_7 | ALT0,\n PA_7_ALT1 = PA_7 | ALT1,\n PA_7_ALT2 = PA_7 | ALT2,\n PA_8 = 0x08,\n PA_9 = 0x09,\n PA_10 = 0x0A,\n PA_11 = 0x0B,\n PA_12 = 0x0C,\n PA_13 = 0x0D,\n PA_14 = 0x0E,\n PA_15 = 0x0F,\n PA_15_ALT0 = PA_15 | ALT0,\n\n PB_0 = 0x10,\n PB_0_ALT0 = PB_0 | ALT0,\n PB_0_ALT1 = PB_0 | ALT1,\n PB_1 = 0x11,\n PB_1_ALT0 = PB_1 | ALT0,\n PB_1_ALT1 = PB_1 | ALT1,\n PB_2 = 0x12,\n PB_3 = 0x13,\n PB_3_ALT0 = PB_3 | ALT0,\n PB_4 = 0x14,\n PB_4_ALT0 = PB_4 | ALT0,\n PB_4_ALT1 = PB_4 | ALT1,\n PB_5 = 0x15,\n PB_5_ALT0 = PB_5 | ALT0,\n PB_5_ALT1 = PB_5 | ALT1,\n PB_6 = 0x16,\n PB_7 = 0x17,\n PB_8 = 0x18,\n PB_8_ALT0 = PB_8 | ALT0,\n PB_8_ALT1 = PB_8 | ALT1,\n PB_9 = 0x19,\n PB_9_ALT0 = PB_9 | ALT0,\n PB_9_ALT1 = PB_9 | ALT1,\n PB_10 = 0x1A,\n PB_11 = 0x1B,\n PB_12 = 0x1C,\n PB_13 = 0x1D,\n PB_14 = 0x1E,\n PB_14_ALT0 = PB_14 | ALT0,\n PB_14_ALT1 = PB_14 | ALT1,\n PB_15 = 0x1F,\n PB_15_ALT0 = PB_15 | ALT0,\n PB_15_ALT1 = PB_15 | ALT1,\n\n PC_0 = 0x20,\n PC_0_ALT0 = PC_0 | ALT0,\n PC_0_ALT1 = PC_0 | ALT1,\n PC_1 = 0x21,\n PC_1_ALT0 = PC_1 | ALT0,\n PC_1_ALT1 = PC_1 | ALT1,\n PC_2 = 0x22,\n PC_2_ALT0 = PC_2 | ALT0,\n PC_2_ALT1 = PC_2 | ALT1,\n PC_3 = 0x23,\n PC_3_ALT0 = PC_3 | ALT0,\n PC_3_ALT1 = PC_3 | ALT1,\n PC_4 = 0x24,\n PC_4_ALT0 = PC_4 | ALT0,\n PC_5 = 0x25,\n PC_5_ALT0 = PC_5 | ALT0,\n PC_6 = 0x26,\n PC_6_ALT0 = PC_6 | ALT0,\n PC_7 = 0x27,\n PC_7_ALT0 = PC_7 | ALT0,\n PC_8 = 0x28,\n PC_8_ALT0 = PC_8 | ALT0,\n PC_9 = 0x29,\n PC_9_ALT0 = PC_9 | ALT0,\n PC_10 = 0x2A,\n PC_11 = 0x2B,\n PC_12 = 0x2C,\n PC_13 = 0x2D,\n PC_14 = 0x2E,\n PC_15 = 0x2F,\n\n PD_0 = 0x30,\n PD_1 = 0x31,\n PD_2 = 0x32,\n PD_3 = 0x33,\n PD_4 = 0x34,\n PD_5 = 0x35,\n PD_6 = 0x36,\n PD_7 = 0x37,\n PD_8 = 0x38,\n PD_9 = 0x39,\n PD_10 = 0x3A,\n PD_11 = 0x3B,\n PD_12 = 0x3C,\n PD_13 = 0x3D,\n PD_14 = 0x3E,\n PD_15 = 0x3F,\n\n PE_0 = 0x40,\n PE_1 = 0x41,\n PE_2 = 0x42,\n PE_3 = 0x43,\n PE_4 = 0x44,\n PE_5 = 0x45,\n PE_6 = 0x46,\n PE_7 = 0x47,\n PE_8 = 0x48,\n PE_9 = 0x49,\n PE_10 = 0x4A,\n PE_11 = 0x4B,\n PE_12 = 0x4C,\n PE_13 = 0x4D,\n PE_14 = 0x4E,\n PE_15 = 0x4F,\n\n PF_0 = 0x50,\n PF_1 = 0x51,\n PF_2 = 0x52,\n PF_3 = 0x53,\n PF_4 = 0x54,\n PF_5 = 0x55,\n PF_6 = 0x56,\n PF_7 = 0x57,\n PF_8 = 0x58,\n PF_9 = 0x59,\n PF_10 = 0x5A,\n PF_11 = 0x5B,\n PF_12 = 0x5C,\n PF_13 = 0x5D,\n PF_14 = 0x5E,\n PF_15 = 0x5F,\n\n PG_0 = 0x60,\n PG_1 = 0x61,\n PG_2 = 0x62,\n PG_3 = 0x63,\n PG_4 = 0x64,\n PG_5 = 0x65,\n PG_6 = 0x66,\n PG_7 = 0x67,\n PG_8 = 0x68,\n PG_9 = 0x69,\n PG_10 = 0x6A,\n PG_11 = 0x6B,\n PG_12 = 0x6C,\n PG_13 = 0x6D,\n PG_14 = 0x6E,\n PG_15 = 0x6F,\n\n PH_0 = 0x70,\n PH_1 = 0x71,\n PH_2 = 0x72,\n\n // ADC internal channels\n ADC_TEMP = 0xF0,\n ADC_VREF = 0xF1,\n ADC_VBAT = 0xF2,\n\n // Arduino connector namings\n A0 = PA_3,\n A1 = PC_0,\n A2 = PC_3,\n A3 = PF_3,\n A4 = PF_5,\n A5 = PF_10,\n D0 = PG_9,\n D1 = PG_14,\n D2 = PF_15,\n D3 = PE_13,\n D4 = PF_14,\n D5 = PE_11,\n D6 = PE_9,\n D7 = PF_13,\n D8 = PF_12,\n D9 = PD_15,\n D10 = PD_14,\n D11 = PA_7,\n D12 = PA_6,\n D13 = PA_5,\n D14 = PB_9,\n D15 = PB_8,\n\n // STDIO for console print\n#ifdef MBED_CONF_TARGET_STDIO_UART_TX\n STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,\n#else\n STDIO_UART_TX = PD_8,\n#endif\n#ifdef MBED_CONF_TARGET_STDIO_UART_RX\n STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,\n#else\n STDIO_UART_RX = PD_9,\n#endif\n\n // Generic signals namings\n LED1 = PB_0,\n LED2 = PB_7,\n LED3 = PB_14,\n LED4 = LED1,\n LED_RED = LED3,\n USER_BUTTON = PC_13,\n // Standardized button names\n BUTTON1 = USER_BUTTON,\n SERIAL_TX = STDIO_UART_TX, // Virtual Com Port\n SERIAL_RX = STDIO_UART_RX, // Virtual Com Port\n USBTX = STDIO_UART_TX, // Virtual Com Port\n USBRX = STDIO_UART_RX, // Virtual Com Port\n I2C_SCL = D15,\n I2C_SDA = D14,\n SPI_MOSI = D11,\n SPI_MISO = D12,\n SPI_SCK = D13,\n SPI_CS = D10,\n PWM_OUT = D9,\n\n /**** USB FS pins ****/\n USB_OTG_FS_DM = PA_11,\n USB_OTG_FS_DP = PA_12,\n USB_OTG_FS_ID = PA_10,\n USB_OTG_FS_SOF = PA_8,\n USB_OTG_FS_VBUS = PA_9,\n\n /**** USB HS pins ****/\n USB_OTG_HS_DM = PB_14,\n USB_OTG_HS_DP = PB_15,\n USB_OTG_HS_ID = PB_12,\n USB_OTG_HS_SOF = PA_4,\n USB_OTG_HS_ULPI_CK = PA_5,\n USB_OTG_HS_ULPI_D0 = PA_3,\n USB_OTG_HS_ULPI_D1 = PB_0,\n USB_OTG_HS_ULPI_D2 = PB_1,\n USB_OTG_HS_ULPI_D3 = PB_10,\n USB_OTG_HS_ULPI_D4 = PB_2,\n USB_OTG_HS_ULPI_D5 = PB_12,\n USB_OTG_HS_ULPI_D6 = PB_13,\n USB_OTG_HS_ULPI_D7 = PB_5,\n USB_OTG_HS_ULPI_DIR = PC_2,\n USB_OTG_HS_ULPI_NXT = PC_3,\n USB_OTG_HS_ULPI_STP = PC_0,\n USB_OTG_HS_VBUS = PB_13,\n\n /**** OSCILLATOR pins ****/\n RCC_OSC32_IN = PC_14,\n RCC_OSC32_OUT = PC_15,\n RCC_OSC_IN = PH_0,\n RCC_OSC_OUT = PH_1,\n\n /**** DEBUG pins ****/\n SYS_JTCK_SWCLK = PA_14,\n SYS_JTDI = PA_15,\n SYS_JTDO_SWO = PB_3,\n SYS_JTMS_SWDIO = PA_13,\n SYS_JTRST = PB_4,\n SYS_TRACECLK = PE_2,\n SYS_TRACED0 = PE_3,\n SYS_TRACED0_ALT0 = PC_8,\n SYS_TRACED1 = PE_4,\n SYS_TRACED1_ALT0 = PD_3,\n SYS_TRACED2 = PE_5,\n SYS_TRACED2_ALT0 = PG_13,\n SYS_TRACED3 = PE_6,\n SYS_TRACED3_ALT0 = PG_14,\n SYS_WKUP0 = PA_0,\n SYS_WKUP1 = PC_13,\n\n // Not connected\n NC = (int)0xFFFFFFFF\n} PinName;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_OCTOPUS_446/system_clock.c", "content": "/* mbed Microcontroller Library\n* Copyright (c) 2006-2017 ARM Limited\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n* http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*/\n\n/**\n * This file configures the system clock as follows:\n *-----------------------------------------------------------------------------\n * System clock source | 1- USE_PLL_HSE_EXTC (external 12 MHz clock)\n * | 2- USE_PLL_HSE_XTAL (external 12 MHz xtal)\n * | 3- USE_PLL_HSI (internal 16 MHz)\n *-----------------------------------------------------------------------------\n * SYSCLK(MHz) | 180\n * AHBCLK (MHz) | 180\n * APB1CLK (MHz) | 45\n * APB2CLK (MHz) | 90\n * USB capable | YES\n *-----------------------------------------------------------------------------\n**/\n\n#include \"stm32f4xx.h\"\n#include \"mbed_error.h\"\n\n\n/*!< Uncomment the following line if you need to relocate your vector Table in\n Internal SRAM. */\n/* #define VECT_TAB_SRAM */\n#define VECT_TAB_OFFSET 0x0000 /*!< Vector Table base offset field.\n This value must be a multiple of 0x200. */\n\n\n// clock source is selected with CLOCK_SOURCE in json config\n#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)\n#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)\n#define USE_PLL_HSI 0x2 // Use HSI internal clock\n\n//#define DEBUG_MCO (1) // Output the MCO1/MCO2 on PA8/PC9 for debugging (0=OFF, 1=ON)\n\n\n#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )\nuint8_t SetSysClock_PLL_HSE(uint8_t bypass);\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */\n\n#if ((CLOCK_SOURCE) & USE_PLL_HSI)\nuint8_t SetSysClock_PLL_HSI(void);\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */\n\n\n/**\n * @brief Setup the microcontroller system\n * Initialize the FPU setting, vector table location and External memory\n * configuration.\n * @param None\n * @retval None\n */\nvoid SystemInit(void)\n{\n /* FPU settings ------------------------------------------------------------*/\n#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\n SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */\n#endif\n /* Reset the RCC clock configuration to the default reset state ------------*/\n /* Set HSION bit */\n RCC->CR |= (uint32_t)0x00000001;\n\n /* Reset CFGR register */\n RCC->CFGR = 0x00000000;\n\n /* Reset HSEON, CSSON and PLLON bits */\n RCC->CR &= (uint32_t)0xFEF6FFFF;\n\n /* Reset PLLCFGR register */\n RCC->PLLCFGR = 0x24003010;\n\n /* Reset HSEBYP bit */\n RCC->CR &= (uint32_t)0xFFFBFFFF;\n\n /* Disable all interrupts */\n RCC->CIR = 0x00000000;\n\n#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)\n SystemInit_ExtMemCtl();\n#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */\n\n /* Configure the Vector Table location add offset address ------------------*/\n#ifdef VECT_TAB_SRAM\n SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\n#else\n SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\n#endif\n\n}\n\n\n/**\n * @brief Configures the System clock source, PLL Multiplier and Divider factors,\n * AHB/APBx prescalers and Flash settings\n * @note This function should be called only once the RCC clock configuration\n * is reset to the default reset state (done in SystemInit() function).\n * @param None\n * @retval None\n */\n\nvoid SetSysClock(void)\n{\n#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)\n /* 1- Try to start with HSE and external clock */\n if (SetSysClock_PLL_HSE(1) == 0)\n#endif\n {\n#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)\n /* 2- If fail try to start with HSE and external xtal */\n if (SetSysClock_PLL_HSE(0) == 0)\n#endif\n {\n#if ((CLOCK_SOURCE) & USE_PLL_HSI)\n /* 3- If fail start with HSI clock */\n if (SetSysClock_PLL_HSI() == 0)\n#endif\n {\n {\n error(\"SetSysClock failed\\n\");\n }\n }\n }\n }\n\n // Output clock on MCO2 pin(PC9) for debugging purpose\n#if DEBUG_MCO == 1\n HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);\n#endif\n}\n\n#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )\n/******************************************************************************/\n/* PLL (clocked by HSE) used as System clock source */\n/******************************************************************************/\nuint8_t SetSysClock_PLL_HSE(uint8_t bypass)\n{\n RCC_OscInitTypeDef RCC_OscInitStruct;\n RCC_ClkInitTypeDef RCC_ClkInitStruct;\n RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;\n\n /* Enable Power Control clock */\n __HAL_RCC_PWR_CLK_ENABLE();\n\n /* The voltage scaling allows optimizing the power consumption when the device is\n clocked below the maximum system frequency, to update the voltage scaling value\n regarding system frequency refer to product datasheet. */\n __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);\n\n /* Enable HSE oscillator and activate PLL with HSE as source */\n RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;\n if (bypass == 0) {\n RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */\n } else {\n RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */\n }\n RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\n RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;\n RCC_OscInitStruct.PLL.PLLM = 6; \n RCC_OscInitStruct.PLL.PLLN = 180; \n RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; \n RCC_OscInitStruct.PLL.PLLQ = 7; \n RCC_OscInitStruct.PLL.PLLR = 2; \n if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {\n return 0; // FAIL\n }\n\n // Activate the OverDrive to reach the 180 MHz Frequency\n if (HAL_PWREx_EnableOverDrive() != HAL_OK) {\n return 0; // FAIL\n }\n\n#if DEVICE_USBDEVICE\n // Select PLLSAI output as USB clock source\n PeriphClkInitStruct.PLLSAI.PLLSAIM = 6;\n PeriphClkInitStruct.PLLSAI.PLLSAIN = 96;\n PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV4;\n PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;\n PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;\n HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);\n#endif /* DEVICE_USBDEVICE */\n\n /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */\n RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);\n RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;\n RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz\n RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz\n RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz\n if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {\n return 0; // FAIL\n }\n\n // Output clock on MCO1 pin(PA8) for debugging purpose\n#if DEBUG_MCO == 1\n if (bypass == 0) {\n HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal\n } else {\n HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock (MCO)\n }\n#endif\n\n return 1; // OK\n}\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */\n\n#if ((CLOCK_SOURCE) & USE_PLL_HSI)\n/******************************************************************************/\n/* PLL (clocked by HSI) used as System clock source */\n/******************************************************************************/\nuint8_t SetSysClock_PLL_HSI(void)\n{\n RCC_OscInitTypeDef RCC_OscInitStruct;\n RCC_ClkInitTypeDef RCC_ClkInitStruct;\n RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;\n\n /* Enable Power Control clock */\n __HAL_RCC_PWR_CLK_ENABLE();\n\n /* The voltage scaling allows optimizing the power consumption when the device is\n clocked below the maximum system frequency, to update the voltage scaling value\n regarding system frequency refer to product datasheet. */\n __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);\n\n /* Enable HSI oscillator and activate PLL with HSI as source */\n RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;\n RCC_OscInitStruct.HSIState = RCC_HSI_ON;\n RCC_OscInitStruct.HSEState = RCC_HSE_OFF;\n RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;\n RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\n RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;\n RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)\n RCC_OscInitStruct.PLL.PLLN = 360; // VCO output clock = 360 MHz (1 MHz * 360)\n RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 180 MHz (360 MHz / 2)\n RCC_OscInitStruct.PLL.PLLQ = 7; //\n RCC_OscInitStruct.PLL.PLLR = 6; //\n if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {\n return 0; // FAIL\n }\n\n#if DEVICE_USBDEVICE\n /* Select PLLSAI output as USB clock source */\n PeriphClkInitStruct.PLLSAI.PLLSAIM = 8;\n PeriphClkInitStruct.PLLSAI.PLLSAIN = 192;\n PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLSAIP_DIV8;\n PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48;\n PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLSAIP;\n HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);\n#endif /* DEVICE_USBDEVICE */\n\n /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */\n RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);\n RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 180 MHz\n RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 180 MHz\n RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 45 MHz\n RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 90 MHz\n if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {\n return 0; // FAIL\n }\n\n // Output clock on MCO1 pin(PA8) for debugging purpose\n#if DEBUG_MCO == 1\n HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz\n#endif\n\n return 1; // OK\n}\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_ROBIN_E3/PeripheralNames.h", "content": "/* mbed Microcontroller Library\n *******************************************************************************\n * Copyright (c) 2014, STMicroelectronics\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and/or other materials provided with the distribution.\n * 3. Neither the name of STMicroelectronics nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *******************************************************************************\n */\n#ifndef MBED_PERIPHERALNAMES_H\n#define MBED_PERIPHERALNAMES_H\n\n#include \"cmsis.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\ntypedef enum {\n ADC_1 = (int)ADC1_BASE,\n ADC_2 = (int)ADC2_BASE,\n ADC_3 = (int)ADC3_BASE\n} ADCName;\n\ntypedef enum {\n DAC_1 = (int)DAC_BASE\n} DACName;\n\ntypedef enum {\n UART_1 = (int)USART1_BASE,\n UART_2 = (int)USART2_BASE,\n UART_3 = (int)USART3_BASE,\n UART_4 = (int)UART4_BASE,\n UART_5 = (int)UART5_BASE\n} UARTName;\n\n#define DEVICE_SPI_COUNT 3\ntypedef enum {\n SPI_1 = (int)SPI1_BASE,\n SPI_2 = (int)SPI2_BASE,\n SPI_3 = (int)SPI3_BASE\n} SPIName;\n\ntypedef enum {\n I2C_1 = (int)I2C1_BASE,\n I2C_2 = (int)I2C2_BASE\n} I2CName;\n\ntypedef enum {\n PWM_1 = (int)TIM1_BASE,\n PWM_2 = (int)TIM2_BASE,\n PWM_3 = (int)TIM3_BASE,\n PWM_4 = (int)TIM4_BASE,\n PWM_5 = (int)TIM5_BASE,\n PWM_8 = (int)TIM8_BASE\n} PWMName;\n\ntypedef enum {\n CAN_1 = (int)CAN1_BASE\n} CANName;\n\ntypedef enum {\n USB_FS = (int)USB_BASE\n} USBName;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_ROBIN_E3/PeripheralPins.c", "content": "/* mbed Microcontroller Library\n *******************************************************************************\n * Copyright (c) 2018, STMicroelectronics\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and/or other materials provided with the distribution.\n * 3. Neither the name of STMicroelectronics nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *******************************************************************************\n */\n\n#include \"PeripheralPins.h\"\n#include \"mbed_toolchain.h\"\n\n//==============================================================================\n// Notes\n//\n// - The pins mentioned Px_y_ALTz are alternative possibilities which use other\n// HW peripheral instances. You can use them the same way as any other \"normal\"\n// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board\n// pinout image on mbed.org.\n//\n// - The pins which are connected to other components present on the board have\n// the comment \"Connected to xxx\". The pin function may not work properly in this\n// case. These pins may not be displayed on the board pinout image on mbed.org.\n// Please read the board reference manual and schematic for more information.\n//\n// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented\n// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.\n//\n//==============================================================================\n\n\n//*** ADC ***\n\nMBED_WEAK const PinMap PinMap_ADC[] = {\n {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0\n {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1\n// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to STDIO_UART_TX\n// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to STDIO_UART_RX\n {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4\n {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to LD2 [Green Led]\n {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6\n {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7\n {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8\n {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9\n {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10\n {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11\n {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12\n {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13\n {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14\n {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_ADC_Internal[] = {\n {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},\n {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},\n {NC, NC, 0}\n};\n\n//*** I2C ***\n\nMBED_WEAK const PinMap PinMap_I2C_SDA[] = {\n {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)},\n {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 2)}, // GPIO_Remap_I2C1\n {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_I2C_SCL[] = {\n {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)},\n {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 2)}, // GPIO_Remap_I2C1\n {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)},\n {NC, NC, 0}\n};\n\n//*** PWM ***\n\n// TIM4 cannot be used because already used by the us_ticker\nMBED_WEAK const PinMap PinMap_PWM[] = {\n {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM2_CH1\n {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM2_CH2\n// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM2_CH3 // Connected to STDIO_UART_TX\n// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM2_CH4 // Connected to STDIO_UART_RX\n {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM3_CH1\n {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM3_CH2\n {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM1_CH1\n {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM1_CH2\n {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM1_CH3\n {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM1_CH4\n {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 1, 0)}, // TIM2_CH1\n {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM3_CH3\n {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM3_CH4\n {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 2, 0)}, // TIM2_CH2 // Connected to SWO\n {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 1, 0)}, // TIM3_CH1\n {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 2, 0)}, // TIM3_CH2\n// {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM4_CH1\n// {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM4_CH2\n// {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM4_CH3\n// {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM4_CH4\n {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 3, 0)}, // TIM2_CH3\n {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 4, 0)}, // TIM2_CH4\n {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 1)}, // TIM1_CH1N\n {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 1)}, // TIM1_CH2N\n {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 1)}, // TIM1_CH3N\n {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 9, 1, 0)}, // TIM3_CH1\n {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 9, 2, 0)}, // TIM3_CH2\n {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 9, 3, 0)}, // TIM3_CH3\n {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 9, 4, 0)}, // TIM3_CH4\n {NC, NC, 0}\n};\n\n//*** SERIAL ***\n\nMBED_WEAK const PinMap PinMap_UART_TX[] = {\n {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // Connected to STDIO_UART_TX\n {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},\n {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 3)}, // GPIO_Remap_USART1\n {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},\n {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 5)}, // GPIO_PartialRemap_USART3\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_UART_RX[] = {\n {PA_3, UART_2, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 0)}, // Connected to STDIO_UART_RX\n {PA_10, UART_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 0)},\n {PB_7, UART_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 3)}, // GPIO_Remap_USART1\n {PB_11, UART_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 0)},\n {PC_11, UART_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 5)}, // GPIO_PartialRemap_USART3\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_UART_RTS[] = {\n {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},\n {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},\n {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_UART_CTS[] = {\n {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},\n {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},\n {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},\n {NC, NC, 0}\n};\n\n//*** SPI ***\n\nMBED_WEAK const PinMap PinMap_SPI_MOSI[] = {\n {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},\n {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, // GPIO_Remap_SPI1\n {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_SPI_MISO[] = {\n {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},\n {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, // GPIO_Remap_SPI1\n {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_SPI_SCLK[] = {\n {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, // Connected to LD2 [Green Led]\n {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, // GPIO_Remap_SPI1 // Connected to SWO\n {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_SPI_SSEL[] = {\n {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},\n {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, // GPIO_Remap_SPI1\n {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},\n {NC, NC, 0}\n};\n\n//*** CAN ***\n\nMBED_WEAK const PinMap PinMap_CAN_RD[] = {\n {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)},\n {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 10)}, // Remap CAN_RX to PB_8\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_CAN_TD[] = {\n {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},\n {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 10)}, // Remap CAN_TX to PB_9\n {NC, NC, 0}\n};\n\n//*** USBDEVICE ***\n\nMBED_WEAK const PinMap PinMap_USB_FS[] = {\n {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)}, // USB_DM\n {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)}, // USB_DP\n {NC, NC, 0}\n};\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_ROBIN_E3/PinNames.h", "content": "/* mbed Microcontroller Library\n *******************************************************************************\n * Copyright (c) 2018, STMicroelectronics\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and/or other materials provided with the distribution.\n * 3. Neither the name of STMicroelectronics nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *******************************************************************************\n */\n\n#ifndef MBED_PINNAMES_H\n#define MBED_PINNAMES_H\n\n#include \"cmsis.h\"\n#include \"PinNamesTypes.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\ntypedef enum {\n PA_0 = 0x00,\n PA_1 = 0x01,\n PA_2 = 0x02,\n PA_3 = 0x03,\n PA_4 = 0x04,\n PA_5 = 0x05,\n PA_6 = 0x06,\n PA_7 = 0x07,\n PA_8 = 0x08,\n PA_9 = 0x09,\n PA_10 = 0x0A,\n PA_11 = 0x0B,\n PA_12 = 0x0C,\n PA_13 = 0x0D,\n PA_14 = 0x0E,\n PA_15 = 0x0F,\n\n PB_0 = 0x10,\n PB_1 = 0x11,\n PB_2 = 0x12,\n PB_3 = 0x13,\n PB_4 = 0x14,\n PB_5 = 0x15,\n PB_6 = 0x16,\n PB_7 = 0x17,\n PB_8 = 0x18,\n PB_9 = 0x19,\n PB_10 = 0x1A,\n PB_11 = 0x1B,\n PB_12 = 0x1C,\n PB_13 = 0x1D,\n PB_14 = 0x1E,\n PB_15 = 0x1F,\n\n PC_0 = 0x20,\n PC_1 = 0x21,\n PC_2 = 0x22,\n PC_3 = 0x23,\n PC_4 = 0x24,\n PC_5 = 0x25,\n PC_6 = 0x26,\n PC_7 = 0x27,\n PC_8 = 0x28,\n PC_9 = 0x29,\n PC_10 = 0x2A,\n PC_11 = 0x2B,\n PC_12 = 0x2C,\n PC_13 = 0x2D,\n PC_14 = 0x2E,\n PC_15 = 0x2F,\n\n PD_0 = 0x30,\n PD_1 = 0x31,\n PD_2 = 0x32,\n\n // ADC internal channels\n ADC_TEMP = 0xF0,\n ADC_VREF = 0xF1,\n\n // Arduino connector namings\n A0 = PA_0,\n A1 = PA_1,\n A2 = PA_4,\n A3 = PB_0,\n A4 = PC_1,\n A5 = PC_0,\n D0 = PA_3,\n D1 = PA_2,\n D2 = PA_10,\n D3 = PB_3,\n D4 = PB_5,\n D5 = PB_4,\n D6 = PB_10,\n D7 = PA_8,\n D8 = PA_9,\n D9 = PC_7,\n D10 = PB_6,\n D11 = PA_7,\n D12 = PA_6,\n D13 = PA_5,\n D14 = PB_9,\n D15 = PB_8,\n\n // STDIO for console print\n#ifdef MBED_CONF_TARGET_STDIO_UART_TX\n STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,\n#else\n STDIO_UART_TX = PA_2,\n#endif\n#ifdef MBED_CONF_TARGET_STDIO_UART_RX\n STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,\n#else\n STDIO_UART_RX = PA_3,\n#endif\n\n // Generic signals namings\n LED1 = PA_5,\n LED2 = PA_5,\n LED3 = PA_5,\n LED4 = PA_5,\n USER_BUTTON = PC_13,\n // Standardized button names\n BUTTON1 = USER_BUTTON,\n SERIAL_TX = STDIO_UART_TX,\n SERIAL_RX = STDIO_UART_RX,\n USBTX = STDIO_UART_TX,\n USBRX = STDIO_UART_RX,\n I2C_SCL = PB_8,\n I2C_SDA = PB_9,\n SPI_MOSI = PA_7,\n SPI_MISO = PA_6,\n SPI_SCK = PA_5,\n SPI_CS = PB_6,\n PWM_OUT = PB_3,\n\n /**** USB pins ****/\n USB_DM = PA_11,\n USB_DP = PA_12,\n\n /**** OSCILLATOR pins ****/\n RCC_OSC32_IN = PC_14,\n RCC_OSC32_OUT = PC_15,\n RCC_OSC_IN = PD_0,\n RCC_OSC_OUT = PD_1,\n\n /**** DEBUG pins ****/\n SYS_JTCK_SWCLK = PA_14,\n SYS_JTDI = PA_15,\n SYS_JTDO_TRACESWO = PB_3,\n SYS_JTMS_SWDIO = PA_13,\n SYS_NJTRST = PB_4,\n SYS_WKUP = PA_0,\n\n // Not connected\n NC = (int)0xFFFFFFFF\n} PinName;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_ROBIN_E3/system_clock.c", "content": "/* mbed Microcontroller Library\n* Copyright (c) 2006-2017 ARM Limited\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n* http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*/\n\n/**\n * This file configures the system clock as follows:\n *-------------------------------------------------------------------------------------------\n * System clock source | 1- PLL_HSE_EXTC / DEVICE_USBDEVICE | 3- PLL_HSI / DEVICE_USBDEVICE\n * | (external 8 MHz clock) | (internal 8 MHz)\n * | 2- PLL_HSE_XTAL / DEVICE_USBDEVICE |\n * | (external 8 MHz xtal) |\n *-------------------------------------------------------------------------------------------\n * SYSCLK(MHz) | 72 / 72 | 64 / 48\n *-------------------------------------------------------------------------------------------\n * AHBCLK (MHz) | 72 / 72 | 64 / 48\n *-------------------------------------------------------------------------------------------\n * APB1CLK (MHz) | 36 / 36 | 32 / 24\n *-------------------------------------------------------------------------------------------\n * APB2CLK (MHz) | 72 / 72 | 64 / 48\n *-------------------------------------------------------------------------------------------\n */\n\n#include \"stm32f1xx.h\"\n#include \"mbed_error.h\"\n\n/*!< Uncomment the following line if you need to relocate your vector Table in\n Internal SRAM. */\n/* #define VECT_TAB_SRAM */\n#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.\n This value must be a multiple of 0x200. */\n\n#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)\n#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)\n#define USE_PLL_HSI 0x2 // Use HSI internal clock\n\n#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )\nuint8_t SetSysClock_PLL_HSE(uint8_t bypass);\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */\n\n#if ((CLOCK_SOURCE) & USE_PLL_HSI)\nuint8_t SetSysClock_PLL_HSI(void);\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */\n\n\n/**\n * @brief Setup the microcontroller system\n * Initialize the Embedded Flash Interface, the PLL and update the\n * SystemCoreClock variable.\n * @note This function should be used only after reset.\n * @param None\n * @retval None\n */\nvoid SystemInit (void)\n{\n /* Reset the RCC clock configuration to the default reset state(for debug purpose) */\n /* Set HSION bit */\n RCC->CR |= 0x00000001U;\n\n /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */\n#if !defined(STM32F105xC) && !defined(STM32F107xC)\n RCC->CFGR &= 0xF8FF0000U;\n#else\n RCC->CFGR &= 0xF0FF0000U;\n#endif /* STM32F105xC */\n\n /* Reset HSEON, CSSON and PLLON bits */\n RCC->CR &= 0xFEF6FFFFU;\n\n /* Reset HSEBYP bit */\n RCC->CR &= 0xFFFBFFFFU;\n\n /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */\n RCC->CFGR &= 0xFF80FFFFU;\n\n#if defined(STM32F105xC) || defined(STM32F107xC)\n /* Reset PLL2ON and PLL3ON bits */\n RCC->CR &= 0xEBFFFFFFU;\n\n /* Disable all interrupts and clear pending bits */\n RCC->CIR = 0x00FF0000U;\n\n /* Reset CFGR2 register */\n RCC->CFGR2 = 0x00000000U;\n#elif defined(STM32F100xB) || defined(STM32F100xE)\n /* Disable all interrupts and clear pending bits */\n RCC->CIR = 0x009F0000U;\n\n /* Reset CFGR2 register */\n RCC->CFGR2 = 0x00000000U;\n#else\n /* Disable all interrupts and clear pending bits */\n RCC->CIR = 0x009F0000U;\n#endif /* STM32F105xC */\n\n#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)\n#ifdef DATA_IN_ExtSRAM\n SystemInit_ExtMemCtl();\n#endif /* DATA_IN_ExtSRAM */\n#endif\n\n#ifdef VECT_TAB_SRAM\n SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */\n#else\n SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */\n#endif\n\n}\n\n/**\n * @brief Configures the System clock source, PLL Multiplier and Divider factors,\n * AHB/APBx prescalers and Flash settings\n * @note This function should be called only once the RCC clock configuration\n * is reset to the default reset state (done in SystemInit() function).\n * @param None\n * @retval None\n */\nvoid SetSysClock(void)\n{\n#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)\n /* 1- Try to start with HSE and external clock */\n if (SetSysClock_PLL_HSE(1) == 0)\n#endif\n {\n#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)\n /* 2- If fail try to start with HSE and external xtal */\n if (SetSysClock_PLL_HSE(0) == 0)\n#endif\n {\n#if ((CLOCK_SOURCE) & USE_PLL_HSI)\n /* 3- If fail start with HSI clock */\n if (SetSysClock_PLL_HSI() == 0)\n#endif\n {\n {\n error(\"SetSysClock failed\\n\");\n }\n }\n }\n }\n\n /* Output clock on MCO1 pin(PA8) for debugging purpose */\n //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 72 MHz or 64 MHz\n}\n\n#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )\n/******************************************************************************/\n/* PLL (clocked by HSE) used as System clock source */\n/******************************************************************************/\nuint8_t SetSysClock_PLL_HSE(uint8_t bypass)\n{\n RCC_ClkInitTypeDef RCC_ClkInitStruct;\n RCC_OscInitTypeDef RCC_OscInitStruct;\n#if (DEVICE_USBDEVICE)\n RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInit;\n#endif /* DEVICE_USBDEVICE */\n\n /* Enable HSE oscillator and activate PLL with HSE as source */\n RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;\n if (bypass == 0) {\n RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */\n } else {\n RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */\n }\n RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;\n RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\n RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;\n RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)\n if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {\n return 0; // FAIL\n }\n\n /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */\n RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);\n RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz\n RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz\n RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz\n RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz\n if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {\n return 0; // FAIL\n }\n\n#if (DEVICE_USBDEVICE)\n /* USB clock selection */\n RCC_PeriphCLKInit.PeriphClockSelection = RCC_PERIPHCLK_USB;\n RCC_PeriphCLKInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;\n HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInit);\n#endif /* DEVICE_USBDEVICE */\n\n /* Output clock on MCO1 pin(PA8) for debugging purpose */\n //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz\n\n return 1; // OK\n}\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */\n\n#if ((CLOCK_SOURCE) & USE_PLL_HSI)\n/******************************************************************************/\n/* PLL (clocked by HSI) used as System clock source */\n/******************************************************************************/\nuint8_t SetSysClock_PLL_HSI(void)\n{\n RCC_ClkInitTypeDef RCC_ClkInitStruct;\n RCC_OscInitTypeDef RCC_OscInitStruct;\n#if (DEVICE_USBDEVICE)\n RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInit;\n#endif /* DEVICE_USBDEVICE */\n\n /* Enable HSI oscillator and activate PLL with HSI as source */\n RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;\n RCC_OscInitStruct.HSIState = RCC_HSI_ON;\n RCC_OscInitStruct.HSEState = RCC_HSE_OFF;\n RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;\n RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\n RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;\n#if (DEVICE_USBDEVICE)\n RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; // 48 MHz (8 MHz/2 * 12)\n#else /* DEVICE_USBDEVICE */\n RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)\n#endif /* DEVICE_USBDEVICE */\n if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {\n return 0; // FAIL\n }\n\n#if (DEVICE_USBDEVICE)\n /* USB clock selection */\n RCC_PeriphCLKInit.PeriphClockSelection = RCC_PERIPHCLK_USB;\n RCC_PeriphCLKInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL;\n HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInit);\n#endif /* DEVICE_USBDEVICE */\n\n /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */\n RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);\n RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz\n RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz\n RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz\n RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz\n if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {\n return 0; // FAIL\n }\n\n /* Output clock on MCO1 pin(PA8) for debugging purpose */\n //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz\n\n return 1; // OK\n}\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/.hg/branch", "content": "default\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/.hg/cache/branch2-base", "content": "97a16bf2ff439853ed01edd65a382207e203c733 17\n97a16bf2ff439853ed01edd65a382207e203c733 o default\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/.hg/cache/rbc-names-v1", "content": "default" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/.hg/cache/tags2-visible", "content": "17 97a16bf2ff439853ed01edd65a382207e203c733\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/.hg/hgrc", "content": "# example repository config (see 'hg help config' for more info)\n[paths]\nmbed-studio-cache = c:\\Users\\tanya\\AppData\\Local\\Mbed Studio\\library-cache\\os.mbed.com\\users\\AjK\\code\\MODDMA\ndefault = https://os.mbed.com/users/AjK/code/MODDMA/\n\n# path aliases to other clones of this repo in URLs or filesystem paths\n# (see 'hg help config.paths' for more info)\n#\n# default:pushurl = ssh://jdoe@example.net/hg/jdoes-fork\n# my-fork = ssh://jdoe@example.net/hg/jdoes-fork\n# my-clone = /home/jdoe/jdoes-clone\n\n[ui]\n# name and email (local to this repository, optional), e.g.\n# username = Jane Doe \n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/.hg/requires", "content": "dotencode\nfncache\ngeneraldelta\nrevlogv1\nsparserevlog\nstore\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/.hg/store/fncache", "content": "data/example4.h.i\ndata/example2.h.i\ndata/ChangeLog.c.i\ndata/example2.cpp.i\ndata/CONFIG.h.i\ndata/example1.h.i\ndata/MODDMA.h.i\ndata/example1.cpp.i\ndata/SETUP.cpp.i\ndata/example3.h.i\ndata/DATALUTS.cpp.i\ndata/INIT.cpp.i\ndata/iomacros.h.i\ndata/MODDMA.cpp.i\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/.hg/thgstatus", "content": "" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/CONFIG.h", "content": "/*\n Copyright (c) 2010 Andy Kirkham\n \n Permission is hereby granted, free of charge, to any person obtaining a copy\n of this software and associated documentation files (the \"Software\"), to deal\n in the Software without restriction, including without limitation the rights\n to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n copies of the Software, and to permit persons to whom the Software is\n furnished to do so, subject to the following conditions:\n \n The above copyright notice and this permission notice shall be included in\n all copies or substantial portions of the Software.\n \n THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n THE SOFTWARE.\n*/\n\n#ifdef NOCOMPILE\n\n#ifndef MODDMA_CONFIG_H\n#define MODDMA_CONFIG_H\n\n#include \"mbed.h\"\n\nnamespace AjK {\n\n// Forward reference.\nclass MODDMA;\n\nclass MODDMA_Channel_CFG_t {\npublic:\n\n // *****************************************\n // From GPDMA by NXP MCU SW Application Team\n // *****************************************\n \n uint32_t ChannelNum; //!< DMA channel number, should be in range from 0 to 7. \n uint32_t TransferSize; //!< Length/Size of transfer \n uint32_t TransferWidth; //!< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_m2m only \n uint32_t SrcMemAddr; //!< Physical Src Addr, used in case TransferType is chosen as MODDMA::GPDMA_TRANSFERTYPE::m2m or MODDMA::GPDMA_TRANSFERTYPE::m2p \n uint32_t DstMemAddr; //!< Physical Destination Address, used in case TransferType is chosen as MODDMA::GPDMA_TRANSFERTYPE::m2m or MODDMA::GPDMA_TRANSFERTYPE::p2m \n uint32_t TransferType; //!< Transfer Type\n uint32_t SrcConn; ///!< Peripheral Source Connection type, used in case TransferType is chosen as\n uint32_t DstConn; //!< Peripheral Destination Connection type, used in case TransferType is chosen as\n uint32_t DMALLI; //!< Linker List Item structure data address if there's no Linker List, set as '0'\n \n // Mbed specifics.\n \n MODDMA_Channel_CFG_t() {\n isrIntTCStat = new FunctionPointer;\n isrIntErrStat = new FunctionPointer;\n }\n \n ~MODDMA_Channel_CFG_t() {\n delete(isrIntTCStat);\n delete(isrIntErrStat);\n }\n \n class MODDMA_Channel_CFG_t * channelNum(uint32_t n) { ChannelNum = n; return this; }\n class MODDMA_Channel_CFG_t * transferSize(uint32_t n) { TransferSize = n; return this; }\n class MODDMA_Channel_CFG_t * transferWidth(uint32_t n) { TransferWidth = n; return this; }\n class MODDMA_Channel_CFG_t * srcMemAddr(uint32_t n) { SrcMemAddr = n; return this; }\n class MODDMA_Channel_CFG_t * dstMemAddr(uint32_t n) { DstMemAddr = n; return this; }\n class MODDMA_Channel_CFG_t * transferType(uint32_t n) { TransferType = n; return this; }\n class MODDMA_Channel_CFG_t * srcConn(uint32_t n) { SrcConn = n; return this; }\n class MODDMA_Channel_CFG_t * dstConn(uint32_t n) { DstConn = n; return this; }\n class MODDMA_Channel_CFG_t * dmaLLI(uint32_t n) { DMALLI = n; return this; }\n \n uint32_t channelNum(void) { return ChannelNum; }\n \n FunctionPointer *isrIntTCStat; \n FunctionPointer *isrIntErrStat; \n};\n\n/**\n * @brief GPDMA Linker List Item structure type definition\n */\nclass GPDMA_LLI_t \n{\npublic:\n uint32_t SrcAddr; //!< Source Address \n uint32_t DstAddr; //!< Destination address \n uint32_t NextLLI; //!< Next LLI address, otherwise set to '0' \n uint32_t Control; //!< GPDMA Control of this LLI \n};\n\n}; // namespace AjK ends.\n\n#endif \n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/ChangeLog.c", "content": "/* $Id:$\n\n1.13- 2 Mar 2013\n\n * Update RESERVED9 to DMAREQSEL in SETUP.cpp\n Thanks Bryce Chee for pointing it out.\n\n1.12- 14 Mar 2011\n\n * Added example4.h that demonstrates alternately sending\n two buffers (double buffering) to the DAC. All those\n people building MP3 players may find this of interest.\n \n1.11- 13 Mar 2011\n\n * Fixed a silly typo in the documentation of example3.h\n \n1.10- 13 Mar 2011\n\n * The rescheduling showed the timer being stopped and restarted\n to perform a new scheduled grab. This was changed to show the \n timer free running and the reschedules being setup.\n\n1.9 - 13 Mar 2011\n\n * Improved example3.h to add rescheduling additional grabs\n based on the timer setup.\n \n1.8 - 13 Mar 2011\n\n * Renamed example files to .h\n * Added pseudo g2m and m2g transferTypes to support GPIO \n \"memory moves\" but triggered by peripheral timer. To \n support this new operating mode added example3.h\n \n1.7 - 13 Mar 2011\n\n * Remove the test at the beginning of the channel setup.\n \n1.6 - 8 Mar 2011\n \n * Fixed a typo bug. Reported by Wim van der Vegt\n http://mbed.org/forum/mbed/topic/1798/?page=1#comment-9845\n \n1.5 - 5 Feb 2011\n\n * Found a bug in the NXP library that I had copied over.\n http://mbed.org/forum/mbed/topic/1798\n * Added example2.cpp to support that forum thread.\n \n1.4 - 23/11/2010\n\n * Added some extra overloaded methods to make calling certain\n userland API methods simpler.\n \n1.3 - 23/10/2010\n\n * Added the LLI class wrapper.\n * Added checking channel's LLI for non-null before auto-disable\n of a channel with the ISR.\n * Tested with MODSERIAL which is now natively MODDMA \"aware\".\n MODSERIAL can now, using MODDMA, send blocks of bytes out\n of it's TX port under DMA control.\n \n1.2 - 23/10/2010\n\n * Improved the IRQ callback attachment API to make \n easier attachments when creating configurations.\n \n1.1 - 23/10/2010\n\n * Tidied up example1.cpp\n * Removed some unneeded methoids that cause compiler errs.\n \n1.0 - 23/11/2010\n\n * First release\n\n*/\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/DATALUTS.cpp", "content": "/*\n Copyright (c) 2010 Andy Kirkham\n \n Permission is hereby granted, free of charge, to any person obtaining a copy\n of this software and associated documentation files (the \"Software\"), to deal\n in the Software without restriction, including without limitation the rights\n to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n copies of the Software, and to permit persons to whom the Software is\n furnished to do so, subject to the following conditions:\n \n The above copyright notice and this permission notice shall be included in\n all copies or substantial portions of the Software.\n \n THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n THE SOFTWARE.\n*/\n\n#include \"MODDMA.h\"\n\n#ifndef MBED_H\n#include \"mbed.h\"\n#endif\n\n#ifndef MODDMA_CONFIG_H\n#include \"CONFIG.h\"\n#endif\n\nnamespace AjK {\n\nuint32_t\nMODDMA::LUTPerAddr(int n)\n{\n const uint32_t lut[] = { \n (uint32_t)&LPC_SSP0->DR // SSP0 Tx\n , (uint32_t)&LPC_SSP0->DR // SSP0 Rx\n , (uint32_t)&LPC_SSP1->DR // SSP1 Tx\n , (uint32_t)&LPC_SSP1->DR // SSP1 Rx\n , (uint32_t)&LPC_ADC->ADGDR // ADC\n , (uint32_t)&LPC_I2S->I2STXFIFO // I2S Tx\n , (uint32_t)&LPC_I2S->I2SRXFIFO // I2S Rx\n , (uint32_t)&LPC_DAC->DACR // DAC\n , (uint32_t)&LPC_UART0->THR // UART0 Tx\n , (uint32_t)&LPC_UART0->RBR // UART0 Rx\n , (uint32_t)&LPC_UART1->THR // UART1 Tx\n , (uint32_t)&LPC_UART1->RBR // UART1 Rx\n , (uint32_t)&LPC_UART2->THR // UART2 Tx\n , (uint32_t)&LPC_UART2->RBR // UART2 Rx\n , (uint32_t)&LPC_UART3->THR // UART3 Tx\n , (uint32_t)&LPC_UART3->RBR // UART3 Rx\n , (uint32_t)&LPC_TIM0->MR0 // MAT0.0\n , (uint32_t)&LPC_TIM0->MR1 // MAT0.1\n , (uint32_t)&LPC_TIM1->MR0 // MAT1.0\n , (uint32_t)&LPC_TIM1->MR1 // MAT1.1\n , (uint32_t)&LPC_TIM2->MR0 // MAT2.0\n , (uint32_t)&LPC_TIM2->MR1 // MAT2.1\n , (uint32_t)&LPC_TIM3->MR0 // MAT3.0\n , (uint32_t)&LPC_TIM3->MR1 // MAT3.1 \n };\n return lut[n & 0xFF]; \n}\n\nuint32_t\nMODDMA::Channel_p(int channel)\n{\n const uint32_t lut[] = {\n (uint32_t)LPC_GPDMACH0\n , (uint32_t)LPC_GPDMACH1\n , (uint32_t)LPC_GPDMACH2\n , (uint32_t)LPC_GPDMACH3\n , (uint32_t)LPC_GPDMACH4\n , (uint32_t)LPC_GPDMACH5\n , (uint32_t)LPC_GPDMACH6\n , (uint32_t)LPC_GPDMACH7\n };\n return lut[channel & 0xFF];\n}\n\nuint8_t\nMODDMA::LUTPerBurst(int n)\n{\n const uint8_t lut[] = {\n (uint8_t)_4 // SSP0 Tx \n , (uint8_t)_4 // SSP0 Rx\n , (uint8_t)_4 // SSP1 Tx\n , (uint8_t)_4 // SSP1 Rx\n , (uint8_t)_1 // ADC\n , (uint8_t)_32 // I2S channel 0\n , (uint8_t)_32 // I2S channel 1\n , (uint8_t)_1 // DAC\n , (uint8_t)_1 // UART0 Tx\n , (uint8_t)_1 // UART0 Rx\n , (uint8_t)_1 // UART1 Tx\n , (uint8_t)_1 // UART1 Rx\n , (uint8_t)_1 // UART2 Tx\n , (uint8_t)_1 // UART2 Rx\n , (uint8_t)_1 // UART3 Tx\n , (uint8_t)_1 // UART3 Rx\n , (uint8_t)_1 // MAT0.0\n , (uint8_t)_1 // MAT0.1\n , (uint8_t)_1 // MAT1.0\n , (uint8_t)_1 // MAT1.1\n , (uint8_t)_1 // MAT2.0\n , (uint8_t)_1 // MAT2.1\n , (uint8_t)_1 // MAT3.0\n , (uint8_t)_1 // MAT3.1\n };\n return lut[n & 0xFFF];\n}\n\nuint8_t\nMODDMA::LUTPerWid(int n)\n{\n const uint8_t lut[] = {\n (uint8_t)byte // SSP0 Tx\n , (uint8_t)byte // SSP0 Rx\n , (uint8_t)byte // SSP1 Tx\n , (uint8_t)byte // SSP1 Rx\n , (uint8_t)word // ADC\n , (uint8_t)word // I2S channel 0\n , (uint8_t)word // I2S channel 1\n , (uint8_t)word // DAC \n , (uint8_t)byte // UART0 Tx\n , (uint8_t)byte // UART0 Rx\n , (uint8_t)byte // UART1 Tx\n , (uint8_t)byte // UART1 Rx\n , (uint8_t)byte // UART2 Tx\n , (uint8_t)byte // UART2 Rx\n , (uint8_t)byte // UART3 Tx\n , (uint8_t)byte // UART3 Rx \n , (uint8_t)word // MAT0.0\n , (uint8_t)word // MAT0.1\n , (uint8_t)word // MAT1.0\n , (uint8_t)word // MAT1.1\n , (uint8_t)word // MAT2.0\n , (uint8_t)word // MAT2.1\n , (uint8_t)word // MAT3.0\n , (uint8_t)word // MAT3.1 \n };\n return lut[n & 0xFFF];\n}\n\n}; // namespace AjK ends\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/INIT.cpp", "content": "/*\n Copyright (c) 2010 Andy Kirkham\n \n Permission is hereby granted, free of charge, to any person obtaining a copy\n of this software and associated documentation files (the \"Software\"), to deal\n in the Software without restriction, including without limitation the rights\n to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n copies of the Software, and to permit persons to whom the Software is\n furnished to do so, subject to the following conditions:\n \n The above copyright notice and this permission notice shall be included in\n all copies or substantial portions of the Software.\n \n THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n THE SOFTWARE.\n*/\n\n#include \"MODDMA.h\"\n\nnamespace AjK {\n\nextern uint32_t oldDMAHandler;\nextern \"C\" void MODDMA_IRQHandler(void);\nextern class MODDMA *moddma_p;\n\nvoid\nMODDMA::init(bool isConstructorCalling, int Channels, int Tc, int Err)\n{\n if (isConstructorCalling) { \n if (LPC_SC->PCONP & (1UL << 29)) {\n if (LPC_GPDMA->DMACConfig & 1) {\n error(\"Only one instance of MODDMA can exist.\");\n }\n }\n LPC_SC->PCONP |= (1UL << 29);\n LPC_GPDMA->DMACConfig = 1;\n moddma_p = this;\n for (int i = 0; i < 8; i++) {\n setups[i] = (MODDMA_Config *)NULL;\n } \n }\n \n // Reset channel configuration register(s)\n if (Channels & 0x01) LPC_GPDMACH0->DMACCConfig = 0;\n if (Channels & 0x02) LPC_GPDMACH1->DMACCConfig = 0;\n if (Channels & 0x04) LPC_GPDMACH2->DMACCConfig = 0;\n if (Channels & 0x08) LPC_GPDMACH3->DMACCConfig = 0;\n if (Channels & 0x10) LPC_GPDMACH4->DMACCConfig = 0;\n if (Channels & 0x20) LPC_GPDMACH5->DMACCConfig = 0;\n if (Channels & 0x40) LPC_GPDMACH6->DMACCConfig = 0;\n if (Channels & 0x80) LPC_GPDMACH7->DMACCConfig = 0;\n\n /* Clear DMA interrupt and error flag */\n LPC_GPDMA->DMACIntTCClear = Tc;\n LPC_GPDMA->DMACIntErrClr = Err;\n \n if (isConstructorCalling) { \n oldDMAHandler = NVIC_GetVector(DMA_IRQn);\n NVIC_SetVector(DMA_IRQn, (uint32_t)MODDMA_IRQHandler);\n NVIC_EnableIRQ(DMA_IRQn);\n }\n}\n\n}; // namespace AjK ends\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/MODDMA.cpp", "content": "/*\n Copyright (c) 2010 Andy Kirkham\n \n Permission is hereby granted, free of charge, to any person obtaining a copy\n of this software and associated documentation files (the \"Software\"), to deal\n in the Software without restriction, including without limitation the rights\n to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n copies of the Software, and to permit persons to whom the Software is\n furnished to do so, subject to the following conditions:\n \n The above copyright notice and this permission notice shall be included in\n all copies or substantial portions of the Software.\n \n THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n THE SOFTWARE.\n*/\n#include \"iomacros.h\"\n#include \"MODDMA.h\"\n\nnamespace AjK {\n\n// Create a \"hook\" for our ISR to make callbacks. Set by init()\nclass MODDMA *moddma_p = (class MODDMA *)NULL;\n\nvoid\nMODDMA::Enable(CHANNELS ChannelNumber)\n{\n LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( ChannelNumber );\n pChannel->DMACCConfig |= _E;\n}\n\nbool\nMODDMA::Enabled(CHANNELS ChannelNumber)\n{\n LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( ChannelNumber ); \n return (bool)(pChannel->DMACCConfig & _E);\n}\n\nvoid\nMODDMA::Disable(CHANNELS ChannelNumber)\n{\n LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( ChannelNumber );\n pChannel->DMACCConfig &= ~(_E);\n}\n\nbool\nMODDMA::isActive(CHANNELS ChannelNumber)\n{\n LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( ChannelNumber );\n return (bool)( pChannel->DMACCConfig & CxConfig_A() ) ;\n}\n\nvoid \nMODDMA::haltChannel(CHANNELS ChannelNumber)\n{\n LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( ChannelNumber );\n pChannel->DMACCConfig |= CxConfig_H();\n}\n\nuint32_t \nMODDMA::getControl(CHANNELS ChannelNumber)\n{\n LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( ChannelNumber );\n return pChannel->DMACCControl;\n}\n\nuint32_t oldDMAHandler = 0;\ntypedef void (*MODDMA_FN)(void);\n\nextern \"C\" void MODDMA_IRQHandler(void) {\n uint32_t channel_mask;\n \n if (moddma_p == (class MODDMA *)NULL) {\n if (oldDMAHandler) {\n ((MODDMA_FN)oldDMAHandler)();\n return;\n }\n else {\n error(\"Interrupt without instance\");\n }\n }\n \n for (int channel_number = 0; channel_number < 8; channel_number++) {\n channel_mask = (1UL << channel_number);\n if (LPC_GPDMA->DMACIntStat & channel_mask) {\n if (LPC_GPDMA->DMACIntTCStat & channel_mask) {\n if (moddma_p->setups[channel_number] != (MODDMA_Config *)NULL) {\n moddma_p->setIrqProcessingChannel((MODDMA::CHANNELS)channel_number);\n moddma_p->setIrqType(MODDMA::TcIrq);\n moddma_p->setups[channel_number]->isrIntTCStat->call();\n moddma_p->isrIntTCStat.call();\n // The user callback should clear the IRQ. But if they forget\n // then the Mbed will lockup. So, check to see if the IRQ has\n // been dismissed, if not, we will dismiss it here.\n if (LPC_GPDMA->DMACIntTCStat & channel_mask) {\n LPC_GPDMA->DMACIntTCClear = channel_mask;\n }\n // If the user has left the channel enabled, disable it.\n // Note, we don't check Active here as it may block inside\n // an ISR, we just shut it down immediately. If the user\n // must wait for completion they should implement their\n // own ISR. But only disable if the LLI linked list register\n // is null otherwise we can crap out a series of transfers.\n if (moddma_p->Enabled( (MODDMA::CHANNELS)channel_number )) {\n if (moddma_p->lli( (MODDMA::CHANNELS)channel_number ) == 0 ) {\n moddma_p->Disable( (MODDMA::CHANNELS)channel_number ); \n }\n }\n } \n }\n \n if (LPC_GPDMA->DMACIntErrStat & channel_mask) {\n if (moddma_p->setups[channel_number] != (MODDMA_Config *)NULL) {\n moddma_p->setIrqProcessingChannel((MODDMA::CHANNELS)channel_number);\n moddma_p->setIrqType(MODDMA::ErrIrq);\n moddma_p->setups[channel_number]->isrIntErrStat->call();\n moddma_p->isrIntErrStat.call();\n // The user callback should clear the IRQ. But if they forget\n // then the Mbed will lockup. So, check to see if the IRQ has\n // been dismissed, if not, we will dismiss it here.\n if (LPC_GPDMA->DMACIntErrStat & channel_mask) {\n LPC_GPDMA->DMACIntErrClr = channel_mask;\n }\n // If the user has left the channel enabled, disable it.\n // Not, we don't check Active here as it may block inside\n // an ISR, we just shut it down immediately. If the user\n // must wait for completion they should implement their\n // own ISR. But only disable if the LLI linked list register\n // is null otherwise we can crap out a series of transfers.\n if (moddma_p->Enabled( (MODDMA::CHANNELS)channel_number )) {\n if (moddma_p->lli( (MODDMA::CHANNELS)channel_number ) == 0 ) {\n moddma_p->Disable( (MODDMA::CHANNELS)channel_number ); \n }\n }\n } \n }\n }\n }\n \n /* IRQ should be handled by now, check to make sure. */\n if (LPC_GPDMA->DMACIntStat) {\n ((MODDMA_FN)oldDMAHandler)();\n LPC_GPDMA->DMACIntTCClear = (uint32_t)0xFF; /* If not, clear anyway! */\n }\n if (LPC_GPDMA->DMACIntErrStat) {\n ((MODDMA_FN)oldDMAHandler)();\n LPC_GPDMA->DMACIntErrClr = (uint32_t)0xFF; /* If not, clear anyway! */\n }\n}\n\n}; // namespace AjK ends\n\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/MODDMA.h", "content": "/*\n Copyright (c) 2010 Andy Kirkham\n \n Permission is hereby granted, free of charge, to any person obtaining a copy\n of this software and associated documentation files (the \"Software\"), to deal\n in the Software without restriction, including without limitation the rights\n to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n copies of the Software, and to permit persons to whom the Software is\n furnished to do so, subject to the following conditions:\n \n The above copyright notice and this permission notice shall be included in\n all copies or substantial portions of the Software.\n \n THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n THE SOFTWARE.\n \n @file MODDMA.h \n @purpose Adds DMA controller and multiple transfer configurations\n @version see ChangeLog.c\n @date Nov 2010\n @author Andy Kirkham \n*/\n\n#ifndef MODDMA_H\n#define MODDMA_H\n\n/** @defgroup API The MODDMA API */\n/** @defgroup MISC Misc MODSERIAL functions */\n/** @defgroup INTERNALS MODSERIAL Internals */\n\n#include \"mbed.h\"\n#include \"iomacros.h\"\n\nnamespace AjK {\n\n/**\n * @brief The MODDMA configuration system\n * @author Andy Kirkham\n * @see http://mbed.org/cookbook/MODDMA_Config\n * @see MODDMA\n * @see API \n *\n * MODDMA_Config defines a configuration that can be passed to the MODDMA controller\n * instance to perform a GPDMA data transfer.\n */\nclass MODDMA_Config {\nprotected:\n\n // *****************************************\n // From GPDMA by NXP MCU SW Application Team\n // *****************************************\n \n uint32_t ChannelNum; //!< DMA channel number, should be in range from 0 to 7. \n uint32_t TransferSize; //!< Length/Size of transfer \n uint32_t TransferWidth; //!< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_m2m only \n uint32_t SrcMemAddr; //!< Physical Src Addr, used in case TransferType is chosen as MODDMA::GPDMA_TRANSFERTYPE::m2m or MODDMA::GPDMA_TRANSFERTYPE::m2p \n uint32_t DstMemAddr; //!< Physical Destination Address, used in case TransferType is chosen as MODDMA::GPDMA_TRANSFERTYPE::m2m or MODDMA::GPDMA_TRANSFERTYPE::p2m \n uint32_t TransferType; //!< Transfer Type\n uint32_t SrcConn; //!< Peripheral Source Connection type, used in case TransferType is chosen as\n uint32_t DstConn; //!< Peripheral Destination Connection type, used in case TransferType is chosen as\n uint32_t DMALLI; //!< Linker List Item structure data address if there's no Linker List, set as '0'\n uint32_t DMACSync; //!< DMACSync if required.\n \n // Mbed specifics.\n\npublic: \n \n MODDMA_Config() {\n isrIntTCStat = new FunctionPointer;\n isrIntErrStat = new FunctionPointer;\n ChannelNum = 0xFFFF;\n TransferSize = 0;\n TransferWidth = 0;\n SrcMemAddr = 0;\n DstMemAddr = 0;\n TransferType = 0;\n SrcConn = 0;\n DstConn = 0;\n DMALLI = 0;\n DMACSync = 0;\n }\n \n ~MODDMA_Config() {\n delete(isrIntTCStat);\n delete(isrIntErrStat);\n }\n \n class MODDMA_Config * channelNum(uint32_t n) { ChannelNum = n & 0x7; return this; }\n class MODDMA_Config * transferSize(uint32_t n) { TransferSize = n; return this; }\n class MODDMA_Config * transferWidth(uint32_t n) { TransferWidth = n; return this; }\n class MODDMA_Config * srcMemAddr(uint32_t n) { SrcMemAddr = n; return this; }\n class MODDMA_Config * dstMemAddr(uint32_t n) { DstMemAddr = n; return this; }\n class MODDMA_Config * transferType(uint32_t n) { TransferType = n; return this; }\n class MODDMA_Config * srcConn(uint32_t n) { SrcConn = n; return this; }\n class MODDMA_Config * dstConn(uint32_t n) { DstConn = n; return this; }\n class MODDMA_Config * dmaLLI(uint32_t n) { DMALLI = n; return this; }\n class MODDMA_Config * dmacSync(uint32_t n) { DMACSync = n; return this; }\n \n uint32_t channelNum(void) { return ChannelNum; }\n uint32_t transferSize(void) { return TransferSize; }\n uint32_t transferWidth(void) { return TransferWidth; }\n uint32_t srcMemAddr(void) { return SrcMemAddr; }\n uint32_t dstMemAddr(void) { return DstMemAddr; }\n uint32_t transferType(void) { return TransferType; }\n uint32_t srcConn(void) { return SrcConn; }\n uint32_t dstConn(void) { return DstConn; }\n uint32_t dmaLLI(void) { return DMALLI; }\n uint32_t dmacSync(void) { return DMACSync; }\n \n /**\n * Attach a callback to the TC IRQ configuration.\n *\n * @param fptr A function pointer to call\n * @return this\n */\n class MODDMA_Config * attach_tc(void (*fptr)(void)) { \n isrIntTCStat->attach(fptr); \n return this;\n }\n \n /**\n * Attach a callback to the ERR IRQ configuration.\n *\n * @param fptr A function pointer to call\n * @return this\n */\n class MODDMA_Config * attach_err(void (*fptr)(void)) { \n isrIntErrStat->attach(fptr); \n return this;\n }\n \n /**\n * Attach a callback to the TC IRQ configuration.\n *\n * @param tptr A template pointer to the calling object\n * @param mptr A method pointer within the object to call.\n * @return this\n */\n template\n class MODDMA_Config * attach_tc(T* tptr, void (T::*mptr)(void)) { \n if((mptr != NULL) && (tptr != NULL)) {\n isrIntTCStat->attach(tptr, mptr);\n }\n return this;\n }\n \n /**\n * Attach a callback to the ERR IRQ configuration.\n *\n * @param tptr A template pointer to the calling object\n * @param mptr A method pointer within the object to call.\n * @return this\n */\n template\n class MODDMA_Config * attach_err(T* tptr, void (T::*mptr)(void)) { \n if((mptr != NULL) && (tptr != NULL)) {\n isrIntErrStat->attach(tptr, mptr);\n }\n return this;\n }\n FunctionPointer *isrIntTCStat; \n FunctionPointer *isrIntErrStat; \n};\n\n/**\n * @brief The MODDMA configuration system (linked list items)\n * @author Andy Kirkham\n * @see http://mbed.org/cookbook/MODDMA_Config\n * @see MODDMA\n * @see MODDMA_Config\n * @see API \n */\nclass MODDMA_LLI {\npublic:\n class MODDMA_LLI *srcAddr(uint32_t n) { SrcAddr = n; return this; }\n class MODDMA_LLI *dstAddr(uint32_t n) { DstAddr = n; return this; }\n class MODDMA_LLI *nextLLI(uint32_t n) { NextLLI = n; return this; }\n class MODDMA_LLI *control(uint32_t n) { Control = n; return this; }\n uint32_t srcAddr(void) { return SrcAddr; }\n uint32_t dstAddr(void) { return DstAddr; }\n uint32_t nextLLI(void) { return NextLLI; }\n uint32_t control(void) { return Control; }\n\n uint32_t SrcAddr; //!< Source Address \n uint32_t DstAddr; //!< Destination address \n uint32_t NextLLI; //!< Next LLI address, otherwise set to '0' \n uint32_t Control; //!< GPDMA Control of this LLI \n};\n\n\n\n /**\n * @brief MODDMA GPDMA Controller\n * @author Andy Kirkham\n * @see http://mbed.org/cookbook/MODDMA\n * @see example1.cpp\n * @see API \n *\n * MODDMA defines a GPDMA controller and multiple DMA configurations that allow for DMA\n * transfers from memory to memory, memory to peripheral or peripheral to memory.\n *\n * At the heart of the library is the MODDMA class that defines a single instance controller that\n * manages all the GPDMA hardware registers and interrupts. The controller can accept multiple\n * configurations that define the channel transfers. Each configuration specifies the source and \n * destination information and other associated parts to maintain the transfer process.\n *\n * Standard example:\n * @code\n * #include \"mbed.h\"\n * #include \"MODDMA.h\"\n *\n * DigitalOut led1(LED1);\n * Serial pc(USBTX, USBRX); // tx, rx\n * MODDMA dma;\n *\n * int main() {\n *\n * // Create a string buffer to send directly to a Uart/Serial\n * char s[] = \"***DMA*** ABCDEFGHIJKLMNOPQRSTUVWXYZ ***DMA***\";\n *\n * // Create a transfer configuarion\n * MODDMA_Config *config = new MODDMA_Config;\n *\n * // Provide a \"minimal\" setup for demo purposes.\n * config\n * ->channelNum ( MODDMA::Channel_0 ) // The DMA channel to use.\n * ->srcMemAddr ( (uint32_t) &s ) // A pointer to the buffer to send.\n * ->transferSize ( sizeof(s) ) // The size of that buffer.\n * ->transferType ( MODDMA::m2p ) // Source is memory, destination is peripheral\n * ->dstConn ( MODDMA::UART0_Tx ) // Specifically, peripheral is Uart0 TX (USBTX, USBRX)\n * ; // config end.\n *\n * // Pass the configuration to the MODDMA controller.\n * dma.Setup( config );\n *\n * // Enable the channel and begin transfer.\n * dma.Enable( config->channelNum() );\n *\n * while(1) {\n * led1 = !led1;\n * wait(0.25);\n * }\n * }\n * @endcode\n */\nclass MODDMA\n{\npublic:\n\n //! Channel definitions.\n enum CHANNELS {\n Channel_0 = 0 /*!< Channel 0 */ \n , Channel_1 /*!< Channel 1 */ \n , Channel_2 /*!< Channel 2 */ \n , Channel_3 /*!< Channel 3 */ \n , Channel_4 /*!< Channel 4 */ \n , Channel_5 /*!< Channel 5 */ \n , Channel_6 /*!< Channel 6 */ \n , Channel_7 /*!< Channel 7 */ \n };\n \n //! Interrupt callback types.\n enum IrqType_t {\n TcIrq = 0 /*!< Terminal Count interrupt */\n , ErrIrq /*!< Error interrupt */\n };\n \n //! Return status codes.\n enum Status {\n Ok = 0 /*!< Ok, suceeded */\n , Error = -1 /*!< General error */\n , ErrChInUse = -2 /*!< Specific error, channel in use */\n };\n \n //! DMA Connection number definitions \n enum GPDMA_CONNECTION {\n SSP0_Tx = 0UL /*!< SSP0 Tx */\n , SSP0_Rx = 1UL /*!< SSP0 Rx */\n , SSP1_Tx = 2UL /*!< SSP1 Tx */\n , SSP1_Rx = 3UL /*!< SSP1 Rx */\n , ADC = 4UL /*!< ADC */\n , I2S_Channel_0 = 5UL /*!< I2S channel 0 */\n , I2S_Channel_1 = 6UL /*!< I2S channel 1 */\n , DAC = 7UL /*!< DAC */\n , UART0_Tx = 8UL /*!< UART0 Tx */\n , UART0_Rx = 9UL /*!< UART0 Rx */\n , UART1_Tx = 10UL /*!< UART1 Tx */\n , UART1_Rx = 11UL /*!< UART1 Rx */\n , UART2_Tx = 12UL /*!< UART2 Tx */\n , UART2_Rx = 13UL /*!< UART2 Rx */\n , UART3_Tx = 14UL /*!< UART3 Tx */\n , UART3_Rx = 15UL /*!< UART3 Rx */\n , MAT0_0 = 16UL /*!< MAT0.0 */\n , MAT0_1 = 17UL /*!< MAT0.1 */\n , MAT1_0 = 18UL /*!< MAT1.0 */\n , MAT1_1 = 19UL /*!< MAT1.1 */\n , MAT2_0 = 20UL /**< MAT2.0 */\n , MAT2_1 = 21UL /*!< MAT2.1 */\n , MAT3_0 = 22UL /*!< MAT3.0 */\n , MAT3_1 = 23UL /*!< MAT3.1 */\n };\n\n //! GPDMA Transfer type definitions \n enum GPDMA_TRANSFERTYPE {\n m2m = 0UL /*!< Memory to memory - DMA control */\n , m2p = 1UL /*!< Memory to peripheral - DMA control */\n , p2m = 2UL /*!< Peripheral to memory - DMA control */\n , p2p = 3UL /*!< Src peripheral to dest peripheral - DMA control */ \n , g2m = 4UL /*!< Psuedo special case for reading \"peripheral GPIO\" that's memory mapped. */\n , m2g = 5UL /*!< Psuedo Special case for writing \"peripheral GPIO\" that's memory mapped. */ \n }; \n\n //! Burst size in Source and Destination definitions */\n enum GPDMA_BSIZE {\n _1 = 0UL /*!< Burst size = 1 */\n , _4 = 1UL /*!< Burst size = 4 */\n , _8 = 2UL /*!< Burst size = 8 */\n , _16 = 3UL /*!< Burst size = 16 */\n , _32 = 4UL /*!< Burst size = 32 */\n , _64 = 5UL /*!< Burst size = 64 */\n , _128 = 6UL /*!< Burst size = 128 */\n , _256 = 7UL /*!< Burst size = 256 */\n };\n \n //! Width in Src transfer width and Dest transfer width definitions */\n enum GPDMA_WIDTH {\n byte = 0UL /*!< Width = 1 byte */\n , halfword = 1UL /*!< Width = 2 bytes */\n , word = 2UL /*!< Width = 4 bytes */\n };\n \n //! DMA Request Select Mode definitions. */\n enum GPDMA_REQSEL {\n uart = 0UL /*!< UART TX/RX is selected */\n , timer = 1UL /*!< Timer match is selected */\n };\n\n //! GPDMA Control register bits.\n enum Config {\n _E = 1 /*!< DMA Controller enable */\n , _M = 2 /*!< AHB Master endianness configuration */\n }; \n\n //! GPDMA Channel config register bits.\n enum CConfig {\n _CE = (1UL << 0) /*!< Channel enable */\n , _IE = (1UL << 14) /*!< Interrupt error mask */\n , _ITC = (1UL << 15) /*!< Terminal count interrupt mask */\n , _L = (1UL << 16) /*!< Lock */\n , _A = (1UL << 17) /*!< Active */\n , _H = (1UL << 18) /*!< Halt */\n };\n \n /**\n * The MODDMA constructor is used to initialise the DMA controller object.\n */ \n MODDMA() { init(true); }\n \n /**\n * The MODDMA destructor.\n */ \n ~MODDMA() {}\n \n /**\n * Used to setup the DMA controller to prepare for a data transfer.\n *\n * @ingroup API\n * @param isConstructorCalling Set true when called from teh constructor\n * @param \n */\n void init(bool isConstructorCalling, int Channels = 0xFF, int Tc = 0xFF, int Err = 0xFF);\n \n /**\n * Used to setup and enable the DMA controller.\n *\n * @see Setup\n * @see Enable\n * @ingroup API\n * @param c A pointer to an instance of MODDMA_Config to setup.\n */\n uint32_t Prepare(MODDMA_Config *c) {\n uint32_t u = Setup(c);\n if (u) Enable(c);\n return u;\n }\n \n /**\n * Used to setup the DMA controller to prepare for a data transfer.\n *\n * @ingroup API\n * @param c A pointer to an instance of MODDMA_Config to setup.\n */\n uint32_t Setup(MODDMA_Config *c);\n \n /**\n * Enable and begin data transfer.\n *\n * @ingroup API\n * @param ChannelNumber Type CHANNELS, the channel number to enable\n */\n void Enable(CHANNELS ChannelNumber);\n \n /**\n * Enable and begin data transfer (overloaded function)\n *\n * @ingroup API\n * @param ChannelNumber Type uin32_t, the channel number to enable\n */\n void Enable(uint32_t ChannelNumber) { Enable((CHANNELS)(ChannelNumber & 0x7)); }\n \n /**\n * Enable and begin data transfer (overloaded function)\n *\n * @ingroup API\n * @param config A pointer to teh configuration\n */\n void Enable(MODDMA_Config *config) { Enable( config->channelNum() ); }\n \n \n /**\n * Disable a channel and end data transfer.\n *\n * @ingroup API\n * @param ChannelNumber Type CHANNELS, the channel number to enable\n */\n void Disable(CHANNELS ChannelNumber);\n \n /**\n * Disable a channel and end data transfer (overloaded function)\n *\n * @ingroup API\n * @param ChannelNumber Type uin32_t, the channel number to disable\n */\n void Disable(uint32_t ChannelNumber) { Disable((CHANNELS)(ChannelNumber & 0x7)); }\n \n /**\n * Is the specified channel enabled?\n *\n * @ingroup API\n * @param ChannelNumber Type CHANNELS, the channel number to test\n * @return bool true if enabled, false otherwise.\n */\n bool Enabled(CHANNELS ChannelNumber);\n \n /**\n * Is the specified channel enabled? (overloaded function)\n *\n * @ingroup API\n * @param ChannelNumber Type uin32_t, the channel number to test\n * @return bool true if enabled, false otherwise.\n */\n bool Enabled(uint32_t ChannelNumber) { return Enabled((CHANNELS)(ChannelNumber & 0x7)); }\n \n __INLINE uint32_t IntStat(uint32_t n) { return (1UL << n) & 0xFF; }\n __INLINE uint32_t IntTCStat_Ch(uint32_t n) { return (1UL << n) & 0xFF; }\n __INLINE uint32_t IntTCClear_Ch(uint32_t n) { return (1UL << n) & 0xFF; }\n __INLINE uint32_t IntErrStat_Ch(uint32_t n) { return (1UL << n) & 0xFF; }\n __INLINE uint32_t IntErrClr_Ch(uint32_t n) { return (1UL << n) & 0xFF; }\n __INLINE uint32_t RawIntErrStat_Ch(uint32_t n) { return (1UL << n) & 0xFF; }\n __INLINE uint32_t EnbldChns_Ch(uint32_t n) { return (1UL << n) & 0xFF; }\n __INLINE uint32_t SoftBReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }\n __INLINE uint32_t SoftSReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }\n __INLINE uint32_t SoftLBReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }\n __INLINE uint32_t SoftLSReq_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }\n __INLINE uint32_t Sync_Src(uint32_t n) { return (1UL << n) & 0xFFFF; }\n __INLINE uint32_t ReqSel_Input(uint32_t n) { return (1UL << (n - 8)) & 0xFF; }\n \n\n __INLINE uint32_t CxControl_TransferSize(uint32_t n) { return (n & 0xFFF) << 0; }\n __INLINE uint32_t CxControl_SBSize(uint32_t n) { return (n & 0x7) << 12; }\n __INLINE uint32_t CxControl_DBSize(uint32_t n) { return (n & 0x7) << 15; }\n __INLINE uint32_t CxControl_SWidth(uint32_t n) { return (n & 0x7) << 18; }\n __INLINE uint32_t CxControl_DWidth(uint32_t n) { return (n & 0x7) << 21; }\n __INLINE uint32_t CxControl_SI() { return (1UL << 26); }\n __INLINE uint32_t CxControl_DI() { return (1UL << 27); }\n __INLINE uint32_t CxControl_Prot1() { return (1UL << 28); }\n __INLINE uint32_t CxControl_Prot2() { return (1UL << 29); }\n __INLINE uint32_t CxControl_Prot3() { return (1UL << 30); }\n __INLINE uint32_t CxControl_I() { return (1UL << 31); }\n __INLINE uint32_t CxControl_E() { return (1UL << 0); }\n __INLINE uint32_t CxConfig_SrcPeripheral(uint32_t n) { return (n & 0x1F) << 1; }\n __INLINE uint32_t CxConfig_DestPeripheral(uint32_t n) { return (n & 0x1F) << 6; }\n __INLINE uint32_t CxConfig_TransferType(uint32_t n) { return (n & 0x7) << 11; }\n __INLINE uint32_t CxConfig_IE() { return (1UL << 14); }\n __INLINE uint32_t CxConfig_ITC() { return (1UL << 15); }\n __INLINE uint32_t CxConfig_L() { return (1UL << 16); }\n __INLINE uint32_t CxConfig_A() { return (1UL << 17); }\n __INLINE uint32_t CxConfig_H() { return (1UL << 18); }\n \n /**\n * A store for up to 8 (8 channels) of configurations.\n * @see MODDMA_Config\n */\n MODDMA_Config *setups[8];\n \n /**\n * Get a pointer to the current configuration the ISR is servicing.\n *\n * @ingroup API\n * @return MODDMA_Config * A pointer to the setup the ISR is currently servicing.\n */\n MODDMA_Config *getConfig(void) { return setups[IrqProcessingChannel]; }\n \n /**\n * Set which channel the ISR is currently servicing.\n *\n * *** USED INTERNALLY. DO NOT CALL FROM USER PROGRAMS ***\n *\n * Must be public so the extern \"C\" ISR can use it.\n */\n void setIrqProcessingChannel(CHANNELS n) { IrqProcessingChannel = n; }\n \n /**\n * Gets which channel the ISR is currently servicing.\n *\n * @ingroup API\n * @return CHANNELS The current channel the ISR is servicing.\n */\n CHANNELS irqProcessingChannel(void) { return IrqProcessingChannel; }\n \n /**\n * Sets which type of IRQ the ISR is making a callback for.\n *\n * *** USED INTERNALLY. DO NOT CALL FROM USER PROGRAMS ***\n *\n * Must be public so the extern \"C\" ISR can use it.\n */ \n void setIrqType(IrqType_t n) { IrqType = n; }\n \n /**\n * Get which type of IRQ the ISR is calling you about,\n * terminal count or error.\n */\n IrqType_t irqType(void) { return IrqType; }\n \n /**\n * Clear the interrupt after handling.\n *\n * @param CHANNELS The channel the IQR occured on.\n */\n void clearTcIrq(CHANNELS n) { LPC_GPDMA->DMACIntTCClear = (uint32_t)(1UL << n); } \n \n /**\n * Clear the interrupt the ISR is currently handing..\n */\n void clearTcIrq(void) { clearTcIrq( IrqProcessingChannel ); }\n \n /**\n * Clear the error interrupt after handling.\n *\n * @ingroup API\n * @param CHANNELS The channel the IQR occured on.\n */\n void clearErrIrq(CHANNELS n) { LPC_GPDMA->DMACIntTCClear = (uint32_t)(1UL << n); } \n \n /**\n * Clear the error interrupt the ISR is currently handing.\n * @ingroup API\n */\n void clearErrIrq(void) { clearErrIrq( IrqProcessingChannel ); }\n \n /**\n * Is the supplied channel currently active?\n *\n * @ingroup API\n * @param CHANNELS The channel to inquire about.\n * @return bool true if active, false otherwise.\n */ \n bool isActive(CHANNELS ChannelNumber);\n \n /**\n * Halt the supplied channel. \n *\n * @ingroup API\n * @param CHANNELS The channel to halt.\n */\n void haltChannel(CHANNELS ChannelNumber);\n \n /**\n * get a channels control register. \n *\n * @ingroup API\n * @param CHANNELS The channel to get the control register for.\n */\n uint32_t getControl(CHANNELS ChannelNumber);\n \n /**\n * Wait for channel transfer to complete and then halt.\n *\n * @ingroup API\n * @param CHANNELS The channel to wait for then halt.\n */\n void haltAndWaitChannelComplete(CHANNELS n) { haltChannel(n); while (isActive(n)); }\n \n /**\n * Attach a callback to the TC IRQ controller.\n *\n * @ingroup API\n * @param fptr A function pointer to call\n * @return this\n */\n void attach_tc(void (*fptr)(void)) { \n isrIntTCStat.attach(fptr); \n }\n \n /**\n * Attach a callback to the TC IRQ controller.\n *\n * @ingroup API\n * @param tptr A template pointer to the calling object\n * @param mptr A method pointer within the object to call.\n * @return this\n */\n template\n void attach_tc(T* tptr, void (T::*mptr)(void)) { \n if((mptr != NULL) && (tptr != NULL)) {\n isrIntTCStat.attach(tptr, mptr); \n } \n }\n \n /**\n * The MODDMA controllers terminal count interrupt callback.\n */\n FunctionPointer isrIntTCStat; \n \n /**\n * Attach a callback to the ERR IRQ controller.\n *\n * @ingroup API\n * @param fptr A function pointer to call\n * @return this\n */\n void attach_err(void (*fptr)(void)) { \n isrIntErrStat.attach(fptr); \n }\n \n /**\n * Attach a callback to the ERR IRQ controller.\n *\n * @ingroup API\n * @param tptr A template pointer to the calling object\n * @param mptr A method pointer within the object to call.\n * @return this\n */\n template\n void attach_err(T* tptr, void (T::*mptr)(void)) { \n if((mptr != NULL) && (tptr != NULL)) {\n isrIntErrStat.attach(tptr, mptr); \n }\n }\n \n /**\n * Get the Linked List index regsiter for the requested channel.\n *\n * @param channelNum The channel number.\n * @return uint32_t The value of the DMACCLLI register\n */\n uint32_t lli(CHANNELS ChannelNumber, MODDMA_LLI *set = 0) { \n LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( ChannelNumber & 0x7 );\n if (set) pChannel->DMACCLLI = (uint32_t)set;\n return pChannel->DMACCLLI; \n }\n \n /**\n * The MODDMA controllers error interrupt callback.\n */\n FunctionPointer isrIntErrStat; \n \n uint32_t Channel_p(int channel);\n \nprotected:\n \n // Data LUTs.\n uint32_t LUTPerAddr(int n);\n uint8_t LUTPerBurst(int n);\n uint8_t LUTPerWid(int n); \n //uint32_t Channel_p(int channel);\n \n CHANNELS IrqProcessingChannel;\n \n IrqType_t IrqType;\n};\n\n}; // namespace AjK ends.\n\nusing namespace AjK;\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/SETUP.cpp", "content": "/*\n Copyright (c) 2010 Andy Kirkham\n \n Permission is hereby granted, free of charge, to any person obtaining a copy\n of this software and associated documentation files (the \"Software\"), to deal\n in the Software without restriction, including without limitation the rights\n to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n copies of the Software, and to permit persons to whom the Software is\n furnished to do so, subject to the following conditions:\n \n The above copyright notice and this permission notice shall be included in\n all copies or substantial portions of the Software.\n \n THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n THE SOFTWARE.\n*/\n\n#include \"MODDMA.h\"\n\nnamespace AjK {\n\nuint32_t\nMODDMA::Setup(MODDMA_Config *config)\n{\n LPC_GPDMACH_TypeDef *pChannel = (LPC_GPDMACH_TypeDef *)Channel_p( config->channelNum() );\n \n setups[config->channelNum() & 0x7] = config;\n \n // Reset the Interrupt status\n LPC_GPDMA->DMACIntTCClear = IntTCClear_Ch( config->channelNum() );\n LPC_GPDMA->DMACIntErrClr = IntErrClr_Ch ( config->channelNum() );\n\n // Clear DMA configure\n pChannel->DMACCControl = 0x00;\n pChannel->DMACCConfig = 0x00;\n\n // Assign Linker List Item value \n pChannel->DMACCLLI = config->dmaLLI();\n\n // Set value to Channel Control Registers \n switch (config->transferType()) {\n \n // Memory to memory\n case m2m:\n // Assign physical source and destination address\n pChannel->DMACCSrcAddr = config->srcMemAddr();\n pChannel->DMACCDestAddr = config->dstMemAddr();\n pChannel->DMACCControl\n = CxControl_TransferSize(config->transferSize()) \n | CxControl_SBSize(_32) \n | CxControl_DBSize(_32) \n | CxControl_SWidth(config->transferWidth()) \n | CxControl_DWidth(config->transferWidth()) \n | CxControl_SI() \n | CxControl_DI() \n | CxControl_I();\n break;\n \n // Memory to peripheral\n case m2p:\n // Assign physical source\n pChannel->DMACCSrcAddr = config->srcMemAddr();\n // Assign peripheral destination address\n pChannel->DMACCDestAddr = (uint32_t)LUTPerAddr(config->dstConn());\n pChannel->DMACCControl\n = CxControl_TransferSize((uint32_t)config->transferSize()) \n | CxControl_SBSize((uint32_t)LUTPerBurst(config->dstConn())) \n | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn())) \n | CxControl_SWidth((uint32_t)LUTPerWid(config->dstConn())) \n | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn())) \n | CxControl_SI() \n | CxControl_I();\n break;\n \n // Peripheral to memory\n case p2m:\n // Assign peripheral source address\n pChannel->DMACCSrcAddr = (uint32_t)LUTPerAddr(config->srcConn());\n // Assign memory destination address\n pChannel->DMACCDestAddr = config->dstMemAddr();\n pChannel->DMACCControl\n = CxControl_TransferSize((uint32_t)config->transferSize()) \n | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn())) \n | CxControl_DBSize((uint32_t)LUTPerBurst(config->srcConn())) \n | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn())) \n | CxControl_DWidth((uint32_t)LUTPerWid(config->srcConn())) \n | CxControl_DI() \n | CxControl_I();\n break;\n \n // Peripheral to peripheral\n case p2p:\n // Assign peripheral source address\n pChannel->DMACCSrcAddr = (uint32_t)LUTPerAddr(config->srcConn());\n // Assign peripheral destination address\n pChannel->DMACCDestAddr = (uint32_t)LUTPerAddr(config->dstConn());\n pChannel->DMACCControl\n = CxControl_TransferSize((uint32_t)config->transferSize()) \n | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn())) \n | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn())) \n | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn())) \n | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn())) \n | CxControl_I();\n break;\n \n // GPIO to memory\n case g2m:\n // Assign GPIO source address\n pChannel->DMACCSrcAddr = config->srcMemAddr();\n // Assign memory destination address\n pChannel->DMACCDestAddr = config->dstMemAddr();\n pChannel->DMACCControl\n = CxControl_TransferSize((uint32_t)config->transferSize()) \n | CxControl_SBSize((uint32_t)LUTPerBurst(config->srcConn())) \n | CxControl_DBSize((uint32_t)LUTPerBurst(config->srcConn())) \n | CxControl_SWidth((uint32_t)LUTPerWid(config->srcConn())) \n | CxControl_DWidth((uint32_t)LUTPerWid(config->srcConn())) \n | CxControl_DI() \n | CxControl_I();\n break;\n \n // Memory to GPIO\n case m2g:\n // Assign physical source\n pChannel->DMACCSrcAddr = config->srcMemAddr();\n // Assign peripheral destination address\n pChannel->DMACCDestAddr = config->dstMemAddr();\n pChannel->DMACCControl\n = CxControl_TransferSize((uint32_t)config->transferSize()) \n | CxControl_SBSize((uint32_t)LUTPerBurst(config->dstConn())) \n | CxControl_DBSize((uint32_t)LUTPerBurst(config->dstConn())) \n | CxControl_SWidth((uint32_t)LUTPerWid(config->dstConn())) \n | CxControl_DWidth((uint32_t)LUTPerWid(config->dstConn())) \n | CxControl_SI() \n | CxControl_I();\n break;\n \n // Do not support any more transfer type, return ERROR\n default:\n return 0;\n }\n\n // Re-Configure DMA Request Select for source peripheral \n if (config->srcConn() > 15) {\n LPC_SC->DMAREQSEL |= (1 << (config->srcConn() - 16));\n } \n else {\n LPC_SC->DMAREQSEL &= ~(1 << (config->srcConn() - 8));\n }\n\n // Re-Configure DMA Request Select for destination peripheral\n if (config->dstConn() > 15) {\n LPC_SC->DMAREQSEL |= (1 << (config->dstConn() - 16));\n } \n else {\n LPC_SC->DMAREQSEL &= ~(1 << (config->dstConn() - 8));\n }\n\n // Enable DMA channels, little endian \n LPC_GPDMA->DMACConfig = _E;\n while (!(LPC_GPDMA->DMACConfig & _E));\n\n // Calculate absolute value for Connection number\n uint32_t tmp1 = config->srcConn(); tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1);\n uint32_t tmp2 = config->dstConn(); tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2);\n\n if (config->dmacSync()) {\n uint32_t tmp3 = config->dmacSync(); tmp3 = ((tmp3 > 15) ? (tmp3 - 8) : tmp3);\n LPC_GPDMA->DMACSync |= Sync_Src( tmp3 );\n }\n \n uint32_t tfer_type = (uint32_t)config->transferType();\n if (tfer_type == g2m || tfer_type == m2g) {\n tfer_type -= 2; // Adjust psuedo transferType to a real transferType.\n }\n \n // Configure DMA Channel, enable Error Counter and Terminate counter\n pChannel->DMACCConfig \n = CxConfig_IE() \n | CxConfig_ITC() \n | CxConfig_TransferType(tfer_type) \n | CxConfig_SrcPeripheral(tmp1) \n | CxConfig_DestPeripheral(tmp2);\n\n return pChannel->DMACCControl;\n}\n\n}; // namespace AjK ends\n\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/example1.h", "content": "#include \"mbed.h\"\n#include \"MODDMA.h\"\n#include \"MODSERIAL.h\"\n\nDigitalOut led1(LED1);\nDigitalOut led2(LED2);\nDigitalOut led3(LED3);\nDigitalOut led4(LED4);\nMODDMA dma;\nMODSERIAL pc(USBTX, USBRX);\n\n// Function prototypes for IRQ callbacks.\n// See definitions following main() below.\nvoid dmaTCCallback(void);\nvoid dmaERRCallback(void);\nvoid TC0_callback(void);\nvoid ERR0_callback(void);\n\nint main() {\n char s[] = \"**DMA** ABCDEFGHIJKLMNOPQRSTUVWXYZ **DMA**\";\n \n pc.baud(PC_BAUD);\n \n dma.attach_tc( &dmaTCCallback );\n dma.attach_err( &dmaERRCallback );\n \n MODDMA_Config *config = new MODDMA_Config;\n config\n ->channelNum ( MODDMA::Channel_0 )\n ->srcMemAddr ( (uint32_t) &s )\n ->dstMemAddr ( 0 )\n ->transferSize ( sizeof(s) )\n ->transferType ( MODDMA::m2p )\n ->transferWidth ( 0 )\n ->srcConn ( 0 )\n ->dstConn ( MODDMA::UART0_Tx )\n ->dmaLLI ( 0 )\n ->attach_tc ( &TC0_callback )\n ->attach_err ( &ERR0_callback )\n ; // config end\n \n // Setup the configuration.\n dma.Setup(config);\n \n //dma.Enable( MODDMA::Channel_0 );\n //dma.Enable( config->channelNum() );\n dma.Enable( config );\n \n while (1) {\n led1 = !led1;\n wait(0.25); \n }\n}\n\n// Main controller TC IRQ callback\nvoid dmaTCCallback(void) {\n led2 = 1;\n}\n\n// Main controller ERR IRQ callback\nvoid dmaERRCallback(void) {\n error(\"Oh no! My Mbed exploded! :( Only kidding, find the problem\");\n}\n\n// Configuration callback on TC\nvoid TC0_callback(void) {\n MODDMA_Config *config = dma.getConfig();\n dma.haltAndWaitChannelComplete( (MODDMA::CHANNELS)config->channelNum());\n dma.Disable( (MODDMA::CHANNELS)config->channelNum() );\n \n // Configurations have two IRQ callbacks for TC and Err so you \n // know which you are processing. However, if you want to use \n // a single callback function you can tell what type of IRQ \n // is being processed thus:-\n if (dma.irqType() == MODDMA::TcIrq) {\n led3 = 1;\n dma.clearTcIrq();\n }\n if (dma.irqType() == MODDMA::ErrIrq) {\n led4 = 1;\n dma.clearErrIrq();\n }\n}\n\n// Configuration cakllback on Error\nvoid ERR0_callback(void) {\n error(\"Oh no! My Mbed exploded! :( Only kidding, find the problem\");\n}\n\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/example2.h", "content": "/*\n * This example was provided to support Mbed forum thread:-\n * http://mbed.org/forum/mbed/topic/1798\n */\n \n#include \"mbed.h\"\n#include \"MODDMA.h\"\n\n#define SAMPLE_BUFFER_LENGTH 32\n\nDigitalOut led1(LED1);\nDigitalOut led2(LED2);\n\nMODDMA dma;\nSerial pc(USBTX, USBRX);\n\n// ISR set's this when transfer complete.\nbool dmaTransferComplete = false;\n\n// Function prototypes for IRQ callbacks.\n// See definitions following main() below.\nvoid TC0_callback(void);\nvoid ERR0_callback(void);\n\nint main() {\n\n // Create a buffer to hold the ADC samples and clear it.\n // Note, we are going to sample two ADC inputs so they\n // end up in this buffer \"interleaved\". So you will want\n // a buffer twice this size to a real life given sample\n // frequency. See the printf() output for details.\n uint32_t adcInputBuffer[SAMPLE_BUFFER_LENGTH]; \n memset(adcInputBuffer, 0, sizeof(adcInputBuffer));\n \n // We use the ADC irq to trigger DMA and the manual says\n // that in this case the NVIC for ADC must be disabled.\n NVIC_DisableIRQ(ADC_IRQn);\n \n // Power up the ADC and set PCLK\n LPC_SC->PCONP |= (1UL << 12);\n LPC_SC->PCLKSEL0 &= ~(3UL << 24); // PCLK = CCLK/4 96M/4 = 24MHz\n \n // Enable the ADC, 12MHz, ADC0.0 & .1\n LPC_ADC->ADCR = (1UL << 21) | (1UL << 8) | (3UL << 0); \n \n // Set the pin functions to ADC\n LPC_PINCON->PINSEL1 &= ~(3UL << 14); /* P0.23, Mbed p15. */\n LPC_PINCON->PINSEL1 |= (1UL << 14);\n LPC_PINCON->PINSEL1 &= ~(3UL << 16); /* P0.24, Mbed p16. */\n LPC_PINCON->PINSEL1 |= (1UL << 16);\n \n // Setup the serial port to print out results.\n pc.baud(115200);\n pc.printf(\"ADC with DMA example\\n\");\n pc.printf(\"====================\\n\");\n \n // Prepare an ADC configuration.\n MODDMA_Config *conf = new MODDMA_Config;\n conf\n ->channelNum ( MODDMA::Channel_0 )\n ->srcMemAddr ( 0 )\n ->dstMemAddr ( (uint32_t)adcInputBuffer )\n ->transferSize ( SAMPLE_BUFFER_LENGTH )\n ->transferType ( MODDMA::p2m )\n ->transferWidth ( MODDMA::word )\n ->srcConn ( MODDMA::ADC )\n ->dstConn ( 0 )\n ->dmaLLI ( 0 )\n ->attach_tc ( &TC0_callback )\n ->attach_err ( &ERR0_callback )\n ; // end conf.\n \n // Prepare configuration.\n dma.Setup( conf );\n \n // Enable configuration.\n dma.Enable( conf );\n \n // Enable ADC irq flag (to DMA).\n // Note, don't set the individual flags,\n // just set the global flag.\n LPC_ADC->ADINTEN = 0x100;\n\n // Enable burst mode on inputs 0 and 1.\n LPC_ADC->ADCR |= (1UL << 16); \n \n while (1) {\n // When transfer complete do this block.\n if (dmaTransferComplete) {\n delete conf; // No memory leaks, delete the configuration.\n dmaTransferComplete = false;\n for (int i = 0; i < SAMPLE_BUFFER_LENGTH; i++) {\n int channel = (adcInputBuffer[i] >> 24) & 0x7;\n int iVal = (adcInputBuffer[i] >> 4) & 0xFFF;\n double fVal = 3.3 * (double)((double)iVal) / ((double)0x1000); // scale to 0v to 3.3v\n pc.printf(\"Array index %02d : ADC input channel %d = 0x%03x %01.3f volts\\n\", i, channel, iVal, fVal); \n }\n }\n \n // Just flash LED1 for something to do.\n led1 = !led1;\n wait(0.25); \n }\n}\n\n// Configuration callback on TC\nvoid TC0_callback(void) {\n \n MODDMA_Config *config = dma.getConfig();\n \n // Disbale burst mode and switch off the IRQ flag.\n LPC_ADC->ADCR &= ~(1UL << 16);\n LPC_ADC->ADINTEN = 0; \n \n // Finish the DMA cycle by shutting down the channel.\n dma.haltAndWaitChannelComplete( (MODDMA::CHANNELS)config->channelNum());\n dma.Disable( (MODDMA::CHANNELS)config->channelNum() );\n \n // Tell main() while(1) loop to print the results.\n dmaTransferComplete = true; \n \n // Switch on LED2 to show transfer complete.\n led2 = 1; \n \n // Clear DMA IRQ flags.\n if (dma.irqType() == MODDMA::TcIrq) dma.clearTcIrq(); \n if (dma.irqType() == MODDMA::ErrIrq) dma.clearErrIrq();\n}\n\n// Configuration callback on Error\nvoid ERR0_callback(void) {\n // Switch off burst conversions.\n LPC_ADC->ADCR |= ~(1UL << 16);\n LPC_ADC->ADINTEN = 0;\n error(\"Oh no! My Mbed EXPLODED! :( Only kidding, go find the problem\");\n}\n\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/example3.h", "content": "/*\n * Demonstrates capturing the GPIO P0.4 to P0.7 \"nibble\" to memory \n * using GPDMA. The transfers from port pins to memory buffer are\n * triggered using Timer1 MAT1.0 match compare.\n *\n * In this example all inputs have pullups. So with nothing connected\n * the P0.4/7 reads as 0xF. Connecting a wire from one or more of the four \n * inputs to ground will show up in the captured buffer sequence.\n */\n \n#include \"mbed.h\"\n#include \"MODDMA.h\"\n#include \"iomacros.h\" // within MODDMA library.\n\n// How long between grabbing GPIO FIO0PIN register.\n// Value is in microseconds. (500000 is half a second).\n#define SAMPLE_PERIOD 500000\n\n#define NUM_OF_SAMPLES 5\n\nSerial pc(USBTX, USBRX);\n\nDigitalOut led1(LED1);\nDigitalOut led2(LED2);\nDigitalOut led3(LED3);\n\nuint32_t buffer[NUM_OF_SAMPLES];\n\nbool dmaTransferComplete;\n\nMODDMA dma;\nMODDMA_Config *conf;\n\nvoid TC0_callback(void);\nvoid ERR0_callback(void);\n\nint main() {\n volatile int life_counter = 0;\n \n // Macros defined in iomacros.h, saves messing with DigitalIn\n p30_AS_INPUT; p30_MODE( PIN_PULLUP ); // P0.4\n p29_AS_INPUT; p29_MODE( PIN_PULLUP ); // P0.5\n p8_AS_INPUT; p8_MODE( PIN_PULLUP ); // P0.6\n p7_AS_INPUT; p7_MODE( PIN_PULLUP ); // P0.7\n \n // Clear the buffer.\n memset(buffer, 0, sizeof(buffer));\n \n // Setup the serial port to print out results.\n pc.baud(115200);\n pc.printf(\"Starting up...\\n\");\n \n // Set-up timer1 as a periodic timer.\n LPC_SC->PCONP |= (1UL << 2); // TIM1 On\n LPC_SC->PCLKSEL0 |= (3UL << 4); // CCLK/8 = 12MHz\n LPC_TIM1->PR = 11; // TC clocks at 1MHz.\n LPC_TIM1->MCR = 2; // Reset TCR to zero on match.\n LPC_TIM1->MR0 = SAMPLE_PERIOD;\n \n // Prepare the GPDMA system.\n conf = new MODDMA_Config;\n conf\n ->channelNum ( MODDMA::Channel_0 )\n ->srcMemAddr ( (uint32_t)&LPC_GPIO0->FIOPIN )\n ->dstMemAddr ( (uint32_t)&buffer[0] )\n ->transferSize ( NUM_OF_SAMPLES )\n ->transferType ( MODDMA::g2m ) // pseudo transfer code MODDMA understands.\n ->transferWidth ( MODDMA::word )\n ->srcConn ( MODDMA::MAT1_0 )\n ->dmacSync ( MODDMA::MAT1_0 ) \n ->attach_tc ( TC0_callback )\n ->attach_err ( ERR0_callback )\n ; // end conf.\n \n // Prepare configuration.\n if (!dma.Setup( conf )) {\n error(\"Doh!\");\n }\n \n // Enable GPDMA to be ready for the TIM1 \"ticks\". \n dma.Enable( conf );\n \n // Begin.\n LPC_TIM1->TCR = 1;\n \n while (1) { \n if (life_counter++ > 1000000) {\n led1 = !led1; // Show some sort of life.\n life_counter = 0;\n }\n \n if (dmaTransferComplete) {\n dmaTransferComplete = false;\n for (int i = 0; i < NUM_OF_SAMPLES; i++) {\n int val = (buffer[i] >> 4) & 0xF; \n pc.printf(\"Buffer index %d = 0x%x\\n\", i, val);\n }\n pc.printf(\"Done.\\n\");\n \n // Schedule another grab.\n if (dma.Setup( conf )) { \n dma.Enable( conf ); \n } \n }\n } \n}\n\n// Configuration callback on TC\nvoid TC0_callback(void) {\n \n // Just show sample sequence grab complete.\n led3 = !led3; \n \n // Get configuration pointer.\n MODDMA_Config *config = dma.getConfig();\n \n // Finish the DMA cycle by shutting down the channel.\n dma.Disable( (MODDMA::CHANNELS)config->channelNum() );\n \n // Tell main() while(1) loop to print the results.\n dmaTransferComplete = true; \n \n // Clear DMA IRQ flags.\n if (dma.irqType() == MODDMA::TcIrq) dma.clearTcIrq(); \n if (dma.irqType() == MODDMA::ErrIrq) dma.clearErrIrq(); \n}\n\n// Configuration callback on Error\nvoid ERR0_callback(void) {\n error(\"Oh no! My Mbed EXPLODED! :( Only kidding, go find the problem\");\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/example4.h", "content": "/*\n * Demonstrates sending a buffer repeatedly to the DAC using DMA.\n * Connect an oscilloscope to Mbed pin 18. This example doesn't\n * output anything else (nothing on any serial ports).\n */\n#include \"mbed.h\"\n#include \"MODDMA.h\"\n\n// Make the buffer size match the number of degrees\n// in a circle since we are going to output a sinewave.\n#define BUFFER_SIZE 360\n\n// Set DAC output power mode.\n#define DAC_POWER_MODE (1 << 16)\n\nDigitalOut led1(LED1);\nDigitalOut led3(LED3);\nDigitalOut led4(LED4);\n\nint buffer[2][BUFFER_SIZE];\n\nAnalogOut signal(p18);\n\nMODDMA dma;\nMODDMA_Config *conf0, *conf1;\n\nvoid TC0_callback(void);\nvoid ERR0_callback(void);\n\nvoid TC1_callback(void);\nvoid ERR1_callback(void);\n\nint main() {\n volatile int life_counter = 0;\n \n // Create a sinewave buffer for testing.\n for (int i = 0; i <= 90; i++) buffer[0][i] = (512 * sin(3.14159/180.0 * i)) + 512; \n for (int i = 91; i <= 180; i++) buffer[0][i] = buffer[0][180 - i];\n for (int i = 181; i <= 270; i++) buffer[0][i] = 512 - (buffer[0][i - 180] - 512);\n for (int i = 271; i < 360; i++) buffer[0][i] = 512 - (buffer[0][360 - i] - 512);\n \n // Adjust the sinewave buffer for use with DAC hardware.\n for (int i = 0; i < 360; i++) {\n buffer[0][i] = DAC_POWER_MODE | ((buffer[0][i] << 6) & 0xFFC0);\n buffer[1][i] = buffer[0][i]; // Just create a copy of buffer0 to continue sinewave.\n }\n \n // Prepare the GPDMA system for buffer0.\n conf0 = new MODDMA_Config;\n conf0\n ->channelNum ( MODDMA::Channel_0 )\n ->srcMemAddr ( (uint32_t) &buffer[0] )\n ->dstMemAddr ( MODDMA::DAC )\n ->transferSize ( 360 )\n ->transferType ( MODDMA::m2p )\n ->dstConn ( MODDMA::DAC )\n ->attach_tc ( &TC0_callback )\n ->attach_err ( &ERR0_callback ) \n ; // config end\n \n \n // Prepare the GPDMA system for buffer1.\n conf1 = new MODDMA_Config;\n conf1\n ->channelNum ( MODDMA::Channel_1 )\n ->srcMemAddr ( (uint32_t) &buffer[1] )\n ->dstMemAddr ( MODDMA::DAC )\n ->transferSize ( 360 )\n ->transferType ( MODDMA::m2p )\n ->dstConn ( MODDMA::DAC )\n ->attach_tc ( &TC1_callback )\n ->attach_err ( &ERR1_callback ) \n ; // config end\n\n \n // Calculating the transfer frequency:\n // By default, the Mbed library sets the PCLK_DAC clock value\n // to 24MHz. One complete sinewave cycle in each buffer is 360\n // points long. So, for a 1Hz wave we would need to transfer 360\n // values per second. That would be 24000000/360 which is approx\n // 66,666. But that's no good! The count val is only 16bits in size\n // so bare this in mind. If you need to go slower you will need to\n // alter PCLK_DAC from CCLK/4 to CCLK/8.\n // For our demo we are going to have the sinewave run at 1kHz.\n // That's 24000000/360000 which is approx 66. Experimentation\n // however showed 65 to get closer to 1kHz (on my Mbed and scope \n // at least).\n LPC_DAC->DACCNTVAL = 65; // 6500 for 10Hz\n\n // Prepare first configuration.\n if (!dma.Prepare( conf0 )) {\n error(\"Doh!\");\n }\n \n // Begin (enable DMA and counter). Note, don't enable\n // DBLBUF_ENA as we are using DMA double buffering.\n LPC_DAC->DACCTRL |= (3UL << 2);\n \n while (1) { \n // There's not a lot to do as DMA and interrupts are\n // now handling the buffer transfers. So we'll just\n // flash led1 to show the Mbed is alive and kicking.\n if (life_counter++ > 1000000) {\n led1 = !led1; // Show some sort of life.\n life_counter = 0;\n }\n } \n}\n\n// Configuration callback on TC\nvoid TC0_callback(void) {\n \n // Just show sending buffer0 complete.\n led3 = !led3; \n \n // Get configuration pointer.\n MODDMA_Config *config = dma.getConfig();\n \n // Finish the DMA cycle by shutting down the channel.\n dma.Disable( (MODDMA::CHANNELS)config->channelNum() );\n \n // Swap to buffer1\n dma.Prepare( conf1 );\n\n // Clear DMA IRQ flags.\n if (dma.irqType() == MODDMA::TcIrq) dma.clearTcIrq(); \n}\n\n// Configuration callback on Error\nvoid ERR0_callback(void) {\n error(\"Oh no! My Mbed EXPLODED! :( Only kidding, go find the problem\");\n}\n\n// Configuration callback on TC\nvoid TC1_callback(void) {\n \n // Just show sending buffer1 complete.\n led4 = !led4; \n \n // Get configuration pointer.\n MODDMA_Config *config = dma.getConfig();\n \n // Finish the DMA cycle by shutting down the channel.\n dma.Disable( (MODDMA::CHANNELS)config->channelNum() );\n \n // Swap to buffer0\n dma.Prepare( conf0 );\n \n // Clear DMA IRQ flags.\n if (dma.irqType() == MODDMA::TcIrq) dma.clearTcIrq(); \n}\n\n// Configuration callback on Error\nvoid ERR1_callback(void) {\n error(\"Oh no! My Mbed EXPLODED! :( Only kidding, go find the problem\");\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA/iomacros.h", "content": "/*\n Copyright (c) 2011 Andy Kirkham\n \n Permission is hereby granted, free of charge, to any person obtaining a copy\n of this software and associated documentation files (the \"Software\"), to deal\n in the Software without restriction, including without limitation the rights\n to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n copies of the Software, and to permit persons to whom the Software is\n furnished to do so, subject to the following conditions:\n \n The above copyright notice and this permission notice shall be included in\n all copies or substantial portions of the Software.\n \n THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\n AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n THE SOFTWARE.\n*/\n\n#ifndef IOMACROS_H\n#define IOMACROS_H\n\n#ifndef __LPC17xx_H__\n#include \"LPC17xx.h\"\n#endif\n\n#define PIN_PULLUP 0UL\n#define PIN_REPEAT 1UL\n#define PIN_NONE 2UL\n#define PIN_PULLDOWN 3UL\n\n/* p5 is P0.9 */\n#define p5_SEL_MASK ~(3UL << 18)\n#define p5_SET_MASK (1UL << 9)\n#define p5_CLR_MASK ~(p5_SET_MASK)\n#define p5_AS_OUTPUT LPC_PINCON->PINSEL0&=p5_SEL_MASK;LPC_GPIO0->FIODIR|=p5_SET_MASK\n#define p5_AS_INPUT LPC_GPIO0->FIOMASK &= p5_CLR_MASK; \n#define p5_SET LPC_GPIO0->FIOSET = p5_SET_MASK\n#define p5_CLR LPC_GPIO0->FIOCLR = p5_SET_MASK\n#define p5_IS_SET (bool)(LPC_GPIO0->FIOPIN & p5_SET_MASK)\n#define p5_IS_CLR !(p5_IS_SET)\n#define p5_MODE(x) LPC_PINCON->PINMODE0&=p5_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<18)\n\n/* p6 is P0.8 */\n#define p6_SEL_MASK ~(3UL << 16)\n#define p6_SET_MASK (1UL << 8)\n#define p6_CLR_MASK ~(p6_SET_MASK)\n#define p6_AS_OUTPUT LPC_PINCON->PINSEL0&=p6_SEL_MASK;LPC_GPIO0->FIODIR|=p6-SET_MASK\n#define p6_AS_INPUT LPC_GPIO0->FIOMASK &= p6_CLR_MASK; \n#define p6_SET LPC_GPIO0->FIOSET = p6_SET_MASK\n#define p6_CLR LPC_GPIO0->FIOCLR = p6_SET_MASK\n#define p6_IS_SET (bool)(LPC_GPIO0->FIOPIN & p6_SET_MASK)\n#define p6_IS_CLR !(p6_IS_SET)\n#define p6_MODE(x) LPC_PINCON->PINMODE0&=p6_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<16) \n\n/* p7 is P0.7 */\n#define p7_SEL_MASK ~(3UL << 14)\n#define p7_SET_MASK (1UL << 7)\n#define p7_CLR_MASK ~(p7_SET_MASK)\n#define p7_AS_OUTPUT LPC_PINCON->PINSEL0&=p7_SEL_MASK;LPC_GPIO0->FIODIR|=p7_SET_MASK\n#define p7_AS_INPUT LPC_GPIO0->FIOMASK &= p7_CLR_MASK; \n#define p7_SET LPC_GPIO0->FIOSET = p7_SET_MASK\n#define p7_CLR LPC_GPIO0->FIOCLR = p7_SET_MASK\n#define p7_IS_SET (bool)(LPC_GPIO0->FIOPIN & p7_SET_MASK)\n#define p7_IS_CLR !(p7_IS_SET)\n#define p7_MODE(x) LPC_PINCON->PINMODE0&=p7_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<14) \n\n/* p8 is P0.6 */\n#define p8_SEL_MASK ~(3UL << 12)\n#define p8_SET_MASK (1UL << 6)\n#define p8_CLR_MASK ~(p8_SET_MASK)\n#define p8_AS_OUTPUT LPC_PINCON->PINSEL0&=p8_SEL_MASK;LPC_GPIO0->FIODIR|=p8_SET_MASK\n#define p8_AS_INPUT LPC_GPIO0->FIOMASK &= p8_CLR_MASK; \n#define p8_SET LPC_GPIO0->FIOSET = p8_SET_MASK\n#define p8_CLR LPC_GPIO0->FIOCLR = p8_SET_MASK\n#define p8_IS_SET (bool)(LPC_GPIO0->FIOPIN & p8_SET_MASK)\n#define p8_IS_CLR !(p8_IS_SET)\n#define p8_MODE(x) LPC_PINCON->PINMODE0&=p8_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<12) \n\n/* p9 is P0.0 */\n#define p9_SEL_MASK ~(3UL << 0)\n#define p9_SET_MASK (1UL << 0)\n#define p9_CLR_MASK ~(p9_SET_MASK)\n#define p9_AS_OUTPUT LPC_PINCON->PINSEL0&=p9_SEL_MASK;LPC_GPIO0->FIODIR|=p9_SET_MASK\n#define p9_AS_INPUT LPC_GPIO0->FIOMASK &= p9_CLR_MASK; \n#define p9_SET LPC_GPIO0->FIOSET = p9_SET_MASK\n#define p9_CLR LPC_GPIO0->FIOCLR = p9_SET_MASK\n#define p9_IS_SET (bool)(LPC_GPIO0->FIOPIN & p9_SET_MASK)\n#define p9_IS_CLR !(p9_IS_SET)\n#define p9_MODE(x) LPC_PINCON->PINMODE0&=p9_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<0) \n\n/* p10 is P0.1 */\n#define p10_SEL_MASK ~(3UL << 2)\n#define p10_SET_MASK (1UL << 1)\n#define p10_CLR_MASK ~(p10_SET_MASK)\n#define p10_AS_OUTPUT LPC_PINCON->PINSEL0&=p10_SEL_MASK;LPC_GPIO0->FIODIR|=p10_SET_MASK\n#define p10_AS_INPUT LPC_GPIO0->FIOMASK &= p10_CLR_MASK; \n#define p10_SET LPC_GPIO0->FIOSET = p10_SET_MASK\n#define p10_CLR LPC_GPIO0->FIOCLR = p10_SET_MASK\n#define p10_IS_SET (bool)(LPC_GPIO0->FIOPIN & p10_SET_MASK)\n#define p10_IS_CLR !(p10_IS_SET)\n#define p10_MODE(x) LPC_PINCON->PINMODE0&=p10_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<2)\n\n/* p11 is P0.18 */\n#define p11_SEL_MASK ~(3UL << 4)\n#define p11_SET_MASK (1UL << 18)\n#define p11_CLR_MASK ~(p11_SET_MASK)\n#define p11_AS_OUTPUT LPC_PINCON->PINSEL1&=p11_SEL_MASK;LPC_GPIO0->FIODIR|=p11_SET_MASK\n#define p11_AS_INPUT LPC_GPIO0->FIOMASK &= p11_CLR_MASK; \n#define p11_SET LPC_GPIO0->FIOSET = p11_SET_MASK\n#define p11_CLR LPC_GPIO0->FIOCLR = p11_SET_MASK\n#define p11_IS_SET (bool)(LPC_GPIO0->FIOPIN & p11_SET_MASK)\n#define p11_IS_CLR !(p11_IS_SET)\n#define p11_MODE(x) LPC_PINCON->PINMODE1&=p11_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<4)\n\n/* p12 is P0.17 */\n#define p12_SEL_MASK ~(3UL << 2)\n#define p12_SET_MASK (1UL << 17)\n#define p12_CLR_MASK ~(p12_SET_MASK)\n#define p12_AS_OUTPUT LPC_PINCON->PINSEL1&=p12_SEL_MASK;LPC_GPIO0->FIODIR|=p12_SET_MASK\n#define p12_AS_INPUT LPC_GPIO0->FIOMASK &= p12_CLR_MASK; \n#define p12_SET LPC_GPIO0->FIOSET = p12_SET_MASK\n#define p12_CLR LPC_GPIO0->FIOCLR = p12_SET_MASK\n#define p12_IS_SET (bool)(LPC_GPIO0->FIOPIN & p12_SET_MASK)\n#define p12_IS_CLR !(p12_IS_SET)\n#define p12_MODE(x) LPC_PINCON->PINMODE1&=p12_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<2)\n\n/* p13 is P0.15 */\n#define p13_SEL_MASK ~(3UL << 30)\n#define p13_SET_MASK (1UL << 15)\n#define p13_CLR_MASK ~(p13_SET_MASK)\n#define p13_AS_OUTPUT LPC_PINCON->PINSEL0&=p13_SEL_MASK;LPC_GPIO0->FIODIR|=p13_SET_MASK\n#define p13_AS_INPUT LPC_GPIO0->FIOMASK &= p13_CLR_MASK; \n#define p13_SET LPC_GPIO0->FIOSET = p13_SET_MASK\n#define p13_CLR LPC_GPIO0->FIOCLR = p13_SET_MASK\n#define p13_IS_SET (bool)(LPC_GPIO0->FIOPIN & p13_SET_MASK)\n#define p13_IS_CLR !(p13_IS_SET)\n#define p13_MODE(x) LPC_PINCON->PINMODE0&=p13_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<30)\n\n/* p14 is P0.16 */\n#define p14_SEL_MASK ~(3UL << 0)\n#define p14_SET_MASK (1UL << 16)\n#define p14_CLR_MASK ~(p14_SET_MASK)\n#define p14_AS_OUTPUT LPC_PINCON->PINSEL1&=p14_SEL_MASK;LPC_GPIO0->FIODIR|=p14_SET_MASK\n#define p14_AS_INPUT LPC_GPIO0->FIOMASK &= p14_CLR_MASK; \n#define p14_SET LPC_GPIO0->FIOSET = p14_SET_MASK\n#define p14_CLR LPC_GPIO0->FIOCLR = p14_SET_MASK\n#define p14_IS_SET (bool)(LPC_GPIO0->FIOPIN & p14_SET_MASK)\n#define p14_IS_CLR !(p14_IS_SET)\n#define p14_MODE(x) LPC_PINCON->PINMODE1&=p14_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<0)\n\n/* p15 is P0.23 */\n#define p15_SEL_MASK ~(3UL << 14)\n#define p15_SET_MASK (1UL << 23)\n#define p15_CLR_MASK ~(p15_SET_MASK)\n#define p15_AS_OUTPUT LPC_PINCON->PINSEL1&=p15_SEL_MASK;LPC_GPIO0->FIODIR|=p15_SET_MASK\n#define p15_AS_INPUT LPC_GPIO0->FIOMASK &= p15_CLR_MASK; \n#define p15_SET LPC_GPIO0->FIOSET = p15_SET_MASK\n#define p15_CLR LPC_GPIO0->FIOCLR = p15_SET_MASK\n#define p15_IS_SET (bool)(LPC_GPIO0->FIOPIN & p15_SET_MASK)\n#define p15_IS_CLR !(p15_IS_SET)\n#define p15_MODE(x) LPC_PINCON->PINMODE1&=p15_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<14)\n\n/* p16 is P0.24 */\n#define p16_SEL_MASK ~(3UL << 16)\n#define p16_SET_MASK (1UL << 24)\n#define p16_CLR_MASK ~(p16_SET_MASK)\n#define p16_AS_OUTPUT LPC_PINCON->PINSEL1&=p16_SEL_MASK;LPC_GPIO0->FIODIR|=p16_SET_MASK\n#define p16_AS_INPUT LPC_GPIO0->FIOMASK &= p16_CLR_MASK; \n#define p16_SET LPC_GPIO0->FIOSET = p16_SET_MASK\n#define p16_CLR LPC_GPIO0->FIOCLR = p16_SET_MASK\n#define p16_IS_SET (bool)(LPC_GPIO0->FIOPIN & p16_SET_MASK)\n#define p16_IS_CLR !(p16_IS_SET)\n#define p16_MODE(x) LPC_PINCON->PINMODE1&=p16_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<16)\n\n/* p17 is P0.25 */\n#define p17_SEL_MASK ~(3UL << 18)\n#define p17_SET_MASK (1UL << 25)\n#define p17_CLR_MASK ~(p17_SET_MASK)\n#define p17_AS_OUTPUT LPC_PINCON->PINSEL1&=p17_SEL_MASK;LPC_GPIO0->FIODIR|=p17_SET_MASK\n#define p17_AS_INPUT LPC_GPIO0->FIOMASK &= p17_CLR_MASK; \n#define p17_SET LPC_GPIO0->FIOSET = p17_SET_MASK\n#define p17_CLR LPC_GPIO0->FIOCLR = p17_SET_MASK\n#define p17_IS_SET (bool)(LPC_GPIO0->FIOPIN & p17_SET_MASK)\n#define p17_IS_CLR !(p17_IS_SET)\n#define p17_MODE(x) LPC_PINCON->PINMODE1&=p17_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<18)\n\n/* p18 is P0.26 */\n#define p18_SEL_MASK ~(3UL << 20)\n#define p18_SET_MASK (1UL << 26)\n#define p18_CLR_MASK ~(p18_SET_MASK)\n#define p18_AS_OUTPUT LPC_PINCON->PINSEL1&=p18_SEL_MASK;LPC_GPIO0->FIODIR|=p18_SET_MASK\n#define p18_AS_INPUT LPC_GPIO0->FIOMASK &= p18_CLR_MASK; \n#define p18_SET LPC_GPIO0->FIOSET = p18_SET_MASK\n#define p18_CLR LPC_GPIO0->FIOCLR = p18_SET_MASK\n#define p18_IS_SET (bool)(LPC_GPIO0->FIOPIN & p18_SET_MASK)\n#define p18_IS_CLR !(p18_IS_SET)\n#define p18_MODE(x) LPC_PINCON->PINMODE1&=p18_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<20)\n\n/* p19 is P1.30 */\n#define p19_SEL_MASK ~(3UL << 28)\n#define p19_SET_MASK (1UL << 30)\n#define p19_AS_OUTPUT LPC_PINCON->PINSEL3&=p19_SEL_MASK;LPC_GPIO1->FIODIR|=p19_SET_MASK\n#define p19_AS_INPUT LPC_GPIO1->FIOMASK &= p19_CLR_MASK; \n#define p19_SET LPC_GPIO1->FIOSET = p19_SET_MASK\n#define p19_CLR LPC_GPIO1->FIOCLR = p19_SET_MASK\n#define p19_IS_SET (bool)(LPC_GPIO1->FIOPIN & p19_SET_MASK)\n#define p19_IS_CLR !(p19_IS_SET)\n#define p19_MODE(x) LPC_PINCON->PINMODE3&=p19_SEL_MASK;LPC_PINCON->PINMODE3|=((x&0x3)<<28)\n\n/* p20 is P1.31 */\n#define p20_SEL_MASK ~(3UL << 30)\n#define p20_SET_MASK (1UL << 31)\n#define p20_CLR_MASK ~(p20_SET_MASK)\n#define p20_AS_OUTPUT LPC_PINCON->PINSEL3&=p20_SEL_MASK;LPC_GPIO1->FIODIR|=p20_SET_MASK\n#define p20_AS_INPUT LPC_GPIO1->FIOMASK &= p20_CLR_MASK; \n#define p20_SET LPC_GPIO1->FIOSET = p20_SET_MASK\n#define p20_CLR LPC_GPIO1->FIOCLR = p20_SET_MASK\n#define p20_IS_SET (bool)(LPC_GPIO1->FIOPIN & p20_SET_MASK)\n#define p20_IS_CLR !(p20_IS_SET)\n#define p20_MODE(x) LPC_PINCON->PINMODE3&=p20_SEL_MASK;LPC_PINCON->PINMODE3|=((x&0x3)<<30)\n\n/* p21 is P2.5 */\n#define p21_SEL_MASK ~(3UL << 10)\n#define p21_SET_MASK (1UL << 5)\n#define p21_CLR_MASK ~(p21_SET_MASK)\n#define p21_AS_OUTPUT LPC_PINCON->PINSEL4&=p21_SEL_MASK;LPC_GPIO2->FIODIR|=p21_SET_MASK\n#define p21_AS_INPUT LPC_GPIO2->FIOMASK &= p21_CLR_MASK; \n#define p21_SET LPC_GPIO2->FIOSET = p21_SET_MASK\n#define p21_CLR LPC_GPIO2->FIOCLR = p21_SET_MASK\n#define p21_IS_SET (bool)(LPC_GPIO2->FIOPIN & p21_SET_MASK)\n#define p21_IS_CLR !(p21_IS_SET)\n#define p21_TOGGLE p21_IS_SET?p21_CLR:p21_SET\n#define p21_MODE(x) LPC_PINCON->PINMODE4&=p21_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<10)\n\n/* p22 is P2.4 */\n#define p22_SEL_MASK ~(3UL << 8)\n#define p22_SET_MASK (1UL << 4)\n#define p22_CLR_MASK ~(p22_SET_MASK)\n#define p22_AS_OUTPUT LPC_PINCON->PINSEL4&=p22_SEL_MASK;LPC_GPIO2->FIODIR|=p22_SET_MASK\n#define p22_AS_INPUT LPC_GPIO2->FIOMASK &= p22_CLR_MASK; \n#define p22_SET LPC_GPIO2->FIOSET = p22_SET_MASK\n#define p22_CLR LPC_GPIO2->FIOCLR = p22_SET_MASK\n#define p22_IS_SET (bool)(LPC_GPIO2->FIOPIN & p22_SET_MASK)\n#define p22_IS_CLR !(p22_IS_SET)\n#define p22_TOGGLE p22_IS_SET?p22_CLR:p22_SET\n#define p22_MODE(x) LPC_PINCON->PINMODE4&=p22_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<8)\n\n/* p23 is P2.3 */\n#define p23_SEL_MASK ~(3UL << 6)\n#define p23_SET_MASK (1UL << 3)\n#define p23_CLR_MASK ~(p23_SET_MASK)\n#define p23_AS_OUTPUT LPC_PINCON->PINSEL4&=p23_SEL_MASK;LPC_GPIO2->FIODIR|=p23_SET_MASK\n#define p23_AS_INPUT LPC_GPIO2->FIOMASK &= p23_CLR_MASK; \n#define p23_SET LPC_GPIO2->FIOSET = p23_SET_MASK\n#define p23_CLR LPC_GPIO2->FIOCLR = p23_SET_MASK\n#define p23_IS_SET (bool)(LPC_GPIO2->FIOPIN & p23_SET_MASK)\n#define p23_IS_CLR !(p23_IS_SET)\n#define p23_TOGGLE p23_IS_SET?p23_CLR:p23_SET\n#define p23_MODE(x) LPC_PINCON->PINMODE4&=p23_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<6)\n\n/* p24 is P2.2 */\n#define p24_SEL_MASK ~(3UL << 4)\n#define p24_SET_MASK (1UL << 2)\n#define p24_CLR_MASK ~(p24_SET_MASK)\n#define p24_AS_OUTPUT LPC_PINCON->PINSEL4&=p24_SEL_MASK;LPC_GPIO2->FIODIR|=p24_SET_MASK\n#define p24_AS_INPUT LPC_GPIO2->FIOMASK &= p24_CLR_MASK; \n#define p24_SET LPC_GPIO2->FIOSET = p24_SET_MASK\n#define p24_CLR LPC_GPIO2->FIOCLR = p24_SET_MASK\n#define p24_IS_SET (bool)(LPC_GPIO2->FIOPIN & p24_SET_MASK)\n#define p24_IS_CLR !(p24_IS_SET)\n#define p24_TOGGLE p24_IS_SET?p24_CLR:p24_SET\n#define p24_MODE(x) LPC_PINCON->PINMODE4&=p24_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<4)\n\n/* p25 is P2.1 */\n#define p25_SEL_MASK ~(3UL << 2)\n#define p25_SET_MASK (1UL << 1)\n#define p25_CLR_MASK ~(p25_SET_MASK)\n#define p25_AS_OUTPUT LPC_PINCON->PINSEL4&=p25_SEL_MASK;LPC_GPIO2->FIODIR|=p25_SET_MASK\n#define p25_AS_INPUT LPC_GPIO2->FIOMASK &= p25_CLR_MASK; \n#define p25_SET LPC_GPIO2->FIOSET = p25_SET_MASK\n#define p25_CLR LPC_GPIO2->FIOCLR = p25_SET_MASK\n#define p25_IS_SET (bool)(LPC_GPIO2->FIOPIN & p25_SET_MASK)\n#define p25_IS_CLR !(p25_IS_SET)\n#define p25_MODE(x) LPC_PINCON->PINMODE4&=p25_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<2)\n\n/* p26 is P2.0 */\n#define p26_SEL_MASK ~(3UL << 0)\n#define p26_SET_MASK (1UL << 0)\n#define p26_CLR_MASK ~(p26_SET_MASK)\n#define p26_AS_OUTPUT LPC_PINCON->PINSEL4&=p26_SEL_MASK;LPC_GPIO2->FIODIR|=p26_SET_MASK\n#define p26_AS_INPUT LPC_GPIO2->FIOMASK &= p26_CLR_MASK; \n#define p26_SET LPC_GPIO2->FIOSET = p26_SET_MASK\n#define p26_CLR LPC_GPIO2->FIOCLR = p26_SET_MASK\n#define p26_IS_SET (bool)(LPC_GPIO2->FIOPIN & p26_SET_MASK)\n#define p26_IS_CLR !(p26_IS_SET)\n#define p26_MODE(x) LPC_PINCON->PINMODE4&=p26_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<0)\n\n/* p27 is P0.11 */\n#define p27_SEL_MASK ~(3UL << 22)\n#define p27_SET_MASK (1UL << 11)\n#define p27_CLR_MASK ~(p27_SET_MASK)\n#define p27_AS_OUTPUT LPC_PINCON->PINSEL0&=p27_SEL_MASK;LPC_GPIO0->FIODIR|=p27_SET_MASK\n#define p27_AS_INPUT LPC_GPIO0->FIOMASK &= p27_CLR_MASK; \n#define p27_SET LPC_GPIO0->FIOSET = p27_SET_MASK\n#define p27_CLR LPC_GPIO0->FIOCLR = p27_SET_MASK\n#define p27_IS_SET (bool)(LPC_GPIO0->FIOPIN & p27_SET_MASK)\n#define p27_IS_CLR !(p27_IS_SET)\n#define p27_MODE(x) LPC_PINCON->PINMODE0&=p27_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<22)\n\n/* p28 is P0.10 */\n#define p28_SEL_MASK ~(3UL << 20)\n#define p28_SET_MASK (1UL << 10)\n#define p28_CLR_MASK ~(p28_SET_MASK)\n#define p28_AS_OUTPUT LPC_PINCON->PINSEL0&=p28_SEL_MASK;LPC_GPIO0->FIODIR|=p28_SET_MASK\n#define p28_AS_INPUT LPC_GPIO0->FIOMASK &= p28_CLR_MASK; \n#define p28_SET LPC_GPIO0->FIOSET = p28_SET_MASK\n#define p28_CLR LPC_GPIO0->FIOCLR = p28_SET_MASK\n#define p28_IS_SET (bool)(LPC_GPIO0->FIOPIN & p28_SET_MASK)\n#define p28_IS_CLR !(p28_IS_SET)\n#define p28_MODE(x) LPC_PINCON->PINMODE0&=p28_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<20)\n\n/* p29 is P0.5 */\n#define p29_SEL_MASK ~(3UL << 10)\n#define p29_SET_MASK (1UL << 5)\n#define p29_CLR_MASK ~(p29_SET_MASK)\n#define p29_AS_OUTPUT LPC_PINCON->PINSEL0&=p29_SEL_MASK;LPC_GPIO0->FIODIR|=p29_SET_MASK\n#define p29_AS_INPUT LPC_GPIO0->FIOMASK &= p29_CLR_MASK; \n#define p29_SET LPC_GPIO0->FIOSET = p29_SET_MASK\n#define p29_CLR LPC_GPIO0->FIOCLR = p29_SET_MASK\n#define p29_IS_SET (bool)(LPC_GPIO0->FIOPIN & p29_SET_MASK)\n#define p29_IS_CLR !(p29_IS_SET)\n#define p29_TOGGLE p29_IS_SET?p29_CLR:p29_SET\n#define p29_MODE(x) LPC_PINCON->PINMODE0&=p29_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<10)\n\n/* p30 is P0.4 */\n#define p30_SEL_MASK ~(3UL << 8)\n#define p30_SET_MASK (1UL << 4)\n#define p30_CLR_MASK ~(p30_SET_MASK)\n#define p30_AS_OUTPUT LPC_PINCON->PINSEL0&=p30_SEL_MASK;LPC_GPIO0->FIODIR|=p30_SET_MASK\n#define p30_AS_INPUT LPC_GPIO0->FIOMASK &= p30_CLR_MASK; \n#define p30_SET LPC_GPIO0->FIOSET = p30_SET_MASK\n#define p30_CLR LPC_GPIO0->FIOCLR = p30_SET_MASK\n#define p30_IS_SET (bool)(LPC_GPIO0->FIOPIN & p30_SET_MASK)\n#define p30_IS_CLR !(p30_IS_SET)\n#define p30_MODE(x) LPC_PINCON->PINMODE0&=p30_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<8)\n\n/* The following definitions are for the four Mbed LEDs.\n LED1 = P1.18\n LED2 = P1.20\n LED3 = P1.21\n LED4 = P1.23 */\n\n#define P1_18_SEL_MASK ~(3UL << 4)\n#define P1_18_SET_MASK (1UL << 18)\n#define P1_18_CLR_MASK ~(P1_18_SET_MASK)\n#define P1_18_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_18_SEL_MASK;LPC_GPIO1->FIODIR|=P1_18_SET_MASK\n#define P1_18_AS_INPUT LPC_GPIO1->FIOMASK &= P1_18_CLR_MASK; \n#define P1_18_SET LPC_GPIO1->FIOSET = P1_18_SET_MASK\n#define P1_18_CLR LPC_GPIO1->FIOCLR = P1_18_SET_MASK\n#define P1_18_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_18_SET_MASK)\n#define P1_18_IS_CLR !(P1_18_IS_SET)\n#define LED1_USE P1_18_AS_OUTPUT;P1_18_AS_INPUT\n#define LED1_ON P1_18_SET\n#define LED1_OFF P1_18_CLR\n#define LED1_IS_ON P1_18_IS_SET\n#define LED1_TOGGLE P1_18_IS_SET?LED1_OFF:LED1_ON\n\n#define P1_20_SEL_MASK ~(3UL << 8)\n#define P1_20_SET_MASK (1UL << 20)\n#define P1_20_CLR_MASK ~(P1_20_SET_MASK)\n#define P1_20_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_20_SEL_MASK;LPC_GPIO1->FIODIR|=P1_20_SET_MASK\n#define P1_20_AS_INPUT LPC_GPIO1->FIOMASK &= P1_20_CLR_MASK; \n#define P1_20_SET LPC_GPIO1->FIOSET = P1_20_SET_MASK\n#define P1_20_CLR LPC_GPIO1->FIOCLR = P1_20_SET_MASK\n#define P1_20_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_20_SET_MASK)\n#define P1_20_IS_CLR !(P1_20_IS_SET) \n#define LED2_USE P1_20_AS_OUTPUT;P1_20_AS_INPUT\n#define LED2_ON P1_20_SET\n#define LED2_OFF P1_20_CLR\n#define LED2_IS_ON P1_20_IS_SET\n#define LED2_TOGGLE P1_20_IS_SET?LED2_OFF:LED2_ON\n\n#define P1_21_SEL_MASK ~(3UL << 10)\n#define P1_21_SET_MASK (1UL << 21)\n#define P1_21_CLR_MASK ~(P1_21_SET_MASK)\n#define P1_21_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_21_SEL_MASK;LPC_GPIO1->FIODIR|=P1_21_SET_MASK\n#define P1_21_AS_INPUT LPC_GPIO1->FIOMASK &= P1_21_CLR_MASK; \n#define P1_21_SET LPC_GPIO1->FIOSET = P1_21_SET_MASK\n#define P1_21_CLR LPC_GPIO1->FIOCLR = P1_21_SET_MASK\n#define P1_21_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_21_SET_MASK)\n#define P1_21_IS_CLR !(P1_21_IS_SET)\n#define LED3_USE P1_21_AS_OUTPUT;P1_21_AS_INPUT\n#define LED3_ON P1_21_SET\n#define LED3_OFF P1_21_CLR\n#define LED3_IS_ON P1_21_IS_SET\n#define LED3_TOGGLE P1_21_IS_SET?LED3_OFF:LED3_ON\n\n#define P1_23_SEL_MASK ~(3UL << 14)\n#define P1_23_SET_MASK (1UL << 23)\n#define P1_23_CLR_MASK ~(P1_23_SET_MASK)\n#define P1_23_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_23_SEL_MASK;LPC_GPIO1->FIODIR|=P1_23_SET_MASK\n#define P1_23_AS_INPUT LPC_GPIO1->FIOMASK &= P1_23_CLR_MASK; \n#define P1_23_SET LPC_GPIO1->FIOSET = P1_23_SET_MASK\n#define P1_23_CLR LPC_GPIO1->FIOCLR = P1_23_SET_MASK\n#define P1_23_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_23_SET_MASK)\n#define P1_23_IS_CLR !(P1_23_IS_SET) \n#define LED4_USE P1_23_AS_OUTPUT;P1_23_AS_INPUT\n#define LED4_ON P1_23_SET\n#define LED4_OFF P1_23_CLR\n#define LED4_IS_ON P1_23_IS_SET\n#define LED4_TOGGLE P1_23_IS_SET?LED4_OFF:LED4_ON\n\n#endif\n\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/MODDMA.lib", "content": "https://os.mbed.com/users/AjK/code/MODDMA/#97a16bf2ff439853ed01edd65a382207e203c733" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/RemoraComms.cpp", "content": "#include \"mbed.h\"\n#include \"RemoraComms.h\"\n\n\nRemoraComms::RemoraComms(volatile rxData_t* ptrRxData, volatile txData_t* ptrTxData) :\n ptrRxData(ptrRxData),\n ptrTxData(ptrTxData),\n spiSlave(MOSI0, MISO0, SCK0, SSEL0)\n{\n spiSlave.frequency(48000000);\n}\n\nvoid RemoraComms::init()\n{\n // Create MODDMA configuration objects for the SPI transfer and memory copy\n spiDMAmemcpy1 = new MODDMA_Config;\n spiDMAmemcpy2 = new MODDMA_Config;\n spiDMAtx1 = new MODDMA_Config;\n spiDMAtx2 = new MODDMA_Config;\n spiDMArx1 = new MODDMA_Config;\n spiDMArx2 = new MODDMA_Config;\n\n // Setup DMA configurations\n spiDMAtx1\n ->channelNum ( MODDMA::Channel_0 )\n ->srcMemAddr ( (uint32_t) ptrTxData )\n ->dstMemAddr ( 0 )\n ->transferSize ( SPI_BUFF_SIZE )\n ->transferType ( MODDMA::m2p )\n ->srcConn ( 0 )\n ->dstConn ( MODDMA::SSP0_Tx )\n ->attach_tc ( this, &RemoraComms::tc0_callback )\n ->attach_err ( this, &RemoraComms::err_callback )\n ;\n\n spiDMAtx2\n ->channelNum ( MODDMA::Channel_1 )\n ->srcMemAddr ( (uint32_t) ptrTxData )\n ->dstMemAddr ( 0 )\n ->transferSize ( SPI_BUFF_SIZE )\n ->transferType ( MODDMA::m2p )\n ->srcConn ( 0 )\n ->dstConn ( MODDMA::SSP0_Tx )\n ->attach_tc ( this, &RemoraComms::tc1_callback )\n ->attach_err ( this, &RemoraComms::err_callback )\n ;\n\n spiDMArx1\n ->channelNum ( MODDMA::Channel_2 )\n ->srcMemAddr ( 0 )\n ->dstMemAddr ( (uint32_t) &spiRxBuffer1 )\n ->transferSize ( SPI_BUFF_SIZE )\n ->transferType ( MODDMA::p2m )\n ->srcConn ( MODDMA::SSP0_Rx )\n ->dstConn ( 0 )\n ->attach_tc ( this, &RemoraComms::tc2_callback )\n ->attach_err ( this, &RemoraComms::err_callback )\n ;\n\n spiDMArx2\n ->channelNum ( MODDMA::Channel_3 )\n ->srcMemAddr ( 0 )\n ->dstMemAddr ( (uint32_t) &spiRxBuffer2 )\n ->transferSize ( SPI_BUFF_SIZE )\n ->transferType ( MODDMA::p2m )\n ->srcConn ( MODDMA::SSP0_Rx )\n ->dstConn ( 0 )\n ->attach_tc ( this, &RemoraComms::tc3_callback )\n ->attach_err ( this, &RemoraComms::err_callback )\n ;\n\n spiDMAmemcpy1\n ->channelNum ( MODDMA::Channel_4 )\n ->srcMemAddr ( (uint32_t) &spiRxBuffer1 )\n ->dstMemAddr ( (uint32_t) &rxData )\n ->transferSize ( SPI_BUFF_SIZE )\n ->transferType ( MODDMA::m2m )\n ;\n\n spiDMAmemcpy2\n ->channelNum ( MODDMA::Channel_5 )\n ->srcMemAddr ( (uint32_t) &spiRxBuffer2 )\n ->dstMemAddr ( (uint32_t) &rxData )\n ->transferSize ( SPI_BUFF_SIZE )\n ->transferType ( MODDMA::m2m )\n ;\n}\n\n\nvoid RemoraComms::start()\n{\n this->ptrTxData->header = PRU_DATA;\n\n // Pass the configurations to the controller\n dma.Prepare( spiDMArx1 );\n dma.Prepare( spiDMAtx1 );\n\n // Enable SSP0 for DMA\n LPC_SSP0->DMACR = 0;\n LPC_SSP0->DMACR = (1<<1)|(1<<0); // TX,RX DMA Enable\n}\n\n\nvoid RemoraComms::tc0_callback()\n{\n // SPI Tx\n MODDMA_Config *config = dma.getConfig();\n dma.Disable( (MODDMA::CHANNELS)config->channelNum() );\n\n // Clear DMA IRQ flags.\n if (dma.irqType() == MODDMA::TcIrq) dma.clearTcIrq();\n if (dma.irqType() == MODDMA::ErrIrq) dma.clearErrIrq();\n\n dma.Prepare( spiDMAtx2 );\n}\n\nvoid RemoraComms::tc1_callback()\n{\n // SPI Tx\n MODDMA_Config *config = dma.getConfig();\n dma.Disable( (MODDMA::CHANNELS)config->channelNum() );\n\n // Clear DMA IRQ flags.\n if (dma.irqType() == MODDMA::TcIrq) dma.clearTcIrq();\n if (dma.irqType() == MODDMA::ErrIrq) dma.clearErrIrq();\n\n dma.Prepare( spiDMAtx1 );\n}\n\nvoid RemoraComms::tc2_callback()\n{\n // SPI Rx\n MODDMA_Config *config = dma.getConfig();\n dma.Disable( (MODDMA::CHANNELS)config->channelNum() );\n\n SPIdata = false;\n SPIdataError = false;\n\n // Clear DMA IRQ flags.\n if (dma.irqType() == MODDMA::TcIrq) dma.clearTcIrq();\n if (dma.irqType() == MODDMA::ErrIrq) dma.clearErrIrq();\n\n // Check and move the recieved SPI data payload\n switch (spiRxBuffer1.header)\n {\n case PRU_READ:\n SPIdata = true;\n rejectCnt = 0;\n dma.Disable( spiDMAmemcpy2->channelNum() );\n break;\n\n case PRU_WRITE:\n SPIdata = true;\n rejectCnt = 0;\n dma.Prepare( spiDMAmemcpy1 );\n break;\n\n default:\n rejectCnt++;\n if (rejectCnt > 5)\n {\n SPIdataError = true;\n }\n dma.Disable( spiDMAmemcpy2->channelNum() );\n }\n\n // swap Rx buffers\n dma.Prepare( spiDMArx2 );\n}\n\nvoid RemoraComms::tc3_callback()\n{\n // SPI Rx\n MODDMA_Config *config = dma.getConfig();\n dma.Disable( (MODDMA::CHANNELS)config->channelNum() );\n\n SPIdata = false;\n SPIdataError = false;\n\n // Clear DMA IRQ flags.\n if (dma.irqType() == MODDMA::TcIrq) dma.clearTcIrq();\n if (dma.irqType() == MODDMA::ErrIrq) dma.clearErrIrq();\n\n // Check and move the recieved SPI data payload\n switch (spiRxBuffer2.header)\n {\n case PRU_READ:\n SPIdata = true;\n rejectCnt = 0;\n dma.Disable( spiDMAmemcpy1->channelNum() );\n break;\n\n case PRU_WRITE:\n SPIdata = true;\n rejectCnt = 0;\n dma.Prepare( spiDMAmemcpy2 );\n break;\n\n default:\n rejectCnt++;\n if (rejectCnt > 5)\n {\n SPIdataError = true;\n }\n dma.Disable( spiDMAmemcpy1->channelNum() );\n }\n\n // swap Rx buffers\n dma.Prepare( spiDMArx1 );\n}\n\nvoid RemoraComms::err_callback()\n{\n printf(\"err\\r\\n\");\n}\n\n\nbool RemoraComms::getStatus(void)\n{\n return this->SPIdata;\n}\n\nvoid RemoraComms::setStatus(bool status)\n{\n this->SPIdata = status;\n}\n\nbool RemoraComms::getError(void)\n{\n return this->SPIdataError;\n}\n\nvoid RemoraComms::setError(bool error)\n{\n this->SPIdataError = error;\n}" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/comms/RemoraComms.h", "content": "#ifndef REMORASPI_H\n#define REMORASPI_H\n\n#include \"mbed.h\"\n#include \"configuration.h\"\n#include \"remora.h\"\n#include \"MODDMA.h\"\n\n// RPi SPI\n#define MOSI0 P0_18\n#define MISO0 P0_17\n#define SCK0 P0_15\n#define SSEL0 P0_16\n\nclass RemoraComms\n{\n private:\n\n SPISlave spiSlave;\n\n MODDMA dma;\n\n MODDMA_Config* spiDMArx1;\n MODDMA_Config* spiDMArx2;\n MODDMA_Config* spiDMAtx1;\n MODDMA_Config* spiDMAtx2;\n MODDMA_Config* spiDMAmemcpy1;\n MODDMA_Config* spiDMAmemcpy2;\n\n volatile rxData_t* ptrRxData;\n volatile txData_t* ptrTxData;\n rxData_t spiRxBuffer1;\n rxData_t spiRxBuffer2;\n uint8_t rejectCnt;\n bool SPIdata;\n bool SPIdataError;\n \n public:\n\n RemoraComms(volatile rxData_t*, volatile txData_t*);\n\n void tc0_callback(void);\n void tc1_callback(void);\n void tc2_callback(void);\n void tc3_callback(void);\n void err_callback(void);\n\n void init(void);\n void start(void);\n bool getStatus(void);\n void setStatus(bool);\n bool getError(void);\n void setError(bool);\n\n};\n\n#endif" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/pin/pin.cpp", "content": "#include \"mbed.h\"\n\n#include \"pin.h\"\n#include \n#include \n#include \n\n#include \"LPC17xx.h\"\n\nPin::Pin(std::string portAndPin, int dir) :\n portAndPin(portAndPin),\n dir(dir)\n{\n this->configPin();\n}\n\nPin::Pin(std::string portAndPin, int dir, int modifier) :\n portAndPin(portAndPin),\n dir(dir),\n modifier(modifier)\n{\n this->configPin();\n\n if (this->dir == 0) //input\n {\n switch(this->modifier)\n {\n case OPENDRAIN:\n printf(\" Setting pin as open drain\\n\");\n this->as_open_drain();\n break;\n case PULLUP:\n printf(\" Setting pin as pull_up\\n\");\n this->pull_up();\n break;\n case PULLDOWN:\n printf(\" Setting pin as pull_down\\n\");\n this->pull_down();\n break;\n case PULLNONE:\n printf(\" Setting pin as pull_none\\n\");\n this->pull_none();\n break;\n }\n }\n}\n\nvoid Pin::configPin()\n{\n printf(\"Creating Pin @\\n\");\n\n LPC_GPIO_TypeDef* gpios[5] ={LPC_GPIO0,LPC_GPIO1,LPC_GPIO2,LPC_GPIO3,LPC_GPIO4};\n\n // The method below to determine the port and pin from the string is taken from Smoothieware, thanks!\n\n // cs is the current position in the string\n const char* cs = this->portAndPin.c_str();\n\n // cn is the position of the next char after the number we just read\n char* cn = NULL;\n\n // grab first integer as port. pointer to first non-digit goes in cn\n this->portNumber = std::strtol(cs, &cn, 10);\n\n printf(\" portNumber = %d\\n\", this->portNumber);\n\n // if cn > cs then strtol read at least one digit\n if ((cn > cs) && (this->portNumber <= 4))\n {\n // translate port index into something useful\n this->port = gpios[this->portNumber];\n\n // if the char after the first integer is a . then we should expect a pin index next\n if (*cn == '.')\n {\n // move pointer to first digit (hopefully) of pin index\n cs = ++cn;\n\n // grab pin index.\n this->pin = strtol(cs, &cn, 10);\n\n printf(\" pin = %d\\n\", this->pin);\n\n // if strtol read some numbers, cn will point to the first non-digit\n if ((cn > cs) && (this->pin < 32) && (this->dir >= 0))\n {\n // configure pin direction: FIODIR\n if (dir == INPUT)\n {\n this->port->FIODIR &= ~(1<pin);\n }\n else\n {\n this->port->FIODIR |= 1<pin;\n }\n\n // configure\n this->port->FIOMASK &= ~(1 << this->pin);\n }\n }\n }\n}\n\nvoid Pin::setAsOutput()\n{\n this->port->FIODIR |= 1<pin;\n}\n\n\nvoid Pin::setAsInput()\n{\n this->port->FIODIR &= ~(1<pin);\n}\n\n// Configure this pin as OD\nvoid Pin::as_open_drain(){\n if( this->portNumber == 0 ){ LPC_PINCON->PINMODE_OD0 |= (1<pin); }\n if( this->portNumber == 1 ){ LPC_PINCON->PINMODE_OD1 |= (1<pin); }\n if( this->portNumber == 2 ){ LPC_PINCON->PINMODE_OD2 |= (1<pin); }\n if( this->portNumber == 3 ){ LPC_PINCON->PINMODE_OD3 |= (1<pin); }\n if( this->portNumber == 4 ){ LPC_PINCON->PINMODE_OD4 |= (1<pin); }\n pull_none(); // no pull up by default\n}\n\n// Configure this pin as no pullup or pulldown\nvoid Pin::pull_none()\n{\n // Set the two bits for this pin as 10\n if( this->portNumber == 0 && this->pin < 16 ){ LPC_PINCON->PINMODE0 |= (2<<( this->pin*2)); LPC_PINCON->PINMODE0 &= ~(1<<( this->pin *2)); }\n if( this->portNumber == 0 && this->pin >= 16 ){ LPC_PINCON->PINMODE1 |= (2<<( this->pin*2)); LPC_PINCON->PINMODE1 &= ~(1<<((this->pin-16)*2)); }\n if( this->portNumber == 1 && this->pin < 16 ){ LPC_PINCON->PINMODE2 |= (2<<( this->pin*2)); LPC_PINCON->PINMODE2 &= ~(1<<( this->pin *2)); }\n if( this->portNumber == 1 && this->pin >= 16 ){ LPC_PINCON->PINMODE3 |= (2<<( this->pin*2)); LPC_PINCON->PINMODE3 &= ~(1<<((this->pin-16)*2)); }\n if( this->portNumber == 2 && this->pin < 16 ){ LPC_PINCON->PINMODE4 |= (2<<( this->pin*2)); LPC_PINCON->PINMODE4 &= ~(1<<( this->pin *2)); }\n if( this->portNumber == 3 && this->pin >= 16 ){ LPC_PINCON->PINMODE7 |= (2<<( this->pin*2)); LPC_PINCON->PINMODE7 &= ~(1<<((this->pin-16)*2)); }\n if( this->portNumber == 4 && this->pin >= 16 ){ LPC_PINCON->PINMODE9 |= (2<<( this->pin*2)); LPC_PINCON->PINMODE9 &= ~(1<<((this->pin-16)*2)); }\n}\n\n// Configure this pin as a pullup\nvoid Pin::pull_up()\n{\n // Set the two bits for this pin as 00\n if( this->portNumber == 0 && this->pin < 16 ){ LPC_PINCON->PINMODE0 &= ~(3<<( this->pin *2)); }\n if( this->portNumber == 0 && this->pin >= 16 ){ LPC_PINCON->PINMODE1 &= ~(3<<((this->pin-16)*2)); }\n if( this->portNumber == 1 && this->pin < 16 ){ LPC_PINCON->PINMODE2 &= ~(3<<( this->pin *2)); }\n if( this->portNumber == 1 && this->pin >= 16 ){ LPC_PINCON->PINMODE3 &= ~(3<<((this->pin-16)*2)); }\n if( this->portNumber == 2 && this->pin < 16 ){ LPC_PINCON->PINMODE4 &= ~(3<<( this->pin *2)); }\n if( this->portNumber == 3 && this->pin >= 16 ){ LPC_PINCON->PINMODE7 &= ~(3<<((this->pin-16)*2)); }\n if( this->portNumber == 4 && this->pin >= 16 ){ LPC_PINCON->PINMODE9 &= ~(3<<((this->pin-16)*2)); }\n}\n\n// Configure this pin as a pulldown\nvoid Pin::pull_down()\n{\n // Set the two bits for this pin as 11\n if( this->portNumber == 0 && this->pin < 16 ){ LPC_PINCON->PINMODE0 |= (3<<( this->pin *2)); }\n if( this->portNumber == 0 && this->pin >= 16 ){ LPC_PINCON->PINMODE1 |= (3<<((this->pin-16)*2)); }\n if( this->portNumber == 1 && this->pin < 16 ){ LPC_PINCON->PINMODE2 |= (3<<( this->pin *2)); }\n if( this->portNumber == 1 && this->pin >= 16 ){ LPC_PINCON->PINMODE3 |= (3<<((this->pin-16)*2)); }\n if( this->portNumber == 2 && this->pin < 16 ){ LPC_PINCON->PINMODE4 |= (3<<( this->pin *2)); }\n if( this->portNumber == 3 && this->pin >= 16 ){ LPC_PINCON->PINMODE7 |= (3<<((this->pin-16)*2)); }\n if( this->portNumber == 4 && this->pin >= 16 ){ LPC_PINCON->PINMODE9 |= (3<<((this->pin-16)*2)); }\n}\n\n// Convert a PortAndPin into a mBed Pin\n// allows use of standard mbed libraries, eg FastAnalogIn\nPinName Pin::pinToPinName()\n{\n if( this->port == LPC_GPIO0 && this->pin == 0 ) {\n return p9;\n } else if( this->port == LPC_GPIO0 && this->pin == 1 ) {\n return p10;\n } else if( this->port == LPC_GPIO0 && this->pin == 23 ) {\n return p15;\n } else if( this->port == LPC_GPIO0 && this->pin == 24 ) {\n return p16;\n } else if( this->port == LPC_GPIO0 && this->pin == 25 ) {\n return p17;\n } else if( this->port == LPC_GPIO0 && this->pin == 26 ) {\n return p18;\n } else if( this->port == LPC_GPIO1 && this->pin == 30 ) {\n return p19;\n } else if( this->port == LPC_GPIO1 && this->pin == 31 ) {\n return p20;\n } else {\n //TODO: Error\n return NC;\n }\n}\n\n// If available on this pin, return mbed hardware pwm class for this pin\nPwmOut* Pin::hardware_pwm()\n{\n if (this->portNumber == 1)\n {\n if (this->pin == 18) { return new mbed::PwmOut(P1_18); }\n if (this->pin == 20) { return new mbed::PwmOut(P1_20); }\n if (this->pin == 21) { return new mbed::PwmOut(P1_21); }\n if (this->pin == 23) { return new mbed::PwmOut(P1_23); }\n if (this->pin == 24) { return new mbed::PwmOut(P1_24); }\n if (this->pin == 26) { return new mbed::PwmOut(P1_26); }\n }\n else if (this->portNumber == 2)\n {\n if (this->pin == 0) { return new mbed::PwmOut(P2_0); }\n if (this->pin == 1) { return new mbed::PwmOut(P2_1); }\n if (this->pin == 2) { return new mbed::PwmOut(P2_2); }\n if (this->pin == 3) { return new mbed::PwmOut(P2_3); }\n if (this->pin == 4) { return new mbed::PwmOut(P2_4); }\n if (this->pin == 5) { return new mbed::PwmOut(P2_5); }\n }\n else if (this->portNumber == 3)\n {\n if (this->pin == 25) { return new mbed::PwmOut(P3_25); }\n if (this->pin == 26) { return new mbed::PwmOut(P3_26); }\n }\n return nullptr;\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/pin/pin.h", "content": "#ifndef PIN_H\n#define PIN_H\n\n#include \"mbed.h\"\n\n#include \n#include \n#include \n#include \n\n#include \"LPC17xx.h\"\n\n#define INPUT 0x0\n#define OUTPUT 0x1\n\n#define NONE 0b000\n#define OPENDRAIN 0b001\n#define PULLUP 0b010\n#define PULLDOWN 0b011\n#define PULLNONE 0b100\n\nclass Pin\n{\n private:\n\n std::string portAndPin;\n uint8_t dir;\n uint8_t modifier;\n uint8_t portNumber;\n uint8_t pin;\n LPC_GPIO_TypeDef* port;\n\n public:\n\n Pin(std::string, int);\n Pin(std::string, int, int);\n\n PwmOut* hardware_pwm();\n\n void configPin();\n void setAsOutput();\n void setAsInput();\n void as_open_drain();\n void pull_none();\n void pull_up();\n void pull_down();\n PinName pinToPinName();\n\n inline bool get()\n {\n return ((this->port->FIOPIN >> this->pin ) & 1);\n }\n\n inline void set(bool value)\n {\n if (value)\n this->port->FIOSET = 1 << this->pin;\n else\n this->port->FIOCLR = 1 << this->pin;\n }\n};\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/qei/qeiDriver.cpp", "content": "#include \"mbed.h\"\n\n#include \"qeiDriver.h\"\n#include \"interrupt.h\"\n#include \"qeiInterrupt.h\"\n\nQEIdriver::QEIdriver()\n{\n this->hasIndex = false;\n\n this->dirinv = 0;\n this->sigmode = 0; // quadrature inputs\n this->capmode = 1; // count channels A and B (4x mode)\n this->invinx = 0;\n\n this->init();\n}\n\n\nQEIdriver::QEIdriver(bool hasIndex) :\n hasIndex(hasIndex)\n{\n this->hasIndex = true;\n\n this->dirinv = 0;\n this->sigmode = 0; // quadrature inputs\n this->capmode = 1; // count channels A and B (4x mode)\n this->invinx = 0;\n\n this->irq = QEI_IRQn;\n\n this->init();\n\n interruptPtr = new qeiInterrupt(this->irq, this);\t// Instantiate a new Timer Interrupt object and pass \"this\" pointer\n\n NVIC_EnableIRQ(this->irq);\n}\n\n\nvoid QEIdriver::interruptHandler()\n{\n this->indexDetected = true;\n this->indexCount = this->get();\n}\n\n\nuint32_t QEIdriver::get()\n{\n return (LPC_QEI->QEIPOS);\n}\n\n\nvoid QEIdriver::init()\n{\n printf(\" Initialising hardware QEI module\\n\");\n\n /* Set up clock and power for QEI module */\n LPC_SC->PCONP |= PCONP_QEI_ENABLE;\n\n /* The clock for theQEI module is set to FCCLK */\n LPC_SC->PCLKSEL1 = LPC_SC->PCLKSEL1 & ~(3UL<<0) | ((PCLKSEL_CCLK_DIV_1 & 3)<<0); \n\n /* Assign the pins. They are hard-coded, not user-selected. */\n // MCI0 (PhA)\n LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & PINSEL3_MCI0_MASK) | PINSEL3_MCI0 ;\n LPC_PINCON->PINMODE3 = (LPC_PINCON->PINMODE3 & PINMODE3_MCI0_MASK) | PINMODE3_MCI0;\n\n // MCI1 (PhB)\n LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & PINSEL3_MCI1_MASK) | PINSEL3_MCI1 ;\n LPC_PINCON->PINMODE3 = (LPC_PINCON->PINMODE3 & PINMODE3_MCI1_MASK) | PINMODE3_MCI1;\n\n // MCI2 (Index)\n if (hasIndex)\n {\n LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & PINSEL3_MCI2_MASK) | PINSEL3_MCI2 ;\n LPC_PINCON->PINMODE3 = (LPC_PINCON->PINMODE3 & PINMODE3_MCI2_MASK) | PINMODE3_MCI2;\n }\n\n // Initialize all remaining values in QEI peripheral\n LPC_QEI->QEICON = QEI_CON_RESP | QEI_CON_RESV | QEI_CON_RESI;\n LPC_QEI->QEIMAXPOS = 0xFFFFFFFF; // Default value\n LPC_QEI->CMPOS0 = 0x00;\n LPC_QEI->CMPOS1 = 0x00;\n LPC_QEI->CMPOS2 = 0x00;\n LPC_QEI->INXCMP = 0x00;\n LPC_QEI->QEILOAD = 0x00;\n LPC_QEI->VELCOMP = 0x00;\n LPC_QEI->FILTER = 200000; // Default for mechanical switches.\n\n // Set QEI configuration value corresponding to the call parameters\n LPC_QEI->QEICONF = (\n ((dirinv << 0) & 1) | \\\n ((sigmode << 1) & 2) | \\\n ((capmode << 2) & 4) | \\\n ((invinx <<3) & 8) );\n \n // Mask all int sources \n LPC_QEI->QEIIEC = QEI_IECLR_BITMASK; // Set the \"clear\" bits for all sources in the IE clear register \n\n // Clear any pending ints \n LPC_QEI->QEICLR = QEI_INTCLR_BITMASK; // Set the \"clear\" bits for for all sources in the Interrupt clear register\n\n // Enable specified interrupt on QEI peropheral\n LPC_QEI->QEIIES = QEI_INTSTAT_INX_Int;\n\n // set digital filter\n LPC_QEI->FILTER = 480UL;\n \n // set max position\n LPC_QEI->QEIMAXPOS = 0xFFFFFFFF;\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/drivers/qei/qeiDriver.h", "content": "#ifndef QEIDRIVER_H\n#define QEIDRIVER_H\n\n#include \"mbed.h\"\n\n#include \n#include \n#include \n#include \n\nclass qeiInterrupt; // forward declatation\n\nclass QEIdriver\n{\n \tfriend class qeiInterrupt;\n \n private:\n\n qeiInterrupt* \tinterruptPtr;\n IRQn_Type \t\tirq;\n\n int dirinv; // Direction invert. When = 1, complements the QEICONF register DIR bit\n int sigmode; // Signal mode. When = 0, PhA and PhB are quadrature inputs. When = 1, PhA is direction and PhB is clock\n int capmode; // Capture mode. When = 0, count PhA edges only (2X mode). Whe = 1, count PhB edges also (4X mode)\n int invinx; // Invert index. When = 1, inverts the sense of the index signal\n\n void interruptHandler();\n\n public:\n\n bool hasIndex;\n bool indexDetected;\n int32_t indexCount;\n\n QEIdriver(); // for channel A & B\n QEIdriver(bool); // For channels A & B, and index\n\n void init(void);\n uint32_t get(void);\n\n\n\n/* Private Macros ------------------------------------------------------------- */\n/* --------------------- BIT DEFINITIONS -------------------------------------- */\n/* Quadrature Encoder Interface Control Register Definition --------------------- */\n/*********************************************************************//**\n * Macro defines for QEI Control register\n **********************************************************************/\n#define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */\n#define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */\n#define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */\n#define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */\n#define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */\n\n/*********************************************************************//**\n * Macro defines for QEI Configuration register\n **********************************************************************/\n#define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */\n#define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */\n#define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */\n#define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */\n#define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */\n\n/*********************************************************************//**\n * Macro defines for QEI Status register\n **********************************************************************/\n#define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */\n#define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */\n\n/* Quadrature Encoder Interface Interrupt registers definitions --------------------- */\n/*********************************************************************//**\n * Macro defines for QEI Interrupt Status register\n **********************************************************************/\n#define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */\n#define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */\n#define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */\n#define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */\n#define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */\n#define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */\n#define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the\n current position */\n#define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the\n current position */\n#define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the\n current position */\n#define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current\n index count */\n#define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when\n both the POS0_Int bit is set and the REV_Int is set */\n#define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when\n both the POS1_Int bit is set and the REV_Int is set */\n#define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when\n both the POS2_Int bit is set and the REV_Int is set */\n#define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */\n\n/*********************************************************************//**\n * Macro defines for QEI Interrupt Set register\n **********************************************************************/\n#define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */\n#define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */\n#define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */\n#define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */\n#define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */\n#define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */\n#define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the\n current position */\n#define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the\n current position */\n#define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the\n current position */\n#define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current\n index count */\n#define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */\n#define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */\n#define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */\n#define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */\n\n/*********************************************************************//**\n * Macro defines for QEI Interrupt Clear register\n **********************************************************************/\n#define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */\n#define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */\n#define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */\n#define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */\n#define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */\n#define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */\n#define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the\n current position */\n#define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the\n current position */\n#define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the\n current position */\n#define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current\n index count */\n#define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */\n#define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */\n#define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */\n#define QEI_INTCLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Clear register bit-mask */\n\n/*********************************************************************//**\n * Macro defines for QEI Interrupt Enable register\n **********************************************************************/\n#define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */\n#define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */\n#define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */\n#define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */\n#define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */\n#define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */\n#define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the\n current position */\n#define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the\n current position */\n#define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the\n current position */\n#define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current\n index count */\n#define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */\n#define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */\n#define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */\n#define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */\n\n/*********************************************************************//**\n * Macro defines for QEI Interrupt Enable Set register\n **********************************************************************/\n#define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */\n#define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */\n#define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */\n#define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */\n#define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */\n#define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */\n#define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the\n current position */\n#define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the\n current position */\n#define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the\n current position */\n#define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current\n index count */\n#define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */\n#define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */\n#define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */\n#define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */\n\n/*********************************************************************//**\n * Macro defines for QEI Interrupt Enable Clear register\n **********************************************************************/\n#define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */\n#define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */\n#define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */\n#define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */\n#define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */\n#define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */\n#define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the\n current position */\n#define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the\n current position */\n#define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the\n current position */\n#define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current\n index count */\n#define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */\n#define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */\n#define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */\n#define QEI_IECLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Clear register bit-mask */\n\n/*********************************************************************//**\n * Macro defines for PCONP register QEI-related bits\n **********************************************************************/\n#define PCONP_QEI_ENABLE ((uint32_t)(1<<18)) /**< QEI peripheral power enable bit */\n#define PCONP_QEI_DISABLE ~((uint32_t)(1<<18)) /**< QEI peripheral power disable bit-mask */\n\n/*********************************************************************//**\n * Macro defines for PCLKSELx register QEI-related bits\n **********************************************************************/\n#define PCLKSEL_CCLK_DIV_1 1UL /**< Set PCLK to CCLK/1 */\n#define PCLKSEL_CCLK_DIV_2 2UL /**< Set PCLK to CCLK/2 */\n#define PCLKSEL_CCLK_DIV_4 0UL /**< Set PCLK to CCLK/4 */\n#define PCLKSEL_CCLK_DIV_8 3UL /**< Set PCLK to CCLK/8 */\n#define PCLKSEL1_PCLK_QEI_MASK ((uint32_t)(3<<0)) /**< PCLK_QEI PCLK_QEI bit field mask */\n/*********************************************************************//**\n * Macro defines for PINSEL3 register QEI-related bits\n **********************************************************************/\n#define PINSEL3_MCI0 ((uint32_t)(1<<8)) /**< MCIO (PhA) pin select */\n#define PINSEL3_MCI0_MASK ~((uint32_t)(3<<8)) /**< MCIO (PhA) pin mask */\n#define PINSEL3_MCI1 ((uint32_t)(1<<14)) /**< MCI1 (PhB) pin select */\n#define PINSEL3_MCI1_MASK ~((uint32_t)(3<<14)) /**< MCI2 (PhB) pin mask */\n#define PINSEL3_MCI2 ((uint32_t)(1<<16)) /**< MCI2 (Index) pin select */\n#define PINSEL3_MCI2_MASK ~((uint32_t)(3<<16)) /**< MCI2 (Index) pin mask */\n\n/*********************************************************************//**\n * Macro defines for PINMODE3 register QEI-related bits\n **********************************************************************/\n#define PIN_PULL_UP 0UL\n#define PIN_REPEATER 1UL\n#define PIN_NORESISTOR 2UL\n#define PIN_PULL_DOWN 3UL \n\n#define PINMODE3_MCI0 ((uint32_t)(PIN_NORESISTOR<<8)) /**< MCIO (PhA) resistor selection */\n#define PINMODE3_GPIO1p20 ((uint32_t)(PIN_PULL_DOWN<<8)) /**< GPIO 1.20) resistor selection */\n#define PINMODE3_MCI0_MASK ~((uint32_t)(3<<8)) /**< MCIO (PhA) resistor mask */\n\n#define PINMODE3_MCI1 ((uint32_t)(PIN_NORESISTOR<<14)) /**< MCI1 (PhB) resistor selection */\n#define PINMODE3_GPIO1p23 ((uint32_t)(PIN_PULL_DOWN<<14)) /**< GPIO 1.23) resistor selection */\n#define PINMODE3_MCI1_MASK ~((uint32_t)(3<<14)) /**< MCI1 (PhB) resistor mask */\n\n#define PINMODE3_MCI2 ((uint32_t)(PIN_PULL_UP<<16)) /**< MCI2 (Index) resistor selection */\n#define PINMODE3_GPIO1p24 ((uint32_t)(PIN_PULL_DOWN<<16)) /**< GPIO 1.24) resistor selection */\n#define PINMODE3_MCI2_MASK ~((uint32_t)(3<<16)) /**< MCI2 (Index) resistor mask */\n\n};\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/thread/createThreads.h", "content": "#include \"extern.h\"\n\n\nvoid createThreads(void)\n{\n // Create the thread objects and set the interrupt vectors to RAM. This is needed\n // as we are using the USB bootloader that requires a different code starting\n // address. Also set interrupt priority with NVIC_SetPriority.\n //\n // Note: DMAC has highest priority, then Base thread and then Servo thread\n // to ensure SPI data transfer is reliable\n\n NVIC_SetPriority(DMA_IRQn, 1);\n\n baseThread = new pruThread(LPC_TIM0, TIMER0_IRQn, base_freq);\n NVIC_SetVector(TIMER0_IRQn, (uint32_t)TIMER0_IRQHandler);\n NVIC_SetPriority(TIMER0_IRQn, 2);\n\n servoThread = new pruThread(LPC_TIM1, TIMER1_IRQn, servo_freq);\n NVIC_SetVector(TIMER1_IRQn, (uint32_t)TIMER1_IRQHandler);\n NVIC_SetPriority(TIMER1_IRQn, 3);\n\n commsThread = new pruThread(LPC_TIM2, TIMER2_IRQn, PRU_COMMSFREQ);\n NVIC_SetVector(TIMER2_IRQn, (uint32_t)TIMER2_IRQHandler);\n NVIC_SetPriority(TIMER2_IRQn, 4);\n\n // for QEI modudule\n NVIC_SetVector(QEI_IRQn, (uint32_t)QEI_IRQHandler);\n NVIC_SetPriority(QEI_IRQn, 5);\n}" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/thread/interrupt.cpp", "content": "#include \"interrupt.h\"\n#include \"LPC17xx.h\"\n\n#include \n\n// Define the vector table, it is only declared in the class declaration\nInterrupt* Interrupt::ISRVectorTable[] = {0};\n\n// Constructor\nInterrupt::Interrupt(void){}\n\n\n// Methods\n\nvoid Interrupt::Register(int interruptNumber, Interrupt* intThisPtr)\n{\n\tprintf(\"Registering interrupt for interrupt number = %d\\n\", interruptNumber);\n\tISRVectorTable[interruptNumber] = intThisPtr;\n}\n\nvoid Interrupt::TIMER0_Wrapper(void)\n{\n\tISRVectorTable[TIMER0_IRQn]->ISR_Handler();\n}\n\nvoid Interrupt::TIMER1_Wrapper(void)\n{\n\tISRVectorTable[TIMER1_IRQn]->ISR_Handler();\n}\n\nvoid Interrupt::TIMER2_Wrapper(void)\n{\n\tISRVectorTable[TIMER2_IRQn]->ISR_Handler();\n}\n\nvoid Interrupt::QEI_Wrapper(void)\n{\n\tISRVectorTable[QEI_IRQn]->ISR_Handler();\n}" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/thread/interrupt.h", "content": "#ifndef INTERRUPT_H\n#define INTERRUPT_H\n\n// Base class for all interrupt derived classes\n\n#define PERIPH_COUNT_IRQn\t32\t\t\t\t// Total number of device interrupt sources\n\nclass Interrupt\n{\n\tprotected:\n\n\t\tstatic Interrupt* ISRVectorTable[PERIPH_COUNT_IRQn];\n\n\tpublic:\n\n\t\tInterrupt(void);\n\n\t\t//static Interrupt* ISRVectorTable[PERIPH_COUNT_IRQn];\n\n\t\tstatic void Register(int interruptNumber, Interrupt* intThisPtr);\n\n\t\t// wrapper functions to ISR_Handler()\n\t\tstatic void TIMER0_Wrapper();\n\t\tstatic void TIMER1_Wrapper();\n static void TIMER2_Wrapper();\n static void QEI_Wrapper();\n\n\t\tvirtual void ISR_Handler(void) = 0;\n\n};\n\n#endif\n\n\n/****** LPC17xx Specific Interrupt Numbers ******************************************************\n WDT_IRQn = 0, Watchdog Timer Interrupt\n TIMER0_IRQn = 1, Timer0 Interrupt\n TIMER1_IRQn = 2, Timer1 Interrupt\n TIMER2_IRQn = 3, Timer2 Interrupt\n TIMER3_IRQn = 4, Timer3 Interrupt\n UART0_IRQn = 5, UART0 Interrupt\n UART1_IRQn = 6, UART1 Interrupt\n UART2_IRQn = 7, UART2 Interrupt\n UART3_IRQn = 8, UART3 Interrupt\n PWM1_IRQn = 9, PWM1 Interrupt\n I2C0_IRQn = 10, I2C0 Interrupt\n I2C1_IRQn = 11, I2C1 Interrupt\n I2C2_IRQn = 12, I2C2 Interrupt\n SPI_IRQn = 13, SPI Interrupt\n SSP0_IRQn = 14, SSP0 Interrupt\n SSP1_IRQn = 15, SSP1 Interrupt\n PLL0_IRQn = 16, PLL0 Lock (Main PLL) Interrupt\n RTC_IRQn = 17, Real Time Clock Interrupt\n EINT0_IRQn = 18, External Interrupt 0 Interrupt\n EINT1_IRQn = 19, External Interrupt 1 Interrupt\n EINT2_IRQn = 20, External Interrupt 2 Interrupt\n EINT3_IRQn = 21, External Interrupt 3 Interrupt\n ADC_IRQn = 22, A/D Converter Interrupt\n BOD_IRQn = 23, Brown-Out Detect Interrupt\n USB_IRQn = 24, USB Interrupt\n CAN_IRQn = 25, CAN Interrupt\n DMA_IRQn = 26, General Purpose DMA Interrupt\n I2S_IRQn = 27, I2S Interrupt\n ENET_IRQn = 28, Ethernet Interrupt\n RIT_IRQn = 29, Repetitive Interrupt Timer Interrupt\n MCPWM_IRQn = 30, Motor Control PWM Interrupt\n QEI_IRQn = 31, Quadrature Encoder Interface Interrupt\n PLL1_IRQn = 32, PLL1 Lock (USB PLL) Interrupt\n\nPERIPH_COUNT_IRQn = 32 < Number of peripheral IDs */\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/thread/irqHandlers.h", "content": "#include \"interrupt.h\"\n\nvoid TIMER0_IRQHandler()\n{\n // Base thread interrupt handler\n unsigned int isrMask = LPC_TIM0->IR;\n LPC_TIM0->IR = isrMask; /* Clear the Interrupt Bit */\n\n Interrupt::TIMER0_Wrapper();\n}\n\n\nvoid TIMER1_IRQHandler(void)\n{\n // Servo thread interrupt handler\n unsigned int isrMask = LPC_TIM1->IR;\n LPC_TIM1->IR = isrMask; /* Clear the Interrupt Bit */\n\n Interrupt::TIMER1_Wrapper();\n}\n\n\nvoid TIMER2_IRQHandler(void)\n{\n // Servo thread interrupt handler\n unsigned int isrMask = LPC_TIM2->IR;\n LPC_TIM2->IR = isrMask; /* Clear the Interrupt Bit */\n\n Interrupt::TIMER2_Wrapper();\n}\n\n\nvoid QEI_IRQHandler(void)\n{\n // QEI (quatrature encoder interface) index interrupt handler\n LPC_QEI->QEICLR = ((uint32_t)(1<<0)); \n Interrupt:: QEI_Wrapper();\n}" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/thread/pruThread.cpp", "content": "#include \"pruThread.h\"\n#include \"modules/module.h\"\n\n\nusing namespace std;\n\n// Thread constructor\npruThread::pruThread(LPC_TIM_TypeDef* timer, IRQn_Type irq, uint32_t frequency) :\n\ttimer(timer),\n\tirq(irq),\n\tfrequency(frequency)\n{\n\tprintf(\"Creating thread %d\\n\", this->frequency);\n}\n\nvoid pruThread::startThread(void)\n{\n\tTimerPtr = new pruTimer(this->timer, this->irq, this->frequency, this);\n}\n\nvoid pruThread::stopThread(void)\n{\n this->TimerPtr->stopTimer();\n}\n\n\nvoid pruThread::registerModule(Module* module)\n{\n\tthis->vThread.push_back(module);\n}\n\n\nvoid pruThread::unregisterModule(Module* module)\n{\n\titer = std::remove(vThread.begin(),vThread.end(), module);\n vThread.erase(iter, vThread.end());\n}\n\nvoid pruThread::run(void)\n{\n\t// iterate over the Thread pointer vector to run all instances of Module::runModule()\n\tfor (iter = vThread.begin(); iter != vThread.end(); ++iter) (*iter)->runModule();\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/thread/pruThread.h", "content": "#ifndef PRUTHREAD_H\n#define PRUTHREAD_H\n\n#include \"LPC17xx.h\"\n#include \"timer.h\"\n\n// Standard Template Library (STL) includes\n#include \n#include \n\nusing namespace std;\n\nclass Module;\n\nclass pruThread\n{\n\n\tprivate:\n\n\t\tpruTimer* \t\t TimerPtr;\n\t\n\t\tLPC_TIM_TypeDef* \ttimer;\n\t\tIRQn_Type \t\t\tirq;\n\t\tuint32_t \t\t\tfrequency;\n\n\t\tvector vThread;\t\t// vector containing pointers to Thread modules\n\t\tvector::iterator iter;\n\n\tpublic:\n\n\t\tpruThread(LPC_TIM_TypeDef* timer, IRQn_Type irq, uint32_t frequency);\n\n\t\tvoid registerModule(Module *module);\n void unregisterModule(Module *module);\n\t\tvoid startThread(void);\n void stopThread(void);\n\t\tvoid run(void);\n};\n\n#endif\n\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/thread/qeiInterrupt.cpp", "content": "#include \"interrupt.h\"\n#include \"qeiInterrupt.h\"\n#include \"qei.h\"\n\n\nqeiInterrupt::qeiInterrupt(int interruptNumber, QEIdriver* owner)\n{\n\t// Allows interrupt to access owner's data\n\tInterruptOwnerPtr = owner;\n\n\t// When a device interrupt object is instantiated, the Register function must be called to let the\n\t// Interrupt base class know that there is an appropriate ISR function for the given interrupt.\n\tInterrupt::Register(interruptNumber, this);\n}\n\n\nvoid qeiInterrupt::ISR_Handler(void)\n{\n\tthis->InterruptOwnerPtr->interruptHandler();\n}\n\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/thread/qeiInterrupt.h", "content": "#ifndef QEIINTERRUPT_H\n#define QEIINTERRUPT_H\n\n// Derived class for timer interrupts\n\nclass QEIdriver; // forward declatation\n\nclass qeiInterrupt : public Interrupt\n{\n\tprivate:\n\t \n\t\tQEIdriver* InterruptOwnerPtr;\n\t\n\tpublic:\n\n\t\tqeiInterrupt(int interruptNumber, QEIdriver* ownerptr);\n \n\t\tvoid ISR_Handler(void);\n};\n\n#endif" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV1_4/thread/timer.cpp", "content": "#include \"mbed.h\"\n#include \"LPC17xx.h\"\n\n#include \n#include \n\n#include \"interrupt.h\"\n#include \"timerInterrupt.h\"\n#include \"timer.h\"\n#include \"pruThread.h\"\n\n\n#define SBIT_TIMER0 1\n#define SBIT_TIMER1 2\n#define SBIT_TIMER2 22\n#define SBIT_TIMER3 23\n\n#define SBIT_MR0I 0\n#define SBIT_MR0R 1\n#define SBIT_CNTEN 0\n\n\n// Timer constructor\npruTimer::pruTimer(LPC_TIM_TypeDef* timer, IRQn_Type irq, uint32_t frequency, pruThread* ownerPtr):\n\ttimer(timer),\n\tirq(irq),\n\tfrequency(frequency),\n\ttimerOwnerPtr(ownerPtr)\n{\n\tinterruptPtr = new TimerInterrupt(this->irq, this);\t// Instantiate a new Timer Interrupt object and pass \"this\" pointer\n\n\tthis->startTimer();\n}\n\n\nvoid pruTimer::timerTick(void)\n{\n\t//Do something here\n\tthis->timerOwnerPtr->run();\n}\n\n\n\nvoid pruTimer::startTimer(void)\n{\n if (this->timer == LPC_TIM0)\n {\n printf(\"\tpower on Timer 0\\n\");\n LPC_SC->PCONP |= (1<timer == LPC_TIM1)\n {\n printf(\"\tpower on Timer 1\\n\");\n LPC_SC->PCONP |= (1<timer == LPC_TIM2)\n {\n printf(\"\tpower on Timer 2\\n\");\n LPC_SC->PCONP |= (1<timer->MCR = (1<timer->PR = 0x00;\n \n printf(\"\ttimer set PRO\\n\");\n this->timer->MR0 = SystemCoreClock/4/this->frequency;\n \n printf(\"\ttimer start\\n\");\n this->timer->TCR = (1<irq);\n}\n\nvoid pruTimer::stopTimer()\n{\n NVIC_DisableIRQ(this->irq);\n\n printf(\"\ttimer stop\\n\");\n this->timer->TCR = (0<\n\nclass TimerInterrupt; // forward declatation\nclass pruThread; // forward declatation\n\nclass pruTimer\n{\n\tfriend class TimerInterrupt;\n\n\tprivate:\n\n\t\tTimerInterrupt* \tinterruptPtr;\n\t\tLPC_TIM_TypeDef* \ttimer;\n\t\tIRQn_Type \t\t\tirq;\n\t\tuint32_t \t\t\tfrequency;\n\t\tpruThread* \t\t\ttimerOwnerPtr;\n\n\t\tvoid startTimer(void);\n\t\tvoid timerTick();\t\t\t// Private timer tiggered method\n\n\tpublic:\n\n\t\tpruTimer(LPC_TIM_TypeDef* timer, IRQn_Type irq, uint32_t frequency, pruThread* ownerPtr);\n void stopTimer(void);\n\n};\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV2/PeripheralNames.h", "content": "/* mbed Microcontroller Library\n *******************************************************************************\n * Copyright (c) 2014, STMicroelectronics\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and/or other materials provided with the distribution.\n * 3. Neither the name of STMicroelectronics nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *******************************************************************************\n */\n#ifndef MBED_PERIPHERALNAMES_H\n#define MBED_PERIPHERALNAMES_H\n\n#include \"cmsis.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\ntypedef enum {\n ADC_1 = (int)ADC1_BASE,\n ADC_2 = (int)ADC2_BASE,\n ADC_3 = (int)ADC3_BASE\n} ADCName;\n\ntypedef enum {\n DAC_0 = 0,\n DAC_1\n} DACName;\n\ntypedef enum {\n UART_1 = (int)USART1_BASE,\n UART_2 = (int)USART2_BASE,\n UART_3 = (int)USART3_BASE,\n UART_4 = (int)UART4_BASE,\n UART_5 = (int)UART5_BASE,\n UART_6 = (int)USART6_BASE,\n} UARTName;\n\n#define DEVICE_SPI_COUNT 3\ntypedef enum {\n SPI_1 = (int)SPI1_BASE,\n SPI_2 = (int)SPI2_BASE,\n SPI_3 = (int)SPI3_BASE\n} SPIName;\n\ntypedef enum {\n I2C_1 = (int)I2C1_BASE,\n I2C_2 = (int)I2C2_BASE,\n I2C_3 = (int)I2C3_BASE\n} I2CName;\n\ntypedef enum {\n PWM_1 = (int)TIM1_BASE,\n PWM_2 = (int)TIM2_BASE,\n PWM_3 = (int)TIM3_BASE,\n PWM_4 = (int)TIM4_BASE,\n PWM_5 = (int)TIM5_BASE,\n PWM_8 = (int)TIM8_BASE,\n PWM_9 = (int)TIM9_BASE,\n PWM_10 = (int)TIM10_BASE,\n PWM_11 = (int)TIM11_BASE,\n PWM_12 = (int)TIM12_BASE,\n PWM_13 = (int)TIM13_BASE,\n PWM_14 = (int)TIM14_BASE\n} PWMName;\n\ntypedef enum {\n CAN_1 = (int)CAN1_BASE,\n CAN_2 = (int)CAN2_BASE\n} CANName;\n\ntypedef enum {\n USB_FS = (int)USB_OTG_FS_PERIPH_BASE,\n USB_HS = (int)USB_OTG_HS_PERIPH_BASE\n} USBName;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV2/PeripheralPins.c", "content": "/* mbed Microcontroller Library\n *******************************************************************************\n * Copyright (c) 2018, STMicroelectronics\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and/or other materials provided with the distribution.\n * 3. Neither the name of STMicroelectronics nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *******************************************************************************\n */\n\n#include \"PeripheralPins.h\"\n#include \"mbed_toolchain.h\"\n\n//==============================================================================\n// Notes\n//\n// - The pins mentioned Px_y_ALTz are alternative possibilities which use other\n// HW peripheral instances. You can use them the same way as any other \"normal\"\n// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board\n// pinout image on mbed.org.\n//\n// - The pins which are connected to other components present on the board have\n// the comment \"Connected to xxx\". The pin function may not work properly in this\n// case. These pins may not be displayed on the board pinout image on mbed.org.\n// Please read the board reference manual and schematic for more information.\n//\n// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented\n// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.\n//\n//==============================================================================\n\n\n//*** ADC ***\n\nMBED_WEAK const PinMap PinMap_ADC[] = {\n {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 // Connected to B1 [Blue PushButton]\n {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_IN0 // Connected to B1 [Blue PushButton]\n {PA_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_IN0 // Connected to B1 [Blue PushButton]\n {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1\n {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1\n {PA_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1\n {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2\n {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2\n {PA_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2\n {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3\n {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3\n {PA_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3\n {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // Connected to I2S3_WS [CS43L22_LRCK]\n {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 // Connected to I2S3_WS [CS43L22_LRCK]\n {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to SPI1_SCK [LIS302DL_SCL/SPC]\n {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 // Connected to SPI1_SCK [LIS302DL_SCL/SPC]\n {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 // Connected to SPI1_MISO [LIS302DL_SDO]\n {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 // Connected to SPI1_MISO [LIS302DL_SDO]\n {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 // Connected to SPI1_MOSI [LIS302DL_SDA/SDI/SDO]\n {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 // Connected to SPI1_MOSI [LIS302DL_SDA/SDI/SDO]\n {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8\n {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8\n {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9\n {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9\n {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 // Connected to OTG_FS_PowerSwitchOn\n {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 // Connected to OTG_FS_PowerSwitchOn\n {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_IN10 // Connected to OTG_FS_PowerSwitchOn\n {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11\n {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11\n {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_IN11\n {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12\n {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12\n {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_IN12\n {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 // Connected to PDM_OUT [MP45DT02_DOUT]\n {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 // Connected to PDM_OUT [MP45DT02_DOUT]\n {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13 // Connected to PDM_OUT [MP45DT02_DOUT]\n {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14\n {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14\n {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15\n {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_ADC_Internal[] = {\n {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},\n {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},\n {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},\n {NC, NC, 0}\n};\n\n//*** DAC ***\n\nMBED_WEAK const PinMap PinMap_DAC[] = {\n {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1 // Connected to I2S3_WS [CS43L22_LRCK]\n {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2 // Connected to SPI1_SCK [LIS302DL_SCL/SPC]\n {NC, NC, 0}\n};\n\n//*** I2C ***\n\nMBED_WEAK const PinMap PinMap_I2C_SDA[] = {\n {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},\n {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to Audio_SDA [CS43L22_SDA]\n {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},\n {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_I2C_SCL[] = {\n {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},\n {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to Audio_SCL [CS43L22_SCL]\n {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},\n {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to CLK_IN [MP45DT02_CLK]\n {NC, NC, 0}\n};\n\n//*** PWM ***\n\n// TIM5 cannot be used because already used by the us_ticker\nMBED_WEAK const PinMap PinMap_PWM[] = {\n {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to B1 [Blue PushButton]\n// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to B1 [Blue PushButton]\n {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2\n// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2\n {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3\n// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3\n {PA_2_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1\n {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4\n// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4\n {PA_3_ALT0, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2\n {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to SPI1_SCK [LIS302DL_SCL/SPC]\n {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to SPI1_SCK [LIS302DL_SCL/SPC]\n {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 // Connected to SPI1_MISO [LIS302DL_SDO]\n {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 // Connected to SPI1_MISO [LIS302DL_SDO]\n {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N // Connected to SPI1_MOSI [LIS302DL_SDA/SDI/SDO]\n {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to SPI1_MOSI [LIS302DL_SDA/SDI/SDO]\n {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N // Connected to SPI1_MOSI [LIS302DL_SDA/SDI/SDO]\n {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 // Connected to SPI1_MOSI [LIS302DL_SDA/SDI/SDO]\n {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1\n {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to VBUS_FS\n {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to OTG_FS_ID\n {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to OTG_FS_DM\n {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1\n {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N\n {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3\n {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N\n {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N\n {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4\n {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N\n {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to SWO\n {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1\n {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2\n {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to Audio_SCL [CS43L22_SCL]\n {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2\n {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3\n {PB_8_ALT0, PWM_10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1\n {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to Audio_SDA [CS43L22_SDA]\n {PB_9_ALT0, PWM_11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 // Connected to Audio_SDA [CS43L22_SDA]\n {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to CLK_IN [MP45DT02_CLK]\n {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4\n {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N\n {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N\n {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N\n {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1\n {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N\n {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N\n {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2\n {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1\n {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1\n {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 // Connected to I2S3_MCK [CS43L22_MCLK]\n {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 // Connected to I2S3_MCK [CS43L22_MCLK]\n {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3\n {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3\n {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4\n {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4\n {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 // Connected to LD4 [Green Led]\n {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 // Connected to LD3 [Orange Led]\n {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 // Connected to LD5 [Red Led]\n {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 // Connected to LD6 [Blue Led]\n {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1\n {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2\n {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N\n {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1\n {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N\n {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2\n {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N\n {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3\n {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4\n {NC, NC, 0}\n};\n\n//*** SERIAL ***\n\nMBED_WEAK const PinMap PinMap_UART_TX[] = {\n {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to B1 [Blue PushButton]\n {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},\n {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to VBUS_FS\n {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to Audio_SCL [CS43L22_SCL]\n {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to CLK_IN [MP45DT02_CLK]\n {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},\n {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to I2S3_SCK [CS43L22_SCLK]\n {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to I2S3_SCK [CS43L22_SCLK]\n {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // Connected to I2S3_SD [CS43L22_SDIN]\n {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to OTG_FS_OverCurrent\n {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_UART_RX[] = {\n {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},\n {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},\n {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to OTG_FS_ID\n {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},\n {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},\n {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, // Connected to I2S3_MCK [CS43L22_MCLK]\n {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},\n {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},\n {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},\n {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},\n {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_UART_RTS[] = {\n {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},\n {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to OTG_FS_DP\n {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},\n {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to Audio_RST [CS43L22_RESET]\n {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LD4 [Green Led]\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_UART_CTS[] = {\n {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to B1 [Blue PushButton]\n {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to OTG_FS_DM\n {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},\n {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},\n {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},\n {NC, NC, 0}\n};\n\n//*** SPI ***\n\nMBED_WEAK const PinMap PinMap_SPI_MOSI[] = {\n {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SPI1_MOSI [LIS302DL_SDA/SDI/SDO]\n {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},\n {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},\n {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},\n {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to PDM_OUT [MP45DT02_DOUT]\n {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to I2S3_SD [CS43L22_SDIN]\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_SPI_MISO[] = {\n {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SPI1_MISO [LIS302DL_SDO]\n {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},\n {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},\n {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},\n {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},\n {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_SPI_SCLK[] = {\n {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SPI1_SCK [LIS302DL_SCL/SPC]\n {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to SWO\n {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SWO\n {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to CLK_IN [MP45DT02_CLK]\n {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},\n {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to I2S3_SCK [CS43L22_SCLK]\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_SPI_SSEL[] = {\n {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to I2S3_WS [CS43L22_LRCK]\n {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to I2S3_WS [CS43L22_LRCK]\n {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},\n {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},\n {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to Audio_SDA [CS43L22_SDA]\n {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},\n {NC, NC, 0}\n};\n\n//*** CAN ***\n\nMBED_WEAK const PinMap PinMap_CAN_RD[] = {\n {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to OTG_FS_DM\n {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},\n {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},\n {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},\n {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_CAN_TD[] = {\n {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to OTG_FS_DP\n {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)}, // Connected to Audio_SCL [CS43L22_SCL]\n {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to Audio_SDA [CS43L22_SDA]\n {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN2)},\n {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},\n {NC, NC, 0}\n};\n\n//*** USBDEVICE ***\n\nMBED_WEAK const PinMap PinMap_USB_FS[] = {\n// {PA_8, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF\n {PA_9, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS // Connected to VBUS_FS\n {PA_10, USB_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_ID // Connected to OTG_FS_ID\n {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DM // Connected to OTG_FS_DM\n {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DP // Connected to OTG_FS_DP\n {NC, NC, 0}\n};\n\n//*** USBDEVICE ***\n\nMBED_WEAK const PinMap PinMap_USB_HS[] = {\n#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_HS_IN_FS)\n// {PA_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_SOF // Connected to I2S3_WS [CS43L22_LRCK]\n {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_ID\n {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS\n {PB_14, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DM\n {PB_15, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DP\n#else /* MBED_CONF_TARGET_USB_SPEED */\n {PA_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D0\n {PA_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_CK // Connected to SPI1_SCK [LIS302DL_SCL/SPC]\n {PB_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D1\n {PB_1, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D2\n {PB_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D7\n {PB_10, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D3 // Connected to CLK_IN [MP45DT02_CLK]\n {PB_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D4\n {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D5\n {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D6\n {PC_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_STP // Connected to OTG_FS_PowerSwitchOn\n {PC_2, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_DIR\n {PC_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_NXT // Connected to PDM_OUT [MP45DT02_DOUT]\n#endif /* MBED_CONF_TARGET_USB_SPEED */\n {NC, NC, 0}\n};\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV2/PinNames.h", "content": "/* mbed Microcontroller Library\n *******************************************************************************\n * Copyright (c) 2018, STMicroelectronics\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and/or other materials provided with the distribution.\n * 3. Neither the name of STMicroelectronics nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *******************************************************************************\n */\n\n#ifndef MBED_PINNAMES_H\n#define MBED_PINNAMES_H\n\n#include \"cmsis.h\"\n#include \"PinNamesTypes.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\ntypedef enum {\n ALT0 = 0x100,\n ALT1 = 0x200,\n ALT2 = 0x300,\n ALT3 = 0x400\n} ALTx;\n\ntypedef enum {\n PA_0 = 0x00,\n PA_0_ALT0 = PA_0 | ALT0,\n PA_0_ALT1 = PA_0 | ALT1,\n PA_1 = 0x01,\n PA_1_ALT0 = PA_1 | ALT0,\n PA_1_ALT1 = PA_1 | ALT1,\n PA_2 = 0x02,\n PA_2_ALT0 = PA_2 | ALT0,\n PA_2_ALT1 = PA_2 | ALT1,\n PA_3 = 0x03,\n PA_3_ALT0 = PA_3 | ALT0,\n PA_3_ALT1 = PA_3 | ALT1,\n PA_4 = 0x04,\n PA_4_ALT0 = PA_4 | ALT0,\n PA_5 = 0x05,\n PA_5_ALT0 = PA_5 | ALT0,\n PA_6 = 0x06,\n PA_6_ALT0 = PA_6 | ALT0,\n PA_7 = 0x07,\n PA_7_ALT0 = PA_7 | ALT0,\n PA_7_ALT1 = PA_7 | ALT1,\n PA_7_ALT2 = PA_7 | ALT2,\n PA_8 = 0x08,\n PA_9 = 0x09,\n PA_10 = 0x0A,\n PA_11 = 0x0B,\n PA_12 = 0x0C,\n PA_13 = 0x0D,\n PA_14 = 0x0E,\n PA_15 = 0x0F,\n PA_15_ALT0 = PA_15 | ALT0,\n\n PB_0 = 0x10,\n PB_0_ALT0 = PB_0 | ALT0,\n PB_0_ALT1 = PB_0 | ALT1,\n PB_1 = 0x11,\n PB_1_ALT0 = PB_1 | ALT0,\n PB_1_ALT1 = PB_1 | ALT1,\n PB_2 = 0x12,\n PB_3 = 0x13,\n PB_3_ALT0 = PB_3 | ALT0,\n PB_4 = 0x14,\n PB_4_ALT0 = PB_4 | ALT0,\n PB_4_ALT1 = PB_4 | ALT1,\n PB_5 = 0x15,\n PB_5_ALT0 = PB_5 | ALT0,\n PB_5_ALT1 = PB_5 | ALT1,\n PB_6 = 0x16,\n PB_7 = 0x17,\n PB_8 = 0x18,\n PB_8_ALT0 = PB_8 | ALT0,\n PB_8_ALT1 = PB_8 | ALT1,\n PB_9 = 0x19,\n PB_9_ALT0 = PB_9 | ALT0,\n PB_9_ALT1 = PB_9 | ALT1,\n PB_10 = 0x1A,\n PB_11 = 0x1B,\n PB_12 = 0x1C,\n PB_13 = 0x1D,\n PB_14 = 0x1E,\n PB_14_ALT0 = PB_14 | ALT0,\n PB_14_ALT1 = PB_14 | ALT1,\n PB_15 = 0x1F,\n PB_15_ALT0 = PB_15 | ALT0,\n PB_15_ALT1 = PB_15 | ALT1,\n\n PC_0 = 0x20,\n PC_0_ALT0 = PC_0 | ALT0,\n PC_0_ALT1 = PC_0 | ALT1,\n PC_1 = 0x21,\n PC_1_ALT0 = PC_1 | ALT0,\n PC_1_ALT1 = PC_1 | ALT1,\n PC_2 = 0x22,\n PC_2_ALT0 = PC_2 | ALT0,\n PC_2_ALT1 = PC_2 | ALT1,\n PC_3 = 0x23,\n PC_3_ALT0 = PC_3 | ALT0,\n PC_3_ALT1 = PC_3 | ALT1,\n PC_4 = 0x24,\n PC_4_ALT0 = PC_4 | ALT0,\n PC_5 = 0x25,\n PC_5_ALT0 = PC_5 | ALT0,\n PC_6 = 0x26,\n PC_6_ALT0 = PC_6 | ALT0,\n PC_7 = 0x27,\n PC_7_ALT0 = PC_7 | ALT0,\n PC_8 = 0x28,\n PC_8_ALT0 = PC_8 | ALT0,\n PC_9 = 0x29,\n PC_9_ALT0 = PC_9 | ALT0,\n PC_10 = 0x2A,\n PC_10_ALT0 = PC_10 | ALT0,\n PC_11 = 0x2B,\n PC_11_ALT0 = PC_11 | ALT0,\n PC_12 = 0x2C,\n PC_13 = 0x2D,\n PC_14 = 0x2E,\n PC_15 = 0x2F,\n\n PD_0 = 0x30,\n PD_1 = 0x31,\n PD_2 = 0x32,\n PD_3 = 0x33,\n PD_4 = 0x34,\n PD_5 = 0x35,\n PD_6 = 0x36,\n PD_7 = 0x37,\n PD_8 = 0x38,\n PD_9 = 0x39,\n PD_10 = 0x3A,\n PD_11 = 0x3B,\n PD_12 = 0x3C,\n PD_13 = 0x3D,\n PD_14 = 0x3E,\n PD_15 = 0x3F,\n\n PE_0 = 0x40,\n PE_1 = 0x41,\n PE_2 = 0x42,\n PE_3 = 0x43,\n PE_4 = 0x44,\n PE_5 = 0x45,\n PE_6 = 0x46,\n PE_7 = 0x47,\n PE_8 = 0x48,\n PE_9 = 0x49,\n PE_10 = 0x4A,\n PE_11 = 0x4B,\n PE_12 = 0x4C,\n PE_13 = 0x4D,\n PE_14 = 0x4E,\n PE_15 = 0x4F,\n\n PF_0 = 0x50,\n PF_1 = 0x51,\n PF_2 = 0x52,\n PF_3 = 0x53,\n PF_4 = 0x54,\n PF_5 = 0x55,\n PF_6 = 0x56,\n PF_7 = 0x57,\n PF_8 = 0x58,\n PF_9 = 0x59,\n PF_10 = 0x5A,\n PF_11 = 0x5B,\n PF_12 = 0x5C,\n PF_13 = 0x5D,\n PF_14 = 0x5E,\n PF_15 = 0x5F,\n\n PG_0 = 0x60,\n PG_1 = 0x61,\n PG_2 = 0x62,\n PG_3 = 0x63,\n PG_4 = 0x64,\n PG_5 = 0x65,\n PG_6 = 0x66,\n PG_7 = 0x67,\n PG_8 = 0x68,\n PG_9 = 0x69,\n PG_10 = 0x6A,\n PG_11 = 0x6B,\n PG_12 = 0x6C,\n PG_13 = 0x6D,\n PG_14 = 0x6E,\n PG_15 = 0x6F,\n\n PH_0 = 0x70,\n PH_1 = 0x71,\n PH_2 = 0x72,\n PH_3 = 0x73,\n PH_4 = 0x74,\n PH_5 = 0x75,\n PH_6 = 0x76,\n PH_7 = 0x77,\n PH_8 = 0x78,\n PH_9 = 0x79,\n PH_10 = 0x7A,\n PH_11 = 0x7B,\n PH_12 = 0x7C,\n PH_13 = 0x7D,\n PH_14 = 0x7E,\n PH_15 = 0x7F,\n\n PI_0 = 0x80,\n PI_1 = 0x81,\n PI_2 = 0x82,\n PI_3 = 0x83,\n PI_4 = 0x84,\n PI_5 = 0x85,\n PI_6 = 0x86,\n PI_7 = 0x87,\n PI_8 = 0x88,\n PI_9 = 0x89,\n PI_10 = 0x8A,\n PI_11 = 0x8B,\n PI_12 = 0x8C,\n PI_13 = 0x8D,\n PI_14 = 0x8E,\n PI_15 = 0x8F,\n\n // ADC internal channels\n ADC_TEMP = 0xF0,\n ADC_VREF = 0xF1,\n ADC_VBAT = 0xF2,\n\n // STDIO for console print\n#ifdef MBED_CONF_TARGET_STDIO_UART_TX\n STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,\n#else\n STDIO_UART_TX = PA_2,\n#endif\n#ifdef MBED_CONF_TARGET_STDIO_UART_RX\n STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,\n#else\n STDIO_UART_RX = PA_3,\n#endif\n\n // Generic signals namings\n LED1 = PD_13, // LD3 as LD1 is not a user LED\n LED2 = PD_12, // LD4 as LD2 is not a user LED\n LED3 = PD_13, // orange\n LED4 = PD_12, // green\n LED5 = PD_14, // red\n LED6 = PD_15, // blue\n LED_RED = LED5,\n USER_BUTTON = PA_0,\n // Standardized button names\n BUTTON1 = USER_BUTTON,\n SERIAL_TX = STDIO_UART_TX, /* USART2 */\n SERIAL_RX = STDIO_UART_RX,\n USBTX = STDIO_UART_TX, /* USART2 */\n USBRX = STDIO_UART_RX,\n I2C_SCL = PB_8, /* I2C1 */\n I2C_SDA = PB_9,\n SPI_MOSI = PA_7,\n SPI_MISO = PA_6,\n SPI_SCK = PA_5,\n SPI_CS = PB_6,\n PWM_OUT = PB_3,\n\n /**** USB FS pins ****/\n USB_OTG_FS_DM = PA_11,\n USB_OTG_FS_DP = PA_12,\n USB_OTG_FS_ID = PA_10,\n USB_OTG_FS_SOF = PA_8,\n USB_OTG_FS_VBUS = PA_9,\n\n /**** USB HS pins ****/\n USB_OTG_HS_DM = PB_14,\n USB_OTG_HS_DP = PB_15,\n USB_OTG_HS_ID = PB_12,\n USB_OTG_HS_SOF = PA_4,\n USB_OTG_HS_ULPI_CK = PA_5,\n USB_OTG_HS_ULPI_D0 = PA_3,\n USB_OTG_HS_ULPI_D1 = PB_0,\n USB_OTG_HS_ULPI_D2 = PB_1,\n USB_OTG_HS_ULPI_D3 = PB_10,\n USB_OTG_HS_ULPI_D4 = PB_11,\n USB_OTG_HS_ULPI_D5 = PB_12,\n USB_OTG_HS_ULPI_D6 = PB_13,\n USB_OTG_HS_ULPI_D7 = PB_5,\n USB_OTG_HS_ULPI_DIR = PC_2,\n USB_OTG_HS_ULPI_NXT = PC_3,\n USB_OTG_HS_ULPI_STP = PC_0,\n USB_OTG_HS_VBUS = PB_13,\n\n /**** ETHERNET pins ****/\n ETH_COL = PA_3,\n ETH_CRS = PA_0,\n ETH_CRS_DV = PA_7,\n ETH_MDC = PC_1,\n ETH_MDIO = PA_2,\n ETH_PPS_OUT = PB_5,\n ETH_REF_CLK = PA_1,\n ETH_RXD0 = PC_4,\n ETH_RXD1 = PC_5,\n ETH_RXD2 = PB_0,\n ETH_RXD3 = PB_1,\n ETH_RX_CLK = PA_1,\n ETH_RX_DV = PA_7,\n ETH_RX_ER = PB_10,\n ETH_TXD0 = PB_12,\n ETH_TXD1 = PB_13,\n ETH_TXD2 = PC_2,\n ETH_TXD3 = PE_2,\n ETH_TXD3_ALT0 = PB_8,\n ETH_TX_CLK = PC_3,\n ETH_TX_EN = PB_11,\n\n /**** OSCILLATOR pins ****/\n RCC_OSC32_IN = PC_14,\n RCC_OSC32_OUT = PC_15,\n RCC_OSC_IN = PH_0,\n RCC_OSC_OUT = PH_1,\n\n /**** DEBUG pins ****/\n SYS_JTCK_SWCLK = PA_14,\n SYS_JTDI = PA_15,\n SYS_JTDO_SWO = PB_3,\n SYS_JTMS_SWDIO = PA_13,\n SYS_JTRST = PB_4,\n SYS_TRACECLK = PE_2,\n SYS_TRACED0 = PE_3,\n SYS_TRACED1 = PE_4,\n SYS_TRACED2 = PE_5,\n SYS_TRACED3 = PE_6,\n SYS_WKUP = PA_0,\n\n // Not connected\n NC = (int)0xFFFFFFFF\n} PinName;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKRV2/system_clock.c", "content": "/* mbed Microcontroller Library\n* Copyright (c) 2006-2017 ARM Limited\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n* http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*/\n\n/**\n * This file configures the system clock as follows:\n *-----------------------------------------------------------------------------\n * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)\n * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)\n * | 3- USE_PLL_HSI (internal 16 MHz)\n *-----------------------------------------------------------------------------\n * SYSCLK(MHz) | 168\n * AHBCLK (MHz) | 168\n * APB1CLK (MHz) | 42\n * APB2CLK (MHz) | 84\n * USB capable | YES\n *-----------------------------------------------------------------------------\n**/\n\n#include \"stm32f4xx.h\"\n#include \"mbed_error.h\"\n\n/*!< Uncomment the following line if you need to relocate your vector Table in\n Internal SRAM. */\n/* #define VECT_TAB_SRAM */\n#define VECT_TAB_OFFSET 0x8000 /*!< Vector Table base offset field.\n This value must be a multiple of 0x200. */\n\n\n// clock source is selected with CLOCK_SOURCE in json config\n#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)\n#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)\n#define USE_PLL_HSI 0x2 // Use HSI internal clock\n\n\n#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )\nuint8_t SetSysClock_PLL_HSE(uint8_t bypass);\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */\n\n#if ((CLOCK_SOURCE) & USE_PLL_HSI)\nuint8_t SetSysClock_PLL_HSI(void);\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */\n\n\n/**\n * @brief Setup the microcontroller system\n * Initialize the FPU setting, vector table location and External memory\n * configuration.\n * @param None\n * @retval None\n */\nvoid SystemInit(void)\n{\n /* FPU settings ------------------------------------------------------------*/\n#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\n SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */\n#endif\n /* Reset the RCC clock configuration to the default reset state ------------*/\n /* Set HSION bit */\n RCC->CR |= (uint32_t)0x00000001;\n\n /* Reset CFGR register */\n RCC->CFGR = 0x00000000;\n\n /* Reset HSEON, CSSON and PLLON bits */\n RCC->CR &= (uint32_t)0xFEF6FFFF;\n\n /* Reset PLLCFGR register */\n RCC->PLLCFGR = 0x24003010;\n\n /* Reset HSEBYP bit */\n RCC->CR &= (uint32_t)0xFFFBFFFF;\n\n /* Disable all interrupts */\n RCC->CIR = 0x00000000;\n\n#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)\n SystemInit_ExtMemCtl();\n#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */\n\n /* Configure the Vector Table location add offset address ------------------*/\n#ifdef VECT_TAB_SRAM\n SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\n#else\n SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */\n#endif\n\n}\n\n/**\n * @brief Configures the System clock source, PLL Multiplier and Divider factors,\n * AHB/APBx prescalers and Flash settings\n * @note This function should be called only once the RCC clock configuration\n * is reset to the default reset state (done in SystemInit() function).\n * @param None\n * @retval None\n */\nvoid SetSysClock(void)\n{\n#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)\n /* 1- Try to start with HSE and external clock */\n if (SetSysClock_PLL_HSE(1) == 0)\n#endif\n {\n#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)\n /* 2- If fail try to start with HSE and external xtal */\n if (SetSysClock_PLL_HSE(0) == 0)\n#endif\n {\n#if ((CLOCK_SOURCE) & USE_PLL_HSI)\n /* 3- If fail start with HSI clock */\n if (SetSysClock_PLL_HSI() == 0)\n#endif\n {\n {\n error(\"SetSysClock failed\\n\");\n }\n }\n }\n }\n\n /* Output clock on MCO2 pin(PC9) for debugging purpose */\n //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1); // 84 MHz\n}\n\n#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )\n/******************************************************************************/\n/* PLL (clocked by HSE) used as System clock source */\n/******************************************************************************/\nuint8_t SetSysClock_PLL_HSE(uint8_t bypass)\n{\n RCC_OscInitTypeDef RCC_OscInitStruct;\n RCC_ClkInitTypeDef RCC_ClkInitStruct;\n\n /* The voltage scaling allows optimizing the power consumption when the device is\n clocked below the maximum system frequency, to update the voltage scaling value\n regarding system frequency refer to product datasheet. */\n __HAL_RCC_PWR_CLK_ENABLE();\n __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);\n\n /* Enable HSE oscillator and activate PLL with HSE as source */\n RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;\n if (bypass == 0) {\n RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */\n } else {\n RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */\n }\n RCC_OscInitStruct.HSIState = RCC_HSI_OFF;\n RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\n RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;\n RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)\n RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)\n RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 168 MHz (336 MHz / 2)\n RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB\n if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {\n return 0; // FAIL\n }\n\n /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */\n RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);\n RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 168 MHz\n RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz\n RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz\n RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz (SPI1 clock...)\n if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {\n return 0; // FAIL\n }\n\n /* Output clock on MCO1 pin(PA8) for debugging purpose */\n /*\n if (bypass == 0)\n HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz\n else\n HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz\n */\n\n return 1; // OK\n}\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */\n\n#if ((CLOCK_SOURCE) & USE_PLL_HSI)\n/******************************************************************************/\n/* PLL (clocked by HSI) used as System clock source */\n/******************************************************************************/\nuint8_t SetSysClock_PLL_HSI(void)\n{\n RCC_OscInitTypeDef RCC_OscInitStruct;\n RCC_ClkInitTypeDef RCC_ClkInitStruct;\n\n /* The voltage scaling allows optimizing the power consumption when the device is\n clocked below the maximum system frequency, to update the voltage scaling value\n regarding system frequency refer to product datasheet. */\n __HAL_RCC_PWR_CLK_ENABLE();\n __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);\n\n /* Enable HSI oscillator and activate PLL with HSI as source */\n RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;\n RCC_OscInitStruct.HSIState = RCC_HSI_ON;\n RCC_OscInitStruct.HSEState = RCC_HSE_OFF;\n RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;\n RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\n RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;\n RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)\n RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)\n RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 168 MHz (336 MHz / 2)\n RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough\n if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {\n return 0; // FAIL\n }\n\n /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */\n RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);\n RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 168 MHz\n RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 168 MHz\n RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 42 MHz\n RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 84 MHz\n if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {\n return 0; // FAIL\n }\n\n /* Output clock on MCO1 pin(PA8) for debugging purpose */\n //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz\n\n return 1; // OK\n}\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKR_MINI_E3/PeripheralNames.h", "content": "/* mbed Microcontroller Library\n *******************************************************************************\n * Copyright (c) 2014, STMicroelectronics\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and/or other materials provided with the distribution.\n * 3. Neither the name of STMicroelectronics nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *******************************************************************************\n */\n#ifndef MBED_PERIPHERALNAMES_H\n#define MBED_PERIPHERALNAMES_H\n\n#include \"cmsis.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\ntypedef enum {\n ADC_1 = (int)ADC1_BASE,\n ADC_2 = (int)ADC2_BASE,\n ADC_3 = (int)ADC3_BASE\n} ADCName;\n\ntypedef enum {\n DAC_1 = (int)DAC_BASE\n} DACName;\n\ntypedef enum {\n UART_1 = (int)USART1_BASE,\n UART_2 = (int)USART2_BASE,\n UART_3 = (int)USART3_BASE,\n UART_4 = (int)UART4_BASE,\n UART_5 = (int)UART5_BASE\n} UARTName;\n\n#define DEVICE_SPI_COUNT 3\ntypedef enum {\n SPI_1 = (int)SPI1_BASE,\n SPI_2 = (int)SPI2_BASE,\n SPI_3 = (int)SPI3_BASE\n} SPIName;\n\ntypedef enum {\n I2C_1 = (int)I2C1_BASE,\n I2C_2 = (int)I2C2_BASE\n} I2CName;\n\ntypedef enum {\n PWM_1 = (int)TIM1_BASE,\n PWM_2 = (int)TIM2_BASE,\n PWM_3 = (int)TIM3_BASE,\n PWM_4 = (int)TIM4_BASE,\n PWM_5 = (int)TIM5_BASE,\n PWM_8 = (int)TIM8_BASE\n} PWMName;\n\ntypedef enum {\n CAN_1 = (int)CAN1_BASE\n} CANName;\n\ntypedef enum {\n USB_FS = (int)USB_BASE\n} USBName;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKR_MINI_E3/PeripheralPins.c", "content": "/* mbed Microcontroller Library\n *******************************************************************************\n * Copyright (c) 2018, STMicroelectronics\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and/or other materials provided with the distribution.\n * 3. Neither the name of STMicroelectronics nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *******************************************************************************\n */\n\n#include \"PeripheralPins.h\"\n#include \"mbed_toolchain.h\"\n\n//==============================================================================\n// Notes\n//\n// - The pins mentioned Px_y_ALTz are alternative possibilities which use other\n// HW peripheral instances. You can use them the same way as any other \"normal\"\n// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board\n// pinout image on mbed.org.\n//\n// - The pins which are connected to other components present on the board have\n// the comment \"Connected to xxx\". The pin function may not work properly in this\n// case. These pins may not be displayed on the board pinout image on mbed.org.\n// Please read the board reference manual and schematic for more information.\n//\n// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented\n// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.\n//\n//==============================================================================\n\n\n//*** ADC ***\n\nMBED_WEAK const PinMap PinMap_ADC[] = {\n {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0\n {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1\n// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to STDIO_UART_TX\n// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to STDIO_UART_RX\n {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4\n {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to LD2 [Green Led]\n {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6\n {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7\n {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8\n {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9\n {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10\n {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11\n {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12\n {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13\n {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14\n {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_ADC_Internal[] = {\n {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},\n {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},\n {NC, NC, 0}\n};\n\n//*** I2C ***\n\nMBED_WEAK const PinMap PinMap_I2C_SDA[] = {\n {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)},\n {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 2)}, // GPIO_Remap_I2C1\n {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_I2C_SCL[] = {\n {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)},\n {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 2)}, // GPIO_Remap_I2C1\n {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, 0)},\n {NC, NC, 0}\n};\n\n//*** PWM ***\n\n// TIM4 cannot be used because already used by the us_ticker\nMBED_WEAK const PinMap PinMap_PWM[] = {\n {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM2_CH1\n {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM2_CH2\n// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM2_CH3 // Connected to STDIO_UART_TX\n// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM2_CH4 // Connected to STDIO_UART_RX\n {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM3_CH1\n {PA_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM3_CH2\n {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM1_CH1\n {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM1_CH2\n {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM1_CH3\n {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM1_CH4\n {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 1, 0)}, // TIM2_CH1\n {PB_0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM3_CH3\n {PB_1, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM3_CH4\n {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 2, 0)}, // TIM2_CH2 // Connected to SWO\n {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 1, 0)}, // TIM3_CH1\n {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 7, 2, 0)}, // TIM3_CH2\n// {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 0)}, // TIM4_CH1\n// {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 0)}, // TIM4_CH2\n// {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 0)}, // TIM4_CH3\n// {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 4, 0)}, // TIM4_CH4\n {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 3, 0)}, // TIM2_CH3\n {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 8, 4, 0)}, // TIM2_CH4\n {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 1, 1)}, // TIM1_CH1N\n {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 2, 1)}, // TIM1_CH2N\n {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 0, 3, 1)}, // TIM1_CH3N\n {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 9, 1, 0)}, // TIM3_CH1\n {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 9, 2, 0)}, // TIM3_CH2\n {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 9, 3, 0)}, // TIM3_CH3\n {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, 9, 4, 0)}, // TIM3_CH4\n {NC, NC, 0}\n};\n\n//*** SERIAL ***\n\nMBED_WEAK const PinMap PinMap_UART_TX[] = {\n {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)}, // Connected to STDIO_UART_TX\n {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},\n {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 3)}, // GPIO_Remap_USART1\n {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},\n {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 5)}, // GPIO_PartialRemap_USART3\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_UART_RX[] = {\n {PA_3, UART_2, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 0)}, // Connected to STDIO_UART_RX\n {PA_10, UART_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 0)},\n {PB_7, UART_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 3)}, // GPIO_Remap_USART1\n {PB_11, UART_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 0)},\n {PC_11, UART_3, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLUP, 5)}, // GPIO_PartialRemap_USART3\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_UART_RTS[] = {\n {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},\n {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},\n {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_UART_CTS[] = {\n {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},\n {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},\n {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0)},\n {NC, NC, 0}\n};\n\n//*** SPI ***\n\nMBED_WEAK const PinMap PinMap_SPI_MOSI[] = {\n {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},\n {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, // GPIO_Remap_SPI1\n {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_SPI_MISO[] = {\n {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},\n {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, // GPIO_Remap_SPI1\n {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_SPI_SCLK[] = {\n {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)}, // Connected to LD2 [Green Led]\n {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, // GPIO_Remap_SPI1 // Connected to SWO\n {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_SPI_SSEL[] = {\n {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},\n {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 1)}, // GPIO_Remap_SPI1\n {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},\n {NC, NC, 0}\n};\n\n//*** CAN ***\n\nMBED_WEAK const PinMap PinMap_CAN_RD[] = {\n {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)},\n {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 10)}, // Remap CAN_RX to PB_8\n {NC, NC, 0}\n};\n\nMBED_WEAK const PinMap PinMap_CAN_TD[] = {\n {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 0)},\n {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, 10)}, // Remap CAN_TX to PB_9\n {NC, NC, 0}\n};\n\n//*** USBDEVICE ***\n\nMBED_WEAK const PinMap PinMap_USB_FS[] = {\n {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)}, // USB_DM\n {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)}, // USB_DP\n {NC, NC, 0}\n};\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKR_MINI_E3/PinNames.h", "content": "/* mbed Microcontroller Library\n *******************************************************************************\n * Copyright (c) 2018, STMicroelectronics\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and/or other materials provided with the distribution.\n * 3. Neither the name of STMicroelectronics nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *******************************************************************************\n */\n\n#ifndef MBED_PINNAMES_H\n#define MBED_PINNAMES_H\n\n#include \"cmsis.h\"\n#include \"PinNamesTypes.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\ntypedef enum {\n PA_0 = 0x00,\n PA_1 = 0x01,\n PA_2 = 0x02,\n PA_3 = 0x03,\n PA_4 = 0x04,\n PA_5 = 0x05,\n PA_6 = 0x06,\n PA_7 = 0x07,\n PA_8 = 0x08,\n PA_9 = 0x09,\n PA_10 = 0x0A,\n PA_11 = 0x0B,\n PA_12 = 0x0C,\n PA_13 = 0x0D,\n PA_14 = 0x0E,\n PA_15 = 0x0F,\n\n PB_0 = 0x10,\n PB_1 = 0x11,\n PB_2 = 0x12,\n PB_3 = 0x13,\n PB_4 = 0x14,\n PB_5 = 0x15,\n PB_6 = 0x16,\n PB_7 = 0x17,\n PB_8 = 0x18,\n PB_9 = 0x19,\n PB_10 = 0x1A,\n PB_11 = 0x1B,\n PB_12 = 0x1C,\n PB_13 = 0x1D,\n PB_14 = 0x1E,\n PB_15 = 0x1F,\n\n PC_0 = 0x20,\n PC_1 = 0x21,\n PC_2 = 0x22,\n PC_3 = 0x23,\n PC_4 = 0x24,\n PC_5 = 0x25,\n PC_6 = 0x26,\n PC_7 = 0x27,\n PC_8 = 0x28,\n PC_9 = 0x29,\n PC_10 = 0x2A,\n PC_11 = 0x2B,\n PC_12 = 0x2C,\n PC_13 = 0x2D,\n PC_14 = 0x2E,\n PC_15 = 0x2F,\n\n PD_0 = 0x30,\n PD_1 = 0x31,\n PD_2 = 0x32,\n\n // ADC internal channels\n ADC_TEMP = 0xF0,\n ADC_VREF = 0xF1,\n\n // Arduino connector namings\n A0 = PA_0,\n A1 = PA_1,\n A2 = PA_4,\n A3 = PB_0,\n A4 = PC_1,\n A5 = PC_0,\n D0 = PA_3,\n D1 = PA_2,\n D2 = PA_10,\n D3 = PB_3,\n D4 = PB_5,\n D5 = PB_4,\n D6 = PB_10,\n D7 = PA_8,\n D8 = PA_9,\n D9 = PC_7,\n D10 = PB_6,\n D11 = PA_7,\n D12 = PA_6,\n D13 = PA_5,\n D14 = PB_9,\n D15 = PB_8,\n\n // STDIO for console print\n#ifdef MBED_CONF_TARGET_STDIO_UART_TX\n STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,\n#else\n STDIO_UART_TX = PA_2,\n#endif\n#ifdef MBED_CONF_TARGET_STDIO_UART_RX\n STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,\n#else\n STDIO_UART_RX = PA_3,\n#endif\n\n // Generic signals namings\n LED1 = PA_5,\n LED2 = PA_5,\n LED3 = PA_5,\n LED4 = PA_5,\n USER_BUTTON = PC_13,\n // Standardized button names\n BUTTON1 = USER_BUTTON,\n SERIAL_TX = STDIO_UART_TX,\n SERIAL_RX = STDIO_UART_RX,\n USBTX = STDIO_UART_TX,\n USBRX = STDIO_UART_RX,\n I2C_SCL = PB_8,\n I2C_SDA = PB_9,\n SPI_MOSI = PA_7,\n SPI_MISO = PA_6,\n SPI_SCK = PA_5,\n SPI_CS = PB_6,\n PWM_OUT = PB_3,\n\n /**** USB pins ****/\n USB_DM = PA_11,\n USB_DP = PA_12,\n\n /**** OSCILLATOR pins ****/\n RCC_OSC32_IN = PC_14,\n RCC_OSC32_OUT = PC_15,\n RCC_OSC_IN = PD_0,\n RCC_OSC_OUT = PD_1,\n\n /**** DEBUG pins ****/\n SYS_JTCK_SWCLK = PA_14,\n SYS_JTDI = PA_15,\n SYS_JTDO_TRACESWO = PB_3,\n SYS_JTMS_SWDIO = PA_13,\n SYS_NJTRST = PB_4,\n SYS_WKUP = PA_0,\n\n // Not connected\n NC = (int)0xFFFFFFFF\n} PinName;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_SKR_MINI_E3/system_clock.c", "content": "/* mbed Microcontroller Library\n* Copyright (c) 2006-2017 ARM Limited\n*\n* Licensed under the Apache License, Version 2.0 (the \"License\");\n* you may not use this file except in compliance with the License.\n* You may obtain a copy of the License at\n*\n* http://www.apache.org/licenses/LICENSE-2.0\n*\n* Unless required by applicable law or agreed to in writing, software\n* distributed under the License is distributed on an \"AS IS\" BASIS,\n* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n* See the License for the specific language governing permissions and\n* limitations under the License.\n*/\n\n/**\n * This file configures the system clock as follows:\n *-------------------------------------------------------------------------------------------\n * System clock source | 1- PLL_HSE_EXTC / DEVICE_USBDEVICE | 3- PLL_HSI / DEVICE_USBDEVICE\n * | (external 8 MHz clock) | (internal 8 MHz)\n * | 2- PLL_HSE_XTAL / DEVICE_USBDEVICE |\n * | (external 8 MHz xtal) |\n *-------------------------------------------------------------------------------------------\n * SYSCLK(MHz) | 72 / 72 | 64 / 48\n *-------------------------------------------------------------------------------------------\n * AHBCLK (MHz) | 72 / 72 | 64 / 48\n *-------------------------------------------------------------------------------------------\n * APB1CLK (MHz) | 36 / 36 | 32 / 24\n *-------------------------------------------------------------------------------------------\n * APB2CLK (MHz) | 72 / 72 | 64 / 48\n *-------------------------------------------------------------------------------------------\n */\n\n#include \"stm32f1xx.h\"\n#include \"mbed_error.h\"\n\n/*!< Uncomment the following line if you need to relocate your vector Table in\n Internal SRAM. */\n/* #define VECT_TAB_SRAM */\n#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.\n This value must be a multiple of 0x200. */\n\n#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)\n#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)\n#define USE_PLL_HSI 0x2 // Use HSI internal clock\n\n#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )\nuint8_t SetSysClock_PLL_HSE(uint8_t bypass);\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */\n\n#if ((CLOCK_SOURCE) & USE_PLL_HSI)\nuint8_t SetSysClock_PLL_HSI(void);\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */\n\n\n/**\n * @brief Setup the microcontroller system\n * Initialize the Embedded Flash Interface, the PLL and update the\n * SystemCoreClock variable.\n * @note This function should be used only after reset.\n * @param None\n * @retval None\n */\nvoid SystemInit (void)\n{\n /* Reset the RCC clock configuration to the default reset state(for debug purpose) */\n /* Set HSION bit */\n RCC->CR |= 0x00000001U;\n\n /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */\n#if !defined(STM32F105xC) && !defined(STM32F107xC)\n RCC->CFGR &= 0xF8FF0000U;\n#else\n RCC->CFGR &= 0xF0FF0000U;\n#endif /* STM32F105xC */\n\n /* Reset HSEON, CSSON and PLLON bits */\n RCC->CR &= 0xFEF6FFFFU;\n\n /* Reset HSEBYP bit */\n RCC->CR &= 0xFFFBFFFFU;\n\n /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */\n RCC->CFGR &= 0xFF80FFFFU;\n\n#if defined(STM32F105xC) || defined(STM32F107xC)\n /* Reset PLL2ON and PLL3ON bits */\n RCC->CR &= 0xEBFFFFFFU;\n\n /* Disable all interrupts and clear pending bits */\n RCC->CIR = 0x00FF0000U;\n\n /* Reset CFGR2 register */\n RCC->CFGR2 = 0x00000000U;\n#elif defined(STM32F100xB) || defined(STM32F100xE)\n /* Disable all interrupts and clear pending bits */\n RCC->CIR = 0x009F0000U;\n\n /* Reset CFGR2 register */\n RCC->CFGR2 = 0x00000000U;\n#else\n /* Disable all interrupts and clear pending bits */\n RCC->CIR = 0x009F0000U;\n#endif /* STM32F105xC */\n\n#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)\n#ifdef DATA_IN_ExtSRAM\n SystemInit_ExtMemCtl();\n#endif /* DATA_IN_ExtSRAM */\n#endif\n\n#ifdef VECT_TAB_SRAM\n SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */\n#else\n SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */\n#endif\n\n}\n\n/**\n * @brief Configures the System clock source, PLL Multiplier and Divider factors,\n * AHB/APBx prescalers and Flash settings\n * @note This function should be called only once the RCC clock configuration\n * is reset to the default reset state (done in SystemInit() function).\n * @param None\n * @retval None\n */\nvoid SetSysClock(void)\n{\n#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)\n /* 1- Try to start with HSE and external clock */\n if (SetSysClock_PLL_HSE(1) == 0)\n#endif\n {\n#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)\n /* 2- If fail try to start with HSE and external xtal */\n if (SetSysClock_PLL_HSE(0) == 0)\n#endif\n {\n#if ((CLOCK_SOURCE) & USE_PLL_HSI)\n /* 3- If fail start with HSI clock */\n if (SetSysClock_PLL_HSI() == 0)\n#endif\n {\n {\n error(\"SetSysClock failed\\n\");\n }\n }\n }\n }\n\n /* Output clock on MCO1 pin(PA8) for debugging purpose */\n //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 72 MHz or 64 MHz\n}\n\n#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )\n/******************************************************************************/\n/* PLL (clocked by HSE) used as System clock source */\n/******************************************************************************/\nuint8_t SetSysClock_PLL_HSE(uint8_t bypass)\n{\n RCC_ClkInitTypeDef RCC_ClkInitStruct;\n RCC_OscInitTypeDef RCC_OscInitStruct;\n#if (DEVICE_USBDEVICE)\n RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInit;\n#endif /* DEVICE_USBDEVICE */\n\n /* Enable HSE oscillator and activate PLL with HSE as source */\n RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;\n if (bypass == 0) {\n RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */\n } else {\n RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */\n }\n RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;\n RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\n RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;\n RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)\n if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {\n return 0; // FAIL\n }\n\n /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */\n RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);\n RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz\n RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz\n RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz\n RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz\n if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {\n return 0; // FAIL\n }\n\n#if (DEVICE_USBDEVICE)\n /* USB clock selection */\n RCC_PeriphCLKInit.PeriphClockSelection = RCC_PERIPHCLK_USB;\n RCC_PeriphCLKInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;\n HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInit);\n#endif /* DEVICE_USBDEVICE */\n\n /* Output clock on MCO1 pin(PA8) for debugging purpose */\n //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz\n\n return 1; // OK\n}\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */\n\n#if ((CLOCK_SOURCE) & USE_PLL_HSI)\n/******************************************************************************/\n/* PLL (clocked by HSI) used as System clock source */\n/******************************************************************************/\nuint8_t SetSysClock_PLL_HSI(void)\n{\n RCC_ClkInitTypeDef RCC_ClkInitStruct;\n RCC_OscInitTypeDef RCC_OscInitStruct;\n#if (DEVICE_USBDEVICE)\n RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInit;\n#endif /* DEVICE_USBDEVICE */\n\n /* Enable HSI oscillator and activate PLL with HSI as source */\n RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;\n RCC_OscInitStruct.HSIState = RCC_HSI_ON;\n RCC_OscInitStruct.HSEState = RCC_HSE_OFF;\n RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;\n RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\n RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;\n#if (DEVICE_USBDEVICE)\n RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12; // 48 MHz (8 MHz/2 * 12)\n#else /* DEVICE_USBDEVICE */\n RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)\n#endif /* DEVICE_USBDEVICE */\n if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {\n return 0; // FAIL\n }\n\n#if (DEVICE_USBDEVICE)\n /* USB clock selection */\n RCC_PeriphCLKInit.PeriphClockSelection = RCC_PERIPHCLK_USB;\n RCC_PeriphCLKInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL;\n HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInit);\n#endif /* DEVICE_USBDEVICE */\n\n /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */\n RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);\n RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz\n RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz\n RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz\n RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz\n if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {\n return 0; // FAIL\n }\n\n /* Output clock on MCO1 pin(PA8) for debugging purpose */\n //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz\n\n return 1; // OK\n}\n#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F1/drivers/comms/RemoraComms.cpp", "content": "#include \"mbed.h\"\n#include \"RemoraComms.h\"\n\n#include \"stm32f1xx_hal.h\"\n\nRemoraComms::RemoraComms(volatile rxData_t* ptrRxData, volatile txData_t* ptrTxData, SPI_TypeDef* spiType, PinName interruptPin) :\n ptrRxData(ptrRxData),\n ptrTxData(ptrTxData),\n spiType(spiType),\n interruptPin(interruptPin),\n slaveSelect(interruptPin)\n{\n this->spiHandle.Instance = this->spiType;\n\n if (this->interruptPin == PA_4)\n {\n // interrupt pin is the NSS pin\n sharedSPI = false;\n HAL_NVIC_SetPriority(EXTI4_IRQn, 5, 0);\n }\n else if (this->interruptPin == PA_15)\n {\n // interrupt pin is not the NSS pin, ie the board shares the SPI bus with the SD card\n // configure the SPI in software NSS mode and always on\n sharedSPI = true;\n HAL_NVIC_SetPriority(EXTI15_10_IRQn , 5, 0);\n }\n else if (this->interruptPin == PC_1)\n {\n // interrupt pin is not the NSS pin, ie the board shares the SPI bus with the SD card\n // configure the SPI in software NSS mode and always on\n sharedSPI = true;\n HAL_NVIC_SetPriority(EXTI1_IRQn , 5, 0);\n }\n\n slaveSelect.rise(callback(this, &RemoraComms::processPacket)); \n}\n\n\n\nvoid RemoraComms::init()\n{\n if(this->spiHandle.Instance == SPI1)\n {\n printf(\"Initialising SPI1 slave\\n\");\n\n GPIO_InitTypeDef GPIO_InitStruct;\n\n /**SPI1 GPIO Configuration\n PA4 ------> SPI1_NSS\n PA5 ------> SPI1_SCK\n PA6 ------> SPI1_MISO\n PA7 ------> SPI1_MOSI\n */\n\n GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_7;\n GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\n GPIO_InitStruct.Pull = GPIO_NOPULL;\n HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n\n GPIO_InitStruct.Pin = GPIO_PIN_6;\n GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\n HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n\n __HAL_RCC_SPI1_CLK_ENABLE();\n\n this->spiHandle.Init.Mode = SPI_MODE_SLAVE;\n this->spiHandle.Init.Direction = SPI_DIRECTION_2LINES;\n this->spiHandle.Init.DataSize = SPI_DATASIZE_8BIT;\n this->spiHandle.Init.CLKPolarity = SPI_POLARITY_LOW;\n this->spiHandle.Init.CLKPhase = SPI_PHASE_1EDGE;\n if (sharedSPI)\n {\n this->spiHandle.Init.NSS = SPI_NSS_SOFT;\n printf(\"SPI is shared with SD card\\n\");\n }\n else\n {\n this->spiHandle.Init.NSS = SPI_NSS_HARD_INPUT;\n }\n this->spiHandle.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;\n this->spiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB;\n this->spiHandle.Init.TIMode = SPI_TIMODE_DISABLE;\n this->spiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\n this->spiHandle.Init.CRCPolynomial = 10;\n\n HAL_SPI_Init(&this->spiHandle);\n\n if (sharedSPI)\n {\n // set SSI (Slave Select Internal) low, ie same as NSS going low\n CLEAR_BIT(this->spiHandle.Instance->CR1, SPI_CR1_SSI);\n }\n \n printf(\"Initialising DMA for SPI\\n\");\n\n __HAL_RCC_GPIOA_CLK_ENABLE();\n __HAL_RCC_DMA1_CLK_ENABLE();\n\n this->hdma_spi_tx.Instance = DMA1_Channel3;\n this->hdma_spi_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;\n this->hdma_spi_tx.Init.PeriphInc = DMA_PINC_DISABLE;\n this->hdma_spi_tx.Init.MemInc = DMA_MINC_ENABLE;\n this->hdma_spi_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\n this->hdma_spi_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;\n this->hdma_spi_tx.Init.Mode = DMA_CIRCULAR;\n //this->hdma_spi_tx.Init.Mode = DMA_NORMAL;\n this->hdma_spi_tx.Init.Priority = DMA_PRIORITY_VERY_HIGH;\n \n HAL_DMA_Init(&this->hdma_spi_tx);\n\n __HAL_LINKDMA(&this->spiHandle, hdmatx, this->hdma_spi_tx);\n\n //HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 0, 0);\n ///NVIC_SetVector(DMA1_Channel3_IRQn, (uint32_t)&DMA1_Channel3_IRQHandler);\n //HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn);\n\n this->hdma_spi_rx.Instance = DMA1_Channel2;\n this->hdma_spi_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;\n this->hdma_spi_rx.Init.PeriphInc = DMA_PINC_DISABLE;\n this->hdma_spi_rx.Init.MemInc = DMA_MINC_ENABLE;\n this->hdma_spi_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\n this->hdma_spi_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;\n this->hdma_spi_rx.Init.Mode = DMA_CIRCULAR;\n //this->hdma_spi_rx.Init.Mode = DMA_NORMAL;\n this->hdma_spi_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH;\n\n HAL_DMA_Init(&this->hdma_spi_rx);\n\n __HAL_LINKDMA(&this->spiHandle,hdmarx,this->hdma_spi_rx);\n\n //HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0);\n //NVIC_SetVector(DMA1_Channel2_IRQn, (uint32_t)&DMA1_Channel2_IRQHandler);\n //HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn);\n }\n}\n\nvoid RemoraComms::start()\n{\n this->ptrTxData->header = PRU_DATA;\n HAL_SPI_TransmitReceive_DMA(&this->spiHandle, (uint8_t *)this->ptrTxData->txBuffer, (uint8_t *)this->spiRxBuffer.rxBuffer, SPI_BUFF_SIZE);\n}\n\nvoid RemoraComms::processPacket()\n{\n switch (this->spiRxBuffer.header)\n {\n case PRU_READ:\n this->SPIdata = true;\n this->rejectCnt = 0;\n // READ so do nothing with the received data\n break;\n\n case PRU_WRITE:\n this->SPIdata = true;\n this->rejectCnt = 0;\n // we've got a good WRITE header, move the data to rxData\n\n // **** would like to use DMA for this but cannot when the stream is in CIRCULAR mode for the SPI transfer ****\n // TODO: figure out how to use NORMAL mode for SPI...\n //this->status = HAL_DMA_Start(&hdma_memtomem_dma2_stream1, (uint32_t)&this->spiRxBuffer.rxBuffer, (uint32_t)this->rxData->rxBuffer, SPI_BUFF_SIZE);\n //if (this->status != HAL_OK) printf(\"F\\n\");\n \n \n // Do it the slower way. This does not seem to impact performance but not great to stay in ISR context for longer.. :-(\n\n // ensure an atomic access to the rxBuffer\n\t\t// disable thread interrupts\n\t\t__disable_irq(); \n for (int i = 0; i < SPI_BUFF_SIZE; i++)\n {\n this->ptrRxData->rxBuffer[i] = this->spiRxBuffer.rxBuffer[i];\n }\n\t\t// re-enable thread interrupts\n\t\t__enable_irq();\n break;\n\n default:\n this->rejectCnt++;\n if (this->rejectCnt > 5)\n {\n this->SPIdataError = true;\n }\n // reset SPI somehow\n }\n\n HAL_SPI_TransmitReceive_DMA(&this->spiHandle, (uint8_t *)this->ptrTxData->txBuffer, (uint8_t *)this->spiRxBuffer.rxBuffer, SPI_BUFF_SIZE);\n}\n\n\nbool RemoraComms::getStatus(void)\n{\n return this->SPIdata;\n}\n\nvoid RemoraComms::setStatus(bool status)\n{\n this->SPIdata = status;\n}\n\nbool RemoraComms::getError(void)\n{\n return this->SPIdataError;\n}\n\nvoid RemoraComms::setError(bool error)\n{\n this->SPIdataError = error;\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F1/drivers/comms/RemoraComms.h", "content": "#ifndef REMORASPI_H\n#define REMORASPI_H\n\n#include \"mbed.h\"\n#include \"configuration.h\"\n#include \"remora.h\"\n\n#include \"stm32f1xx_hal.h\"\n\n\n\nclass RemoraComms\n{\n private:\n\n SPI_TypeDef* spiType;\n SPI_HandleTypeDef spiHandle;\n DMA_HandleTypeDef hdma_spi_tx;\n DMA_HandleTypeDef hdma_spi_rx;\n DMA_HandleTypeDef hdma_memtomem_dma2_stream1;\n HAL_StatusTypeDef status;\n\n volatile rxData_t* ptrRxData;\n volatile txData_t* ptrTxData;\n rxData_t spiRxBuffer;\n uint8_t rejectCnt;\n bool SPIdata;\n bool SPIdataError;\n \n PinName interruptPin;\n InterruptIn slaveSelect;\n bool sharedSPI;\n \n void processPacket(void);\n\n public:\n\n RemoraComms(volatile rxData_t*, volatile txData_t*, SPI_TypeDef*, PinName);\n void init(void);\n void start(void);\n bool getStatus(void);\n void setStatus(bool);\n bool getError(void);\n void setError(bool);\n\n};\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F1/drivers/pin/pin.cpp", "content": "#include \"mbed.h\"\n\n#include \"pin.h\"\n#include \n#include \n#include \n\n#include \"stm32f1xx_hal.h\"\n\nPin::Pin(std::string portAndPin, int dir) :\n portAndPin(portAndPin),\n dir(dir)\n{\n // Set direction\n if (this->dir == INPUT)\n {\n this->mode = GPIO_MODE_INPUT;\n this->pull = GPIO_NOPULL;\n }\n else\n {\n this->mode = GPIO_MODE_OUTPUT_PP;\n this->pull = GPIO_NOPULL;\n }\n\n this->configPin();\n}\n\nPin::Pin(std::string portAndPin, int dir, int modifier) :\n portAndPin(portAndPin),\n dir(dir),\n modifier(modifier)\n{\n // Set direction\n if (this->dir == INPUT)\n {\n this->mode = GPIO_MODE_INPUT;\n\n // Set pin modifier\n switch(this->modifier)\n {\n case PULLUP:\n printf(\" Setting pin as Pull Up\\n\");\n this->pull = GPIO_PULLUP;\n break;\n case PULLDOWN:\n printf(\" Setting pin as Pull Down\\n\");\n this->pull = GPIO_PULLDOWN;\n break;\n case NONE:\n case PULLNONE:\n printf(\" Setting pin as No Pull\\n\");\n this->pull = GPIO_NOPULL;\n break;\n }\n }\n else\n {\n this->mode = GPIO_MODE_OUTPUT_PP;\n this->pull = GPIO_NOPULL;\n }\n\n this->configPin();\n}\n\nvoid Pin::configPin()\n{\n printf(\"Creating Pin @\\n\");\n\n //x can be (A..H) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.\n GPIO_TypeDef* gpios[5] ={GPIOA,GPIOB,GPIOC,GPIOD,GPIOE};\n \n\n if (this->portAndPin[0] == 'P') // PXXX e.g.PA2 PC15\n { \n this->portIndex = this->portAndPin[1] - 'A';\n this->pinNumber = this->portAndPin[3] - '0'; \n uint16_t pin2 = this->portAndPin[4] - '0'; \n\n if (pin2 <= 8) \n {\n this->pinNumber = this->pinNumber * 10 + pin2;\n }\n\n this->pin = 1 << this->pinNumber; // this is equivalent to GPIO_PIN_x definition\n }\n else\n {\n printf(\" Invalid port and pin definition\\n\");\n return;\n } \n\n printf(\" port = GPIO%c\\n\", char('A' + this->portIndex));\n printf(\" pin = %d\\n\", this->pinNumber);\n\n // translate port index into something useful\n this->GPIOx = gpios[this->portIndex];\n\n // enable the peripheral clock\n switch (portIndex){\n case 0:\n __HAL_RCC_GPIOA_CLK_ENABLE();\n break;\n\n case 1:\n __HAL_RCC_GPIOB_CLK_ENABLE();\n break;\n\n case 2:\n __HAL_RCC_GPIOC_CLK_ENABLE();\n break;\n \n case 3:\n __HAL_RCC_GPIOD_CLK_ENABLE();\n break;\n\n case 4:\n __HAL_RCC_GPIOE_CLK_ENABLE();\n break;\n }\n\n this->initPin();\n}\n\n\nvoid Pin::initPin()\n{\n // Configure GPIO pin Output Level\n HAL_GPIO_WritePin(this->GPIOx, this->pin, GPIO_PIN_RESET);\n\n // Configure the GPIO pin\n this->GPIO_InitStruct.Pin = this->pin;\n this->GPIO_InitStruct.Mode = this->mode;\n this->GPIO_InitStruct.Pull = this->pull;\n this->GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\n HAL_GPIO_Init(this->GPIOx, &this->GPIO_InitStruct); \n}\n\nvoid Pin::setAsOutput()\n{\n this->mode = GPIO_MODE_OUTPUT_PP;\n this->pull = GPIO_NOPULL;\n this->initPin();\n}\n\n\nvoid Pin::setAsInput()\n{\n this->mode = GPIO_MODE_INPUT;\n this->pull = GPIO_NOPULL;\n this->initPin();\n}\n\n\nvoid Pin::pull_none()\n{\n this->pull = GPIO_NOPULL;\n this->initPin();\n}\n\n\nvoid Pin::pull_up()\n{\n this->pull = GPIO_PULLUP;\n this->initPin();\n}\n\n\nvoid Pin::pull_down()\n{\n this->pull = GPIO_PULLDOWN;\n this->initPin();\n}\n\n\nPinName Pin::pinToPinName()\n{\n printf(\"PinName = 0x%x\\n\", (this->portIndex << 4) | this->pinNumber);\n return static_cast((this->portIndex << 4) | this->pinNumber);\n}\n\n\n// If available on this pin, return mbed hardware pwm class for this pin\nPwmOut* Pin::hardware_pwm()\n{\n if (this->portIndex == 0)\n {\n if (this->pinNumber == 0) { return new mbed::PwmOut(PA_0); }\n if (this->pinNumber == 1) { return new mbed::PwmOut(PA_1); }\n //if (this->pinNumber == 2) { return new mbed::PwmOut(PA_2); }\n //if (this->pinNumber == 3) { return new mbed::PwmOut(PA_3); }\n if (this->pinNumber == 5) { return new mbed::PwmOut(PA_5); }\n if (this->pinNumber == 6) { return new mbed::PwmOut(PA_6); }\n if (this->pinNumber == 7) { return new mbed::PwmOut(PA_7); }\n }\n else if (this->portIndex == 1)\n {\n if (this->pinNumber == 0) { return new mbed::PwmOut(PB_0); }\n if (this->pinNumber == 1) { return new mbed::PwmOut(PB_1); }\n }\n else if (this->portIndex == 2)\n {\n if (this->pinNumber == 0) { return new mbed::PwmOut(PC_0); }\n if (this->pinNumber == 1) { return new mbed::PwmOut(PC_1); }\n if (this->pinNumber == 2) { return new mbed::PwmOut(PC_2); }\n if (this->pinNumber == 3) { return new mbed::PwmOut(PC_3); }\n if (this->pinNumber == 4) { return new mbed::PwmOut(PC_4); }\n if (this->pinNumber == 5) { return new mbed::PwmOut(PC_5); }\n }\n return nullptr;\n}" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F1/drivers/pin/pin.h", "content": "#ifndef PIN_H\n#define PIN_H\n\n#include \"mbed.h\"\n\n#include \n#include \n#include \n#include \n\n#include \"stm32f1xx_hal.h\"\n\n#define INPUT 0x0\n#define OUTPUT 0x1\n\n#define NONE 0b000\n#define OPENDRAIN 0b001\n#define PULLUP 0b010\n#define PULLDOWN 0b011\n#define PULLNONE 0b100\n\nclass Pin\n{\n private:\n\n std::string portAndPin;\n uint8_t dir;\n uint8_t modifier;\n uint8_t portIndex;\n uint16_t pinNumber;\n uint16_t pin;\n uint32_t mode;\n uint32_t pull;\n uint32_t speed;\n GPIO_TypeDef* GPIOx;\n GPIO_InitTypeDef GPIO_InitStruct = {0};\n\n public:\n\n Pin(std::string, int);\n Pin(std::string, int, int);\n\n PwmOut* hardware_pwm();\n\n void configPin();\n void initPin();\n void setAsOutput();\n void setAsInput();\n void pull_none();\n void pull_up();\n void pull_down();\n PinName pinToPinName();\n\n inline bool get()\n {\n return HAL_GPIO_ReadPin(this->GPIOx, this->pin);\n }\n\n inline void set(bool value)\n {\n if (value)\n {\n HAL_GPIO_WritePin(this->GPIOx, this->pin, GPIO_PIN_SET);\n }\n else\n {\n HAL_GPIO_WritePin(this->GPIOx, this->pin, GPIO_PIN_RESET);\n }\n }\n};\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F1/drivers/qei/qeiDriver.cpp", "content": "#include \"mbed.h\"\n\n#include \"qeiDriver.h\"\n\nQEIdriver::QEIdriver() :\n qeiIndex(NC)\n{\n this->init();\n\n}\n\nQEIdriver::QEIdriver(bool hasIndex) :\n hasIndex(hasIndex),\n qeiIndex(NC)\n{\n this->init();;\n}\n\nvoid QEIdriver::interruptHandler()\n{\n\n}\n\n\nuint32_t QEIdriver::get()\n{\n return false;\n}\n\n\nvoid QEIdriver::init()\n{\n printf(\" Initialising hardware QEI module\\n\");\n printf(\" This target does not support a QEI module\\n\");\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F1/drivers/qei/qeiDriver.h", "content": "#ifndef QEIDRIVER_H\n#define QEIDRIVER_H\n\n#include \"mbed.h\"\n\n#include \n#include \n#include \n#include \n\n#include \"stm32f1xx_hal.h\"\n\n\nclass QEIdriver\n{\n private:\n\n TIM_HandleTypeDef htim;\n TIM_Encoder_InitTypeDef sConfig = {0};\n TIM_MasterConfigTypeDef sMasterConfig = {0};\n\n InterruptIn qeiIndex;\n IRQn_Type \t\t irq;\n\n void interruptHandler();\n\n public:\n\n bool hasIndex;\n bool indexDetected;\n int32_t indexCount;\n\n QEIdriver(); // for channel A & B\n QEIdriver(bool); // For channels A & B, and index\n\n void init(void);\n uint32_t get(void);\n\n};\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F1/thread/createThreads.h", "content": "#include \"extern.h\"\n\n\nvoid createThreads(void)\n{\n // Create the thread objects and set the interrupt vectors to RAM. This is needed\n // as we are using the SD bootloader that requires a different code starting\n // address. Also set interrupt priority with NVIC_SetPriority.\n\n baseThread = new pruThread(TIM1, TIM1_UP_IRQn, base_freq);\n NVIC_SetVector(TIM1_UP_IRQn, (uint32_t)TIM1_IRQHandler);\n NVIC_SetPriority(TIM1_UP_IRQn, 2);\n\n servoThread = new pruThread(TIM2, TIM2_IRQn , servo_freq);\n NVIC_SetVector(TIM2_IRQn , (uint32_t)TIM2_IRQHandler);\n NVIC_SetPriority(TIM2_IRQn , 3);\n\n commsThread = new pruThread(TIM3, TIM3_IRQn, PRU_COMMSFREQ);\n NVIC_SetVector(TIM3_IRQn, (uint32_t)TIM3_IRQHandler);\n NVIC_SetPriority(TIM3_IRQn, 4);\n}" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F1/thread/interrupt.cpp", "content": "#include \"interrupt.h\"\n#include \"stm32f1xx_hal.h\"\n\n#include \n\n// Define the vector table, it is only declared in the class declaration\nInterrupt* Interrupt::ISRVectorTable[] = {0};\n\n// Constructor\nInterrupt::Interrupt(void){}\n\n\n// Methods\n\nvoid Interrupt::Register(int interruptNumber, Interrupt* intThisPtr)\n{\n\tprintf(\"Registering interrupt for interrupt number = %d\\n\", interruptNumber);\n\tISRVectorTable[interruptNumber] = intThisPtr;\n}\n\nvoid Interrupt::TIM1_Wrapper(void)\n{\n\tISRVectorTable[TIM1_UP_IRQn]->ISR_Handler();\n}\n\nvoid Interrupt::TIM2_Wrapper(void)\n{\n\tISRVectorTable[TIM2_IRQn]->ISR_Handler();\n}\n\nvoid Interrupt::TIM3_Wrapper(void)\n{\n\tISRVectorTable[TIM3_IRQn]->ISR_Handler();\n}" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F1/thread/interrupt.h", "content": "#ifndef INTERRUPT_H\n#define INTERRUPT_H\n\n// Base class for all interrupt derived classes\n\n#define PERIPH_COUNT_IRQn\t60\t\t\t\t// Total number of device interrupt sources\n\nclass Interrupt\n{\n\tprotected:\n\n\t\tstatic Interrupt* ISRVectorTable[PERIPH_COUNT_IRQn];\n\n\tpublic:\n\n\t\tInterrupt(void);\n\n\t\t//static Interrupt* ISRVectorTable[PERIPH_COUNT_IRQn];\n\n\t\tstatic void Register(int interruptNumber, Interrupt* intThisPtr);\n\n\t\t// wrapper functions to ISR_Handler()\n\t\tstatic void TIM1_Wrapper();\n static void TIM2_Wrapper();\n static void TIM3_Wrapper();\n\n\t\tvirtual void ISR_Handler(void) = 0;\n\n};\n\n#endif\n\n/****** STM32 specific Interrupt Numbers *********************************************************************\n WWDG_IRQn = 0, !< Window WatchDog Interrupt \n PVD_IRQn = 1, !< PVD through EXTI Line detection Interrupt \n TAMPER_IRQn = 2, !< Tamper Interrupt \n RTC_IRQn = 3, !< RTC global Interrupt \n FLASH_IRQn = 4, !< FLASH global Interrupt \n RCC_IRQn = 5, !< RCC global Interrupt \n EXTI0_IRQn = 6, !< EXTI Line0 Interrupt \n EXTI1_IRQn = 7, !< EXTI Line1 Interrupt \n EXTI2_IRQn = 8, !< EXTI Line2 Interrupt \n EXTI3_IRQn = 9, !< EXTI Line3 Interrupt \n EXTI4_IRQn = 10, !< EXTI Line4 Interrupt \n DMA1_Channel1_IRQn = 11, !< DMA1 Channel 1 global Interrupt \n DMA1_Channel2_IRQn = 12, !< DMA1 Channel 2 global Interrupt \n DMA1_Channel3_IRQn = 13, !< DMA1 Channel 3 global Interrupt \n DMA1_Channel4_IRQn = 14, !< DMA1 Channel 4 global Interrupt \n DMA1_Channel5_IRQn = 15, !< DMA1 Channel 5 global Interrupt \n DMA1_Channel6_IRQn = 16, !< DMA1 Channel 6 global Interrupt \n DMA1_Channel7_IRQn = 17, !< DMA1 Channel 7 global Interrupt \n ADC1_2_IRQn = 18, !< ADC1 and ADC2 global Interrupt \n USB_HP_CAN1_TX_IRQn = 19, !< USB Device High Priority or CAN1 TX Interrupts \n USB_LP_CAN1_RX0_IRQn = 20, !< USB Device Low Priority or CAN1 RX0 Interrupts \n CAN1_RX1_IRQn = 21, !< CAN1 RX1 Interrupt \n CAN1_SCE_IRQn = 22, !< CAN1 SCE Interrupt \n EXTI9_5_IRQn = 23, !< External Line[9:5] Interrupts \n TIM1_BRK_IRQn = 24, !< TIM1 Break Interrupt \n TIM1_UP_IRQn = 25, !< TIM1 Update Interrupt \n TIM1_TRG_COM_IRQn = 26, !< TIM1 Trigger and Commutation Interrupt \n TIM1_CC_IRQn = 27, !< TIM1 Capture Compare Interrupt \n TIM2_IRQn = 28, !< TIM2 global Interrupt \n TIM3_IRQn = 29, !< TIM3 global Interrupt \n TIM4_IRQn = 30, !< TIM4 global Interrupt \n I2C1_EV_IRQn = 31, !< I2C1 Event Interrupt \n I2C1_ER_IRQn = 32, !< I2C1 Error Interrupt \n I2C2_EV_IRQn = 33, !< I2C2 Event Interrupt \n I2C2_ER_IRQn = 34, !< I2C2 Error Interrupt \n SPI1_IRQn = 35, !< SPI1 global Interrupt \n SPI2_IRQn = 36, !< SPI2 global Interrupt \n USART1_IRQn = 37, !< USART1 global Interrupt \n USART2_IRQn = 38, !< USART2 global Interrupt \n USART3_IRQn = 39, !< USART3 global Interrupt \n EXTI15_10_IRQn = 40, !< External Line[15:10] Interrupts \n RTC_Alarm_IRQn = 41, !< RTC Alarm through EXTI Line Interrupt \n USBWakeUp_IRQn = 42, !< USB Device WakeUp from suspend through EXTI Line Interrupt \n TIM8_BRK_IRQn = 43, !< TIM8 Break Interrupt \n TIM8_UP_IRQn = 44, !< TIM8 Update Interrupt \n TIM8_TRG_COM_IRQn = 45, !< TIM8 Trigger and Commutation Interrupt \n TIM8_CC_IRQn = 46, !< TIM8 Capture Compare Interrupt \n ADC3_IRQn = 47, !< ADC3 global Interrupt \n FSMC_IRQn = 48, !< FSMC global Interrupt \n SDIO_IRQn = 49, !< SDIO global Interrupt \n TIM5_IRQn = 50, !< TIM5 global Interrupt \n SPI3_IRQn = 51, !< SPI3 global Interrupt \n UART4_IRQn = 52, !< UART4 global Interrupt \n UART5_IRQn = 53, !< UART5 global Interrupt \n TIM6_IRQn = 54, !< TIM6 global Interrupt \n TIM7_IRQn = 55, !< TIM7 global Interrupt \n DMA2_Channel1_IRQn = 56, !< DMA2 Channel 1 global Interrupt \n DMA2_Channel2_IRQn = 57, !< DMA2 Channel 2 global Interrupt \n DMA2_Channel3_IRQn = 58, !< DMA2 Channel 3 global Interrupt \n DMA2_Channel4_5_IRQn = 59, !< DMA2 Channel 4 and Channel 5 global Interrupt \n*/" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F1/thread/irqHandlers.h", "content": "#include \"interrupt.h\"\n\n\nvoid TIM1_IRQHandler()\n{\n if(TIM1->SR & TIM_SR_UIF) // if UIF flag is set\n {\n TIM1->SR &= ~TIM_SR_UIF; // clear UIF flag\n \n Interrupt::TIM1_Wrapper();\n }\n}\n\nvoid TIM2_IRQHandler()\n{\n if(TIM2->SR & TIM_SR_UIF) // if UIF flag is set\n {\n TIM2->SR &= ~TIM_SR_UIF; // clear UIF flag\n \n Interrupt::TIM2_Wrapper();\n }\n}\n\nvoid TIM3_IRQHandler()\n{\n if(TIM3->SR & TIM_SR_UIF) // if UIF flag is set\n {\n TIM3->SR &= ~TIM_SR_UIF; // clear UIF flag\n \n Interrupt::TIM3_Wrapper();\n }\n}" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F1/thread/pruThread.cpp", "content": "#include \"pruThread.h\"\n#include \"modules/module.h\"\n\n\nusing namespace std;\n\n// Thread constructor\npruThread::pruThread(TIM_TypeDef* timer, IRQn_Type irq, uint32_t frequency) :\n\ttimer(timer),\n\tirq(irq),\n\tfrequency(frequency)\n{\n\tprintf(\"Creating thread %d\\n\", this->frequency);\n}\n\nvoid pruThread::startThread(void)\n{\n\tTimerPtr = new pruTimer(this->timer, this->irq, this->frequency, this);\n}\n\nvoid pruThread::stopThread(void)\n{\n this->TimerPtr->stopTimer();\n}\n\n\nvoid pruThread::registerModule(Module* module)\n{\n\tthis->vThread.push_back(module);\n}\n\n\nvoid pruThread::unregisterModule(Module* module)\n{\n\titer = std::remove(vThread.begin(),vThread.end(), module);\n vThread.erase(iter, vThread.end());\n}\n\nvoid pruThread::run(void)\n{\n\t// iterate over the Thread pointer vector to run all instances of Module::runModule()\n\tfor (iter = vThread.begin(); iter != vThread.end(); ++iter) (*iter)->runModule();\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F1/thread/pruThread.h", "content": "#ifndef PRUTHREAD_H\n#define PRUTHREAD_H\n\n#include \"stm32f1xx_hal.h\"\n#include \"timer.h\"\n\n// Standard Template Library (STL) includes\n#include \n#include \n\nusing namespace std;\n\nclass Module;\n\nclass pruThread\n{\n\n\tprivate:\n\n\t\tpruTimer* \t\t TimerPtr;\n\t\n\t\tTIM_TypeDef* \t timer;\n\t\tIRQn_Type \t\t\tirq;\n\t\tuint32_t \t\t\tfrequency;\n\n\t\tvector vThread;\t\t// vector containing pointers to Thread modules\n\t\tvector::iterator iter;\n\n\tpublic:\n\n\t\tpruThread(TIM_TypeDef* timer, IRQn_Type irq, uint32_t frequency);\n\n\t\tvoid registerModule(Module *module);\n void unregisterModule(Module *module);\n\t\tvoid startThread(void);\n void stopThread(void);\n\t\tvoid run(void);\n};\n\n#endif\n\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F1/thread/timer.cpp", "content": "#include \"mbed.h\"\n#include \"stm32f1xx_hal.h\"\n\n#include \n#include \n\n#include \"interrupt.h\"\n#include \"timerInterrupt.h\"\n#include \"timer.h\"\n#include \"pruThread.h\"\n\n\n\n// Timer constructor\npruTimer::pruTimer(TIM_TypeDef* timer, IRQn_Type irq, uint32_t frequency, pruThread* ownerPtr):\n\ttimer(timer),\n\tirq(irq),\n\tfrequency(frequency),\n\ttimerOwnerPtr(ownerPtr)\n{\n\tinterruptPtr = new TimerInterrupt(this->irq, this);\t// Instantiate a new Timer Interrupt object and pass \"this\" pointer\n\n\tthis->startTimer();\n}\n\n\nvoid pruTimer::timerTick(void)\n{\n\t//Do something here\n\tthis->timerOwnerPtr->run();\n}\n\n\n\nvoid pruTimer::startTimer(void)\n{\n uint32_t TIM_CLK;\n\n if (this->timer == TIM1)\n {\n printf(\"\tpower on Timer 1\\n\\r\");\n __HAL_RCC_TIM1_CLK_ENABLE();\n TIM_CLK = APB2CLK;\n }\n else if (this->timer == TIM2)\n {\n printf(\"\tpower on Timer 2\\n\\r\");\n __HAL_RCC_TIM2_CLK_ENABLE();\n TIM_CLK = APB1CLK;\n }\n else if (this->timer == TIM3)\n {\n printf(\"\tpower on Timer 30\\n\\r\");\n __HAL_RCC_TIM3_CLK_ENABLE();\n TIM_CLK = APB1CLK;\n }\n\n\n //timer uptade frequency = TIM_CLK/(TIM_PSC+1)/(TIM_ARR + 1)\n\n this->timer->CR2 &= 0; // UG used as trigg output\n this->timer->PSC = TIM_PSC-1; // prescaler\n this->timer->ARR = ((TIM_CLK / TIM_PSC / this->frequency) - 1); // period \n this->timer->EGR = TIM_EGR_UG; // reinit the counter\n this->timer->DIER = TIM_DIER_UIE; // enable update interrupts\n\n this->timer->CR1 |= TIM_CR1_CEN; // enable timer\n\n NVIC_EnableIRQ(this->irq);\n}\n\nvoid pruTimer::stopTimer()\n{\n NVIC_DisableIRQ(this->irq);\n\n printf(\"\ttimer stop\\n\\r\");\n this->timer->CR1 &= (~(TIM_CR1_CEN)); // disable timer\n}" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F1/thread/timer.h", "content": "#ifndef TIMER_H\n#define TIMER_H\n\n#include \"mbed.h\"\n#include \n\n#define TIM_PSC 1\n#define APB1CLK SystemCoreClock\n#define APB2CLK SystemCoreClock\n\nclass TimerInterrupt; // forward declatation\nclass pruThread; // forward declatation\n\nclass pruTimer\n{\n\tfriend class TimerInterrupt;\n\n\tprivate:\n\n\t\tTimerInterrupt* \tinterruptPtr;\n\t\tTIM_TypeDef* \t timer;\n\t\tIRQn_Type \t\t\tirq;\n\t\tuint32_t \t\t\tfrequency;\n\t\tpruThread* \t\t\ttimerOwnerPtr;\n\n\t\tvoid startTimer(void);\n\t\tvoid timerTick();\t\t\t// Private timer tiggered method\n\n\tpublic:\n\n\t\tpruTimer(TIM_TypeDef* timer, IRQn_Type irq, uint32_t frequency, pruThread* ownerPtr);\n void stopTimer(void);\n\n};\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F103xC/device/TOOLCHAIN_ARM/startup_stm32f103xe.S", "content": ";******************** (C) COPYRIGHT 2017 STMicroelectronics ********************\n;* File Name : startup_stm32f103xe.s\n;* Author : MCD Application Team\n;* Description : STM32F103xE Devices vector table for MDK-ARM toolchain. \n;* This module performs:\n;* - Set the initial SP\n;* - Set the initial PC == Reset_Handler\n;* - Set the vector table entries with the exceptions ISR address\n;* - Configure the clock system\n;* - Branches to __main in the C library (which eventually\n;* calls main()).\n;* After Reset the Cortex-M3 processor is in Thread mode,\n;* priority is Privileged, and the Stack is set to Main.\n;******************************************************************************\n;* @attention\n;*\n;* Copyright (c) 2017 STMicroelectronics.\n;* All rights reserved.\n;*\n;* This software component is licensed by ST under BSD 3-Clause license,\n;* the \"License\"; You may not use this file except in compliance with the\n;* License. You may obtain a copy of the License at:\n;* opensource.org/licenses/BSD-3-Clause\n;*\n;******************************************************************************\n\n; Amount of memory (in bytes) allocated for Stack\n; Tailor this value to your application needs\n; Stack Configuration\n; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; \n\nStack_Size EQU 0x00000400\n\n AREA STACK, NOINIT, READWRITE, ALIGN=3\nStack_Mem SPACE Stack_Size\n__initial_sp\n \n; Heap Configuration\n; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>\n; \n\nHeap_Size EQU 0x00000200\n\n AREA HEAP, NOINIT, READWRITE, ALIGN=3\n__heap_base\nHeap_Mem SPACE Heap_Size\n__heap_limit\n\n PRESERVE8\n THUMB\n\n\n; Vector Table Mapped to Address 0 at Reset\n AREA RESET, DATA, READONLY\n EXPORT __Vectors\n EXPORT __Vectors_End\n EXPORT __Vectors_Size\n\n__Vectors DCD __initial_sp ; Top of Stack\n DCD Reset_Handler ; Reset Handler\n DCD NMI_Handler ; NMI Handler\n DCD HardFault_Handler ; Hard Fault Handler\n DCD MemManage_Handler ; MPU Fault Handler\n DCD BusFault_Handler ; Bus Fault Handler\n DCD UsageFault_Handler ; Usage Fault Handler\n DCD 0 ; Reserved\n DCD 0 ; Reserved\n DCD 0 ; Reserved\n DCD 0 ; Reserved\n DCD SVC_Handler ; SVCall Handler\n DCD DebugMon_Handler ; Debug Monitor Handler\n DCD 0 ; Reserved\n DCD PendSV_Handler ; PendSV Handler\n DCD SysTick_Handler ; SysTick Handler\n\n ; External Interrupts\n DCD WWDG_IRQHandler ; Window Watchdog\n DCD PVD_IRQHandler ; PVD through EXTI Line detect\n DCD TAMPER_IRQHandler ; Tamper\n DCD RTC_IRQHandler ; RTC\n DCD FLASH_IRQHandler ; Flash\n DCD RCC_IRQHandler ; RCC\n DCD EXTI0_IRQHandler ; EXTI Line 0\n DCD EXTI1_IRQHandler ; EXTI Line 1\n DCD EXTI2_IRQHandler ; EXTI Line 2\n DCD EXTI3_IRQHandler ; EXTI Line 3\n DCD EXTI4_IRQHandler ; EXTI Line 4\n DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1\n DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2\n DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3\n DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4\n DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5\n DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6\n DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7\n DCD ADC1_2_IRQHandler ; ADC1 & ADC2\n DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX\n DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0\n DCD CAN1_RX1_IRQHandler ; CAN1 RX1\n DCD CAN1_SCE_IRQHandler ; CAN1 SCE\n DCD EXTI9_5_IRQHandler ; EXTI Line 9..5\n DCD TIM1_BRK_IRQHandler ; TIM1 Break\n DCD TIM1_UP_IRQHandler ; TIM1 Update\n DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation\n DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare\n DCD TIM2_IRQHandler ; TIM2\n DCD TIM3_IRQHandler ; TIM3\n DCD TIM4_IRQHandler ; TIM4\n DCD I2C1_EV_IRQHandler ; I2C1 Event\n DCD I2C1_ER_IRQHandler ; I2C1 Error\n DCD I2C2_EV_IRQHandler ; I2C2 Event\n DCD I2C2_ER_IRQHandler ; I2C2 Error\n DCD SPI1_IRQHandler ; SPI1\n DCD SPI2_IRQHandler ; SPI2\n DCD USART1_IRQHandler ; USART1\n DCD USART2_IRQHandler ; USART2\n DCD USART3_IRQHandler ; USART3\n DCD EXTI15_10_IRQHandler ; EXTI Line 15..10\n DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line\n DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend\n DCD TIM8_BRK_IRQHandler ; TIM8 Break\n DCD TIM8_UP_IRQHandler ; TIM8 Update\n DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation\n DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare\n DCD ADC3_IRQHandler ; ADC3\n DCD FSMC_IRQHandler ; FSMC\n DCD SDIO_IRQHandler ; SDIO\n DCD TIM5_IRQHandler ; TIM5\n DCD SPI3_IRQHandler ; SPI3\n DCD UART4_IRQHandler ; UART4\n DCD UART5_IRQHandler ; UART5\n DCD TIM6_IRQHandler ; TIM6\n DCD TIM7_IRQHandler ; TIM7\n DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1\n DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2\n DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3\n DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5\n__Vectors_End\n\n__Vectors_Size EQU __Vectors_End - __Vectors\n\n AREA |.text|, CODE, READONLY\n \n; Reset handler\nReset_Handler PROC\n EXPORT Reset_Handler [WEAK]\n IMPORT __main\n IMPORT SystemInit\n LDR R0, =SystemInit\n BLX R0 \n LDR R0, =__main\n BX R0\n ENDP\n \n; Dummy Exception Handlers (infinite loops which can be modified)\n\nNMI_Handler PROC\n EXPORT NMI_Handler [WEAK]\n B .\n ENDP\nHardFault_Handler\\\n PROC\n EXPORT HardFault_Handler [WEAK]\n B .\n ENDP\nMemManage_Handler\\\n PROC\n EXPORT MemManage_Handler [WEAK]\n B .\n ENDP\nBusFault_Handler\\\n PROC\n EXPORT BusFault_Handler [WEAK]\n B .\n ENDP\nUsageFault_Handler\\\n PROC\n EXPORT UsageFault_Handler [WEAK]\n B .\n ENDP\nSVC_Handler PROC\n EXPORT SVC_Handler [WEAK]\n B .\n ENDP\nDebugMon_Handler\\\n PROC\n EXPORT DebugMon_Handler [WEAK]\n B .\n ENDP\nPendSV_Handler PROC\n EXPORT PendSV_Handler [WEAK]\n B .\n ENDP\nSysTick_Handler PROC\n EXPORT SysTick_Handler [WEAK]\n B .\n ENDP\n\nDefault_Handler PROC\n\n EXPORT WWDG_IRQHandler [WEAK]\n EXPORT PVD_IRQHandler [WEAK]\n EXPORT TAMPER_IRQHandler [WEAK]\n EXPORT RTC_IRQHandler [WEAK]\n EXPORT FLASH_IRQHandler [WEAK]\n EXPORT RCC_IRQHandler [WEAK]\n EXPORT EXTI0_IRQHandler [WEAK]\n EXPORT EXTI1_IRQHandler [WEAK]\n EXPORT EXTI2_IRQHandler [WEAK]\n EXPORT EXTI3_IRQHandler [WEAK]\n EXPORT EXTI4_IRQHandler [WEAK]\n EXPORT DMA1_Channel1_IRQHandler [WEAK]\n EXPORT DMA1_Channel2_IRQHandler [WEAK]\n EXPORT DMA1_Channel3_IRQHandler [WEAK]\n EXPORT DMA1_Channel4_IRQHandler [WEAK]\n EXPORT DMA1_Channel5_IRQHandler [WEAK]\n EXPORT DMA1_Channel6_IRQHandler [WEAK]\n EXPORT DMA1_Channel7_IRQHandler [WEAK]\n EXPORT ADC1_2_IRQHandler [WEAK]\n EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]\n EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]\n EXPORT CAN1_RX1_IRQHandler [WEAK]\n EXPORT CAN1_SCE_IRQHandler [WEAK]\n EXPORT EXTI9_5_IRQHandler [WEAK]\n EXPORT TIM1_BRK_IRQHandler [WEAK]\n EXPORT TIM1_UP_IRQHandler [WEAK]\n EXPORT TIM1_TRG_COM_IRQHandler [WEAK]\n EXPORT TIM1_CC_IRQHandler [WEAK]\n EXPORT TIM2_IRQHandler [WEAK]\n EXPORT TIM3_IRQHandler [WEAK]\n EXPORT TIM4_IRQHandler [WEAK]\n EXPORT I2C1_EV_IRQHandler [WEAK]\n EXPORT I2C1_ER_IRQHandler [WEAK]\n EXPORT I2C2_EV_IRQHandler [WEAK]\n EXPORT I2C2_ER_IRQHandler [WEAK]\n EXPORT SPI1_IRQHandler [WEAK]\n EXPORT SPI2_IRQHandler [WEAK]\n EXPORT USART1_IRQHandler [WEAK]\n EXPORT USART2_IRQHandler [WEAK]\n EXPORT USART3_IRQHandler [WEAK]\n EXPORT EXTI15_10_IRQHandler [WEAK]\n EXPORT RTC_Alarm_IRQHandler [WEAK]\n EXPORT USBWakeUp_IRQHandler [WEAK]\n EXPORT TIM8_BRK_IRQHandler [WEAK]\n EXPORT TIM8_UP_IRQHandler [WEAK]\n EXPORT TIM8_TRG_COM_IRQHandler [WEAK]\n EXPORT TIM8_CC_IRQHandler [WEAK]\n EXPORT ADC3_IRQHandler [WEAK]\n EXPORT FSMC_IRQHandler [WEAK]\n EXPORT SDIO_IRQHandler [WEAK]\n EXPORT TIM5_IRQHandler [WEAK]\n EXPORT SPI3_IRQHandler [WEAK]\n EXPORT UART4_IRQHandler [WEAK]\n EXPORT UART5_IRQHandler [WEAK]\n EXPORT TIM6_IRQHandler [WEAK]\n EXPORT TIM7_IRQHandler [WEAK]\n EXPORT DMA2_Channel1_IRQHandler [WEAK]\n EXPORT DMA2_Channel2_IRQHandler [WEAK]\n EXPORT DMA2_Channel3_IRQHandler [WEAK]\n EXPORT DMA2_Channel4_5_IRQHandler [WEAK]\n\nWWDG_IRQHandler\nPVD_IRQHandler\nTAMPER_IRQHandler\nRTC_IRQHandler\nFLASH_IRQHandler\nRCC_IRQHandler\nEXTI0_IRQHandler\nEXTI1_IRQHandler\nEXTI2_IRQHandler\nEXTI3_IRQHandler\nEXTI4_IRQHandler\nDMA1_Channel1_IRQHandler\nDMA1_Channel2_IRQHandler\nDMA1_Channel3_IRQHandler\nDMA1_Channel4_IRQHandler\nDMA1_Channel5_IRQHandler\nDMA1_Channel6_IRQHandler\nDMA1_Channel7_IRQHandler\nADC1_2_IRQHandler\nUSB_HP_CAN1_TX_IRQHandler\nUSB_LP_CAN1_RX0_IRQHandler\nCAN1_RX1_IRQHandler\nCAN1_SCE_IRQHandler\nEXTI9_5_IRQHandler\nTIM1_BRK_IRQHandler\nTIM1_UP_IRQHandler\nTIM1_TRG_COM_IRQHandler\nTIM1_CC_IRQHandler\nTIM2_IRQHandler\nTIM3_IRQHandler\nTIM4_IRQHandler\nI2C1_EV_IRQHandler\nI2C1_ER_IRQHandler\nI2C2_EV_IRQHandler\nI2C2_ER_IRQHandler\nSPI1_IRQHandler\nSPI2_IRQHandler\nUSART1_IRQHandler\nUSART2_IRQHandler\nUSART3_IRQHandler\nEXTI15_10_IRQHandler\nRTC_Alarm_IRQHandler\nUSBWakeUp_IRQHandler\nTIM8_BRK_IRQHandler\nTIM8_UP_IRQHandler\nTIM8_TRG_COM_IRQHandler\nTIM8_CC_IRQHandler\nADC3_IRQHandler\nFSMC_IRQHandler\nSDIO_IRQHandler\nTIM5_IRQHandler\nSPI3_IRQHandler\nUART4_IRQHandler\nUART5_IRQHandler\nTIM6_IRQHandler\nTIM7_IRQHandler\nDMA2_Channel1_IRQHandler\nDMA2_Channel2_IRQHandler\nDMA2_Channel3_IRQHandler\nDMA2_Channel4_5_IRQHandler\n B .\n\n ENDP\n\n ALIGN\n\n;*******************************************************************************\n; User Stack and Heap initialization\n;*******************************************************************************\n\n END\n\n;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F103xC/device/TOOLCHAIN_ARM/stm32f103xe.sct", "content": "#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m3\n; Scatter-Loading Description File\n;\n; SPDX-License-Identifier: BSD-3-Clause\n;******************************************************************************\n;* @attention\n;*\n;* Copyright (c) 2016-2020 STMicroelectronics.\n;* All rights reserved.\n;*\n;* This software component is licensed by ST under BSD 3-Clause license,\n;* the \"License\"; You may not use this file except in compliance with the\n;* License. You may obtain a copy of the License at:\n;* opensource.org/licenses/BSD-3-Clause\n;*\n;******************************************************************************\n\n#include \"../cmsis_nvic.h\"\n\n#if !defined(MBED_APP_START)\n #define MBED_APP_START MBED_ROM_START\n#endif\n\n#if !defined(MBED_APP_SIZE)\n #define MBED_APP_SIZE MBED_ROM_SIZE\n#endif\n\n/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */\n#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)\n# if defined(MBED_BOOT_STACK_SIZE)\n# define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE\n# else\n# define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400\n# endif\n#endif\n\n/* Round up VECTORS_SIZE to 8 bytes */\n#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)\n\nLR_IROM1 MBED_APP_START MBED_APP_SIZE {\n\n ER_IROM1 MBED_APP_START MBED_APP_SIZE {\n *.o (RESET, +First)\n *(InRoot$$Sections)\n .ANY (+RO)\n }\n\n RW_IRAM1 (MBED_RAM_START + VECTORS_SIZE) { ; RW data\n .ANY (+RW +ZI)\n }\n\n ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up\n }\n\n ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down\n }\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F103xC/device/cmsis_nvic.h", "content": "/* mbed Microcontroller Library\n * SPDX-License-Identifier: BSD-3-Clause\n ******************************************************************************\n * @attention\n *\n *

© Copyright (c) 2016-2020 STMicroelectronics.\n * All rights reserved.

\n *\n * This software component is licensed by ST under BSD 3-Clause license,\n * the \"License\"; You may not use this file except in compliance with the\n * License. You may obtain a copy of the License at:\n * opensource.org/licenses/BSD-3-Clause\n *\n ******************************************************************************\n*/\n\n#ifndef MBED_CMSIS_NVIC_H\n#define MBED_CMSIS_NVIC_H\n\n#if !defined(MBED_ROM_START)\n#define MBED_ROM_START 0x8000000\n#endif\n\n#if !defined(MBED_ROM_SIZE)\n#define MBED_ROM_SIZE 0x40000 // 256 KB\n#endif\n\n#if !defined(MBED_RAM_START)\n#define MBED_RAM_START 0x20000000\n#endif\n\n#if !defined(MBED_RAM_SIZE)\n#define MBED_RAM_SIZE 0xC000 // 48 KB\n#endif\n\n#define NVIC_NUM_VECTORS 76\n#define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F103xC/device/stm32f103xe.h", "content": "/**\n ******************************************************************************\n * @file stm32f103xe.h\n * @author MCD Application Team\n * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. \n * This file contains all the peripheral register's definitions, bits \n * definitions and memory mapping for STM32F1xx devices. \n * \n * This file contains:\n * - Data structures and the address mapping for all peripherals\n * - Peripheral's registers declarations and bits definition\n * - Macros to access peripherals registers hardware\n * \n ******************************************************************************\n * @attention\n *\n *

© Copyright (c) 2017 STMicroelectronics.\n * All rights reserved.

\n *\n * This software component is licensed by ST under BSD 3-Clause license,\n * the \"License\"; You may not use this file except in compliance with the\n * License. You may obtain a copy of the License at:\n * opensource.org/licenses/BSD-3-Clause\n *\n ******************************************************************************\n */\n\n\n/** @addtogroup CMSIS\n * @{\n */\n\n/** @addtogroup stm32f103xe\n * @{\n */\n \n#ifndef __STM32F103xE_H\n#define __STM32F103xE_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif \n\n/** @addtogroup Configuration_section_for_CMSIS\n * @{\n */\n/**\n * @brief Configuration of the Cortex-M3 Processor and Core Peripherals \n */\n#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */\n #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */\n#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */\n#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */\n\n/**\n * @}\n */\n\n/** @addtogroup Peripheral_interrupt_number_definition\n * @{\n */\n\n/**\n * @brief STM32F10x Interrupt Number Definition, according to the selected device \n * in @ref Library_configuration_section \n */\n\n /*!< Interrupt Number Definition */\ntypedef enum\n{\n/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/\n NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\n HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\n MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\n BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\n UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\n SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\n DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\n PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\n SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */\n\n/****** STM32 specific Interrupt Numbers *********************************************************/\n WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\n PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\n TAMPER_IRQn = 2, /*!< Tamper Interrupt */\n RTC_IRQn = 3, /*!< RTC global Interrupt */\n FLASH_IRQn = 4, /*!< FLASH global Interrupt */\n RCC_IRQn = 5, /*!< RCC global Interrupt */\n EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\n EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\n EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\n EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\n EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\n DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */\n DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */\n DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */\n DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */\n DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */\n DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */\n DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */\n ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\n USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\n USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\n CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\n CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\n EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\n TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */\n TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */\n TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */\n TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\n TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\n TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\n TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\n I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\n I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\n I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\n I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\n SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\n SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\n USART1_IRQn = 37, /*!< USART1 global Interrupt */\n USART2_IRQn = 38, /*!< USART2 global Interrupt */\n USART3_IRQn = 39, /*!< USART3 global Interrupt */\n EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\n RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\n USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */\n TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */\n TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */\n TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */\n TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\n ADC3_IRQn = 47, /*!< ADC3 global Interrupt */\n FSMC_IRQn = 48, /*!< FSMC global Interrupt */\n SDIO_IRQn = 49, /*!< SDIO global Interrupt */\n TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\n SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\n UART4_IRQn = 52, /*!< UART4 global Interrupt */\n UART5_IRQn = 53, /*!< UART5 global Interrupt */\n TIM6_IRQn = 54, /*!< TIM6 global Interrupt */\n TIM7_IRQn = 55, /*!< TIM7 global Interrupt */\n DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */\n DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */\n DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */\n DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */\n} IRQn_Type;\n\n/**\n * @}\n */\n\n#include \"core_cm3.h\"\n#include \"system_stm32f1xx.h\"\n#include \n\n/** @addtogroup Peripheral_registers_structures\n * @{\n */ \n\n/** \n * @brief Analog to Digital Converter \n */\n\ntypedef struct\n{\n __IO uint32_t SR;\n __IO uint32_t CR1;\n __IO uint32_t CR2;\n __IO uint32_t SMPR1;\n __IO uint32_t SMPR2;\n __IO uint32_t JOFR1;\n __IO uint32_t JOFR2;\n __IO uint32_t JOFR3;\n __IO uint32_t JOFR4;\n __IO uint32_t HTR;\n __IO uint32_t LTR;\n __IO uint32_t SQR1;\n __IO uint32_t SQR2;\n __IO uint32_t SQR3;\n __IO uint32_t JSQR;\n __IO uint32_t JDR1;\n __IO uint32_t JDR2;\n __IO uint32_t JDR3;\n __IO uint32_t JDR4;\n __IO uint32_t DR;\n} ADC_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */\n __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */\n __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */\n uint32_t RESERVED[16];\n __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */\n} ADC_Common_TypeDef;\n\n/** \n * @brief Backup Registers \n */\n\ntypedef struct\n{\n uint32_t RESERVED0;\n __IO uint32_t DR1;\n __IO uint32_t DR2;\n __IO uint32_t DR3;\n __IO uint32_t DR4;\n __IO uint32_t DR5;\n __IO uint32_t DR6;\n __IO uint32_t DR7;\n __IO uint32_t DR8;\n __IO uint32_t DR9;\n __IO uint32_t DR10;\n __IO uint32_t RTCCR;\n __IO uint32_t CR;\n __IO uint32_t CSR;\n uint32_t RESERVED13[2];\n __IO uint32_t DR11;\n __IO uint32_t DR12;\n __IO uint32_t DR13;\n __IO uint32_t DR14;\n __IO uint32_t DR15;\n __IO uint32_t DR16;\n __IO uint32_t DR17;\n __IO uint32_t DR18;\n __IO uint32_t DR19;\n __IO uint32_t DR20;\n __IO uint32_t DR21;\n __IO uint32_t DR22;\n __IO uint32_t DR23;\n __IO uint32_t DR24;\n __IO uint32_t DR25;\n __IO uint32_t DR26;\n __IO uint32_t DR27;\n __IO uint32_t DR28;\n __IO uint32_t DR29;\n __IO uint32_t DR30;\n __IO uint32_t DR31;\n __IO uint32_t DR32;\n __IO uint32_t DR33;\n __IO uint32_t DR34;\n __IO uint32_t DR35;\n __IO uint32_t DR36;\n __IO uint32_t DR37;\n __IO uint32_t DR38;\n __IO uint32_t DR39;\n __IO uint32_t DR40;\n __IO uint32_t DR41;\n __IO uint32_t DR42;\n} BKP_TypeDef;\n \n/** \n * @brief Controller Area Network TxMailBox \n */\n\ntypedef struct\n{\n __IO uint32_t TIR;\n __IO uint32_t TDTR;\n __IO uint32_t TDLR;\n __IO uint32_t TDHR;\n} CAN_TxMailBox_TypeDef;\n\n/** \n * @brief Controller Area Network FIFOMailBox \n */\n \ntypedef struct\n{\n __IO uint32_t RIR;\n __IO uint32_t RDTR;\n __IO uint32_t RDLR;\n __IO uint32_t RDHR;\n} CAN_FIFOMailBox_TypeDef;\n\n/** \n * @brief Controller Area Network FilterRegister \n */\n \ntypedef struct\n{\n __IO uint32_t FR1;\n __IO uint32_t FR2;\n} CAN_FilterRegister_TypeDef;\n\n/** \n * @brief Controller Area Network \n */\n \ntypedef struct\n{\n __IO uint32_t MCR;\n __IO uint32_t MSR;\n __IO uint32_t TSR;\n __IO uint32_t RF0R;\n __IO uint32_t RF1R;\n __IO uint32_t IER;\n __IO uint32_t ESR;\n __IO uint32_t BTR;\n uint32_t RESERVED0[88];\n CAN_TxMailBox_TypeDef sTxMailBox[3];\n CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];\n uint32_t RESERVED1[12];\n __IO uint32_t FMR;\n __IO uint32_t FM1R;\n uint32_t RESERVED2;\n __IO uint32_t FS1R;\n uint32_t RESERVED3;\n __IO uint32_t FFA1R;\n uint32_t RESERVED4;\n __IO uint32_t FA1R;\n uint32_t RESERVED5[8];\n CAN_FilterRegister_TypeDef sFilterRegister[14];\n} CAN_TypeDef;\n\n/** \n * @brief CRC calculation unit \n */\n\ntypedef struct\n{\n __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */\n __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */\n uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */\n uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ \n __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ \n} CRC_TypeDef;\n\n/** \n * @brief Digital to Analog Converter\n */\n\ntypedef struct\n{\n __IO uint32_t CR;\n __IO uint32_t SWTRIGR;\n __IO uint32_t DHR12R1;\n __IO uint32_t DHR12L1;\n __IO uint32_t DHR8R1;\n __IO uint32_t DHR12R2;\n __IO uint32_t DHR12L2;\n __IO uint32_t DHR8R2;\n __IO uint32_t DHR12RD;\n __IO uint32_t DHR12LD;\n __IO uint32_t DHR8RD;\n __IO uint32_t DOR1;\n __IO uint32_t DOR2;\n} DAC_TypeDef;\n\n/** \n * @brief Debug MCU\n */\n\ntypedef struct\n{\n __IO uint32_t IDCODE;\n __IO uint32_t CR;\n}DBGMCU_TypeDef;\n\n/** \n * @brief DMA Controller\n */\n\ntypedef struct\n{\n __IO uint32_t CCR;\n __IO uint32_t CNDTR;\n __IO uint32_t CPAR;\n __IO uint32_t CMAR;\n} DMA_Channel_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t ISR;\n __IO uint32_t IFCR;\n} DMA_TypeDef;\n\n\n\n/** \n * @brief External Interrupt/Event Controller\n */\n\ntypedef struct\n{\n __IO uint32_t IMR;\n __IO uint32_t EMR;\n __IO uint32_t RTSR;\n __IO uint32_t FTSR;\n __IO uint32_t SWIER;\n __IO uint32_t PR;\n} EXTI_TypeDef;\n\n/** \n * @brief FLASH Registers\n */\n\ntypedef struct\n{\n __IO uint32_t ACR;\n __IO uint32_t KEYR;\n __IO uint32_t OPTKEYR;\n __IO uint32_t SR;\n __IO uint32_t CR;\n __IO uint32_t AR;\n __IO uint32_t RESERVED;\n __IO uint32_t OBR;\n __IO uint32_t WRPR;\n} FLASH_TypeDef;\n\n/** \n * @brief Option Bytes Registers\n */\n \ntypedef struct\n{\n __IO uint16_t RDP;\n __IO uint16_t USER;\n __IO uint16_t Data0;\n __IO uint16_t Data1;\n __IO uint16_t WRP0;\n __IO uint16_t WRP1;\n __IO uint16_t WRP2;\n __IO uint16_t WRP3;\n} OB_TypeDef;\n\n/** \n * @brief Flexible Static Memory Controller\n */\n\ntypedef struct\n{\n __IO uint32_t BTCR[8]; \n} FSMC_Bank1_TypeDef; \n\n/** \n * @brief Flexible Static Memory Controller Bank1E\n */\n \ntypedef struct\n{\n __IO uint32_t BWTR[7];\n} FSMC_Bank1E_TypeDef;\n\n/** \n * @brief Flexible Static Memory Controller Bank2\n */\n \ntypedef struct\n{\n __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */\n __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */\n __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */\n __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\n uint32_t RESERVED0; /*!< Reserved, 0x70 */\n __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */\n uint32_t RESERVED1; /*!< Reserved, 0x78 */\n uint32_t RESERVED2; /*!< Reserved, 0x7C */\n __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */\n __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */\n __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */\n __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\n uint32_t RESERVED3; /*!< Reserved, 0x90 */\n __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */\n} FSMC_Bank2_3_TypeDef; \n\n/** \n * @brief Flexible Static Memory Controller Bank4\n */\n \ntypedef struct\n{\n __IO uint32_t PCR4;\n __IO uint32_t SR4;\n __IO uint32_t PMEM4;\n __IO uint32_t PATT4;\n __IO uint32_t PIO4; \n} FSMC_Bank4_TypeDef; \n\n/** \n * @brief General Purpose I/O\n */\n\ntypedef struct\n{\n __IO uint32_t CRL;\n __IO uint32_t CRH;\n __IO uint32_t IDR;\n __IO uint32_t ODR;\n __IO uint32_t BSRR;\n __IO uint32_t BRR;\n __IO uint32_t LCKR;\n} GPIO_TypeDef;\n\n/** \n * @brief Alternate Function I/O\n */\n\ntypedef struct\n{\n __IO uint32_t EVCR;\n __IO uint32_t MAPR;\n __IO uint32_t EXTICR[4];\n uint32_t RESERVED0;\n __IO uint32_t MAPR2; \n} AFIO_TypeDef;\n/** \n * @brief Inter Integrated Circuit Interface\n */\n\ntypedef struct\n{\n __IO uint32_t CR1;\n __IO uint32_t CR2;\n __IO uint32_t OAR1;\n __IO uint32_t OAR2;\n __IO uint32_t DR;\n __IO uint32_t SR1;\n __IO uint32_t SR2;\n __IO uint32_t CCR;\n __IO uint32_t TRISE;\n} I2C_TypeDef;\n\n/** \n * @brief Independent WATCHDOG\n */\n\ntypedef struct\n{\n __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */\n __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */\n __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */\n __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */\n} IWDG_TypeDef;\n\n/** \n * @brief Power Control\n */\n\ntypedef struct\n{\n __IO uint32_t CR;\n __IO uint32_t CSR;\n} PWR_TypeDef;\n\n/** \n * @brief Reset and Clock Control\n */\n\ntypedef struct\n{\n __IO uint32_t CR;\n __IO uint32_t CFGR;\n __IO uint32_t CIR;\n __IO uint32_t APB2RSTR;\n __IO uint32_t APB1RSTR;\n __IO uint32_t AHBENR;\n __IO uint32_t APB2ENR;\n __IO uint32_t APB1ENR;\n __IO uint32_t BDCR;\n __IO uint32_t CSR;\n\n\n} RCC_TypeDef;\n\n/** \n * @brief Real-Time Clock\n */\n\ntypedef struct\n{\n __IO uint32_t CRH;\n __IO uint32_t CRL;\n __IO uint32_t PRLH;\n __IO uint32_t PRLL;\n __IO uint32_t DIVH;\n __IO uint32_t DIVL;\n __IO uint32_t CNTH;\n __IO uint32_t CNTL;\n __IO uint32_t ALRH;\n __IO uint32_t ALRL;\n} RTC_TypeDef;\n\n/** \n * @brief SD host Interface\n */\n\ntypedef struct\n{\n __IO uint32_t POWER;\n __IO uint32_t CLKCR;\n __IO uint32_t ARG;\n __IO uint32_t CMD;\n __I uint32_t RESPCMD;\n __I uint32_t RESP1;\n __I uint32_t RESP2;\n __I uint32_t RESP3;\n __I uint32_t RESP4;\n __IO uint32_t DTIMER;\n __IO uint32_t DLEN;\n __IO uint32_t DCTRL;\n __I uint32_t DCOUNT;\n __I uint32_t STA;\n __IO uint32_t ICR;\n __IO uint32_t MASK;\n uint32_t RESERVED0[2];\n __I uint32_t FIFOCNT;\n uint32_t RESERVED1[13];\n __IO uint32_t FIFO;\n} SDIO_TypeDef;\n\n/** \n * @brief Serial Peripheral Interface\n */\n\ntypedef struct\n{\n __IO uint32_t CR1;\n __IO uint32_t CR2;\n __IO uint32_t SR;\n __IO uint32_t DR;\n __IO uint32_t CRCPR;\n __IO uint32_t RXCRCR;\n __IO uint32_t TXCRCR;\n __IO uint32_t I2SCFGR;\n __IO uint32_t I2SPR;\n} SPI_TypeDef;\n\n/**\n * @brief TIM Timers\n */\ntypedef struct\n{\n __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */\n __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */\n __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */\n __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */\n __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */\n __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\n __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\n __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */\n __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */\n __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */\n __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */\n __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */\n __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */\n __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */\n __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */\n __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */\n __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */\n __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */\n __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */\n __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */\n}TIM_TypeDef;\n\n\n/** \n * @brief Universal Synchronous Asynchronous Receiver Transmitter\n */\n \ntypedef struct\n{\n __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */\n __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */\n __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */\n __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */\n __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */\n __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */\n __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */\n} USART_TypeDef;\n\n/** \n * @brief Universal Serial Bus Full Speed Device\n */\n \ntypedef struct\n{\n __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ \n __IO uint16_t RESERVED0; /*!< Reserved */ \n __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */\n __IO uint16_t RESERVED1; /*!< Reserved */ \n __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */\n __IO uint16_t RESERVED2; /*!< Reserved */ \n __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ \n __IO uint16_t RESERVED3; /*!< Reserved */ \n __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */\n __IO uint16_t RESERVED4; /*!< Reserved */ \n __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */\n __IO uint16_t RESERVED5; /*!< Reserved */ \n __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */\n __IO uint16_t RESERVED6; /*!< Reserved */ \n __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */\n __IO uint16_t RESERVED7[17]; /*!< Reserved */ \n __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */\n __IO uint16_t RESERVED8; /*!< Reserved */ \n __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */\n __IO uint16_t RESERVED9; /*!< Reserved */ \n __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */\n __IO uint16_t RESERVEDA; /*!< Reserved */ \n __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */\n __IO uint16_t RESERVEDB; /*!< Reserved */ \n __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */\n __IO uint16_t RESERVEDC; /*!< Reserved */ \n} USB_TypeDef;\n\n\n/** \n * @brief Window WATCHDOG\n */\n\ntypedef struct\n{\n __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */\n __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */\n __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */\n} WWDG_TypeDef;\n\n/**\n * @}\n */\n \n/** @addtogroup Peripheral_memory_map\n * @{\n */\n\n\n#define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */\n#define FLASH_BANK1_END 0x0807FFFFUL /*!< FLASH END address of bank1 */\n#define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */\n#define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */\n\n#define SRAM_BB_BASE 0x22000000UL /*!< SRAM base address in the bit-band region */\n#define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */\n\n#define FSMC_BASE 0x60000000UL /*!< FSMC base address */\n#define FSMC_R_BASE 0xA0000000UL /*!< FSMC registers base address */\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE PERIPH_BASE\n#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)\n#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)\n\n#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)\n#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)\n#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)\n#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL)\n#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL)\n#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL)\n#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)\n#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)\n#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)\n#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)\n#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL)\n#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)\n#define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)\n#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL)\n#define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL)\n#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)\n#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)\n#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL)\n#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL)\n#define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)\n#define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL)\n#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL)\n#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)\n#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL)\n#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL)\n#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL)\n#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL)\n#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL)\n#define GPIOF_BASE (APB2PERIPH_BASE + 0x00001C00UL)\n#define GPIOG_BASE (APB2PERIPH_BASE + 0x00002000UL)\n#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL)\n#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL)\n#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)\n#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)\n#define TIM8_BASE (APB2PERIPH_BASE + 0x00003400UL)\n#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)\n#define ADC3_BASE (APB2PERIPH_BASE + 0x00003C00UL)\n\n#define SDIO_BASE (PERIPH_BASE + 0x00018000UL)\n\n#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)\n#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL)\n#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL)\n#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL)\n#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL)\n#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL)\n#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL)\n#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL)\n#define DMA2_BASE (AHBPERIPH_BASE + 0x00000400UL)\n#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408UL)\n#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CUL)\n#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430UL)\n#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444UL)\n#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458UL)\n#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)\n#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)\n\n#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */\n#define FLASHSIZE_BASE 0x1FFFF7E0UL /*!< FLASH Size register base address */\n#define UID_BASE 0x1FFFF7E8UL /*!< Unique device ID register base address */\n#define OB_BASE 0x1FFFF800UL /*!< Flash Option Bytes base address */\n\n\n#define FSMC_BANK1 (FSMC_BASE) /*!< FSMC Bank1 base address */\n#define FSMC_BANK1_1 (FSMC_BANK1) /*!< FSMC Bank1_1 base address */\n#define FSMC_BANK1_2 (FSMC_BANK1 + 0x04000000UL) /*!< FSMC Bank1_2 base address */\n#define FSMC_BANK1_3 (FSMC_BANK1 + 0x08000000UL) /*!< FSMC Bank1_3 base address */\n#define FSMC_BANK1_4 (FSMC_BANK1 + 0x0C000000UL) /*!< FSMC Bank1_4 base address */\n\n#define FSMC_BANK2 (FSMC_BASE + 0x10000000UL) /*!< FSMC Bank2 base address */\n#define FSMC_BANK3 (FSMC_BASE + 0x20000000UL) /*!< FSMC Bank3 base address */\n#define FSMC_BANK4 (FSMC_BASE + 0x30000000UL) /*!< FSMC Bank4 base address */\n\n#define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x00000000UL) /*!< FSMC Bank1 registers base address */\n#define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x00000104UL) /*!< FSMC Bank1E registers base address */\n#define FSMC_BANK2_3_R_BASE (FSMC_R_BASE + 0x00000060UL) /*!< FSMC Bank2/Bank3 registers base address */\n#define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x000000A0UL) /*!< FSMC Bank4 registers base address */\n\n#define DBGMCU_BASE 0xE0042000UL /*!< Debug MCU registers base address */\n\n/* USB device FS */\n#define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */\n#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */\n\n\n/**\n * @}\n */\n \n/** @addtogroup Peripheral_declaration\n * @{\n */ \n\n#define TIM2 ((TIM_TypeDef *)TIM2_BASE)\n#define TIM3 ((TIM_TypeDef *)TIM3_BASE)\n#define TIM4 ((TIM_TypeDef *)TIM4_BASE)\n#define TIM5 ((TIM_TypeDef *)TIM5_BASE)\n#define TIM6 ((TIM_TypeDef *)TIM6_BASE)\n#define TIM7 ((TIM_TypeDef *)TIM7_BASE)\n#define RTC ((RTC_TypeDef *)RTC_BASE)\n#define WWDG ((WWDG_TypeDef *)WWDG_BASE)\n#define IWDG ((IWDG_TypeDef *)IWDG_BASE)\n#define SPI2 ((SPI_TypeDef *)SPI2_BASE)\n#define SPI3 ((SPI_TypeDef *)SPI3_BASE)\n#define USART2 ((USART_TypeDef *)USART2_BASE)\n#define USART3 ((USART_TypeDef *)USART3_BASE)\n#define UART4 ((USART_TypeDef *)UART4_BASE)\n#define UART5 ((USART_TypeDef *)UART5_BASE)\n#define I2C1 ((I2C_TypeDef *)I2C1_BASE)\n#define I2C2 ((I2C_TypeDef *)I2C2_BASE)\n#define USB ((USB_TypeDef *)USB_BASE)\n#define CAN1 ((CAN_TypeDef *)CAN1_BASE)\n#define BKP ((BKP_TypeDef *)BKP_BASE)\n#define PWR ((PWR_TypeDef *)PWR_BASE)\n#define DAC1 ((DAC_TypeDef *)DAC_BASE)\n#define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */\n#define AFIO ((AFIO_TypeDef *)AFIO_BASE)\n#define EXTI ((EXTI_TypeDef *)EXTI_BASE)\n#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)\n#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)\n#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)\n#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)\n#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)\n#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE)\n#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE)\n#define ADC1 ((ADC_TypeDef *)ADC1_BASE)\n#define ADC2 ((ADC_TypeDef *)ADC2_BASE)\n#define ADC3 ((ADC_TypeDef *)ADC3_BASE)\n#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)\n#define TIM1 ((TIM_TypeDef *)TIM1_BASE)\n#define SPI1 ((SPI_TypeDef *)SPI1_BASE)\n#define TIM8 ((TIM_TypeDef *)TIM8_BASE)\n#define USART1 ((USART_TypeDef *)USART1_BASE)\n#define SDIO ((SDIO_TypeDef *)SDIO_BASE)\n#define DMA1 ((DMA_TypeDef *)DMA1_BASE)\n#define DMA2 ((DMA_TypeDef *)DMA2_BASE)\n#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)\n#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)\n#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)\n#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)\n#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)\n#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)\n#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)\n#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)\n#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)\n#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)\n#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)\n#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)\n#define RCC ((RCC_TypeDef *)RCC_BASE)\n#define CRC ((CRC_TypeDef *)CRC_BASE)\n#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)\n#define OB ((OB_TypeDef *)OB_BASE)\n#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *)FSMC_BANK1_R_BASE)\n#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *)FSMC_BANK1E_R_BASE)\n#define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *)FSMC_BANK2_3_R_BASE)\n#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *)FSMC_BANK4_R_BASE)\n#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)\n\n\n/**\n * @}\n */\n\n/** @addtogroup Exported_constants\n * @{\n */\n \n /** @addtogroup Peripheral_Registers_Bits_Definition\n * @{\n */\n \n/******************************************************************************/\n/* Peripheral Registers_Bits_Definition */\n/******************************************************************************/\n\n/******************************************************************************/\n/* */\n/* CRC calculation unit (CRC) */\n/* */\n/******************************************************************************/\n\n/******************* Bit definition for CRC_DR register *********************/\n#define CRC_DR_DR_Pos (0U) \n#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */\n#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */\n\n/******************* Bit definition for CRC_IDR register ********************/\n#define CRC_IDR_IDR_Pos (0U) \n#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */\n#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */\n\n/******************** Bit definition for CRC_CR register ********************/\n#define CRC_CR_RESET_Pos (0U) \n#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */\n#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */\n\n/******************************************************************************/\n/* */\n/* Power Control */\n/* */\n/******************************************************************************/\n\n/******************** Bit definition for PWR_CR register ********************/\n#define PWR_CR_LPDS_Pos (0U) \n#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */\n#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */\n#define PWR_CR_PDDS_Pos (1U) \n#define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */\n#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */\n#define PWR_CR_CWUF_Pos (2U) \n#define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */\n#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */\n#define PWR_CR_CSBF_Pos (3U) \n#define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */\n#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */\n#define PWR_CR_PVDE_Pos (4U) \n#define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */\n#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */\n\n#define PWR_CR_PLS_Pos (5U) \n#define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */\n#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */\n#define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */\n#define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */\n#define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */\n\n/*!< PVD level configuration */\n#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */\n#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */\n#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */\n#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */\n#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */\n#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */\n#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */\n#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */\n\n/* Legacy defines */\n#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0\n#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1\n#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2\n#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3\n#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4\n#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5\n#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6\n#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7\n\n#define PWR_CR_DBP_Pos (8U) \n#define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */\n#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */\n\n\n/******************* Bit definition for PWR_CSR register ********************/\n#define PWR_CSR_WUF_Pos (0U) \n#define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */\n#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */\n#define PWR_CSR_SBF_Pos (1U) \n#define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */\n#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */\n#define PWR_CSR_PVDO_Pos (2U) \n#define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */\n#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */\n#define PWR_CSR_EWUP_Pos (8U) \n#define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */\n#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */\n\n/******************************************************************************/\n/* */\n/* Backup registers */\n/* */\n/******************************************************************************/\n\n/******************* Bit definition for BKP_DR1 register ********************/\n#define BKP_DR1_D_Pos (0U) \n#define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR2 register ********************/\n#define BKP_DR2_D_Pos (0U) \n#define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR3 register ********************/\n#define BKP_DR3_D_Pos (0U) \n#define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR4 register ********************/\n#define BKP_DR4_D_Pos (0U) \n#define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR5 register ********************/\n#define BKP_DR5_D_Pos (0U) \n#define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR6 register ********************/\n#define BKP_DR6_D_Pos (0U) \n#define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR7 register ********************/\n#define BKP_DR7_D_Pos (0U) \n#define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR8 register ********************/\n#define BKP_DR8_D_Pos (0U) \n#define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR9 register ********************/\n#define BKP_DR9_D_Pos (0U) \n#define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR10 register *******************/\n#define BKP_DR10_D_Pos (0U) \n#define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR11 register *******************/\n#define BKP_DR11_D_Pos (0U) \n#define BKP_DR11_D_Msk (0xFFFFUL << BKP_DR11_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR11_D BKP_DR11_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR12 register *******************/\n#define BKP_DR12_D_Pos (0U) \n#define BKP_DR12_D_Msk (0xFFFFUL << BKP_DR12_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR12_D BKP_DR12_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR13 register *******************/\n#define BKP_DR13_D_Pos (0U) \n#define BKP_DR13_D_Msk (0xFFFFUL << BKP_DR13_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR13_D BKP_DR13_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR14 register *******************/\n#define BKP_DR14_D_Pos (0U) \n#define BKP_DR14_D_Msk (0xFFFFUL << BKP_DR14_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR14_D BKP_DR14_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR15 register *******************/\n#define BKP_DR15_D_Pos (0U) \n#define BKP_DR15_D_Msk (0xFFFFUL << BKP_DR15_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR15_D BKP_DR15_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR16 register *******************/\n#define BKP_DR16_D_Pos (0U) \n#define BKP_DR16_D_Msk (0xFFFFUL << BKP_DR16_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR16_D BKP_DR16_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR17 register *******************/\n#define BKP_DR17_D_Pos (0U) \n#define BKP_DR17_D_Msk (0xFFFFUL << BKP_DR17_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR17_D BKP_DR17_D_Msk /*!< Backup data */\n\n/****************** Bit definition for BKP_DR18 register ********************/\n#define BKP_DR18_D_Pos (0U) \n#define BKP_DR18_D_Msk (0xFFFFUL << BKP_DR18_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR18_D BKP_DR18_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR19 register *******************/\n#define BKP_DR19_D_Pos (0U) \n#define BKP_DR19_D_Msk (0xFFFFUL << BKP_DR19_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR19_D BKP_DR19_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR20 register *******************/\n#define BKP_DR20_D_Pos (0U) \n#define BKP_DR20_D_Msk (0xFFFFUL << BKP_DR20_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR20_D BKP_DR20_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR21 register *******************/\n#define BKP_DR21_D_Pos (0U) \n#define BKP_DR21_D_Msk (0xFFFFUL << BKP_DR21_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR21_D BKP_DR21_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR22 register *******************/\n#define BKP_DR22_D_Pos (0U) \n#define BKP_DR22_D_Msk (0xFFFFUL << BKP_DR22_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR22_D BKP_DR22_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR23 register *******************/\n#define BKP_DR23_D_Pos (0U) \n#define BKP_DR23_D_Msk (0xFFFFUL << BKP_DR23_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR23_D BKP_DR23_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR24 register *******************/\n#define BKP_DR24_D_Pos (0U) \n#define BKP_DR24_D_Msk (0xFFFFUL << BKP_DR24_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR24_D BKP_DR24_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR25 register *******************/\n#define BKP_DR25_D_Pos (0U) \n#define BKP_DR25_D_Msk (0xFFFFUL << BKP_DR25_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR25_D BKP_DR25_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR26 register *******************/\n#define BKP_DR26_D_Pos (0U) \n#define BKP_DR26_D_Msk (0xFFFFUL << BKP_DR26_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR26_D BKP_DR26_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR27 register *******************/\n#define BKP_DR27_D_Pos (0U) \n#define BKP_DR27_D_Msk (0xFFFFUL << BKP_DR27_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR27_D BKP_DR27_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR28 register *******************/\n#define BKP_DR28_D_Pos (0U) \n#define BKP_DR28_D_Msk (0xFFFFUL << BKP_DR28_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR28_D BKP_DR28_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR29 register *******************/\n#define BKP_DR29_D_Pos (0U) \n#define BKP_DR29_D_Msk (0xFFFFUL << BKP_DR29_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR29_D BKP_DR29_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR30 register *******************/\n#define BKP_DR30_D_Pos (0U) \n#define BKP_DR30_D_Msk (0xFFFFUL << BKP_DR30_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR30_D BKP_DR30_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR31 register *******************/\n#define BKP_DR31_D_Pos (0U) \n#define BKP_DR31_D_Msk (0xFFFFUL << BKP_DR31_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR31_D BKP_DR31_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR32 register *******************/\n#define BKP_DR32_D_Pos (0U) \n#define BKP_DR32_D_Msk (0xFFFFUL << BKP_DR32_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR32_D BKP_DR32_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR33 register *******************/\n#define BKP_DR33_D_Pos (0U) \n#define BKP_DR33_D_Msk (0xFFFFUL << BKP_DR33_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR33_D BKP_DR33_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR34 register *******************/\n#define BKP_DR34_D_Pos (0U) \n#define BKP_DR34_D_Msk (0xFFFFUL << BKP_DR34_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR34_D BKP_DR34_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR35 register *******************/\n#define BKP_DR35_D_Pos (0U) \n#define BKP_DR35_D_Msk (0xFFFFUL << BKP_DR35_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR35_D BKP_DR35_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR36 register *******************/\n#define BKP_DR36_D_Pos (0U) \n#define BKP_DR36_D_Msk (0xFFFFUL << BKP_DR36_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR36_D BKP_DR36_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR37 register *******************/\n#define BKP_DR37_D_Pos (0U) \n#define BKP_DR37_D_Msk (0xFFFFUL << BKP_DR37_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR37_D BKP_DR37_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR38 register *******************/\n#define BKP_DR38_D_Pos (0U) \n#define BKP_DR38_D_Msk (0xFFFFUL << BKP_DR38_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR38_D BKP_DR38_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR39 register *******************/\n#define BKP_DR39_D_Pos (0U) \n#define BKP_DR39_D_Msk (0xFFFFUL << BKP_DR39_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR39_D BKP_DR39_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR40 register *******************/\n#define BKP_DR40_D_Pos (0U) \n#define BKP_DR40_D_Msk (0xFFFFUL << BKP_DR40_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR40_D BKP_DR40_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR41 register *******************/\n#define BKP_DR41_D_Pos (0U) \n#define BKP_DR41_D_Msk (0xFFFFUL << BKP_DR41_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR41_D BKP_DR41_D_Msk /*!< Backup data */\n\n/******************* Bit definition for BKP_DR42 register *******************/\n#define BKP_DR42_D_Pos (0U) \n#define BKP_DR42_D_Msk (0xFFFFUL << BKP_DR42_D_Pos) /*!< 0x0000FFFF */\n#define BKP_DR42_D BKP_DR42_D_Msk /*!< Backup data */\n\n#define RTC_BKP_NUMBER 42\n\n/****************** Bit definition for BKP_RTCCR register *******************/\n#define BKP_RTCCR_CAL_Pos (0U) \n#define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */\n#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */\n#define BKP_RTCCR_CCO_Pos (7U) \n#define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */\n#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */\n#define BKP_RTCCR_ASOE_Pos (8U) \n#define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */\n#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */\n#define BKP_RTCCR_ASOS_Pos (9U) \n#define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */\n#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */\n\n/******************** Bit definition for BKP_CR register ********************/\n#define BKP_CR_TPE_Pos (0U) \n#define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos) /*!< 0x00000001 */\n#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */\n#define BKP_CR_TPAL_Pos (1U) \n#define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos) /*!< 0x00000002 */\n#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */\n\n/******************* Bit definition for BKP_CSR register ********************/\n#define BKP_CSR_CTE_Pos (0U) \n#define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos) /*!< 0x00000001 */\n#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */\n#define BKP_CSR_CTI_Pos (1U) \n#define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos) /*!< 0x00000002 */\n#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */\n#define BKP_CSR_TPIE_Pos (2U) \n#define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */\n#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */\n#define BKP_CSR_TEF_Pos (8U) \n#define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos) /*!< 0x00000100 */\n#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */\n#define BKP_CSR_TIF_Pos (9U) \n#define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos) /*!< 0x00000200 */\n#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */\n\n/******************************************************************************/\n/* */\n/* Reset and Clock Control */\n/* */\n/******************************************************************************/\n\n/******************** Bit definition for RCC_CR register ********************/\n#define RCC_CR_HSION_Pos (0U) \n#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */\n#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */\n#define RCC_CR_HSIRDY_Pos (1U) \n#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */\n#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */\n#define RCC_CR_HSITRIM_Pos (3U) \n#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */\n#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */\n#define RCC_CR_HSICAL_Pos (8U) \n#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */\n#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */\n#define RCC_CR_HSEON_Pos (16U) \n#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */\n#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */\n#define RCC_CR_HSERDY_Pos (17U) \n#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */\n#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */\n#define RCC_CR_HSEBYP_Pos (18U) \n#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */\n#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */\n#define RCC_CR_CSSON_Pos (19U) \n#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */\n#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */\n#define RCC_CR_PLLON_Pos (24U) \n#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */\n#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */\n#define RCC_CR_PLLRDY_Pos (25U) \n#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */\n#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */\n\n\n/******************* Bit definition for RCC_CFGR register *******************/\n/*!< SW configuration */\n#define RCC_CFGR_SW_Pos (0U) \n#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */\n#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */\n#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */\n#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */\n\n#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */\n#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */\n#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */\n\n/*!< SWS configuration */\n#define RCC_CFGR_SWS_Pos (2U) \n#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */\n#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */\n#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */\n#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */\n\n#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */\n#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */\n#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */\n\n/*!< HPRE configuration */\n#define RCC_CFGR_HPRE_Pos (4U) \n#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */\n#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */\n#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */\n#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */\n#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */\n#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */\n\n#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */\n#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */\n#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */\n#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */\n#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */\n#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */\n#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */\n#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */\n#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */\n\n/*!< PPRE1 configuration */\n#define RCC_CFGR_PPRE1_Pos (8U) \n#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */\n#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */\n#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */\n#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */\n#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */\n\n#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */\n#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */\n#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */\n#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */\n#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */\n\n/*!< PPRE2 configuration */\n#define RCC_CFGR_PPRE2_Pos (11U) \n#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */\n#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */\n#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */\n#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */\n#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */\n\n#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */\n#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */\n#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */\n#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */\n#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */\n\n/*!< ADCPPRE configuration */\n#define RCC_CFGR_ADCPRE_Pos (14U) \n#define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */\n#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */\n#define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */\n#define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */\n\n#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */\n#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */\n#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */\n#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */\n\n#define RCC_CFGR_PLLSRC_Pos (16U) \n#define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */\n#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */\n\n#define RCC_CFGR_PLLXTPRE_Pos (17U) \n#define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */\n#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */\n\n/*!< PLLMUL configuration */\n#define RCC_CFGR_PLLMULL_Pos (18U) \n#define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */\n#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */\n#define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */\n#define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */\n#define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */\n#define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */\n\n#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */\n#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */\n\n#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */\n#define RCC_CFGR_PLLMULL3_Pos (18U) \n#define RCC_CFGR_PLLMULL3_Msk (0x1UL << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */\n#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */\n#define RCC_CFGR_PLLMULL4_Pos (19U) \n#define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */\n#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */\n#define RCC_CFGR_PLLMULL5_Pos (18U) \n#define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */\n#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */\n#define RCC_CFGR_PLLMULL6_Pos (20U) \n#define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */\n#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */\n#define RCC_CFGR_PLLMULL7_Pos (18U) \n#define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */\n#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */\n#define RCC_CFGR_PLLMULL8_Pos (19U) \n#define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */\n#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */\n#define RCC_CFGR_PLLMULL9_Pos (18U) \n#define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */\n#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */\n#define RCC_CFGR_PLLMULL10_Pos (21U) \n#define RCC_CFGR_PLLMULL10_Msk (0x1UL << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */\n#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */\n#define RCC_CFGR_PLLMULL11_Pos (18U) \n#define RCC_CFGR_PLLMULL11_Msk (0x9UL << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */\n#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */\n#define RCC_CFGR_PLLMULL12_Pos (19U) \n#define RCC_CFGR_PLLMULL12_Msk (0x5UL << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */\n#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */\n#define RCC_CFGR_PLLMULL13_Pos (18U) \n#define RCC_CFGR_PLLMULL13_Msk (0xBUL << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */\n#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */\n#define RCC_CFGR_PLLMULL14_Pos (20U) \n#define RCC_CFGR_PLLMULL14_Msk (0x3UL << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */\n#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */\n#define RCC_CFGR_PLLMULL15_Pos (18U) \n#define RCC_CFGR_PLLMULL15_Msk (0xDUL << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */\n#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */\n#define RCC_CFGR_PLLMULL16_Pos (19U) \n#define RCC_CFGR_PLLMULL16_Msk (0x7UL << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */\n#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */\n#define RCC_CFGR_USBPRE_Pos (22U) \n#define RCC_CFGR_USBPRE_Msk (0x1UL << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */\n#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */\n\n/*!< MCO configuration */\n#define RCC_CFGR_MCO_Pos (24U) \n#define RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */\n#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */\n#define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */\n#define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */\n#define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */\n\n#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */\n#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */\n#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */\n#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */\n#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */\n\n /* Reference defines */\n #define RCC_CFGR_MCOSEL RCC_CFGR_MCO\n #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0\n #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1\n #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2\n #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK\n #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK\n #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI\n #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE\n #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2\n\n/*!<****************** Bit definition for RCC_CIR register ********************/\n#define RCC_CIR_LSIRDYF_Pos (0U) \n#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */\n#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */\n#define RCC_CIR_LSERDYF_Pos (1U) \n#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */\n#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */\n#define RCC_CIR_HSIRDYF_Pos (2U) \n#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */\n#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */\n#define RCC_CIR_HSERDYF_Pos (3U) \n#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */\n#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */\n#define RCC_CIR_PLLRDYF_Pos (4U) \n#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */\n#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */\n#define RCC_CIR_CSSF_Pos (7U) \n#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */\n#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */\n#define RCC_CIR_LSIRDYIE_Pos (8U) \n#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */\n#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */\n#define RCC_CIR_LSERDYIE_Pos (9U) \n#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */\n#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */\n#define RCC_CIR_HSIRDYIE_Pos (10U) \n#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */\n#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */\n#define RCC_CIR_HSERDYIE_Pos (11U) \n#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */\n#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */\n#define RCC_CIR_PLLRDYIE_Pos (12U) \n#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */\n#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */\n#define RCC_CIR_LSIRDYC_Pos (16U) \n#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */\n#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */\n#define RCC_CIR_LSERDYC_Pos (17U) \n#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */\n#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */\n#define RCC_CIR_HSIRDYC_Pos (18U) \n#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */\n#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */\n#define RCC_CIR_HSERDYC_Pos (19U) \n#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */\n#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */\n#define RCC_CIR_PLLRDYC_Pos (20U) \n#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */\n#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */\n#define RCC_CIR_CSSC_Pos (23U) \n#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */\n#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */\n\n\n/***************** Bit definition for RCC_APB2RSTR register *****************/\n#define RCC_APB2RSTR_AFIORST_Pos (0U) \n#define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */\n#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */\n#define RCC_APB2RSTR_IOPARST_Pos (2U) \n#define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */\n#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */\n#define RCC_APB2RSTR_IOPBRST_Pos (3U) \n#define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */\n#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */\n#define RCC_APB2RSTR_IOPCRST_Pos (4U) \n#define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */\n#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */\n#define RCC_APB2RSTR_IOPDRST_Pos (5U) \n#define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */\n#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */\n#define RCC_APB2RSTR_ADC1RST_Pos (9U) \n#define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */\n#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */\n\n#define RCC_APB2RSTR_ADC2RST_Pos (10U) \n#define RCC_APB2RSTR_ADC2RST_Msk (0x1UL << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */\n#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */\n\n#define RCC_APB2RSTR_TIM1RST_Pos (11U) \n#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */\n#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */\n#define RCC_APB2RSTR_SPI1RST_Pos (12U) \n#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */\n#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */\n#define RCC_APB2RSTR_USART1RST_Pos (14U) \n#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */\n#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */\n\n\n#define RCC_APB2RSTR_IOPERST_Pos (6U) \n#define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */\n#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */\n\n#define RCC_APB2RSTR_IOPFRST_Pos (7U) \n#define RCC_APB2RSTR_IOPFRST_Msk (0x1UL << RCC_APB2RSTR_IOPFRST_Pos) /*!< 0x00000080 */\n#define RCC_APB2RSTR_IOPFRST RCC_APB2RSTR_IOPFRST_Msk /*!< I/O port F reset */\n#define RCC_APB2RSTR_IOPGRST_Pos (8U) \n#define RCC_APB2RSTR_IOPGRST_Msk (0x1UL << RCC_APB2RSTR_IOPGRST_Pos) /*!< 0x00000100 */\n#define RCC_APB2RSTR_IOPGRST RCC_APB2RSTR_IOPGRST_Msk /*!< I/O port G reset */\n#define RCC_APB2RSTR_TIM8RST_Pos (13U) \n#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00002000 */\n#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 Timer reset */\n#define RCC_APB2RSTR_ADC3RST_Pos (15U) \n#define RCC_APB2RSTR_ADC3RST_Msk (0x1UL << RCC_APB2RSTR_ADC3RST_Pos) /*!< 0x00008000 */\n#define RCC_APB2RSTR_ADC3RST RCC_APB2RSTR_ADC3RST_Msk /*!< ADC3 interface reset */\n\n\n\n/***************** Bit definition for RCC_APB1RSTR register *****************/\n#define RCC_APB1RSTR_TIM2RST_Pos (0U) \n#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */\n#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */\n#define RCC_APB1RSTR_TIM3RST_Pos (1U) \n#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */\n#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */\n#define RCC_APB1RSTR_WWDGRST_Pos (11U) \n#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */\n#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */\n#define RCC_APB1RSTR_USART2RST_Pos (17U) \n#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */\n#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */\n#define RCC_APB1RSTR_I2C1RST_Pos (21U) \n#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */\n#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */\n\n#define RCC_APB1RSTR_CAN1RST_Pos (25U) \n#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */\n#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */\n\n#define RCC_APB1RSTR_BKPRST_Pos (27U) \n#define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */\n#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */\n#define RCC_APB1RSTR_PWRRST_Pos (28U) \n#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */\n#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */\n\n#define RCC_APB1RSTR_TIM4RST_Pos (2U) \n#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */\n#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */\n#define RCC_APB1RSTR_SPI2RST_Pos (14U) \n#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */\n#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */\n#define RCC_APB1RSTR_USART3RST_Pos (18U) \n#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */\n#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */\n#define RCC_APB1RSTR_I2C2RST_Pos (22U) \n#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */\n#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */\n\n#define RCC_APB1RSTR_USBRST_Pos (23U) \n#define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */\n#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */\n\n#define RCC_APB1RSTR_TIM5RST_Pos (3U) \n#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */\n#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */\n#define RCC_APB1RSTR_TIM6RST_Pos (4U) \n#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */\n#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */\n#define RCC_APB1RSTR_TIM7RST_Pos (5U) \n#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */\n#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */\n#define RCC_APB1RSTR_SPI3RST_Pos (15U) \n#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */\n#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */\n#define RCC_APB1RSTR_UART4RST_Pos (19U) \n#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */\n#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */\n#define RCC_APB1RSTR_UART5RST_Pos (20U) \n#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */\n#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */\n\n\n\n\n#define RCC_APB1RSTR_DACRST_Pos (29U) \n#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */\n#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */\n\n/****************** Bit definition for RCC_AHBENR register ******************/\n#define RCC_AHBENR_DMA1EN_Pos (0U) \n#define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */\n#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */\n#define RCC_AHBENR_SRAMEN_Pos (2U) \n#define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */\n#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */\n#define RCC_AHBENR_FLITFEN_Pos (4U) \n#define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */\n#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */\n#define RCC_AHBENR_CRCEN_Pos (6U) \n#define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */\n#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */\n\n#define RCC_AHBENR_DMA2EN_Pos (1U) \n#define RCC_AHBENR_DMA2EN_Msk (0x1UL << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */\n#define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */\n\n#define RCC_AHBENR_FSMCEN_Pos (8U) \n#define RCC_AHBENR_FSMCEN_Msk (0x1UL << RCC_AHBENR_FSMCEN_Pos) /*!< 0x00000100 */\n#define RCC_AHBENR_FSMCEN RCC_AHBENR_FSMCEN_Msk /*!< FSMC clock enable */\n#define RCC_AHBENR_SDIOEN_Pos (10U) \n#define RCC_AHBENR_SDIOEN_Msk (0x1UL << RCC_AHBENR_SDIOEN_Pos) /*!< 0x00000400 */\n#define RCC_AHBENR_SDIOEN RCC_AHBENR_SDIOEN_Msk /*!< SDIO clock enable */\n\n\n/****************** Bit definition for RCC_APB2ENR register *****************/\n#define RCC_APB2ENR_AFIOEN_Pos (0U) \n#define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */\n#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */\n#define RCC_APB2ENR_IOPAEN_Pos (2U) \n#define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */\n#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */\n#define RCC_APB2ENR_IOPBEN_Pos (3U) \n#define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */\n#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */\n#define RCC_APB2ENR_IOPCEN_Pos (4U) \n#define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */\n#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */\n#define RCC_APB2ENR_IOPDEN_Pos (5U) \n#define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */\n#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */\n#define RCC_APB2ENR_ADC1EN_Pos (9U) \n#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */\n#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */\n\n#define RCC_APB2ENR_ADC2EN_Pos (10U) \n#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */\n#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */\n\n#define RCC_APB2ENR_TIM1EN_Pos (11U) \n#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */\n#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */\n#define RCC_APB2ENR_SPI1EN_Pos (12U) \n#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */\n#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */\n#define RCC_APB2ENR_USART1EN_Pos (14U) \n#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */\n#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */\n\n\n#define RCC_APB2ENR_IOPEEN_Pos (6U) \n#define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */\n#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */\n\n#define RCC_APB2ENR_IOPFEN_Pos (7U) \n#define RCC_APB2ENR_IOPFEN_Msk (0x1UL << RCC_APB2ENR_IOPFEN_Pos) /*!< 0x00000080 */\n#define RCC_APB2ENR_IOPFEN RCC_APB2ENR_IOPFEN_Msk /*!< I/O port F clock enable */\n#define RCC_APB2ENR_IOPGEN_Pos (8U) \n#define RCC_APB2ENR_IOPGEN_Msk (0x1UL << RCC_APB2ENR_IOPGEN_Pos) /*!< 0x00000100 */\n#define RCC_APB2ENR_IOPGEN RCC_APB2ENR_IOPGEN_Msk /*!< I/O port G clock enable */\n#define RCC_APB2ENR_TIM8EN_Pos (13U) \n#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */\n#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 Timer clock enable */\n#define RCC_APB2ENR_ADC3EN_Pos (15U) \n#define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00008000 */\n#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk /*!< DMA1 clock enable */\n\n\n\n/***************** Bit definition for RCC_APB1ENR register ******************/\n#define RCC_APB1ENR_TIM2EN_Pos (0U) \n#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */\n#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/\n#define RCC_APB1ENR_TIM3EN_Pos (1U) \n#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */\n#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */\n#define RCC_APB1ENR_WWDGEN_Pos (11U) \n#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */\n#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */\n#define RCC_APB1ENR_USART2EN_Pos (17U) \n#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */\n#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */\n#define RCC_APB1ENR_I2C1EN_Pos (21U) \n#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */\n#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */\n\n#define RCC_APB1ENR_CAN1EN_Pos (25U) \n#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */\n#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */\n\n#define RCC_APB1ENR_BKPEN_Pos (27U) \n#define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */\n#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */\n#define RCC_APB1ENR_PWREN_Pos (28U) \n#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */\n#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */\n\n#define RCC_APB1ENR_TIM4EN_Pos (2U) \n#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */\n#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */\n#define RCC_APB1ENR_SPI2EN_Pos (14U) \n#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */\n#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */\n#define RCC_APB1ENR_USART3EN_Pos (18U) \n#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */\n#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */\n#define RCC_APB1ENR_I2C2EN_Pos (22U) \n#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */\n#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */\n\n#define RCC_APB1ENR_USBEN_Pos (23U) \n#define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */\n#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */\n\n#define RCC_APB1ENR_TIM5EN_Pos (3U) \n#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */\n#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */\n#define RCC_APB1ENR_TIM6EN_Pos (4U) \n#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */\n#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */\n#define RCC_APB1ENR_TIM7EN_Pos (5U) \n#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */\n#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */\n#define RCC_APB1ENR_SPI3EN_Pos (15U) \n#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */\n#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */\n#define RCC_APB1ENR_UART4EN_Pos (19U) \n#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */\n#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */\n#define RCC_APB1ENR_UART5EN_Pos (20U) \n#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */\n#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */\n\n\n\n\n#define RCC_APB1ENR_DACEN_Pos (29U) \n#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */\n#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */\n\n/******************* Bit definition for RCC_BDCR register *******************/\n#define RCC_BDCR_LSEON_Pos (0U) \n#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */\n#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */\n#define RCC_BDCR_LSERDY_Pos (1U) \n#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */\n#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */\n#define RCC_BDCR_LSEBYP_Pos (2U) \n#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */\n#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */\n\n#define RCC_BDCR_RTCSEL_Pos (8U) \n#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */\n#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */\n#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */\n#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */\n\n/*!< RTC congiguration */\n#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */\n#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */\n#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */\n#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */\n\n#define RCC_BDCR_RTCEN_Pos (15U) \n#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */\n#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */\n#define RCC_BDCR_BDRST_Pos (16U) \n#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */\n#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */\n\n/******************* Bit definition for RCC_CSR register ********************/ \n#define RCC_CSR_LSION_Pos (0U) \n#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */\n#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */\n#define RCC_CSR_LSIRDY_Pos (1U) \n#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */\n#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */\n#define RCC_CSR_RMVF_Pos (24U) \n#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */\n#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */\n#define RCC_CSR_PINRSTF_Pos (26U) \n#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */\n#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */\n#define RCC_CSR_PORRSTF_Pos (27U) \n#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */\n#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */\n#define RCC_CSR_SFTRSTF_Pos (28U) \n#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */\n#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */\n#define RCC_CSR_IWDGRSTF_Pos (29U) \n#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */\n#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */\n#define RCC_CSR_WWDGRSTF_Pos (30U) \n#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */\n#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */\n#define RCC_CSR_LPWRRSTF_Pos (31U) \n#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */\n#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */\n\n\n \n/******************************************************************************/\n/* */\n/* General Purpose and Alternate Function I/O */\n/* */\n/******************************************************************************/\n\n/******************* Bit definition for GPIO_CRL register *******************/\n#define GPIO_CRL_MODE_Pos (0U) \n#define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */\n#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */\n\n#define GPIO_CRL_MODE0_Pos (0U) \n#define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */\n#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */\n#define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */\n#define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */\n\n#define GPIO_CRL_MODE1_Pos (4U) \n#define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */\n#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */\n#define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */\n#define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */\n\n#define GPIO_CRL_MODE2_Pos (8U) \n#define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */\n#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */\n#define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */\n#define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */\n\n#define GPIO_CRL_MODE3_Pos (12U) \n#define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */\n#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */\n#define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */\n#define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */\n\n#define GPIO_CRL_MODE4_Pos (16U) \n#define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */\n#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */\n#define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */\n#define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */\n\n#define GPIO_CRL_MODE5_Pos (20U) \n#define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */\n#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */\n#define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */\n#define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */\n\n#define GPIO_CRL_MODE6_Pos (24U) \n#define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */\n#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */\n#define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */\n#define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */\n\n#define GPIO_CRL_MODE7_Pos (28U) \n#define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */\n#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */\n#define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */\n#define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */\n\n#define GPIO_CRL_CNF_Pos (2U) \n#define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */\n#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */\n\n#define GPIO_CRL_CNF0_Pos (2U) \n#define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */\n#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */\n#define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */\n#define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */\n\n#define GPIO_CRL_CNF1_Pos (6U) \n#define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */\n#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */\n#define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */\n#define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */\n\n#define GPIO_CRL_CNF2_Pos (10U) \n#define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */\n#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */\n#define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */\n#define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */\n\n#define GPIO_CRL_CNF3_Pos (14U) \n#define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */\n#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */\n#define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */\n#define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */\n\n#define GPIO_CRL_CNF4_Pos (18U) \n#define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */\n#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */\n#define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */\n#define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */\n\n#define GPIO_CRL_CNF5_Pos (22U) \n#define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */\n#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */\n#define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */\n#define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */\n\n#define GPIO_CRL_CNF6_Pos (26U) \n#define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */\n#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */\n#define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */\n#define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */\n\n#define GPIO_CRL_CNF7_Pos (30U) \n#define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */\n#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */\n#define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */\n#define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */\n\n/******************* Bit definition for GPIO_CRH register *******************/\n#define GPIO_CRH_MODE_Pos (0U) \n#define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */\n#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */\n\n#define GPIO_CRH_MODE8_Pos (0U) \n#define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */\n#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */\n#define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */\n#define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */\n\n#define GPIO_CRH_MODE9_Pos (4U) \n#define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */\n#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */\n#define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */\n#define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */\n\n#define GPIO_CRH_MODE10_Pos (8U) \n#define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */\n#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */\n#define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */\n#define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */\n\n#define GPIO_CRH_MODE11_Pos (12U) \n#define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */\n#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */\n#define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */\n#define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */\n\n#define GPIO_CRH_MODE12_Pos (16U) \n#define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */\n#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */\n#define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */\n#define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */\n\n#define GPIO_CRH_MODE13_Pos (20U) \n#define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */\n#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */\n#define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */\n#define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */\n\n#define GPIO_CRH_MODE14_Pos (24U) \n#define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */\n#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */\n#define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */\n#define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */\n\n#define GPIO_CRH_MODE15_Pos (28U) \n#define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */\n#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */\n#define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */\n#define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */\n\n#define GPIO_CRH_CNF_Pos (2U) \n#define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */\n#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */\n\n#define GPIO_CRH_CNF8_Pos (2U) \n#define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */\n#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */\n#define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */\n#define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */\n\n#define GPIO_CRH_CNF9_Pos (6U) \n#define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */\n#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */\n#define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */\n#define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */\n\n#define GPIO_CRH_CNF10_Pos (10U) \n#define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */\n#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */\n#define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */\n#define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */\n\n#define GPIO_CRH_CNF11_Pos (14U) \n#define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */\n#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */\n#define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */\n#define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */\n\n#define GPIO_CRH_CNF12_Pos (18U) \n#define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */\n#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */\n#define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */\n#define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */\n\n#define GPIO_CRH_CNF13_Pos (22U) \n#define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */\n#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */\n#define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */\n#define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */\n\n#define GPIO_CRH_CNF14_Pos (26U) \n#define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */\n#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */\n#define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */\n#define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */\n\n#define GPIO_CRH_CNF15_Pos (30U) \n#define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */\n#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */\n#define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */\n#define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */\n\n/*!<****************** Bit definition for GPIO_IDR register *******************/\n#define GPIO_IDR_IDR0_Pos (0U) \n#define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */\n#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */\n#define GPIO_IDR_IDR1_Pos (1U) \n#define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */\n#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */\n#define GPIO_IDR_IDR2_Pos (2U) \n#define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */\n#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */\n#define GPIO_IDR_IDR3_Pos (3U) \n#define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */\n#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */\n#define GPIO_IDR_IDR4_Pos (4U) \n#define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */\n#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */\n#define GPIO_IDR_IDR5_Pos (5U) \n#define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */\n#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */\n#define GPIO_IDR_IDR6_Pos (6U) \n#define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */\n#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */\n#define GPIO_IDR_IDR7_Pos (7U) \n#define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */\n#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */\n#define GPIO_IDR_IDR8_Pos (8U) \n#define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */\n#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */\n#define GPIO_IDR_IDR9_Pos (9U) \n#define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */\n#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */\n#define GPIO_IDR_IDR10_Pos (10U) \n#define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */\n#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */\n#define GPIO_IDR_IDR11_Pos (11U) \n#define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */\n#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */\n#define GPIO_IDR_IDR12_Pos (12U) \n#define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */\n#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */\n#define GPIO_IDR_IDR13_Pos (13U) \n#define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */\n#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */\n#define GPIO_IDR_IDR14_Pos (14U) \n#define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */\n#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */\n#define GPIO_IDR_IDR15_Pos (15U) \n#define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */\n#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */\n\n/******************* Bit definition for GPIO_ODR register *******************/\n#define GPIO_ODR_ODR0_Pos (0U) \n#define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */\n#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */\n#define GPIO_ODR_ODR1_Pos (1U) \n#define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */\n#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */\n#define GPIO_ODR_ODR2_Pos (2U) \n#define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */\n#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */\n#define GPIO_ODR_ODR3_Pos (3U) \n#define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */\n#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */\n#define GPIO_ODR_ODR4_Pos (4U) \n#define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */\n#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */\n#define GPIO_ODR_ODR5_Pos (5U) \n#define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */\n#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */\n#define GPIO_ODR_ODR6_Pos (6U) \n#define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */\n#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */\n#define GPIO_ODR_ODR7_Pos (7U) \n#define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */\n#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */\n#define GPIO_ODR_ODR8_Pos (8U) \n#define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */\n#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */\n#define GPIO_ODR_ODR9_Pos (9U) \n#define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */\n#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */\n#define GPIO_ODR_ODR10_Pos (10U) \n#define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */\n#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */\n#define GPIO_ODR_ODR11_Pos (11U) \n#define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */\n#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */\n#define GPIO_ODR_ODR12_Pos (12U) \n#define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */\n#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */\n#define GPIO_ODR_ODR13_Pos (13U) \n#define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */\n#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */\n#define GPIO_ODR_ODR14_Pos (14U) \n#define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */\n#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */\n#define GPIO_ODR_ODR15_Pos (15U) \n#define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */\n#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */\n\n/****************** Bit definition for GPIO_BSRR register *******************/\n#define GPIO_BSRR_BS0_Pos (0U) \n#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */\n#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */\n#define GPIO_BSRR_BS1_Pos (1U) \n#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */\n#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */\n#define GPIO_BSRR_BS2_Pos (2U) \n#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */\n#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */\n#define GPIO_BSRR_BS3_Pos (3U) \n#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */\n#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */\n#define GPIO_BSRR_BS4_Pos (4U) \n#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */\n#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */\n#define GPIO_BSRR_BS5_Pos (5U) \n#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */\n#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */\n#define GPIO_BSRR_BS6_Pos (6U) \n#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */\n#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */\n#define GPIO_BSRR_BS7_Pos (7U) \n#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */\n#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */\n#define GPIO_BSRR_BS8_Pos (8U) \n#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */\n#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */\n#define GPIO_BSRR_BS9_Pos (9U) \n#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */\n#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */\n#define GPIO_BSRR_BS10_Pos (10U) \n#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */\n#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */\n#define GPIO_BSRR_BS11_Pos (11U) \n#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */\n#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */\n#define GPIO_BSRR_BS12_Pos (12U) \n#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */\n#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */\n#define GPIO_BSRR_BS13_Pos (13U) \n#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */\n#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */\n#define GPIO_BSRR_BS14_Pos (14U) \n#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */\n#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */\n#define GPIO_BSRR_BS15_Pos (15U) \n#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */\n#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */\n\n#define GPIO_BSRR_BR0_Pos (16U) \n#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */\n#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */\n#define GPIO_BSRR_BR1_Pos (17U) \n#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */\n#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */\n#define GPIO_BSRR_BR2_Pos (18U) \n#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */\n#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */\n#define GPIO_BSRR_BR3_Pos (19U) \n#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */\n#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */\n#define GPIO_BSRR_BR4_Pos (20U) \n#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */\n#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */\n#define GPIO_BSRR_BR5_Pos (21U) \n#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */\n#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */\n#define GPIO_BSRR_BR6_Pos (22U) \n#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */\n#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */\n#define GPIO_BSRR_BR7_Pos (23U) \n#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */\n#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */\n#define GPIO_BSRR_BR8_Pos (24U) \n#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */\n#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */\n#define GPIO_BSRR_BR9_Pos (25U) \n#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */\n#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */\n#define GPIO_BSRR_BR10_Pos (26U) \n#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */\n#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */\n#define GPIO_BSRR_BR11_Pos (27U) \n#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */\n#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */\n#define GPIO_BSRR_BR12_Pos (28U) \n#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */\n#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */\n#define GPIO_BSRR_BR13_Pos (29U) \n#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */\n#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */\n#define GPIO_BSRR_BR14_Pos (30U) \n#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */\n#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */\n#define GPIO_BSRR_BR15_Pos (31U) \n#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */\n#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */\n\n/******************* Bit definition for GPIO_BRR register *******************/\n#define GPIO_BRR_BR0_Pos (0U) \n#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */\n#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */\n#define GPIO_BRR_BR1_Pos (1U) \n#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */\n#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */\n#define GPIO_BRR_BR2_Pos (2U) \n#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */\n#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */\n#define GPIO_BRR_BR3_Pos (3U) \n#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */\n#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */\n#define GPIO_BRR_BR4_Pos (4U) \n#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */\n#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */\n#define GPIO_BRR_BR5_Pos (5U) \n#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */\n#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */\n#define GPIO_BRR_BR6_Pos (6U) \n#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */\n#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */\n#define GPIO_BRR_BR7_Pos (7U) \n#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */\n#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */\n#define GPIO_BRR_BR8_Pos (8U) \n#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */\n#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */\n#define GPIO_BRR_BR9_Pos (9U) \n#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */\n#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */\n#define GPIO_BRR_BR10_Pos (10U) \n#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */\n#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */\n#define GPIO_BRR_BR11_Pos (11U) \n#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */\n#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */\n#define GPIO_BRR_BR12_Pos (12U) \n#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */\n#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */\n#define GPIO_BRR_BR13_Pos (13U) \n#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */\n#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */\n#define GPIO_BRR_BR14_Pos (14U) \n#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */\n#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */\n#define GPIO_BRR_BR15_Pos (15U) \n#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */\n#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */\n\n/****************** Bit definition for GPIO_LCKR register *******************/\n#define GPIO_LCKR_LCK0_Pos (0U) \n#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */\n#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */\n#define GPIO_LCKR_LCK1_Pos (1U) \n#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */\n#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */\n#define GPIO_LCKR_LCK2_Pos (2U) \n#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */\n#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */\n#define GPIO_LCKR_LCK3_Pos (3U) \n#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */\n#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */\n#define GPIO_LCKR_LCK4_Pos (4U) \n#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */\n#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */\n#define GPIO_LCKR_LCK5_Pos (5U) \n#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */\n#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */\n#define GPIO_LCKR_LCK6_Pos (6U) \n#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */\n#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */\n#define GPIO_LCKR_LCK7_Pos (7U) \n#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */\n#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */\n#define GPIO_LCKR_LCK8_Pos (8U) \n#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */\n#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */\n#define GPIO_LCKR_LCK9_Pos (9U) \n#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */\n#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */\n#define GPIO_LCKR_LCK10_Pos (10U) \n#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */\n#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */\n#define GPIO_LCKR_LCK11_Pos (11U) \n#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */\n#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */\n#define GPIO_LCKR_LCK12_Pos (12U) \n#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */\n#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */\n#define GPIO_LCKR_LCK13_Pos (13U) \n#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */\n#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */\n#define GPIO_LCKR_LCK14_Pos (14U) \n#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */\n#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */\n#define GPIO_LCKR_LCK15_Pos (15U) \n#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */\n#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */\n#define GPIO_LCKR_LCKK_Pos (16U) \n#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */\n#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */\n\n/*----------------------------------------------------------------------------*/\n\n/****************** Bit definition for AFIO_EVCR register *******************/\n#define AFIO_EVCR_PIN_Pos (0U) \n#define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */\n#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */\n#define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */\n#define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */\n#define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */\n#define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */\n\n/*!< PIN configuration */\n#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */\n#define AFIO_EVCR_PIN_PX1_Pos (0U) \n#define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */\n#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */\n#define AFIO_EVCR_PIN_PX2_Pos (1U) \n#define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */\n#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */\n#define AFIO_EVCR_PIN_PX3_Pos (0U) \n#define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */\n#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */\n#define AFIO_EVCR_PIN_PX4_Pos (2U) \n#define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */\n#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */\n#define AFIO_EVCR_PIN_PX5_Pos (0U) \n#define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */\n#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */\n#define AFIO_EVCR_PIN_PX6_Pos (1U) \n#define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */\n#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */\n#define AFIO_EVCR_PIN_PX7_Pos (0U) \n#define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */\n#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */\n#define AFIO_EVCR_PIN_PX8_Pos (3U) \n#define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */\n#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */\n#define AFIO_EVCR_PIN_PX9_Pos (0U) \n#define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */\n#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */\n#define AFIO_EVCR_PIN_PX10_Pos (1U) \n#define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */\n#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */\n#define AFIO_EVCR_PIN_PX11_Pos (0U) \n#define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */\n#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */\n#define AFIO_EVCR_PIN_PX12_Pos (2U) \n#define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */\n#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */\n#define AFIO_EVCR_PIN_PX13_Pos (0U) \n#define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */\n#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */\n#define AFIO_EVCR_PIN_PX14_Pos (1U) \n#define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */\n#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */\n#define AFIO_EVCR_PIN_PX15_Pos (0U) \n#define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */\n#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */\n\n#define AFIO_EVCR_PORT_Pos (4U) \n#define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */\n#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */\n#define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */\n#define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */\n#define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */\n\n/*!< PORT configuration */\n#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */\n#define AFIO_EVCR_PORT_PB_Pos (4U) \n#define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */\n#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */\n#define AFIO_EVCR_PORT_PC_Pos (5U) \n#define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */\n#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */\n#define AFIO_EVCR_PORT_PD_Pos (4U) \n#define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */\n#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */\n#define AFIO_EVCR_PORT_PE_Pos (6U) \n#define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */\n#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */\n\n#define AFIO_EVCR_EVOE_Pos (7U) \n#define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */\n#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */\n\n/****************** Bit definition for AFIO_MAPR register *******************/\n#define AFIO_MAPR_SPI1_REMAP_Pos (0U) \n#define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */\n#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */\n#define AFIO_MAPR_I2C1_REMAP_Pos (1U) \n#define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */\n#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */\n#define AFIO_MAPR_USART1_REMAP_Pos (2U) \n#define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */\n#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */\n#define AFIO_MAPR_USART2_REMAP_Pos (3U) \n#define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */\n#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */\n\n#define AFIO_MAPR_USART3_REMAP_Pos (4U) \n#define AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */\n#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */\n#define AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */\n#define AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */\n\n/* USART3_REMAP configuration */\n#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */\n#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) \n#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */\n#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */\n#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) \n#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */\n#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */\n\n#define AFIO_MAPR_TIM1_REMAP_Pos (6U) \n#define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */\n#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */\n#define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */\n#define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */\n\n/*!< TIM1_REMAP configuration */\n#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */\n#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) \n#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */\n#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */\n#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) \n#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */\n#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */\n\n#define AFIO_MAPR_TIM2_REMAP_Pos (8U) \n#define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */\n#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */\n#define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */\n#define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */\n\n/*!< TIM2_REMAP configuration */\n#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */\n#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) \n#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */\n#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */\n#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) \n#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */\n#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */\n#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) \n#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */\n#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */\n\n#define AFIO_MAPR_TIM3_REMAP_Pos (10U) \n#define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */\n#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */\n#define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */\n#define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */\n\n/*!< TIM3_REMAP configuration */\n#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */\n#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) \n#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */\n#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */\n#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) \n#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */\n#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */\n\n#define AFIO_MAPR_TIM4_REMAP_Pos (12U) \n#define AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */\n#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */\n\n#define AFIO_MAPR_CAN_REMAP_Pos (13U) \n#define AFIO_MAPR_CAN_REMAP_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */\n#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */\n#define AFIO_MAPR_CAN_REMAP_0 (0x1UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */\n#define AFIO_MAPR_CAN_REMAP_1 (0x2UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */\n\n/*!< CAN_REMAP configuration */\n#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */\n#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) \n#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */\n#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */\n#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) \n#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */\n#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */\n\n#define AFIO_MAPR_PD01_REMAP_Pos (15U) \n#define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */\n#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */\n#define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U) \n#define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1UL << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /*!< 0x00010000 */\n#define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk /*!< TIM5 Channel4 Internal Remap */\n#define AFIO_MAPR_ADC1_ETRGINJ_REMAP_Pos (17U) \n#define AFIO_MAPR_ADC1_ETRGINJ_REMAP_Msk (0x1UL << AFIO_MAPR_ADC1_ETRGINJ_REMAP_Pos) /*!< 0x00020000 */\n#define AFIO_MAPR_ADC1_ETRGINJ_REMAP AFIO_MAPR_ADC1_ETRGINJ_REMAP_Msk /*!< ADC 1 External Trigger Injected Conversion remapping */\n#define AFIO_MAPR_ADC1_ETRGREG_REMAP_Pos (18U) \n#define AFIO_MAPR_ADC1_ETRGREG_REMAP_Msk (0x1UL << AFIO_MAPR_ADC1_ETRGREG_REMAP_Pos) /*!< 0x00040000 */\n#define AFIO_MAPR_ADC1_ETRGREG_REMAP AFIO_MAPR_ADC1_ETRGREG_REMAP_Msk /*!< ADC 1 External Trigger Regular Conversion remapping */\n#define AFIO_MAPR_ADC2_ETRGINJ_REMAP_Pos (19U) \n#define AFIO_MAPR_ADC2_ETRGINJ_REMAP_Msk (0x1UL << AFIO_MAPR_ADC2_ETRGINJ_REMAP_Pos) /*!< 0x00080000 */\n#define AFIO_MAPR_ADC2_ETRGINJ_REMAP AFIO_MAPR_ADC2_ETRGINJ_REMAP_Msk /*!< ADC 2 External Trigger Injected Conversion remapping */\n#define AFIO_MAPR_ADC2_ETRGREG_REMAP_Pos (20U) \n#define AFIO_MAPR_ADC2_ETRGREG_REMAP_Msk (0x1UL << AFIO_MAPR_ADC2_ETRGREG_REMAP_Pos) /*!< 0x00100000 */\n#define AFIO_MAPR_ADC2_ETRGREG_REMAP AFIO_MAPR_ADC2_ETRGREG_REMAP_Msk /*!< ADC 2 External Trigger Regular Conversion remapping */\n\n/*!< SWJ_CFG configuration */\n#define AFIO_MAPR_SWJ_CFG_Pos (24U) \n#define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */\n#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */\n#define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */\n#define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */\n#define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */\n\n#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */\n#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) \n#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */\n#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */\n#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) \n#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */\n#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */\n#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) \n#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */\n#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */\n\n\n/***************** Bit definition for AFIO_EXTICR1 register *****************/\n#define AFIO_EXTICR1_EXTI0_Pos (0U) \n#define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */\n#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */\n#define AFIO_EXTICR1_EXTI1_Pos (4U) \n#define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */\n#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */\n#define AFIO_EXTICR1_EXTI2_Pos (8U) \n#define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */\n#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */\n#define AFIO_EXTICR1_EXTI3_Pos (12U) \n#define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */\n#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */\n\n/*!< EXTI0 configuration */\n#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */\n#define AFIO_EXTICR1_EXTI0_PB_Pos (0U) \n#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */\n#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */\n#define AFIO_EXTICR1_EXTI0_PC_Pos (1U) \n#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */\n#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */\n#define AFIO_EXTICR1_EXTI0_PD_Pos (0U) \n#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */\n#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */\n#define AFIO_EXTICR1_EXTI0_PE_Pos (2U) \n#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */\n#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */\n#define AFIO_EXTICR1_EXTI0_PF_Pos (0U) \n#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */\n#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */\n#define AFIO_EXTICR1_EXTI0_PG_Pos (1U) \n#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */\n#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */\n\n/*!< EXTI1 configuration */\n#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */\n#define AFIO_EXTICR1_EXTI1_PB_Pos (4U) \n#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */\n#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */\n#define AFIO_EXTICR1_EXTI1_PC_Pos (5U) \n#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */\n#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */\n#define AFIO_EXTICR1_EXTI1_PD_Pos (4U) \n#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */\n#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */\n#define AFIO_EXTICR1_EXTI1_PE_Pos (6U) \n#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */\n#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */\n#define AFIO_EXTICR1_EXTI1_PF_Pos (4U) \n#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */\n#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */\n#define AFIO_EXTICR1_EXTI1_PG_Pos (5U) \n#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */\n#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */\n\n/*!< EXTI2 configuration */ \n#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */\n#define AFIO_EXTICR1_EXTI2_PB_Pos (8U) \n#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */\n#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */\n#define AFIO_EXTICR1_EXTI2_PC_Pos (9U) \n#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */\n#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */\n#define AFIO_EXTICR1_EXTI2_PD_Pos (8U) \n#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */\n#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */\n#define AFIO_EXTICR1_EXTI2_PE_Pos (10U) \n#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */\n#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */\n#define AFIO_EXTICR1_EXTI2_PF_Pos (8U) \n#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */\n#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */\n#define AFIO_EXTICR1_EXTI2_PG_Pos (9U) \n#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */\n#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */\n\n/*!< EXTI3 configuration */\n#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */\n#define AFIO_EXTICR1_EXTI3_PB_Pos (12U) \n#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */\n#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */\n#define AFIO_EXTICR1_EXTI3_PC_Pos (13U) \n#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */\n#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */\n#define AFIO_EXTICR1_EXTI3_PD_Pos (12U) \n#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */\n#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */\n#define AFIO_EXTICR1_EXTI3_PE_Pos (14U) \n#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */\n#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */\n#define AFIO_EXTICR1_EXTI3_PF_Pos (12U) \n#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */\n#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */\n#define AFIO_EXTICR1_EXTI3_PG_Pos (13U) \n#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */\n#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */\n\n/***************** Bit definition for AFIO_EXTICR2 register *****************/\n#define AFIO_EXTICR2_EXTI4_Pos (0U) \n#define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */\n#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */\n#define AFIO_EXTICR2_EXTI5_Pos (4U) \n#define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */\n#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */\n#define AFIO_EXTICR2_EXTI6_Pos (8U) \n#define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */\n#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */\n#define AFIO_EXTICR2_EXTI7_Pos (12U) \n#define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */\n#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */\n\n/*!< EXTI4 configuration */\n#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */\n#define AFIO_EXTICR2_EXTI4_PB_Pos (0U) \n#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */\n#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */\n#define AFIO_EXTICR2_EXTI4_PC_Pos (1U) \n#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */\n#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */\n#define AFIO_EXTICR2_EXTI4_PD_Pos (0U) \n#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */\n#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */\n#define AFIO_EXTICR2_EXTI4_PE_Pos (2U) \n#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */\n#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */\n#define AFIO_EXTICR2_EXTI4_PF_Pos (0U) \n#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */\n#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */\n#define AFIO_EXTICR2_EXTI4_PG_Pos (1U) \n#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */\n#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */\n\n/* EXTI5 configuration */\n#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */\n#define AFIO_EXTICR2_EXTI5_PB_Pos (4U) \n#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */\n#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */\n#define AFIO_EXTICR2_EXTI5_PC_Pos (5U) \n#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */\n#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */\n#define AFIO_EXTICR2_EXTI5_PD_Pos (4U) \n#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */\n#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */\n#define AFIO_EXTICR2_EXTI5_PE_Pos (6U) \n#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */\n#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */\n#define AFIO_EXTICR2_EXTI5_PF_Pos (4U) \n#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */\n#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */\n#define AFIO_EXTICR2_EXTI5_PG_Pos (5U) \n#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */\n#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */\n\n/*!< EXTI6 configuration */ \n#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */\n#define AFIO_EXTICR2_EXTI6_PB_Pos (8U) \n#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */\n#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */\n#define AFIO_EXTICR2_EXTI6_PC_Pos (9U) \n#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */\n#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */\n#define AFIO_EXTICR2_EXTI6_PD_Pos (8U) \n#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */\n#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */\n#define AFIO_EXTICR2_EXTI6_PE_Pos (10U) \n#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */\n#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */\n#define AFIO_EXTICR2_EXTI6_PF_Pos (8U) \n#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */\n#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */\n#define AFIO_EXTICR2_EXTI6_PG_Pos (9U) \n#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */\n#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */\n\n/*!< EXTI7 configuration */\n#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */\n#define AFIO_EXTICR2_EXTI7_PB_Pos (12U) \n#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */\n#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */\n#define AFIO_EXTICR2_EXTI7_PC_Pos (13U) \n#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */\n#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */\n#define AFIO_EXTICR2_EXTI7_PD_Pos (12U) \n#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */\n#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */\n#define AFIO_EXTICR2_EXTI7_PE_Pos (14U) \n#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */\n#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */\n#define AFIO_EXTICR2_EXTI7_PF_Pos (12U) \n#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */\n#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */\n#define AFIO_EXTICR2_EXTI7_PG_Pos (13U) \n#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */\n#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */\n\n/***************** Bit definition for AFIO_EXTICR3 register *****************/\n#define AFIO_EXTICR3_EXTI8_Pos (0U) \n#define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */\n#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */\n#define AFIO_EXTICR3_EXTI9_Pos (4U) \n#define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */\n#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */\n#define AFIO_EXTICR3_EXTI10_Pos (8U) \n#define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */\n#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */\n#define AFIO_EXTICR3_EXTI11_Pos (12U) \n#define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */\n#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */\n\n/*!< EXTI8 configuration */\n#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */\n#define AFIO_EXTICR3_EXTI8_PB_Pos (0U) \n#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */\n#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */\n#define AFIO_EXTICR3_EXTI8_PC_Pos (1U) \n#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */\n#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */\n#define AFIO_EXTICR3_EXTI8_PD_Pos (0U) \n#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */\n#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */\n#define AFIO_EXTICR3_EXTI8_PE_Pos (2U) \n#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */\n#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */\n#define AFIO_EXTICR3_EXTI8_PF_Pos (0U) \n#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */\n#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */\n#define AFIO_EXTICR3_EXTI8_PG_Pos (1U) \n#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */\n#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */\n\n/*!< EXTI9 configuration */\n#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */\n#define AFIO_EXTICR3_EXTI9_PB_Pos (4U) \n#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */\n#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */\n#define AFIO_EXTICR3_EXTI9_PC_Pos (5U) \n#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */\n#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */\n#define AFIO_EXTICR3_EXTI9_PD_Pos (4U) \n#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */\n#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */\n#define AFIO_EXTICR3_EXTI9_PE_Pos (6U) \n#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */\n#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */\n#define AFIO_EXTICR3_EXTI9_PF_Pos (4U) \n#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */\n#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */\n#define AFIO_EXTICR3_EXTI9_PG_Pos (5U) \n#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */\n#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */\n\n/*!< EXTI10 configuration */ \n#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */\n#define AFIO_EXTICR3_EXTI10_PB_Pos (8U) \n#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */\n#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */\n#define AFIO_EXTICR3_EXTI10_PC_Pos (9U) \n#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */\n#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */\n#define AFIO_EXTICR3_EXTI10_PD_Pos (8U) \n#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */\n#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */\n#define AFIO_EXTICR3_EXTI10_PE_Pos (10U) \n#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */\n#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */\n#define AFIO_EXTICR3_EXTI10_PF_Pos (8U) \n#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */\n#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */\n#define AFIO_EXTICR3_EXTI10_PG_Pos (9U) \n#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */\n#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */\n\n/*!< EXTI11 configuration */\n#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */\n#define AFIO_EXTICR3_EXTI11_PB_Pos (12U) \n#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */\n#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */\n#define AFIO_EXTICR3_EXTI11_PC_Pos (13U) \n#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */\n#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */\n#define AFIO_EXTICR3_EXTI11_PD_Pos (12U) \n#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */\n#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */\n#define AFIO_EXTICR3_EXTI11_PE_Pos (14U) \n#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */\n#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */\n#define AFIO_EXTICR3_EXTI11_PF_Pos (12U) \n#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */\n#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */\n#define AFIO_EXTICR3_EXTI11_PG_Pos (13U) \n#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */\n#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */\n\n/***************** Bit definition for AFIO_EXTICR4 register *****************/\n#define AFIO_EXTICR4_EXTI12_Pos (0U) \n#define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */\n#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */\n#define AFIO_EXTICR4_EXTI13_Pos (4U) \n#define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */\n#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */\n#define AFIO_EXTICR4_EXTI14_Pos (8U) \n#define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */\n#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */\n#define AFIO_EXTICR4_EXTI15_Pos (12U) \n#define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */\n#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */\n\n/* EXTI12 configuration */\n#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */\n#define AFIO_EXTICR4_EXTI12_PB_Pos (0U) \n#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */\n#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */\n#define AFIO_EXTICR4_EXTI12_PC_Pos (1U) \n#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */\n#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */\n#define AFIO_EXTICR4_EXTI12_PD_Pos (0U) \n#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */\n#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */\n#define AFIO_EXTICR4_EXTI12_PE_Pos (2U) \n#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */\n#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */\n#define AFIO_EXTICR4_EXTI12_PF_Pos (0U) \n#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */\n#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */\n#define AFIO_EXTICR4_EXTI12_PG_Pos (1U) \n#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */\n#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */\n\n/* EXTI13 configuration */\n#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */\n#define AFIO_EXTICR4_EXTI13_PB_Pos (4U) \n#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */\n#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */\n#define AFIO_EXTICR4_EXTI13_PC_Pos (5U) \n#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */\n#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */\n#define AFIO_EXTICR4_EXTI13_PD_Pos (4U) \n#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */\n#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */\n#define AFIO_EXTICR4_EXTI13_PE_Pos (6U) \n#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */\n#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */\n#define AFIO_EXTICR4_EXTI13_PF_Pos (4U) \n#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */\n#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */\n#define AFIO_EXTICR4_EXTI13_PG_Pos (5U) \n#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */\n#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */\n\n/*!< EXTI14 configuration */ \n#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */\n#define AFIO_EXTICR4_EXTI14_PB_Pos (8U) \n#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */\n#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */\n#define AFIO_EXTICR4_EXTI14_PC_Pos (9U) \n#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */\n#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */\n#define AFIO_EXTICR4_EXTI14_PD_Pos (8U) \n#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */\n#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */\n#define AFIO_EXTICR4_EXTI14_PE_Pos (10U) \n#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */\n#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */\n#define AFIO_EXTICR4_EXTI14_PF_Pos (8U) \n#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */\n#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */\n#define AFIO_EXTICR4_EXTI14_PG_Pos (9U) \n#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */\n#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */\n\n/*!< EXTI15 configuration */\n#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */\n#define AFIO_EXTICR4_EXTI15_PB_Pos (12U) \n#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */\n#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */\n#define AFIO_EXTICR4_EXTI15_PC_Pos (13U) \n#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */\n#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */\n#define AFIO_EXTICR4_EXTI15_PD_Pos (12U) \n#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */\n#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */\n#define AFIO_EXTICR4_EXTI15_PE_Pos (14U) \n#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */\n#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */\n#define AFIO_EXTICR4_EXTI15_PF_Pos (12U) \n#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */\n#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */\n#define AFIO_EXTICR4_EXTI15_PG_Pos (13U) \n#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */\n#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */\n\n/****************** Bit definition for AFIO_MAPR2 register ******************/\n\n\n#define AFIO_MAPR2_FSMC_NADV_REMAP_Pos (10U) \n#define AFIO_MAPR2_FSMC_NADV_REMAP_Msk (0x1UL << AFIO_MAPR2_FSMC_NADV_REMAP_Pos) /*!< 0x00000400 */\n#define AFIO_MAPR2_FSMC_NADV_REMAP AFIO_MAPR2_FSMC_NADV_REMAP_Msk /*!< FSMC NADV remapping */\n\n/******************************************************************************/\n/* */\n/* External Interrupt/Event Controller */\n/* */\n/******************************************************************************/\n\n/******************* Bit definition for EXTI_IMR register *******************/\n#define EXTI_IMR_MR0_Pos (0U) \n#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */\n#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */\n#define EXTI_IMR_MR1_Pos (1U) \n#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */\n#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */\n#define EXTI_IMR_MR2_Pos (2U) \n#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */\n#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */\n#define EXTI_IMR_MR3_Pos (3U) \n#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */\n#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */\n#define EXTI_IMR_MR4_Pos (4U) \n#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */\n#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */\n#define EXTI_IMR_MR5_Pos (5U) \n#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */\n#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */\n#define EXTI_IMR_MR6_Pos (6U) \n#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */\n#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */\n#define EXTI_IMR_MR7_Pos (7U) \n#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */\n#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */\n#define EXTI_IMR_MR8_Pos (8U) \n#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */\n#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */\n#define EXTI_IMR_MR9_Pos (9U) \n#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */\n#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */\n#define EXTI_IMR_MR10_Pos (10U) \n#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */\n#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */\n#define EXTI_IMR_MR11_Pos (11U) \n#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */\n#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */\n#define EXTI_IMR_MR12_Pos (12U) \n#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */\n#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */\n#define EXTI_IMR_MR13_Pos (13U) \n#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */\n#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */\n#define EXTI_IMR_MR14_Pos (14U) \n#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */\n#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */\n#define EXTI_IMR_MR15_Pos (15U) \n#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */\n#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */\n#define EXTI_IMR_MR16_Pos (16U) \n#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */\n#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */\n#define EXTI_IMR_MR17_Pos (17U) \n#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */\n#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */\n#define EXTI_IMR_MR18_Pos (18U) \n#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */\n#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */\n\n/* References Defines */\n#define EXTI_IMR_IM0 EXTI_IMR_MR0\n#define EXTI_IMR_IM1 EXTI_IMR_MR1\n#define EXTI_IMR_IM2 EXTI_IMR_MR2\n#define EXTI_IMR_IM3 EXTI_IMR_MR3\n#define EXTI_IMR_IM4 EXTI_IMR_MR4\n#define EXTI_IMR_IM5 EXTI_IMR_MR5\n#define EXTI_IMR_IM6 EXTI_IMR_MR6\n#define EXTI_IMR_IM7 EXTI_IMR_MR7\n#define EXTI_IMR_IM8 EXTI_IMR_MR8\n#define EXTI_IMR_IM9 EXTI_IMR_MR9\n#define EXTI_IMR_IM10 EXTI_IMR_MR10\n#define EXTI_IMR_IM11 EXTI_IMR_MR11\n#define EXTI_IMR_IM12 EXTI_IMR_MR12\n#define EXTI_IMR_IM13 EXTI_IMR_MR13\n#define EXTI_IMR_IM14 EXTI_IMR_MR14\n#define EXTI_IMR_IM15 EXTI_IMR_MR15\n#define EXTI_IMR_IM16 EXTI_IMR_MR16\n#define EXTI_IMR_IM17 EXTI_IMR_MR17\n#define EXTI_IMR_IM18 EXTI_IMR_MR18\n#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */\n \n/******************* Bit definition for EXTI_EMR register *******************/\n#define EXTI_EMR_MR0_Pos (0U) \n#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */\n#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */\n#define EXTI_EMR_MR1_Pos (1U) \n#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */\n#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */\n#define EXTI_EMR_MR2_Pos (2U) \n#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */\n#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */\n#define EXTI_EMR_MR3_Pos (3U) \n#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */\n#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */\n#define EXTI_EMR_MR4_Pos (4U) \n#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */\n#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */\n#define EXTI_EMR_MR5_Pos (5U) \n#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */\n#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */\n#define EXTI_EMR_MR6_Pos (6U) \n#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */\n#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */\n#define EXTI_EMR_MR7_Pos (7U) \n#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */\n#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */\n#define EXTI_EMR_MR8_Pos (8U) \n#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */\n#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */\n#define EXTI_EMR_MR9_Pos (9U) \n#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */\n#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */\n#define EXTI_EMR_MR10_Pos (10U) \n#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */\n#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */\n#define EXTI_EMR_MR11_Pos (11U) \n#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */\n#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */\n#define EXTI_EMR_MR12_Pos (12U) \n#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */\n#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */\n#define EXTI_EMR_MR13_Pos (13U) \n#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */\n#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */\n#define EXTI_EMR_MR14_Pos (14U) \n#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */\n#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */\n#define EXTI_EMR_MR15_Pos (15U) \n#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */\n#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */\n#define EXTI_EMR_MR16_Pos (16U) \n#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */\n#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */\n#define EXTI_EMR_MR17_Pos (17U) \n#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */\n#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */\n#define EXTI_EMR_MR18_Pos (18U) \n#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */\n#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */\n\n/* References Defines */\n#define EXTI_EMR_EM0 EXTI_EMR_MR0\n#define EXTI_EMR_EM1 EXTI_EMR_MR1\n#define EXTI_EMR_EM2 EXTI_EMR_MR2\n#define EXTI_EMR_EM3 EXTI_EMR_MR3\n#define EXTI_EMR_EM4 EXTI_EMR_MR4\n#define EXTI_EMR_EM5 EXTI_EMR_MR5\n#define EXTI_EMR_EM6 EXTI_EMR_MR6\n#define EXTI_EMR_EM7 EXTI_EMR_MR7\n#define EXTI_EMR_EM8 EXTI_EMR_MR8\n#define EXTI_EMR_EM9 EXTI_EMR_MR9\n#define EXTI_EMR_EM10 EXTI_EMR_MR10\n#define EXTI_EMR_EM11 EXTI_EMR_MR11\n#define EXTI_EMR_EM12 EXTI_EMR_MR12\n#define EXTI_EMR_EM13 EXTI_EMR_MR13\n#define EXTI_EMR_EM14 EXTI_EMR_MR14\n#define EXTI_EMR_EM15 EXTI_EMR_MR15\n#define EXTI_EMR_EM16 EXTI_EMR_MR16\n#define EXTI_EMR_EM17 EXTI_EMR_MR17\n#define EXTI_EMR_EM18 EXTI_EMR_MR18\n\n/****************** Bit definition for EXTI_RTSR register *******************/\n#define EXTI_RTSR_TR0_Pos (0U) \n#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */\n#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */\n#define EXTI_RTSR_TR1_Pos (1U) \n#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */\n#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */\n#define EXTI_RTSR_TR2_Pos (2U) \n#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */\n#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */\n#define EXTI_RTSR_TR3_Pos (3U) \n#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */\n#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */\n#define EXTI_RTSR_TR4_Pos (4U) \n#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */\n#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */\n#define EXTI_RTSR_TR5_Pos (5U) \n#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */\n#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */\n#define EXTI_RTSR_TR6_Pos (6U) \n#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */\n#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */\n#define EXTI_RTSR_TR7_Pos (7U) \n#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */\n#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */\n#define EXTI_RTSR_TR8_Pos (8U) \n#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */\n#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */\n#define EXTI_RTSR_TR9_Pos (9U) \n#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */\n#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */\n#define EXTI_RTSR_TR10_Pos (10U) \n#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */\n#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */\n#define EXTI_RTSR_TR11_Pos (11U) \n#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */\n#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */\n#define EXTI_RTSR_TR12_Pos (12U) \n#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */\n#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */\n#define EXTI_RTSR_TR13_Pos (13U) \n#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */\n#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */\n#define EXTI_RTSR_TR14_Pos (14U) \n#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */\n#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */\n#define EXTI_RTSR_TR15_Pos (15U) \n#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */\n#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */\n#define EXTI_RTSR_TR16_Pos (16U) \n#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */\n#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */\n#define EXTI_RTSR_TR17_Pos (17U) \n#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */\n#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */\n#define EXTI_RTSR_TR18_Pos (18U) \n#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */\n#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */\n\n/* References Defines */\n#define EXTI_RTSR_RT0 EXTI_RTSR_TR0\n#define EXTI_RTSR_RT1 EXTI_RTSR_TR1\n#define EXTI_RTSR_RT2 EXTI_RTSR_TR2\n#define EXTI_RTSR_RT3 EXTI_RTSR_TR3\n#define EXTI_RTSR_RT4 EXTI_RTSR_TR4\n#define EXTI_RTSR_RT5 EXTI_RTSR_TR5\n#define EXTI_RTSR_RT6 EXTI_RTSR_TR6\n#define EXTI_RTSR_RT7 EXTI_RTSR_TR7\n#define EXTI_RTSR_RT8 EXTI_RTSR_TR8\n#define EXTI_RTSR_RT9 EXTI_RTSR_TR9\n#define EXTI_RTSR_RT10 EXTI_RTSR_TR10\n#define EXTI_RTSR_RT11 EXTI_RTSR_TR11\n#define EXTI_RTSR_RT12 EXTI_RTSR_TR12\n#define EXTI_RTSR_RT13 EXTI_RTSR_TR13\n#define EXTI_RTSR_RT14 EXTI_RTSR_TR14\n#define EXTI_RTSR_RT15 EXTI_RTSR_TR15\n#define EXTI_RTSR_RT16 EXTI_RTSR_TR16\n#define EXTI_RTSR_RT17 EXTI_RTSR_TR17\n#define EXTI_RTSR_RT18 EXTI_RTSR_TR18\n\n/****************** Bit definition for EXTI_FTSR register *******************/\n#define EXTI_FTSR_TR0_Pos (0U) \n#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */\n#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */\n#define EXTI_FTSR_TR1_Pos (1U) \n#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */\n#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */\n#define EXTI_FTSR_TR2_Pos (2U) \n#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */\n#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */\n#define EXTI_FTSR_TR3_Pos (3U) \n#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */\n#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */\n#define EXTI_FTSR_TR4_Pos (4U) \n#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */\n#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */\n#define EXTI_FTSR_TR5_Pos (5U) \n#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */\n#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */\n#define EXTI_FTSR_TR6_Pos (6U) \n#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */\n#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */\n#define EXTI_FTSR_TR7_Pos (7U) \n#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */\n#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */\n#define EXTI_FTSR_TR8_Pos (8U) \n#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */\n#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */\n#define EXTI_FTSR_TR9_Pos (9U) \n#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */\n#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */\n#define EXTI_FTSR_TR10_Pos (10U) \n#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */\n#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */\n#define EXTI_FTSR_TR11_Pos (11U) \n#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */\n#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */\n#define EXTI_FTSR_TR12_Pos (12U) \n#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */\n#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */\n#define EXTI_FTSR_TR13_Pos (13U) \n#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */\n#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */\n#define EXTI_FTSR_TR14_Pos (14U) \n#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */\n#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */\n#define EXTI_FTSR_TR15_Pos (15U) \n#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */\n#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */\n#define EXTI_FTSR_TR16_Pos (16U) \n#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */\n#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */\n#define EXTI_FTSR_TR17_Pos (17U) \n#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */\n#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */\n#define EXTI_FTSR_TR18_Pos (18U) \n#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */\n#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */\n\n/* References Defines */\n#define EXTI_FTSR_FT0 EXTI_FTSR_TR0\n#define EXTI_FTSR_FT1 EXTI_FTSR_TR1\n#define EXTI_FTSR_FT2 EXTI_FTSR_TR2\n#define EXTI_FTSR_FT3 EXTI_FTSR_TR3\n#define EXTI_FTSR_FT4 EXTI_FTSR_TR4\n#define EXTI_FTSR_FT5 EXTI_FTSR_TR5\n#define EXTI_FTSR_FT6 EXTI_FTSR_TR6\n#define EXTI_FTSR_FT7 EXTI_FTSR_TR7\n#define EXTI_FTSR_FT8 EXTI_FTSR_TR8\n#define EXTI_FTSR_FT9 EXTI_FTSR_TR9\n#define EXTI_FTSR_FT10 EXTI_FTSR_TR10\n#define EXTI_FTSR_FT11 EXTI_FTSR_TR11\n#define EXTI_FTSR_FT12 EXTI_FTSR_TR12\n#define EXTI_FTSR_FT13 EXTI_FTSR_TR13\n#define EXTI_FTSR_FT14 EXTI_FTSR_TR14\n#define EXTI_FTSR_FT15 EXTI_FTSR_TR15\n#define EXTI_FTSR_FT16 EXTI_FTSR_TR16\n#define EXTI_FTSR_FT17 EXTI_FTSR_TR17\n#define EXTI_FTSR_FT18 EXTI_FTSR_TR18\n\n/****************** Bit definition for EXTI_SWIER register ******************/\n#define EXTI_SWIER_SWIER0_Pos (0U) \n#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */\n#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */\n#define EXTI_SWIER_SWIER1_Pos (1U) \n#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */\n#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */\n#define EXTI_SWIER_SWIER2_Pos (2U) \n#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */\n#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */\n#define EXTI_SWIER_SWIER3_Pos (3U) \n#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */\n#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */\n#define EXTI_SWIER_SWIER4_Pos (4U) \n#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */\n#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */\n#define EXTI_SWIER_SWIER5_Pos (5U) \n#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */\n#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */\n#define EXTI_SWIER_SWIER6_Pos (6U) \n#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */\n#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */\n#define EXTI_SWIER_SWIER7_Pos (7U) \n#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */\n#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */\n#define EXTI_SWIER_SWIER8_Pos (8U) \n#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */\n#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */\n#define EXTI_SWIER_SWIER9_Pos (9U) \n#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */\n#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */\n#define EXTI_SWIER_SWIER10_Pos (10U) \n#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */\n#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */\n#define EXTI_SWIER_SWIER11_Pos (11U) \n#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */\n#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */\n#define EXTI_SWIER_SWIER12_Pos (12U) \n#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */\n#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */\n#define EXTI_SWIER_SWIER13_Pos (13U) \n#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */\n#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */\n#define EXTI_SWIER_SWIER14_Pos (14U) \n#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */\n#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */\n#define EXTI_SWIER_SWIER15_Pos (15U) \n#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */\n#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */\n#define EXTI_SWIER_SWIER16_Pos (16U) \n#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */\n#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */\n#define EXTI_SWIER_SWIER17_Pos (17U) \n#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */\n#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */\n#define EXTI_SWIER_SWIER18_Pos (18U) \n#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */\n#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */\n\n/* References Defines */\n#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0\n#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1\n#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2\n#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3\n#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4\n#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5\n#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6\n#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7\n#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8\n#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9\n#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10\n#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11\n#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12\n#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13\n#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14\n#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15\n#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16\n#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17\n#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18\n\n/******************* Bit definition for EXTI_PR register ********************/\n#define EXTI_PR_PR0_Pos (0U) \n#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */\n#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */\n#define EXTI_PR_PR1_Pos (1U) \n#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */\n#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */\n#define EXTI_PR_PR2_Pos (2U) \n#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */\n#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */\n#define EXTI_PR_PR3_Pos (3U) \n#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */\n#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */\n#define EXTI_PR_PR4_Pos (4U) \n#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */\n#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */\n#define EXTI_PR_PR5_Pos (5U) \n#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */\n#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */\n#define EXTI_PR_PR6_Pos (6U) \n#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */\n#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */\n#define EXTI_PR_PR7_Pos (7U) \n#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */\n#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */\n#define EXTI_PR_PR8_Pos (8U) \n#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */\n#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */\n#define EXTI_PR_PR9_Pos (9U) \n#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */\n#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */\n#define EXTI_PR_PR10_Pos (10U) \n#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */\n#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */\n#define EXTI_PR_PR11_Pos (11U) \n#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */\n#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */\n#define EXTI_PR_PR12_Pos (12U) \n#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */\n#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */\n#define EXTI_PR_PR13_Pos (13U) \n#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */\n#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */\n#define EXTI_PR_PR14_Pos (14U) \n#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */\n#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */\n#define EXTI_PR_PR15_Pos (15U) \n#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */\n#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */\n#define EXTI_PR_PR16_Pos (16U) \n#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */\n#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */\n#define EXTI_PR_PR17_Pos (17U) \n#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */\n#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */\n#define EXTI_PR_PR18_Pos (18U) \n#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */\n#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */\n\n/* References Defines */\n#define EXTI_PR_PIF0 EXTI_PR_PR0\n#define EXTI_PR_PIF1 EXTI_PR_PR1\n#define EXTI_PR_PIF2 EXTI_PR_PR2\n#define EXTI_PR_PIF3 EXTI_PR_PR3\n#define EXTI_PR_PIF4 EXTI_PR_PR4\n#define EXTI_PR_PIF5 EXTI_PR_PR5\n#define EXTI_PR_PIF6 EXTI_PR_PR6\n#define EXTI_PR_PIF7 EXTI_PR_PR7\n#define EXTI_PR_PIF8 EXTI_PR_PR8\n#define EXTI_PR_PIF9 EXTI_PR_PR9\n#define EXTI_PR_PIF10 EXTI_PR_PR10\n#define EXTI_PR_PIF11 EXTI_PR_PR11\n#define EXTI_PR_PIF12 EXTI_PR_PR12\n#define EXTI_PR_PIF13 EXTI_PR_PR13\n#define EXTI_PR_PIF14 EXTI_PR_PR14\n#define EXTI_PR_PIF15 EXTI_PR_PR15\n#define EXTI_PR_PIF16 EXTI_PR_PR16\n#define EXTI_PR_PIF17 EXTI_PR_PR17\n#define EXTI_PR_PIF18 EXTI_PR_PR18\n\n/******************************************************************************/\n/* */\n/* DMA Controller */\n/* */\n/******************************************************************************/\n\n/******************* Bit definition for DMA_ISR register ********************/\n#define DMA_ISR_GIF1_Pos (0U) \n#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */\n#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */\n#define DMA_ISR_TCIF1_Pos (1U) \n#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */\n#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */\n#define DMA_ISR_HTIF1_Pos (2U) \n#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */\n#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */\n#define DMA_ISR_TEIF1_Pos (3U) \n#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */\n#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */\n#define DMA_ISR_GIF2_Pos (4U) \n#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */\n#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */\n#define DMA_ISR_TCIF2_Pos (5U) \n#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */\n#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */\n#define DMA_ISR_HTIF2_Pos (6U) \n#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */\n#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */\n#define DMA_ISR_TEIF2_Pos (7U) \n#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */\n#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */\n#define DMA_ISR_GIF3_Pos (8U) \n#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */\n#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */\n#define DMA_ISR_TCIF3_Pos (9U) \n#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */\n#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */\n#define DMA_ISR_HTIF3_Pos (10U) \n#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */\n#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */\n#define DMA_ISR_TEIF3_Pos (11U) \n#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */\n#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */\n#define DMA_ISR_GIF4_Pos (12U) \n#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */\n#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */\n#define DMA_ISR_TCIF4_Pos (13U) \n#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */\n#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */\n#define DMA_ISR_HTIF4_Pos (14U) \n#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */\n#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */\n#define DMA_ISR_TEIF4_Pos (15U) \n#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */\n#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */\n#define DMA_ISR_GIF5_Pos (16U) \n#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */\n#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */\n#define DMA_ISR_TCIF5_Pos (17U) \n#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */\n#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */\n#define DMA_ISR_HTIF5_Pos (18U) \n#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */\n#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */\n#define DMA_ISR_TEIF5_Pos (19U) \n#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */\n#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */\n#define DMA_ISR_GIF6_Pos (20U) \n#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */\n#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */\n#define DMA_ISR_TCIF6_Pos (21U) \n#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */\n#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */\n#define DMA_ISR_HTIF6_Pos (22U) \n#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */\n#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */\n#define DMA_ISR_TEIF6_Pos (23U) \n#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */\n#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */\n#define DMA_ISR_GIF7_Pos (24U) \n#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */\n#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */\n#define DMA_ISR_TCIF7_Pos (25U) \n#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */\n#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */\n#define DMA_ISR_HTIF7_Pos (26U) \n#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */\n#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */\n#define DMA_ISR_TEIF7_Pos (27U) \n#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */\n#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */\n\n/******************* Bit definition for DMA_IFCR register *******************/\n#define DMA_IFCR_CGIF1_Pos (0U) \n#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */\n#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */\n#define DMA_IFCR_CTCIF1_Pos (1U) \n#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */\n#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */\n#define DMA_IFCR_CHTIF1_Pos (2U) \n#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */\n#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */\n#define DMA_IFCR_CTEIF1_Pos (3U) \n#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */\n#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */\n#define DMA_IFCR_CGIF2_Pos (4U) \n#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */\n#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */\n#define DMA_IFCR_CTCIF2_Pos (5U) \n#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */\n#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */\n#define DMA_IFCR_CHTIF2_Pos (6U) \n#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */\n#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */\n#define DMA_IFCR_CTEIF2_Pos (7U) \n#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */\n#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */\n#define DMA_IFCR_CGIF3_Pos (8U) \n#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */\n#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */\n#define DMA_IFCR_CTCIF3_Pos (9U) \n#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */\n#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */\n#define DMA_IFCR_CHTIF3_Pos (10U) \n#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */\n#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */\n#define DMA_IFCR_CTEIF3_Pos (11U) \n#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */\n#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */\n#define DMA_IFCR_CGIF4_Pos (12U) \n#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */\n#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */\n#define DMA_IFCR_CTCIF4_Pos (13U) \n#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */\n#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */\n#define DMA_IFCR_CHTIF4_Pos (14U) \n#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */\n#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */\n#define DMA_IFCR_CTEIF4_Pos (15U) \n#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */\n#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */\n#define DMA_IFCR_CGIF5_Pos (16U) \n#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */\n#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */\n#define DMA_IFCR_CTCIF5_Pos (17U) \n#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */\n#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */\n#define DMA_IFCR_CHTIF5_Pos (18U) \n#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */\n#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */\n#define DMA_IFCR_CTEIF5_Pos (19U) \n#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */\n#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */\n#define DMA_IFCR_CGIF6_Pos (20U) \n#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */\n#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */\n#define DMA_IFCR_CTCIF6_Pos (21U) \n#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */\n#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */\n#define DMA_IFCR_CHTIF6_Pos (22U) \n#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */\n#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */\n#define DMA_IFCR_CTEIF6_Pos (23U) \n#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */\n#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */\n#define DMA_IFCR_CGIF7_Pos (24U) \n#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */\n#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */\n#define DMA_IFCR_CTCIF7_Pos (25U) \n#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */\n#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */\n#define DMA_IFCR_CHTIF7_Pos (26U) \n#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */\n#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */\n#define DMA_IFCR_CTEIF7_Pos (27U) \n#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */\n#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */\n\n/******************* Bit definition for DMA_CCR register *******************/\n#define DMA_CCR_EN_Pos (0U) \n#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */\n#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */\n#define DMA_CCR_TCIE_Pos (1U) \n#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */\n#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */\n#define DMA_CCR_HTIE_Pos (2U) \n#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */\n#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */\n#define DMA_CCR_TEIE_Pos (3U) \n#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */\n#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */\n#define DMA_CCR_DIR_Pos (4U) \n#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */\n#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */\n#define DMA_CCR_CIRC_Pos (5U) \n#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */\n#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */\n#define DMA_CCR_PINC_Pos (6U) \n#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */\n#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */\n#define DMA_CCR_MINC_Pos (7U) \n#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */\n#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */\n\n#define DMA_CCR_PSIZE_Pos (8U) \n#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */\n#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */\n#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */\n#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */\n\n#define DMA_CCR_MSIZE_Pos (10U) \n#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */\n#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */\n#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */\n#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */\n\n#define DMA_CCR_PL_Pos (12U) \n#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */\n#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */\n#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */\n#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */\n\n#define DMA_CCR_MEM2MEM_Pos (14U) \n#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */\n#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */\n\n/****************** Bit definition for DMA_CNDTR register ******************/\n#define DMA_CNDTR_NDT_Pos (0U) \n#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */\n#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */\n\n/****************** Bit definition for DMA_CPAR register *******************/\n#define DMA_CPAR_PA_Pos (0U) \n#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */\n#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */\n\n/****************** Bit definition for DMA_CMAR register *******************/\n#define DMA_CMAR_MA_Pos (0U) \n#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */\n#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */\n\n/******************************************************************************/\n/* */\n/* Analog to Digital Converter (ADC) */\n/* */\n/******************************************************************************/\n\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)\n */\n#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */\n\n/******************** Bit definition for ADC_SR register ********************/\n#define ADC_SR_AWD_Pos (0U) \n#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */\n#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */\n#define ADC_SR_EOS_Pos (1U) \n#define ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos) /*!< 0x00000002 */\n#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */\n#define ADC_SR_JEOS_Pos (2U) \n#define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */\n#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */\n#define ADC_SR_JSTRT_Pos (3U) \n#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */\n#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */\n#define ADC_SR_STRT_Pos (4U) \n#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */\n#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */\n\n/* Legacy defines */\n#define ADC_SR_EOC (ADC_SR_EOS)\n#define ADC_SR_JEOC (ADC_SR_JEOS)\n\n/******************* Bit definition for ADC_CR1 register ********************/\n#define ADC_CR1_AWDCH_Pos (0U) \n#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */\n#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */\n#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */\n#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */\n#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */\n#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */\n#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */\n\n#define ADC_CR1_EOSIE_Pos (5U) \n#define ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */\n#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */\n#define ADC_CR1_AWDIE_Pos (6U) \n#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */\n#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */\n#define ADC_CR1_JEOSIE_Pos (7U) \n#define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */\n#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */\n#define ADC_CR1_SCAN_Pos (8U) \n#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */\n#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */\n#define ADC_CR1_AWDSGL_Pos (9U) \n#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */\n#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */\n#define ADC_CR1_JAUTO_Pos (10U) \n#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */\n#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */\n#define ADC_CR1_DISCEN_Pos (11U) \n#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */\n#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */\n#define ADC_CR1_JDISCEN_Pos (12U) \n#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */\n#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */\n\n#define ADC_CR1_DISCNUM_Pos (13U) \n#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */\n#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */\n#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */\n#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */\n#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */\n\n#define ADC_CR1_DUALMOD_Pos (16U) \n#define ADC_CR1_DUALMOD_Msk (0xFUL << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */\n#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */\n#define ADC_CR1_DUALMOD_0 (0x1UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */\n#define ADC_CR1_DUALMOD_1 (0x2UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */\n#define ADC_CR1_DUALMOD_2 (0x4UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */\n#define ADC_CR1_DUALMOD_3 (0x8UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */\n\n#define ADC_CR1_JAWDEN_Pos (22U) \n#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */\n#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */\n#define ADC_CR1_AWDEN_Pos (23U) \n#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */\n#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */\n\n/* Legacy defines */\n#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)\n#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)\n\n/******************* Bit definition for ADC_CR2 register ********************/\n#define ADC_CR2_ADON_Pos (0U) \n#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */\n#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */\n#define ADC_CR2_CONT_Pos (1U) \n#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */\n#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */\n#define ADC_CR2_CAL_Pos (2U) \n#define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos) /*!< 0x00000004 */\n#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */\n#define ADC_CR2_RSTCAL_Pos (3U) \n#define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */\n#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */\n#define ADC_CR2_DMA_Pos (8U) \n#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */\n#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */\n#define ADC_CR2_ALIGN_Pos (11U) \n#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */\n#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */\n\n#define ADC_CR2_JEXTSEL_Pos (12U) \n#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */\n#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */\n#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */\n#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */\n#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */\n\n#define ADC_CR2_JEXTTRIG_Pos (15U) \n#define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */\n#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */\n\n#define ADC_CR2_EXTSEL_Pos (17U) \n#define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */\n#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */\n#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */\n#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */\n#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */\n\n#define ADC_CR2_EXTTRIG_Pos (20U) \n#define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */\n#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */\n#define ADC_CR2_JSWSTART_Pos (21U) \n#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */\n#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */\n#define ADC_CR2_SWSTART_Pos (22U) \n#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */\n#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */\n#define ADC_CR2_TSVREFE_Pos (23U) \n#define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */\n#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */\n\n/****************** Bit definition for ADC_SMPR1 register *******************/\n#define ADC_SMPR1_SMP10_Pos (0U) \n#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */\n#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */\n#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */\n#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */\n#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */\n\n#define ADC_SMPR1_SMP11_Pos (3U) \n#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */\n#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */\n#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */\n#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */\n#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */\n\n#define ADC_SMPR1_SMP12_Pos (6U) \n#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */\n#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */\n#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */\n#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */\n#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */\n\n#define ADC_SMPR1_SMP13_Pos (9U) \n#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */\n#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */\n#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */\n#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */\n#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */\n\n#define ADC_SMPR1_SMP14_Pos (12U) \n#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */\n#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */\n#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */\n#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */\n#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */\n\n#define ADC_SMPR1_SMP15_Pos (15U) \n#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */\n#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */\n#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */\n#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */\n#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */\n\n#define ADC_SMPR1_SMP16_Pos (18U) \n#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */\n#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */\n#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */\n#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */\n#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */\n\n#define ADC_SMPR1_SMP17_Pos (21U) \n#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */\n#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */\n#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */\n#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */\n#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */\n\n/****************** Bit definition for ADC_SMPR2 register *******************/\n#define ADC_SMPR2_SMP0_Pos (0U) \n#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */\n#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */\n#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */\n#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */\n#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */\n\n#define ADC_SMPR2_SMP1_Pos (3U) \n#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */\n#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */\n#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */\n#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */\n#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */\n\n#define ADC_SMPR2_SMP2_Pos (6U) \n#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */\n#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */\n#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */\n#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */\n#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */\n\n#define ADC_SMPR2_SMP3_Pos (9U) \n#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */\n#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */\n#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */\n#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */\n#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */\n\n#define ADC_SMPR2_SMP4_Pos (12U) \n#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */\n#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */\n#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */\n#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */\n#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */\n\n#define ADC_SMPR2_SMP5_Pos (15U) \n#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */\n#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */\n#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */\n#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */\n#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */\n\n#define ADC_SMPR2_SMP6_Pos (18U) \n#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */\n#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */\n#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */\n#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */\n#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */\n\n#define ADC_SMPR2_SMP7_Pos (21U) \n#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */\n#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */\n#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */\n#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */\n#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */\n\n#define ADC_SMPR2_SMP8_Pos (24U) \n#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */\n#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */\n#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */\n#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */\n#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */\n\n#define ADC_SMPR2_SMP9_Pos (27U) \n#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */\n#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */\n#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */\n#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */\n#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */\n\n/****************** Bit definition for ADC_JOFR1 register *******************/\n#define ADC_JOFR1_JOFFSET1_Pos (0U) \n#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */\n#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */\n\n/****************** Bit definition for ADC_JOFR2 register *******************/\n#define ADC_JOFR2_JOFFSET2_Pos (0U) \n#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */\n#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */\n\n/****************** Bit definition for ADC_JOFR3 register *******************/\n#define ADC_JOFR3_JOFFSET3_Pos (0U) \n#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */\n#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */\n\n/****************** Bit definition for ADC_JOFR4 register *******************/\n#define ADC_JOFR4_JOFFSET4_Pos (0U) \n#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */\n#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */\n\n/******************* Bit definition for ADC_HTR register ********************/\n#define ADC_HTR_HT_Pos (0U) \n#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */\n#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */\n\n/******************* Bit definition for ADC_LTR register ********************/\n#define ADC_LTR_LT_Pos (0U) \n#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */\n#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */\n\n/******************* Bit definition for ADC_SQR1 register *******************/\n#define ADC_SQR1_SQ13_Pos (0U) \n#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */\n#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */\n#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */\n#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */\n#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */\n#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */\n#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */\n\n#define ADC_SQR1_SQ14_Pos (5U) \n#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */\n#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */\n#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */\n#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */\n#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */\n#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */\n#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */\n\n#define ADC_SQR1_SQ15_Pos (10U) \n#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */\n#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */\n#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */\n#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */\n#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */\n#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */\n#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */\n\n#define ADC_SQR1_SQ16_Pos (15U) \n#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */\n#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */\n#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */\n#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */\n#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */\n#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */\n#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */\n\n#define ADC_SQR1_L_Pos (20U) \n#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */\n#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */\n#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */\n#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */\n#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */\n#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */\n\n/******************* Bit definition for ADC_SQR2 register *******************/\n#define ADC_SQR2_SQ7_Pos (0U) \n#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */\n#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */\n#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */\n#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */\n#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */\n#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */\n#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */\n\n#define ADC_SQR2_SQ8_Pos (5U) \n#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */\n#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */\n#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */\n#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */\n#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */\n#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */\n#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */\n\n#define ADC_SQR2_SQ9_Pos (10U) \n#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */\n#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */\n#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */\n#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */\n#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */\n#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */\n#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */\n\n#define ADC_SQR2_SQ10_Pos (15U) \n#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */\n#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */\n#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */\n#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */\n#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */\n#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */\n#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */\n\n#define ADC_SQR2_SQ11_Pos (20U) \n#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */\n#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */\n#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */\n#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */\n#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */\n#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */\n#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */\n\n#define ADC_SQR2_SQ12_Pos (25U) \n#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */\n#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */\n#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */\n#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */\n#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */\n#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */\n#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */\n\n/******************* Bit definition for ADC_SQR3 register *******************/\n#define ADC_SQR3_SQ1_Pos (0U) \n#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */\n#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */\n#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */\n#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */\n#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */\n#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */\n#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */\n\n#define ADC_SQR3_SQ2_Pos (5U) \n#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */\n#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */\n#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */\n#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */\n#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */\n#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */\n#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */\n\n#define ADC_SQR3_SQ3_Pos (10U) \n#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */\n#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */\n#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */\n#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */\n#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */\n#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */\n#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */\n\n#define ADC_SQR3_SQ4_Pos (15U) \n#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */\n#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */\n#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */\n#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */\n#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */\n#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */\n#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */\n\n#define ADC_SQR3_SQ5_Pos (20U) \n#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */\n#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */\n#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */\n#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */\n#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */\n#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */\n#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */\n\n#define ADC_SQR3_SQ6_Pos (25U) \n#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */\n#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */\n#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */\n#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */\n#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */\n#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */\n#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */\n\n/******************* Bit definition for ADC_JSQR register *******************/\n#define ADC_JSQR_JSQ1_Pos (0U) \n#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */\n#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */\n#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */\n#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */\n#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */\n#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */\n#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */\n\n#define ADC_JSQR_JSQ2_Pos (5U) \n#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */\n#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */\n#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */\n#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */\n#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */\n#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */\n#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */\n\n#define ADC_JSQR_JSQ3_Pos (10U) \n#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */\n#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */\n#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */\n#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */\n#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */\n#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */\n#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */\n\n#define ADC_JSQR_JSQ4_Pos (15U) \n#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */\n#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */\n#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */\n#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */\n#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */\n#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */\n#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */\n\n#define ADC_JSQR_JL_Pos (20U) \n#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */\n#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */\n#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */\n#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */\n\n/******************* Bit definition for ADC_JDR1 register *******************/\n#define ADC_JDR1_JDATA_Pos (0U) \n#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */\n\n/******************* Bit definition for ADC_JDR2 register *******************/\n#define ADC_JDR2_JDATA_Pos (0U) \n#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */\n\n/******************* Bit definition for ADC_JDR3 register *******************/\n#define ADC_JDR3_JDATA_Pos (0U) \n#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */\n\n/******************* Bit definition for ADC_JDR4 register *******************/\n#define ADC_JDR4_JDATA_Pos (0U) \n#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */\n\n/******************** Bit definition for ADC_DR register ********************/\n#define ADC_DR_DATA_Pos (0U) \n#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */\n#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */\n#define ADC_DR_ADC2DATA_Pos (16U) \n#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */\n#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */\n/******************************************************************************/\n/* */\n/* Digital to Analog Converter */\n/* */\n/******************************************************************************/\n\n/******************** Bit definition for DAC_CR register ********************/\n#define DAC_CR_EN1_Pos (0U) \n#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */\n#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */\n#define DAC_CR_BOFF1_Pos (1U) \n#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */\n#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */\n#define DAC_CR_TEN1_Pos (2U) \n#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */\n#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */\n\n#define DAC_CR_TSEL1_Pos (3U) \n#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */\n#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */\n#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */\n#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */\n#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */\n\n#define DAC_CR_WAVE1_Pos (6U) \n#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */\n#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */\n#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */\n\n#define DAC_CR_MAMP1_Pos (8U) \n#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */\n#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\n#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */\n#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */\n#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */\n#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */\n\n#define DAC_CR_DMAEN1_Pos (12U) \n#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */\n#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */\n#define DAC_CR_EN2_Pos (16U) \n#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */\n#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */\n#define DAC_CR_BOFF2_Pos (17U) \n#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */\n#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */\n#define DAC_CR_TEN2_Pos (18U) \n#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */\n#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */\n\n#define DAC_CR_TSEL2_Pos (19U) \n#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */\n#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */\n#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */\n#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */\n#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */\n\n#define DAC_CR_WAVE2_Pos (22U) \n#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */\n#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */\n#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */\n\n#define DAC_CR_MAMP2_Pos (24U) \n#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */\n#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\n#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */\n#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */\n#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */\n#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */\n\n#define DAC_CR_DMAEN2_Pos (28U) \n#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */\n#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */\n\n\n/***************** Bit definition for DAC_SWTRIGR register ******************/\n#define DAC_SWTRIGR_SWTRIG1_Pos (0U) \n#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */\n#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */\n#define DAC_SWTRIGR_SWTRIG2_Pos (1U) \n#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */\n#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */\n\n/***************** Bit definition for DAC_DHR12R1 register ******************/\n#define DAC_DHR12R1_DACC1DHR_Pos (0U) \n#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */\n#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */\n\n/***************** Bit definition for DAC_DHR12L1 register ******************/\n#define DAC_DHR12L1_DACC1DHR_Pos (4U) \n#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */\n#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */\n\n/****************** Bit definition for DAC_DHR8R1 register ******************/\n#define DAC_DHR8R1_DACC1DHR_Pos (0U) \n#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */\n#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */\n\n/***************** Bit definition for DAC_DHR12R2 register ******************/\n#define DAC_DHR12R2_DACC2DHR_Pos (0U) \n#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */\n#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */\n\n/***************** Bit definition for DAC_DHR12L2 register ******************/\n#define DAC_DHR12L2_DACC2DHR_Pos (4U) \n#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */\n#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */\n\n/****************** Bit definition for DAC_DHR8R2 register ******************/\n#define DAC_DHR8R2_DACC2DHR_Pos (0U) \n#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */\n#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */\n\n/***************** Bit definition for DAC_DHR12RD register ******************/\n#define DAC_DHR12RD_DACC1DHR_Pos (0U) \n#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */\n#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */\n#define DAC_DHR12RD_DACC2DHR_Pos (16U) \n#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */\n#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */\n\n/***************** Bit definition for DAC_DHR12LD register ******************/\n#define DAC_DHR12LD_DACC1DHR_Pos (4U) \n#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */\n#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */\n#define DAC_DHR12LD_DACC2DHR_Pos (20U) \n#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */\n#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */\n\n/****************** Bit definition for DAC_DHR8RD register ******************/\n#define DAC_DHR8RD_DACC1DHR_Pos (0U) \n#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */\n#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */\n#define DAC_DHR8RD_DACC2DHR_Pos (8U) \n#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */\n#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */\n\n/******************* Bit definition for DAC_DOR1 register *******************/\n#define DAC_DOR1_DACC1DOR_Pos (0U) \n#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */\n#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */\n\n/******************* Bit definition for DAC_DOR2 register *******************/\n#define DAC_DOR2_DACC2DOR_Pos (0U) \n#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */\n#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */\n\n\n\n/*****************************************************************************/\n/* */\n/* Timers (TIM) */\n/* */\n/*****************************************************************************/\n/******************* Bit definition for TIM_CR1 register *******************/\n#define TIM_CR1_CEN_Pos (0U) \n#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */\n#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!
© COPYRIGHT(c) 2017 STMicroelectronics
\n *\n * Redistribution and use in source and binary forms, with or without modification,\n * are permitted provided that the following conditions are met:\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and/or other materials provided with the distribution.\n * 3. Neither the name of STMicroelectronics nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n ******************************************************************************\n */\n\n/** @addtogroup CMSIS\n * @{\n */\n\n/** @addtogroup stm32f1xx\n * @{\n */\n \n#ifndef __STM32F1XX_H\n#define __STM32F1XX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n \n/** @addtogroup Library_configuration_section\n * @{\n */\n\n/**\n * @brief STM32 Family\n */\n#if !defined (STM32F1)\n#define STM32F1\n#endif /* STM32F1 */\n\n/* Uncomment the line below according to the target STM32L device used in your \n application \n */\n\n#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \\\n !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \\\n !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)\n /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */\n /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */\n /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */\n /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */\n /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ \n /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */\n /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */\n /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */\n /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */\n /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */\n #define STM32F103xE /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */\n /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */\n /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */\n /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */ \n#endif\n\n/* Tip: To avoid modifying this file each time you need to switch between these\n devices, you can define the device in your toolchain compiler preprocessor.\n */\n \n#if !defined (USE_HAL_DRIVER)\n/**\n * @brief Comment the line below if you will not use the peripherals drivers.\n In this case, these drivers will not be included and the application code will \n be based on direct access to peripherals registers \n */\n#define USE_HAL_DRIVER\n#endif /* USE_HAL_DRIVER */\n\n/**\n * @brief CMSIS Device version number V4.2.0\n */\n#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */\n#define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */\n#define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\n#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ \n#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\\\n |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\\\n |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\\\n |(__STM32F1_CMSIS_VERSION_RC))\n\n/**\n * @}\n */\n\n/** @addtogroup Device_Included\n * @{\n */\n\n#if defined(STM32F100xB)\n #include \"stm32f100xb.h\"\n#elif defined(STM32F100xE)\n #include \"stm32f100xe.h\"\n#elif defined(STM32F101x6)\n #include \"stm32f101x6.h\"\n#elif defined(STM32F101xB)\n #include \"stm32f101xb.h\"\n#elif defined(STM32F101xE)\n #include \"stm32f101xe.h\"\n#elif defined(STM32F101xG)\n #include \"stm32f101xg.h\"\n#elif defined(STM32F102x6)\n #include \"stm32f102x6.h\"\n#elif defined(STM32F102xB)\n #include \"stm32f102xb.h\"\n#elif defined(STM32F103x6)\n #include \"stm32f103x6.h\"\n#elif defined(STM32F103xB)\n #include \"stm32f103xb.h\"\n#elif defined(STM32F103xE)\n #include \"stm32f103xe.h\"\n#elif defined(STM32F103xG)\n #include \"stm32f103xg.h\"\n#elif defined(STM32F105xC)\n #include \"stm32f105xc.h\"\n#elif defined(STM32F107xC)\n #include \"stm32f107xc.h\"\n#else\n #error \"Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)\"\n#endif\n\n/**\n * @}\n */\n\n/** @addtogroup Exported_types\n * @{\n */ \ntypedef enum \n{\n RESET = 0, \n SET = !RESET\n} FlagStatus, ITStatus;\n\ntypedef enum \n{\n DISABLE = 0, \n ENABLE = !DISABLE\n} FunctionalState;\n#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\n\ntypedef enum \n{\n ERROR = 0, \n SUCCESS = !ERROR\n} ErrorStatus;\n\n/**\n * @}\n */\n\n\n/** @addtogroup Exported_macros\n * @{\n */\n#define SET_BIT(REG, BIT) ((REG) |= (BIT))\n\n#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))\n\n#define READ_BIT(REG, BIT) ((REG) & (BIT))\n\n#define CLEAR_REG(REG) ((REG) = (0x0))\n\n#define WRITE_REG(REG, VAL) ((REG) = (VAL))\n\n#define READ_REG(REG) ((REG))\n\n#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\n\n#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) \n\n\n/**\n * @}\n */\n\n#if defined (USE_HAL_DRIVER)\n #include \"stm32f1xx_hal.h\"\n#endif /* USE_HAL_DRIVER */\n\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F1xx_H */\n/**\n * @}\n */\n\n/**\n * @}\n */\n \n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F103xC/device/system_stm32f1xx.h", "content": "/**\n ******************************************************************************\n * @file system_stm32f10x.h\n * @author MCD Application Team\n * @version V4.2.0\n * @date 31-March-2017\n * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.\n ******************************************************************************\n * @attention\n *\n *

© COPYRIGHT(c) 2017 STMicroelectronics

\n *\n * Redistribution and use in source and binary forms, with or without modification,\n * are permitted provided that the following conditions are met:\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and/or other materials provided with the distribution.\n * 3. Neither the name of STMicroelectronics nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n ******************************************************************************\n */\n\n/** @addtogroup CMSIS\n * @{\n */\n\n/** @addtogroup stm32f10x_system\n * @{\n */ \n \n/**\n * @brief Define to prevent recursive inclusion\n */\n#ifndef __SYSTEM_STM32F10X_H\n#define __SYSTEM_STM32F10X_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif \n\n/** @addtogroup STM32F10x_System_Includes\n * @{\n */\n\n/**\n * @}\n */\n\n\n/** @addtogroup STM32F10x_System_Exported_types\n * @{\n */\n\nextern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\nextern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */\nextern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */\n\n/**\n * @}\n */\n\n/** @addtogroup STM32F10x_System_Exported_Constants\n * @{\n */\n\n/**\n * @}\n */\n\n/** @addtogroup STM32F10x_System_Exported_Macros\n * @{\n */\n\n/**\n * @}\n */\n\n/** @addtogroup STM32F10x_System_Exported_Functions\n * @{\n */\n \nextern void SystemInit(void);\nextern void SystemCoreClockUpdate(void);\nextern void SetSysClock(void);\n\n/**\n * @}\n */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /*__SYSTEM_STM32F10X_H */\n\n/**\n * @}\n */\n \n/**\n * @}\n */ \n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F103xC/device/us_ticker_data.h", "content": "/* mbed Microcontroller Library\n * Copyright (c) 2006-2018 ARM Limited\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n#ifndef __US_TICKER_DATA_H\n#define __US_TICKER_DATA_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n#include \"stm32f1xx.h\"\n#include \"stm32f1xx_ll_tim.h\"\n#include \"cmsis_nvic.h\"\n \n#define TIM_MST TIM4\n#define TIM_MST_IRQ TIM4_IRQn\n#define TIM_MST_RCC __HAL_RCC_TIM4_CLK_ENABLE()\n#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM4()\n\n#define TIM_MST_RESET_ON __HAL_RCC_TIM4_FORCE_RESET()\n#define TIM_MST_RESET_OFF __HAL_RCC_TIM4_RELEASE_RESET()\n\n#define TIM_MST_BIT_WIDTH 16 // 16 or 32\n\n#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif // __US_TICKER_DATA_H\n\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F103xC/objects.h", "content": "/* mbed Microcontroller Library\n *******************************************************************************\n * Copyright (c) 2016, STMicroelectronics\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n * 2. Redistributions in binary form must reproduce the above copyright notice,\n * this list of conditions and the following disclaimer in the documentation\n * and/or other materials provided with the distribution.\n * 3. Neither the name of STMicroelectronics nor the names of its contributors\n * may be used to endorse or promote products derived from this software\n * without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *******************************************************************************\n */\n#ifndef MBED_OBJECTS_H\n#define MBED_OBJECTS_H\n\n#include \"cmsis.h\"\n#include \"PortNames.h\"\n#include \"PeripheralNames.h\"\n#include \"PinNames.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nstruct gpio_irq_s {\n IRQn_Type irq_n;\n uint32_t irq_index;\n uint32_t event;\n PinName pin;\n};\n\nstruct port_s {\n PortName port;\n uint32_t mask;\n PinDirection direction;\n __IO uint32_t *reg_in;\n __IO uint32_t *reg_out;\n};\n\n#include \"common_objects.h\"\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F4/drivers/SDIO/SDIOBlockDevice.cpp", "content": "/* mbed Microcontroller Library\n * Copyright (c) 2017 ARM Limited\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#include \n#include \"platform/mbed_debug.h\"\n#include \"platform/mbed_wait_api.h\"\n#include \"SDIOBlockDevice.h\"\n\nnamespace mbed\n{\n\n/*\n * defines\n */\n\n#define SD_DBG 0 /*!< 1 - Enable debugging */\n#define SD_CMD_TRACE 0 /*!< 1 - Enable SD command tracing */\n\n#define SD_BLOCK_DEVICE_ERROR_WOULD_BLOCK -5001 /*!< operation would block */\n#define SD_BLOCK_DEVICE_ERROR_UNSUPPORTED -5002 /*!< unsupported operation */\n#define SD_BLOCK_DEVICE_ERROR_PARAMETER -5003 /*!< invalid parameter */\n#define SD_BLOCK_DEVICE_ERROR_NO_INIT -5004 /*!< uninitialized */\n#define SD_BLOCK_DEVICE_ERROR_NO_DEVICE -5005 /*!< device is missing or not connected */\n#define SD_BLOCK_DEVICE_ERROR_WRITE_PROTECTED -5006 /*!< write protected */\n#define SD_BLOCK_DEVICE_ERROR_UNUSABLE -5007 /*!< unusable card */\n#define SD_BLOCK_DEVICE_ERROR_NO_RESPONSE -5008 /*!< No response from device */\n#define SD_BLOCK_DEVICE_ERROR_CRC -5009 /*!< CRC error */\n#define SD_BLOCK_DEVICE_ERROR_ERASE -5010 /*!< Erase error: reset/sequence */\n#define SD_BLOCK_DEVICE_ERROR_WRITE -5011 /*!< SPI Write error: !SPI_DATA_ACCEPTED */\n#define SD_BLOCK_DEVICE_ERROR_UNSUPPORTED_BLOCKSIZE -5012 /*!< unsupported blocksize, only 512 byte supported */\n#define SD_BLOCK_DEVICE_ERROR_READBLOCKS -5013 /*!< read data blocks from SD failed */\n#define SD_BLOCK_DEVICE_ERROR_WRITEBLOCKS -5014 /*!< write data blocks to SD failed */\n#define SD_BLOCK_DEVICE_ERROR_ERASEBLOCKS -5015 /*!< erase data blocks to SD failed */\n\n#define BLOCK_SIZE_HC 512 /*!< Block size supported for SD card is 512 bytes */\n\n// Types\n#define SDCARD_NONE 0 /**< No card is present */\n#define SDCARD_V1 1 /**< v1.x Standard Capacity */\n#define SDCARD_V2 2 /**< v2.x Standard capacity SD card */\n#define SDCARD_V2HC 3 /**< v2.x High capacity SD card */\n#define CARD_UNKNOWN 4 /**< Unknown or unsupported card */\n\n#ifndef MBED_CONF_SD_TIMEOUT\n#define MBED_CONF_SD_TIMEOUT (30 * 1000) /* ms */\n#endif\n\nSDIOBlockDevice::SDIOBlockDevice(PinName cardDetect) : _cardDetect(cardDetect),\n _is_initialized(0),\n _sectors(0),\n _init_ref_count(0)\n{\n _card_type = SDCARD_NONE;\n\n // Only HC block size is supported.\n _block_size = BLOCK_SIZE_HC;\n _erase_size = BLOCK_SIZE_HC;\n}\n\nSDIOBlockDevice::~SDIOBlockDevice()\n{\n if (_is_initialized)\n {\n deinit();\n }\n}\n\nint SDIOBlockDevice::init()\n{\n debug_if(SD_DBG, \"init Card...\\r\\n\");\n\n lock();\n\n if (!_is_initialized)\n {\n _init_ref_count = 0;\n }\n\n _init_ref_count++;\n\n if (_init_ref_count != 1)\n {\n unlock();\n return BD_ERROR_OK;\n }\n\n if (isPresent() == false)\n {\n unlock();\n return SD_BLOCK_DEVICE_ERROR_NO_DEVICE;\n }\n\n int status = SD_Init();\n if (BD_ERROR_OK != status)\n {\n unlock();\n return BD_ERROR_DEVICE_ERROR;\n }\n\n SD_GetCardInfo(&_cardInfo);\n _is_initialized = true;\n debug_if(SD_DBG, \"SD initialized: type: %ld version: %ld class: %ld\\n\",\n _cardInfo.CardType, _cardInfo.CardVersion, _cardInfo.Class);\n debug_if(SD_DBG, \"SD size: %ld MB\\n\",\n _cardInfo.LogBlockNbr / 2 / 1024);\n\n // get sectors count from cardinfo\n _sectors = _cardInfo.LogBlockNbr;\n if (BLOCK_SIZE_HC != _cardInfo.BlockSize)\n {\n unlock();\n return SD_BLOCK_DEVICE_ERROR_UNSUPPORTED_BLOCKSIZE;\n }\n\n unlock();\n return status;\n}\n\nint SDIOBlockDevice::deinit()\n{\n debug_if(SD_DBG, \"deinit Card...\\r\\n\");\n lock();\n\n if (!_is_initialized)\n {\n _init_ref_count = 0;\n unlock();\n return BD_ERROR_OK;\n }\n\n _init_ref_count--;\n\n if (_init_ref_count)\n {\n unlock();\n return BD_ERROR_OK;\n }\n\n int status = SD_DeInit();\n _is_initialized = false;\n\n _sectors = 0;\n\n unlock();\n return status;\n}\n\nint SDIOBlockDevice::read(void *buffer, bd_addr_t addr, bd_size_t size)\n{\n lock();\n if (isPresent() == false)\n {\n unlock();\n return SD_BLOCK_DEVICE_ERROR_NO_DEVICE;\n }\n if (!is_valid_read(addr, size))\n {\n unlock();\n return SD_BLOCK_DEVICE_ERROR_PARAMETER;\n }\n\n if (!_is_initialized)\n {\n unlock();\n return SD_BLOCK_DEVICE_ERROR_NO_INIT;\n }\n\n uint32_t *_buffer = static_cast(buffer);\n\n // ReadBlocks uses byte unit address\n // SDHC and SDXC Cards different addressing is handled in ReadBlocks()\n bd_addr_t blockCnt = size / _block_size;\n addr = addr / _block_size;\n\n // make sure card is ready\n {\n uint32_t tickstart = HAL_GetTick();\n while (SD_GetCardState() != SD_TRANSFER_OK)\n {\n // wait until SD ready\n if ((HAL_GetTick() - tickstart) >= MBED_CONF_SD_TIMEOUT)\n {\n unlock();\n return SD_BLOCK_DEVICE_ERROR_READBLOCKS;\n }\n }\n }\n\n // receive the data : one block/ multiple blocks is handled in ReadBlocks()\n int status = SD_ReadBlocks_DMA(_buffer, addr, blockCnt);\n debug_if(SD_DBG, \"ReadBlocks dbgtest addr: %lld blockCnt: %lld \\n\", addr, blockCnt);\n\n if (status == MSD_OK)\n {\n // wait until DMA finished\n uint32_t tickstart = HAL_GetTick();\n while (SD_DMA_ReadPending() != SD_TRANSFER_OK)\n {\n if ((HAL_GetTick() - tickstart) >= MBED_CONF_SD_TIMEOUT)\n {\n unlock();\n return SD_BLOCK_DEVICE_ERROR_READBLOCKS;\n }\n }\n // make sure card is ready\n tickstart = HAL_GetTick();\n while (SD_GetCardState() != SD_TRANSFER_OK)\n {\n // wait until SD ready\n if ((HAL_GetTick() - tickstart) >= MBED_CONF_SD_TIMEOUT)\n {\n unlock();\n return SD_BLOCK_DEVICE_ERROR_READBLOCKS;\n }\n }\n }\n else\n {\n debug_if(SD_DBG, \"ReadBlocks failed! addr: %lld blockCnt: %lld \\n\", addr, blockCnt);\n unlock();\n return SD_BLOCK_DEVICE_ERROR_READBLOCKS;\n }\n\n unlock();\n return status;\n}\n\nint SDIOBlockDevice::program(const void *buffer, bd_addr_t addr, bd_size_t size)\n{\n lock();\n\n if (isPresent() == false)\n {\n unlock();\n return SD_BLOCK_DEVICE_ERROR_NO_DEVICE;\n }\n if (!is_valid_program(addr, size))\n {\n unlock();\n return SD_BLOCK_DEVICE_ERROR_PARAMETER;\n }\n\n if (!_is_initialized)\n {\n unlock();\n return SD_BLOCK_DEVICE_ERROR_NO_INIT;\n }\n\n // HAL layer uses uint32_t for addr/size\n uint32_t *_buffer = (uint32_t *)(buffer);\n\n // Get block count\n bd_size_t blockCnt = size / _block_size;\n addr = addr / _block_size;\n\n // make sure card is ready\n {\n uint32_t tickstart = HAL_GetTick();\n while (SD_GetCardState() != SD_TRANSFER_OK)\n {\n // wait until SD ready\n if ((HAL_GetTick() - tickstart) >= MBED_CONF_SD_TIMEOUT)\n {\n unlock();\n return SD_BLOCK_DEVICE_ERROR_WRITEBLOCKS;\n }\n }\n }\n\n int status = SD_WriteBlocks_DMA(_buffer, addr, blockCnt);\n debug_if(SD_DBG, \"WriteBlocks dbgtest addr: %lld blockCnt: %lld \\n\", addr, blockCnt);\n\n if (status == MSD_OK)\n {\n // wait until DMA finished\n uint32_t tickstart = HAL_GetTick();\n while (SD_DMA_WritePending() != SD_TRANSFER_OK)\n {\n if ((HAL_GetTick() - tickstart) >= MBED_CONF_SD_TIMEOUT)\n {\n unlock();\n return SD_BLOCK_DEVICE_ERROR_WRITEBLOCKS;\n }\n }\n // make sure card is ready\n tickstart = HAL_GetTick();\n while (SD_GetCardState() != SD_TRANSFER_OK)\n {\n // wait until SD ready\n if ((HAL_GetTick() - tickstart) >= MBED_CONF_SD_TIMEOUT)\n {\n unlock();\n return SD_BLOCK_DEVICE_ERROR_WRITEBLOCKS;\n }\n }\n }\n else\n {\n debug_if(SD_DBG, \"WriteBlocks failed! addr: %lld blockCnt: %lld \\n\", addr, blockCnt);\n unlock();\n return SD_BLOCK_DEVICE_ERROR_WRITEBLOCKS;\n }\n\n unlock();\n return status;\n}\n\nint SDIOBlockDevice::trim(bd_addr_t addr, bd_size_t size)\n{\n debug_if(SD_DBG, \"trim Card...\\r\\n\");\n lock();\n if (isPresent() == false)\n {\n unlock();\n return SD_BLOCK_DEVICE_ERROR_NO_DEVICE;\n }\n if (!_is_valid_trim(addr, size))\n {\n unlock();\n return SD_BLOCK_DEVICE_ERROR_PARAMETER;\n }\n\n if (!_is_initialized)\n {\n unlock();\n return SD_BLOCK_DEVICE_ERROR_NO_INIT;\n }\n\n bd_size_t blockCnt = size / _block_size;\n addr = addr / _block_size;\n\n int status = SD_Erase(addr, blockCnt);\n if (status != 0)\n {\n debug_if(SD_DBG, \"Erase blocks failed! addr: %lld blockCnt: %lld \\n\", addr, blockCnt);\n unlock();\n return SD_BLOCK_DEVICE_ERROR_ERASEBLOCKS;\n }\n else\n {\n uint32_t tickstart = HAL_GetTick();\n while (SD_GetCardState() != SD_TRANSFER_OK)\n {\n // wait until SD ready\n if ((HAL_GetTick() - tickstart) >= MBED_CONF_SD_TIMEOUT)\n {\n unlock();\n return SD_BLOCK_DEVICE_ERROR_ERASEBLOCKS;\n }\n }\n }\n\n unlock();\n return status;\n}\n\nbd_size_t SDIOBlockDevice::get_read_size() const\n{\n return _block_size;\n}\n\nbd_size_t SDIOBlockDevice::get_program_size() const\n{\n return _block_size;\n}\n\nbd_size_t SDIOBlockDevice::size() const\n{\n return _block_size * _sectors;\n}\n\nvoid SDIOBlockDevice::debug(bool dbg)\n{\n}\n\nbool SDIOBlockDevice::_is_valid_trim(bd_addr_t addr, bd_size_t size)\n{\n return (\n addr % _erase_size == 0 &&\n size % _erase_size == 0 &&\n addr + size <= this->size());\n}\n\nbool SDIOBlockDevice::isPresent(void)\n{\n if (_cardDetect.is_connected()) {\n return (_cardDetect.read() == 0);\n }\n else {\n return true;\n }\n}\n\nconst char *SDIOBlockDevice::get_type() const\n{\n return \"SDIO\";\n}\n\n} // namespace mbed\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F4/drivers/SDIO/SDIOBlockDevice.h", "content": "/* mbed Microcontroller Library\n * Copyright (c) 2017 ARM Limited\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef MBED_OS_FEATURES_STORAGE_BLOCKDEVICE_SDIOBLOCKDEVICE_H_\n\n#define MBED_OS_FEATURES_STORAGE_BLOCKDEVICE_SDIOBLOCKDEVICE_H_\n\n#include \"BlockDevice.h\"\n#include \"DigitalIn.h\"\n#include \"PlatformMutex.h\"\n#include \"sdio_device.h\"\n\nnamespace mbed\n{\n\nclass SDIOBlockDevice : public BlockDevice\n{\n public:\n SDIOBlockDevice(PinName cardDetect = NC);\n virtual ~SDIOBlockDevice();\n /** Initialize a block device\n *\n * @return 0 on success or a negative error code on failure\n */\n virtual int init();\n\n /** Deinitialize a block device\n *\n * @return 0 on success or a negative error code on failure\n */\n virtual int deinit();\n\n /** Read blocks from a block device\n *\n * @param buffer Buffer to write blocks to\n * @param addr Address of block to begin reading from\n * @param size Size to read in bytes, must be a multiple of read block size\n * @return 0 on success, negative error code on failure\n */\n virtual int read(void *buffer, bd_addr_t addr, bd_size_t size);\n\n /** Program blocks to a block device\n *\n * The blocks must have been erased prior to being programmed\n *\n * @param buffer Buffer of data to write to blocks\n * @param addr Address of block to begin writing to\n * @param size Size to write in bytes, must be a multiple of program block size\n * @return 0 on success, negative error code on failure\n */\n virtual int program(const void *buffer, bd_addr_t addr, bd_size_t size);\n\n /** Mark blocks as no longer in use\n *\n * This function provides a hint to the underlying block device that a region of blocks\n * is no longer in use and may be erased without side effects. Erase must still be called\n * before programming, but trimming allows flash-translation-layers to schedule erases when\n * the device is not busy.\n *\n * @param addr Address of block to mark as unused\n * @param size Size to mark as unused in bytes, must be a multiple of erase block size\n * @return 0 on success, negative error code on failure\n */\n virtual int trim(bd_addr_t addr, bd_size_t size);\n\n /** Get the size of a readable block\n *\n * @return Size of a readable block in bytes\n */\n virtual bd_size_t get_read_size() const;\n\n /** Get the size of a programable block\n *\n * @return Size of a programable block in bytes\n * @note Must be a multiple of the read size\n */\n virtual bd_size_t get_program_size() const;\n\n /** Get the total size of the underlying device\n *\n * @return Size of the underlying device in bytes\n */\n virtual bd_size_t size() const;\n\n /** Enable or disable debugging\n *\n * @param dbg State of debugging\n */\n virtual void debug(bool dbg);\n\n /** Set the transfer frequency\n *\n * @param freq Transfer frequency\n * @note Max frequency supported is 25MHZ\n */\n virtual int frequency(uint64_t freq) { return BD_ERROR_OK; };\n\n /** check if SD is present\n *\n * @note check physical present switch. Maybe not support by hardware, then function will always return true.\n */\n virtual bool isPresent(void);\n\n /** Get the BlockDevice class type.\n *\n * @return A string representation of the BlockDevice class type.\n */\n virtual const char *get_type() const;\n\n\n private:\n DigitalIn _cardDetect;\n bool _is_initialized;\n bd_size_t _block_size;\n bd_size_t _erase_size;\n bd_size_t _sectors;\n uint32_t _init_ref_count;\n SD_Cardinfo_t _cardInfo;\n uint32_t _card_type;\n\n PlatformMutex _mutex;\n virtual void lock()\n {\n _mutex.lock();\n }\n\n virtual void unlock()\n {\n _mutex.unlock();\n }\n\n bool _is_valid_trim(bd_addr_t addr, bd_size_t size);\n};\n\n} // namespace mbed\n\n#endif /* MBED_OS_FEATURES_STORAGE_BLOCKDEVICE_SDIOBLOCKDEVICE_H_ */\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F4/drivers/SDIO/sdio_device.c", "content": "/* mbed Microcontroller Library\n * Copyright (c) 2017 ARM Limited\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n\n#include \"sdio_device.h\"\n#include \"platform/mbed_error.h\"\n\n/* Extern variables ---------------------------------------------------------*/\n\nSD_HandleTypeDef hsd;\nDMA_HandleTypeDef hdma_sdio_rx;\nDMA_HandleTypeDef hdma_sdio_tx;\n\n// simple flags for DMA pending signaling\nvolatile uint8_t SD_DMA_ReadPendingState = SD_TRANSFER_OK;\nvolatile uint8_t SD_DMA_WritePendingState = SD_TRANSFER_OK;\n\n/* DMA Handlers are global, there is only one SDIO interface */\n\n/**\n* @brief This function handles SDIO global interrupt.\n*/\nvoid _SDIO_IRQHandler(void)\n{\n HAL_SD_IRQHandler(&hsd);\n}\n\n/**\n* @brief This function handles DMAx stream_n global interrupt. DMA Rx\n*/\nvoid _DMA_Stream_Rx_IRQHandler(void)\n{\n HAL_DMA_IRQHandler(hsd.hdmarx);\n}\n\n/**\n* @brief This function handles DMAx stream_n global interrupt. DMA Tx\n*/\nvoid _DMA_Stream_Tx_IRQHandler(void)\n{\n HAL_DMA_IRQHandler(hsd.hdmatx);\n}\n\n/**\n *\n * @param hsd: Handle for SD handle Structure definition\n */\nvoid HAL_SD_MspInit(SD_HandleTypeDef *hsd)\n{\n IRQn_Type IRQn;\n GPIO_InitTypeDef GPIO_InitStruct;\n\n if (hsd->Instance == SDIO)\n {\n /* Peripheral clock enable */\n __HAL_RCC_SDIO_CLK_ENABLE();\n __HAL_RCC_DMA2_CLK_ENABLE();\n\n /* Enable GPIOs clock */\n __HAL_RCC_GPIOC_CLK_ENABLE();\n __HAL_RCC_GPIOD_CLK_ENABLE();\n\n /**SDIO GPIO Configuration\n PC12 ------> SDIO_CK\n PC11 ------> SDIO_D3\n PC10 ------> SDIO_D2\n PD2 ------> SDIO_CMD\n PC9 ------> SDIO_D1\n PC8 ------> SDIO_D0\n */\n GPIO_InitStruct.Pin = GPIO_PIN_12 | GPIO_PIN_11 | GPIO_PIN_10 | GPIO_PIN_9 | GPIO_PIN_8;\n GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n GPIO_InitStruct.Pull = GPIO_PULLUP;\n GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n GPIO_InitStruct.Alternate = GPIO_AF12_SDIO;\n HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\n\n GPIO_InitStruct.Pin = GPIO_PIN_2;\n GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n GPIO_InitStruct.Pull = GPIO_PULLUP;\n GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n GPIO_InitStruct.Alternate = GPIO_AF12_SDIO;\n HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);\n\n /* NVIC configuration for SDIO interrupts */\n IRQn = SDIO_IRQn;\n HAL_NVIC_SetPriority(IRQn, 0x0E, 0);\n NVIC_SetVector(IRQn, (uint32_t)&_SDIO_IRQHandler);\n HAL_NVIC_EnableIRQ(IRQn);\n\n /* SDIO DMA Init */\n /* SDIO_RX Init */\n hdma_sdio_rx.Instance = DMA2_Stream3;\n hdma_sdio_rx.Init.Channel = DMA_CHANNEL_4;\n hdma_sdio_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;\n hdma_sdio_rx.Init.PeriphInc = DMA_PINC_DISABLE;\n hdma_sdio_rx.Init.MemInc = DMA_MINC_ENABLE;\n hdma_sdio_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;\n hdma_sdio_rx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;\n hdma_sdio_rx.Init.Mode = DMA_PFCTRL;\n hdma_sdio_rx.Init.Priority = DMA_PRIORITY_LOW;\n hdma_sdio_rx.Init.FIFOMode = DMA_FIFOMODE_ENABLE;\n hdma_sdio_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;\n hdma_sdio_rx.Init.MemBurst = DMA_MBURST_INC4;\n hdma_sdio_rx.Init.PeriphBurst = DMA_PBURST_INC4;\n if (HAL_DMA_Init(&hdma_sdio_rx) != HAL_OK)\n {\n error(\"SDIO DMA Init error at %d in %s\", __LINE__, __FILE__);\n }\n\n __HAL_LINKDMA(hsd, hdmarx, hdma_sdio_rx);\n\n /* Deinitialize the stream for new transfer */\n HAL_DMA_DeInit(&hdma_sdio_rx);\n\n /* Configure the DMA stream */\n HAL_DMA_Init(&hdma_sdio_rx);\n\n /* SDIO_TX Init */\n hdma_sdio_tx.Instance = DMA2_Stream6;\n hdma_sdio_tx.Init.Channel = DMA_CHANNEL_4;\n hdma_sdio_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;\n hdma_sdio_tx.Init.PeriphInc = DMA_PINC_DISABLE;\n hdma_sdio_tx.Init.MemInc = DMA_MINC_ENABLE;\n hdma_sdio_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;\n hdma_sdio_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;\n hdma_sdio_tx.Init.Mode = DMA_PFCTRL;\n hdma_sdio_tx.Init.Priority = DMA_PRIORITY_LOW;\n hdma_sdio_tx.Init.FIFOMode = DMA_FIFOMODE_ENABLE;\n hdma_sdio_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;\n hdma_sdio_tx.Init.MemBurst = DMA_MBURST_INC4;\n hdma_sdio_tx.Init.PeriphBurst = DMA_PBURST_INC4;\n if (HAL_DMA_Init(&hdma_sdio_tx) != HAL_OK)\n {\n error(\"SDIO DMA Init error at %d in %s\", __LINE__, __FILE__);\n }\n\n __HAL_LINKDMA(hsd, hdmatx, hdma_sdio_tx);\n\n /* Deinitialize the stream for new transfer */\n HAL_DMA_DeInit(&hdma_sdio_tx);\n\n /* Configure the DMA stream */\n HAL_DMA_Init(&hdma_sdio_tx);\n\n /* Enable NVIC for DMA transfer complete interrupts */\n IRQn = DMA2_Stream3_IRQn;\n NVIC_SetVector(IRQn, (uint32_t)&_DMA_Stream_Rx_IRQHandler);\n HAL_NVIC_SetPriority(IRQn, 0x0F, 0);\n HAL_NVIC_EnableIRQ(IRQn);\n\n IRQn = DMA2_Stream6_IRQn;\n NVIC_SetVector(IRQn, (uint32_t)&_DMA_Stream_Tx_IRQHandler);\n HAL_NVIC_SetPriority(IRQn, 0x0F, 0);\n HAL_NVIC_EnableIRQ(IRQn);\n }\n}\n\n/**\n *\n * @param hsd: Handle for SD handle Structure definition\n */\nvoid HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)\n{\n\n if (hsd->Instance == SDIO)\n {\n /* Peripheral clock disable */\n __HAL_RCC_SDIO_CLK_DISABLE();\n\n /**SDIO GPIO Configuration\n PC12 ------> SDIO_CK\n PC11 ------> SDIO_D3\n PC10 ------> SDIO_D2\n PD2 ------> SDIO_CMD\n PC9 ------> SDIO_D1\n PC8 ------> SDIO_D0\n */\n HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12 | GPIO_PIN_11 | GPIO_PIN_10 | GPIO_PIN_9 | GPIO_PIN_8);\n\n HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2);\n\n /* SDIO DMA DeInit */\n HAL_DMA_DeInit(hsd->hdmarx);\n HAL_DMA_DeInit(hsd->hdmatx);\n }\n}\n\n/**\n * @brief DeInitializes the SD MSP.\n * @param hsd: SD handle\n * @param Params : pointer on additional configuration parameters, can be NULL.\n */\n__weak void SD_MspDeInit(SD_HandleTypeDef *hsd, void *Params)\n{\n static DMA_HandleTypeDef dma_rx_handle;\n static DMA_HandleTypeDef dma_tx_handle;\n\n /* Disable NVIC for DMA transfer complete interrupts */\n HAL_NVIC_DisableIRQ(DMA2_Stream3_IRQn);\n HAL_NVIC_DisableIRQ(DMA2_Stream6_IRQn);\n\n /* Deinitialize the stream for new transfer */\n dma_rx_handle.Instance = DMA2_Stream3;\n HAL_DMA_DeInit(&dma_rx_handle);\n\n /* Deinitialize the stream for new transfer */\n dma_tx_handle.Instance = DMA2_Stream6;\n HAL_DMA_DeInit(&dma_tx_handle);\n\n /* Disable NVIC for SDIO interrupts */\n HAL_NVIC_DisableIRQ(SDIO_IRQn);\n\n /* Disable SDIO clock */\n __HAL_RCC_SDIO_CLK_DISABLE();\n}\n\n/**\n * @brief Enables the SDIO wide bus mode.\n * @param hsd pointer to SD handle\n * @retval error state\n */\nstatic uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)\n{\n uint32_t errorstate = HAL_SD_ERROR_NONE;\n\n if ((SDIO_GetResponse(hsd->Instance, SDIO_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED)\n {\n return HAL_SD_ERROR_LOCK_UNLOCK_FAILED;\n }\n\n /* Send CMD55 APP_CMD with argument as card's RCA.*/\n errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U));\n if (errorstate != HAL_OK)\n {\n return errorstate;\n }\n\n /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */\n errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U);\n if (errorstate != HAL_OK)\n {\n return errorstate;\n }\n\n hsd->Init.BusWide = SDIO_BUS_WIDE_4B;\n SDIO_Init(hsd->Instance, hsd->Init);\n\n return HAL_SD_ERROR_NONE;\n}\n\n/**\n * @brief Initializes the SD card device.\n * @retval SD status\n */\nuint8_t SD_Init(void)\n{\n uint8_t sd_state = MSD_OK;\n\n hsd.Instance = SDIO;\n hsd.Init.ClockEdge = SDIO_CLOCK_EDGE_RISING;\n hsd.Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE;\n hsd.Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE;\n hsd.Init.BusWide = SDIO_BUS_WIDE_1B;\n hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;\n hsd.Init.ClockDiv = 0;\n\n /* HAL SD initialization */\n sd_state = HAL_SD_Init(&hsd);\n /* Configure SD Bus width (4 bits mode selected) */\n if (sd_state == MSD_OK)\n {\n /* Enable wide operation */\n if (SD_WideBus_Enable(&hsd) != HAL_OK)\n {\n sd_state = MSD_ERROR;\n }\n }\n\n return sd_state;\n}\n\n/**\n * @brief DeInitializes the SD card device.\n * @retval SD status\n */\nuint8_t SD_DeInit(void)\n{\n uint8_t sd_state = MSD_OK;\n\n hsd.Instance = SDIO;\n\n /* HAL SD deinitialization */\n if (HAL_SD_DeInit(&hsd) != HAL_OK)\n {\n sd_state = MSD_ERROR;\n }\n\n /* Msp SD deinitialization */\n hsd.Instance = SDIO;\n SD_MspDeInit(&hsd, NULL);\n\n return sd_state;\n}\n\n/**\n * @brief Reads block(s) from a specified address in an SD card, in polling mode.\n * @param pData: Pointer to the buffer that will contain the data to transmit\n * @param ReadAddr: Address from where data is to be read\n * @param NumOfBlocks: Number of SD blocks to read\n * @param Timeout: Timeout for read operation\n * @retval SD status\n */\nuint8_t SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout)\n{\n uint8_t sd_state = MSD_OK;\n\n if (HAL_SD_ReadBlocks(&hsd, (uint8_t *)pData, ReadAddr, NumOfBlocks, Timeout) != HAL_OK)\n {\n sd_state = MSD_ERROR;\n }\n\n return sd_state;\n}\n\n/**\n * @brief Writes block(s) to a specified address in an SD card, in polling mode.\n * @param pData: Pointer to the buffer that will contain the data to transmit\n * @param WriteAddr: Address from where data is to be written\n * @param NumOfBlocks: Number of SD blocks to write\n * @param Timeout: Timeout for write operation\n * @retval SD status\n */\nuint8_t SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout)\n{\n uint8_t sd_state = MSD_OK;\n\n if (HAL_SD_WriteBlocks(&hsd, (uint8_t *)pData, WriteAddr, NumOfBlocks, Timeout) != HAL_OK)\n {\n sd_state = MSD_ERROR;\n }\n\n return sd_state;\n}\n\n/**\n * @brief Reads block(s) from a specified address in an SD card, in DMA mode.\n * @param pData: Pointer to the buffer that will contain the data to transmit\n * @param ReadAddr: Address from where data is to be read\n * @param NumOfBlocks: Number of SD blocks to read\n * @retval SD status\n */\nuint8_t SD_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks)\n{\n uint8_t sd_state = MSD_OK;\n SD_DMA_ReadPendingState = SD_TRANSFER_BUSY;\n\n /* Read block(s) in DMA transfer mode */\n if (HAL_SD_ReadBlocks_DMA(&hsd, (uint8_t *)pData, ReadAddr, NumOfBlocks) != HAL_OK)\n {\n sd_state = MSD_ERROR;\n SD_DMA_ReadPendingState = SD_TRANSFER_OK;\n }\n\n return sd_state;\n}\n\n/**\n * @brief Writes block(s) to a specified address in an SD card, in DMA mode.\n * @param pData: Pointer to the buffer that will contain the data to transmit\n * @param WriteAddr: Address from where data is to be written\n * @param NumOfBlocks: Number of SD blocks to write\n * @retval SD status\n */\nuint8_t SD_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks)\n{\n uint8_t sd_state = MSD_OK;\n SD_DMA_WritePendingState = SD_TRANSFER_BUSY;\n\n /* Write block(s) in DMA transfer mode */\n if (HAL_SD_WriteBlocks_DMA(&hsd, (uint8_t *)pData, WriteAddr, NumOfBlocks) != HAL_OK)\n {\n sd_state = MSD_ERROR;\n SD_DMA_WritePendingState = SD_TRANSFER_OK;\n }\n\n return sd_state;\n}\n\n/**\n * @brief Erases the specified memory area of the given SD card.\n * @param StartAddr: Start byte address\n * @param EndAddr: End byte address\n * @retval SD status\n */\nuint8_t SD_Erase(uint32_t StartAddr, uint32_t EndAddr)\n{\n uint8_t sd_state = MSD_OK;\n\n if (HAL_SD_Erase(&hsd, StartAddr, EndAddr) != HAL_OK)\n {\n sd_state = MSD_ERROR;\n }\n\n return sd_state;\n}\n\n/**\n * @brief Gets the current SD card data status.\n * @param None\n * @retval Data transfer state.\n * This value can be one of the following values:\n * @arg SD_TRANSFER_OK: No data transfer is acting\n * @arg SD_TRANSFER_BUSY: Data transfer is acting\n */\nuint8_t SD_GetCardState(void)\n{\n return ((HAL_SD_GetCardState(&hsd) == HAL_SD_CARD_TRANSFER) ? SD_TRANSFER_OK : SD_TRANSFER_BUSY);\n}\n\n/**\n * @brief Get SD information about specific SD card.\n * @param CardInfo: Pointer to HAL_SD_CardInfoTypedef structure\n * @retval None\n */\nvoid SD_GetCardInfo(SD_Cardinfo_t *CardInfo)\n{\n /* Get SD card Information, copy structure for portability */\n HAL_SD_CardInfoTypeDef HAL_CardInfo;\n\n HAL_SD_GetCardInfo(&hsd, &HAL_CardInfo);\n\n if (CardInfo)\n {\n CardInfo->CardType = HAL_CardInfo.CardType;\n CardInfo->CardVersion = HAL_CardInfo.CardVersion;\n CardInfo->Class = HAL_CardInfo.Class;\n CardInfo->RelCardAdd = HAL_CardInfo.RelCardAdd;\n CardInfo->BlockNbr = HAL_CardInfo.BlockNbr;\n CardInfo->BlockSize = HAL_CardInfo.BlockSize;\n CardInfo->LogBlockNbr = HAL_CardInfo.LogBlockNbr;\n CardInfo->LogBlockSize = HAL_CardInfo.LogBlockSize;\n }\n}\n\n/**\n * @brief Check if a DMA operation is pending\n * @retval DMA operation is pending\n * This value can be one of the following values:\n * @arg SD_TRANSFER_OK: No data transfer is acting\n * @arg SD_TRANSFER_BUSY: Data transfer is acting\n */\nuint8_t SD_DMA_ReadPending(void)\n{\n return SD_DMA_ReadPendingState;\n}\n\n/**\n * @brief Check if a DMA operation is pending\n * @retval DMA operation is pending\n * This value can be one of the following values:\n * @arg SD_TRANSFER_OK: No data transfer is acting\n * @arg SD_TRANSFER_BUSY: Data transfer is acting\n */\nuint8_t SD_DMA_WritePending(void)\n{\n return SD_DMA_WritePendingState;\n}\n\n/**\n * @brief Rx Transfer completed callbacks\n * @param hsd Pointer SD handle\n * @retval None\n */\nvoid HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)\n{\n SD_DMA_ReadPendingState = SD_TRANSFER_OK;\n}\n\n/**\n * @brief Tx Transfer completed callbacks\n * @param hsd Pointer to SD handle\n * @retval None\n */\nvoid HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)\n{\n SD_DMA_WritePendingState = SD_TRANSFER_OK;\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F4/drivers/SDIO/sdio_device.h", "content": "/* mbed Microcontroller Library\n * Copyright (c) 2017 ARM Limited\n *\n * Licensed under the Apache License, Version 2.0 (the \"License\");\n * you may not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * http://www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an \"AS IS\" BASIS,\n * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __SDIO_DEVICE_H\n#define __SDIO_DEVICE_H\n\n#ifdef __cplusplus\nextern \"C\"\n{\n#endif\n\n#include \"stm32f4xx_hal.h\"\n\n /* Typedefs */\n\n typedef struct\n {\n uint32_t CardType; /* Specifies the card Type */\n uint32_t CardVersion; /* Specifies the card version */\n uint32_t Class; /* Specifies the class of the card class */\n uint32_t RelCardAdd; /* Specifies the Relative Card Address */\n uint32_t BlockNbr; /* Specifies the Card Capacity in blocks */\n uint32_t BlockSize; /* Specifies one block size in bytes */\n uint32_t LogBlockNbr; /* Specifies the Card logical Capacity in blocks */\n uint32_t LogBlockSize; /* Specifies logical block size in bytes */\n } SD_Cardinfo_t;\n\n /* External Global var */\n\n extern SD_HandleTypeDef hsd;\n\n/* Exported types */\n/** \n * @brief SD Card information structure \n */\n#define BSP_SD_CardInfo HAL_SD_CardInfoTypeDef\n\n/* Exported constants */\n/**\n * @brief SD status structure definition \n */\n#define MSD_OK ((uint8_t)0x00)\n#define MSD_ERROR ((uint8_t)0x01)\n\n/** \n * @brief SD transfer state definition \n */\n#define SD_TRANSFER_OK ((uint8_t)0x00)\n#define SD_TRANSFER_BUSY ((uint8_t)0x01)\n\n /* Exported functions */\n uint8_t SD_Init(void);\n uint8_t SD_DeInit(void);\n uint8_t SD_ReadBlocks(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks, uint32_t Timeout);\n uint8_t SD_WriteBlocks(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks, uint32_t Timeout);\n uint8_t SD_ReadBlocks_DMA(uint32_t *pData, uint32_t ReadAddr, uint32_t NumOfBlocks);\n uint8_t SD_WriteBlocks_DMA(uint32_t *pData, uint32_t WriteAddr, uint32_t NumOfBlocks);\n uint8_t SD_DMA_ReadPending(void);\n uint8_t SD_DMA_WritePending(void);\n uint8_t SD_Erase(uint32_t StartAddr, uint32_t EndAddr);\n\n uint8_t SD_GetCardState(void);\n void SD_GetCardInfo(SD_Cardinfo_t *CardInfo);\n\n /* callback function for DMA Rx/Tx completete, called by HAL SDIO interrupt handler */\n void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);\n void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __SDIO_DEVICE_H */\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F4/drivers/comms/RemoraComms.cpp", "content": "#include \"mbed.h\"\n#include \"RemoraComms.h\"\n\n#include \"stm32f4xx_hal.h\"\n\nRemoraComms::RemoraComms(volatile rxData_t* ptrRxData, volatile txData_t* ptrTxData, SPI_TypeDef* spiType, PinName interruptPin) :\n ptrRxData(ptrRxData),\n ptrTxData(ptrTxData),\n spiType(spiType),\n interruptPin(interruptPin), \n slaveSelect(interruptPin)\n{\n this->spiHandle.Instance = this->spiType;\n\n if (this->interruptPin == PA_4)\n {\n // interrupt pin is the NSS pin\n sharedSPI = false;\n HAL_NVIC_SetPriority(EXTI4_IRQn, 5, 0);\n }\n else if (this->interruptPin == PC_6)\n {\n // interrupt pin is not the NSS pin, ie the board shares the SPI bus with the SD card\n // configure the SPI in software NSS mode and always on\n sharedSPI = true;\n HAL_NVIC_SetPriority(EXTI9_5_IRQn , 5, 0);\n }\n\n slaveSelect.rise(callback(this, &RemoraComms::processPacket));\n}\n\n\n\nvoid RemoraComms::init()\n{\n if(this->spiHandle.Instance == SPI1)\n {\n printf(\"Initialising SPI1 slave\\n\");\n\n GPIO_InitTypeDef GPIO_InitStruct;\n\n /**SPI1 GPIO Configuration\n PA4 ------> SPI1_NSS\n PA5 ------> SPI1_SCK\n PA6 ------> SPI1_MISO\n PA7 ------> SPI1_MOSI\n */\n GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;\n GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n GPIO_InitStruct.Pull = GPIO_NOPULL;\n GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;\n HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n\n __HAL_RCC_SPI1_CLK_ENABLE();\n\n this->spiHandle.Init.Mode = SPI_MODE_SLAVE;\n this->spiHandle.Init.Direction = SPI_DIRECTION_2LINES;\n this->spiHandle.Init.DataSize = SPI_DATASIZE_8BIT;\n this->spiHandle.Init.CLKPolarity = SPI_POLARITY_LOW;\n this->spiHandle.Init.CLKPhase = SPI_PHASE_1EDGE;\n if (sharedSPI)\n {\n this->spiHandle.Init.NSS = SPI_NSS_SOFT;\n printf(\"SPI is shared with SD card\\n\");\n }\n else\n {\n this->spiHandle.Init.NSS = SPI_NSS_HARD_INPUT;\n } \n this->spiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB;\n this->spiHandle.Init.TIMode = SPI_TIMODE_DISABLE;\n this->spiHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\n this->spiHandle.Init.CRCPolynomial = 10;\n\n HAL_SPI_Init(&this->spiHandle);\n\n if (sharedSPI)\n {\n // set SSI (Slave Select Internal) low, ie same as NSS going low\n CLEAR_BIT(this->spiHandle.Instance->CR1, SPI_CR1_SSI);\n }\n\n printf(\"Initialising DMA for SPI\\n\");\n\n __HAL_RCC_GPIOA_CLK_ENABLE();\n __HAL_RCC_DMA2_CLK_ENABLE();\n\n this->hdma_spi_tx.Instance = DMA2_Stream3;\n this->hdma_spi_tx.Init.Channel = DMA_CHANNEL_3;\n this->hdma_spi_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;\n this->hdma_spi_tx.Init.PeriphInc = DMA_PINC_DISABLE;\n this->hdma_spi_tx.Init.MemInc = DMA_MINC_ENABLE;\n this->hdma_spi_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\n this->hdma_spi_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;\n this->hdma_spi_tx.Init.Mode = DMA_CIRCULAR;\n //this->hdma_spi_tx.Init.Mode = DMA_NORMAL;\n this->hdma_spi_tx.Init.Priority = DMA_PRIORITY_VERY_HIGH;\n this->hdma_spi_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;\n \n HAL_DMA_Init(&this->hdma_spi_tx);\n\n __HAL_LINKDMA(&this->spiHandle, hdmatx, this->hdma_spi_tx);\n\n //HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 0, 0);\n ///NVIC_SetVector(DMA2_Stream3_IRQn, (uint32_t)&DMA2_Stream3_IRQHandler);\n //HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn);\n\n this->hdma_spi_rx.Instance = DMA2_Stream0;\n this->hdma_spi_rx.Init.Channel = DMA_CHANNEL_3;\n this->hdma_spi_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;\n this->hdma_spi_rx.Init.PeriphInc = DMA_PINC_DISABLE;\n this->hdma_spi_rx.Init.MemInc = DMA_MINC_ENABLE;\n this->hdma_spi_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\n this->hdma_spi_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;\n this->hdma_spi_rx.Init.Mode = DMA_CIRCULAR;\n //this->hdma_spi_rx.Init.Mode = DMA_NORMAL;\n this->hdma_spi_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH;\n this->hdma_spi_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;\n\n HAL_DMA_Init(&this->hdma_spi_rx);\n\n __HAL_LINKDMA(&this->spiHandle,hdmarx,this->hdma_spi_rx);\n\n //HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 0, 0);\n //NVIC_SetVector(DMA2_Stream0_IRQn, (uint32_t)&DMA2_Stream0_IRQHandler);\n //HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);\n\n \n this->hdma_memtomem_dma2_stream1.Instance = DMA2_Stream1;\n this->hdma_memtomem_dma2_stream1.Init.Channel = DMA_CHANNEL_0;\n this->hdma_memtomem_dma2_stream1.Init.Direction = DMA_MEMORY_TO_MEMORY;\n this->hdma_memtomem_dma2_stream1.Init.PeriphInc = DMA_PINC_ENABLE;\n this->hdma_memtomem_dma2_stream1.Init.MemInc = DMA_MINC_ENABLE;\n this->hdma_memtomem_dma2_stream1.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\n this->hdma_memtomem_dma2_stream1.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;\n this->hdma_memtomem_dma2_stream1.Init.Mode = DMA_NORMAL;\n this->hdma_memtomem_dma2_stream1.Init.Priority = DMA_PRIORITY_LOW;\n this->hdma_memtomem_dma2_stream1.Init.FIFOMode = DMA_FIFOMODE_ENABLE;\n this->hdma_memtomem_dma2_stream1.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;\n this->hdma_memtomem_dma2_stream1.Init.MemBurst = DMA_MBURST_SINGLE;\n this->hdma_memtomem_dma2_stream1.Init.PeriphBurst = DMA_PBURST_SINGLE;\n\n HAL_DMA_Init(&this->hdma_memtomem_dma2_stream1);\n\n }\n}\n\nvoid RemoraComms::start()\n{\n this->ptrTxData->header = PRU_DATA;\n HAL_SPI_TransmitReceive_DMA(&this->spiHandle, (uint8_t *)this->ptrTxData->txBuffer, (uint8_t *)this->spiRxBuffer.rxBuffer, SPI_BUFF_SIZE);\n}\n\nvoid RemoraComms::processPacket()\n{\n switch (this->spiRxBuffer.header)\n {\n case PRU_READ:\n this->SPIdata = true;\n this->rejectCnt = 0;\n // READ so do nothing with the received data\n break;\n\n case PRU_WRITE:\n this->SPIdata = true;\n this->rejectCnt = 0;\n // we've got a good WRITE header, move the data to rxData\n\n // **** would like to use DMA for this but cannot when the stream is in CIRCULAR mode for the SPI transfer ****\n // TODO: figure out how to use NORMAL mode for SPI...\n //this->status = HAL_DMA_Start(&hdma_memtomem_dma2_stream1, (uint32_t)&this->spiRxBuffer.rxBuffer, (uint32_t)this->rxData->rxBuffer, SPI_BUFF_SIZE);\n //if (this->status != HAL_OK) printf(\"F\\n\");\n\n \n // Do it the slower way. This does not seem to impact performance but not great to stay in ISR context for longer.. :-(\n\n // ensure an atomic access to the rxBuffer\n\t\t// disable thread interrupts\n\t\t__disable_irq(); \n for (int i = 0; i < SPI_BUFF_SIZE; i++)\n {\n this->ptrRxData->rxBuffer[i] = this->spiRxBuffer.rxBuffer[i];\n }\n\t\t// re-enable thread interrupts\n\t\t__enable_irq();\n break;\n\n default:\n this->rejectCnt++;\n if (this->rejectCnt > 5)\n {\n this->SPIdataError = true;\n }\n // reset SPI somehow\n }\n\n HAL_SPI_TransmitReceive_DMA(&this->spiHandle, (uint8_t *)this->ptrTxData->txBuffer, (uint8_t *)this->spiRxBuffer.rxBuffer, SPI_BUFF_SIZE);\n}\n\n\nbool RemoraComms::getStatus(void)\n{\n return this->SPIdata;\n}\n\nvoid RemoraComms::setStatus(bool status)\n{\n this->SPIdata = status;\n}\n\nbool RemoraComms::getError(void)\n{\n return this->SPIdataError;\n}\n\nvoid RemoraComms::setError(bool error)\n{\n this->SPIdataError = error;\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F4/drivers/comms/RemoraComms.h", "content": "#ifndef REMORASPI_H\n#define REMORASPI_H\n\n#include \"mbed.h\"\n#include \"configuration.h\"\n#include \"remora.h\"\n\n#include \"stm32f4xx_hal.h\"\n\n\n\nclass RemoraComms\n{\n private:\n\n SPI_TypeDef* spiType;\n SPI_HandleTypeDef spiHandle;\n DMA_HandleTypeDef hdma_spi_tx;\n DMA_HandleTypeDef hdma_spi_rx;\n DMA_HandleTypeDef hdma_memtomem_dma2_stream1;\n HAL_StatusTypeDef status;\n\n volatile rxData_t* ptrRxData;\n volatile txData_t* ptrTxData;\n rxData_t spiRxBuffer;\n uint8_t rejectCnt;\n bool SPIdata;\n bool SPIdataError;\n \n PinName interruptPin;\n InterruptIn slaveSelect;\n bool sharedSPI;\n \n void processPacket(void);\n\n public:\n\n RemoraComms(volatile rxData_t*, volatile txData_t*, SPI_TypeDef*, PinName);\n void init(void);\n void start(void);\n bool getStatus(void);\n void setStatus(bool);\n bool getError(void);\n void setError(bool);\n\n};\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F4/drivers/pin/pin.cpp", "content": "#include \"mbed.h\"\n\n#include \"pin.h\"\n#include \n#include \n#include \n\n#include \"stm32f4xx_hal.h\"\n\nPin::Pin(std::string portAndPin, int dir) :\n portAndPin(portAndPin),\n dir(dir)\n{\n // Set direction\n if (this->dir == INPUT)\n {\n this->mode = GPIO_MODE_INPUT;\n this->pull = GPIO_NOPULL;\n }\n else\n {\n this->mode = GPIO_MODE_OUTPUT_PP;\n this->pull = GPIO_NOPULL;\n }\n\n this->configPin();\n}\n\nPin::Pin(std::string portAndPin, int dir, int modifier) :\n portAndPin(portAndPin),\n dir(dir),\n modifier(modifier)\n{\n // Set direction\n if (this->dir == INPUT)\n {\n this->mode = GPIO_MODE_INPUT;\n\n // Set pin modifier\n switch(this->modifier)\n {\n case PULLUP:\n printf(\" Setting pin as Pull Up\\n\");\n this->pull = GPIO_PULLUP;\n break;\n case PULLDOWN:\n printf(\" Setting pin as Pull Down\\n\");\n this->pull = GPIO_PULLDOWN;\n break;\n case NONE:\n case PULLNONE:\n printf(\" Setting pin as No Pull\\n\");\n this->pull = GPIO_NOPULL;\n break;\n }\n }\n else\n {\n this->mode = GPIO_MODE_OUTPUT_PP;\n this->pull = GPIO_NOPULL;\n }\n\n\n this->configPin();\n}\n\nvoid Pin::configPin()\n{\n printf(\"Creating Pin @\\n\");\n\n //x can be (A..H) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.\n GPIO_TypeDef* gpios[8] ={GPIOA,GPIOB,GPIOC,GPIOD,GPIOE,GPIOF,GPIOG,GPIOH};\n \n\n if (this->portAndPin[0] == 'P') // PXXX e.g.PA2 PC15\n { \n this->portIndex = this->portAndPin[1] - 'A';\n this->pinNumber = this->portAndPin[3] - '0'; \n uint16_t pin2 = this->portAndPin[4] - '0'; \n\n if (pin2 <= 8) \n {\n this->pinNumber = this->pinNumber * 10 + pin2;\n }\n\n this->pin = 1 << this->pinNumber; // this is equivalent to GPIO_PIN_x definition\n }\n else\n {\n printf(\" Invalid port and pin definition\\n\");\n return;\n } \n\n printf(\" port = GPIO%c\\n\", char('A' + this->portIndex));\n printf(\" pin = %d\\n\", this->pinNumber);\n\n // translate port index into something useful\n this->GPIOx = gpios[this->portIndex];\n\n // enable the peripheral clock\n switch (portIndex){\n case 0:\n __HAL_RCC_GPIOA_CLK_ENABLE();\n break;\n\n case 1:\n __HAL_RCC_GPIOB_CLK_ENABLE();\n break;\n\n case 2:\n __HAL_RCC_GPIOC_CLK_ENABLE();\n break;\n \n case 3:\n __HAL_RCC_GPIOD_CLK_ENABLE();\n break;\n\n case 4:\n __HAL_RCC_GPIOE_CLK_ENABLE();\n break;\n \n case 5:\n __HAL_RCC_GPIOF_CLK_ENABLE();\n break;\n \n case 6:\n __HAL_RCC_GPIOG_CLK_ENABLE();\n break;\n \n case 7:\n __HAL_RCC_GPIOH_CLK_ENABLE();\n break;\n }\n\n this->initPin();\n}\n\n\nvoid Pin::initPin()\n{\n // Configure GPIO pin Output Level\n HAL_GPIO_WritePin(this->GPIOx, this->pin, GPIO_PIN_RESET);\n\n // Configure the GPIO pin\n this->GPIO_InitStruct.Pin = this->pin;\n this->GPIO_InitStruct.Mode = this->mode;\n this->GPIO_InitStruct.Pull = this->pull;\n this->GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\n HAL_GPIO_Init(this->GPIOx, &this->GPIO_InitStruct); \n}\n\nvoid Pin::setAsOutput()\n{\n this->mode = GPIO_MODE_OUTPUT_PP;\n this->pull = GPIO_NOPULL;\n this->initPin();\n}\n\n\nvoid Pin::setAsInput()\n{\n this->mode = GPIO_MODE_INPUT;\n this->pull = GPIO_NOPULL;\n this->initPin();\n}\n\n\nvoid Pin::pull_none()\n{\n this->pull = GPIO_NOPULL;\n this->initPin();\n}\n\n\nvoid Pin::pull_up()\n{\n this->pull = GPIO_PULLUP;\n this->initPin();\n}\n\n\nvoid Pin::pull_down()\n{\n this->pull = GPIO_PULLDOWN;\n this->initPin();\n}\n\n\nPinName Pin::pinToPinName()\n{\n printf(\"PinName = 0x%x\\n\", (this->portIndex << 4) | this->pinNumber);\n return static_cast((this->portIndex << 4) | this->pinNumber);\n}\n\n\n// If available on this pin, return mbed hardware pwm class for this pin\nPwmOut* Pin::hardware_pwm()\n{\n if (this->portIndex == 0)\n {\n if (this->pinNumber == 0) { return new mbed::PwmOut(PA_0); }\n if (this->pinNumber == 1) { return new mbed::PwmOut(PA_1); }\n if (this->pinNumber == 2) { return new mbed::PwmOut(PA_2); }\n if (this->pinNumber == 3) { return new mbed::PwmOut(PA_3); }\n if (this->pinNumber == 5) { return new mbed::PwmOut(PA_5); }\n if (this->pinNumber == 6) { return new mbed::PwmOut(PA_6); }\n if (this->pinNumber == 7) { return new mbed::PwmOut(PA_7); }\n if (this->pinNumber == 8) { return new mbed::PwmOut(PA_8); }\n if (this->pinNumber == 9) { return new mbed::PwmOut(PA_9); }\n if (this->pinNumber == 10) { return new mbed::PwmOut(PA_10); }\n if (this->pinNumber == 11) { return new mbed::PwmOut(PA_11); }\n if (this->pinNumber == 15) { return new mbed::PwmOut(PA_15); }\n }\n else if (this->portIndex == 1)\n {\n if (this->pinNumber == 0) { return new mbed::PwmOut(PB_0); }\n if (this->pinNumber == 1) { return new mbed::PwmOut(PB_1); }\n if (this->pinNumber == 3) { return new mbed::PwmOut(PB_3); }\n if (this->pinNumber == 4) { return new mbed::PwmOut(PB_4); }\n if (this->pinNumber == 5) { return new mbed::PwmOut(PB_5); }\n if (this->pinNumber == 6) { return new mbed::PwmOut(PB_6); }\n if (this->pinNumber == 7) { return new mbed::PwmOut(PB_7); }\n if (this->pinNumber == 8) { return new mbed::PwmOut(PB_8); }\n if (this->pinNumber == 9) { return new mbed::PwmOut(PB_9); }\n if (this->pinNumber == 10) { return new mbed::PwmOut(PB_10); }\n if (this->pinNumber == 11) { return new mbed::PwmOut(PB_11); }\n if (this->pinNumber == 13) { return new mbed::PwmOut(PB_13); }\n if (this->pinNumber == 14) { return new mbed::PwmOut(PB_14); }\n if (this->pinNumber == 15) { return new mbed::PwmOut(PB_15); }\n }\n else if (this->portIndex == 2)\n {\n if (this->pinNumber == 6) { return new mbed::PwmOut(PC_6); }\n if (this->pinNumber == 7) { return new mbed::PwmOut(PC_7); }\n if (this->pinNumber == 8) { return new mbed::PwmOut(PC_8); }\n if (this->pinNumber == 9) { return new mbed::PwmOut(PC_9); }\n }\n else if (this->portIndex == 3)\n {\n if (this->pinNumber == 12) { return new mbed::PwmOut(PD_12); }\n if (this->pinNumber == 13) { return new mbed::PwmOut(PD_13); }\n if (this->pinNumber == 14) { return new mbed::PwmOut(PD_14); }\n if (this->pinNumber == 15) { return new mbed::PwmOut(PD_15); }\n }\n else if (this->portIndex == 4)\n {\n if (this->pinNumber == 5) { return new mbed::PwmOut(PE_5); }\n if (this->pinNumber == 6) { return new mbed::PwmOut(PE_6); }\n if (this->pinNumber == 8) { return new mbed::PwmOut(PE_8); }\n if (this->pinNumber == 9) { return new mbed::PwmOut(PE_9); }\n if (this->pinNumber == 10) { return new mbed::PwmOut(PE_10); }\n if (this->pinNumber == 11) { return new mbed::PwmOut(PE_11); }\n if (this->pinNumber == 12) { return new mbed::PwmOut(PE_12); }\n if (this->pinNumber == 13) { return new mbed::PwmOut(PE_13); }\n if (this->pinNumber == 14) { return new mbed::PwmOut(PE_14); }\n }\n return nullptr;\n}" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F4/drivers/pin/pin.h", "content": "#ifndef PIN_H\n#define PIN_H\n\n#include \"mbed.h\"\n\n#include \n#include \n#include \n#include \n\n#include \"stm32f4xx_hal.h\"\n\n#define INPUT 0x0\n#define OUTPUT 0x1\n\n#define NONE 0b000\n#define OPENDRAIN 0b001\n#define PULLUP 0b010\n#define PULLDOWN 0b011\n#define PULLNONE 0b100\n\nclass Pin\n{\n private:\n\n std::string portAndPin;\n uint8_t dir;\n uint8_t modifier;\n uint8_t portIndex;\n uint16_t pinNumber;\n uint16_t pin;\n uint32_t mode;\n uint32_t pull;\n uint32_t speed;\n GPIO_TypeDef* GPIOx;\n GPIO_InitTypeDef GPIO_InitStruct = {0};\n\n public:\n\n Pin(std::string, int);\n Pin(std::string, int, int);\n\n PwmOut* hardware_pwm();\n\n void configPin();\n void initPin();\n void setAsOutput();\n void setAsInput();\n void pull_none();\n void pull_up();\n void pull_down();\n PinName pinToPinName();\n\n inline bool get()\n {\n return HAL_GPIO_ReadPin(this->GPIOx, this->pin);\n }\n\n inline void set(bool value)\n {\n if (value)\n {\n HAL_GPIO_WritePin(this->GPIOx, this->pin, GPIO_PIN_SET);\n }\n else\n {\n HAL_GPIO_WritePin(this->GPIOx, this->pin, GPIO_PIN_RESET);\n }\n }\n};\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F4/drivers/qei/qeiDriver.cpp", "content": "#include \"mbed.h\"\n\n#include \"qeiDriver.h\"\n\nQEIdriver::QEIdriver() :\n qeiIndex(NC)\n{\n this->hasIndex = false;\n this->init();\n}\n\n\nQEIdriver::QEIdriver(bool hasIndex) :\n hasIndex(hasIndex),\n qeiIndex(PE_13)\n{\n this->hasIndex = true;\n this->irq = EXTI15_10_IRQn;\n\n this->init();\n\n qeiIndex.rise(callback(this, &QEIdriver::interruptHandler));\n //NVIC_EnableIRQ(this->irq);\n HAL_NVIC_SetPriority(this->irq, 0, 0);\n}\n\n\nvoid QEIdriver::interruptHandler()\n{\n this->indexDetected = true;\n this->indexCount = this->get();\n}\n\n\nuint32_t QEIdriver::get()\n{\n return __HAL_TIM_GET_COUNTER(&htim);\n}\n\n\n// reference https://os.mbed.com/users/gregeric/code/Nucleo_Hello_Encoder/\n\nvoid QEIdriver::init()\n{\n printf(\" Initialising hardware QEI module\\n\");\n\n this->htim.Instance = TIM1;\n this->htim.Init.Prescaler = 0;\n this->htim.Init.CounterMode = TIM_COUNTERMODE_UP;\n //this->htim.Init.Period = 0xffffffff; // 32-bit count for TIM2\n this->htim.Init.Period = 65535;\n this->htim.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\n this->htim.Init.RepetitionCounter = 0;\n\n this->sConfig.EncoderMode = TIM_ENCODERMODE_TI12;\n\n this->sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;\n this->sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;\n this->sConfig.IC1Prescaler = TIM_ICPSC_DIV1;\n this->sConfig.IC1Filter = 0;\n\n this->sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;\n this->sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;\n this->sConfig.IC2Prescaler = TIM_ICPSC_DIV1;\n this->sConfig.IC2Filter = 0;\n\n if (HAL_TIM_Encoder_Init(&this->htim, &this->sConfig) != HAL_OK)\n {\n printf(\"Couldn't Init Encoder\\r\\n\");\n }\n\n this->sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;\n this->sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;\n HAL_TIMEx_MasterConfigSynchronization(&this->htim, &this->sMasterConfig);\n\n if (HAL_TIM_Encoder_Start(&this->htim, TIM_CHANNEL_2)!=HAL_OK)\n {\n printf(\"Couldn't Start Encoder\\r\\n\");\n }\n}\n\n\nvoid HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)\n{\n GPIO_InitTypeDef GPIO_InitStruct = {0};\n if(htim_encoder->Instance==TIM1)\n {\n __HAL_RCC_TIM1_CLK_ENABLE();\n\n __HAL_RCC_GPIOE_CLK_ENABLE();\n /**TIM1 GPIO Configuration\n PE9 ------> TIM1_CH1\n PE11 ------> TIM1_CH2\n */\n GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_11;\n GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n GPIO_InitStruct.Pull = GPIO_NOPULL;\n GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\n GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;\n HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);\n }\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F4/drivers/qei/qeiDriver.h", "content": "#ifndef QEIDRIVER_H\n#define QEIDRIVER_H\n\n#include \"mbed.h\"\n\n#include \n#include \n#include \n#include \n\n#include \"stm32f4xx_hal.h\"\n\n\nclass QEIdriver\n{\n private:\n\n TIM_HandleTypeDef htim;\n TIM_Encoder_InitTypeDef sConfig = {0};\n TIM_MasterConfigTypeDef sMasterConfig = {0};\n\n InterruptIn qeiIndex;\n IRQn_Type \t\t irq;\n\n void interruptHandler();\n\n public:\n\n bool hasIndex;\n bool indexDetected;\n int32_t indexCount;\n\n QEIdriver(); // for channel A & B\n QEIdriver(bool); // For channels A & B, and index\n\n void init(void);\n uint32_t get(void);\n\n};\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F4/thread/createThreads.h", "content": "#include \"extern.h\"\n\n\nvoid createThreads(void)\n{\n // Create the thread objects and set the interrupt vectors to RAM. This is needed\n // as we are using the SD bootloader that requires a different code starting\n // address. Also set interrupt priority with NVIC_SetPriority.\n\n baseThread = new pruThread(TIM9, TIM1_BRK_TIM9_IRQn, base_freq);\n NVIC_SetVector(TIM1_BRK_TIM9_IRQn, (uint32_t)TIM9_IRQHandler);\n NVIC_SetPriority(TIM1_BRK_TIM9_IRQn, 2);\n\n servoThread = new pruThread(TIM10, TIM1_UP_TIM10_IRQn, servo_freq);\n NVIC_SetVector(TIM1_UP_TIM10_IRQn, (uint32_t)TIM10_IRQHandler);\n NVIC_SetPriority(TIM1_UP_TIM10_IRQn, 3);\n\n commsThread = new pruThread(TIM11, TIM1_TRG_COM_TIM11_IRQn, PRU_COMMSFREQ);\n NVIC_SetVector(TIM1_TRG_COM_TIM11_IRQn, (uint32_t)TIM11_IRQHandler);\n NVIC_SetPriority(TIM1_TRG_COM_TIM11_IRQn, 4);\n}" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F4/thread/interrupt.cpp", "content": "#include \"interrupt.h\"\n#include \"stm32f4xx_hal.h\"\n\n#include \n\n// Define the vector table, it is only declared in the class declaration\nInterrupt* Interrupt::ISRVectorTable[] = {0};\n\n// Constructor\nInterrupt::Interrupt(void){}\n\n\n// Methods\n\nvoid Interrupt::Register(int interruptNumber, Interrupt* intThisPtr)\n{\n\tprintf(\"Registering interrupt for interrupt number = %d\\n\", interruptNumber);\n\tISRVectorTable[interruptNumber] = intThisPtr;\n}\n\n//void Interrupt::TIM3_Wrapper(void)\n//{\n//\tISRVectorTable[TIM3_IRQn]->ISR_Handler();\n//}\n\nvoid Interrupt::TIM9_Wrapper(void)\n{\n\tISRVectorTable[TIM1_BRK_TIM9_IRQn]->ISR_Handler();\n}\n\nvoid Interrupt::TIM10_Wrapper(void)\n{\n\tISRVectorTable[TIM1_UP_TIM10_IRQn]->ISR_Handler();\n}\n\nvoid Interrupt::TIM11_Wrapper(void)\n{\n\tISRVectorTable[TIM1_TRG_COM_TIM11_IRQn]->ISR_Handler();\n}" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F4/thread/interrupt.h", "content": "#ifndef INTERRUPT_H\n#define INTERRUPT_H\n\n// Base class for all interrupt derived classes\n\n#define PERIPH_COUNT_IRQn\t82\t\t\t\t// Total number of device interrupt sources\n\nclass Interrupt\n{\n\tprotected:\n\n\t\tstatic Interrupt* ISRVectorTable[PERIPH_COUNT_IRQn];\n\n\tpublic:\n\n\t\tInterrupt(void);\n\n\t\t//static Interrupt* ISRVectorTable[PERIPH_COUNT_IRQn];\n\n\t\tstatic void Register(int interruptNumber, Interrupt* intThisPtr);\n\n\t\t// wrapper functions to ISR_Handler()\n //static void TIM3_Wrapper();\n\t\tstatic void TIM9_Wrapper();\n static void TIM10_Wrapper();\n static void TIM11_Wrapper();\n\n\t\tvirtual void ISR_Handler(void) = 0;\n\n};\n\n#endif\n\n/****** STM32 specific Interrupt Numbers *********************************************************************\n WWDG_IRQn = 0, !SR & TIM_SR_UIF) // if UIF flag is set\n// {\n// TIM3->SR &= ~TIM_SR_UIF; // clear UIF flag\n \n// Interrupt::TIM3_Wrapper();\n// }\n//}\n\n\nvoid TIM9_IRQHandler()\n{\n if(TIM9->SR & TIM_SR_UIF) // if UIF flag is set\n {\n TIM9->SR &= ~TIM_SR_UIF; // clear UIF flag\n \n Interrupt::TIM9_Wrapper();\n }\n}\n\nvoid TIM10_IRQHandler()\n{\n if(TIM10->SR & TIM_SR_UIF) // if UIF flag is set\n {\n TIM10->SR &= ~TIM_SR_UIF; // clear UIF flag\n \n Interrupt::TIM10_Wrapper();\n }\n}\n\nvoid TIM11_IRQHandler()\n{\n if(TIM11->SR & TIM_SR_UIF) // if UIF flag is set\n {\n TIM11->SR &= ~TIM_SR_UIF; // clear UIF flag\n \n Interrupt::TIM11_Wrapper();\n }\n}" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F4/thread/pruThread.cpp", "content": "#include \"pruThread.h\"\n#include \"modules/module.h\"\n\n\nusing namespace std;\n\n// Thread constructor\npruThread::pruThread(TIM_TypeDef* timer, IRQn_Type irq, uint32_t frequency) :\n\ttimer(timer),\n\tirq(irq),\n\tfrequency(frequency)\n{\n\tprintf(\"Creating thread %d\\n\", this->frequency);\n}\n\nvoid pruThread::startThread(void)\n{\n\tTimerPtr = new pruTimer(this->timer, this->irq, this->frequency, this);\n}\n\nvoid pruThread::stopThread(void)\n{\n this->TimerPtr->stopTimer();\n}\n\n\nvoid pruThread::registerModule(Module* module)\n{\n\tthis->vThread.push_back(module);\n}\n\n\nvoid pruThread::unregisterModule(Module* module)\n{\n\titer = std::remove(vThread.begin(),vThread.end(), module);\n vThread.erase(iter, vThread.end());\n}\n\nvoid pruThread::run(void)\n{\n\t// iterate over the Thread pointer vector to run all instances of Module::runModule()\n\tfor (iter = vThread.begin(); iter != vThread.end(); ++iter) (*iter)->runModule();\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F4/thread/pruThread.h", "content": "#ifndef PRUTHREAD_H\n#define PRUTHREAD_H\n\n#include \"stm32f4xx_hal.h\"\n#include \"timer.h\"\n\n// Standard Template Library (STL) includes\n#include \n#include \n\nusing namespace std;\n\nclass Module;\n\nclass pruThread\n{\n\n\tprivate:\n\n\t\tpruTimer* \t\t TimerPtr;\n\t\n\t\tTIM_TypeDef* \t timer;\n\t\tIRQn_Type \t\t\tirq;\n\t\tuint32_t \t\t\tfrequency;\n\n\t\tvector vThread;\t\t// vector containing pointers to Thread modules\n\t\tvector::iterator iter;\n\n\tpublic:\n\n\t\tpruThread(TIM_TypeDef* timer, IRQn_Type irq, uint32_t frequency);\n\n\t\tvoid registerModule(Module *module);\n void unregisterModule(Module *module);\n\t\tvoid startThread(void);\n void stopThread(void);\n\t\tvoid run(void);\n};\n\n#endif\n\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F4/thread/timer.cpp", "content": "#include \"mbed.h\"\n#include \"stm32f4xx_hal.h\"\n\n#include \n#include \n\n#include \"interrupt.h\"\n#include \"timerInterrupt.h\"\n#include \"timer.h\"\n#include \"pruThread.h\"\n\n\n\n// Timer constructor\npruTimer::pruTimer(TIM_TypeDef* timer, IRQn_Type irq, uint32_t frequency, pruThread* ownerPtr):\n\ttimer(timer),\n\tirq(irq),\n\tfrequency(frequency),\n\ttimerOwnerPtr(ownerPtr)\n{\n\tinterruptPtr = new TimerInterrupt(this->irq, this);\t// Instantiate a new Timer Interrupt object and pass \"this\" pointer\n\n\tthis->startTimer();\n}\n\n\nvoid pruTimer::timerTick(void)\n{\n\t//Do something here\n\tthis->timerOwnerPtr->run();\n}\n\n\n\nvoid pruTimer::startTimer(void)\n{\n uint32_t TIM_CLK;\n\n if (this->timer == TIM3)\n {\n printf(\"\tpower on Timer 3\\n\\r\");\n __TIM3_CLK_ENABLE();\n TIM_CLK = APB2CLK;\n }\n else if (this->timer == TIM9)\n {\n printf(\"\tpower on Timer 9\\n\\r\");\n __TIM9_CLK_ENABLE();\n TIM_CLK = APB1CLK;\n }\n else if (this->timer == TIM10)\n {\n printf(\"\tpower on Timer 10\\n\\r\");\n __TIM10_CLK_ENABLE();\n TIM_CLK = APB1CLK;\n }\n else if (this->timer == TIM11)\n {\n printf(\"\tpower on Timer 11\\n\\r\");\n __TIM11_CLK_ENABLE();\n TIM_CLK = APB1CLK;\n }\n\n //timer uptade frequency = TIM_CLK/(TIM_PSC+1)/(TIM_ARR + 1)\n\n this->timer->CR2 &= 0; // UG used as trigg output\n this->timer->PSC = TIM_PSC-1; // prescaler\n this->timer->ARR = ((TIM_CLK / TIM_PSC / this->frequency) - 1); // period \n this->timer->EGR = TIM_EGR_UG; // reinit the counter\n this->timer->DIER = TIM_DIER_UIE; // enable update interrupts\n\n this->timer->CR1 |= TIM_CR1_CEN; // enable timer\n\n NVIC_EnableIRQ(this->irq);\n}\n\nvoid pruTimer::stopTimer()\n{\n NVIC_DisableIRQ(this->irq);\n\n printf(\"\ttimer stop\\n\\r\");\n this->timer->CR1 &= (~(TIM_CR1_CEN)); // disable timer\n}" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TARGET_STM32F4/thread/timer.h", "content": "#ifndef TIMER_H\n#define TIMER_H\n\n#include \"mbed.h\"\n#include \n\n#define TIM_PSC 4\n#define APB1CLK SystemCoreClock\n#define APB2CLK SystemCoreClock/2\n\nclass TimerInterrupt; // forward declatation\nclass pruThread; // forward declatation\n\nclass pruTimer\n{\n\tfriend class TimerInterrupt;\n\n\tprivate:\n\n\t\tTimerInterrupt* \tinterruptPtr;\n\t\tTIM_TypeDef* \t timer;\n\t\tIRQn_Type \t\t\tirq;\n\t\tuint32_t \t\t\tfrequency;\n\t\tpruThread* \t\t\ttimerOwnerPtr;\n\n\t\tvoid startTimer(void);\n\t\tvoid timerTick();\t\t\t// Private timer tiggered method\n\n\tpublic:\n\n\t\tpruTimer(TIM_TypeDef* timer, IRQn_Type irq, uint32_t frequency, pruThread* ownerPtr);\n void stopTimer(void);\n\n};\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/.hg/branch", "content": "default\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/.hg/cache/branch2-base", "content": "5ba0c258c4ed90a7b2d84a782374f254077a2acc 1\n5ba0c258c4ed90a7b2d84a782374f254077a2acc o default\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/.hg/cache/rbc-names-v1", "content": "default" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/.hg/cache/tags2-visible", "content": "1 5ba0c258c4ed90a7b2d84a782374f254077a2acc\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/.hg/hgrc", "content": "# example repository config (see 'hg help config' for more info)\n[paths]\nmbed-studio-cache = c:\\Users\\tanya\\AppData\\Local\\Mbed Studio\\library-cache\\os.mbed.com\\users\\charly\\code\\TMCStepper\ndefault = https://os.mbed.com/users/charly/code/TMCStepper/\n\n# path aliases to other clones of this repo in URLs or filesystem paths\n# (see 'hg help config.paths' for more info)\n#\n# default:pushurl = ssh://jdoe@example.net/hg/jdoes-fork\n# my-fork = ssh://jdoe@example.net/hg/jdoes-fork\n# my-clone = /home/jdoe/jdoes-clone\n\n[ui]\n# name and email (local to this repository, optional), e.g.\n# username = Jane Doe \n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/.hg/requires", "content": "dotencode\nfncache\ngeneraldelta\nrevlogv1\nsparserevlog\nstore\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/.hg/store/fncache", "content": "data/DRV_STATUS.cpp.i\ndata/TMC_MACROS.h.i\ndata/TMCStepper.cpp.i\ndata/TMC2208Stepper.cpp.i\ndata/GCONF.cpp.i\ndata/IHOLD_IRUN.cpp.i\ndata/TMC2209_bitfields.h.i\ndata/TMCStepper.h.i\ndata/TMC2208_bitfields.h.i\ndata/CHOPCONF.cpp.i\ndata/TMC2209Stepper.cpp.i\ndata/PWMCONF.cpp.i\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/.hg/thgstatus", "content": "m\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/CHOPCONF.cpp", "content": "#include \"TMCStepper.h\"\n#include \"TMC_MACROS.h\"\n\n#define SET_REG(SETTING) CHOPCONF_register.SETTING = B; write(CHOPCONF_register.address, CHOPCONF_register.sr)\n\n// CHOPCONF\n/*\nuint32_t TMC2130Stepper::CHOPCONF() {\n return read(CHOPCONF_register.address);\n}\nvoid TMC2130Stepper::CHOPCONF(uint32_t input) {\n CHOPCONF_register.sr = input;\n write(CHOPCONF_register.address, CHOPCONF_register.sr);\n}\n\nvoid TMC2130Stepper::toff( uint8_t B ) { SET_REG(toff); }\nvoid TMC2130Stepper::hstrt( uint8_t B ) { SET_REG(hstrt); }\nvoid TMC2130Stepper::hend( uint8_t B ) { SET_REG(hend); }\n//void TMC2130Stepper::fd( uint8_t B ) { SET_REG(fd); }\nvoid TMC2130Stepper::disfdcc( bool B ) { SET_REG(disfdcc); }\nvoid TMC2130Stepper::rndtf( bool B ) { SET_REG(rndtf); }\nvoid TMC2130Stepper::chm( bool B ) { SET_REG(chm); }\nvoid TMC2130Stepper::tbl( uint8_t B ) { SET_REG(tbl); }\nvoid TMC2130Stepper::vsense( bool B ) { SET_REG(vsense); }\nvoid TMC2130Stepper::vhighfs( bool B ) { SET_REG(vhighfs); }\nvoid TMC2130Stepper::vhighchm( bool B ) { SET_REG(vhighchm);}\nvoid TMC2130Stepper::sync( uint8_t B ) { SET_REG(sync); }\nvoid TMC2130Stepper::mres( uint8_t B ) { SET_REG(mres); }\nvoid TMC2130Stepper::intpol( bool B ) { SET_REG(intpol); }\nvoid TMC2130Stepper::dedge( bool B ) { SET_REG(dedge); }\nvoid TMC2130Stepper::diss2g( bool B ) { SET_REG(diss2g); }\n\nuint8_t TMC2130Stepper::toff() { CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.toff; }\nuint8_t TMC2130Stepper::hstrt() { CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.hstrt; }\nuint8_t TMC2130Stepper::hend() { CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.hend; }\n//uint8_t TMC2130Stepper::fd() { CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.fd; }\nbool TMC2130Stepper::disfdcc() { CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.disfdcc; }\nbool TMC2130Stepper::rndtf() { CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.rndtf; }\nbool TMC2130Stepper::chm() { CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.chm; }\nuint8_t TMC2130Stepper::tbl() { CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.tbl; }\nbool TMC2130Stepper::vsense() { CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.vsense; }\nbool TMC2130Stepper::vhighfs() { CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.vhighfs; }\nbool TMC2130Stepper::vhighchm() { CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.vhighchm;}\nuint8_t TMC2130Stepper::sync() { CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.sync; }\nuint8_t TMC2130Stepper::mres() { CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.mres; }\nbool TMC2130Stepper::intpol() { CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.intpol; }\nbool TMC2130Stepper::dedge() { CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.dedge; }\nbool TMC2130Stepper::diss2g() { CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.diss2g; }\n\nvoid TMC5160Stepper::diss2vs(bool B){ SET_REG(diss2vs); }\nvoid TMC5160Stepper::tpfd(uint8_t B){ SET_REG(tpfd); }\nbool TMC5160Stepper::diss2vs() { CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.diss2vs; }\nuint8_t TMC5160Stepper::tpfd() { CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.tpfd; }\n*/\nvoid TMC2208Stepper::CHOPCONF(uint32_t input) {\n CHOPCONF_register.sr = input;\n write(CHOPCONF_register.address, CHOPCONF_register.sr);\n}\nuint32_t TMC2208Stepper::CHOPCONF() {\n return read(CHOPCONF_register.address);\n}\nvoid TMC2208Stepper::toff ( uint8_t B ) { SET_REG(toff); }\nvoid TMC2208Stepper::hstrt ( uint8_t B ) { SET_REG(hstrt); }\nvoid TMC2208Stepper::hend ( uint8_t B ) { SET_REG(hend); }\nvoid TMC2208Stepper::tbl ( uint8_t B ) { SET_REG(tbl); }\nvoid TMC2208Stepper::vsense ( bool B ) { SET_REG(vsense); }\nvoid TMC2208Stepper::mres ( uint8_t B ) { SET_REG(mres); }\nvoid TMC2208Stepper::intpol ( bool B ) { SET_REG(intpol); }\nvoid TMC2208Stepper::dedge ( bool B ) { SET_REG(dedge); }\nvoid TMC2208Stepper::diss2g ( bool B ) { SET_REG(diss2g); }\nvoid TMC2208Stepper::diss2vs( bool B ) { SET_REG(diss2vs); }\n\nuint8_t TMC2208Stepper::toff() { TMC2208_n::CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.toff; }\nuint8_t TMC2208Stepper::hstrt() { TMC2208_n::CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.hstrt; }\nuint8_t TMC2208Stepper::hend() { TMC2208_n::CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.hend; }\nuint8_t TMC2208Stepper::tbl() { TMC2208_n::CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.tbl; }\nbool TMC2208Stepper::vsense() { TMC2208_n::CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.vsense; }\nuint8_t TMC2208Stepper::mres() { TMC2208_n::CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.mres; }\nbool TMC2208Stepper::intpol() { TMC2208_n::CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.intpol; }\nbool TMC2208Stepper::dedge() { TMC2208_n::CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.dedge; }\nbool TMC2208Stepper::diss2g() { TMC2208_n::CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.diss2g; }\nbool TMC2208Stepper::diss2vs() { TMC2208_n::CHOPCONF_t r{0}; r.sr = CHOPCONF(); return r.diss2vs; }\n/*\n#define GET_REG_2660(SETTING) return CHOPCONF_register.SETTING;\n\nuint32_t TMC2660Stepper::CHOPCONF() { return CHOPCONF_register.sr; }\nvoid TMC2660Stepper::CHOPCONF(uint32_t data) {\n CHOPCONF_register.sr = data;\n write(CHOPCONF_register.address, CHOPCONF_register.sr);\n}\n\nvoid TMC2660Stepper::toff(uint8_t B) {\n SET_REG(toff);\n if (B>0) _savedToff = B;\n}\nvoid TMC2660Stepper::hstrt(uint8_t B) { SET_REG(hstrt); }\nvoid TMC2660Stepper::hend(uint8_t B) { SET_REG(hend); }\nvoid TMC2660Stepper::hdec(uint8_t B) { SET_REG(hdec); }\nvoid TMC2660Stepper::rndtf(bool B) { SET_REG(rndtf); }\nvoid TMC2660Stepper::chm(bool B) { SET_REG(chm); }\nvoid TMC2660Stepper::tbl(uint8_t B) { SET_REG(tbl); }\n\nuint8_t TMC2660Stepper::toff() { GET_REG_2660(toff); }\nuint8_t TMC2660Stepper::hstrt() { GET_REG_2660(hstrt); }\nuint8_t TMC2660Stepper::hend() { GET_REG_2660(hend); }\nuint8_t TMC2660Stepper::hdec() { GET_REG_2660(hdec); }\nbool TMC2660Stepper::rndtf() { GET_REG_2660(rndtf); }\nbool TMC2660Stepper::chm() { GET_REG_2660(chm); }\nuint8_t TMC2660Stepper::tbl() { GET_REG_2660(tbl); }\n*/" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/COOLCONF.cpp", "content": "#include \"TMCStepper.h\"\n#include \"TMC_MACROS.h\"\n\n#define SET_REG(SETTING) COOLCONF_register.SETTING = B; write(COOLCONF_register.address, COOLCONF_register.sr);\n#define GET_REG(SETTING) return COOLCONF_register.SETTING;\n\n// COOLCONF\nuint16_t TMC2209Stepper::COOLCONF() { return COOLCONF_register.sr; }\nvoid TMC2209Stepper::COOLCONF(uint16_t input) {\n\tCOOLCONF_register.sr = input;\n\twrite(COOLCONF_register.address, COOLCONF_register.sr);\n}\n\nvoid TMC2209Stepper::semin(\tuint8_t B )\t{ SET_REG(semin);\t}\nvoid TMC2209Stepper::seup(\tuint8_t B )\t{ SET_REG(seup);\t}\nvoid TMC2209Stepper::semax(\tuint8_t B )\t{ SET_REG(semax);\t}\nvoid TMC2209Stepper::sedn(\tuint8_t B )\t{ SET_REG(sedn);\t}\nvoid TMC2209Stepper::seimin(bool \tB )\t{ SET_REG(seimin);\t}\n\nuint8_t TMC2209Stepper::semin()\t{ GET_REG(semin);\t}\nuint8_t TMC2209Stepper::seup()\t{ GET_REG(seup);\t}\nuint8_t TMC2209Stepper::semax()\t{ GET_REG(semax);\t}\nuint8_t TMC2209Stepper::sedn()\t{ GET_REG(sedn);\t}\nbool \tTMC2209Stepper::seimin(){ GET_REG(seimin);\t}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/DRV_STATUS.cpp", "content": "#include \"TMCStepper.h\"\n#include \"TMC_MACROS.h\"\n\n#define GET_REG(NS, SETTING) NS::DRV_STATUS_t r{0}; r.sr = DRV_STATUS(); return r.SETTING\n/*\nuint32_t TMC2130Stepper::DRV_STATUS() { return read(DRV_STATUS_t::address); }\n\nuint16_t TMC2130Stepper::sg_result(){ GET_REG(TMC2130_n, sg_result); }\nbool TMC2130Stepper::fsactive() { GET_REG(TMC2130_n, fsactive); }\nuint8_t TMC2130Stepper::cs_actual() { GET_REG(TMC2130_n, cs_actual); }\nbool TMC2130Stepper::stallguard() { GET_REG(TMC2130_n, stallGuard); }\nbool TMC2130Stepper::ot() { GET_REG(TMC2130_n, ot); }\nbool TMC2130Stepper::otpw() { GET_REG(TMC2130_n, otpw); }\nbool TMC2130Stepper::s2ga() { GET_REG(TMC2130_n, s2ga); }\nbool TMC2130Stepper::s2gb() { GET_REG(TMC2130_n, s2gb); }\nbool TMC2130Stepper::ola() { GET_REG(TMC2130_n, ola); }\nbool TMC2130Stepper::olb() { GET_REG(TMC2130_n, olb); }\nbool TMC2130Stepper::stst() { GET_REG(TMC2130_n, stst); }\n*/\nuint32_t TMC2208Stepper::DRV_STATUS() {\n return read(TMC2208_n::DRV_STATUS_t::address);\n}\n\nbool TMC2208Stepper::otpw() { GET_REG(TMC2208_n, otpw); }\nbool TMC2208Stepper::ot() { GET_REG(TMC2208_n, ot); }\nbool TMC2208Stepper::s2ga() { GET_REG(TMC2208_n, s2ga); }\nbool TMC2208Stepper::s2gb() { GET_REG(TMC2208_n, s2gb); }\nbool TMC2208Stepper::s2vsa() { GET_REG(TMC2208_n, s2vsa); }\nbool TMC2208Stepper::s2vsb() { GET_REG(TMC2208_n, s2vsb); }\nbool TMC2208Stepper::ola() { GET_REG(TMC2208_n, ola); }\nbool TMC2208Stepper::olb() { GET_REG(TMC2208_n, olb); }\nbool TMC2208Stepper::t120() { GET_REG(TMC2208_n, t120); }\nbool TMC2208Stepper::t143() { GET_REG(TMC2208_n, t143); }\nbool TMC2208Stepper::t150() { GET_REG(TMC2208_n, t150); }\nbool TMC2208Stepper::t157() { GET_REG(TMC2208_n, t157); }\nuint16_t TMC2208Stepper::cs_actual() { GET_REG(TMC2208_n, cs_actual); }\nbool TMC2208Stepper::stealth() { GET_REG(TMC2208_n, stealth); }\nbool TMC2208Stepper::stst() { GET_REG(TMC2208_n, stst); }" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/GCONF.cpp", "content": "#include \"TMCStepper.h\"\n#include \"TMC_MACROS.h\"\n\n#define SET_REG(SETTING) GCONF_register.SETTING = B; write(GCONF_register.address, GCONF_register.sr)\n\n// GCONF\n/*\nuint32_t TMC2130Stepper::GCONF() {\n return read(GCONF_register.address);\n}\nvoid TMC2130Stepper::GCONF(uint32_t input) {\n GCONF_register.sr = input;\n write(GCONF_register.address, GCONF_register.sr);\n}\n\nvoid TMC2130Stepper::I_scale_analog(bool B) { SET_REG(i_scale_analog); }\nvoid TMC2130Stepper::internal_Rsense(bool B) { SET_REG(internal_rsense); }\nvoid TMC2130Stepper::en_pwm_mode(bool B) { SET_REG(en_pwm_mode); }\nvoid TMC2130Stepper::enc_commutation(bool B) { SET_REG(enc_commutation); }\nvoid TMC2130Stepper::shaft(bool B) { SET_REG(shaft); }\nvoid TMC2130Stepper::diag0_error(bool B) { SET_REG(diag0_error); }\nvoid TMC2130Stepper::diag0_otpw(bool B) { SET_REG(diag0_otpw); }\nvoid TMC2130Stepper::diag0_stall(bool B) { SET_REG(diag0_stall); }\nvoid TMC2130Stepper::diag1_stall(bool B) { SET_REG(diag1_stall); }\nvoid TMC2130Stepper::diag1_index(bool B) { SET_REG(diag1_index); }\nvoid TMC2130Stepper::diag1_onstate(bool B) { SET_REG(diag1_onstate); }\nvoid TMC2130Stepper::diag1_steps_skipped(bool B) { SET_REG(diag1_steps_skipped); }\nvoid TMC2130Stepper::diag0_int_pushpull(bool B) { SET_REG(diag0_int_pushpull); }\nvoid TMC2130Stepper::diag1_pushpull(bool B) { SET_REG(diag1_poscomp_pushpull); }\nvoid TMC2130Stepper::small_hysteresis(bool B) { SET_REG(small_hysteresis); }\nvoid TMC2130Stepper::stop_enable(bool B) { SET_REG(stop_enable); }\nvoid TMC2130Stepper::direct_mode(bool B) { SET_REG(direct_mode); }\n\nbool TMC2130Stepper::I_scale_analog() { GCONF_t r{0}; r.sr = GCONF(); return r.i_scale_analog; }\nbool TMC2130Stepper::internal_Rsense() { GCONF_t r{0}; r.sr = GCONF(); return r.internal_rsense; }\nbool TMC2130Stepper::en_pwm_mode() { GCONF_t r{0}; r.sr = GCONF(); return r.en_pwm_mode; }\nbool TMC2130Stepper::enc_commutation() { GCONF_t r{0}; r.sr = GCONF(); return r.enc_commutation; }\nbool TMC2130Stepper::shaft() { GCONF_t r{0}; r.sr = GCONF(); return r.shaft; }\nbool TMC2130Stepper::diag0_error() { GCONF_t r{0}; r.sr = GCONF(); return r.diag0_error; }\nbool TMC2130Stepper::diag0_otpw() { GCONF_t r{0}; r.sr = GCONF(); return r.diag0_otpw; }\nbool TMC2130Stepper::diag0_stall() { GCONF_t r{0}; r.sr = GCONF(); return r.diag0_stall; }\nbool TMC2130Stepper::diag1_stall() { GCONF_t r{0}; r.sr = GCONF(); return r.diag1_stall; }\nbool TMC2130Stepper::diag1_index() { GCONF_t r{0}; r.sr = GCONF(); return r.diag1_index; }\nbool TMC2130Stepper::diag1_onstate() { GCONF_t r{0}; r.sr = GCONF(); return r.diag1_onstate; }\nbool TMC2130Stepper::diag1_steps_skipped() { GCONF_t r{0}; r.sr = GCONF(); return r.diag1_steps_skipped; }\nbool TMC2130Stepper::diag0_int_pushpull() { GCONF_t r{0}; r.sr = GCONF(); return r.diag0_int_pushpull; }\nbool TMC2130Stepper::diag1_pushpull() { GCONF_t r{0}; r.sr = GCONF(); return r.diag1_poscomp_pushpull;}\nbool TMC2130Stepper::small_hysteresis() { GCONF_t r{0}; r.sr = GCONF(); return r.small_hysteresis; }\nbool TMC2130Stepper::stop_enable() { GCONF_t r{0}; r.sr = GCONF(); return r.stop_enable; }\nbool TMC2130Stepper::direct_mode() { GCONF_t r{0}; r.sr = GCONF(); return r.direct_mode; }\n*/\n/*\nbit 18 not implemented:\ntest_mode 0:\nNormal operation 1:\nEnable analog test output on pin DCO. IHOLD[1..0] selects the function of DCO:\n0…2: T120, DAC, VDDH Attention:\nNot for user, set to 0 for normal operation!\n*/\n/*\nvoid TMC5160Stepper::recalibrate(bool B) { SET_REG(recalibrate); }\nvoid TMC5160Stepper::faststandstill(bool B) { SET_REG(faststandstill); }\nvoid TMC5160Stepper::multistep_filt(bool B) { SET_REG(multistep_filt); }\nbool TMC5160Stepper::recalibrate() { GCONF_t r{0}; r.sr = GCONF(); return r.recalibrate; }\nbool TMC5160Stepper::faststandstill() { GCONF_t r{0}; r.sr = GCONF(); return r.faststandstill; }\nbool TMC5160Stepper::multistep_filt() { GCONF_t r{0}; r.sr = GCONF(); return r.multistep_filt; }\n*/\nuint32_t TMC2208Stepper::GCONF() {\n return read(GCONF_register.address);\n}\nvoid TMC2208Stepper::GCONF(uint32_t input) {\n GCONF_register.sr = input;\n write(GCONF_register.address, GCONF_register.sr);\n}\n\nvoid TMC2208Stepper::I_scale_analog(bool B) { SET_REG(i_scale_analog); }\nvoid TMC2208Stepper::internal_Rsense(bool B) { SET_REG(internal_rsense); }\nvoid TMC2208Stepper::en_spreadCycle(bool B) { SET_REG(en_spreadcycle); }\nvoid TMC2208Stepper::shaft(bool B) { SET_REG(shaft); }\nvoid TMC2208Stepper::index_otpw(bool B) { SET_REG(index_otpw); }\nvoid TMC2208Stepper::index_step(bool B) { SET_REG(index_step); }\nvoid TMC2208Stepper::pdn_disable(bool B) { SET_REG(pdn_disable); }\nvoid TMC2208Stepper::mstep_reg_select(bool B) { SET_REG(mstep_reg_select);}\nvoid TMC2208Stepper::multistep_filt(bool B) { SET_REG(multistep_filt); }\n\nbool TMC2208Stepper::I_scale_analog() { TMC2208_n::GCONF_t r{0}; r.sr = GCONF(); return r.i_scale_analog; }\nbool TMC2208Stepper::internal_Rsense() { TMC2208_n::GCONF_t r{0}; r.sr = GCONF(); return r.internal_rsense; }\nbool TMC2208Stepper::en_spreadCycle() { TMC2208_n::GCONF_t r{0}; r.sr = GCONF(); return r.en_spreadcycle; }\nbool TMC2208Stepper::shaft() { TMC2208_n::GCONF_t r{0}; r.sr = GCONF(); return r.shaft; }\nbool TMC2208Stepper::index_otpw() { TMC2208_n::GCONF_t r{0}; r.sr = GCONF(); return r.index_otpw; }\nbool TMC2208Stepper::index_step() { TMC2208_n::GCONF_t r{0}; r.sr = GCONF(); return r.index_step; }\nbool TMC2208Stepper::pdn_disable() { TMC2208_n::GCONF_t r{0}; r.sr = GCONF(); return r.pdn_disable; }\nbool TMC2208Stepper::mstep_reg_select() { TMC2208_n::GCONF_t r{0}; r.sr = GCONF(); return r.mstep_reg_select; }\nbool TMC2208Stepper::multistep_filt() { TMC2208_n::GCONF_t r{0}; r.sr = GCONF(); return r.multistep_filt; }" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/IHOLD_IRUN.cpp", "content": "#include \"TMCStepper.h\"\n#include \"TMC_MACROS.h\"\n\n#define SET_REG(SETTING) IHOLD_IRUN_register.SETTING = B; write(IHOLD_IRUN_register.address, IHOLD_IRUN_register.sr);\n#define GET_REG(SETTING) return IHOLD_IRUN_register.SETTING;\n\n// IHOLD_IRUN\nuint32_t TMCStepper::IHOLD_IRUN() { return IHOLD_IRUN_register.sr; }\nvoid TMCStepper::IHOLD_IRUN(uint32_t input) {\n IHOLD_IRUN_register.sr = input;\n write(IHOLD_IRUN_register.address, IHOLD_IRUN_register.sr);\n}\n\nvoid TMCStepper::ihold(uint8_t B) { SET_REG(ihold); }\nvoid TMCStepper::irun(uint8_t B) { SET_REG(irun); }\nvoid TMCStepper::iholddelay(uint8_t B) { SET_REG(iholddelay); }\n\nuint8_t TMCStepper::ihold() { GET_REG(ihold); }\nuint8_t TMCStepper::irun() { GET_REG(irun); }\nuint8_t TMCStepper::iholddelay() { GET_REG(iholddelay); }" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/PWMCONF.cpp", "content": "#include \"TMCStepper.h\"\n#include \"TMC_MACROS.h\"\n\n#define SET_REG(SETTING) PWMCONF_register.SETTING = B; write(PWMCONF_register.address, PWMCONF_register.sr)\n#define GET_REG(SETTING) return PWMCONF_register.SETTING\n\n// PWMCONF\n/*\nuint32_t TMC2130Stepper::PWMCONF() { return PWMCONF_register.sr; }\nvoid TMC2130Stepper::PWMCONF(uint32_t input) {\n\tPWMCONF_register.sr = input;\n\twrite(PWMCONF_register.address, PWMCONF_register.sr);\n}\n\nvoid TMC2130Stepper::pwm_ampl(\t\tuint8_t B )\t{ SET_REG(pwm_ampl);\t\t}\nvoid TMC2130Stepper::pwm_grad(\t\tuint8_t B )\t{ SET_REG(pwm_grad);\t\t}\nvoid TMC2130Stepper::pwm_freq(\t\tuint8_t B )\t{ SET_REG(pwm_freq);\t\t}\nvoid TMC2130Stepper::pwm_autoscale(\tbool \tB )\t{ SET_REG(pwm_autoscale);\t}\nvoid TMC2130Stepper::pwm_symmetric(\tbool \tB )\t{ SET_REG(pwm_symmetric);\t}\nvoid TMC2130Stepper::freewheel(\t\tuint8_t B )\t{ SET_REG(freewheel);\t\t}\n\nuint8_t TMC2130Stepper::pwm_ampl()\t\t{ GET_REG(pwm_ampl);\t\t}\nuint8_t TMC2130Stepper::pwm_grad()\t\t{ GET_REG(pwm_grad);\t\t}\nuint8_t TMC2130Stepper::pwm_freq()\t\t{ GET_REG(pwm_freq);\t\t}\nbool \tTMC2130Stepper::pwm_autoscale()\t{ GET_REG(pwm_autoscale);\t}\nbool \tTMC2130Stepper::pwm_symmetric()\t{ GET_REG(pwm_symmetric);\t}\nuint8_t TMC2130Stepper::freewheel()\t\t{ GET_REG(freewheel);\t\t}\n\nuint32_t TMC2160Stepper::PWMCONF() {\n\treturn PWMCONF_register.sr;\n}\nvoid TMC2160Stepper::PWMCONF(uint32_t input) {\n\tPWMCONF_register.sr = input;\n\twrite(PWMCONF_register.address, PWMCONF_register.sr);\n}\n\nvoid TMC2160Stepper::pwm_ofs\t\t( uint8_t B ) { PWMCONF_register.pwm_ofs = B; \t\twrite(PWMCONF_register.address, PWMCONF_register.sr); }\nvoid TMC2160Stepper::pwm_grad\t\t( uint8_t B ) { PWMCONF_register.pwm_grad = B; \t\twrite(PWMCONF_register.address, PWMCONF_register.sr); }\nvoid TMC2160Stepper::pwm_freq\t\t( uint8_t B ) { PWMCONF_register.pwm_freq = B; \t\twrite(PWMCONF_register.address, PWMCONF_register.sr); }\nvoid TMC2160Stepper::pwm_autoscale\t( bool \t B ) { PWMCONF_register.pwm_autoscale = B; write(PWMCONF_register.address, PWMCONF_register.sr); }\nvoid TMC2160Stepper::pwm_autograd\t( bool B ) { PWMCONF_register.pwm_autograd = B; \twrite(PWMCONF_register.address, PWMCONF_register.sr); }\nvoid TMC2160Stepper::freewheel\t\t( uint8_t B ) { PWMCONF_register.freewheel = B; \twrite(PWMCONF_register.address, PWMCONF_register.sr); }\nvoid TMC2160Stepper::pwm_reg\t\t( uint8_t B ) { PWMCONF_register.pwm_reg = B; \t\twrite(PWMCONF_register.address, PWMCONF_register.sr); }\nvoid TMC2160Stepper::pwm_lim\t\t( uint8_t B ) { PWMCONF_register.pwm_lim = B; \t\twrite(PWMCONF_register.address, PWMCONF_register.sr); }\n\nuint8_t TMC2160Stepper::pwm_ofs()\t\t{ return PWMCONF_register.pwm_ofs;\t\t}\nuint8_t TMC2160Stepper::pwm_grad()\t\t{ return PWMCONF_register.pwm_grad;\t\t}\nuint8_t TMC2160Stepper::pwm_freq()\t\t{ return PWMCONF_register.pwm_freq;\t\t}\nbool \tTMC2160Stepper::pwm_autoscale()\t{ return PWMCONF_register.pwm_autoscale;}\nbool \tTMC2160Stepper::pwm_autograd()\t{ return PWMCONF_register.pwm_autograd;\t}\nuint8_t TMC2160Stepper::freewheel()\t\t{ return PWMCONF_register.freewheel;\t}\nuint8_t TMC2160Stepper::pwm_reg()\t\t{ return PWMCONF_register.pwm_reg;\t\t}\nuint8_t TMC2160Stepper::pwm_lim()\t\t{ return PWMCONF_register.pwm_lim;\t\t}\n*/\nuint32_t TMC2208Stepper::PWMCONF() {\n\treturn read(PWMCONF_register.address);\n}\nvoid TMC2208Stepper::PWMCONF(uint32_t input) {\n\tPWMCONF_register.sr = input;\n\twrite(PWMCONF_register.address, PWMCONF_register.sr);\n}\n\nvoid TMC2208Stepper::pwm_ofs\t\t( uint8_t B ) { PWMCONF_register.pwm_ofs = B; write(PWMCONF_register.address, PWMCONF_register.sr); }\nvoid TMC2208Stepper::pwm_grad\t\t( uint8_t B ) { PWMCONF_register.pwm_grad = B; write(PWMCONF_register.address, PWMCONF_register.sr); }\nvoid TMC2208Stepper::pwm_freq\t\t( uint8_t B ) { PWMCONF_register.pwm_freq = B; write(PWMCONF_register.address, PWMCONF_register.sr); }\nvoid TMC2208Stepper::pwm_autoscale\t( bool \t B ) { PWMCONF_register.pwm_autoscale = B; write(PWMCONF_register.address, PWMCONF_register.sr); }\nvoid TMC2208Stepper::pwm_autograd\t( bool B ) { PWMCONF_register.pwm_autograd = B; write(PWMCONF_register.address, PWMCONF_register.sr); }\nvoid TMC2208Stepper::freewheel\t\t( uint8_t B ) { PWMCONF_register.freewheel = B; write(PWMCONF_register.address, PWMCONF_register.sr); }\nvoid TMC2208Stepper::pwm_reg\t\t( uint8_t B ) { PWMCONF_register.pwm_reg = B; write(PWMCONF_register.address, PWMCONF_register.sr); }\nvoid TMC2208Stepper::pwm_lim\t\t( uint8_t B ) { PWMCONF_register.pwm_lim = B; write(PWMCONF_register.address, PWMCONF_register.sr); }\n\nuint8_t TMC2208Stepper::pwm_ofs()\t\t{ TMC2208_n::PWMCONF_t r{0}; r.sr = PWMCONF(); return r.pwm_ofs;\t\t}\nuint8_t TMC2208Stepper::pwm_grad()\t\t{ TMC2208_n::PWMCONF_t r{0}; r.sr = PWMCONF(); return r.pwm_grad;\t\t}\nuint8_t TMC2208Stepper::pwm_freq()\t\t{ TMC2208_n::PWMCONF_t r{0}; r.sr = PWMCONF(); return r.pwm_freq;\t\t}\nbool \tTMC2208Stepper::pwm_autoscale()\t{ TMC2208_n::PWMCONF_t r{0}; r.sr = PWMCONF(); return r.pwm_autoscale;\t}\nbool \tTMC2208Stepper::pwm_autograd()\t{ TMC2208_n::PWMCONF_t r{0}; r.sr = PWMCONF(); return r.pwm_autograd;\t}\nuint8_t TMC2208Stepper::freewheel()\t\t{ TMC2208_n::PWMCONF_t r{0}; r.sr = PWMCONF(); return r.freewheel;\t\t}\nuint8_t TMC2208Stepper::pwm_reg()\t\t{ TMC2208_n::PWMCONF_t r{0}; r.sr = PWMCONF(); return r.pwm_reg;\t\t}\nuint8_t TMC2208Stepper::pwm_lim()\t\t{ TMC2208_n::PWMCONF_t r{0}; r.sr = PWMCONF(); return r.pwm_lim;\t\t}\n\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/TMC2208Stepper.cpp", "content": "#include \"TMCStepper.h\"\n#include \"TMC_MACROS.h\"\n\n// Protected\n// addr needed for TMC2209\nTMC2208Stepper::TMC2208Stepper(std::string SWRXpin, std::string SWTXpin, float RS, uint8_t addr) :\n SWRXpin(SWRXpin),\n SWTXpin(SWRXpin),\n TMCStepper(RS),\n //RXTX_pin(SW_RX_pin == SW_TX_pin ? SW_RX_pin : 0),\n slave_address(addr)\n {\n SoftwareSerial *SWSerialObj = new SoftwareSerial(SWRXpin, SWTXpin);\n SWSerial = SWSerialObj;\n defaults();\n\n\n #if defined TARGET_LPC176X\n //this->debug1 = new DigitalOut(P1_30);\n //this->debug2 = new DigitalOut(P0_28);\n #elif defined TARGET_STM32F4\n //this->debug1 = new DigitalOut(PE_5);\n //this->debug2 = new DigitalOut(PE_4);\n #endif\n\n }\n\n\nvoid TMC2208Stepper::beginSerial(uint32_t baudrate) {\n\n SWSerial->begin(baudrate);\n}\n\n\nvoid TMC2208Stepper::begin() {\n\n beginSerial(19600);\n pdn_disable(true);\n mstep_reg_select(true);\n //Wait to initialize\n wait_ms(replyDelay);\n\n}\n\nvoid TMC2208Stepper::defaults() {\n GCONF_register.i_scale_analog = 1;\n GCONF_register.internal_rsense = 0; // OTP\n GCONF_register.en_spreadcycle = 0; // OTP\n GCONF_register.multistep_filt = 1; // OTP\n IHOLD_IRUN_register.iholddelay = 1; // OTP\n TPOWERDOWN_register.sr = 20;\n CHOPCONF_register.sr = 0x10000053;\n PWMCONF_register.sr = 0xC10D0024;\n //MSLUT0_register.sr = ???;\n //MSLUT1_register.sr = ???;\n //MSLUT2_register.sr = ???;\n //MSLUT3_register.sr = ???;\n //MSLUT4_register.sr = ???;\n //MSLUT5_register.sr = ???;\n //MSLUT6_register.sr = ???;\n //MSLUT7_register.sr = ???;\n //MSLUTSTART_register.start_sin90 = 247;\n}\n\nvoid TMC2208Stepper::push() {\n GCONF(GCONF_register.sr);\n IHOLD_IRUN(IHOLD_IRUN_register.sr);\n SLAVECONF(SLAVECONF_register.sr);\n TPOWERDOWN(TPOWERDOWN_register.sr);\n TPWMTHRS(TPWMTHRS_register.sr);\n VACTUAL(VACTUAL_register.sr);\n CHOPCONF(CHOPCONF_register.sr);\n PWMCONF(PWMCONF_register.sr);\n}\n\nbool TMC2208Stepper::isEnabled() { return !enn() && toff(); }\n\nuint8_t TMC2208Stepper::calcCRC(uint8_t datagram[], uint8_t len) {\n uint8_t crc = 0;\n for (uint8_t i = 0; i < len; i++) {\n uint8_t currentByte = datagram[i];\n for (uint8_t j = 0; j < 8; j++) {\n if ((crc >> 7) ^ (currentByte & 0x01)) {\n crc = (crc << 1) ^ 0x07;\n } else {\n crc = (crc << 1);\n }\n crc &= 0xff;\n currentByte = currentByte >> 1;\n }\n }\n return crc;\n}\n\n__attribute__((weak))\nint TMC2208Stepper::available() {\n int out = 0;\n\n\tout = SWSerial->available();\n\n return out;\n}\n\n\n__attribute__((weak))\nvoid TMC2208Stepper::preWriteCommunication() {\n //this->debug1->write(1);\n}\n\n\n__attribute__((weak))\nvoid TMC2208Stepper::preReadCommunication() {\n\n\tSWSerial->listen();\t\n //this->debug2->write(1);\t\t\t\t\n}\n\n\n__attribute__((weak))\nvoid TMC2208Stepper::postWriteCommunication() {\n //this->debug1->write(0);\n}\n\n\n__attribute__((weak))\nvoid TMC2208Stepper::postReadCommunication() {\n //this->debug2->write(0);\n}\n\n\n__attribute__((weak))\nint16_t TMC2208Stepper::serial_read() {\n int16_t out = 0;\n \n out = SWSerial->read();\n\n\treturn out;\n}\n\n__attribute__((weak))\nuint8_t TMC2208Stepper::serial_write(const uint8_t data) {\n int out = 0;\n\n SWSerial->write(data);\n\n return out;\n}\n\n\nvoid TMC2208Stepper::write(uint8_t addr, uint32_t regVal) {\n uint8_t len = 7;\n addr |= TMC_WRITE;\n uint8_t datagram[] = {TMC2208_SYNC, slave_address, addr, (uint8_t)(regVal>>24), (uint8_t)(regVal>>16), (uint8_t)(regVal>>8), (uint8_t)(regVal>>0), 0x00};\n\t\n datagram[len] = calcCRC(datagram, len);\n\t\n\t//printf(\"write datagram = %x, %x, %x, %x, %x, %x, %x, %x\\n\", datagram[0], datagram[1], datagram[2], datagram[3], datagram[4], datagram[5], datagram[6], datagram[7]);\n \n preWriteCommunication();\n\n for(uint8_t i=0; i<=len; i++) {\n bytesWritten += serial_write(datagram[i]);\n }\n postWriteCommunication();\n\n //delay(replyDelay);\n //ThisThread::sleep_for(150);\n wait_ms(5);\n}\n\nuint64_t TMC2208Stepper::_sendDatagram(uint8_t datagram[], const uint8_t len, uint16_t timeout) {\n\t\n while (available() > 0) serial_read(); // Flush\n\n tmcTimer.reset();\n tmcTimer.start(); \n\n preWriteCommunication();\n\tfor(int i=0; i<=len; i++)\n { \n serial_write(datagram[i]);\n }\n\t//delay(replyDelay);\n //ThisThread::sleep_for(replyDelay);\n postWriteCommunication();\n\n\t// scan for the rx frame and read it\n\tuint32_t ms = tmcTimer.read_ms();\n\tuint32_t sync_target = (static_cast(datagram[0])<<16) | 0xFF00 | datagram[2];\n\tuint32_t sync = 0;\n\n\tdo {\n\t\tuint32_t ms2 = tmcTimer.read_ms();\n\t\tif (ms2 != ms) {\n\t\t\t// 1ms tick\n\t\t\tms = ms2;\n\t\t\ttimeout--;\n\t\t}\n\t\tif (!timeout) return 0;\n\n\t\tint16_t res = serial_read();\n\t\tif (res < 0) continue;\n\n\t\tsync <<= 8;\n\t\tsync |= res & 0xFF;\n\t\tsync &= 0xFFFFFF;\n\n\t} while (sync != sync_target);\n\n\tuint64_t out = sync;\n\tms = tmcTimer.read_ms();\n\ttimeout = this->abort_window;\n\t\t \n\tfor(uint8_t i=0; i<5;) {\n\t\tuint32_t ms2 = tmcTimer.read_ms();\n\t\tif (ms2 != ms) {\n\t\t\t// 1ms tick\n\t\t\tms = ms2;\n\t\t\ttimeout--;\n\t\t}\n\t\tif (!timeout) return 0;\n\n\t\tint16_t res = serial_read();\n\t\tif (res < 0) continue;\n\n\t\tout <<= 8;\n\t\tout |= res & 0xFF;\n\t\ti++;\n\t}\n\n tmcTimer.stop();\n\t\t\n\twhile (available() > 0) serial_read(); // Flush\n\n\treturn out;\n}\n\nuint32_t TMC2208Stepper::read(uint8_t addr) {\n constexpr uint8_t len = 3;\n addr |= TMC_READ;\n uint8_t datagram[] = {TMC2208_SYNC, slave_address, addr, 0x00};\n datagram[len] = calcCRC(datagram, len);\n uint64_t out = 0x00000000UL;\n\n for (uint8_t i = 0; i < max_retries; i++) {\t\t\t \n preReadCommunication();\n out = _sendDatagram(datagram, len, abort_window);\n postReadCommunication();\n\n// delay(replyDelay);\n //ThisThread::sleep_for(replyDelay);\n wait_ms(5);\n\n CRCerror = false;\n uint8_t out_datagram[] = {\n static_cast(out>>56),\n static_cast(out>>48),\n static_cast(out>>40),\n static_cast(out>>32),\n static_cast(out>>24),\n static_cast(out>>16),\n static_cast(out>> 8),\n static_cast(out>> 0)\n };\n //printf(\"read datagram = %x, %x, %x, %x, %x, %x, %x, %x\\n\", out_datagram[0], out_datagram[1], out_datagram[2], out_datagram[3], out_datagram[4], out_datagram[5], out_datagram[6], out_datagram[7]);\n\t\t\n uint8_t crc = calcCRC(out_datagram, 7);\n if ((crc != static_cast(out)) || crc == 0 ) {\n CRCerror = true;\n out = 0;\n } else {\n break;\n }\n }\n\n return out>>8;\n}\n\nuint8_t TMC2208Stepper::IFCNT() {\n return read(IFCNT_t::address);\n}\n\nvoid TMC2208Stepper::SLAVECONF(uint16_t input) {\n SLAVECONF_register.sr = input&0xF00;\n write(SLAVECONF_register.address, SLAVECONF_register.sr);\n}\nuint16_t TMC2208Stepper::SLAVECONF() {\n return SLAVECONF_register.sr;\n}\nvoid TMC2208Stepper::senddelay(uint8_t B) { SLAVECONF_register.senddelay = B; write(SLAVECONF_register.address, SLAVECONF_register.sr); }\nuint8_t TMC2208Stepper::senddelay() { return SLAVECONF_register.senddelay; }\n\nvoid TMC2208Stepper::OTP_PROG(uint16_t input) {\n write(OTP_PROG_t::address, input);\n}\n\nuint32_t TMC2208Stepper::OTP_READ() {\n return read(OTP_READ_t::address);\n}\n\nuint32_t TMC2208Stepper::IOIN() {\n return read(TMC2208_n::IOIN_t::address);\n}\nbool TMC2208Stepper::enn() { TMC2208_n::IOIN_t r{0}; r.sr = IOIN(); return r.enn; }\nbool TMC2208Stepper::ms1() { TMC2208_n::IOIN_t r{0}; r.sr = IOIN(); return r.ms1; }\nbool TMC2208Stepper::ms2() { TMC2208_n::IOIN_t r{0}; r.sr = IOIN(); return r.ms2; }\nbool TMC2208Stepper::diag() { TMC2208_n::IOIN_t r{0}; r.sr = IOIN(); return r.diag; }\nbool TMC2208Stepper::pdn_uart() { TMC2208_n::IOIN_t r{0}; r.sr = IOIN(); return r.pdn_uart; }\nbool TMC2208Stepper::step() { TMC2208_n::IOIN_t r{0}; r.sr = IOIN(); return r.step; }\nbool TMC2208Stepper::sel_a() { TMC2208_n::IOIN_t r{0}; r.sr = IOIN(); return r.sel_a; }\nbool TMC2208Stepper::dir() { TMC2208_n::IOIN_t r{0}; r.sr = IOIN(); return r.dir; }\nuint8_t TMC2208Stepper::version() { TMC2208_n::IOIN_t r{0}; r.sr = IOIN(); return r.version; }\n\n/*\nuint32_t TMC2224Stepper::IOIN() {\n return read(TMC2224_n::IOIN_t::address);\n}\nbool TMC2224Stepper::enn() { TMC2224_n::IOIN_t r{0}; r.sr = IOIN(); return r.enn; }\nbool TMC2224Stepper::ms1() { TMC2224_n::IOIN_t r{0}; r.sr = IOIN(); return r.ms1; }\nbool TMC2224Stepper::ms2() { TMC2224_n::IOIN_t r{0}; r.sr = IOIN(); return r.ms2; }\nbool TMC2224Stepper::pdn_uart() { TMC2224_n::IOIN_t r{0}; r.sr = IOIN(); return r.pdn_uart; }\nbool TMC2224Stepper::spread() { TMC2224_n::IOIN_t r{0}; r.sr = IOIN(); return r.spread; }\nbool TMC2224Stepper::step() { TMC2224_n::IOIN_t r{0}; r.sr = IOIN(); return r.step; }\nbool TMC2224Stepper::sel_a() { TMC2224_n::IOIN_t r{0}; r.sr = IOIN(); return r.sel_a; }\nbool TMC2224Stepper::dir() { TMC2224_n::IOIN_t r{0}; r.sr = IOIN(); return r.dir; }\nuint8_t TMC2224Stepper::version() { TMC2224_n::IOIN_t r{0}; r.sr = IOIN(); return r.version; }\n*/\nuint16_t TMC2208Stepper::FACTORY_CONF() {\n return read(FACTORY_CONF_register.address);\n}\nvoid TMC2208Stepper::FACTORY_CONF(uint16_t input) {\n FACTORY_CONF_register.sr = input;\n write(FACTORY_CONF_register.address, FACTORY_CONF_register.sr);\n}\nvoid TMC2208Stepper::fclktrim(uint8_t B){ FACTORY_CONF_register.fclktrim = B; write(FACTORY_CONF_register.address, FACTORY_CONF_register.sr); }\nvoid TMC2208Stepper::ottrim(uint8_t B) { FACTORY_CONF_register.ottrim = B; write(FACTORY_CONF_register.address, FACTORY_CONF_register.sr); }\nuint8_t TMC2208Stepper::fclktrim() { FACTORY_CONF_t r{0}; r.sr = FACTORY_CONF(); return r.fclktrim; }\nuint8_t TMC2208Stepper::ottrim() { FACTORY_CONF_t r{0}; r.sr = FACTORY_CONF(); return r.ottrim; }\n\nvoid TMC2208Stepper::VACTUAL(uint32_t input) {\n VACTUAL_register.sr = input;\n write(VACTUAL_register.address, VACTUAL_register.sr);\n}\nuint32_t TMC2208Stepper::VACTUAL() {\n return VACTUAL_register.sr;\n}\n\nuint32_t TMC2208Stepper::PWM_SCALE() {\n return read(TMC2208_n::PWM_SCALE_t::address);\n}\nuint8_t TMC2208Stepper::pwm_scale_sum() {\n TMC2208_n::PWM_SCALE_t r{0};\n r.sr = PWM_SCALE();\n return r.pwm_scale_sum;\n}\n\nint16_t TMC2208Stepper::pwm_scale_auto() {\n TMC2208_n::PWM_SCALE_t r{0};\n r.sr = PWM_SCALE();\n return r.pwm_scale_auto;\n // Not two's complement? 9nth bit determines sign\n /*\n uint32_t d = PWM_SCALE();\n int16_t response = (d>>PWM_SCALE_AUTO_bp)&0xFF;\n if (((d&PWM_SCALE_AUTO_bm) >> 24) & 0x1) return -response;\n else return response;\n */\n}\n\n// R: PWM_AUTO\nuint32_t TMC2208Stepper::PWM_AUTO() {\n return read(PWM_AUTO_t::address);\n}\nuint8_t TMC2208Stepper::pwm_ofs_auto() { PWM_AUTO_t r{0}; r.sr = PWM_AUTO(); return r.pwm_ofs_auto; }\nuint8_t TMC2208Stepper::pwm_grad_auto() { PWM_AUTO_t r{0}; r.sr = PWM_AUTO(); return r.pwm_grad_auto; }" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/TMC2208_bitfields.h", "content": "#pragma once\n#pragma pack(push, 1)\n\nnamespace TMC2208_n {\n struct GCONF_t {\n constexpr static uint8_t address = 0x00;\n union {\n uint16_t sr : 10;\n struct {\n bool i_scale_analog : 1,\n internal_rsense : 1,\n en_spreadcycle : 1,\n shaft : 1,\n index_otpw : 1,\n index_step : 1,\n pdn_disable : 1,\n mstep_reg_select : 1,\n multistep_filt : 1,\n test_mode : 1;\n };\n };\n };\n}\n\nnamespace TMC2208_n {\n struct IOIN_t {\n constexpr static uint8_t address = 0x06;\n union {\n uint32_t sr;\n struct {\n bool enn : 1,\n : 1,\n ms1 : 1,\n ms2 : 1,\n diag : 1,\n : 1,\n pdn_uart : 1,\n step : 1,\n sel_a : 1,\n dir : 1;\n uint16_t : 14;\n uint8_t version : 8;\n };\n };\n };\n}\n\nnamespace TMC2224_n {\n struct IOIN_t {\n constexpr static uint8_t address = 0x06;\n union {\n uint32_t sr;\n struct {\n bool : 1,\n pdn_uart : 1,\n spread : 1,\n dir : 1,\n enn : 1,\n step : 1,\n ms1 : 1,\n ms2 : 1,\n sel_a : 1;\n uint16_t : 15;\n uint8_t version : 8;\n };\n };\n };\n}\n\nstruct FACTORY_CONF_t {\n constexpr static uint8_t address = 0x07;\n union {\n uint16_t sr;\n struct {\n uint8_t fclktrim : 5,\n : 3,\n ottrim : 2;\n };\n };\n};\n\nnamespace TMC2208_n {\n struct VACTUAL_t {\n constexpr static uint8_t address = 0x22;\n uint32_t sr;\n };\n}\n\nstruct MSCURACT_t {\n constexpr static uint8_t address = 0x6B;\n union {\n uint32_t sr : 25;\n struct {\n int16_t cur_a : 9,\n : 7,\n cur_b : 9;\n };\n };\n};\n\nnamespace TMC2208_n {\n struct CHOPCONF_t {\n constexpr static uint8_t address = 0x6C;\n union {\n uint32_t sr;\n struct {\n uint8_t toff : 4,\n hstrt : 3,\n hend : 4,\n : 4,\n tbl : 2;\n bool vsense : 1;\n uint8_t : 6,\n mres : 4;\n bool intpol : 1,\n dedge : 1,\n diss2g : 1,\n diss2vs : 1;\n };\n };\n };\n\n struct PWMCONF_t {\n constexpr static uint8_t address = 0x70;\n union {\n uint32_t sr;\n struct {\n uint8_t pwm_ofs : 8,\n pwm_grad : 8,\n pwm_freq : 2;\n bool pwm_autoscale : 1,\n pwm_autograd : 1;\n uint8_t freewheel : 2,\n : 2,\n pwm_reg : 4,\n pwm_lim : 4;\n };\n };\n };\n\n struct DRV_STATUS_t {\n constexpr static uint8_t address = 0x6F;\n union {\n uint32_t sr;\n struct {\n bool otpw : 1,\n ot : 1,\n s2ga : 1,\n s2gb : 1,\n s2vsa : 1,\n s2vsb : 1,\n ola : 1,\n olb : 1,\n t120 : 1,\n t143 : 1,\n t150 : 1,\n t157 : 1;\n uint8_t : 4,\n cs_actual : 5,\n : 3,\n : 6;\n bool stealth : 1,\n stst : 1;\n };\n };\n };\n\n struct PWM_SCALE_t {\n constexpr static uint8_t address = 0x71;\n union {\n uint32_t sr;\n struct {\n uint8_t pwm_scale_sum : 8,\n : 8;\n int16_t pwm_scale_auto : 9;\n };\n };\n };\n}\n\n#pragma pack(pop)" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/TMC2209Stepper.cpp", "content": "#include \"TMCStepper.h\"\n\nuint32_t TMC2209Stepper::IOIN() {\n return read(TMC2209_n::IOIN_t::address);\n}\nbool TMC2209Stepper::enn() { TMC2209_n::IOIN_t r{0}; r.sr = IOIN(); return r.enn; }\nbool TMC2209Stepper::ms1() { TMC2209_n::IOIN_t r{0}; r.sr = IOIN(); return r.ms1; }\nbool TMC2209Stepper::ms2() { TMC2209_n::IOIN_t r{0}; r.sr = IOIN(); return r.ms2; }\nbool TMC2209Stepper::diag() { TMC2209_n::IOIN_t r{0}; r.sr = IOIN(); return r.diag; }\nbool TMC2209Stepper::pdn_uart() { TMC2209_n::IOIN_t r{0}; r.sr = IOIN(); return r.pdn_uart; }\nbool TMC2209Stepper::step() { TMC2209_n::IOIN_t r{0}; r.sr = IOIN(); return r.step; }\nbool TMC2209Stepper::spread_en() { TMC2209_n::IOIN_t r{0}; r.sr = IOIN(); return r.spread_en;}\nbool TMC2209Stepper::dir() { TMC2209_n::IOIN_t r{0}; r.sr = IOIN(); return r.dir; }\nuint8_t TMC2209Stepper::version() { TMC2209_n::IOIN_t r{0}; r.sr = IOIN(); return r.version; }\n\nvoid TMC2209Stepper::push() {\n IHOLD_IRUN(IHOLD_IRUN_register.sr);\n TPOWERDOWN(TPOWERDOWN_register.sr);\n TPWMTHRS(TPWMTHRS_register.sr);\n GCONF(GCONF_register.sr);\n SLAVECONF(SLAVECONF_register.sr);\n VACTUAL(VACTUAL_register.sr);\n CHOPCONF(CHOPCONF_register.sr);\n PWMCONF(PWMCONF_register.sr);\n TCOOLTHRS(TCOOLTHRS_register.sr);\n}\n\nvoid TMC2209Stepper::SGTHRS(uint8_t input) {\n SGTHRS_register.sr = input;\n write(SGTHRS_register.address, SGTHRS_register.sr);\n}\nuint8_t TMC2209Stepper::SGTHRS() {\n return SGTHRS_register.sr;\n}\n\n// W: TCOOLTHRS\nuint32_t TMC2209Stepper::TCOOLTHRS() { return TCOOLTHRS_register.sr; }\nvoid TMC2209Stepper::TCOOLTHRS(uint32_t input) {\n TCOOLTHRS_register.sr = input;\n write(TCOOLTHRS_register.address, TCOOLTHRS_register.sr);\n}\n\nuint16_t TMC2209Stepper::SG_RESULT() {\n return read(TMC2209_n::SG_RESULT_t::address);\n}" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/TMC2209_bitfields.h", "content": "#pragma once\n#pragma pack(push, 1)\n\nnamespace TMC2209_n {\n struct IOIN_t {\n constexpr static uint8_t address = 0x06;\n union {\n uint32_t sr;\n struct {\n bool enn : 1,\n : 1,\n ms1 : 1,\n ms2 : 1,\n diag : 1,\n : 1,\n pdn_uart : 1,\n step : 1,\n spread_en : 1,\n dir : 1;\n uint16_t : 14;\n uint8_t version : 8;\n };\n };\n };\n\n struct SGTHRS_t {\n constexpr static uint8_t address = 0x40;\n uint8_t sr : 8;\n };\n\n struct SG_RESULT_t {\n constexpr static uint8_t address = 0x41;\n uint16_t sr : 10;\n };\n\n struct COOLCONF_t {\n constexpr static uint8_t address = 0x42;\n union {\n uint16_t sr;\n struct {\n uint8_t semin : 4,\n : 1,\n seup : 2,\n : 1,\n semax : 4,\n : 1,\n sedn : 2;\n bool seimin : 1;\n };\n };\n };\n\n} //namespace \n//////////////////////////////////////////////////////\nstruct SLAVECONF_t {\n constexpr static uint8_t address = 0x03;\n union {\n uint16_t sr : 12;\n struct {\n uint8_t slaveaddr : 8;\n uint8_t senddelay : 4;\n };\n };\n};\n\nstruct PWM_AUTO_t {\n constexpr static uint8_t address = 0x72;\n union {\n uint32_t sr : 24;\n struct {\n uint8_t pwm_ofs_auto : 8,\n : 8,\n pwm_grad_auto : 8;\n };\n };\n};\n\nstruct GCONF_t {\n constexpr static uint8_t address = 0x00;\n union {\n uint32_t sr : 18;\n struct {\n bool i_scale_analog : 1, // 2130, 5130\n internal_rsense : 1, // 2130, 5130\n en_pwm_mode : 1,\n enc_commutation : 1, // 2130, 5130\n shaft : 1,\n diag0_error : 1,\n diag0_otpw : 1,\n diag0_stall : 1,\n diag1_stall : 1,\n diag1_index : 1,\n diag1_onstate : 1,\n diag1_steps_skipped : 1,\n diag0_int_pushpull : 1,\n diag1_pushpull : 1,\n small_hysteresis : 1,\n stop_enable : 1,\n direct_mode : 1;\n };\n struct { // TMC5160\n bool recalibrate : 1,\n faststandstill : 1,\n : 1,\n multistep_filt : 1,\n : 3,\n diag0_step : 1,\n diag1_dir : 1,\n : 4,\n diag1_poscomp_pushpull : 1;\n };\n };\n};\n\nstruct IHOLD_IRUN_t {\n constexpr static uint8_t address = 0x10;\n union {\n uint32_t sr : 20;\n struct {\n uint8_t ihold : 5,\n : 3,\n irun : 5,\n : 3,\n iholddelay : 4;\n };\n };\n};\n\nstruct GSTAT_t {\n constexpr static uint8_t address = 0x01;\n union {\n uint8_t sr : 3;\n struct {\n bool reset : 1,\n drv_err : 1,\n uv_cp : 1;\n };\n };\n};\n\nstruct TPOWERDOWN_t {\n constexpr static uint8_t address = 0x11;\n uint8_t sr : 8;\n};\n\nstruct TPWMTHRS_t {\n constexpr static uint8_t address = 0x13;\n uint32_t sr : 20;\n};\n\nstruct TCOOLTHRS_t {\n constexpr static uint8_t address = 0x14;\n uint32_t sr : 20;\n};\n\nstruct THIGH_t {\n constexpr static uint8_t address = 0x15;\n uint32_t sr : 20;\n};\n\nstruct XDIRECT_t {\n constexpr static uint8_t address = 0x2D;\n union {\n uint32_t sr : 25;\n struct {\n int16_t coil_A : 9;\n int8_t : 7;\n int16_t coil_B : 9;\n };\n };\n};\n\nstruct VDCMIN_t {\n constexpr static uint8_t address = 0x33;\n uint32_t sr : 23;\n};\n\nstruct CHOPCONF_t {\n constexpr static uint8_t address = 0x6C;\n union {\n uint32_t sr : 32;\n struct {\n uint8_t toff : 4,\n hstrt : 3,\n hend : 4,\n : 1;\n bool disfdcc : 1,\n rndtf : 1,\n chm : 1;\n uint8_t tbl : 2;\n bool vsense : 1,\n vhighfs : 1,\n vhighchm : 1;\n uint8_t sync : 4, // 2130, 5130\n mres : 4;\n bool intpol : 1,\n dedge : 1,\n diss2g : 1;\n };\n struct { // TMC5160\n uint32_t : 20;\n uint8_t tpfd : 4; // 5160\n uint16_t : 7;\n bool diss2vs : 1; // TMC5160 only\n };\n };\n};\n\nstruct DCCTRL_t {\n constexpr static uint8_t address = 0x6E;\n union {\n uint32_t sr : 24;\n struct {\n uint16_t dc_time : 10,\n : 6;\n uint8_t dc_sg : 8;\n };\n };\n};\n\nstruct PWMCONF_t {\n constexpr static uint8_t address = 0x70;\n union {\n uint32_t sr : 22;\n struct {\n uint8_t pwm_ampl : 8,\n pwm_grad : 8,\n pwm_freq : 2;\n bool pwm_autoscale : 1,\n pwm_symmetric : 1;\n uint8_t freewheel : 2;\n };\n };\n};\n\nstruct ENCM_CTRL_t {\n constexpr static uint8_t address = 0x72;\n union {\n uint8_t sr : 2;\n struct {\n bool inv : 1,\n maxspeed : 1;\n };\n };\n}; \n \n#pragma pack(pop)" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/TMCStepper.cpp", "content": "#include \"TMCStepper.h\"\n\n\n/*\n Requested current = mA = I_rms/1000\n Equation for current:\n I_rms = (CS+1)/32 * V_fs/(R_sense+0.02ohm) * 1/sqrt(2)\n Solve for CS ->\n CS = 32*sqrt(2)*I_rms*(R_sense+0.02)/V_fs - 1\n\n Example:\n vsense = 0b0 -> V_fs = 0.325V\n mA = 1640mA = I_rms/1000 = 1.64A\n R_sense = 0.10 Ohm\n ->\n CS = 32*sqrt(2)*1.64*(0.10+0.02)/0.325 - 1 = 26.4\n CS = 26\n*/\n\nuint16_t TMCStepper::cs2rms(uint8_t CS) {\n return (float)(CS+1)/32.0 * (vsense() ? 0.180 : 0.325)/(Rsense+0.02) / 1.41421 * 1000;\n}\n\nvoid TMCStepper::rms_current(uint16_t mA) {\n uint8_t CS = 32.0*1.41421*mA/1000.0*(Rsense+0.02)/0.325 - 1;\n // If Current Scale is too low, turn on high sensitivity R_sense and calculate again\n if (CS < 16) {\n vsense(true);\n CS = 32.0*1.41421*mA/1000.0*(Rsense+0.02)/0.180 - 1;\n } else { // If CS >= 16, turn off high_sense_r\n vsense(false);\n }\n\n if (CS > 31)\n CS = 31;\n\n irun(CS);\n ihold(CS*holdMultiplier);\n //val_mA = mA;\n}\nvoid TMCStepper::rms_current(uint16_t mA, float mult) {\n holdMultiplier = mult;\n rms_current(mA);\n}\n\nuint16_t TMCStepper::rms_current() {\n return cs2rms(irun());\n}\n\nuint8_t TMCStepper::test_connection() {\n uint32_t drv_status = DRV_STATUS();\n switch (drv_status) {\n case 0xFFFFFFFF: return 1;\n case 0: return 2;\n default: return 0;\n }\n}\n\nvoid TMCStepper::hysteresis_end(int8_t value) { hend(value+3); }\nint8_t TMCStepper::hysteresis_end() { return hend()-3; };\n\nvoid TMCStepper::hysteresis_start(uint8_t value) { hstrt(value-1); }\nuint8_t TMCStepper::hysteresis_start() { return hstrt()+1; }\n\nvoid TMCStepper::microsteps(uint16_t ms) {\n switch(ms) {\n case 256: mres(0); break;\n case 128: mres(1); break;\n case 64: mres(2); break;\n case 32: mres(3); break;\n case 16: mres(4); break;\n case 8: mres(5); break;\n case 4: mres(6); break;\n case 2: mres(7); break;\n case 1: mres(8); break;\n default: break;\n }\n}\n\nuint16_t TMCStepper::microsteps() {\n switch(mres()) {\n case 0: return 256;\n case 1: return 128;\n case 2: return 64;\n case 3: return 32;\n case 4: return 16;\n case 5: return 8;\n case 6: return 4;\n case 7: return 2;\n case 8: return 1;\n }\n return 1;\n}\n\nvoid TMCStepper::blank_time(uint8_t value) {\n switch (value) {\n case 16: tbl(0b00); break;\n case 24: tbl(0b01); break;\n case 36: tbl(0b10); break;\n case 54: tbl(0b11); break;\n }\n}\n\nuint8_t TMCStepper::blank_time() {\n switch (tbl()) {\n case 0b00: return 16;\n case 0b01: return 24;\n case 0b10: return 36;\n case 0b11: return 54;\n }\n return 0;\n}\n\n///////////////////////////////////////////////////////////////////////////////////////\n// R+C: GSTAT\nuint8_t TMCStepper::GSTAT() { return read(GSTAT_t::address); }\nvoid TMCStepper::GSTAT(uint8_t){ write(GSTAT_t::address, 0b111); }\nbool TMCStepper::reset() { GSTAT_t r; r.sr = GSTAT(); return r.reset; }\nbool TMCStepper::drv_err() { GSTAT_t r; r.sr = GSTAT(); return r.drv_err; }\nbool TMCStepper::uv_cp() { GSTAT_t r; r.sr = GSTAT(); return r.uv_cp; }\n///////////////////////////////////////////////////////////////////////////////////////\n// W: TPOWERDOWN\nuint8_t TMCStepper::TPOWERDOWN() { return TPOWERDOWN_register.sr; }\nvoid TMCStepper::TPOWERDOWN(uint8_t input) {\n TPOWERDOWN_register.sr = input;\n write(TPOWERDOWN_register.address, TPOWERDOWN_register.sr);\n}\n///////////////////////////////////////////////////////////////////////////////////////\n// R: TSTEP\nuint32_t TMCStepper::TSTEP() { return read(TSTEP_t::address); }\n///////////////////////////////////////////////////////////////////////////////////////\n// W: TPWMTHRS\nuint32_t TMCStepper::TPWMTHRS() { return TPWMTHRS_register.sr; }\nvoid TMCStepper::TPWMTHRS(uint32_t input) {\n TPWMTHRS_register.sr = input;\n write(TPWMTHRS_register.address, TPWMTHRS_register.sr);\n}\n\nuint16_t TMCStepper::MSCNT() {\n return read(MSCNT_t::address);\n}\n\nuint32_t TMCStepper::MSCURACT() { return read(MSCURACT_t::address); }\nint16_t TMCStepper::cur_a() {\n MSCURACT_t r{0};\n r.sr = MSCURACT();\n int16_t value = r.cur_a;\n if (value > 255) value -= 512;\n return value;\n}\nint16_t TMCStepper::cur_b() {\n MSCURACT_t r{0};\n r.sr = MSCURACT();\n int16_t value = r.cur_b;\n if (value > 255) value -= 512;\n return value;\n}" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/TMCStepper.h", "content": "#include \"mbed.h\"\n#include \n#include \"../SoftwareSerial/SoftwareSerial.h\"\n#include \"../pin/pin.h\"\n\n//#include \"TMC2130_bitfields.h\"\n//#include \"TMC2160_bitfields.h\"\n//#include \"TMC5130_bitfields.h\"\n//#include \"TMC5160_bitfields.h\"\n#include \"TMC2208_bitfields.h\"\n#include \"TMC2209_bitfields.h\"\n//#include \"TMC2660_bitfields.h\"\n\n\n#define INIT_REGISTER(REG) REG##_t REG##_register = REG##_t\n#define INIT2208_REGISTER(REG) TMC2208_n::REG##_t REG##_register = TMC2208_n::REG##_t\n#define SET_ALIAS(TYPE, DRIVER, NEW, ARG, OLD) TYPE (DRIVER::*NEW)(ARG) = &DRIVER::OLD\n\n#define TMCSTEPPER_VERSION 0x000701 // v0.7.1\n\nclass TMCStepper {\n public:\n uint16_t cs2rms(uint8_t CS);\n void rms_current(uint16_t mA);\n void rms_current(uint16_t mA, float mult);\n uint16_t rms_current();\n void hold_multiplier(float val) { holdMultiplier = val; }\n float hold_multiplier() { return holdMultiplier; }\n uint8_t test_connection();\n\n // Helper functions\n void microsteps(uint16_t ms);\n uint16_t microsteps();\n void blank_time(uint8_t value);\n uint8_t blank_time();\n void hysteresis_end(int8_t value);\n int8_t hysteresis_end();\n void hysteresis_start(uint8_t value);\n uint8_t hysteresis_start();\n\n // R+WC: GSTAT\n void GSTAT( uint8_t input);\n uint8_t GSTAT();\n bool reset();\n bool drv_err();\n bool uv_cp();\n\n // W: IHOLD_IRUN\n void IHOLD_IRUN( uint32_t input);\n uint32_t IHOLD_IRUN();\n void ihold( uint8_t B);\n void irun( uint8_t B);\n void iholddelay( uint8_t B);\n uint8_t ihold();\n uint8_t irun();\n uint8_t iholddelay();\n\n // W: TPOWERDOWN\n uint8_t TPOWERDOWN();\n void TPOWERDOWN( uint8_t input);\n\n // R: TSTEP\n uint32_t TSTEP();\n\n // W: TPWMTHRS\n uint32_t TPWMTHRS();\n void TPWMTHRS( uint32_t input);\n\n // R: MSCNT\n uint16_t MSCNT();\n\n // R: MSCURACT\n uint32_t MSCURACT();\n int16_t cur_a();\n int16_t cur_b();\n\n\t\tTimer tmcTimer;\n\n protected:\n TMCStepper(float RS) : Rsense(RS) {};\n INIT_REGISTER(IHOLD_IRUN){{.sr=0}}; // 32b\n INIT_REGISTER(TPOWERDOWN){.sr=0}; // 8b\n INIT_REGISTER(TPWMTHRS){.sr=0}; // 32b\n\n static constexpr uint8_t TMC_READ = 0x00,\n TMC_WRITE = 0x80;\n\n struct TSTEP_t { constexpr static uint8_t address = 0x12; };\n struct MSCNT_t { constexpr static uint8_t address = 0x6A; };\n\n virtual void write(uint8_t, uint32_t) = 0;\n virtual uint32_t read(uint8_t) = 0;\n virtual void vsense(bool) = 0;\n virtual bool vsense(void) = 0;\n virtual uint32_t DRV_STATUS() = 0;\n virtual void hend(uint8_t) = 0;\n virtual uint8_t hend() = 0;\n virtual void hstrt(uint8_t) = 0;\n virtual uint8_t hstrt() = 0;\n virtual void mres(uint8_t) = 0;\n virtual uint8_t mres() = 0;\n virtual void tbl(uint8_t) = 0;\n virtual uint8_t tbl() = 0;\n\n const float Rsense;\n float holdMultiplier = 0.5;\n};\n\n\nclass TMC2208Stepper : public TMCStepper {\n public:\n\n TMC2208Stepper(std::string SWRXpin, std::string SWTXpin, float RS) :\n TMC2208Stepper(SWRXpin, SWTXpin, RS, TMC2208_SLAVE_ADDR)\n {}\n\n SoftwareSerial * SWSerial = nullptr;\n\n void defaults();\n void push();\n void begin();\n void beginSerial(uint32_t baudrate) __attribute__((weak));\n\n bool isEnabled();\n\n // RW: GCONF\n void GCONF(uint32_t input);\n void I_scale_analog(bool B);\n void internal_Rsense(bool B);\n void en_spreadCycle(bool B);\n void shaft(bool B);\n void index_otpw(bool B);\n void index_step(bool B);\n void pdn_disable(bool B);\n void mstep_reg_select(bool B);\n void multistep_filt(bool B);\n uint32_t GCONF();\n bool I_scale_analog();\n bool internal_Rsense();\n bool en_spreadCycle();\n bool shaft();\n bool index_otpw();\n bool index_step();\n bool pdn_disable();\n bool mstep_reg_select();\n bool multistep_filt();\n\n // R: IFCNT\n uint8_t IFCNT();\n\n // W: SLAVECONF\n void SLAVECONF(uint16_t input);\n uint16_t SLAVECONF();\n void senddelay(uint8_t B);\n uint8_t senddelay();\n\n // W: OTP_PROG\n void OTP_PROG(uint16_t input);\n\n // R: OTP_READ\n uint32_t OTP_READ();\n\n // R: IOIN\n uint32_t IOIN();\n bool enn();\n bool ms1();\n bool ms2();\n bool diag();\n bool pdn_uart();\n bool step();\n bool sel_a();\n bool dir();\n uint8_t version();\n\n // RW: FACTORY_CONF\n void FACTORY_CONF(uint16_t input);\n uint16_t FACTORY_CONF();\n void fclktrim(uint8_t B);\n void ottrim(uint8_t B);\n uint8_t fclktrim();\n uint8_t ottrim();\n\n // W: VACTUAL\n void VACTUAL(uint32_t input);\n uint32_t VACTUAL();\n\n // RW: CHOPCONF\n void CHOPCONF(uint32_t input);\n void toff(uint8_t B);\n void hstrt(uint8_t B);\n void hend(uint8_t B);\n void tbl(uint8_t B);\n void vsense(bool B);\n void mres(uint8_t B);\n void intpol(bool B);\n void dedge(bool B);\n void diss2g(bool B);\n void diss2vs(bool B);\n uint32_t CHOPCONF();\n uint8_t toff();\n uint8_t hstrt();\n uint8_t hend();\n uint8_t tbl();\n bool vsense();\n uint8_t mres();\n bool intpol();\n bool dedge();\n bool diss2g();\n bool diss2vs();\n\n // R: DRV_STATUS\n uint32_t DRV_STATUS();\n bool otpw();\n bool ot();\n bool s2ga();\n bool s2gb();\n bool s2vsa();\n bool s2vsb();\n bool ola();\n bool olb();\n bool t120();\n bool t143();\n bool t150();\n bool t157();\n uint16_t cs_actual();\n bool stealth();\n bool stst();\n\n // RW: PWMCONF\n void PWMCONF(uint32_t input);\n void pwm_ofs(uint8_t B);\n void pwm_grad(uint8_t B);\n void pwm_freq(uint8_t B);\n void pwm_autoscale(bool B);\n void pwm_autograd(bool B);\n void freewheel(uint8_t B);\n void pwm_reg(uint8_t B);\n void pwm_lim(uint8_t B);\n uint32_t PWMCONF();\n uint8_t pwm_ofs();\n uint8_t pwm_grad();\n uint8_t pwm_freq();\n bool pwm_autoscale();\n bool pwm_autograd();\n uint8_t freewheel();\n uint8_t pwm_reg();\n uint8_t pwm_lim();\n\n // R: PWM_SCALE\n uint32_t PWM_SCALE();\n uint8_t pwm_scale_sum();\n int16_t pwm_scale_auto();\n\n // R: PWM_AUTO (0x72)\n uint32_t PWM_AUTO();\n uint8_t pwm_ofs_auto();\n uint8_t pwm_grad_auto();\n\n uint16_t bytesWritten = 0;\n float Rsense = 0.11;\n bool CRCerror = false;\n protected:\n INIT2208_REGISTER(GCONF) {{.sr=0}};\n INIT_REGISTER(SLAVECONF) {{.sr=0}};\n INIT_REGISTER(FACTORY_CONF) {{.sr=0}};\n INIT2208_REGISTER(VACTUAL) {.sr=0};\n INIT2208_REGISTER(CHOPCONF) {{.sr=0}};\n INIT2208_REGISTER(PWMCONF) {{.sr=0}};\n\n struct IFCNT_t { constexpr static uint8_t address = 0x02; };\n struct OTP_PROG_t { constexpr static uint8_t address = 0x04; };\n struct OTP_READ_t { constexpr static uint8_t address = 0x05; };\n\n //SoftwareSerial * SWSerial = nullptr;\n\n TMC2208Stepper(std::string SWRXpin, std::string SWTXpin, float RS, uint8_t addr);\n\n std::string SWTXpin;\n std::string SWRXpin;\n\n DigitalOut* debug1;\n DigitalOut* debug2;\n\n int available();\n void preWriteCommunication();\n void preReadCommunication();\n int16_t serial_read();\n uint8_t serial_write(const uint8_t data);\n void postWriteCommunication();\n void postReadCommunication();\n void write(uint8_t, uint32_t);\n uint32_t read(uint8_t);\n const uint8_t slave_address;\n uint8_t calcCRC(uint8_t datagram[], uint8_t len);\n static constexpr uint8_t TMC2208_SYNC = 0x05,\n TMC2208_SLAVE_ADDR = 0x00;\n static constexpr uint8_t replyDelay = 2; //ms\n static constexpr uint8_t abort_window = 5;\n static constexpr uint8_t max_retries = 2;\n\n uint64_t _sendDatagram(uint8_t [], const uint8_t, uint16_t);\n};\n\nclass TMC2209Stepper : public TMC2208Stepper {\n public:\n\n TMC2209Stepper(std::string SWRXpin, std::string SWTXpin, float RS, uint8_t addr) :\n TMC2208Stepper(SWRXpin, SWTXpin, RS, addr) {}\n\n void push();\n\n // R: IOIN\n uint32_t IOIN();\n bool enn();\n bool ms1();\n bool ms2();\n bool diag();\n bool pdn_uart();\n bool step();\n bool spread_en();\n bool dir();\n uint8_t version();\n\n // W: TCOOLTHRS\n uint32_t TCOOLTHRS();\n void TCOOLTHRS(uint32_t input);\n\n // W: SGTHRS\n void SGTHRS(uint8_t B);\n uint8_t SGTHRS();\n\n // R: SG_RESULT\n uint16_t SG_RESULT();\n\n // W: COOLCONF\n void COOLCONF(uint16_t B);\n uint16_t COOLCONF();\n void semin(uint8_t B);\n void seup(uint8_t B);\n void semax(uint8_t B);\n void sedn(uint8_t B);\n void seimin(bool B);\n uint8_t semin();\n uint8_t seup();\n uint8_t semax();\n uint8_t sedn();\n bool seimin();\n\n protected:\n INIT_REGISTER(TCOOLTHRS){.sr=0};\n TMC2209_n::SGTHRS_t SGTHRS_register{.sr=0};\n TMC2209_n::COOLCONF_t COOLCONF_register{{.sr=0}};\n};\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/TMCStepper/TMC_MACROS.h", "content": "#pragma once\n\n#define DEBUG_PRINT(CFG, VAL) Serial.print(CFG); Serial.print('('); Serial.print(VAL, HEX); Serial.println(')')\n//#define WRITE_REG(R) write(R##_register.address, R##_register.sr)\n//#define READ_REG(R) read(R##_register.address)" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/.hg/branch", "content": "default\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/.hg/cache/branch2-base", "content": "d4c8fe4d9b29d4e5614620b0820a49d31087b512 0\nd4c8fe4d9b29d4e5614620b0820a49d31087b512 o default\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/.hg/cache/rbc-names-v1", "content": "default" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/.hg/cache/tags2-visible", "content": "0 d4c8fe4d9b29d4e5614620b0820a49d31087b512\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/.hg/hgrc", "content": "# example repository config (see 'hg help config' for more info)\n[paths]\nmbed-studio-cache = c:\\Users\\tanya\\AppData\\Local\\Mbed Studio\\library-cache\\os.mbed.com\\teams\\WIZnet\\code\\WIZnetInterface-OS5\ndefault = http://os.mbed.com/teams/WIZnet/code/WIZnetInterface-OS5/\n\n# path aliases to other clones of this repo in URLs or filesystem paths\n# (see 'hg help config.paths' for more info)\n#\n# default:pushurl = ssh://jdoe@example.net/hg/jdoes-fork\n# my-fork = ssh://jdoe@example.net/hg/jdoes-fork\n# my-clone = /home/jdoe/jdoes-clone\n\n[ui]\n# name and email (local to this repository, optional), e.g.\n# username = Jane Doe \n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/.hg/requires", "content": "dotencode\nfncache\ngeneraldelta\nrevlogv1\nsparserevlog\nstore\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/.hg/store/fncache", "content": "data/Socket/DNSClient.h.i\ndata/arch/int/W7500x_toe.cpp.i\ndata/Socket/TCPSocketServer.h.i\ndata/Socket/TCPSocketConnection.cpp.i\ndata/arch/ext/W5500.cpp.i\ndata/arch/ext/W5500.h.i\ndata/Socket/DHCPClient.h.i\ndata/Socket/TCPSocketServer.cpp.i\ndata/Socket/WIZnet_UDPSocket.cpp.i\ndata/Socket/TCPSocketConnection.h.i\ndata/WIZnetInterface.h.i\ndata/arch/int/W7500x_toe.h.i\ndata/Socket/WIZnet_Socket.h.i\ndata/Socket/WIZnet_Socket.cpp.i\ndata/Socket/Endpoint.h.i\ndata/Socket/DNSClient.cpp.i\ndata/WIZnetInterface.cpp.i\ndata/Socket/Endpoint.cpp.i\ndata/eth_arch.h.i\ndata/Socket/DHCPClient.cpp.i\ndata/Socket/WIZnet_UDPSocket.h.i\ndata/Socket/dnsname.h.i\ndata/Socket/pico_string.h.i\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/Socket/DHCPClient.cpp", "content": "// DHCPClient.cpp 2013/4/10\n#include \"mbed.h\"\n#include \"mbed_debug.h\"\n#include \"WIZnet_UDPSocket.h\"\n#include \"DHCPClient.h\"\n\n#define DBG_DHCP 0\n\n#if DBG_DHCP\n#define DBG(...) do{debug(\"[%s:%d]\", __PRETTY_FUNCTION__,__LINE__);debug(__VA_ARGS__);} while(0);\n#define DBG_HEX(A,B) do{debug(\"[%s:%d]\\r\\n\", __PRETTY_FUNCTION__,__LINE__);debug_hex(A,B);} while(0);\n#else\n#define DBG(...) while(0);\n#define DBG_HEX(A,B) while(0);\n#endif\n\nint DHCPClient::discover()\n{\n m_pos = 0;\n const uint8_t header[] = {0x01,0x01,0x06,0x00};\n add_buf((uint8_t*)header, sizeof(header));\n uint32_t x = time(NULL) + rand();\n xid[0] = x>>24; xid[1] = x>>16; xid[2] = x>>8; xid[3] = x;\n add_buf(xid, 4);\n fill_buf(20, 0x00);\n add_buf(chaddr, 6);\n fill_buf(10+192, 0x00);\n const uint8_t options[] = {0x63,0x82,0x53,0x63, // magic cookie\n 53,1,DHCPDISCOVER, // DHCP option 53: DHCP Discover\n 55,4,1,3,15,6,\n 255}; \n add_buf((uint8_t*)options, sizeof(options));\n return m_pos;\n}\n\nint DHCPClient::request()\n{\n m_pos = 0;\n const uint8_t header[] = {0x01,0x01,0x06,0x00};\n add_buf((uint8_t*)header, sizeof(header));\n add_buf(xid, 4);\n fill_buf(12, 0x00);\n add_buf(siaddr, 4);\n fill_buf(4, 0x00); // giaddr\n add_buf(chaddr, 6);\n fill_buf(10+192, 0x00);\n const uint8_t options[] = {0x63,0x82,0x53,0x63, // magic cookie\n 53,1,DHCPREQUEST, // DHCP option 53: DHCP Request\n 55,4,1,3,15,6, // DHCP option 55:\n };\n add_buf((uint8_t*)options, sizeof(options));\n add_option(50, yiaddr, 4);\n add_option(54, siaddr, 4);\n add_option(255);\n return m_pos;\n}\n\nint DHCPClient::offer(uint8_t buf[], int size) {\n memcpy(yiaddr, buf+DHCP_OFFSET_YIADDR, 4); \n memcpy(siaddr, buf+DHCP_OFFSET_SIADDR, 4); \n uint8_t *p;\n int msg_type = -1;\n p = buf + DHCP_OFFSET_OPTIONS;\n while(*p != 255 && p < (buf+size)) {\n uint8_t code = *p++;\n if (code == 0) { // Pad Option\n continue;\n }\n int len = *p++;\n \n DBG(\"DHCP option: %d\\r\\n\", code);\n DBG_HEX(p, len);\n\n switch(code) {\n case 53:\n msg_type = *p;\n break;\n case 1:\n memcpy(netmask, p, 4); // Subnet mask address\n break;\n case 3:\n memcpy(gateway, p, 4); // Gateway IP address\n break; \n case 6: // DNS server\n memcpy(dnsaddr, p, 4);\n break;\n case 51: // IP lease time \n break;\n case 54: // DHCP server\n memcpy(siaddr, p, 4);\n break;\n }\n p += len;\n }\n return msg_type;\n}\n\nbool DHCPClient::verify(uint8_t buf[], int len) {\n if (len < DHCP_OFFSET_OPTIONS) {\n return false;\n }\n if (buf[DHCP_OFFSET_OP] != 0x02) {\n return false;\n }\n if (memcmp(buf+DHCP_OFFSET_XID, xid, 4) != 0) {\n return false;\n }\n return true;\n}\n\nvoid DHCPClient::callback()\n{\n Endpoint host;\n int recv_len = m_udp->receiveFrom(host, (char*)m_buf, sizeof(m_buf));\n if (recv_len < 0) {\n return;\n }\n if (!verify(m_buf, recv_len)) {\n return;\n }\n int r = offer(m_buf, recv_len);\n if (r == DHCPOFFER) {\n int send_size = request();\n m_udp->sendTo(m_server, (char*)m_buf, send_size);\n } else if (r == DHCPACK) {\n exit_flag = true;\n }\n}\n\nvoid DHCPClient::add_buf(uint8_t c)\n{\n m_buf[m_pos++] = c;\n}\n\nvoid DHCPClient::add_buf(uint8_t* buf, int len)\n{\n for(int i = 0; i < len; i++) {\n add_buf(buf[i]);\n }\n}\n\nvoid DHCPClient::fill_buf(int len, uint8_t data)\n{\n while(len-- > 0) {\n add_buf(data);\n }\n}\n\nvoid DHCPClient::add_option(uint8_t code, uint8_t* buf, int len)\n{\n add_buf(code);\n if (len > 0) {\n add_buf((uint8_t)len);\n add_buf(buf, len);\n }\n}\n\nint DHCPClient::setup(int timeout_ms)\n{\n eth = WIZnet_Chip::getInstance();\n if (eth == NULL) {\n return -1;\n } \n eth->reg_rd_mac(SHAR, chaddr);\n int interval_ms = 5*1000; // 5000msec\n if (timeout_ms < interval_ms) {\n interval_ms = timeout_ms;\n }\n m_udp = new WIZnet_UDPSocket;\n m_udp->init();\n m_udp->set_blocking(false);\n eth->reg_wr(SIPR, 0x00000000); // local ip \"0.0.0.0\"\n m_udp->bind(68); // local port\n m_server.set_address(\"255.255.255.255\", 67); // DHCP broadcast\n exit_flag = false;\n int err = 0;\n int seq = 0;\n int send_size;\n while(!exit_flag) {\n switch(seq) {\n case 0:\n m_retry = 0;\n seq++;\n break;\n case 1:\n send_size = discover();\n m_udp->sendTo(m_server, (char*)m_buf, send_size);\n m_interval.reset();\n m_interval.start();\n seq++;\n break;\n case 2:\n callback();\n if (m_interval.read_ms() > interval_ms) {\n DBG(\"m_retry: %d\\n\", m_retry);\n if (++m_retry >= (timeout_ms/interval_ms)) {\n err = -1;\n exit_flag = true;\n }\n seq--;\n }\n break;\n }\n }\n DBG(\"m_retry: %d, m_interval: %d\\n\", m_retry, m_interval.read_ms());\n delete m_udp;\n return err;\n}\n\nDHCPClient::DHCPClient() {\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/Socket/DHCPClient.h", "content": "// DHCPClient.h 2013/4/10\n#ifndef DHCPCLIENT_H\n#define DHCPCLIENT_H\n#include \"eth_arch.h\"\n#include \"WIZnet_UDPSocket.h\"\n\n#define DHCP_OFFSET_OP 0\n#define DHCP_OFFSET_XID 4\n#define DHCP_OFFSET_YIADDR 16\n#define DHCP_OFFSET_SIADDR 20\n#define DHCP_OFFSET_OPTIONS 240\n#define DHCP_MAX_PACKET_SIZE 600\n\n// DHCP Message Type\n#define DHCPDISCOVER 1\n#define DHCPOFFER 2\n#define DHCPREQUEST 3\n#define DHCPDECLINE 4\n#define DHCPACK 5\n#define DHCPNAK 6\n#define DHCPRELEASE 7\n#define DHCPINFORM 8\n\nclass DHCPClient {\npublic:\n DHCPClient();\n int setup(int timeout_ms = 15*1000);\n uint8_t chaddr[6]; // MAC\n uint8_t yiaddr[4]; // IP\n uint8_t dnsaddr[4]; // DNS\n uint8_t gateway[4];\n uint8_t netmask[4];\n uint8_t siaddr[4];\nprivate:\n int discover();\n int request();\n int offer(uint8_t buf[], int size);\n void add_buf(uint8_t* buf, int len);\n void fill_buf(int len, uint8_t data = 0x00);\n void add_buf(uint8_t c);\n void add_option(uint8_t code, uint8_t* buf = NULL, int len = 0);\n bool verify(uint8_t buf[], int len);\n void callback();\n WIZnet_UDPSocket* m_udp;\n Endpoint m_server;\n uint8_t xid[4];\n bool exit_flag;\n Timer m_interval;\n int m_retry;\n uint8_t m_buf[DHCP_MAX_PACKET_SIZE];\n int m_pos;\n WIZnet_Chip* eth;\n};\n#endif //DHCPCLIENT_H\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/Socket/DNSClient.cpp", "content": "// DNSClient.cpp 2013/8/27\n#include \"mbed.h\"\n#include \"mbed_debug.h\"\n#include \"DNSClient.h\"\n#include \"WIZnet_UDPSocket.h\"\n#include \"dnsname.h\"\n#include \"eth_arch.h\"\n\n#define DBG_DNS 0\n\n#if DBG_DNS\n#define DBG2(...) do{debug(\"[DNS]%p %d %s \", this,__LINE__,__PRETTY_FUNCTION__); debug(__VA_ARGS__); } while(0);\n#else\n#define DBG2(...) while(0);\n#endif\n\nDNSClient::DNSClient(const char* hostname) : m_state(MYNETDNS_START), m_udp(NULL) {\n m_hostname = hostname;\n}\n\nDNSClient::DNSClient(Endpoint* pHost) : m_state(MYNETDNS_START), m_udp(NULL) {\n}\n\nDNSClient::~DNSClient() {\n if (m_udp) {\n delete m_udp;\n }\n}\n\nvoid DNSClient::callback()\n{\n uint8_t buf[512];\n Endpoint host;\n int len = m_udp->receiveFrom(host, (char*)buf, sizeof(buf));\n if (len < 0) {\n return;\n }\n if (memcmp(buf+0, m_id, 2) != 0) { //verify\n return;\n }\n int rcode = response(buf, len);\n if (rcode == 0) {\n m_state = MYNETDNS_OK;\n } else {\n m_state = MYNETDNS_NOTFOUND;\n }\n}\n\nint DNSClient::response(uint8_t buf[], int size) {\n int rcode = buf[3] & 0x0f;\n if (rcode != 0) {\n return rcode;\n }\n int qdcount = buf[4]<<8|buf[5];\n int ancount = buf[6]<<8|buf[7];\n int pos = 12;\n while(qdcount-- > 0) {\n dnsname qname(buf);\n pos = qname.decode(pos); // qname\n pos += 4; // qtype qclass\n }\n while(ancount-- > 0) {\n dnsname name(buf);\n pos = name.decode(pos); // name\n int type = buf[pos]<<8|buf[pos+1];\n pos += 8; // type class TTL \n int rdlength = buf[pos]<<8|buf[pos+1]; pos += 2;\n int rdata_pos = pos;\n pos += rdlength;\n if (type == 1) { // A record\n ip = (buf[rdata_pos]<<24) | (buf[rdata_pos+1]<<16) | (buf[rdata_pos+2]<<8) | buf[rdata_pos+3];\n }\n#if DBG_DNS\n printf(\"%s\", name.str.c_str());\n if (type == 1) {\n printf(\" A %d.%d.%d.%d\\n\", \n buf[rdata_pos],buf[rdata_pos+1],buf[rdata_pos+2],buf[rdata_pos+3]);\n } else if (type == 5) {\n dnsname rdname(buf);\n rdname.decode(rdata_pos);\n printf(\" CNAME %s\\n\", rdname.str.c_str());\n } else {\n printf(\" TYPE:%d\", type);\n printfBytes(\" RDATA:\", &buf[rdata_pos], rdlength);\n }\n#endif\n }\n return rcode;\n}\n\nint DNSClient::query(uint8_t buf[], int size, const char* hostname) {\n const uint8_t header[] = {\n 0x00,0x00,0x01,0x00, // id=0x0000 QR=0 rd=1 opcode=0 rcode=0\n 0x00,0x01,0x00,0x00, // qdcount=1 ancount=0\n 0x00,0x00,0x00,0x00};// nscount=0 arcount=0 \n const uint8_t tail[] = {0x00,0x01,0x00,0x01}; // qtype=A qclass=IN\n memcpy(buf, header, sizeof(header));\n int t = rand();\n m_id[0] = t>>8;\n m_id[1] = t;\n memcpy(buf, m_id, 2); \n dnsname qname(buf);\n int pos = qname.encode(sizeof(header), (char*)hostname);\n memcpy(buf+pos, tail, sizeof(tail));\n pos += sizeof(tail);\n return pos;\n}\n\nvoid DNSClient::resolve(const char* hostname) {\n if (m_udp == NULL) {\n m_udp = new WIZnet_UDPSocket;\n }\n m_udp->init();\n m_udp->set_blocking(false);\n Endpoint server;\n server.set_address(\"8.8.8.8\", 53); // DNS\n m_udp->bind(rand()&0x7fff);\n uint8_t buf[256]; \n int size = query(buf, sizeof(buf), hostname);\n#if DBG_DNS\n printf(\"hostname:[%s]\\n\", hostname);\n printHex(buf, size);\n#endif\n m_udp->sendTo(server, (char*)buf, size);\n m_interval.reset();\n m_interval.start();\n}\n\nvoid DNSClient::poll() {\n#if DBG_DNS\n printf(\"%p m_state: %d, m_udp: %p\\n\", this, m_state, m_udp);\n wait_ms(400);\n#endif\n switch(m_state) {\n case MYNETDNS_START:\n m_retry = 0;\n resolve(m_hostname);\n m_state = MYNETDNS_PROCESSING;\n break;\n case MYNETDNS_PROCESSING: \n break;\n case MYNETDNS_NOTFOUND: \n break;\n case MYNETDNS_ERROR: \n break;\n case MYNETDNS_OK:\n DBG2(\"m_retry=%d, m_interval=%d\\n\", m_retry, m_interval.read_ms());\n break;\n }\n if (m_interval.read_ms() > 1000) {\n m_interval.stop();\n DBG2(\"timeout m_retry=%d\\n\", m_retry);\n if (++m_retry >= 2) {\n m_state = MYNETDNS_ERROR;\n } else {\n resolve(m_hostname);\n m_state = MYNETDNS_PROCESSING;\n }\n }\n}\n\nbool DNSClient::lookup(const char* hostname) {\n m_hostname = hostname;\n m_state = MYNETDNS_START;\n while(1) {\n poll();\n callback();\n if (m_state != MYNETDNS_PROCESSING) {\n break;\n } \n }\n return m_state == MYNETDNS_OK;\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/Socket/DNSClient.h", "content": "// DNSClient.h 2013/4/5\n#pragma once\n\n#include \"WIZnet_UDPSocket.h\"\n \nclass DNSClient {\npublic:\n DNSClient(const char* hostname = NULL);\n DNSClient(Endpoint* pHost);\n virtual ~DNSClient();\n bool lookup(const char* hostname = NULL);\n uint32_t ip;\nprotected:\n void poll();\n void callback();\n int response(uint8_t buf[], int size);\n int query(uint8_t buf[], int size, const char* hostname);\n void resolve(const char* hostname);\n uint8_t m_id[2];\n Timer m_interval;\n int m_retry;\n const char* m_hostname;\nprivate:\n enum MyNetDnsState\n {\n MYNETDNS_START,\n MYNETDNS_PROCESSING, //Req has not completed\n MYNETDNS_NOTFOUND,\n MYNETDNS_ERROR,\n MYNETDNS_OK\n };\n MyNetDnsState m_state;\n WIZnet_UDPSocket *m_udp;\n};\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/Socket/Endpoint.cpp", "content": "/* Copyright (C) 2012 mbed.org, MIT License\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of this software\n * and associated documentation files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge, publish, distribute,\n * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all copies or\n * substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING\n * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,\n * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n */\n#include \"WIZnet_Socket.h\"\n#include \"Endpoint.h\"\n\nEndpoint::Endpoint()\n{\n //printf(\"reset_address\\r\\n\");\n reset_address();\n}\nEndpoint::~Endpoint() {}\n\nvoid Endpoint::reset_address(void)\n{\n _ipAddress[0] = '\\0';\n _port = 0;\n}\n\nint Endpoint::set_address(const char* host, const int port)\n{\n //Resolve DNS address or populate hard-coded IP address\n WIZnet_Chip* eth = WIZnet_Chip::getInstance();\n if (eth == NULL) {\n error(\"Endpoint constructor error: no WIZnet chip instance available!\\r\\n\");\n return -1;\n }\n uint32_t addr;\n if (!eth->gethostbyname(host, &addr)) {\n error(\"DNS error : Cannot get url from DNS server\\r\\n\");\n return -1;\n }\n snprintf(_ipAddress, sizeof(_ipAddress), \"%d.%d.%d.%d\", (addr>>24)&0xff, (addr>>16)&0xff, (addr>>8)&0xff, addr&0xff);\n _port = port;\n return 0;\n}\n\nchar* Endpoint::get_address()\n{\n return _ipAddress;\n}\n\nint Endpoint::get_port()\n{\n return _port;\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/Socket/Endpoint.h", "content": "/* Copyright (C) 2012 mbed.org, MIT License\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of this software\n * and associated documentation files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge, publish, distribute,\n * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all copies or\n * substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING\n * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,\n * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n */\n#ifndef ENDPOINT_H\n#define ENDPOINT_H\n\n#include \"eth_arch.h\"\n\nclass WIZnet_UDPSocket;\n\n/**\nIP Endpoint (address, port)\n*/\nclass Endpoint {\n friend class WIZnet_UDPSocket;\n\npublic:\n /** IP Endpoint (address, port)\n */\n Endpoint(void);\n \n ~Endpoint(void);\n \n /** Reset the address of this endpoint\n */\n void reset_address(void);\n \n /** Set the address of this endpoint\n \\param host The endpoint address (it can either be an IP Address or a hostname that will be resolved with DNS).\n \\param port The endpoint port\n \\return 0 on success, -1 on failure (when an hostname cannot be resolved by DNS).\n */\n int set_address(const char* host, const int port);\n \n /** Get the IP address of this endpoint\n \\return The IP address of this endpoint.\n */\n char* get_address(void);\n \n /** Get the port of this endpoint\n \\return The port of this endpoint\n */\n int get_port(void);\n\nprotected:\n char _ipAddress[16];\n int _port;\n};\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/Socket/TCPSocketConnection.cpp", "content": "/* Copyright (C) 2012 mbed.org, MIT License\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of this software\n * and associated documentation files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge, publish, distribute,\n * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all copies or\n * substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING\n * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,\n * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n */\n\n#include \"TCPSocketConnection.h\"\n#include \n\nusing std::memset;\nusing std::memcpy;\n\n// not a big code.\n// refer from EthernetInterface by mbed official driver\nTCPSocketConnection::TCPSocketConnection() :\n _is_connected(false)\n{\n}\n\nint TCPSocketConnection::connect(const char* host, const int port)\n{\n if (_sock_fd < 0) {\n _sock_fd = eth->new_socket();\n if (_sock_fd < 0) {\n return -1;\n }\n }\n if (set_address(host, port) != 0) {\n return -1;\n }\n if (!eth->connect(_sock_fd, get_address(), port)) {\n return -1;\n }\n set_blocking(false);\n // add code refer from EthernetInterface.\n _is_connected = true;\n\n return 0;\n}\n\nbool TCPSocketConnection::is_connected(void)\n{\n // force update recent state.\n _is_connected = eth->is_connected(_sock_fd);\n return _is_connected;\n}\n\nint TCPSocketConnection::send(char* data, int length)\n{\n if((_sock_fd<0) || !(eth->is_connected(_sock_fd)))\n return -1;\n\n int size = eth->wait_writeable(_sock_fd, _blocking ? -1 : _timeout);\n if (size < 0) \n return -1;\n\n if (size > length) \n size = length;\n\n return eth->send(_sock_fd, data, size);\n}\n\n// -1 if unsuccessful, else number of bytes written\nint TCPSocketConnection::send_all(char* data, int length)\n{\n int writtenLen = 0;\n\n if(_sock_fd<0)\n return -1;\n\n while (writtenLen < length) {\n\n if(!(eth->is_connected(_sock_fd)))\n return -1;\n\n int size = eth->wait_writeable(_sock_fd, _blocking ? -1 : _timeout);\n if (size < 0) {\n return -1;\n }\n if (size > (length-writtenLen)) {\n size = (length-writtenLen);\n }\n int ret = eth->send(_sock_fd, data + writtenLen, size);\n if (ret < 0) {\n return -1;\n }\n writtenLen += ret;\n }\n return writtenLen;\n}\n\n// -1 if unsuccessful, else number of bytes received\nint TCPSocketConnection::receive(char* data, int length)\n{\n if((_sock_fd<0) || !(eth->is_connected(_sock_fd)))\n return -1;\n\n int size = eth->wait_readable(_sock_fd, _blocking ? -1 : _timeout);\n if (size < 0) {\n return -1;\n }\n if (size > length) {\n size = length;\n }\n return eth->recv(_sock_fd, data, size);\n}\n\n// -1 if unsuccessful, else number of bytes received\nint TCPSocketConnection::receive_all(char* data, int length)\n{\n if(_sock_fd<0)\n return -1;\n\n int readLen = 0;\n while (readLen < length) {\n\n if(!(eth->is_connected(_sock_fd)))\n return -1;\n\n int size = eth->wait_readable(_sock_fd, _blocking ? -1 :_timeout);\n if (size <= 0) {\n break;\n }\n if (size > (length - readLen)) {\n size = length - readLen;\n }\n int ret = eth->recv(_sock_fd, data + readLen, size);\n if (ret < 0) {\n return -1;\n }\n readLen += ret;\n }\n return readLen;\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/Socket/TCPSocketConnection.h", "content": "/* Copyright (C) 2012 mbed.org, MIT License\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of this software\n * and associated documentation files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge, publish, distribute,\n * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all copies or\n * substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING\n * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,\n * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n */\n\n#ifndef TCPSOCKETCONNECTION_H\n#define TCPSOCKETCONNECTION_H\n\n#include \"WIZnet_Socket.h\"\n#include \"Endpoint.h\"\n\n/**\nTCP socket connection\n*/\nclass TCPSocketConnection: public WIZnet_Socket, public Endpoint {\n friend class TCPSocketServer;\n \npublic:\n /** TCP socket connection\n */\n TCPSocketConnection();\n \n /** Connects this TCP socket to the server\n \\param host The host to connect to. It can either be an IP Address or a hostname that will be resolved with DNS.\n \\param port The host's port to connect to.\n \\return 0 on success, -1 on failure.\n */\n int connect(const char* host, const int port);\n \n /** Check if the socket is connected\n \\return true if connected, false otherwise.\n */\n bool is_connected(void);\n \n /** Send data to the remote host.\n \\param data The buffer to send to the host.\n \\param length The length of the buffer to send.\n \\return the number of written bytes on success (>=0) or -1 on failure\n */\n int send(char* data, int length);\n \n /** Send all the data to the remote host.\n \\param data The buffer to send to the host.\n \\param length The length of the buffer to send.\n \\return the number of written bytes on success (>=0) or -1 on failure\n */\n int send_all(char* data, int length);\n \n /** Receive data from the remote host.\n \\param data The buffer in which to store the data received from the host.\n \\param length The maximum length of the buffer.\n \\return the number of received bytes on success (>=0) or -1 on failure\n */\n int receive(char* data, int length);\n \n /** Receive all the data from the remote host.\n \\param data The buffer in which to store the data received from the host.\n \\param length The maximum length of the buffer.\n \\return the number of received bytes on success (>=0) or -1 on failure\n */\n int receive_all(char* data, int length);\n\nprivate:\n bool _is_connected;\n};\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/Socket/TCPSocketServer.cpp", "content": "/* Copyright (C) 2012 mbed.org, MIT License\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of this software\n * and associated documentation files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge, publish, distribute,\n * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all copies or\n * substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING\n * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,\n * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n */\n\n#include \"TCPSocketServer.h\"\n\nTCPSocketServer::TCPSocketServer() {}\n\n// Server initialization\nint TCPSocketServer::bind(int port)\n{\n // set the listen_port for next connection. \n listen_port = port;\n if (_sock_fd < 0) {\n _sock_fd = eth->new_socket();\n if (_sock_fd < 0) {\n return -1;\n }\n }\n // set TCP protocol\n eth->setProtocol(_sock_fd, WIZnet_Chip::TCP);\n // set local port\n eth->sreg(_sock_fd, Sn_PORT, port);\n // connect the network\n eth->scmd(_sock_fd, WIZnet_Chip::OPEN);\n return 0;\n}\n\nint TCPSocketServer::listen(int backlog)\n{\n if (_sock_fd < 0) {\n return -1;\n }\n if (backlog != 1) {\n return -1;\n }\n eth->scmd(_sock_fd, WIZnet_Chip::LISTEN);\n return 0;\n}\n\n\nint TCPSocketServer::accept(TCPSocketConnection& connection)\n{\n if (_sock_fd < 0) {\n return -1;\n }\n Timer t;\n t.reset();\n t.start();\n while(1) {\n if (t.read_ms() > _timeout && _blocking == false) {\n return -1;\n }\n if (eth->sreg(_sock_fd, Sn_SR) == WIZnet_Chip::SOCK_ESTABLISHED) {\n break;\n }\n }\n uint32_t ip = eth->sreg(_sock_fd, Sn_DIPR);\n char host[16];\n snprintf(host, sizeof(host), \"%d.%d.%d.%d\", (ip>>24)&0xff, (ip>>16)&0xff, (ip>>8)&0xff, ip&0xff);\n uint16_t port = eth->sreg(_sock_fd, Sn_DPORT);\n\n // change this server socket to connection socket.\n connection._sock_fd = _sock_fd;\n connection._is_connected = true;\n connection.set_address(host, port);\n\n // and then, for the next connection, server socket should be assigned new one.\n _sock_fd = -1; // want to assign new available _sock_fd.\n if(bind(listen_port) < 0) {\n // modified by Patrick Pollet\n error(\"No more socket for listening, bind error\");\n return -1;\n } else {\n //return -1;\n if(listen(1) < 0) {\n // modified by Patrick Pollet\n error(\"No more socket for listening, listen error\");\n return -1;\n }\n }\n\n return 0;\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/Socket/TCPSocketServer.h", "content": "/* Copyright (C) 2012 mbed.org, MIT License\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of this software\n * and associated documentation files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge, publish, distribute,\n * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all copies or\n * substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING\n * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,\n * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n */\n#ifndef TCPSOCKETSERVER_H\n#define TCPSOCKETSERVER_H\n\n#include \"WIZnet_Socket.h\"\n#include \"TCPSocketConnection.h\"\n\n/** TCP Server.\n */\nclass TCPSocketServer : public WIZnet_Socket\n{\npublic:\n /** Instantiate a TCP Server.\n */\n TCPSocketServer();\n\n /** Bind a socket to a specific port.\n \\param port The port to listen for incoming connections on.\n \\return 0 on success, -1 on failure.\n */\n int bind(int port);\n\n /** Start listening for incoming connections.\n \\param backlog number of pending connections that can be queued up at any\n one time [Default: 1].\n \\return 0 on success, -1 on failure.\n */\n int listen(int backlog=1);\n\n /** Accept a new connection.\n \\param connection A TCPSocketConnection instance that will handle the incoming connection.\n \\return 0 on success, -1 on failure.\n */\n int accept(TCPSocketConnection& connection);\n\nprivate :\n int listen_port;\n};\n\n#endif\n\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/Socket/WIZnet_Socket.cpp", "content": "/* Copyright (C) 2012 mbed.org, MIT License\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of this software\n * and associated documentation files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge, publish, distribute,\n * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all copies or\n * substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING\n * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,\n * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n */\n\n#include \"WIZnet_Socket.h\"\n\nWIZnet_Socket::WIZnet_Socket() : _sock_fd(-1),_blocking(true), _timeout(1500)\n{\n eth = WIZnet_Chip::getInstance();\n if (eth == NULL) {\n error(\"Socket constructor error: no W7500 instance available!\\r\\n\");\n }\n}\n\nvoid WIZnet_Socket::set_blocking(bool blocking, unsigned int timeout)\n{\n _blocking = blocking;\n _timeout = timeout;\n}\n\nint WIZnet_Socket::close()\n{\n // add this code refer from EthernetInterface.\n // update by Patrick Pollet\n int res;\n res = eth->close(_sock_fd);\n _sock_fd = -1;\n return (res)? 0: -1;\n}\n\nWIZnet_Socket::~WIZnet_Socket()\n{\n close(); //Don't want to leak\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/Socket/WIZnet_Socket.h", "content": "/* Copyright (C) 2012 mbed.org, MIT License\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of this software\n * and associated documentation files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge, publish, distribute,\n * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all copies or\n * substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING\n * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,\n * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n */\n#ifndef WIZnet_SOCKET_H_\n#define WIZnet_SOCKET_H_\n\n#include \"eth_arch.h\"\n\n#define htons(x) __REV16(x)\n#define ntohs(x) __REV16(x)\n#define htonl(x) __REV(x)\n#define ntohl(x) __REV(x)\n\n/** Socket file descriptor and select wrapper\n */\nclass WIZnet_Socket {\npublic:\n /** Socket\n */\n WIZnet_Socket();\n \n /** Set blocking or non-blocking mode of the socket and a timeout on\n blocking socket operations\n \\param blocking true for blocking mode, false for non-blocking mode.\n \\param timeout timeout in ms [Default: (1500)ms].\n */\n //void set_blocking(bool blocking, unsigned int timeout=1500);\n void set_blocking(bool blocking, unsigned int timeout=1);\n \n /** Close the socket file descriptor\n */\n int close();\n \n ~WIZnet_Socket();\n \nprotected:\n int _sock_fd;\n bool _blocking;\n int _timeout;\n\n WIZnet_Chip* eth;\n};\n\n\n#endif /* SOCKET_H_ */\n\n\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/Socket/WIZnet_UDPSocket.cpp", "content": "/* Copyright (C) 2012 mbed.org, MIT License\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of this software\n * and associated documentation files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge, publish, distribute,\n * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all copies or\n * substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING\n * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,\n * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n */\n\n#include \"WIZnet_UDPSocket.h\"\n\nstatic int udp_local_port;\n\nWIZnet_UDPSocket::WIZnet_UDPSocket()\n{\n}\n// After init function, bind() should be called.\nint WIZnet_UDPSocket::init(void)\n{\n if (_sock_fd < 0) {\n _sock_fd = eth->new_socket();\n }\n if (eth->setProtocol(_sock_fd, WIZnet_Chip::UDP) == false) return -1;\n return 0;\n}\n\n// Server initialization\nint WIZnet_UDPSocket::bind(int port)\n{\n if (_sock_fd < 0) {\n _sock_fd = eth->new_socket();\n if (_sock_fd < 0) {\n return -1;\n }\n }\n // set local port\n if (port != 0) {\n eth->sreg(_sock_fd, Sn_PORT, port);\n } else {\n udp_local_port++;\n eth->sreg(_sock_fd, Sn_PORT, udp_local_port);\n }\n // set udp protocol\n eth->setProtocol(_sock_fd, WIZnet_Chip::UDP);\n eth->scmd(_sock_fd, WIZnet_Chip::OPEN);\n return 0;\n}\n\n// -1 if unsuccessful, else number of bytes written\nint WIZnet_UDPSocket::sendTo(Endpoint &remote, char *packet, int length)\n{\n int size = eth->wait_writeable(_sock_fd, _blocking ? -1 : _timeout, length-1);\n if (size < 0) {\n return -1;\n }\n confEndpoint(remote);\n int ret = eth->send(_sock_fd, packet, length);\n return ret;\n}\n\n// -1 if unsuccessful, else number of bytes received\nint WIZnet_UDPSocket::receiveFrom(Endpoint &remote, char *buffer, int length)\n{\n uint8_t info[8];\n int size = eth->wait_readable(_sock_fd, _blocking ? -1 : _timeout, sizeof(info));\n if (size < 0) {\n return -1;\n }\n eth->recv(_sock_fd, (char*)info, sizeof(info));\n readEndpoint(remote, info);\n int udp_size = info[6]<<8|info[7];\n //TEST_ASSERT(udp_size <= (size-sizeof(info)));\n if (udp_size > (size-sizeof(info))) {\n return -1;\n }\n\n /* Perform Length check here to prevent buffer overrun */\n /* fixed by Sean Newton (https://developer.mbed.org/users/SeanNewton/) */\n if (udp_size > length) {\n //printf(\"udp_size: %d\\n\",udp_size);\n return -1;\n }\n return eth->recv(_sock_fd, buffer, udp_size);\n}\n\nvoid WIZnet_UDPSocket::confEndpoint(Endpoint & ep)\n{\n char * host = ep.get_address();\n // set remote host\n eth->sreg_ip(_sock_fd, Sn_DIPR, host);\n // set remote port\n eth->sreg(_sock_fd, Sn_DPORT, ep.get_port());\n}\n\nvoid WIZnet_UDPSocket::readEndpoint(Endpoint & ep, uint8_t info[])\n{\n char addr[17];\n snprintf(addr, sizeof(addr), \"%d.%d.%d.%d\", info[0], info[1], info[2], info[3]);\n uint16_t port = info[4]<<8|info[5];\n ep.set_address(addr, port);\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/Socket/WIZnet_UDPSocket.h", "content": "/* Copyright (C) 2012 mbed.org, MIT License\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of this software\n * and associated documentation files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge, publish, distribute,\n * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all copies or\n * substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING\n * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,\n * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n */\n\n#ifndef WIZnet_UDPSOCKET_H\n#define WIZnet_UDPSOCKET_H\n\n#include \"Endpoint.h\"\n#include \"WIZnet_Socket.h\"\n\n/**\nUDP Socket\n*/\nclass WIZnet_UDPSocket: public WIZnet_Socket {\n\npublic:\n /** Instantiate an UDP Socket.\n */\n WIZnet_UDPSocket();\n \n /** Init the UDP Client Socket without binding it to any specific port\n \\return 0 on success, -1 on failure.\n */\n int init(void);\n \n /** Bind a UDP Server Socket to a specific port\n \\param port The port to listen for incoming connections on\n \\return 0 on success, -1 on failure.\n */\n int bind(int port = -1);\n \n /** Send a packet to a remote endpoint\n \\param remote The remote endpoint\n \\param packet The packet to be sent\n \\param length The length of the packet to be sent\n \\return the number of written bytes on success (>=0) or -1 on failure\n */\n int sendTo(Endpoint &remote, char *packet, int length);\n \n /** Receive a packet from a remote endpoint\n \\param remote The remote endpoint\n \\param buffer The buffer for storing the incoming packet data. If a packet\n is too long to fit in the supplied buffer, excess bytes are discarded\n \\param length The length of the buffer\n \\return the number of received bytes on success (>=0) or -1 on failure\n */\n int receiveFrom(Endpoint &remote, char *buffer, int length);\n \nprivate:\n void confEndpoint(Endpoint & ep);\n void readEndpoint(Endpoint & ep, uint8_t info[]);\n};\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/Socket/dnsname.h", "content": "// dnsname.h 2013/8/27\n#pragma once\n//#include \n#include \"pico_string.h\"\nclass dnsname {\npublic:\n uint8_t *buf;\n pico_string str;\n dnsname(uint8_t *s) {\n buf = s;\n }\n int decode(int pos) {\n while(1) {\n int len = buf[pos++];\n if (len == 0x00) {\n break;\n }\n if ((len&0xc0) == 0xc0) { //compress\n int offset = (len&0x3f)<<8|buf[pos];\n decode(offset);\n return pos+1;\n }\n if (!str.empty()) {\n str.append(\".\");\n }\n str.append((const char*)(buf+pos), len);\n pos += len;\n }\n return pos;\n }\n\n int encode(int pos, char* s) {\n while(*s) { \n char *f = strchr(s, '.');\n if (f == NULL) {\n int len = strlen(s);\n buf[pos++] = len;\n memcpy(buf+pos, s, len);\n pos += len;\n break;\n }\n int len = f - s;\n buf[pos++] = len;\n memcpy(buf+pos, s, len);\n s = f+1;\n pos += len;\n }\n buf[pos++] = 0x00;\n return pos;\n }\n};\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/Socket/pico_string.h", "content": "// pico_string.h 2013/8/27\n#pragma once\nclass pico_string {\npublic:\n pico_string(){\n _len = 0;\n _buf = (char*)malloc(1);\n if (_buf) {\n _buf[0] = '\\0';\n }\n }\n ~pico_string() {\n if (_buf) {\n free(_buf);\n }\n }\n bool empty() {\n return _len == 0;\n }\n void append(const char* s, int len) {\n if (_buf == NULL) {\n return;\n }\n char* p = (char*)malloc(_len+len+1);\n if (p == NULL) {\n return;\n }\n memcpy(p, _buf, _len);\n memcpy(p+_len, s, len);\n p[_len+len] = '\\0';\n free(_buf);\n _buf = p;\n }\n void append(const char* s) {\n append(s, strlen(s));\n }\n char* c_str() {\n if (_buf) {\n return _buf;\n }\n return \"\";\n }\nprivate:\n char* _buf;\n int _len;\n};\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/WIZnetInterface.cpp", "content": "/* Copyright (C) 2012 mbed.org, MIT License\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of this software\n * and associated documentation files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge, publish, distribute,\n * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all copies or\n * substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING\n * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,\n * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n */\n\n#include \"WIZnetInterface.h\"\n#include \"DHCPClient.h\"\n\n#if (not defined TARGET_WIZwiki_W7500) && (not defined TARGET_WIZwiki_W7500P) && (not defined TARGET_WIZwiki_W7500ECO)\nWIZnetInterface::WIZnetInterface(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset) :\n WIZnet_Chip(mosi, miso, sclk, cs, reset)\n{\n ip_set = false;\n}\n\nWIZnetInterface::WIZnetInterface(SPI* spi, PinName cs, PinName reset) :\n WIZnet_Chip(spi, cs, reset)\n{\n ip_set = false;\n}\n#endif\n\nint WIZnetInterface::init()\n{\n dhcp = true;\n reset();\n \n return 0;\n}\n\nint WIZnetInterface::init(uint8_t * mac)\n{\n dhcp = true;\n //\n for (int i =0; i < 6; i++) this->mac[i] = mac[i];\n //\n reset();\n \n return 0;\n}\n\nint WIZnetInterface::init(uint8_t * mac, const char* ip, const char* mask, const char* gateway)\n{\n dhcp = false;\n //\n for (int i =0; i < 6; i++) this->mac[i] = mac[i];\n //\n this->ip = str_to_ip(ip);\n strcpy(ip_string, ip);\n ip_set = true;\n this->netmask = str_to_ip(mask);\n this->gateway = str_to_ip(gateway);\n reset();\n\n // @Jul. 8. 2014 add code. should be called to write chip.\n setmac();\n setip();\n \n return 0;\n}\n\n// Connect Bring the interface up, start DHCP if needed.\nint WIZnetInterface::connect()\n{\n if (dhcp) {\n int r = IPrenew();\n if (r < 0) {\n return r;\n }\n }\n \n if (WIZnet_Chip::setip() == false) return -1;\n return 0;\n}\n\n// Disconnect Bring the interface down.\nint WIZnetInterface::disconnect()\n{\n //if (WIZnet_Chip::disconnect() == false) return -1;\n return 0;\n}\n\n\nchar* WIZnetInterface::getIPAddress()\n{\n uint32_t ip = reg_rd(SIPR);\n snprintf(ip_string, sizeof(ip_string), \"%d.%d.%d.%d\", \n (uint8_t)((ip>>24)&0xff), \n (uint8_t)((ip>>16)&0xff), \n (uint8_t)((ip>>8)&0xff), \n (uint8_t)(ip&0xff));\n return ip_string;\n}\n\nchar* WIZnetInterface::getNetworkMask()\n{\n uint32_t ip = reg_rd(SUBR);\n snprintf(mask_string, sizeof(mask_string), \"%d.%d.%d.%d\", \n (uint8_t)((ip>>24)&0xff), \n (uint8_t)((ip>>16)&0xff), \n (uint8_t)((ip>>8)&0xff), \n (uint8_t)(ip&0xff));\n return mask_string;\n}\n\nchar* WIZnetInterface::getGateway()\n{\n uint32_t ip = reg_rd(GAR);\n snprintf(gw_string, sizeof(gw_string), \"%d.%d.%d.%d\", \n (uint8_t)((ip>>24)&0xff), \n (uint8_t)((ip>>16)&0xff), \n (uint8_t)((ip>>8)&0xff), \n (uint8_t)(ip&0xff));\n return gw_string;\n}\n\nchar* WIZnetInterface::getMACAddress()\n{\n uint8_t mac[6];\n reg_rd_mac(SHAR, mac);\n snprintf(mac_string, sizeof(mac_string), \"%02X:%02X:%02X:%02X:%02X:%02X\", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);\n //ethernet_address(mac_string);\n return mac_string; \n \n}\n\nint WIZnetInterface::IPrenew(int timeout_ms)\n{\n DHCPClient dhcp;\n int err = dhcp.setup(timeout_ms);\n if (err == (-1)) {\n return -1;\n }\n// printf(\"Connected, IP: %d.%d.%d.%d\\n\", dhcp.yiaddr[0], dhcp.yiaddr[1], dhcp.yiaddr[2], dhcp.yiaddr[3]);\n ip = (dhcp.yiaddr[0] <<24) | (dhcp.yiaddr[1] <<16) | (dhcp.yiaddr[2] <<8) | dhcp.yiaddr[3];\n gateway = (dhcp.gateway[0]<<24) | (dhcp.gateway[1]<<16) | (dhcp.gateway[2]<<8) | dhcp.gateway[3];\n netmask = (dhcp.netmask[0]<<24) | (dhcp.netmask[1]<<16) | (dhcp.netmask[2]<<8) | dhcp.netmask[3];\n dnsaddr = (dhcp.dnsaddr[0]<<24) | (dhcp.dnsaddr[1]<<16) | (dhcp.dnsaddr[2]<<8) | dhcp.dnsaddr[3];\n return 0;\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/WIZnetInterface.h", "content": "/* Copyright (C) 2012 mbed.org, MIT License\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of this software\n * and associated documentation files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge, publish, distribute,\n * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all copies or\n * substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING\n * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,\n * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n */\n\n#pragma once\n#include \"eth_arch.h\"\n /** Interface using Wiznet chip to connect to an IP-based network\n *\n */\nclass WIZnetInterface: public WIZnet_Chip {\npublic:\n\n#if (not defined TARGET_WIZwiki_W7500) && (not defined TARGET_WIZwiki_W7500P) && (not defined TARGET_WIZwiki_W7500ECO)\n\n /**\n * Constructor\n *\n * \\param mosi mbed pin to use for SPI\n * \\param miso mbed pin to use for SPI\n * \\param sclk mbed pin to use for SPI\n * \\param cs chip select of the WIZnet_Chip\n * \\param reset reset pin of the WIZnet_Chip\n */\n WIZnetInterface(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset);\n WIZnetInterface(SPI* spi, PinName cs, PinName reset);\n#endif\n\n /** Initialize the interface with DHCP.\n * Initialize the interface and configure it to use DHCP (no connection at this point).\n * \\return 0 on success, a negative number on failure\n */\n int init(); //With DHCP\n int init(uint8_t * mac); //With DHCP\n\n /** Initialize the interface with a static IP address.\n * Initialize the interface and configure it with the following static configuration (no connection at this point).\n * \\param ip the IP address to use\n * \\param mask the IP address mask\n * \\param gateway the gateway to use\n * \\return 0 on success, a negative number on failure\n */\n int init(uint8_t * mac, const char* ip, const char* mask, const char* gateway);\n\n /** Connect\n * Bring the interface up, start DHCP if needed.\n * \\return 0 on success, a negative number on failure\n */\n int connect();\n \n /** Disconnect\n * Bring the interface down\n * \\return 0 on success, a negative number on failure\n */\n int disconnect();\n \n /** Get IP address & MAC address\n *\n * @ returns ip address\n */\n char* getIPAddress();\n char* getNetworkMask();\n char* getGateway();\n char* getMACAddress();\n\n int IPrenew(int timeout_ms = 15*1000);\n \nprivate:\n char ip_string[20];\n char mask_string[20];\n char gw_string[20];\n char mac_string[20];\n bool ip_set;\n};\n\n#include \"TCPSocketConnection.h\"\n#include \"TCPSocketServer.h\"\n#include \"WIZnet_UDPSocket.h\"\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/arch/ext/W5500.cpp", "content": "/* Copyright (C) 2012 mbed.org, MIT License\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of this software\n * and associated documentation files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge, publish, distribute,\n * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all copies or\n * substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING\n * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,\n * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n */\n#include \"eth_arch.h\"\n#if (not defined TARGET_WIZwiki_W7500) && (not defined TARGET_WIZwiki_W7500P) && (not defined TARGET_WIZwiki_W7500ECO)\n\n\n\n#include \"mbed.h\"\n#include \"mbed_debug.h\"\n#include \"DNSClient.h\"\n\n\n//Debug is disabled by default\n#if 0\n#define DBG(...) do{debug(\"%p %d %s \", this,__LINE__,__PRETTY_FUNCTION__); debug(__VA_ARGS__); } while(0);\n//#define DBG(x, ...) debug(\"[W5500:DBG]\"x\"\\r\\n\", ##__VA_ARGS__);\n#define WARN(x, ...) debug(\"[W5500:WARN]\"x\"\\r\\n\", ##__VA_ARGS__);\n#define ERR(x, ...) debug(\"[W5500:ERR]\"x\"\\r\\n\", ##__VA_ARGS__);\n#else\n#define DBG(x, ...)\n#define WARN(x, ...)\n#define ERR(x, ...)\n#endif\n\n#if 1\n#define INFO(x, ...) debug(\"[W5500:INFO]\"x\"\\r\\n\", ##__VA_ARGS__);\n#else\n#define INFO(x, ...)\n#endif\n\n#define DBG_SPI 0\n\nWIZnet_Chip* WIZnet_Chip::inst;\n\nWIZnet_Chip::WIZnet_Chip(PinName mosi, PinName miso, PinName sclk, PinName _cs, PinName _reset):\n cs(_cs), reset_pin(_reset)\n{\n spi = new SPI(mosi, miso, sclk);\n cs = 1;\n reset_pin = 1;\n inst = this;\n sock_any_port = SOCK_ANY_PORT_NUM;\n}\n\nWIZnet_Chip::WIZnet_Chip(SPI* spi, PinName _cs, PinName _reset):\n cs(_cs), reset_pin(_reset)\n{\n this->spi = spi;\n cs = 1;\n reset_pin = 1;\n inst = this;\n sock_any_port = SOCK_ANY_PORT_NUM;\n}\n\nbool WIZnet_Chip::setmac()\n{\n\n for (int i =0; i < 6; i++) reg_wr(SHAR+i, mac[i]);\n\n return true;\n}\n\n// Set the IP\nbool WIZnet_Chip::setip()\n{\n reg_wr(SIPR, ip);\n reg_wr(GAR, gateway);\n reg_wr(SUBR, netmask);\n return true;\n}\n\nbool WIZnet_Chip::setProtocol(int socket, Protocol p)\n{\n if (socket < 0) {\n return false;\n }\n sreg(socket, Sn_MR, p);\n return true;\n}\n\nbool WIZnet_Chip::connect(int socket, const char * host, int port, int timeout_ms)\n{\n if (socket < 0) {\n return false;\n }\n sreg(socket, Sn_MR, TCP);\n scmd(socket, OPEN);\n sreg_ip(socket, Sn_DIPR, host);\n sreg(socket, Sn_DPORT, port);\n sreg(socket, Sn_PORT, new_port());\n scmd(socket, CONNECT);\n Timer t;\n t.reset();\n t.start();\n while(!is_connected(socket)) {\n if (t.read_ms() > timeout_ms) {\n return false;\n }\n }\n return true;\n}\n\nbool WIZnet_Chip::gethostbyname(const char* host, uint32_t* ip)\n{\n uint32_t addr = str_to_ip(host);\n char buf[17];\n snprintf(buf, sizeof(buf), \"%d.%d.%d.%d\", (addr>>24)&0xff, (addr>>16)&0xff, (addr>>8)&0xff, addr&0xff);\n if (strcmp(buf, host) == 0) {\n *ip = addr;\n return true;\n }\n DNSClient client;\n if(client.lookup(host)) {\n *ip = client.ip;\n return true;\n }\n return false;\n}\n\nbool WIZnet_Chip::disconnect()\n{\n return true;\n}\n\nbool WIZnet_Chip::is_connected(int socket)\n{\n /*\n if (sreg(socket, Sn_SR) == SOCK_ESTABLISHED) {\n return true;\n }\n */\n uint8_t tmpSn_SR;\n tmpSn_SR = sreg(socket, Sn_SR);\n // packet sending is possible, when state is SOCK_CLOSE_WAIT.\n if ((tmpSn_SR == SOCK_ESTABLISHED) || (tmpSn_SR == SOCK_CLOSE_WAIT)) {\n return true;\n }\n return false;\n}\n\n// Reset the chip & set the buffer\nvoid WIZnet_Chip::reset()\n{\n#if defined(USE_WIZ550IO_MAC)\n //read the MAC address inside the module \n reg_rd_mac(SHAR, mac); \n#endif\n // hw reset\n reset_pin = 1;\n reset_pin = 0;\n wait_us(500); // 500us (w5500)\n reset_pin = 1;\n wait_ms(400); // 400ms (w5500)\n#if defined(USE_WIZ550IO_MAC)\n // write MAC address inside the WZTOE MAC address register\n reg_wr_mac(SHAR, mac);\n#endif\n // set RX and TX buffer size\n#if 0\n for (int socket = 0; socket < MAX_SOCK_NUM; socket++) {\n sreg(socket, Sn_RXBUF_SIZE, 2);\n sreg(socket, Sn_TXBUF_SIZE, 2);\n }\n#endif\n}\n\n\nbool WIZnet_Chip::close(int socket)\n{\n if (socket < 0) {\n return false;\n }\n // if not connected, return\n if (sreg(socket, Sn_SR) == SOCK_CLOSED) {\n return true;\n }\n if (sreg(socket, Sn_MR) == TCP) {\n scmd(socket, DISCON);\n }\n scmd(socket, CLOSE);\n sreg(socket, Sn_IR, 0xff);\n return true;\n}\n\nint WIZnet_Chip::wait_readable(int socket, int wait_time_ms, int req_size)\n{\n if (socket < 0) {\n return -1;\n }\n Timer t;\n t.reset();\n t.start();\n while(1) {\n //int size = sreg(socket, Sn_RX_RSR);\n // during the reading Sn_RX_RXR, it has the possible change of this register.\n // so read twice and get same value then use size information.\n int size, size2;\n do {\n size = sreg(socket, Sn_RX_RSR);\n size2 = sreg(socket, Sn_RX_RSR);\n } while (size != size2);\n \n if (size > req_size) {\n return size;\n }\n break;\n //if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {\n // break;\n //}\n }\n return -1;\n}\n\nint WIZnet_Chip::wait_writeable(int socket, int wait_time_ms, int req_size)\n{\n if (socket < 0) {\n return -1;\n }\n Timer t;\n t.reset();\n t.start();\n while(1) {\n //int size = sreg(socket, Sn_TX_FSR);\n // during the reading Sn_TX_FSR, it has the possible change of this register.\n // so read twice and get same value then use size information.\n int size, size2;\n do {\n size = sreg(socket, Sn_TX_FSR);\n size2 = sreg(socket, Sn_TX_FSR);\n } while (size != size2);\n \n if (size > req_size) {\n return size;\n }\n break;\n //if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {\n // break;\n //}\n }\n return -1;\n}\n\nint WIZnet_Chip::send(int socket, const char * str, int len)\n{\n if (socket < 0) {\n return -1;\n }\n uint16_t ptr = sreg(socket, Sn_TX_WR);\n uint8_t cntl_byte = (0x14 + (socket << 5));\n spi_write(ptr, cntl_byte, (uint8_t*)str, len);\n sreg(socket, Sn_TX_WR, ptr + len);\n scmd(socket, SEND);\n uint8_t tmp_Sn_IR;\n while (( (tmp_Sn_IR = sreg(socket, Sn_IR)) & INT_SEND_OK) != INT_SEND_OK) {\n // @Jul.10, 2014 fix contant name, and udp sendto function.\n switch (sreg(socket, Sn_SR)) {\n case SOCK_CLOSED :\n close(socket);\n return 0;\n //break;\n case SOCK_UDP :\n // ARP timeout is possible.\n if ((tmp_Sn_IR & INT_TIMEOUT) == INT_TIMEOUT) {\n sreg(socket, Sn_IR, INT_TIMEOUT);\n return 0;\n }\n break;\n default :\n break;\n }\n }\n /*\n while ((sreg(socket, Sn_IR) & INT_SEND_OK) != INT_SEND_OK) {\n if (sreg(socket, Sn_SR) == CLOSED) {\n close(socket);\n return 0;\n }\n }\n */\n sreg(socket, Sn_IR, INT_SEND_OK);\n\n return len;\n}\n\nint WIZnet_Chip::recv(int socket, char* buf, int len)\n{\n if (socket < 0) {\n return -1;\n }\n uint16_t ptr = sreg(socket, Sn_RX_RD);\n uint8_t cntl_byte = (0x18 + (socket << 5));\n spi_read(ptr, cntl_byte, (uint8_t*)buf, len);\n sreg(socket, Sn_RX_RD, ptr + len);\n scmd(socket, RECV);\n return len;\n}\n\nint WIZnet_Chip::new_socket()\n{\n for(int s = 0; s < MAX_SOCK_NUM; s++) {\n if (sreg(s, Sn_SR) == SOCK_CLOSED) {\n return s;\n }\n }\n return -1;\n}\n\nuint16_t WIZnet_Chip::new_port()\n{\n uint16_t port = rand();\n port |= 49152;\n return port;\n}\n\nbool WIZnet_Chip::link(int wait_time_ms)\n{\n Timer t;\n t.reset();\n t.start();\n while(1) {\n int is_link = ethernet_link();\n \n if (is_link) {\n return true;\n }\n if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {\n break;\n }\n }\n return 0;\n}\n\nvoid WIZnet_Chip::set_link(PHYMode phymode)\n{\n int speed = -1;\n int duplex = 0;\n\n switch(phymode) {\n case AutoNegotiate : speed = -1; duplex = 0; break;\n case HalfDuplex10 : speed = 0; duplex = 0; break;\n case FullDuplex10 : speed = 0; duplex = 1; break;\n case HalfDuplex100 : speed = 1; duplex = 0; break;\n case FullDuplex100 : speed = 1; duplex = 1; break;\n }\n\n ethernet_set_link(speed, duplex);\n}\n\nvoid WIZnet_Chip::scmd(int socket, Command cmd)\n{\n sreg(socket, Sn_CR, cmd);\n while(sreg(socket, Sn_CR));\n}\n\nvoid WIZnet_Chip::spi_write(uint16_t addr, uint8_t cb, const uint8_t *buf, uint16_t len)\n{\n cs = 0;\n spi->write(addr >> 8);\n spi->write(addr & 0xff);\n spi->write(cb);\n for(int i = 0; i < len; i++) {\n spi->write(buf[i]);\n }\n cs = 1;\n\n#if DBG_SPI \n debug(\"[SPI]W %04x(%02x %d)\", addr, cb, len);\n for(int i = 0; i < len; i++) {\n debug(\" %02x\", buf[i]);\n if (i > 16) {\n debug(\" ...\");\n break;\n }\n }\n debug(\"\\r\\n\");\n#endif\n}\n\nvoid WIZnet_Chip::spi_read(uint16_t addr, uint8_t cb, uint8_t *buf, uint16_t len)\n{\n cs = 0;\n spi->write(addr >> 8);\n spi->write(addr & 0xff);\n spi->write(cb);\n for(int i = 0; i < len; i++) {\n buf[i] = spi->write(0);\n }\n cs = 1;\n\n#if DBG_SPI\n debug(\"[SPI]R %04x(%02x %d)\", addr, cb, len);\n for(int i = 0; i < len; i++) {\n debug(\" %02x\", buf[i]);\n if (i > 16) {\n debug(\" ...\");\n break;\n }\n }\n debug(\"\\r\\n\");\n if ((addr&0xf0ff)==0x4026 || (addr&0xf0ff)==0x4003) {\n wait_ms(200);\n }\n#endif\n}\n\nuint32_t str_to_ip(const char* str)\n{\n uint32_t ip = 0;\n char* p = (char*)str;\n for(int i = 0; i < 4; i++) {\n ip |= atoi(p);\n p = strchr(p, '.');\n if (p == NULL) {\n break;\n }\n ip <<= 8;\n p++;\n }\n return ip;\n}\n\nvoid printfBytes(char* str, uint8_t* buf, int len)\n{\n printf(\"%s %d:\", str, len);\n for(int i = 0; i < len; i++) {\n printf(\" %02x\", buf[i]);\n }\n printf(\"\\n\");\n}\n\nvoid printHex(uint8_t* buf, int len)\n{\n for(int i = 0; i < len; i++) {\n if ((i%16) == 0) {\n printf(\"%p\", buf+i);\n }\n printf(\" %02x\", buf[i]);\n if ((i%16) == 15) {\n printf(\"\\n\");\n }\n }\n printf(\"\\n\");\n}\n\nvoid debug_hex(uint8_t* buf, int len)\n{\n for(int i = 0; i < len; i++) {\n if ((i%16) == 0) {\n debug(\"%p\", buf+i);\n }\n debug(\" %02x\", buf[i]);\n if ((i%16) == 15) {\n debug(\"\\n\");\n }\n }\n debug(\"\\n\");\n}\n\nint WIZnet_Chip::ethernet_link(void) {\n int val = getPHYCFGR();\n return (val&0x01);\n}\n\nvoid WIZnet_Chip::ethernet_set_link(int speed, int duplex) {\n uint32_t val=0;\n if((speed < 0) || (speed > 1)) {\n val = (PHYCFGR_OPMDC_ALLA)<<3; \n } else {\n val = (((speed&0x01)<<1)+ (duplex&0x01))<<3; \n }\n setPHYCFGR((uint8_t)(PHYCFGR_RST&(PHYCFGR_OPMD|val)));\n wait(0.2);\n setPHYCFGR((uint8_t)((~PHYCFGR_RST)|(PHYCFGR_OPMD|val)));\n wait(0.2);\n}\n\n void WIZnet_Chip::reg_rd_mac(uint16_t addr, uint8_t* data) {\n spi_read(addr, 0x00, data, 6);\n }\n\n void WIZnet_Chip::reg_wr_ip(uint16_t addr, uint8_t cb, const char* ip) {\n uint8_t buf[4];\n char* p = (char*)ip;\n for(int i = 0; i < 4; i++) {\n buf[i] = atoi(p);\n p = strchr(p, '.');\n if (p == NULL) {\n break;\n }\n p++;\n }\n spi_write(addr, cb, buf, sizeof(buf));\n }\n \n void WIZnet_Chip::sreg_ip(int socket, uint16_t addr, const char* ip) {\n reg_wr_ip(addr, (0x0C + (socket << 5)), ip);\n }\n \n void WIZnet_Chip::reg_rd_ip_byte(uint16_t addr, uint8_t* data) {\n spi_read(addr, 0x00, data, 4);\n }\n \n void WIZnet_Chip::reg_wr_ip_byte(uint16_t addr, uint8_t* data) {\n spi_write(addr, 0x04, data, 4);\n }\n\n\n#endif\n\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/arch/ext/W5500.h", "content": "/* Copyright (C) 2012 mbed.org, MIT License\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of this software\n * and associated documentation files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge, publish, distribute,\n * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all copies or\n * substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING\n * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,\n * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n */\n\n#pragma once\n\n#include \"mbed.h\"\n#include \"mbed_debug.h\"\n\n#define TEST_ASSERT(A) while(!(A)){debug(\"\\n\\n%s@%d %s ASSERT!\\n\\n\",__PRETTY_FUNCTION__,__LINE__,#A);exit(1);};\n\n#define DEFAULT_WAIT_RESP_TIMEOUT 500\n\n#define SOCK_ERROR 0 \n#define SOCKERR_SOCKNUM (SOCK_ERROR - 1) ///< Invalid socket number\n#define SOCKERR_SOCKOPT (SOCK_ERROR - 2) ///< Invalid socket option\n#define SOCKERR_SOCKINIT (SOCK_ERROR - 3) ///< Socket is not initialized\n#define SOCKERR_SOCKCLOSED (SOCK_ERROR - 4) ///< Socket unexpectedly closed.\n#define SOCKERR_SOCKMODE (SOCK_ERROR - 5) ///< Invalid socket mode for socket operation.\n#define SOCKERR_SOCKFLAG (SOCK_ERROR - 6) ///< Invalid socket flag\n#define SOCKERR_SOCKSTATUS (SOCK_ERROR - 7) ///< Invalid socket status for socket operation.\n#define SOCKERR_ARG (SOCK_ERROR - 10) ///< Invalid argrument.\n#define SOCKERR_PORTZERO (SOCK_ERROR - 11) ///< Port number is zero\n#define SOCKERR_IPINVALID (SOCK_ERROR - 12) ///< Invalid IP address\n#define SOCKERR_TIMEOUT (SOCK_ERROR - 13) ///< Timeout occurred\n#define SOCKERR_DATALEN (SOCK_ERROR - 14) ///< Data length is zero or greater than buffer max size.\n#define SOCKERR_BUFFER (SOCK_ERROR - 15) ///< Socket buffer is not enough for data communication.\n\n#define SOCK_ANY_PORT_NUM 0xC000;\n\n\n#define MAX_SOCK_NUM 8\n\n#define MR 0x0000\n#define GAR 0x0001\n#define SUBR 0x0005\n#define SHAR 0x0009\n#define SIPR 0x000f\n#define IR 0x0015\n#define IMR 0x0016\n#define SIR 0x0017\n#define SIMR 0x0018\n#define RTR 0x0019\n#define RCR 0x001b\n#define UIPR 0x0028\n#define UPORTR 0x002c\n#define PHYCFGR 0x002e\n\n// W5500 socket register\n#define Sn_MR 0x0000\n#define Sn_CR 0x0001\n#define Sn_IR 0x0002\n#define Sn_SR 0x0003\n#define Sn_PORT 0x0004\n#define Sn_DHAR 0x0006\n#define Sn_DIPR 0x000c\n#define Sn_DPORT 0x0010\n#define Sn_RXBUF_SIZE 0x001e\n#define Sn_TXBUF_SIZE 0x001f\n#define Sn_TX_FSR 0x0020\n#define Sn_TX_RD 0x0022\n#define Sn_TX_WR 0x0024\n#define Sn_RX_RSR 0x0026\n#define Sn_RX_RD 0x0028\n#define Sn_RX_WR 0x002a\n#define Sn_IMR 0x002c\n\n\n//Define for Socket Command register option value\n#define Sn_CR_OPEN 0x01\n#define Sn_CR_LISTEN 0x02\n#define Sn_CR_CONNECT 0x04\n#define Sn_CR_DISCON 0x08\n#define Sn_CR_CLOSE 0x10\n#define Sn_CR_SEND 0x20\n#define Sn_CR_SEND_MAC 0x21\n#define Sn_CR_SEND_KEEP 0x22\n#define Sn_CR_RECV 0x40\n\n\n//Define for Socket Mode register option value\n#define Sn_MR_CLOSE 0x00\n#define Sn_MR_TCP 0x01\n#define Sn_MR_UDP 0x02\n#define Sn_MR_MACRAW 0x04\n#define Sn_MR_UCASTB 0x10\n#define Sn_MR_ND 0x20\n#define Sn_MR_BCASTB 0x40\n#define Sn_MR_MULTI 0x80\n\n#define Sn_IR_SENDOK 0x10\n\n//Sn_IR values\n\n#define Sn_IR_TIMEOUT 0x08\n#define Sn_IR_RECV 0x04\n#define Sn_IR_DISCON 0x02\n#define Sn_IR_CON 0x01\n\n/* PHYCFGR register value */\n#define PHYCFGR_RST ~(1<<7) //< For PHY reset, must operate AND mask.\n#define PHYCFGR_OPMD (1<<6) // Configre PHY with OPMDC value\n#define PHYCFGR_OPMDC_ALLA (7<<3)\n#define PHYCFGR_OPMDC_PDOWN (6<<3)\n#define PHYCFGR_OPMDC_NA (5<<3)\n#define PHYCFGR_OPMDC_100FA (4<<3)\n#define PHYCFGR_OPMDC_100F (3<<3)\n#define PHYCFGR_OPMDC_100H (2<<3)\n#define PHYCFGR_OPMDC_10F (1<<3)\n#define PHYCFGR_OPMDC_10H (0<<3) \n#define PHYCFGR_DPX_FULL (1<<2)\n#define PHYCFGR_DPX_HALF (0<<2)\n#define PHYCFGR_SPD_100 (1<<1)\n#define PHYCFGR_SPD_10 (0<<1)\n#define PHYCFGR_LNK_ON (1<<0)\n#define PHYCFGR_LNK_OFF (0<<0)\n\n//PHY status define\n#define PHY_CONFBY_HW 0 ///< Configured PHY operation mode by HW pin\n#define PHY_CONFBY_SW 1 ///< Configured PHY operation mode by SW register \n#define PHY_MODE_MANUAL 0 ///< Configured PHY operation mode with user setting.\n#define PHY_MODE_AUTONEGO 1 ///< Configured PHY operation mode with auto-negotiation\n#define PHY_SPEED_10 0 ///< Link Speed 10\n#define PHY_SPEED_100 1 ///< Link Speed 100\n#define PHY_DUPLEX_HALF 0 ///< Link Half-Duplex\n#define PHY_DUPLEX_FULL 1 ///< Link Full-Duplex\n#define PHY_LINK_OFF 0 ///< Link Off\n#define PHY_LINK_ON 1 ///< Link On\n#define PHY_POWER_NORM 0 ///< PHY power normal mode\n#define PHY_POWER_DOWN 1 ///< PHY power down mode \n\nenum PHYMode {\n AutoNegotiate = 0,\n HalfDuplex10 = 1,\n FullDuplex10 = 2,\n HalfDuplex100 = 3,\n FullDuplex100 = 4,\n};\nclass WIZnet_Chip {\npublic:\nenum Protocol {\n CLOSED = 0,\n TCP = 1,\n UDP = 2,\n};\n\nenum Command {\n OPEN = 0x01,\n LISTEN = 0x02,\n CONNECT = 0x04,\n DISCON = 0x08,\n CLOSE = 0x10,\n SEND = 0x20,\n SEND_MAC = 0x21, \n SEND_KEEP = 0x22,\n RECV = 0x40,\n \n}; \n\nenum Interrupt {\n INT_CON = 0x01,\n INT_DISCON = 0x02,\n INT_RECV = 0x04,\n INT_TIMEOUT = 0x08,\n INT_SEND_OK = 0x10,\n};\n\nenum Status {\n SOCK_CLOSED = 0x00,\n SOCK_INIT = 0x13,\n SOCK_LISTEN = 0x14,\n SOCK_SYNSENT = 0x15,\n SOCK_ESTABLISHED = 0x17,\n SOCK_CLOSE_WAIT = 0x1c,\n SOCK_UDP = 0x22,\n};\n\n \n uint16_t sock_any_port;\n \n /*\n * Constructor\n *\n * @param spi spi class\n * @param cs cs of the W5500\n * @param reset reset pin of the W5500\n */\n WIZnet_Chip(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset);\n WIZnet_Chip(SPI* spi, PinName cs, PinName reset);\n\n /*\n * Set MAC Address to W5500\n *\n * @return true if connected, false otherwise\n */ \n bool setmac();\n\n /*\n * Set Network Informations (SrcIP, Netmask, Gataway)\n *\n * @return true if connected, false otherwise\n */ \n bool setip();\n\n /*\n * Disconnect the connection\n *\n * @ returns true \n */\n bool disconnect();\n\n /*\n * Open a tcp connection with the specified host on the specified port\n *\n * @param host host (can be either an ip address or a name. If a name is provided, a dns request will be established)\n * @param port port\n * @ returns true if successful\n */\n bool connect(int socket, const char * host, int port, int timeout_ms = 10*1000);\n\n /*\n * Set the protocol (UDP or TCP)\n *\n * @param p protocol\n * @ returns true if successful\n */\n bool setProtocol(int socket, Protocol p);\n\n /*\n * Reset the W5500\n */\n void reset();\n \n int wait_readable(int socket, int wait_time_ms, int req_size = 0);\n\n int wait_writeable(int socket, int wait_time_ms, int req_size = 0);\n\n /*\n * Check if an ethernet link is pressent or not.\n *\n * @returns true if successful\n */\n bool link(int wait_time_ms= 3*1000);\n\n /*\n * Sets the speed and duplex parameters of an ethernet link.\n *\n * @returns true if successful\n */\n void set_link(PHYMode phymode);\n\n /*\n * Check if a tcp link is active\n *\n * @returns true if successful\n */\n bool is_connected(int socket);\n\n /*\n * Close a tcp connection\n *\n * @ returns true if successful\n */\n bool close(int socket);\n\n /*\n * @param str string to be sent\n * @param len string length\n */\n int send(int socket, const char * str, int len);\n\n int recv(int socket, char* buf, int len);\n\n /*\n * Return true if the module is using dhcp\n *\n * @returns true if the module is using dhcp\n */\n bool isDHCP() {\n return dhcp;\n }\n\n bool gethostbyname(const char* host, uint32_t* ip);\n\n static WIZnet_Chip * getInstance() {\n return inst;\n };\n\n int new_socket();\n uint16_t new_port();\n void scmd(int socket, Command cmd);\n\n template\n void sreg(int socket, uint16_t addr, T data) {\n reg_wr(addr, (0x0C + (socket << 5)), data);\n }\n\n template\n T sreg(int socket, uint16_t addr) {\n return reg_rd(addr, (0x08 + (socket << 5)));\n }\n\n template\n void reg_wr(uint16_t addr, T data) {\n return reg_wr(addr, 0x04, data);\n }\n \n template\n void reg_wr(uint16_t addr, uint8_t cb, T data) {\n uint8_t buf[sizeof(T)];\n *reinterpret_cast(buf) = data;\n for(int i = 0; i < sizeof(buf)/2; i++) { // Little Endian to Big Endian\n uint8_t t = buf[i];\n buf[i] = buf[sizeof(buf)-1-i];\n buf[sizeof(buf)-1-i] = t;\n }\n spi_write(addr, cb, buf, sizeof(buf));\n }\n\n template\n T reg_rd(uint16_t addr) {\n return reg_rd(addr, 0x00);\n }\n\n template\n T reg_rd(uint16_t addr, uint8_t cb) {\n uint8_t buf[sizeof(T)];\n spi_read(addr, cb, buf, sizeof(buf));\n for(int i = 0; i < sizeof(buf)/2; i++) { // Big Endian to Little Endian\n uint8_t t = buf[i];\n buf[i] = buf[sizeof(buf)-1-i];\n buf[sizeof(buf)-1-i] = t;\n }\n return *reinterpret_cast(buf);\n }\n\n void reg_rd_mac(uint16_t addr, uint8_t* data);\n/* {\n spi_read(addr, 0x00, data, 6);\n }*/\n\n void reg_wr_ip(uint16_t addr, uint8_t cb, const char* ip);\n /* {\n uint8_t buf[4];\n char* p = (char*)ip;\n for(int i = 0; i < 4; i++) {\n buf[i] = atoi(p);\n p = strchr(p, '.');\n if (p == NULL) {\n break;\n }\n p++;\n }\n spi_write(addr, cb, buf, sizeof(buf));\n }\n */\n void sreg_ip(int socket, uint16_t addr, const char* ip);\n/* {\n reg_wr_ip(addr, (0x0C + (socket << 5)), ip);\n }*/\n \n void reg_rd_ip_byte(uint16_t addr, uint8_t* data);\n/* {\n spi_read(addr, 0x00, data, 4);\n }*/\n \n void reg_wr_ip_byte(uint16_t addr, uint8_t* data);\n/* {\n spi_write(addr, 0x04, data, 4);\n }*/\n \n/////////////////////////////////\n// Common Register I/O function //\n/////////////////////////////////\n/**\n * @ingroup Common_register_access_function\n * @brief Set Mode Register\n * @param (uint8_t)mr The value to be set.\n * @sa getMR()\n */\n void setMR(uint8_t mr) {\n reg_wr(MR,mr);\n }\n\n\n/**\n * @ingroup Common_register_access_function\n * @brief Get Mode Register\n * @return uint8_t. The value of Mode register.\n * @sa setMR()\n */\n uint8_t getMR() {\n return reg_rd(MR);\n }\n\n/**\n * @ingroup Common_register_access_function\n * @brief Set gateway IP address\n * @param (uint8_t*)gar Pointer variable to set gateway IP address. It should be allocated 4 bytes.\n * @sa getGAR()\n */\n void setGAR(uint8_t * gar) {\n reg_wr_ip_byte(GAR,gar);\n }\n\n/**\n * @ingroup Common_register_access_function\n * @brief Get gateway IP address\n * @param (uint8_t*)gar Pointer variable to get gateway IP address. It should be allocated 4 bytes.\n * @sa setGAR()\n */\n void getGAR(uint8_t * gar) { \n reg_rd_ip_byte(GAR,gar);\n }\n\n/**\n * @ingroup Common_register_access_function\n * @brief Set subnet mask address\n * @param (uint8_t*)subr Pointer variable to set subnet mask address. It should be allocated 4 bytes.\n * @sa getSUBR()\n */\n void setSUBR(uint8_t * subr) {\n reg_wr_ip_byte(SUBR, subr);\n }\n\n\n/**\n * @ingroup Common_register_access_function\n * @brief Get subnet mask address\n * @param (uint8_t*)subr Pointer variable to get subnet mask address. It should be allocated 4 bytes.\n * @sa setSUBR()\n */\n void getSUBR(uint8_t * subr) {\n reg_rd_ip_byte(SUBR, subr);\n }\n\n/**\n * @ingroup Common_register_access_function\n * @brief Set local MAC address\n * @param (uint8_t*)shar Pointer variable to set local MAC address. It should be allocated 6 bytes.\n * @sa getSHAR()\n */\n void setSHAR(uint8_t * shar) {\n reg_wr_mac(SHAR, shar);\n }\n\n/**\n * @ingroup Common_register_access_function\n * @brief Get local MAC address\n * @param (uint8_t*)shar Pointer variable to get local MAC address. It should be allocated 6 bytes.\n * @sa setSHAR()\n */\n void getSHAR(uint8_t * shar) {\n reg_rd_mac(SHAR, shar);\n }\n\n/**\n * @ingroup Common_register_access_function\n * @brief Set local IP address\n * @param (uint8_t*)sipr Pointer variable to set local IP address. It should be allocated 4 bytes.\n * @sa getSIPR()\n */\n void setSIPR(uint8_t * sipr) {\n reg_wr_ip_byte(SIPR, sipr);\n }\n\n/**\n * @ingroup Common_register_access_function\n * @brief Get local IP address\n * @param (uint8_t*)sipr Pointer variable to get local IP address. It should be allocated 4 bytes.\n * @sa setSIPR()\n */\n void getSIPR(uint8_t * sipr) {\n reg_rd_ip_byte(SIPR, sipr);\n }\n\n/**\n * @ingroup Common_register_access_function\n * @brief Set @ref IR register\n * @param (uint8_t)ir Value to set @ref IR register.\n * @sa getIR()\n */\n void setIR(uint8_t ir) { \n reg_wr(IR, (ir & 0xF0));\n }\n\n/**\n * @ingroup Common_register_access_function\n * @brief Get @ref IR register\n * @return uint8_t. Value of @ref IR register.\n * @sa setIR()\n */\n uint8_t getIR() {\n return reg_rd(IR & 0xF0);\n }\n \n/**\n * @ingroup Common_register_access_function\n * @brief Set @ref IMR register\n * @param (uint8_t)imr Value to set @ref IMR register.\n * @sa getIMR()\n */\n void setIMR(uint8_t imr) {\n reg_wr(IMR, imr);\n }\n\n/**\n * @ingroup Common_register_access_function\n * @brief Get @ref IMR register\n * @return uint8_t. Value of @ref IMR register.\n * @sa setIMR()\n */\n uint8_t getIMR() {\n return reg_rd(IMR);\n }\n\n\n/**\n * @ingroup Common_register_access_function\n * @brief Set @ref SIR register\n * @param (uint8_t)sir Value to set @ref SIR register.\n * @sa getSIR()\n */\n void setSIR(uint8_t sir) {\n reg_wr(SIR, sir);\n }\n\n/**\n * @ingroup Common_register_access_function\n * @brief Get @ref SIR register\n * @return uint8_t. Value of @ref SIR register.\n * @sa setSIR()\n */\n uint8_t getSIR() {\n return reg_rd(SIR);\n }\n/**\n * @ingroup Common_register_access_function\n * @brief Set @ref SIMR register\n * @param (uint8_t)simr Value to set @ref SIMR register.\n * @sa getSIMR()\n */\n void setSIMR(uint8_t simr) {\n reg_wr(SIMR, simr);\n }\n\n/**\n * @ingroup Common_register_access_function\n * @brief Get @ref SIMR register\n * @return uint8_t. Value of @ref SIMR register.\n * @sa setSIMR()\n */\n uint8_t getSIMR() {\n return reg_rd(SIMR);\n }\n\n/**\n * @ingroup Common_register_access_function\n * @brief Set @ref RTR register\n * @param (uint16_t)rtr Value to set @ref RTR register.\n * @sa getRTR()\n */\n void setRTR(uint16_t rtr) {\n reg_wr(RTR, rtr);\n } \n\n/**\n * @ingroup Common_register_access_function\n * @brief Get @ref RTR register\n * @return uint16_t. Value of @ref RTR register.\n * @sa setRTR()\n */\n uint16_t getRTR() {\n return reg_rd(RTR);\n }\n\n/**\n * @ingroup Common_register_access_function\n * @brief Set @ref RCR register\n * @param (uint8_t)rcr Value to set @ref RCR register.\n * @sa getRCR()\n */\n void setRCR(uint8_t rcr) {\n reg_wr(RCR, rcr);\n }\n\n/**\n * @ingroup Common_register_access_function\n * @brief Get @ref RCR register\n * @return uint8_t. Value of @ref RCR register.\n * @sa setRCR()\n */\n uint8_t getRCR() {\n return reg_rd(RCR);\n }\n\n//================================================== test done ===========================================================\n\n/**\n * @ingroup Common_register_access_function\n * @brief Set @ref PHYCFGR register\n * @param (uint8_t)phycfgr Value to set @ref PHYCFGR register.\n * @sa setPHYCFGR()\n */\n void setPHYCFGR(uint8_t phycfgr) {\n reg_wr(PHYCFGR, phycfgr);\n }\n\n/**\n * @ingroup Common_register_access_function\n * @brief Get @ref PHYCFGR register\n * @return uint8_t. Value of @ref PHYCFGR register.\n * @sa getPHYCFGR()\n */\n uint8_t getPHYCFGR() {\n return reg_rd(PHYCFGR);\n }\n\n\n/////////////////////////////////////\n\n///////////////////////////////////\n// Socket N register I/O function //\n///////////////////////////////////\n/**\n * @ingroup Socket_register_access_function\n * @brief Set @ref Sn_MR register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @param (uint8_t)mr Value to set @ref Sn_MR\n * @sa getSn_MR()\n */\n void setSn_MR(uint8_t sn, uint8_t mr) {\n sreg(sn, MR, mr);\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Get @ref Sn_MR register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @return uint8_t. Value of @ref Sn_MR.\n * @sa setSn_MR()\n */\n uint8_t getSn_MR(uint8_t sn) {\n return sreg(sn, Sn_MR);\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Set @ref Sn_CR register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @param (uint8_t)cr Value to set @ref Sn_CR\n * @sa getSn_CR()\n */\n void setSn_CR(uint8_t sn, uint8_t cr) {\n sreg(sn, Sn_CR, cr);\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Get @ref Sn_CR register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @return uint8_t. Value of @ref Sn_CR.\n * @sa setSn_CR()\n */\n uint8_t getSn_CR(uint8_t sn) {\n return sreg(sn, Sn_CR);\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Set @ref Sn_IR register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @param (uint8_t)ir Value to set @ref Sn_IR\n * @sa getSn_IR()\n */\n void setSn_IR(uint8_t sn, uint8_t ir) { \n sreg(sn, Sn_IR, (ir & 0x1F));\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Get @ref Sn_IR register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @return uint8_t. Value of @ref Sn_IR.\n * @sa setSn_IR()\n */\n uint8_t getSn_IR(uint8_t sn) {\n return (sreg(sn, Sn_IR)) & 0x1F;\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Set @ref Sn_IMR register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @param (uint8_t)imr Value to set @ref Sn_IMR\n * @sa getSn_IMR()\n */\n void setSn_IMR(uint8_t sn, uint8_t imr) {\n sreg(sn, Sn_IMR, (imr & 0x1F));\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Get @ref Sn_IMR register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @return uint8_t. Value of @ref Sn_IMR.\n * @sa setSn_IMR()\n */\n uint8_t getSn_IMR(uint8_t sn) {\n return (sreg(sn, Sn_IMR)) & 0x1F;\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Get @ref Sn_SR register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @return uint8_t. Value of @ref Sn_SR.\n */\n uint8_t getSn_SR(uint8_t sn) {\n return sreg(sn, Sn_SR);\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Set @ref Sn_PORT register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @param (uint16_t)port Value to set @ref Sn_PORT.\n * @sa getSn_PORT()\n */\n void setSn_PORT(uint8_t sn, uint16_t port) { \n sreg(sn, Sn_PORT, port );\n } \n\n/**\n * @ingroup Socket_register_access_function\n * @brief Get @ref Sn_PORT register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @return uint16_t. Value of @ref Sn_PORT.\n * @sa setSn_PORT()\n */\n uint16_t getSn_PORT(uint8_t sn) {\n return sreg(sn, Sn_PORT);\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Set @ref Sn_DHAR register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @param (uint8_t*)dhar Pointer variable to set socket n destination hardware address. It should be allocated 6 bytes.\n * @sa getSn_DHAR()\n */\n void setSn_DHAR(uint8_t sn, uint8_t * dhar) {\n spi_write(Sn_DHAR, (0x0C + (sn << 5)), dhar, 6);\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Get @ref Sn_MR register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @param (uint8_t*)dhar Pointer variable to get socket n destination hardware address. It should be allocated 6 bytes.\n * @sa setSn_DHAR()\n */\n void getSn_DHAR(uint8_t sn, uint8_t * dhar) {\n spi_read(Sn_DHAR, (0x08 + (sn << 5)), dhar, 6);\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Set @ref Sn_DIPR register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @param (uint8_t*)dipr Pointer variable to set socket n destination IP address. It should be allocated 4 bytes.\n * @sa getSn_DIPR()\n */\n void setSn_DIPR(uint8_t sn, uint8_t * dipr) {\n spi_write(Sn_DIPR, (0x0C + (sn << 5)), dipr, 4);\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Get @ref Sn_DIPR register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @param (uint8_t*)dipr Pointer variable to get socket n destination IP address. It should be allocated 4 bytes.\n * @sa SetSn_DIPR()\n */\n void getSn_DIPR(uint8_t sn, uint8_t * dipr) {\n spi_read(Sn_DIPR, (0x08 + (sn << 5)), dipr, 4);\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Set @ref Sn_DPORT register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @param (uint16_t)dport Value to set @ref Sn_DPORT\n * @sa getSn_DPORT()\n */\n void setSn_DPORT(uint8_t sn, uint16_t dport) { \n sreg(sn, Sn_DPORT, dport);\n } \n\n/**\n * @ingroup Socket_register_access_function\n * @brief Get @ref Sn_DPORT register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @return uint16_t. Value of @ref Sn_DPORT.\n * @sa setSn_DPORT()\n */\n uint16_t getSn_DPORT(uint8_t sn) {\n return sreg(sn, Sn_DPORT);\n }\n\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Set @ref Sn_RXBUF_SIZE register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @param (uint8_t)rxbufsize Value to set @ref Sn_RXBUF_SIZE\n * @sa getSn_RXBUF_SIZE()\n */\n void setSn_RXBUF_SIZE(uint8_t sn, uint8_t rxbufsize) {\n sreg(sn, Sn_RXBUF_SIZE ,rxbufsize);\n }\n\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Get @ref Sn_RXBUF_SIZE register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @return uint8_t. Value of @ref Sn_RXBUF_SIZE.\n * @sa setSn_RXBUF_SIZE()\n */\n uint8_t getSn_RXBUF_SIZE(uint8_t sn) {\n return sreg(sn, Sn_RXBUF_SIZE);\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Set @ref Sn_TXBUF_SIZE register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @param (uint8_t)txbufsize Value to set @ref Sn_TXBUF_SIZE\n * @sa getSn_TXBUF_SIZE()\n */\n void setSn_TXBUF_SIZE(uint8_t sn, uint8_t txbufsize) {\n sreg(sn, Sn_TXBUF_SIZE, txbufsize);\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Get @ref Sn_TXBUF_SIZE register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @return uint8_t. Value of @ref Sn_TXBUF_SIZE.\n * @sa setSn_TXBUF_SIZE()\n */\n uint8_t getSn_TXBUF_SIZE(uint8_t sn) {\n return sreg(sn, Sn_TXBUF_SIZE);\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Get @ref Sn_TX_FSR register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @return uint16_t. Value of @ref Sn_TX_FSR.\n */\n uint16_t getSn_TX_FSR(uint8_t sn) {\n return sreg(sn, Sn_TX_FSR);\n }\n\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Get @ref Sn_TX_RD register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @return uint16_t. Value of @ref Sn_TX_RD.\n */\n uint16_t getSn_TX_RD(uint8_t sn) {\n return sreg(sn, Sn_TX_RD);\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Set @ref Sn_TX_WR register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @param (uint16_t)txwr Value to set @ref Sn_TX_WR\n * @sa GetSn_TX_WR()\n */\n void setSn_TX_WR(uint8_t sn, uint16_t txwr) { \n sreg(sn, Sn_TX_WR, txwr); \n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Get @ref Sn_TX_WR register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @return uint16_t. Value of @ref Sn_TX_WR.\n * @sa setSn_TX_WR()\n */\n uint16_t getSn_TX_WR(uint8_t sn) {\n return sreg(sn, Sn_TX_WR);\n }\n\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Get @ref Sn_RX_RSR register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @return uint16_t. Value of @ref Sn_RX_RSR.\n */\n uint16_t getSn_RX_RSR(uint8_t sn) {\n return sreg(sn, Sn_RX_RSR);\n }\n\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Set @ref Sn_RX_RD register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @param (uint16_t)rxrd Value to set @ref Sn_RX_RD\n * @sa getSn_RX_RD()\n */\n void setSn_RX_RD(uint8_t sn, uint16_t rxrd) { \n sreg(sn, Sn_RX_RD, rxrd); \n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Get @ref Sn_RX_RD register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @regurn uint16_t. Value of @ref Sn_RX_RD.\n * @sa setSn_RX_RD()\n */\n uint16_t getSn_RX_RD(uint8_t sn) {\n return sreg(sn, Sn_RX_RD);\n }\n\n/**\n * @ingroup Socket_register_access_function\n * @brief Get @ref Sn_RX_WR register\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @return uint16_t. Value of @ref Sn_RX_WR.\n */\n uint16_t getSn_RX_WR(uint8_t sn) { \n return sreg(sn, Sn_RX_WR);\n }\n\n\n//////////////////////////////////////\n\n/////////////////////////////////////\n// Sn_TXBUF & Sn_RXBUF IO function //\n/////////////////////////////////////\n/** \n * @brief Gets the max buffer size of socket sn passed as parameter.\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @return uint16_t. Value of Socket n RX max buffer size.\n */\n uint16_t getSn_RxMAX(uint8_t sn) {\n return (getSn_RXBUF_SIZE(sn) << 10);\n }\n\n/** \n * @brief Gets the max buffer size of socket sn passed as parameters.\n * @param (uint8_t)sn Socket number. It should be 0 ~ 7.\n * @return uint16_t. Value of Socket n TX max buffer size.\n */\n//uint16_t getSn_TxMAX(uint8_t sn);\n uint16_t getSn_TxMAX(uint8_t sn) {\n return (getSn_TXBUF_SIZE(sn) << 10);\n }\n\n\n int ethernet_link(void);\n void ethernet_set_link(int speed, int duplex);\nprotected:\n uint8_t mac[6];\n uint32_t ip;\n uint32_t netmask;\n uint32_t gateway;\n uint32_t dnsaddr;\n bool dhcp;\n \n void spi_write(uint16_t addr, uint8_t cb, const uint8_t *buf, uint16_t len);\n void spi_read(uint16_t addr, uint8_t cb, uint8_t *buf, uint16_t len);\n SPI* spi;\n DigitalOut cs;\n DigitalOut reset_pin;\n static WIZnet_Chip* inst;\n\n void reg_wr_mac(uint16_t addr, uint8_t* data) {\n spi_write(addr, 0x04, data, 6);\n }\n\n};\n\n\nextern uint32_t str_to_ip(const char* str);\nextern void printfBytes(char* str, uint8_t* buf, int len);\nextern void printHex(uint8_t* buf, int len);\nextern void debug_hex(uint8_t* buf, int len);\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/arch/int/W7500x_toe.cpp", "content": "/* Copyright (C) 2012 mbed.org, MIT License\n *\n * and associated documentation files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge, publish, distribute,\n * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all copies or\n * substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING\n * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,\n * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n */\n#include \"eth_arch.h\"\n#if defined(TARGET_WIZwiki_W7500) || defined(TARGET_WIZwiki_W7500P) || defined(TARGET_WIZwiki_W7500ECO)\n\n\n#include \"mbed.h\"\n#include \"mbed_debug.h\"\n#include \"DNSClient.h\"\n\n\n/*\n * MDIO via GPIO\n * mdio via gpio is supported and related functions as follows.\n * - mdio_init(),mdio_read(),mdio_write()\n * - input_MDIO(),output_MDIO(),turnaroud_MDIO(),idle_MDIO()\n * called by ethernet_link() and ethernet_set_link()\n */\n \n#if defined (TARGET_WIZwiki_W7500) || defined(TARGET_WIZwiki_W7500ECO)\n\n#define MDIO GPIO_Pin_14\n#define MDC GPIO_Pin_15\n#define GPIO_MDC GPIOB\n#define PHY_ADDR_IP101G 0x07 \n#define PHY_ADDR PHY_ADDR_IP101G\n#define SVAL 0x2 //right shift val = 2 \n#define PHYREG_CONTROL 0x0 //Control Register address (Contorl basic register)\n#define PHYREG_STATUS 0x1 //Status Register address (Status basic register)\n#define CNTL_DUPLEX (0x01ul<< 7)\n#define CNTL_AUTONEGO (0x01ul<<11)\n#define CNTL_SPEED (0x01ul<<12)\n#define MDC_WAIT (1)\n\n#elif defined (TARGET_WIZwiki_W7500P) \n\n#define MDIO GPIO_Pin_15\n#define MDC GPIO_Pin_14\n#define GPIO_MDC GPIOB\n#define PHY_ADDR_IP101G 0x01 \n#define PHY_ADDR PHY_ADDR_IP101G\n#define SVAL 0x2 //right shift val = 2 \n#define PHYREG_CONTROL 0x0 //Control Register address (Contorl basic register)\n#define PHYREG_STATUS 0x1 //Status Register address (Status basic register)\n#define CNTL_DUPLEX (0x01ul<< 8)\n#define CNTL_AUTONEGO (0x01ul<<12)\n#define CNTL_SPEED (0x01ul<<13)\n#define MDC_WAIT (1)\n\n#endif\n\nvoid mdio_init(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin_MDC, uint16_t GPIO_Pin_MDIO);\nvoid mdio_write(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr, uint32_t val);\nuint32_t mdio_read(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr);\n\nWIZnet_Chip* WIZnet_Chip::inst;\n\nWIZnet_Chip::WIZnet_Chip()\n{\n inst = this;\n}\n\nbool WIZnet_Chip::setmac()\n{\n reg_wr_mac(SHAR, mac);\n return true;\n}\n\n// Set the IP\nbool WIZnet_Chip::setip()\n{\n reg_wr(SIPR, ip);\n reg_wr(GAR, gateway);\n reg_wr(SUBR, netmask);\n return true;\n}\n\nbool WIZnet_Chip::setProtocol(int socket, Protocol p)\n{\n if (socket < 0) {\n return false;\n }\n sreg(socket, Sn_MR, p);\n return true;\n}\n\nbool WIZnet_Chip::connect(int socket, const char * host, int port, int timeout_ms)\n{\n if (socket < 0) {\n return false;\n }\n sreg(socket, Sn_MR, TCP);\n scmd(socket, OPEN);\n sreg_ip(socket, Sn_DIPR, host);\n sreg(socket, Sn_DPORT, port);\n sreg(socket, Sn_PORT, new_port());\n scmd(socket, CONNECT);\n Timer t;\n t.reset();\n t.start();\n while(!is_connected(socket)) {\n if (t.read_ms() > timeout_ms) {\n return false;\n }\n }\n return true;\n}\n\nbool WIZnet_Chip::gethostbyname(const char* host, uint32_t* ip)\n{\n uint32_t addr = str_to_ip(host);\n char buf[17];\n snprintf(buf, sizeof(buf), \"%d.%d.%d.%d\", \n (uint8_t)((addr>>24)&0xff), \n (uint8_t)((addr>>16)&0xff), \n (uint8_t)((addr>>8)&0xff), \n (uint8_t)(addr&0xff));\n if (strcmp(buf, host) == 0) {\n *ip = addr;\n return true;\n }\n DNSClient client;\n if(client.lookup(host)) {\n *ip = client.ip;\n return true;\n }\n return false;\n}\n\n\nbool WIZnet_Chip::is_connected(int socket)\n{\n /*\n if (sreg(socket, Sn_SR) == SOCK_ESTABLISHED) {\n return true;\n }\n */\n uint8_t tmpSn_SR;\n tmpSn_SR = sreg(socket, Sn_SR);\n // packet sending is possible, when state is SOCK_CLOSE_WAIT.\n if ((tmpSn_SR == SOCK_ESTABLISHED) || (tmpSn_SR == SOCK_CLOSE_WAIT)) {\n return true;\n }\n return false;\n}\n// Reset the chip & set the buffer\nvoid WIZnet_Chip::reset()\n{\n /* S/W Reset PHY */\n mdio_write(GPIO_MDC, PHYREG_CONTROL, 0x8000);\n wait_ms(10);//for S/W reset\n wait_ms(10);//for MDC I/F RDY\n\n mdio_init(GPIO_MDC, MDC, MDIO);\n \n /* S/W Reset WZTOE */\n reg_wr(MR, MR_RST);\n // set PAD strengh and pull-up for TXD[3:0] and TXE \n#ifdef __DEF_USED_IC101AG__ //For using IC+101AG\n\n#if defined(TARGET_WIZwiki_W7500) || defined(TARGET_WIZwiki_W7500ECO)\n\n *(volatile uint32_t *)(0x41003068) = 0x64; //TXD0 \n *(volatile uint32_t *)(0x4100306C) = 0x64; //TXD1\n *(volatile uint32_t *)(0x41003070) = 0x64; //TXD2\n *(volatile uint32_t *)(0x41003074) = 0x64; //TXD3\n *(volatile uint32_t *)(0x41003050) = 0x64; //TXE\n#endif\n\n#endif \n\n // set ticker counter\n reg_wr(TIC100US, (SystemCoreClock/10000));\n // write MAC address inside the WZTOE MAC address register\n reg_wr_mac(SHAR, mac);\n /*\n * set RX and TX buffer size\n * for (int socket = 0; socket < MAX_SOCK_NUM; socket++) {\n * sreg(socket, Sn_RXBUF_SIZE, 2);\n * sreg(socket, Sn_TXBUF_SIZE, 2);\n * }\n */\n}\n\n\nbool WIZnet_Chip::close(int socket)\n{\n if (socket < 0) {\n return false;\n }\n // if SOCK_CLOSED, return\n if (sreg(socket, Sn_SR) == SOCK_CLOSED) {\n return true;\n }\n // if SOCK_ESTABLISHED, send FIN-Packet to peer \n if (sreg(socket, Sn_MR) == TCP) {\n scmd(socket, DISCON);\n }\n // close socket\n scmd(socket, CLOSE);\n // clear Socket Interrupt Register\n sreg(socket, Sn_ICR, 0xff);\n return true;\n}\n\nint WIZnet_Chip::wait_readable(int socket, int wait_time_ms, int req_size)\n{\n if (socket < 0) {\n return -1;\n }\n Timer t;\n t.reset();\n t.start();\n while(1) {\n int size = sreg(socket, Sn_RX_RSR);\n if (size > req_size) {\n return size;\n }\n if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {\n break;\n }\n }\n return -1;\n}\n\nint WIZnet_Chip::wait_writeable(int socket, int wait_time_ms, int req_size)\n{\n if (socket < 0) {\n return -1;\n }\n Timer t;\n t.reset();\n t.start();\n while(1) {\n int size = sreg(socket, Sn_TX_FSR);\n if (size > req_size) {\n return size;\n }\n if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {\n break;\n }\n }\n return -1;\n}\n\nint WIZnet_Chip::send(int socket, const char * str, int len)\n{\n if (socket < 0) {\n return -1;\n }\n\n uint16_t ptr = sreg(socket, Sn_TX_WR);\n uint32_t sn_tx_base = W7500x_TXMEM_BASE + (uint32_t)(socket<<18); \n\n for(int i=0; i(socket, Sn_TX_WR, ptr + len);\n scmd(socket, SEND);\n\n uint8_t tmp_Sn_IR;\n while (( (tmp_Sn_IR = sreg(socket, Sn_IR)) & INT_SEND_OK) != INT_SEND_OK) {\n // @Jul.10, 2014 fix contant name, and udp sendto function.\n switch (sreg(socket, Sn_SR)) {\n case SOCK_CLOSED :\n close(socket);\n return 0;\n //break;\n case SOCK_UDP :\n // ARP timeout is possible.\n if ((tmp_Sn_IR & INT_TIMEOUT) == INT_TIMEOUT) {\n sreg(socket, Sn_ICR, INT_TIMEOUT);\n return 0;\n }\n break;\n default :\n break;\n }\n }\n\n sreg(socket, Sn_ICR, INT_SEND_OK);\n\n return len;\n}\n\nint WIZnet_Chip::recv(int socket, char* buf, int len)\n{\n if (socket < 0) {\n return -1;\n }\n uint16_t ptr = sreg(socket, Sn_RX_RD);\n uint32_t sn_rx_base = W7500x_RXMEM_BASE + (uint32_t)(socket<<18); \n\n for(int i=0; i(socket, Sn_RX_RD, ptr + len);\n scmd(socket, RECV);\n\n return len;\n}\n\nint WIZnet_Chip::new_socket()\n{\n for(int s = 0; s < MAX_SOCK_NUM; s++) {\n if (sreg(s, Sn_SR) == SOCK_CLOSED) {\n return s;\n }\n }\n return -1;\n}\n\nuint16_t WIZnet_Chip::new_port()\n{\n uint16_t port = rand();\n port |= 49152;\n return port;\n}\n\nbool WIZnet_Chip::link(int wait_time_ms)\n{\n Timer t;\n t.reset();\n t.start();\n while(1) {\n int is_link = ethernet_link();\n \n if (is_link) {\n return true;\n }\n if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {\n break;\n }\n }\n return 0;\n}\n\nvoid WIZnet_Chip::set_link(PHYMode phymode)\n{\n int speed = -1;\n int duplex = 0;\n\n switch(phymode) {\n case AutoNegotiate : speed = -1; duplex = 0; break;\n case HalfDuplex10 : speed = 0; duplex = 0; break;\n case FullDuplex10 : speed = 0; duplex = 1; break;\n case HalfDuplex100 : speed = 1; duplex = 0; break;\n case FullDuplex100 : speed = 1; duplex = 1; break;\n }\n\n ethernet_set_link(speed, duplex);\n}\n\nuint32_t str_to_ip(const char* str)\n{\n uint32_t ip = 0;\n char* p = (char*)str;\n for(int i = 0; i < 4; i++) {\n ip |= atoi(p);\n p = strchr(p, '.');\n if (p == NULL) {\n break;\n }\n ip <<= 8;\n p++;\n }\n return ip;\n}\n\nvoid printfBytes(char* str, uint8_t* buf, int len)\n{\n printf(\"%s %d:\", str, len);\n for(int i = 0; i < len; i++) {\n printf(\" %02x\", buf[i]);\n }\n printf(\"\\n\");\n}\n\nvoid printHex(uint8_t* buf, int len)\n{\n for(int i = 0; i < len; i++) {\n if ((i%16) == 0) {\n printf(\"%p\", buf+i);\n }\n printf(\" %02x\", buf[i]);\n if ((i%16) == 15) {\n printf(\"\\n\");\n }\n }\n printf(\"\\n\");\n}\n\nvoid debug_hex(uint8_t* buf, int len)\n{\n for(int i = 0; i < len; i++) {\n if ((i%16) == 0) {\n debug(\"%p\", buf+i);\n }\n debug(\" %02x\", buf[i]);\n if ((i%16) == 15) {\n debug(\"\\n\");\n }\n }\n debug(\"\\n\");\n}\n\nvoid WIZnet_Chip::scmd(int socket, Command cmd)\n{\n sreg(socket, Sn_CR, cmd);\n while(sreg(socket, Sn_CR));\n}\n\n\nvoid mdio_init(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin_MDC, uint16_t GPIO_Pin_MDIO)\n{\n /* Set GPIOs for MDIO and MDC */\n GPIO_InitTypeDef MDIO_InitDef; \n HAL_PAD_AFConfig(PAD_PB, GPIO_Pin_MDIO, PAD_AF1); \n HAL_PAD_AFConfig(PAD_PB, GPIO_Pin_MDC, PAD_AF1); \n MDIO_InitDef.GPIO_Pin = GPIO_Pin_MDC | GPIO_Pin_MDIO;\n MDIO_InitDef.GPIO_Mode = GPIO_Mode_OUT;\n HAL_GPIO_Init(GPIOx, &MDIO_InitDef);\n}\n\nvoid output_MDIO(GPIO_TypeDef* GPIOx, uint32_t val, uint32_t n)\n{\n for(val <<= (32-n); n; val<<=1, n--)\n {\n if(val & 0x80000000)\n HAL_GPIO_SetBits(GPIOx, MDIO); \n else\n HAL_GPIO_ResetBits(GPIOx, MDIO);\n\n wait_ms(MDC_WAIT);\n HAL_GPIO_SetBits(GPIOx, MDC); \n wait_ms(MDC_WAIT);\n HAL_GPIO_ResetBits(GPIOx, MDC);\n }\n}\n\nuint32_t input_MDIO( GPIO_TypeDef* GPIOx )\n{\n uint32_t i, val=0; \n for(i=0; i<16; i++)\n {\n val <<=1;\n HAL_GPIO_SetBits(GPIOx, MDC); \n wait_ms(MDC_WAIT);\n HAL_GPIO_ResetBits(GPIOx, MDC);\n wait_ms(MDC_WAIT);\n val |= HAL_GPIO_ReadInputDataBit(GPIOx, MDIO);\n }\n return (val);\n}\n\nvoid turnaround_MDIO( GPIO_TypeDef* GPIOx)\n{\n GPIOx->OUTENCLR = MDIO ;\n HAL_GPIO_SetBits(GPIOx, MDC); \n wait_ms(MDC_WAIT);\n HAL_GPIO_ResetBits(GPIOx, MDC);\n wait_ms(MDC_WAIT);\n}\n\nvoid idle_MDIO( GPIO_TypeDef* GPIOx )\n{\n GPIOx->OUTENSET = MDIO ;\n HAL_GPIO_SetBits(GPIOx,MDC); \n wait_ms(MDC_WAIT);\n HAL_GPIO_ResetBits(GPIOx, MDC);\n wait_ms(MDC_WAIT);\n}\n\nuint32_t mdio_read(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr)\n{\n output_MDIO(GPIOx, 0xFFFFFFFF, 32);\n output_MDIO(GPIOx, 0x06, 4);\n output_MDIO(GPIOx, PHY_ADDR, 5);\n output_MDIO(GPIOx, PhyRegAddr, 5);\n turnaround_MDIO(GPIOx);\n uint32_t val = input_MDIO(GPIOx );\n idle_MDIO(GPIOx);\n return val;\n}\n\nvoid mdio_write(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr, uint32_t val)\n{\n output_MDIO(GPIOx, 0xFFFFFFFF, 32);\n output_MDIO(GPIOx, 0x05, 4);\n output_MDIO(GPIOx, PHY_ADDR, 5);\n output_MDIO(GPIOx, PhyRegAddr, 5);\n output_MDIO(GPIOx, 0x02, 2);\n output_MDIO(GPIOx, val, 16);\n idle_MDIO(GPIOx);\n}\n\nint WIZnet_Chip::ethernet_link(void) {\n return ((mdio_read(GPIO_MDC, PHYREG_STATUS)>>SVAL)&0x01); \n}\n\nvoid WIZnet_Chip::ethernet_set_link(int speed, int duplex) {\n uint32_t val=0;\n if((speed < 0) || (speed > 1)) {\n val = CNTL_AUTONEGO; \n } else {\n val = ((CNTL_SPEED&(speed<<11))|(CNTL_DUPLEX&(duplex<<7))); \n }\n mdio_write(GPIO_MDC, PHYREG_CONTROL, val);\n}\n\n void WIZnet_Chip::reg_rd_mac(uint16_t addr, uint8_t* data) \n {\n data[0] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+3));\n data[1] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+2));\n data[2] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+1));\n data[3] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+0));\n data[4] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+7));\n data[5] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+6));\n }\n\n void WIZnet_Chip::reg_wr_ip(uint16_t addr, uint8_t cb, const char* ip)\n {\n uint8_t buf[4]={0,};\n uint32_t wr_ip = 0;\n char* p = (char*)ip;\n \n for(int i = 0; i < 4; i++) {\n wr_ip = (wr_ip<<8);\n buf[i] = atoi(p);\n wr_ip |= buf[i];\n p = strchr(p, '.');\n if (p == NULL) break;\n p++;\n }\n *(volatile uint32_t *)(W7500x_WZTOE_BASE + (uint32_t)((cb<<16)+addr)) = wr_ip;\n }\n\n void WIZnet_Chip::sreg_ip(int socket, uint16_t addr, const char* ip) {\n reg_wr_ip(addr, (uint8_t)(0x01+(socket<<2)), ip);\n }\n\n#endif\n\n\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/arch/int/W7500x_toe.h", "content": "/* Copyright (C) 2012 mbed.org, MIT License\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of this software\n * and associated documentation files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge, publish, distribute,\n * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all copies or\n * substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING\n * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,\n * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n */\n#pragma once\n\n#include \"mbed.h\"\n#include \"mbed_debug.h\"\n\n#define TEST_ASSERT(A) while(!(A)){debug(\"\\n\\n%s@%d %s ASSERT!\\n\\n\",__PRETTY_FUNCTION__,__LINE__,#A);exit(1);};\n\n#define DEFAULT_WAIT_RESP_TIMEOUT 500\n\n\n#define MAX_SOCK_NUM 8\n\n// Peripheral base address \n#define W7500x_WZTOE_BASE (0x46000000)\n#define W7500x_TXMEM_BASE (W7500x_WZTOE_BASE + 0x00020000)\n#define W7500x_RXMEM_BASE (W7500x_WZTOE_BASE + 0x00030000)\n// Common register\n#define MR (0x2300)\n#define GAR (0x6008)\n#define SUBR (0x600C)\n#define SHAR (0x6000)\n#define SIPR (0x6010)\n\n// Added Common register @W7500\n#define TIC100US (0x2000) \n\n// Socket register\n#define Sn_MR (0x0000)\n#define Sn_CR (0x0010)\n#define Sn_IR (0x0020) //--Sn_ISR\n#define Sn_SR (0x0030)\n#define Sn_PORT (0x0114)\n#define Sn_DIPR (0x0124)\n#define Sn_DPORT (0x0120)\n#define Sn_RXBUF_SIZE (0x0200)\n#define Sn_TXBUF_SIZE (0x0220)\n#define Sn_TX_FSR (0x0204)\n#define Sn_TX_WR (0x020C)\n#define Sn_RX_RSR (0x0224)\n#define Sn_RX_RD (0x0228)\n// added Socket register @W7500\n#define Sn_ICR (0x0028)\nenum PHYMode {\n AutoNegotiate = 0,\n HalfDuplex10 = 1,\n FullDuplex10 = 2,\n HalfDuplex100 = 3,\n FullDuplex100 = 4,\n};\n\n//bool plink(int wait_time_ms= 3*1000);\n\nclass WIZnet_Chip {\npublic:\nenum Protocol {\n CLOSED = 0,\n TCP = 1,\n UDP = 2,\n};\n\nenum Command {\n OPEN = 0x01,\n LISTEN = 0x02,\n CONNECT = 0x04,\n DISCON = 0x08,\n CLOSE = 0x10,\n SEND = 0x20,\n SEND_MAC = 0x21, \n SEND_KEEP = 0x22,\n RECV = 0x40,\n \n};\n\nenum Interrupt {\n INT_CON = 0x01,\n INT_DISCON = 0x02,\n INT_RECV = 0x04,\n INT_TIMEOUT = 0x08,\n INT_SEND_OK = 0x10,\n};\nenum Status {\n SOCK_CLOSED = 0x00,\n SOCK_INIT = 0x13,\n SOCK_LISTEN = 0x14,\n SOCK_SYNSENT = 0x15,\n SOCK_ESTABLISHED = 0x17,\n SOCK_CLOSE_WAIT = 0x1c,\n SOCK_UDP = 0x22,\n};\nenum Mode {\n MR_RST = 0x80, \n MR_WOL = 0x20, \n MR_PB = 0x10, \n MR_FARP = 0x02, \n};\n\n WIZnet_Chip();\n\n /*\n * Set MAC Address to W7500x_TOE\n *\n * @return true if connected, false otherwise\n */ \n bool setmac();\n\n /*\n * Connect the W7500 WZTOE to the ssid contained in the constructor.\n *\n * @return true if connected, false otherwise\n */ \n bool setip();\n\n\n /*\n * Open a tcp connection with the specified host on the specified port\n *\n * @param host host (can be either an ip address or a name. If a name is provided, a dns request will be established)\n * @param port port\n * @ returns true if successful\n */\n bool connect(int socket, const char * host, int port, int timeout_ms = 10*1000);\n\n /*\n * Set the protocol (UDP or TCP)\n *\n * @param p protocol\n * @ returns true if successful\n */\n bool setProtocol(int socket, Protocol p);\n\n /*\n * Reset the W7500 WZTOE\n */\n void reset();\n \n int wait_readable(int socket, int wait_time_ms, int req_size = 0);\n\n int wait_writeable(int socket, int wait_time_ms, int req_size = 0);\n\n /*\n * Check if an ethernet link is pressent or not.\n *\n * @returns true if successful\n */\n bool link(int wait_time_ms= 3*1000);\n\n /*\n * Sets the speed and duplex parameters of an ethernet link.\n *\n * @returns true if successful\n */\n void set_link(PHYMode phymode);\n\n /*\n * Check if a tcp link is active\n *\n * @returns true if successful\n */\n bool is_connected(int socket);\n\n /*\n * Close a tcp connection\n *\n * @ returns true if successful\n */\n bool close(int socket);\n\n /*\n * @param str string to be sent\n * @param len string length\n */\n int send(int socket, const char * str, int len);\n\n int recv(int socket, char* buf, int len);\n\n /*\n * Return true if the module is using dhcp\n *\n * @returns true if the module is using dhcp\n */\n bool isDHCP() {\n return dhcp;\n }\n\n bool gethostbyname(const char* host, uint32_t* ip);\n\n static WIZnet_Chip * getInstance() {\n return inst;\n };\n\n int new_socket();\n uint16_t new_port();\n\n void scmd(int socket, Command cmd);\n\n template\n void sreg(int socket, uint16_t addr, T data) {\n reg_wr(addr, (uint8_t)(0x01+(socket<<2)), data);\n }\n\n template\n T sreg(int socket, uint16_t addr) {\n return reg_rd(addr, (uint8_t)(0x01+(socket<<2)));\n }\n\n template\n void reg_wr(uint16_t addr, T data) {\n return reg_wr(addr, 0x00, data);\n }\n \n template\n void reg_wr(uint16_t addr, uint8_t cb, T data) {\n uint8_t buf[sizeof(T)];\n *reinterpret_cast(buf) = data;\n /*\n for(int i = 0; i < sizeof(buf)/2; i++) { // Little Endian to Big Endian\n uint8_t t = buf[i];\n buf[i] = buf[sizeof(buf)-1-i];\n buf[sizeof(buf)-1-i] = t;\n }\n */\n for(int i = 0; i < sizeof(buf); i++) { // Little Endian to Big Endian\n *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)((cb<<16)+addr)+i) = buf[i];\n }\n }\n\n template\n T reg_rd(uint16_t addr) {\n return reg_rd(addr, (uint8_t)(0x00));\n }\n\n template\n T reg_rd(uint16_t addr, uint8_t cb) {\n uint8_t buf[sizeof(T)] = {0,};\n for(int i = 0; i < sizeof(buf); i++) { // Little Endian to Big Endian\n buf[i] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)((cb<<16)+addr)+i);\n }\n /*\n for(int i = 0; i < sizeof(buf)/2; i++) { // Big Endian to Little Endian\n uint8_t t = buf[i];\n buf[i] = buf[sizeof(buf)-1-i];\n buf[sizeof(buf)-1-i] = t;\n }\n */\n return *reinterpret_cast(buf);\n }\n\n void reg_rd_mac(uint16_t addr, uint8_t* data);\n \n void reg_wr_ip(uint16_t addr, uint8_t cb, const char* ip);\n\n void sreg_ip(int socket, uint16_t addr, const char* ip);\n\n int ethernet_link(void);\n \n void ethernet_set_link(int speed, int duplex);\n\n\nprotected:\n uint8_t mac[6];\n uint32_t ip;\n uint32_t netmask;\n uint32_t gateway;\n uint32_t dnsaddr;\n bool dhcp;\n\n static WIZnet_Chip* inst;\n\n void reg_wr_mac(uint16_t addr, uint8_t* data) {\n *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+3)) = data[0] ;\n *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+2)) = data[1] ;\n *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+1)) = data[2] ;\n *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+0)) = data[3] ;\n *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+7)) = data[4] ;\n *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+6)) = data[5] ;\n }\n};\n\nextern uint32_t str_to_ip(const char* str);\nextern void printfBytes(char* str, uint8_t* buf, int len);\nextern void printHex(uint8_t* buf, int len);\nextern void debug_hex(uint8_t* buf, int len);\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5/eth_arch.h", "content": "/* Copyright (C) 2012 mbed.org, MIT License\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of this software\n * and associated documentation files (the \"Software\"), to deal in the Software without restriction,\n * including without limitation the rights to use, copy, modify, merge, publish, distribute,\n * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is\n * furnished to do so, subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all copies or\n * substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING\n * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,\n * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n */\n\n#pragma once\n\n#if defined(TARGET_WIZwiki_W7500) || defined(TARGET_WIZwiki_W7500ECO)\n\n#include \"W7500x_toe.h\"\n#define __DEF_USED_IC101AG__ //For using IC+101AG@WIZwiki-W7500\n\n#elif defined(TARGET_WIZwiki_W7500P)\n\n#include \"W7500x_toe.h\"\n\n#else\n#include \"W5500.h\" // W5500 Ethernet Shield \n//#define USE_WIZ550IO_MAC // WIZ550io; using the MAC address\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/WIZnetInterface-OS5.lib", "content": "http://os.mbed.com/teams/WIZnet/code/WIZnetInterface-OS5/#d4c8fe4d9b29d4e5614620b0820a49d31087b512" }, { "path": "Firmware/FirmwareSource/Remora-OS5/configuration.h", "content": "#ifndef CONFIGURATION_H\n#define CONFIGURATION_H\n\n#define PRU_BASEFREQ \t40000 //24000 // PRU Base thread ISR update frequency (hz)\n#define PRU_SERVOFREQ 1000 // PRU Servo thread ISR update freqency (hz)\n#define OVERSAMPLE 3\n#define SWBAUDRATE 19200 // Software serial baud rate\n#define PRU_COMMSFREQ (SWBAUDRATE * OVERSAMPLE)\n\n#define STEPBIT \t\t22 \t// bit location in DDS accum\n#define STEP_MASK \t\t (1L<\n\n#define confine(value, min, max) (((value) < (min))?(min):(((value) > (max))?(max):(value)))\n#define PID_PWM_MAX 256\t\t// 8 bit resolution\n\nusing namespace std;\n\nSoftPWM::SoftPWM(std::string pin) :\n\tpin(pin),\n\tpwmMax(PID_PWM_MAX-1),\n\tpwmSP(0),\n\tSDaccumulator(0),\n\tSDdirection(false)\n{\n\tthis->pwmPin = new Pin(this->pin, OUTPUT);\n}\n\n\nvoid SoftPWM::setMaxPwm(int pwmMax)\n{\n\tthis->pwmMax = confine(pwmMax, 0, PID_PWM_MAX-1);\n}\n\n\nvoid SoftPWM::setPwmSP(int newPwmSP)\n{\n\tthis->pwmSP = newPwmSP; //confine(newPwmSP, 0, pwmMax);\n}\n\n\nvoid SoftPWM::update()\n{\n\t// Use the standard Moudle interface\n\n\tif ((this->pwmSP < 0) || this->pwmSP >= PID_PWM_MAX)\n\t{\n return;\n }\n else if (this->pwmSP == 0)\n\t{\n\t\tthis->pwmPin->set(false);\n return;\n }\n else if (this->pwmSP == PID_PWM_MAX-1)\n\t{\n\t\tthis->pwmPin->set(true);\n return;\n }\n\n\n // this line should never actually do anything, it's just a sanity check in case our accumulator gets corrupted somehow.\n // If we didn't check and the accumulator is corrupted, we could leave a heater on for quite a long time\n // the accumulator is kept within these limits by the normal operation of the Sigma-Delta algorithm\n\n SDaccumulator = confine(SDaccumulator, -PID_PWM_MAX, PID_PWM_MAX << 1);\n\n // when SDdirection == false, our output is 0 and our accumulator is increasing by pwmSP\n if (this->SDdirection == false)\n {\n // increment accumulator\n this->SDaccumulator += this->pwmSP;\n // if we've reached half of max, flip our direction\n if (this->SDaccumulator >= (PID_PWM_MAX >> 1))\n this->SDdirection = true;\n }\n // when SDdirection == true, our output is 1 and our accumulator is decreasing by (maxPwm - pwmSP)\n else\n {\n // decrement accumulator\n this->SDaccumulator -= (PID_PWM_MAX - this->pwmSP);\n // if we've reached 0, flip our direction\n if (this->SDaccumulator <= 0)\n this->SDdirection = false;\n }\n\n\tthis->pwmPin->set(this->SDdirection);\n\n return;\n}\n\nvoid SoftPWM::slowUpdate()\n{\n\treturn;\n}\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/drivers/softPwm/softPwm.h", "content": "#ifndef SOFTPWM_H\n#define SOFTPWM_H\n\n#include \n\n#include \"modules/module.h\"\n#include \"drivers/pin/pin.h\"\n\nclass SoftPWM : public Module\n{\n\tprivate:\n\n\t\tstd::string pin;\t\t\t// PWM output pin\n\t\tint pwmMax;\t\t\t\t\t\t// maximum PWM output: 8 bit resolution (ie 0 to 255)\n\t\tint pwmSP;\t\t\t\t\t\t// PWM setpoint as a percentage of maxPwm\n\t\tint SDaccumulator;\t\t// Sigma-Delta accumulator\n\t\tbool SDdirection;\t\t\t// direction the SD accumulator is being updated\n\n\t\tPin* pwmPin;\t\t\t\t\t// pin object\n\n\tpublic:\n\n\t\tSoftPWM(std::string);\t\t\t\t\t// constructor\n\n\t\tvoid setMaxPwm(int pwmMax);\n\t\tvoid setPwmSP(int newPwmSP);\n\n\t\tvirtual void update(void); // Module default interface\n\t\tvirtual void slowUpdate(void); // Module default interface\n};\n\n#endif\n\n\n/*\n\t The following is taken from Smoothieware...\n\n * Sigma-Delta PWM algorithm\n *\n * This Sigma-Delta implementation works by increasing _sd_accumulator by _pwm until we reach _half_ of max,\n * then decreasing by (max - target_pwm) until we hit zero\n *\n * While we're increasing, the output is 0 and while we're decreasing the output is 1\n *\n * For example, with pwm=128 and a max of 256, we'll see the following pattern:\n * ACC ADD OUT\n * 0 128 1 // after the add, we hit 256/2 = 128 so we change direction\n * 128 -128 0 // after the add, we hit 0 so we change direction again\n * 0 128 1\n * 128 -128 0\n * as expected\n *\n * with a pwm value of 192 (75%) we'll see this:\n * ACC ADD OUT\n * 0 192 0 // after the add, we are beyond max/2 so we change direction\n * 192 -64 1 // haven't reached 0 yet\n * 128 -64 1 // haven't reached 0 yet\n * 64 -64 1 // after this add we reach 0, and change direction\n * 0 192 0\n * 192 -64 1\n * 128 -64 1\n * 64 -64 1\n * 0 192 0\n * etcetera\n *\n * with a pwm value of 75 (about 29%) we'll see this pattern:\n * ACC ADD OUT\n * 0 75 0\n * 75 75 0\n * 150 -181 1\n * -31 75 0\n * 44 75 0\n * 119 75 0\n * 194 -181 1\n * 13 -181 1\n * -168 75 0\n * -93 75 0\n * -18 75 0\n * 57 75 0\n * 132 -181 1\n * -49 75 0\n * 26 75 0\n * 101 75 0\n * 176 -181 1\n * -5 75 0\n * 70 75 0\n * 145 -181 1\n * -36 75 0\n * etcetera. This pattern has 6 '1's over a total of 21 lines which is on 28.57% of the time. If we let it run longer, it would get closer to the target as time went on\n */\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/extern.h", "content": "#ifndef EXTERN_H\n#define EXTERN_H\n\n#include \"configuration.h\"\n#include \"remora.h\"\n\n#include \"ArduinoJson.h\"\n#include \"pruThread.h\"\n\nextern uint32_t base_freq;\nextern uint32_t servo_freq;\n\nextern JsonObject module;\n\nextern volatile bool PRUreset;\n\n// unions for RX and TX data\nextern volatile rxData_t rxData;\nextern volatile txData_t txData;\n\n// pointers to objects with global scope\nextern pruThread* baseThread;\nextern pruThread* servoThread;\nextern pruThread* commsThread;\n\n// pointers to data\nextern volatile rxData_t* ptrRxData;\nextern volatile txData_t* ptrTxData;\nextern volatile int32_t* ptrTxHeader; \nextern volatile bool* ptrPRUreset;\nextern volatile int32_t* ptrJointFreqCmd[JOINTS];\nextern volatile int32_t* ptrJointFeedback[JOINTS];\nextern volatile uint8_t* ptrJointEnable;\nextern volatile float* ptrSetPoint[VARIABLES];\nextern volatile float* ptrProcessVariable[VARIABLES];\nextern volatile uint16_t* ptrInputs;\nextern volatile uint16_t* ptrOutputs;\n\n\n#endif" }, { "path": "Firmware/FirmwareSource/Remora-OS5/lib/ArduinoJson6/ArduinoJson/Array/ArrayFunctions.hpp", "content": "// ArduinoJson - arduinojson.org\n// Copyright Benoit Blanchon 2014-2019\n// MIT License\n\n#pragma once\n\n#include \"../Collection/CollectionData.hpp\"\n\nnamespace ARDUINOJSON_NAMESPACE {\n\ninline VariantData *arrayAdd(CollectionData *arr, MemoryPool *pool) {\n return arr ? arr->add(pool) : 0;\n}\n\ntemplate \ninline void arrayAccept(const CollectionData *arr, Visitor &visitor) {\n if (arr)\n visitor.visitArray(*arr);\n else\n visitor.visitNull();\n}\n\ninline bool arrayEquals(const CollectionData *lhs, const CollectionData *rhs) {\n if (lhs == rhs) return true;\n if (!lhs || !rhs) return false;\n\n return lhs->equalsArray(*rhs);\n}\n} // namespace ARDUINOJSON_NAMESPACE\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/lib/ArduinoJson6/ArduinoJson/Array/ArrayImpl.hpp", "content": "// ArduinoJson - arduinojson.org\n// Copyright Benoit Blanchon 2014-2019\n// MIT License\n\n#pragma once\n\n#include \"../Object/ObjectRef.hpp\"\n#include \"ArrayRef.hpp\"\n\nnamespace ARDUINOJSON_NAMESPACE {\n\ntemplate \ninline ArrayRef ArrayShortcuts::createNestedArray() const {\n return impl()->addElement().template to();\n}\n\ntemplate \ninline ObjectRef ArrayShortcuts::createNestedObject() const {\n return impl()->addElement().template to();\n}\n\n} // namespace ARDUINOJSON_NAMESPACE\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/lib/ArduinoJson6/ArduinoJson/Array/ArrayIterator.hpp", "content": "// ArduinoJson - arduinojson.org\n// Copyright Benoit Blanchon 2014-2019\n// MIT License\n\n#pragma once\n\n#include \"../Variant/SlotFunctions.hpp\"\n#include \"../Variant/VariantRef.hpp\"\n\nnamespace ARDUINOJSON_NAMESPACE {\n\nclass VariantPtr {\n public:\n VariantPtr(MemoryPool *pool, VariantData *data) : _variant(pool, data) {}\n\n VariantRef *operator->() {\n return &_variant;\n }\n\n VariantRef &operator*() {\n return _variant;\n }\n\n private:\n VariantRef _variant;\n};\n\nclass ArrayIterator {\n public:\n ArrayIterator() : _slot(0) {}\n explicit ArrayIterator(MemoryPool *pool, VariantSlot *slot)\n : _pool(pool), _slot(slot) {}\n\n VariantRef operator*() const {\n return VariantRef(_pool, _slot->data());\n }\n VariantPtr operator->() {\n return VariantPtr(_pool, _slot->data());\n }\n\n bool operator==(const ArrayIterator &other) const {\n return _slot == other._slot;\n }\n\n bool operator!=(const ArrayIterator &other) const {\n return _slot != other._slot;\n }\n\n ArrayIterator &operator++() {\n _slot = _slot->next();\n return *this;\n }\n\n ArrayIterator &operator+=(size_t distance) {\n _slot = _slot->next(distance);\n return *this;\n }\n\n VariantSlot *internal() {\n return _slot;\n }\n\n private:\n MemoryPool *_pool;\n VariantSlot *_slot;\n};\n\nclass VariantConstPtr {\n public:\n VariantConstPtr(const VariantData *data) : _variant(data) {}\n\n VariantConstRef *operator->() {\n return &_variant;\n }\n\n VariantConstRef &operator*() {\n return _variant;\n }\n\n private:\n VariantConstRef _variant;\n};\n\nclass ArrayConstRefIterator {\n public:\n ArrayConstRefIterator() : _slot(0) {}\n explicit ArrayConstRefIterator(const VariantSlot *slot) : _slot(slot) {}\n\n VariantConstRef operator*() const {\n return VariantConstRef(_slot->data());\n }\n VariantConstPtr operator->() {\n return VariantConstPtr(_slot->data());\n }\n\n bool operator==(const ArrayConstRefIterator &other) const {\n return _slot == other._slot;\n }\n\n bool operator!=(const ArrayConstRefIterator &other) const {\n return _slot != other._slot;\n }\n\n ArrayConstRefIterator &operator++() {\n _slot = _slot->next();\n return *this;\n }\n\n ArrayConstRefIterator &operator+=(size_t distance) {\n _slot = _slot->next(distance);\n return *this;\n }\n\n const VariantSlot *internal() {\n return _slot;\n }\n\n private:\n const VariantSlot *_slot;\n};\n} // namespace ARDUINOJSON_NAMESPACE\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/lib/ArduinoJson6/ArduinoJson/Array/ArrayRef.hpp", "content": "// ArduinoJson - arduinojson.org\n// Copyright Benoit Blanchon 2014-2019\n// MIT License\n\n#pragma once\n\n#include \"../Variant/VariantData.hpp\"\n#include \"ArrayFunctions.hpp\"\n#include \"ArrayIterator.hpp\"\n\n// Returns the size (in bytes) of an array with n elements.\n// Can be very handy to determine the size of a StaticMemoryPool.\n#define JSON_ARRAY_SIZE(NUMBER_OF_ELEMENTS) \\\n ((NUMBER_OF_ELEMENTS) * sizeof(ARDUINOJSON_NAMESPACE::VariantSlot))\n\nnamespace ARDUINOJSON_NAMESPACE {\n\nclass ObjectRef;\ntemplate \nclass ElementProxy;\n\ntemplate \nclass ArrayRefBase {\n public:\n operator VariantConstRef() const {\n const void* data = _data; // prevent warning cast-align\n return VariantConstRef(reinterpret_cast(data));\n }\n\n template \n FORCE_INLINE void accept(Visitor& visitor) const {\n arrayAccept(_data, visitor);\n }\n\n FORCE_INLINE bool isNull() const {\n return _data == 0;\n }\n\n FORCE_INLINE size_t memoryUsage() const {\n return _data ? _data->memoryUsage() : 0;\n }\n\n FORCE_INLINE size_t nesting() const {\n return _data ? _data->nesting() : 0;\n }\n\n FORCE_INLINE size_t size() const {\n return _data ? _data->size() : 0;\n }\n\n protected:\n ArrayRefBase(TData* data) : _data(data) {}\n TData* _data;\n};\n\nclass ArrayConstRef : public ArrayRefBase,\n public Visitable {\n friend class ArrayRef;\n typedef ArrayRefBase base_type;\n\n public:\n typedef ArrayConstRefIterator iterator;\n\n FORCE_INLINE iterator begin() const {\n if (!_data) return iterator();\n return iterator(_data->head());\n }\n\n FORCE_INLINE iterator end() const {\n return iterator();\n }\n\n FORCE_INLINE ArrayConstRef() : base_type(0) {}\n FORCE_INLINE ArrayConstRef(const CollectionData* data) : base_type(data) {}\n\n FORCE_INLINE bool operator==(ArrayConstRef rhs) const {\n return arrayEquals(_data, rhs._data);\n }\n\n FORCE_INLINE VariantConstRef operator[](size_t index) const {\n return getElement(index);\n }\n\n FORCE_INLINE VariantConstRef getElement(size_t index) const {\n return VariantConstRef(_data ? _data->get(index) : 0);\n }\n};\n\nclass ArrayRef : public ArrayRefBase,\n public ArrayShortcuts,\n public Visitable {\n typedef ArrayRefBase base_type;\n\n public:\n typedef ArrayIterator iterator;\n\n FORCE_INLINE ArrayRef() : base_type(0), _pool(0) {}\n FORCE_INLINE ArrayRef(MemoryPool* pool, CollectionData* data)\n : base_type(data), _pool(pool) {}\n\n operator VariantRef() {\n void* data = _data; // prevent warning cast-align\n return VariantRef(_pool, reinterpret_cast(data));\n }\n\n operator ArrayConstRef() const {\n return ArrayConstRef(_data);\n }\n\n VariantRef addElement() const {\n return VariantRef(_pool, arrayAdd(_data, _pool));\n }\n\n FORCE_INLINE iterator begin() const {\n if (!_data) return iterator();\n return iterator(_pool, _data->head());\n }\n\n FORCE_INLINE iterator end() const {\n return iterator();\n }\n\n // Copy a ArrayRef\n FORCE_INLINE bool set(ArrayConstRef src) const {\n if (!_data || !src._data) return false;\n return _data->copyFrom(*src._data, _pool);\n }\n\n FORCE_INLINE bool operator==(ArrayRef rhs) const {\n return arrayEquals(_data, rhs._data);\n }\n\n // Gets the value at the specified index.\n FORCE_INLINE VariantRef getElement(size_t index) const {\n return VariantRef(_pool, _data ? _data->get(index) : 0);\n }\n\n // Removes element at specified position.\n FORCE_INLINE void remove(iterator it) const {\n if (!_data) return;\n _data->remove(it.internal());\n }\n\n // Removes element at specified index.\n FORCE_INLINE void remove(size_t index) const {\n if (!_data) return;\n _data->remove(index);\n }\n\n private:\n MemoryPool* _pool;\n};\n} // namespace ARDUINOJSON_NAMESPACE\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/lib/ArduinoJson6/ArduinoJson/Array/ArrayShortcuts.hpp", "content": "// ArduinoJson - arduinojson.org\n// Copyright Benoit Blanchon 2014-2019\n// MIT License\n\n#pragma once\n\n#include \"../Polyfills/attributes.hpp\"\n#include \"../Polyfills/type_traits.hpp\"\n\nnamespace ARDUINOJSON_NAMESPACE {\n// Forward declarations.\ntemplate \nclass ElementProxy;\n\ntemplate \nclass ArrayShortcuts {\n public:\n // Returns the element at specified index if the variant is an array.\n FORCE_INLINE ElementProxy operator[](size_t index) const;\n\n FORCE_INLINE ObjectRef createNestedObject() const;\n\n FORCE_INLINE ArrayRef createNestedArray() const;\n\n // Adds the specified value at the end of the array.\n //\n // bool add(TValue);\n // TValue = bool, long, int, short, float, double, serialized, VariantRef,\n // std::string, String, ObjectRef\n template \n FORCE_INLINE bool add(const T &value) const {\n return impl()->addElement().set(value);\n }\n //\n // bool add(TValue);\n // TValue = char*, const char*, const __FlashStringHelper*\n template \n FORCE_INLINE bool add(T *value) const {\n return impl()->addElement().set(value);\n }\n\n private:\n const TArray *impl() const {\n return static_cast(this);\n }\n};\n} // namespace ARDUINOJSON_NAMESPACE\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/lib/ArduinoJson6/ArduinoJson/Array/ElementProxy.hpp", "content": "// ArduinoJson - arduinojson.org\n// Copyright Benoit Blanchon 2014-2019\n// MIT License\n\n#pragma once\n\n#include \"../Configuration.hpp\"\n#include \"../Operators/VariantOperators.hpp\"\n\n#ifdef _MSC_VER\n#pragma warning(push)\n#pragma warning(disable : 4522)\n#endif\n\nnamespace ARDUINOJSON_NAMESPACE {\n\ntemplate \nclass ElementProxy : public VariantOperators >,\n public Visitable {\n typedef ElementProxy this_type;\n\n public:\n FORCE_INLINE ElementProxy(TArray array, size_t index)\n : _array(array), _index(index) {}\n\n FORCE_INLINE this_type& operator=(const this_type& src) {\n getUpstreamElement().set(src.as());\n return *this;\n }\n\n // Replaces the value\n //\n // operator=(const TValue&)\n // TValue = bool, long, int, short, float, double, serialized, VariantRef,\n // std::string, String, ArrayRef, ObjectRef\n template \n FORCE_INLINE this_type& operator=(const T& src) {\n getUpstreamElement().set(src);\n return *this;\n }\n //\n // operator=(TValue)\n // TValue = char*, const char*, const __FlashStringHelper*\n template \n FORCE_INLINE this_type& operator=(T* src) {\n getUpstreamElement().set(src);\n return *this;\n }\n\n FORCE_INLINE void clear() const {\n getUpstreamElement().clear();\n }\n\n FORCE_INLINE bool isNull() const {\n return getUpstreamElement().isNull();\n }\n\n template \n FORCE_INLINE typename VariantAs::type as() const {\n return getUpstreamElement().template as();\n }\n\n template \n FORCE_INLINE bool is() const {\n return getUpstreamElement().template is();\n }\n\n template \n FORCE_INLINE typename VariantTo::type to() const {\n return getUpstreamElement().template to();\n }\n\n // Replaces the value\n //\n // bool set(const TValue&)\n // TValue = bool, long, int, short, float, double, serialized, VariantRef,\n // std::string, String, ArrayRef, ObjectRef\n template \n FORCE_INLINE bool set(const TValue& value) const {\n return getUpstreamElement().set(value);\n }\n //\n // bool set(TValue)\n // TValue = char*, const char*, const __FlashStringHelper*\n template \n FORCE_INLINE bool set(TValue* value) const {\n return getUpstreamElement().set(value);\n }\n\n template \n void accept(Visitor& visitor) const {\n return getUpstreamElement().accept(visitor);\n }\n\n FORCE_INLINE size_t size() const {\n return getUpstreamElement().size();\n }\n\n template \n VariantRef getMember(TNestedKey* key) const {\n return getUpstreamElement().getMember(key);\n }\n\n template \n VariantRef getMember(const TNestedKey& key) const {\n return getUpstreamElement().getMember(key);\n }\n\n template \n VariantRef getOrAddMember(TNestedKey* key) const {\n return getUpstreamElement().getOrAddMember(key);\n }\n\n template \n VariantRef getOrAddMember(const TNestedKey& key) const {\n return getUpstreamElement().getOrAddMember(key);\n }\n\n VariantRef addElement() const {\n return getUpstreamElement().addElement();\n }\n\n VariantRef getElement(size_t index) const {\n return getUpstreamElement().getElement(index);\n }\n\n FORCE_INLINE void remove(size_t index) const {\n getUpstreamElement().remove(index);\n }\n // remove(char*) const\n // remove(const char*) const\n // remove(const __FlashStringHelper*) const\n template \n FORCE_INLINE typename enable_if::value>::type remove(\n TChar* key) const {\n getUpstreamElement().remove(key);\n }\n // remove(const std::string&) const\n // remove(const String&) const\n template \n FORCE_INLINE typename enable_if::value>::type remove(\n const TString& key) const {\n getUpstreamElement().remove(key);\n }\n\n private:\n FORCE_INLINE VariantRef getUpstreamElement() const {\n return _array.getElement(_index);\n }\n\n TArray _array;\n const size_t _index;\n};\n\ntemplate \ninline ElementProxy ArrayShortcuts::operator[](\n size_t index) const {\n return ElementProxy(*impl(), index);\n}\n\n} // namespace ARDUINOJSON_NAMESPACE\n\n#ifdef _MSC_VER\n#pragma warning(pop)\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/lib/ArduinoJson6/ArduinoJson/Array/Utilities.hpp", "content": "// ArduinoJson - arduinojson.org\n// Copyright Benoit Blanchon 2014-2019\n// MIT License\n\n#pragma once\n\n#include \"ArrayRef.hpp\"\n\nnamespace ARDUINOJSON_NAMESPACE {\n\n// Copy a 1D array to a JsonArray\ntemplate \ninline bool copyArray(T (&src)[N], ArrayRef dst) {\n return copyArray(src, N, dst);\n}\n\n// Copy a 1D array to a JsonArray\ntemplate \ninline bool copyArray(T* src, size_t len, ArrayRef dst) {\n bool ok = true;\n for (size_t i = 0; i < len; i++) {\n ok &= dst.add(src[i]);\n }\n return ok;\n}\n\n// Copy a 2D array to a JsonArray\ntemplate \ninline bool copyArray(T (&src)[N1][N2], ArrayRef dst) {\n bool ok = true;\n for (size_t i = 0; i < N1; i++) {\n ArrayRef nestedArray = dst.createNestedArray();\n for (size_t j = 0; j < N2; j++) {\n ok &= nestedArray.add(src[i][j]);\n }\n }\n return ok;\n}\n\n// Copy a JsonArray to a 1D array\ntemplate \ninline size_t copyArray(ArrayConstRef src, T (&dst)[N]) {\n return copyArray(src, dst, N);\n}\n\n// Copy a JsonArray to a 1D array\ntemplate \ninline size_t copyArray(ArrayConstRef src, T* dst, size_t len) {\n size_t i = 0;\n for (ArrayConstRef::iterator it = src.begin(); it != src.end() && i < len;\n ++it)\n dst[i++] = *it;\n return i;\n}\n\n// Copy a JsonArray to a 2D array\ntemplate \ninline void copyArray(ArrayConstRef src, T (&dst)[N1][N2]) {\n size_t i = 0;\n for (ArrayConstRef::iterator it = src.begin(); it != src.end() && i < N1;\n ++it) {\n copyArray(it->as(), dst[i++]);\n }\n}\n\n} // namespace ARDUINOJSON_NAMESPACE\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/lib/ArduinoJson6/ArduinoJson/Collection/CollectionData.hpp", "content": "// ArduinoJson - arduinojson.org\n// Copyright Benoit Blanchon 2014-2019\n// MIT License\n\n#pragma once\n\nnamespace ARDUINOJSON_NAMESPACE {\n\nclass MemoryPool;\nclass VariantData;\nclass VariantSlot;\n\nclass CollectionData {\n VariantSlot *_head;\n VariantSlot *_tail;\n\n public:\n // Must be a POD!\n // - no constructor\n // - no destructor\n // - no virtual\n // - no inheritance\n VariantSlot *addSlot(MemoryPool *);\n\n VariantData *add(MemoryPool *pool);\n\n template \n VariantData *add(TAdaptedString key, MemoryPool *pool);\n\n void clear();\n\n template \n bool containsKey(const TAdaptedString &key) const;\n\n bool copyFrom(const CollectionData &src, MemoryPool *pool);\n\n bool equalsArray(const CollectionData &other) const;\n bool equalsObject(const CollectionData &other) const;\n\n VariantData *get(size_t index) const;\n\n template \n VariantData *get(TAdaptedString key) const;\n\n VariantSlot *head() const {\n return _head;\n }\n\n void remove(size_t index);\n\n template \n void remove(TAdaptedString key) {\n remove(getSlot(key));\n }\n\n void remove(VariantSlot *slot);\n\n size_t memoryUsage() const;\n size_t nesting() const;\n size_t size() const;\n\n private:\n VariantSlot *getSlot(size_t index) const;\n\n template \n VariantSlot *getSlot(TAdaptedString key) const;\n\n VariantSlot *getPreviousSlot(VariantSlot *) const;\n};\n} // namespace ARDUINOJSON_NAMESPACE\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/lib/ArduinoJson6/ArduinoJson/Collection/CollectionImpl.hpp", "content": "// ArduinoJson - arduinojson.org\n// Copyright Benoit Blanchon 2014-2019\n// MIT License\n\n#pragma once\n\n#include \"../Variant/VariantData.hpp\"\n#include \"CollectionData.hpp\"\n\nnamespace ARDUINOJSON_NAMESPACE {\n\ninline VariantSlot* CollectionData::addSlot(MemoryPool* pool) {\n VariantSlot* slot = pool->allocVariant();\n if (!slot) return 0;\n\n if (_tail) {\n _tail->setNextNotNull(slot);\n _tail = slot;\n } else {\n _head = slot;\n _tail = slot;\n }\n\n slot->clear();\n return slot;\n}\n\ninline VariantData* CollectionData::add(MemoryPool* pool) {\n return slotData(addSlot(pool));\n}\n\ntemplate \ninline VariantData* CollectionData::add(TAdaptedString key, MemoryPool* pool) {\n VariantSlot* slot = addSlot(pool);\n if (!slotSetKey(slot, key, pool)) return 0;\n return slot->data();\n}\n\ninline void CollectionData::clear() {\n _head = 0;\n _tail = 0;\n}\n\ntemplate \ninline bool CollectionData::containsKey(const TAdaptedString& key) const {\n return getSlot(key) != 0;\n}\n\ninline bool CollectionData::copyFrom(const CollectionData& src,\n MemoryPool* pool) {\n clear();\n for (VariantSlot* s = src._head; s; s = s->next()) {\n VariantData* var;\n if (s->key() != 0) {\n if (s->ownsKey())\n var = add(RamStringAdapter(s->key()), pool);\n else\n var = add(ConstRamStringAdapter(s->key()), pool);\n } else {\n var = add(pool);\n }\n if (!var) return false;\n if (!var->copyFrom(*s->data(), pool)) return false;\n }\n return true;\n}\n\ninline bool CollectionData::equalsObject(const CollectionData& other) const {\n size_t count = 0;\n for (VariantSlot* slot = _head; slot; slot = slot->next()) {\n VariantData* v1 = slot->data();\n VariantData* v2 = other.get(adaptString(slot->key()));\n if (!variantEquals(v1, v2)) return false;\n count++;\n }\n return count == other.size();\n}\n\ninline bool CollectionData::equalsArray(const CollectionData& other) const {\n VariantSlot* s1 = _head;\n VariantSlot* s2 = other._head;\n for (;;) {\n if (s1 == s2) return true;\n if (!s1 || !s2) return false;\n if (!variantEquals(s1->data(), s2->data())) return false;\n s1 = s1->next();\n s2 = s2->next();\n }\n}\n\ntemplate \ninline VariantSlot* CollectionData::getSlot(TAdaptedString key) const {\n VariantSlot* slot = _head;\n while (slot) {\n if (key.equals(slot->key())) break;\n slot = slot->next();\n }\n return slot;\n}\n\ninline VariantSlot* CollectionData::getSlot(size_t index) const {\n return _head->next(index);\n}\n\ninline VariantSlot* CollectionData::getPreviousSlot(VariantSlot* target) const {\n VariantSlot* current = _head;\n while (current) {\n VariantSlot* next = current->next();\n if (next == target) return current;\n current = next;\n }\n return 0;\n}\n\ntemplate \ninline VariantData* CollectionData::get(TAdaptedString key) const {\n VariantSlot* slot = getSlot(key);\n return slot ? slot->data() : 0;\n}\n\ninline VariantData* CollectionData::get(size_t index) const {\n VariantSlot* slot = getSlot(index);\n return slot ? slot->data() : 0;\n}\n\ninline void CollectionData::remove(VariantSlot* slot) {\n if (!slot) return;\n VariantSlot* prev = getPreviousSlot(slot);\n VariantSlot* next = slot->next();\n if (prev)\n prev->setNext(next);\n else\n _head = next;\n if (!next) _tail = prev;\n}\n\ninline void CollectionData::remove(size_t index) {\n remove(getSlot(index));\n}\n\ninline size_t CollectionData::memoryUsage() const {\n size_t total = 0;\n for (VariantSlot* s = _head; s; s = s->next()) {\n total += sizeof(VariantSlot) + s->data()->memoryUsage();\n if (s->ownsKey()) total += strlen(s->key()) + 1;\n }\n return total;\n}\n\ninline size_t CollectionData::nesting() const {\n size_t maxChildNesting = 0;\n for (VariantSlot* s = _head; s; s = s->next()) {\n size_t childNesting = s->data()->nesting();\n if (childNesting > maxChildNesting) maxChildNesting = childNesting;\n }\n return maxChildNesting + 1;\n}\n\ninline size_t CollectionData::size() const {\n return slotSize(_head);\n}\n\n} // namespace ARDUINOJSON_NAMESPACE\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/lib/ArduinoJson6/ArduinoJson/Configuration.hpp", "content": "// ArduinoJson - arduinojson.org\n// Copyright Benoit Blanchon 2014-2019\n// MIT License\n\n#pragma once\n\n#if defined(_MSC_VER)\n#define ARDUINOJSON_HAS_INT64 1\n#else\n#define ARDUINOJSON_HAS_INT64 0\n#endif\n\n#if __cplusplus >= 201103L\n#define ARDUINOJSON_HAS_LONG_LONG 1\n#else\n#define ARDUINOJSON_HAS_LONG_LONG 0\n#endif\n\n// Small or big machine?\n#ifndef ARDUINOJSON_EMBEDDED_MODE\n#if defined(ARDUINO) || defined(__IAR_SYSTEMS_ICC__) || defined(__XC) || \\\n defined(__ARMCC_VERSION)\n#define ARDUINOJSON_EMBEDDED_MODE 1\n#else\n#define ARDUINOJSON_EMBEDDED_MODE 0\n#endif\n#endif\n\n#if ARDUINOJSON_EMBEDDED_MODE\n\n// Store floats by default to reduce the memory usage (issue #134)\n#ifndef ARDUINOJSON_USE_DOUBLE\n#define ARDUINOJSON_USE_DOUBLE 0\n#endif\n\n// Store longs by default, because they usually match the size of a float.\n#ifndef ARDUINOJSON_USE_LONG_LONG\n#define ARDUINOJSON_USE_LONG_LONG 0\n#endif\n\n// Embedded systems usually don't have std::string\n#ifndef ARDUINOJSON_ENABLE_STD_STRING\n#define ARDUINOJSON_ENABLE_STD_STRING 0\n#endif\n\n// Embedded systems usually don't have std::stream\n#ifndef ARDUINOJSON_ENABLE_STD_STREAM\n#define ARDUINOJSON_ENABLE_STD_STREAM 0\n#endif\n\n// Limit nesting as the stack is likely to be small\n#ifndef ARDUINOJSON_DEFAULT_NESTING_LIMIT\n#define ARDUINOJSON_DEFAULT_NESTING_LIMIT 10\n#endif\n\n#else // ARDUINOJSON_EMBEDDED_MODE\n\n// On a computer we have plenty of memory so we can use doubles\n#ifndef ARDUINOJSON_USE_DOUBLE\n#define ARDUINOJSON_USE_DOUBLE 1\n#endif\n\n// Use long long when available\n#ifndef ARDUINOJSON_USE_LONG_LONG\n#if ARDUINOJSON_HAS_LONG_LONG || ARDUINOJSON_HAS_INT64\n#define ARDUINOJSON_USE_LONG_LONG 1\n#else\n#define ARDUINOJSON_USE_LONG_LONG 0\n#endif\n#endif\n\n// On a computer, we can use std::string\n#ifndef ARDUINOJSON_ENABLE_STD_STRING\n#define ARDUINOJSON_ENABLE_STD_STRING 1\n#endif\n\n// On a computer, we can assume std::stream\n#ifndef ARDUINOJSON_ENABLE_STD_STREAM\n#define ARDUINOJSON_ENABLE_STD_STREAM 1\n#endif\n\n// On a computer, the stack is large so we can increase nesting limit\n#ifndef ARDUINOJSON_DEFAULT_NESTING_LIMIT\n#define ARDUINOJSON_DEFAULT_NESTING_LIMIT 50\n#endif\n\n#endif // ARDUINOJSON_EMBEDDED_MODE\n\n#ifdef ARDUINO\n\n// Enable support for Arduino's String class\n#ifndef ARDUINOJSON_ENABLE_ARDUINO_STRING\n#define ARDUINOJSON_ENABLE_ARDUINO_STRING 1\n#endif\n\n// Enable support for Arduino's Stream class\n#ifndef ARDUINOJSON_ENABLE_ARDUINO_STREAM\n#define ARDUINOJSON_ENABLE_ARDUINO_STREAM 1\n#endif\n\n// Enable support for Arduino's Print class\n#ifndef ARDUINOJSON_ENABLE_ARDUINO_PRINT\n#define ARDUINOJSON_ENABLE_ARDUINO_PRINT 1\n#endif\n\n#else // ARDUINO\n\n// Enable support for Arduino's String class\n#ifndef ARDUINOJSON_ENABLE_ARDUINO_STRING\n#define ARDUINOJSON_ENABLE_ARDUINO_STRING 0\n#endif\n\n// Enable support for Arduino's Stream class\n#ifndef ARDUINOJSON_ENABLE_ARDUINO_STREAM\n#define ARDUINOJSON_ENABLE_ARDUINO_STREAM 0\n#endif\n\n// Enable support for Arduino's Print class\n#ifndef ARDUINOJSON_ENABLE_ARDUINO_PRINT\n#define ARDUINOJSON_ENABLE_ARDUINO_PRINT 0\n#endif\n\n#endif // ARDUINO\n\n#ifndef ARDUINOJSON_ENABLE_PROGMEM\n#ifdef PROGMEM\n#define ARDUINOJSON_ENABLE_PROGMEM 1\n#else\n#define ARDUINOJSON_ENABLE_PROGMEM 0\n#endif\n#endif\n\n// Convert unicode escape sequence (\\u0123) to UTF-8\n#ifndef ARDUINOJSON_DECODE_UNICODE\n#define ARDUINOJSON_DECODE_UNICODE 0\n#endif\n\n// Control the exponentiation threshold for big numbers\n// CAUTION: cannot be more that 1e9 !!!!\n#ifndef ARDUINOJSON_POSITIVE_EXPONENTIATION_THRESHOLD\n#define ARDUINOJSON_POSITIVE_EXPONENTIATION_THRESHOLD 1e7\n#endif\n\n// Control the exponentiation threshold for small numbers\n#ifndef ARDUINOJSON_NEGATIVE_EXPONENTIATION_THRESHOLD\n#define ARDUINOJSON_NEGATIVE_EXPONENTIATION_THRESHOLD 1e-5\n#endif\n\n#ifndef ARDUINOJSON_LITTLE_ENDIAN\n#if defined(_MSC_VER) || \\\n (defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) || \\\n defined(__LITTLE_ENDIAN__) || defined(__i386) || defined(__x86_64)\n#define ARDUINOJSON_LITTLE_ENDIAN 1\n#else\n#define ARDUINOJSON_LITTLE_ENDIAN 0\n#endif\n#endif\n\n#ifndef ARDUINOJSON_TAB\n#define ARDUINOJSON_TAB \" \"\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/lib/ArduinoJson6/ArduinoJson/Deserialization/ArduinoStreamReader.hpp", "content": "// ArduinoJson - arduinojson.org\n// Copyright Benoit Blanchon 2014-2019\n// MIT License\n\n#pragma once\n\n#if ARDUINOJSON_ENABLE_ARDUINO_STREAM\n\n#include \n\nnamespace ARDUINOJSON_NAMESPACE {\n\nstruct ArduinoStreamReader {\n Stream& _stream;\n char _current;\n bool _ended;\n\n public:\n explicit ArduinoStreamReader(Stream& stream)\n : _stream(stream), _current(0), _ended(false) {}\n\n char read() {\n // don't use _stream.read() as it ignores the timeout\n char c = 0;\n _ended = _stream.readBytes(&c, 1) == 0;\n return c;\n }\n\n bool ended() const {\n return _ended;\n }\n};\n\ninline ArduinoStreamReader makeReader(Stream& input) {\n return ArduinoStreamReader(input);\n}\n} // namespace ARDUINOJSON_NAMESPACE\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/lib/ArduinoJson6/ArduinoJson/Deserialization/CharPointerReader.hpp", "content": "// ArduinoJson - arduinojson.org\n// Copyright Benoit Blanchon 2014-2019\n// MIT License\n\n#pragma once\n\nnamespace ARDUINOJSON_NAMESPACE {\n\nclass UnsafeCharPointerReader {\n const char* _ptr;\n\n public:\n explicit UnsafeCharPointerReader(const char* ptr)\n : _ptr(ptr ? ptr : reinterpret_cast(\"\")) {}\n\n char read() {\n return static_cast(*_ptr++);\n }\n\n bool ended() const {\n // we cannot know, that's why it's unsafe\n return false;\n }\n};\n\nclass SafeCharPointerReader {\n const char* _ptr;\n const char* _end;\n\n public:\n explicit SafeCharPointerReader(const char* ptr, size_t len)\n : _ptr(ptr ? ptr : reinterpret_cast(\"\")), _end(_ptr + len) {}\n\n char read() {\n return static_cast(*_ptr++);\n }\n\n bool ended() const {\n return _ptr == _end;\n }\n};\n\ntemplate \ninline UnsafeCharPointerReader makeReader(TChar* input) {\n return UnsafeCharPointerReader(reinterpret_cast(input));\n}\n\ntemplate \ninline SafeCharPointerReader makeReader(TChar* input, size_t n) {\n return SafeCharPointerReader(reinterpret_cast(input), n);\n}\n\n#if ARDUINOJSON_ENABLE_ARDUINO_STRING\ninline SafeCharPointerReader makeReader(const ::String& input) {\n return SafeCharPointerReader(input.c_str(), input.length());\n}\n#endif\n\n} // namespace ARDUINOJSON_NAMESPACE\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/lib/ArduinoJson6/ArduinoJson/Deserialization/DeserializationError.hpp", "content": "// ArduinoJson - arduinojson.org\n// Copyright Benoit Blanchon 2014-2019\n// MIT License\n\n#pragma once\n\n#if ARDUINOJSON_ENABLE_STD_STREAM\n#include \n#endif\n\nnamespace ARDUINOJSON_NAMESPACE {\n\nclass DeserializationError {\n // safe bool idiom\n typedef void (DeserializationError::*bool_type)() const;\n void safeBoolHelper() const {}\n\n public:\n enum Code {\n Ok,\n IncompleteInput,\n InvalidInput,\n NoMemory,\n NotSupported,\n TooDeep\n };\n\n DeserializationError() {}\n DeserializationError(Code c) : _code(c) {}\n\n // Compare with DeserializationError\n friend bool operator==(const DeserializationError& lhs,\n const DeserializationError& rhs) {\n return lhs._code == rhs._code;\n }\n friend bool operator!=(const DeserializationError& lhs,\n const DeserializationError& rhs) {\n return lhs._code != rhs._code;\n }\n\n // Compare with Code\n friend bool operator==(const DeserializationError& lhs, Code rhs) {\n return lhs._code == rhs;\n }\n friend bool operator==(Code lhs, const DeserializationError& rhs) {\n return lhs == rhs._code;\n }\n friend bool operator!=(const DeserializationError& lhs, Code rhs) {\n return lhs._code != rhs;\n }\n friend bool operator!=(Code lhs, const DeserializationError& rhs) {\n return lhs != rhs._code;\n }\n\n // Behaves like a bool\n operator bool_type() const {\n return _code != Ok ? &DeserializationError::safeBoolHelper : 0;\n }\n friend bool operator==(bool value, const DeserializationError& err) {\n return static_cast(err) == value;\n }\n friend bool operator==(const DeserializationError& err, bool value) {\n return static_cast(err) == value;\n }\n friend bool operator!=(bool value, const DeserializationError& err) {\n return static_cast(err) != value;\n }\n friend bool operator!=(const DeserializationError& err, bool value) {\n return static_cast(err) != value;\n }\n\n // Returns internal enum, useful for switch statement\n Code code() const {\n return _code;\n }\n\n const char* c_str() const {\n switch (_code) {\n case Ok:\n return \"Ok\";\n case TooDeep:\n return \"TooDeep\";\n case NoMemory:\n return \"NoMemory\";\n case InvalidInput:\n return \"InvalidInput\";\n case IncompleteInput:\n return \"IncompleteInput\";\n case NotSupported:\n return \"NotSupported\";\n default:\n return \"???\";\n }\n }\n\n private:\n Code _code;\n};\n\n#if ARDUINOJSON_ENABLE_STD_STREAM\ninline std::ostream& operator<<(std::ostream& s,\n const DeserializationError& e) {\n s << e.c_str();\n return s;\n}\n\ninline std::ostream& operator<<(std::ostream& s, DeserializationError::Code c) {\n s << DeserializationError(c).c_str();\n return s;\n}\n#endif\n\n} // namespace ARDUINOJSON_NAMESPACE\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/lib/ArduinoJson6/ArduinoJson/Deserialization/FlashStringReader.hpp", "content": "// ArduinoJson - arduinojson.org\n// Copyright Benoit Blanchon 2014-2019\n// MIT License\n\n#pragma once\n\n#if ARDUINOJSON_ENABLE_PROGMEM\n\nnamespace ARDUINOJSON_NAMESPACE {\nclass UnsafeFlashStringReader {\n const char* _ptr;\n\n public:\n explicit UnsafeFlashStringReader(const __FlashStringHelper* ptr)\n : _ptr(reinterpret_cast(ptr)) {}\n\n char read() {\n return pgm_read_byte_near(_ptr++);\n }\n\n bool ended() const {\n // this reader cannot detect the end\n return false;\n }\n};\n\nclass SafeFlashStringReader {\n const char* _ptr;\n const char* _end;\n\n public:\n explicit SafeFlashStringReader(const __FlashStringHelper* ptr, size_t size)\n : _ptr(reinterpret_cast(ptr)), _end(_ptr + size) {}\n\n char read() {\n return pgm_read_byte_near(_ptr++);\n }\n\n bool ended() const {\n return _ptr == _end;\n }\n};\n\ninline UnsafeFlashStringReader makeReader(const __FlashStringHelper* input) {\n return UnsafeFlashStringReader(input);\n}\n\ninline SafeFlashStringReader makeReader(const __FlashStringHelper* input,\n size_t size) {\n return SafeFlashStringReader(input, size);\n}\n} // namespace ARDUINOJSON_NAMESPACE\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/lib/ArduinoJson6/ArduinoJson/Deserialization/IteratorReader.hpp", "content": "// ArduinoJson - arduinojson.org\n// Copyright Benoit Blanchon 2014-2019\n// MIT License\n\n#pragma once\n\nnamespace ARDUINOJSON_NAMESPACE {\n\ntemplate \nclass IteratorReader {\n TIterator _ptr, _end;\n\n public:\n explicit IteratorReader(TIterator begin, TIterator end)\n : _ptr(begin), _end(end) {}\n\n bool ended() const {\n return _ptr == _end;\n }\n\n char read() {\n return char(*_ptr++);\n }\n};\n\ntemplate \ninline IteratorReader makeReader(\n const TInput& input) {\n return IteratorReader(input.begin(),\n input.end());\n}\n} // namespace ARDUINOJSON_NAMESPACE\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/lib/ArduinoJson6/ArduinoJson/Deserialization/NestingLimit.hpp", "content": "// ArduinoJson - arduinojson.org\n// Copyright Benoit Blanchon 2014-2019\n// MIT License\n\n#pragma once\n\n#include \"../Configuration.hpp\"\n\nnamespace ARDUINOJSON_NAMESPACE {\n\nstruct NestingLimit {\n NestingLimit() : value(ARDUINOJSON_DEFAULT_NESTING_LIMIT) {}\n explicit NestingLimit(uint8_t n) : value(n) {}\n\n uint8_t value;\n};\n} // namespace ARDUINOJSON_NAMESPACE\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/lib/ArduinoJson6/ArduinoJson/Deserialization/StdStreamReader.hpp", "content": "// ArduinoJson - arduinojson.org\n// Copyright Benoit Blanchon 2014-2019\n// MIT License\n\n#pragma once\n\n#if ARDUINOJSON_ENABLE_STD_STREAM\n\n#include \n\nnamespace ARDUINOJSON_NAMESPACE {\n\nclass StdStreamReader {\n std::istream& _stream;\n char _current;\n\n public:\n explicit StdStreamReader(std::istream& stream)\n : _stream(stream), _current(0) {}\n\n bool ended() const {\n return _stream.eof();\n }\n\n char read() {\n return static_cast(_stream.get());\n }\n\n private:\n StdStreamReader& operator=(const StdStreamReader&); // Visual Studio C4512\n};\n\ninline StdStreamReader makeReader(std::istream& input) {\n return StdStreamReader(input);\n}\n} // namespace ARDUINOJSON_NAMESPACE\n\n#endif\n" }, { "path": "Firmware/FirmwareSource/Remora-OS5/lib/ArduinoJson6/ArduinoJson/Deserialization/deserialize.hpp", "content": "// ArduinoJson - arduinojson.org\n// Copyright Benoit Blanchon 2014-2019\n// MIT License\n\n#pragma once\n\n#include \"../StringStorage/StringStorage.hpp\"\n#include \"ArduinoStreamReader.hpp\"\n#include \"CharPointerReader.hpp\"\n#include \"DeserializationError.hpp\"\n#include \"FlashStringReader.hpp\"\n#include \"IteratorReader.hpp\"\n#include \"NestingLimit.hpp\"\n#include \"StdStreamReader.hpp\"\n\nnamespace ARDUINOJSON_NAMESPACE {\n\ntemplate