[ { "path": ".gitignore", "content": "fusesoc.log\n\n*.bak\n*.rpt\n*.qws\n*.bmp\nPLLJ_PLLSPE_INFO.txt\n\nwork/\ngreybox_tmp/\nsimulation/\ndb/\nincremental_db/\noutput_files/\njunk/\n.qsys_edit/\n" }, { "path": "bench/double_click_tb.v", "content": "/**\n * Test bench for double click detector module, simulates\n * - Reset\n * - 1-Click\n * - 2-Click - expect 2 -click\n * - Long-Click - expect 1-click\n * - Multi-Click - exepect 2-click\n */\nmodule double_click_tb();\n\n vlog_tb_utils vlog_tb_utils0();\n\n reg button_r;\n reg rst_n, clk;\n wire single, double;\n \ninitial \nbegin\n button_r = 1'b0;\n rst_n = 1'b1;\n clk = 1'b0;\nend\n\nalways\n #1 clk <= ~clk;\n \ninitial\nbegin\n #3 rst_n = 1'b0;\n #3 rst_n = 1'b1;\n \n #10 button_r = 1'b1;\n #100 button_r = 1'b0;\n \n \n #3 rst_n = 1'b0;\n #3 rst_n = 1'b1;\n\n #10 button_r = 1'b1;\n #4 button_r = 1'b0;\n #5 button_r = 1'b1;\n #3 button_r = 1'b0;\n \n #100 $finish;\n \nend\n \ndouble_click #(.WAIT_WIDTH(4)) double_clicki (\n .button(button_r), .single(single), .double(double), \n .clk(clk), .rst_n(rst_n)\n);\n\nendmodule\n" }, { "path": "bench/fifo_tb.v", "content": "/**\n * Test bentch for fifo's\n * 1. fifo fast write read slow\n * 2. fifo write flow read fast\n * 3. fifo slight difference between clocks\n */\nmodule fifo_tb();\n\n vlog_tb_utils vlog_tb_utils0();\n \n reg rst_n, clka, clkb, rd, wr;\n reg [3:0] datain;\n \n wire [3:0] dataout_slow;\n wire [3:0] dataout_fast;\n wire full_fast, empty_slow, full_slow, empty_fast;\n \ninitial \nbegin\n rd = 0;\n wr = 0;\n datain = 4'b0000;\n rst_n = 1'b1;\n clka = 1'b0;\n clkb = 1'b0;\nend\n\nalways\n #1 clka <= ~clka;\n \nalways\n #13 clkb <= ~clkb;\n \ninitial\nbegin\n #3 rst_n = 1'b0;\n #3 rst_n = 1'b1;\n \n \n #5 datain = 4'b0110;\n wr = 1'b1;\n #2 wr = 1'b0;\n #5 datain = 4'b0000;\n \n #80 rd = 1'b1;\n #26 rd = 1'b0;\n \n #100 $finish;\n \nend\n \nfifo #(.BUS_WIDTH(4)) fifo_f2si (\n .wr_data (datain), \n .rd_data (dataout_slow),\n .wr_clk (clka), \n .rd_clk (clkb),\n .wr (wr), \n .rd (rd),\n .full (full_fast), \n .empty_n (empty_slow),\n .rst_n (rst_n)\n);\n\nfifo #(.BUS_WIDTH(4)) fifo_s2fi (\n .wr_data (datain), \n .rd_data (dataout_fast),\n .wr_clk (clkb),\n .rd_clk (clka),\n .wr (wr),\n .rd (rd),\n .full (full_slow),\n .empty_n (empty_fast),\n .rst_n (rst_n)\n);\n \nendmodule\n" }, { "path": "bench/sdram_controller_tb.v", "content": "/**\n * Testbench for sdram_controller modules, simulates:\n * - Iinit\n * - Write\n * - Read\n */\nmodule sdram_controller_tb();\n\n vlog_tb_utils vlog_tb_utils0();\n\n /* HOST CONTROLLS */\n reg [23:0] haddr;\n reg [15:0] data_input;\n wire [15:0] data_output;\n wire busy; \n reg rd_enable, wr_enable, rst_n, clk;\n\n /* SDRAM SIDE */\n wire [12:0] addr;\n wire [1:0] bank_addr;\n wire [15:0] data; \n wire clock_enable, cs_n, ras_n, cas_n, we_n, data_mask_low, data_mask_high;\n\n reg [15:0] data_r;\n\n assign data = data_r;\n\n\n initial \n begin\n haddr = 24'd0;\n data_input = 16'd0;\n rd_enable = 1'b0;\n wr_enable = 1'b0;\n rst_n = 1'b1;\n clk = 1'b0;\n data_r = 16'hzzzz;\n end\n\n always\n #1 clk <= ~clk;\n \n initial\n begin\n #3 rst_n = 1'b0;\n #3 rst_n = 1'b1;\n \n #120 haddr = 24'hfedbed;\n data_input = 16'd3333;\n \n #3 wr_enable = 1'b1;\n #6 wr_enable = 1'b0;\n haddr = 24'd0;\n data_input = 16'd0; \n \n #120 haddr = 24'hbedfed;\n #3 rd_enable = 1'b1;\n #6 rd_enable = 1'b0;\n haddr = 24'd0;\n \n #8 data_r = 16'hbbbb;\n #2 data_r = 16'hzzzz;\n \n #1000 $finish;\n end\n\n\nsdram_controller sdram_controlleri (\n /* HOST INTERFACE */\n .wr_addr(haddr), \n .wr_data(data_input),\n .rd_data(data_output),\n .busy(busy), .rd_enable(rd_enable), .wr_enable(wr_enable), .rst_n(rst_n), .clk(clk),\n\n /* SDRAM SIDE */\n .addr(addr), .bank_addr(bank_addr), .data(data), .clock_enable(clock_enable), .cs_n(cs_n), .ras_n(ras_n), .cas_n(cas_n), .we_n(we_n), .data_mask_low(data_mask_low), .data_mask_high(data_mask_high)\n);\n\nendmodule\n" }, { "path": "data/de0_nano.sdc", "content": "# Main system clock (50 Mhz)\ncreate_clock -name \"sys_clk_pad_i\" -period 20.000ns [get_ports {sys_clk_pad_i}]\n\n# Automatically constrain PLL and other generated clocks\nderive_pll_clocks -create_base_clocks\n\n# Automatically calculate clock uncertainty to jitter and other effects.\nderive_clock_uncertainty\n\n# Ignore timing on the reset input\n# set_false_path -through [get_nets {rst_n_pad_i}]\n\n" }, { "path": "data/options.tcl", "content": "" }, { "path": "data/pinmap.tcl", "content": "#\n# Clock / Reset\n#\nset_location_assignment PIN_J15 -to rst_n_pad_i\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to rst_n_pad_i\nset_location_assignment PIN_E1 -to btn_n_pad_i\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to btn_n_pad_i\nset_location_assignment PIN_R8 -to sys_clk_pad_i\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sys_clk_pad_i\n\n#\n# UART0: RX <-> GPIO_2[0] (Pin 5, bottom header)\n# TX <-> GPIO_2[1] (Pin 6, bottom header)\n#\nset_location_assignment PIN_A14 -to uart0_srx_pad_i\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to uart0_srx_pad_i\nset_location_assignment PIN_B16 -to uart0_stx_pad_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to uart0_stx_pad_o\n\n#\n# I2C0: Connected to the EEPROM and Accelerometer\n#\nset_location_assignment PIN_F2 -to i2c0_scl_io\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to i2c0_scl_io\nset_location_assignment PIN_F1 -to i2c0_sda_io\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to i2c0_sda_io\n\n#\n# Accelerometer specific lines\n#\nset_location_assignment PIN_M2 -to accelerometer_irq_i\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to accelerometer_irq_i\nset_location_assignment PIN_G5 -to accelerometer_cs_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to accelerometer_cs_o\n\n#\n# I2C1: sda <-> GPIO_2[6] (Pin 11, bottom header)\n# scl <-> GPIO_2[7] (Pin 12, bottom header)\n#\nset_location_assignment PIN_D15 -to i2c1_sda_io\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to i2c1_sda_io\nset_location_assignment PIN_D14 -to i2c1_scl_io\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to i2c1_scl_io\n\n#\n# SPI0: Connected to the EPCS\n#\nset_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION \"USE AS REGULAR IO\"\nset_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION \"USE AS REGULAR IO\"\nset_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION \"USE AS REGULAR IO\"\nset_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION \"USE AS REGULAR IO\"\nset_location_assignment PIN_C1 -to spi0_mosi_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi0_mosi_o\nset_location_assignment PIN_H2 -to spi0_miso_i\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi0_miso_i\nset_location_assignment PIN_H1 -to spi0_sck_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi0_sck_o\nset_location_assignment PIN_D2 -to spi0_ss_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi0_ss_o\n\n#\n# SPI1: Connected to the AD converter\n#\nset_location_assignment PIN_B10 -to spi1_mosi_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi1_mosi_o\nset_location_assignment PIN_A9 -to spi1_miso_i\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi1_miso_i\nset_location_assignment PIN_B14 -to spi1_sck_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi1_sck_o\nset_location_assignment PIN_A10 -to spi1_ss_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi1_ss_o\n\n#\n# SPI2: MOSI <-> GPIO_2[2] (Pin 7, bottom header)\n# MISO <-> GPIO_2[3] (Pin 8, bottom header)\n# SCK <-> GPIO_2[4] (Pin 9, bottom header)\n# SS <-> GPIO_2[5] (Pin 10, bottom header)\n#\nset_location_assignment PIN_C14 -to spi2_mosi_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi2_mosi_o\nset_location_assignment PIN_C16 -to spi2_miso_i\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi2_miso_i\nset_location_assignment PIN_C15 -to spi2_sck_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi2_sck_o\nset_location_assignment PIN_D16 -to spi2_ss_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi2_ss_o\n\n#\n# SDRAM\n#\nset_location_assignment PIN_P2 -to sdram_a_pad_o[0]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[0]\nset_location_assignment PIN_N5 -to sdram_a_pad_o[1]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[1]\nset_location_assignment PIN_N6 -to sdram_a_pad_o[2]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[2]\nset_location_assignment PIN_M8 -to sdram_a_pad_o[3]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[3]\nset_location_assignment PIN_P8 -to sdram_a_pad_o[4]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[4]\nset_location_assignment PIN_T7 -to sdram_a_pad_o[5]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[5]\nset_location_assignment PIN_N8 -to sdram_a_pad_o[6]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[6]\nset_location_assignment PIN_T6 -to sdram_a_pad_o[7]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[7]\nset_location_assignment PIN_R1 -to sdram_a_pad_o[8]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[8]\nset_location_assignment PIN_P1 -to sdram_a_pad_o[9]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[9]\nset_location_assignment PIN_N2 -to sdram_a_pad_o[10]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[10]\nset_location_assignment PIN_N1 -to sdram_a_pad_o[11]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[11]\nset_location_assignment PIN_L4 -to sdram_a_pad_o[12]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[12]\n\nset_location_assignment PIN_G2 -to sdram_dq_pad_io[0]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[0]\nset_location_assignment PIN_G1 -to sdram_dq_pad_io[1]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[1]\nset_location_assignment PIN_L8 -to sdram_dq_pad_io[2]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[2]\nset_location_assignment PIN_K5 -to sdram_dq_pad_io[3]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[3]\nset_location_assignment PIN_K2 -to sdram_dq_pad_io[4]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[4]\nset_location_assignment PIN_J2 -to sdram_dq_pad_io[5]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[5]\nset_location_assignment PIN_J1 -to sdram_dq_pad_io[6]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[6]\nset_location_assignment PIN_R7 -to sdram_dq_pad_io[7]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[7]\nset_location_assignment PIN_T4 -to sdram_dq_pad_io[8]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[8]\nset_location_assignment PIN_T2 -to sdram_dq_pad_io[9]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[9]\nset_location_assignment PIN_T3 -to sdram_dq_pad_io[10]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[10]\nset_location_assignment PIN_R3 -to sdram_dq_pad_io[11]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[11]\nset_location_assignment PIN_R5 -to sdram_dq_pad_io[12]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[12]\nset_location_assignment PIN_P3 -to sdram_dq_pad_io[13]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[13]\nset_location_assignment PIN_N3 -to sdram_dq_pad_io[14]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[14]\nset_location_assignment PIN_K1 -to sdram_dq_pad_io[15]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[15]\n\nset_location_assignment PIN_R6 -to sdram_dqm_pad_o[0]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dqm_pad_o[0]\nset_location_assignment PIN_T5 -to sdram_dqm_pad_o[1]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dqm_pad_o[1]\n\nset_location_assignment PIN_M7 -to sdram_ba_pad_o[0]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_ba_pad_o[0]\nset_location_assignment PIN_M6 -to sdram_ba_pad_o[1]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_ba_pad_o[1]\n\nset_location_assignment PIN_L1 -to sdram_cas_pad_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_cas_pad_o\n\nset_location_assignment PIN_L7 -to sdram_cke_pad_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_cke_pad_o\n\nset_location_assignment PIN_P6 -to sdram_cs_n_pad_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_cs_n_pad_o\n\nset_location_assignment PIN_L2 -to sdram_ras_pad_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_ras_pad_o\n\nset_location_assignment PIN_C2 -to sdram_we_pad_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_we_pad_o\n\nset_location_assignment PIN_R4 -to sdram_clk_pad_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_clk_pad_o\n\n#\n# GPIO0 (LEDs)\n#\nset_location_assignment PIN_A15 -to gpio0_io[0]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to gpio0_io[0]\nset_location_assignment PIN_A13 -to gpio0_io[1]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to gpio0_io[1]\nset_location_assignment PIN_B13 -to gpio0_io[2]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to gpio0_io[2]\nset_location_assignment PIN_A11 -to gpio0_io[3]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to gpio0_io[3]\nset_location_assignment PIN_D1 -to gpio0_io[4]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to gpio0_io[4]\nset_location_assignment PIN_F3 -to gpio0_io[5]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to gpio0_io[5]\nset_location_assignment PIN_B1 -to gpio0_io[6]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to gpio0_io[6]\nset_location_assignment PIN_L3 -to gpio0_io[7]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to gpio0_io[7]\n\n#============================================================\n# GPIO1 (Switches)\n#============================================================\nset_location_assignment PIN_M1 -to gpio1_i[0]\nset_location_assignment PIN_T8 -to gpio1_i[1]\nset_location_assignment PIN_B9 -to gpio1_i[2]\nset_location_assignment PIN_M15 -to gpio1_i[3]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to gpio1_i[*]\n" }, { "path": "dram_controller.core", "content": "CAPI=1\n[main]\ndescription = \"Stafford's toy dram controller for de0 nano\"\nsimulators = icarus\n\n[fileset rtl_files]\nfiles =\n rtl/dnano_interface.v\n rtl/double_click.v\n rtl/fifo.v\n rtl/sdram_controller.v\nfile_type = verilogSource\nusage = sim synth\n\n# Files only used when building the system top level\n[fileset top_files]\nscope = private\nfiles =\n rtl/toplevel.v\n quartus/pll_100m.v\n quartus/pll_1m.v\nfile_type = verilogSource\nusage = synth\n\n# File only used when building and running tests\n[fileset tb_files]\nscope = private\nfiles =\n bench/double_click_tb.v\n bench/fifo_tb.v\n bench/sdram_controller_tb.v\nfile_type = verilogSource\nusage = sim\n\n[icarus]\ndepend = vlog_tb_utils-1.0\n\n[simulator]\ndepend = vlog_tb_utils-1.0\ntoplevel = sdram_controller_tb\n\n#[provider]\n#name = github\n#user = stffrdhrn\n#repo = dram_controller\n" }, { "path": "dram_controller.system", "content": "SAPI=1\n[main]\nname = dram_controller\ndescription = \"Stafford toy dram controller for de0 Nano\"\n\nbackend = quartus\n\n[quartus]\nfamily = \"Cyclone IV E\"\ndevice = EP4CE22F17C6\ntop_module = toplevel\nsdc_files = data/de0_nano.sdc\ntcl_files = data/pinmap.tcl\n data/options.tcl\n" }, { "path": "quartus/dram_controller.qpf", "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.\n# Your use of Altera Corporation's design tools, logic functions \n# and other software and tools, and its AMPP partner logic \n# functions, and any output files from any of the foregoing \n# (including device programming or simulation files), and any \n# associated documentation or information are expressly subject \n# to the terms and conditions of the Altera Program License \n# Subscription Agreement, the Altera Quartus II License Agreement,\n# the Altera MegaCore Function License Agreement, or other \n# applicable license agreement, including, without limitation, \n# that your use is for the sole purpose of programming logic \n# devices manufactured by Altera and sold by Altera or its \n# authorized distributors. Please refer to the applicable \n# agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus II 64-Bit\n# Version 15.0.2 Build 153 07/15/2015 SJ Web Edition\n# Date created = 20:55:03 February 03, 2017\n#\n# -------------------------------------------------------------------------- #\n\nQUARTUS_VERSION = \"15.0\"\nDATE = \"20:55:03 February 03, 2017\"\n\n# Revisions\n\nPROJECT_REVISION = \"dram_controller\"\n" }, { "path": "quartus/dram_controller.qsf", "content": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.\n# Your use of Altera Corporation's design tools, logic functions \n# and other software and tools, and its AMPP partner logic \n# functions, and any output files from any of the foregoing \n# (including device programming or simulation files), and any \n# associated documentation or information are expressly subject \n# to the terms and conditions of the Altera Program License \n# Subscription Agreement, the Altera Quartus II License Agreement,\n# the Altera MegaCore Function License Agreement, or other \n# applicable license agreement, including, without limitation, \n# that your use is for the sole purpose of programming logic \n# devices manufactured by Altera and sold by Altera or its \n# authorized distributors. Please refer to the applicable \n# agreement for further details.\n#\n# -------------------------------------------------------------------------- #\n#\n# Quartus II 64-Bit\n# Version 15.0.2 Build 153 07/15/2015 SJ Web Edition\n# Date created = 20:55:03 February 03, 2017\n#\n# -------------------------------------------------------------------------- #\n#\n# Notes:\n#\n# 1) The default values for assignments are stored in the file:\n#\t\tdram_controller_assignment_defaults.qdf\n# If this file doesn't exist, see file:\n#\t\tassignment_defaults.qdf\n#\n# 2) Altera recommends that you do not modify this file. This\n# file is updated automatically by the Quartus II software\n# and any changes you make may be lost or overwritten.\n#\n# -------------------------------------------------------------------------- #\n\n\nset_global_assignment -name FAMILY \"Cyclone IV E\"\nset_global_assignment -name DEVICE EP4CE22F17C6\nset_global_assignment -name TOP_LEVEL_ENTITY toplevel\nset_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.2\nset_global_assignment -name PROJECT_CREATION_TIME_DATE \"20:55:03 FEBRUARY 03, 2017\"\nset_global_assignment -name LAST_QUARTUS_VERSION 15.0.2\nset_global_assignment -name VERILOG_FILE ../rtl/dnano_interface.v\nset_global_assignment -name VERILOG_FILE ../rtl/double_click.v\nset_global_assignment -name VERILOG_FILE ../rtl/fifo.v\nset_global_assignment -name VERILOG_FILE ../rtl/sdram_controller.v\nset_global_assignment -name VERILOG_FILE ../rtl/toplevel.v\nset_global_assignment -name VERILOG_FILE ../quartus/pll_100m.v\nset_global_assignment -name VERILOG_FILE ../quartus/pll_1m.v\nset_global_assignment -name SDC_FILE ../data/de0_nano.sdc\nset_location_assignment PIN_J15 -to rst_n_pad_i\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to rst_n_pad_i\nset_location_assignment PIN_E1 -to btn_n_pad_i\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to btn_n_pad_i\nset_location_assignment PIN_R8 -to sys_clk_pad_i\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sys_clk_pad_i\nset_location_assignment PIN_A14 -to uart0_srx_pad_i\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to uart0_srx_pad_i\nset_location_assignment PIN_B16 -to uart0_stx_pad_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to uart0_stx_pad_o\nset_location_assignment PIN_F2 -to i2c0_scl_io\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to i2c0_scl_io\nset_location_assignment PIN_F1 -to i2c0_sda_io\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to i2c0_sda_io\nset_location_assignment PIN_M2 -to accelerometer_irq_i\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to accelerometer_irq_i\nset_location_assignment PIN_G5 -to accelerometer_cs_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to accelerometer_cs_o\nset_location_assignment PIN_D15 -to i2c1_sda_io\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to i2c1_sda_io\nset_location_assignment PIN_D14 -to i2c1_scl_io\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to i2c1_scl_io\nset_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION \"USE AS REGULAR IO\"\nset_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION \"USE AS REGULAR IO\"\nset_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION \"USE AS REGULAR IO\"\nset_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION \"USE AS REGULAR IO\"\nset_location_assignment PIN_C1 -to spi0_mosi_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi0_mosi_o\nset_location_assignment PIN_H2 -to spi0_miso_i\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi0_miso_i\nset_location_assignment PIN_H1 -to spi0_sck_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi0_sck_o\nset_location_assignment PIN_D2 -to spi0_ss_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi0_ss_o\nset_location_assignment PIN_B10 -to spi1_mosi_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi1_mosi_o\nset_location_assignment PIN_A9 -to spi1_miso_i\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi1_miso_i\nset_location_assignment PIN_B14 -to spi1_sck_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi1_sck_o\nset_location_assignment PIN_A10 -to spi1_ss_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi1_ss_o\nset_location_assignment PIN_C14 -to spi2_mosi_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi2_mosi_o\nset_location_assignment PIN_C16 -to spi2_miso_i\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi2_miso_i\nset_location_assignment PIN_C15 -to spi2_sck_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi2_sck_o\nset_location_assignment PIN_D16 -to spi2_ss_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to spi2_ss_o\nset_location_assignment PIN_P2 -to sdram_a_pad_o[0]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[0]\nset_location_assignment PIN_N5 -to sdram_a_pad_o[1]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[1]\nset_location_assignment PIN_N6 -to sdram_a_pad_o[2]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[2]\nset_location_assignment PIN_M8 -to sdram_a_pad_o[3]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[3]\nset_location_assignment PIN_P8 -to sdram_a_pad_o[4]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[4]\nset_location_assignment PIN_T7 -to sdram_a_pad_o[5]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[5]\nset_location_assignment PIN_N8 -to sdram_a_pad_o[6]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[6]\nset_location_assignment PIN_T6 -to sdram_a_pad_o[7]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[7]\nset_location_assignment PIN_R1 -to sdram_a_pad_o[8]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[8]\nset_location_assignment PIN_P1 -to sdram_a_pad_o[9]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[9]\nset_location_assignment PIN_N2 -to sdram_a_pad_o[10]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[10]\nset_location_assignment PIN_N1 -to sdram_a_pad_o[11]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[11]\nset_location_assignment PIN_L4 -to sdram_a_pad_o[12]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_a_pad_o[12]\nset_location_assignment PIN_G2 -to sdram_dq_pad_io[0]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[0]\nset_location_assignment PIN_G1 -to sdram_dq_pad_io[1]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[1]\nset_location_assignment PIN_L8 -to sdram_dq_pad_io[2]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[2]\nset_location_assignment PIN_K5 -to sdram_dq_pad_io[3]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[3]\nset_location_assignment PIN_K2 -to sdram_dq_pad_io[4]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[4]\nset_location_assignment PIN_J2 -to sdram_dq_pad_io[5]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[5]\nset_location_assignment PIN_J1 -to sdram_dq_pad_io[6]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[6]\nset_location_assignment PIN_R7 -to sdram_dq_pad_io[7]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[7]\nset_location_assignment PIN_T4 -to sdram_dq_pad_io[8]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[8]\nset_location_assignment PIN_T2 -to sdram_dq_pad_io[9]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[9]\nset_location_assignment PIN_T3 -to sdram_dq_pad_io[10]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[10]\nset_location_assignment PIN_R3 -to sdram_dq_pad_io[11]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[11]\nset_location_assignment PIN_R5 -to sdram_dq_pad_io[12]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[12]\nset_location_assignment PIN_P3 -to sdram_dq_pad_io[13]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[13]\nset_location_assignment PIN_N3 -to sdram_dq_pad_io[14]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[14]\nset_location_assignment PIN_K1 -to sdram_dq_pad_io[15]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dq_pad_io[15]\nset_location_assignment PIN_R6 -to sdram_dqm_pad_o[0]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dqm_pad_o[0]\nset_location_assignment PIN_T5 -to sdram_dqm_pad_o[1]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_dqm_pad_o[1]\nset_location_assignment PIN_M7 -to sdram_ba_pad_o[0]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_ba_pad_o[0]\nset_location_assignment PIN_M6 -to sdram_ba_pad_o[1]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_ba_pad_o[1]\nset_location_assignment PIN_L1 -to sdram_cas_pad_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_cas_pad_o\nset_location_assignment PIN_L7 -to sdram_cke_pad_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_cke_pad_o\nset_location_assignment PIN_P6 -to sdram_cs_n_pad_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_cs_n_pad_o\nset_location_assignment PIN_L2 -to sdram_ras_pad_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_ras_pad_o\nset_location_assignment PIN_C2 -to sdram_we_pad_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_we_pad_o\nset_location_assignment PIN_R4 -to sdram_clk_pad_o\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to sdram_clk_pad_o\nset_location_assignment PIN_A15 -to gpio0_io[0]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to gpio0_io[0]\nset_location_assignment PIN_A13 -to gpio0_io[1]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to gpio0_io[1]\nset_location_assignment PIN_B13 -to gpio0_io[2]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to gpio0_io[2]\nset_location_assignment PIN_A11 -to gpio0_io[3]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to gpio0_io[3]\nset_location_assignment PIN_D1 -to gpio0_io[4]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to gpio0_io[4]\nset_location_assignment PIN_F3 -to gpio0_io[5]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to gpio0_io[5]\nset_location_assignment PIN_B1 -to gpio0_io[6]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to gpio0_io[6]\nset_location_assignment PIN_L3 -to gpio0_io[7]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to gpio0_io[7]\nset_location_assignment PIN_M1 -to gpio1_i[0]\nset_location_assignment PIN_T8 -to gpio1_i[1]\nset_location_assignment PIN_B9 -to gpio1_i[2]\nset_location_assignment PIN_M15 -to gpio1_i[3]\nset_instance_assignment -name IO_STANDARD \"3.3-V LVTTL\" -to gpio1_i[*]\n\nset_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\nset_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top\nset_global_assignment -name PARTITION_COLOR 16764057 -section_id Top\nset_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top" }, { "path": "quartus/pll_100m.v", "content": "// megafunction wizard: %ALTPLL%\n// GENERATION: STANDARD\n// VERSION: WM1.0\n// MODULE: altpll \n\n// ============================================================\n// File Name: pll_100m.v\n// Megafunction Name(s):\n// \t\t\taltpll\n//\n// Simulation Library Files(s):\n// \t\t\taltera_mf\n// ============================================================\n// ************************************************************\n// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\n//\n// 14.0.0 Build 200 06/17/2014 SJ Web Edition\n// ************************************************************\n\n\n//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.\n//Your use of Altera Corporation's design tools, logic functions \n//and other software and tools, and its AMPP partner logic \n//functions, and any output files from any of the foregoing \n//(including device programming or simulation files), and any \n//associated documentation or information are expressly subject \n//to the terms and conditions of the Altera Program License \n//Subscription Agreement, the Altera Quartus II License Agreement,\n//the Altera MegaCore Function License Agreement, or other \n//applicable license agreement, including, without limitation, \n//that your use is for the sole purpose of programming logic \n//devices manufactured by Altera and sold by Altera or its \n//authorized distributors. Please refer to the applicable \n//agreement for further details.\n\n\n// synopsys translate_off\n`timescale 1 ps / 1 ps\n// synopsys translate_on\nmodule pll_100m (\n\tinclk0,\n\tc0);\n\n\tinput\t inclk0;\n\toutput\t c0;\n\n\twire [0:0] sub_wire2 = 1'h0;\n\twire [4:0] sub_wire3;\n\twire sub_wire0 = inclk0;\n\twire [1:0] sub_wire1 = {sub_wire2, sub_wire0};\n\twire [0:0] sub_wire4 = sub_wire3[0:0];\n\twire c0 = sub_wire4;\n\n\taltpll\taltpll_component (\n\t\t\t\t.inclk (sub_wire1),\n\t\t\t\t.clk (sub_wire3),\n\t\t\t\t.activeclock (),\n\t\t\t\t.areset (1'b0),\n\t\t\t\t.clkbad (),\n\t\t\t\t.clkena ({6{1'b1}}),\n\t\t\t\t.clkloss (),\n\t\t\t\t.clkswitch (1'b0),\n\t\t\t\t.configupdate (1'b0),\n\t\t\t\t.enable0 (),\n\t\t\t\t.enable1 (),\n\t\t\t\t.extclk (),\n\t\t\t\t.extclkena ({4{1'b1}}),\n\t\t\t\t.fbin (1'b1),\n\t\t\t\t.fbmimicbidir (),\n\t\t\t\t.fbout (),\n\t\t\t\t.fref (),\n\t\t\t\t.icdrclk (),\n\t\t\t\t.locked (),\n\t\t\t\t.pfdena (1'b1),\n\t\t\t\t.phasecounterselect ({4{1'b1}}),\n\t\t\t\t.phasedone (),\n\t\t\t\t.phasestep (1'b1),\n\t\t\t\t.phaseupdown (1'b1),\n\t\t\t\t.pllena (1'b1),\n\t\t\t\t.scanaclr (1'b0),\n\t\t\t\t.scanclk (1'b0),\n\t\t\t\t.scanclkena (1'b1),\n\t\t\t\t.scandata (1'b0),\n\t\t\t\t.scandataout (),\n\t\t\t\t.scandone (),\n\t\t\t\t.scanread (1'b0),\n\t\t\t\t.scanwrite (1'b0),\n\t\t\t\t.sclkout0 (),\n\t\t\t\t.sclkout1 (),\n\t\t\t\t.vcooverrange (),\n\t\t\t\t.vcounderrange ());\n\tdefparam\n\t\taltpll_component.bandwidth_type = \"AUTO\",\n\t\taltpll_component.clk0_divide_by = 1,\n\t\taltpll_component.clk0_duty_cycle = 50,\n\t\taltpll_component.clk0_multiply_by = 2,\n\t\taltpll_component.clk0_phase_shift = \"0\",\n\t\taltpll_component.compensate_clock = \"CLK0\",\n\t\taltpll_component.inclk0_input_frequency = 20000,\n\t\taltpll_component.intended_device_family = \"Cyclone IV E\",\n\t\taltpll_component.lpm_hint = \"CBX_MODULE_PREFIX=pll_100m\",\n\t\taltpll_component.lpm_type = \"altpll\",\n\t\taltpll_component.operation_mode = \"NORMAL\",\n\t\taltpll_component.pll_type = \"AUTO\",\n\t\taltpll_component.port_activeclock = \"PORT_UNUSED\",\n\t\taltpll_component.port_areset = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkbad0 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkbad1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkloss = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkswitch = \"PORT_UNUSED\",\n\t\taltpll_component.port_configupdate = \"PORT_UNUSED\",\n\t\taltpll_component.port_fbin = \"PORT_UNUSED\",\n\t\taltpll_component.port_inclk0 = \"PORT_USED\",\n\t\taltpll_component.port_inclk1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_locked = \"PORT_UNUSED\",\n\t\taltpll_component.port_pfdena = \"PORT_UNUSED\",\n\t\taltpll_component.port_phasecounterselect = \"PORT_UNUSED\",\n\t\taltpll_component.port_phasedone = \"PORT_UNUSED\",\n\t\taltpll_component.port_phasestep = \"PORT_UNUSED\",\n\t\taltpll_component.port_phaseupdown = \"PORT_UNUSED\",\n\t\taltpll_component.port_pllena = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanaclr = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanclk = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanclkena = \"PORT_UNUSED\",\n\t\taltpll_component.port_scandata = \"PORT_UNUSED\",\n\t\taltpll_component.port_scandataout = \"PORT_UNUSED\",\n\t\taltpll_component.port_scandone = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanread = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanwrite = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk0 = \"PORT_USED\",\n\t\taltpll_component.port_clk1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk2 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk3 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk4 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk5 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena0 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena2 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena3 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena4 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena5 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk0 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk2 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk3 = \"PORT_UNUSED\",\n\t\taltpll_component.width_clock = 5;\n\n\nendmodule\n\n// ============================================================\n// CNX file retrieval info\n// ============================================================\n// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: BANDWIDTH STRING \"1.000\"\n// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING \"1\"\n// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING \"MHz\"\n// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING \"Low\"\n// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING \"1\"\n// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING \"0\"\n// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING \"c0\"\n// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING \"c0\"\n// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING \"6\"\n// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC \"1\"\n// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING \"50.00000000\"\n// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING \"100.000000\"\n// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING \"0\"\n// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING \"1\"\n// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING \"0\"\n// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC \"1048575\"\n// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING \"1\"\n// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING \"50.000\"\n// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING \"MHz\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING \"100.000\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING \"1\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING \"1\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING \"MHz\"\n// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING \"Cyclone IV E\"\n// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING \"1\"\n// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING \"1\"\n// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING \"Not Available\"\n// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC \"0\"\n// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING \"deg\"\n// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING \"Any\"\n// Retrieval info: PRIVATE: MIRROR_CLK0 STRING \"0\"\n// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC \"1\"\n// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING \"1\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING \"100.00000000\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING \"1\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING \"MHz\"\n// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING \"1\"\n// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING \"0.00000000\"\n// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING \"deg\"\n// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC \"1\"\n// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING \"inclk0\"\n// Retrieval info: PRIVATE: RECONFIG_FILE STRING \"pll_100m.mif\"\n// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING \"1\"\n// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING \"0\"\n// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING \"0\"\n// Retrieval info: PRIVATE: SPREAD_FREQ STRING \"50.000\"\n// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING \"KHz\"\n// Retrieval info: PRIVATE: SPREAD_PERCENT STRING \"0.500\"\n// Retrieval info: PRIVATE: SPREAD_USE STRING \"0\"\n// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: STICKY_CLK0 STRING \"1\"\n// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC \"1\"\n// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING \"1\"\n// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING \"1\"\n// Retrieval info: PRIVATE: USE_CLK0 STRING \"1\"\n// Retrieval info: PRIVATE: USE_CLKENA0 STRING \"0\"\n// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC \"0\"\n// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING \"0\"\n// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\n// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING \"AUTO\"\n// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC \"1\"\n// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC \"50\"\n// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC \"2\"\n// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING \"0\"\n// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING \"CLK0\"\n// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC \"20000\"\n// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING \"Cyclone IV E\"\n// Retrieval info: CONSTANT: LPM_TYPE STRING \"altpll\"\n// Retrieval info: CONSTANT: OPERATION_MODE STRING \"NORMAL\"\n// Retrieval info: CONSTANT: PLL_TYPE STRING \"AUTO\"\n// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_ARESET STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKLOSS STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_FBIN STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_INCLK0 STRING \"PORT_USED\"\n// Retrieval info: CONSTANT: PORT_INCLK1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_LOCKED STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PFDENA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASEDONE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASESTEP STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PLLENA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANACLR STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANCLK STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANDATA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANDONE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANREAD STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANWRITE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk0 STRING \"PORT_USED\"\n// Retrieval info: CONSTANT: PORT_clk1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk2 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk3 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk4 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk5 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena0 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena2 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena3 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena4 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena5 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk0 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk2 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk3 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC \"5\"\n// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC \"@clk[4..0]\"\n// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC \"c0\"\n// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND \"inclk0\"\n// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0\n// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0\n// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_100m.v TRUE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_100m.ppf TRUE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_100m.inc FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_100m.cmp FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_100m.bsf FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_100m_inst.v FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_100m_bb.v FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_100m_syn.v TRUE\n// Retrieval info: LIB_FILE: altera_mf\n// Retrieval info: CBX_MODULE_PREFIX: ON\n" }, { "path": "quartus/pll_1m.v", "content": "// megafunction wizard: %ALTPLL%\n// GENERATION: STANDARD\n// VERSION: WM1.0\n// MODULE: altpll \n\n// ============================================================\n// File Name: pll_1m.v\n// Megafunction Name(s):\n// \t\t\taltpll\n//\n// Simulation Library Files(s):\n// \t\t\taltera_mf\n// ============================================================\n// ************************************************************\n// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!\n//\n// 14.0.0 Build 200 06/17/2014 SJ Web Edition\n// ************************************************************\n\n\n//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.\n//Your use of Altera Corporation's design tools, logic functions \n//and other software and tools, and its AMPP partner logic \n//functions, and any output files from any of the foregoing \n//(including device programming or simulation files), and any \n//associated documentation or information are expressly subject \n//to the terms and conditions of the Altera Program License \n//Subscription Agreement, the Altera Quartus II License Agreement,\n//the Altera MegaCore Function License Agreement, or other \n//applicable license agreement, including, without limitation, \n//that your use is for the sole purpose of programming logic \n//devices manufactured by Altera and sold by Altera or its \n//authorized distributors. Please refer to the applicable \n//agreement for further details.\n\n\n// synopsys translate_off\n`timescale 1 ps / 1 ps\n// synopsys translate_on\nmodule pll_1m (\n\tinclk0,\n\tc0);\n\n\tinput\t inclk0;\n\toutput\t c0;\n\n\twire [0:0] sub_wire2 = 1'h0;\n\twire [4:0] sub_wire3;\n\twire sub_wire0 = inclk0;\n\twire [1:0] sub_wire1 = {sub_wire2, sub_wire0};\n\twire [0:0] sub_wire4 = sub_wire3[0:0];\n\twire c0 = sub_wire4;\n\n\taltpll\taltpll_component (\n\t\t\t\t.inclk (sub_wire1),\n\t\t\t\t.clk (sub_wire3),\n\t\t\t\t.activeclock (),\n\t\t\t\t.areset (1'b0),\n\t\t\t\t.clkbad (),\n\t\t\t\t.clkena ({6{1'b1}}),\n\t\t\t\t.clkloss (),\n\t\t\t\t.clkswitch (1'b0),\n\t\t\t\t.configupdate (1'b0),\n\t\t\t\t.enable0 (),\n\t\t\t\t.enable1 (),\n\t\t\t\t.extclk (),\n\t\t\t\t.extclkena ({4{1'b1}}),\n\t\t\t\t.fbin (1'b1),\n\t\t\t\t.fbmimicbidir (),\n\t\t\t\t.fbout (),\n\t\t\t\t.fref (),\n\t\t\t\t.icdrclk (),\n\t\t\t\t.locked (),\n\t\t\t\t.pfdena (1'b1),\n\t\t\t\t.phasecounterselect ({4{1'b1}}),\n\t\t\t\t.phasedone (),\n\t\t\t\t.phasestep (1'b1),\n\t\t\t\t.phaseupdown (1'b1),\n\t\t\t\t.pllena (1'b1),\n\t\t\t\t.scanaclr (1'b0),\n\t\t\t\t.scanclk (1'b0),\n\t\t\t\t.scanclkena (1'b1),\n\t\t\t\t.scandata (1'b0),\n\t\t\t\t.scandataout (),\n\t\t\t\t.scandone (),\n\t\t\t\t.scanread (1'b0),\n\t\t\t\t.scanwrite (1'b0),\n\t\t\t\t.sclkout0 (),\n\t\t\t\t.sclkout1 (),\n\t\t\t\t.vcooverrange (),\n\t\t\t\t.vcounderrange ());\n\tdefparam\n\t\taltpll_component.bandwidth_type = \"AUTO\",\n\t\taltpll_component.clk0_divide_by = 50,\n\t\taltpll_component.clk0_duty_cycle = 50,\n\t\taltpll_component.clk0_multiply_by = 1,\n\t\taltpll_component.clk0_phase_shift = \"0\",\n\t\taltpll_component.compensate_clock = \"CLK0\",\n\t\taltpll_component.inclk0_input_frequency = 20000,\n\t\taltpll_component.intended_device_family = \"Cyclone IV E\",\n\t\taltpll_component.lpm_hint = \"CBX_MODULE_PREFIX=pll_1m\",\n\t\taltpll_component.lpm_type = \"altpll\",\n\t\taltpll_component.operation_mode = \"NORMAL\",\n\t\taltpll_component.pll_type = \"AUTO\",\n\t\taltpll_component.port_activeclock = \"PORT_UNUSED\",\n\t\taltpll_component.port_areset = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkbad0 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkbad1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkloss = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkswitch = \"PORT_UNUSED\",\n\t\taltpll_component.port_configupdate = \"PORT_UNUSED\",\n\t\taltpll_component.port_fbin = \"PORT_UNUSED\",\n\t\taltpll_component.port_inclk0 = \"PORT_USED\",\n\t\taltpll_component.port_inclk1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_locked = \"PORT_UNUSED\",\n\t\taltpll_component.port_pfdena = \"PORT_UNUSED\",\n\t\taltpll_component.port_phasecounterselect = \"PORT_UNUSED\",\n\t\taltpll_component.port_phasedone = \"PORT_UNUSED\",\n\t\taltpll_component.port_phasestep = \"PORT_UNUSED\",\n\t\taltpll_component.port_phaseupdown = \"PORT_UNUSED\",\n\t\taltpll_component.port_pllena = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanaclr = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanclk = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanclkena = \"PORT_UNUSED\",\n\t\taltpll_component.port_scandata = \"PORT_UNUSED\",\n\t\taltpll_component.port_scandataout = \"PORT_UNUSED\",\n\t\taltpll_component.port_scandone = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanread = \"PORT_UNUSED\",\n\t\taltpll_component.port_scanwrite = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk0 = \"PORT_USED\",\n\t\taltpll_component.port_clk1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk2 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk3 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk4 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clk5 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena0 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena2 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena3 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena4 = \"PORT_UNUSED\",\n\t\taltpll_component.port_clkena5 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk0 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk1 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk2 = \"PORT_UNUSED\",\n\t\taltpll_component.port_extclk3 = \"PORT_UNUSED\",\n\t\taltpll_component.width_clock = 5;\n\n\nendmodule\n\n// ============================================================\n// CNX file retrieval info\n// ============================================================\n// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: BANDWIDTH STRING \"1.000\"\n// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING \"1\"\n// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING \"MHz\"\n// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING \"Low\"\n// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING \"1\"\n// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING \"0\"\n// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING \"c0\"\n// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING \"c0\"\n// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING \"6\"\n// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC \"1\"\n// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING \"50.00000000\"\n// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING \"1.000000\"\n// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING \"0\"\n// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING \"1\"\n// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING \"0\"\n// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC \"1048575\"\n// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING \"1\"\n// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING \"50.000\"\n// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING \"MHz\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING \"100.000\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING \"1\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING \"1\"\n// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING \"MHz\"\n// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING \"Cyclone IV E\"\n// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING \"1\"\n// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING \"1\"\n// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING \"Not Available\"\n// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC \"0\"\n// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING \"deg\"\n// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING \"Any\"\n// Retrieval info: PRIVATE: MIRROR_CLK0 STRING \"0\"\n// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC \"1\"\n// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING \"1\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING \"1.00000000\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING \"1\"\n// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING \"MHz\"\n// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING \"1\"\n// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING \"0.00000000\"\n// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING \"deg\"\n// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC \"1\"\n// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC \"0\"\n// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING \"inclk0\"\n// Retrieval info: PRIVATE: RECONFIG_FILE STRING \"pll_1m.mif\"\n// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING \"0\"\n// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING \"1\"\n// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING \"0\"\n// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING \"0\"\n// Retrieval info: PRIVATE: SPREAD_FREQ STRING \"50.000\"\n// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING \"KHz\"\n// Retrieval info: PRIVATE: SPREAD_PERCENT STRING \"0.500\"\n// Retrieval info: PRIVATE: SPREAD_USE STRING \"0\"\n// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING \"0\"\n// Retrieval info: PRIVATE: STICKY_CLK0 STRING \"1\"\n// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC \"1\"\n// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING \"1\"\n// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING \"0\"\n// Retrieval info: PRIVATE: USE_CLK0 STRING \"1\"\n// Retrieval info: PRIVATE: USE_CLKENA0 STRING \"0\"\n// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC \"0\"\n// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING \"0\"\n// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\n// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING \"AUTO\"\n// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC \"50\"\n// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC \"50\"\n// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC \"1\"\n// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING \"0\"\n// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING \"CLK0\"\n// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC \"20000\"\n// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING \"Cyclone IV E\"\n// Retrieval info: CONSTANT: LPM_TYPE STRING \"altpll\"\n// Retrieval info: CONSTANT: OPERATION_MODE STRING \"NORMAL\"\n// Retrieval info: CONSTANT: PLL_TYPE STRING \"AUTO\"\n// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_ARESET STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKLOSS STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_FBIN STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_INCLK0 STRING \"PORT_USED\"\n// Retrieval info: CONSTANT: PORT_INCLK1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_LOCKED STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PFDENA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASEDONE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASESTEP STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_PLLENA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANACLR STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANCLK STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANDATA STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANDONE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANREAD STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_SCANWRITE STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk0 STRING \"PORT_USED\"\n// Retrieval info: CONSTANT: PORT_clk1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk2 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk3 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk4 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clk5 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena0 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena2 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena3 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena4 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_clkena5 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk0 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk1 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk2 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: PORT_extclk3 STRING \"PORT_UNUSED\"\n// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC \"5\"\n// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC \"@clk[4..0]\"\n// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC \"c0\"\n// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND \"inclk0\"\n// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0\n// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0\n// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_1m.v TRUE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_1m.ppf TRUE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_1m.inc FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_1m.cmp FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_1m.bsf FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_1m_inst.v FALSE\n// Retrieval info: GEN_FILE: TYPE_NORMAL pll_1m_bb.v FALSE\n// Retrieval info: LIB_FILE: altera_mf\n// Retrieval info: CBX_MODULE_PREFIX: ON\n" }, { "path": "quartus/vsim-wave.do", "content": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate -radix binary /init_tb/haddr\nadd wave -noupdate /init_tb/data_input\nadd wave -noupdate /init_tb/data_output\nadd wave -noupdate /init_tb/busy\nadd wave -noupdate /init_tb/rd_enable\nadd wave -noupdate /init_tb/wr_enable\nadd wave -noupdate /init_tb/rst_n\nadd wave -noupdate /init_tb/clk\nadd wave -noupdate -radix hexadecimal /init_tb/addr\nadd wave -noupdate /init_tb/bank_addr\nadd wave -noupdate /init_tb/data\nadd wave -noupdate /init_tb/clock_enable\nadd wave -noupdate /init_tb/cs_n\nadd wave -noupdate /init_tb/ras_n\nadd wave -noupdate /init_tb/cas_n\nadd wave -noupdate /init_tb/we_n\nadd wave -noupdate /init_tb/data_mask_low\nadd wave -noupdate /init_tb/data_mask_high\nadd wave -noupdate /init_tb/sdram_controlleri/data_input_r\nadd wave -noupdate /init_tb/sdram_controlleri/data_output_r\nadd wave -noupdate -radix unsigned /init_tb/sdram_controlleri/state_cnt\nadd wave -noupdate -radix unsigned /init_tb/sdram_controlleri/refresh_cnt\nadd wave -noupdate /init_tb/sdram_controlleri/state\nTreeUpdate [SetDefaultTree]\nWaveRestoreCursors {{Cursor 1} {270 ps} 0}\nquietly wave cursor active 1\nconfigure wave -namecolwidth 289\nconfigure wave -valuecolwidth 132\nconfigure wave -justifyvalue left\nconfigure wave -signalnamewidth 0\nconfigure wave -snapdistance 10\nconfigure wave -datasetprefix 0\nconfigure wave -rowmargin 4\nconfigure wave -childrowmargin 2\nconfigure wave -gridoffset 0\nconfigure wave -gridperiod 1\nconfigure wave -griddelta 40\nconfigure wave -timeline 0\nconfigure wave -timelineunits ps\nupdate\nWaveRestoreZoom {0 ps} {110 ps}\n" }, { "path": "readme.md", "content": "# _SDRAM Memory Controller_\n\n`CURRENT STATUS : stable`\n\nThis is a very a simple sdram controller which works on the De0 Nano. The project\nalso contains a simple push button interface for testing on the dev board.\n\nBasic features\n - Operates at 100Mhz, CAS 3, 32MB, 16-bit data\n - On reset will go into `INIT` sequnce\n - After `INIT` the controller sits in `IDLE` waiting for `REFRESH`, `READ` or `WRITE` \n - `REFRESH` operations are spaced evenly 8192 times every 32ms\n - `READ` is always single read with auto precharge\n - `WRITE` is always single write with auto precharge\n\n```\n\n Host Interface SDRAM Interface\n\n /-----------------------------\\\n | sdram_controller |\n==> wr_addr addr ==>\n==> wr_data bank_addr ==>\n--> wr_enable data <=>\n | clock_enable -->\n==> rd_addr cs_n --> \n--> rd_enable ras_n -->\n<== rd_data cas_n -->\n<-- rd_ready we_n -->\n<-- busy data_mask_low --> \n | data_mask_high -->\n--> rst_n |\n--> clk |\n \\-----------------------------/\n\n```\n\nFrom the above diagram most signals should be pretty much self explainatory. Here are some important points for now. It will be expanded on later. \n - `wr_addr` and `rd_addr` are equivelant to the concatenation of `{bank, row, column}`\n - `rd_enable` should be set to high once an address is presented on the `addr` bus and we wish to read data. \n - `wr_enable` should be set to high once `addr` and `data` is presented on the bus\n - `busy` will go high when the read or write command is acknowledged. `busy` will go low when the write or read operation is complete. \n - `rd_ready` will go high when data `rd_data` is available on the `data` bus.\n - **NOTE** For single reads and writes `wr_enable` and `rd_enable` should be set low once `busy` is observed. This will protect from the controller thinking another request is needed if left higher any longer. \n\n## Build\n\nThe recommended way to build is to use `fusesoc`. The build steps are then:\n\n```\n# Build the project with quartus\nfusesoc build dram_controller\n# Program the project to de0 nano\nfusesoc pgm dram_controller\n\n# Build with icarus verilog and test\nfusesoc sim dram_controller --vcd\ngtkwave $fusebuild/dram_controller/sim-icarus/testlog.vcd\n\n# Run other test cases \nfusesoc sim --testbench fifo_tb dram_controller --vcd\nfusesoc sim --testbench double_click_tb dram_controller --vcd\n```\n\n\n## Timings\n\n# Initialization\n![wave init](https://raw.githubusercontent.com/stffrdhrn/sdram-controller/master/readme/wave-init.png)\n\nInitialization process showing:\n - Precharge all banks\n - 2 refresh cycles\n - Mode programming\n\n# Refresh\n![wave refresh](https://raw.githubusercontent.com/stffrdhrn/sdram-controller/master/readme/wave-refresh.png)\n\nRefresh process showing:\n - Precharge all banks\n - Single Refresh \n\n# Writes\n![wave write](https://raw.githubusercontent.com/stffrdhrn/sdram-controller/master/readme/wave-write.png)\n\nWrite operation showing:\n - Bank Activation & Row Address Strobe\n - Column Address Strobe with Auto Precharge set and Data on bus\n\n# Reads\n![wave read](https://raw.githubusercontent.com/stffrdhrn/sdram-controller/master/readme/wave-read.png)\n\nRead operation showing:\n - Bank Activation & Row Address Strobe\n - Column Address Strobe with Auto Precharge set\n - Data on bus\n\n\n## Test Application\n\n![Test Application](https://raw.githubusercontent.com/stffrdhrn/sdram-controller/master/readme/block.png)\n*Figure - test application block diagram*\n\nThe test application provides a simple user interface for testing the functionality\nof the sdram controller. \n\nBasics:\n - The clock input should be 50Mhz (a pll multiplies it up to 100Mhz)\n - One push button is used for `reset`\n - A Second push button is used for `read` and `write`\n - single click for `write`\n - double click for `read`\n - A 4-bit dip switch is used for inputting addresses and data \n - Upon `reset` the read/write addresses are read from the dip switch\n - When `writing` the dip switch is data is written to the sdram\n - Address and data busses are greather than 4 bits, data is duplicated to fill the bus \n - 8 LEDs are used to display the data read from the sdram. The data but is 16-bits, high and low bytes are alternated on the LEDs about every half second. \n\n## Project Status/TODO\n - [x] Compiles\n - [x] Simulated `Init`\n - [x] Simulated `Refresh`\n - [x] Simulated `Read`\n - [x] Simulated `Write`\n - [x] Confirmed in De0 Nano\n\n\n## Project Setup\nThis project has been developed with altera quartus II. \n\n## License\nBSD\n\n## Further Reading\nI didn't look at these when designing my controller. But it might be good to take a look at for ideas. \n - http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller - featured on hackaday\n - http://ladybug.xs4all.nl/arlet/fpga/source/sdram.v - Arlet's implementation from a comment on the hackaday article\n" }, { "path": "rtl/dnano_interface.v", "content": "/* De0 Nano interface for testing sdram controller \n * Handles interpreting buttons and switches \n * to talk to the sdram controller.\n */\n\nmodule dnano_interface (\n /* Human Interface */\n button_n, dip, leds,\n\n /* Controller Interface */\n haddr, // RW-FIFO- data1\n busy, // RW-FIFO- full\n \n wr_enable, // WR-FIFO- write\n wr_data, // WR-FIFO- data2\n \n rd_enable, //RO-FIFO- write\n \n rd_data, //RI-FIFO- data\n rd_rdy, // RI-FIFO-~empty\n rd_ack, // RI-FIFO- read\n\n /* basics */\n rst_n, clk\n\n);\n\nparameter HADDR_WIDTH = 24;\n\n// @ 1mhz 19bit (512K) is about 1/2 second\n// @ 100mhz 26bit (64M) is about 1/2 second\nlocalparam DOUBlE_CLICK_WAIT = 19;\nlocalparam LED_BLINK = 20;\n \ninput button_n;\ninput [3:0] dip;\noutput [7:0] leds;\n\noutput [HADDR_WIDTH-1:0] haddr;\noutput [15:0] wr_data;\ninput [15:0] rd_data;\ninput busy;\noutput rd_enable;\ninput rd_rdy;\noutput rd_ack;\noutput wr_enable;\n\ninput rst_n;\ninput clk;\n\nwire [15:0] wr_data;\nreg [15:0] rd_data_r;\nreg [LED_BLINK-1:0] led_cnt;\nwire [7:0] leds;\nwire wr_enable;\nreg rd_ack_r;\n\nwire dbl_clck_rst_n;\n\n// When to reset the double click output\n// we want to reset after we know the sdram is busy\n// busy | rst_n\n// 0 0 - reset is on (be-low )\n// 0 1 - reset is off (be high)\n// 1 0 - busy + reset (be-low)\n// 1 1 - busy is on (be-low)\nassign dbl_clck_rst_n = rst_n & ~busy;\n\n// expand the dip data from 4 to 16 bits\nassign wr_data = {dip, dip, ~dip, ~dip};\n// toggle leds between sdram msb and lsb\nassign leds = led_cnt[LED_BLINK-1] ? rd_data_r[15:8] : rd_data_r[7:0]; \n\nassign haddr = {(HADDR_WIDTH/4){dip}};\nassign rd_ack = rd_ack_r;\n\n// handle led counter should just loop every half second\nalways @ (posedge clk) \n if (~rst_n) \n led_cnt <= {LED_BLINK{1'b0}};\n else\n led_cnt <= led_cnt + 1'b1;\n \n\nalways @ (posedge clk)\n if (~rst_n)\n begin\n rd_data_r <= 16'b0;\n rd_ack_r <= 1'b0;\n end\n else\n begin \n rd_ack_r <= rd_rdy;\n \n if (rd_rdy)\n rd_data_r <= rd_data;\n else \n rd_data_r <= rd_data_r;\n end\n \ndouble_click #(.WAIT_WIDTH(DOUBlE_CLICK_WAIT)) double_clicki (\n .button (~button_n),\n .single (wr_enable),\n .double (rd_enable), \n .clk (clk),\n .rst_n (dbl_clck_rst_n)\n);\n\nendmodule\n" }, { "path": "rtl/double_click.v", "content": "/* Input is a button \n * Detect if the button is double clicked or single clicked in \n * a time interval. Outputs are maintained until reset. \n */\n\nmodule double_click (\n button, \n\n single, double, \n\n clk, rst_n\n);\n\nparameter WAIT_WIDTH = 19;\n\ninput button;\noutput single, double;\ninput clk, rst_n;\n\nreg btn_now, btn_last, collect;\n\nreg [2:0] click_cnt;\nreg [WAIT_WIDTH-1:0] dbl_click_cnt;\n\n// if we are done counting and we have 1 click its single, else double\nassign single = (!dbl_click_cnt & (click_cnt == 3'b001)) ? 1'b1 : 1'b0;\nassign double = (!dbl_click_cnt & (click_cnt != 3'b001)) ? 1'b1 : 1'b0;\n\n// detect button down vs button up\nwire btn_down = btn_now & ~btn_last;\n//wire btn_up = ~btn_now & btn_last;\nalways @ (negedge clk)\n if (~rst_n) \n { btn_last, btn_now } <= 2'b00;\n else\n { btn_last, btn_now } <= { btn_now, button };\n\n// start down counter and count clicks\nalways @ (posedge clk) \n if (~rst_n)\n begin\n click_cnt <= 3'd0;\n dbl_click_cnt <= {WAIT_WIDTH{1'b1}};\n collect <= 1'b0;\n end\n else\n begin\n if (collect & (dbl_click_cnt != {WAIT_WIDTH{1'b0}})) \n dbl_click_cnt <= dbl_click_cnt - 1'b1;\n else\n dbl_click_cnt <= dbl_click_cnt;\n \n if (btn_down)\n begin\n collect <= 1'b1;\n click_cnt <= click_cnt + 1'b1;\n end\n else\n begin\n collect <= collect;\n click_cnt <= click_cnt;\n end \n end\n\nendmodule\n" }, { "path": "rtl/fifo.v", "content": "/*\n * This is a 2 clock fifo used for transferring data between\n * clock domains. \n * \n * I assume here that the output (read) clock is >5X slower than the\n * input (write) clock.\n *\n * Also, the fifo is just 1 word deep. \n *\n * Changes\n * - 2015-07-03 issue when writing from low speed clock, empty_n goes\n * high and stays high. The reader side will see and read, but\n * after complete empty_n is still high. It will continue\n * to read until empty_n is lowered based on the write side\n * clock.\n * The empty_n should go low once the reader reads.\n *\n */\nmodule fifo (\n // Write side\n wr_clk,\n wr_data, \n wr,\n full, // means don't write any more\n \n // Read side\n rd_data,\n rd_clk,\n rd,\n empty_n, // also means we can read\n \n rst_n\n);\n\nparameter BUS_WIDTH = 16;\n\ninput [BUS_WIDTH-1:0] wr_data;\ninput wr_clk;\ninput wr;\noutput full; // Low-Means in side can write\n\noutput [BUS_WIDTH-1:0] rd_data; \ninput rd_clk;\ninput rd;\noutput empty_n; // High-Means out side can read\n\ninput rst_n;\n\nreg [BUS_WIDTH-1:0] wr_data_r;\nreg [BUS_WIDTH-1:0] rd_data;\n\n/* \n * these reg sets span accross 2 clock domtains\n * CLK WR | CLK RD\n * [wr_r] ------------------> | -> [wr_syn1] -> [wr_syn2] -\\\n * <- [wr_ack2] <- [wr_ack1] | ---------------------------/\n * ^^^^^^^^^^ | \n * Set wr_r when we get a wr | increment counter when we get\n * Clr wr when we get wr_ack2 | wr_syn2, and syncronize data\n * \n */\nreg wr_r, wr_syn1, wr_syn2, wr_ack1, wr_ack2;\nreg rd_r, rd_syn1, rd_syn2, rd_ack1, rd_ack2;\nreg wr_fifo_cnt;\nreg rd_fifo_cnt;\n\nassign full = wr_fifo_cnt == 1'b1;\nassign empty_n = rd_fifo_cnt == 1'b1;\n\nalways @ (posedge rd_clk)\n if (~rst_n)\n begin\n rd_fifo_cnt <= 1'b0;\n {rd_ack2, rd_ack1} <= 2'b00; \n {wr_syn2, wr_syn1} <= 2'b00; \n end\n else\n begin\n \n {rd_ack2, rd_ack1} <= {rd_ack1, rd_syn2}; \n {wr_syn2, wr_syn1} <= {wr_syn1, wr_r}; \n \n if (rd)\n rd_r <= 1'b1;\n else if (rd_ack2)\n rd_r <= 1'b0;\n \n if (rd)\n rd_fifo_cnt <= 1'b0;\n if ({wr_syn2, wr_syn1} == 2'b01) // if we want to just do increment 1 time, we can check posedge\n rd_fifo_cnt <= 1'b1;\n \n if (wr_syn2)\n rd_data <= wr_data_r;\n end\n \nalways @ (posedge wr_clk)\n if (~rst_n)\n begin\n wr_fifo_cnt <= 1'b0;\n {rd_syn2, rd_syn1} <= 2'b00;\n {wr_ack2, wr_ack1} <= 2'b00;\n end\n else\n begin\n {wr_ack2, wr_ack1} <= {wr_ack1, wr_syn2}; \n {rd_syn2, rd_syn1} <= {rd_syn1, rd_r};\n \n if (wr)\n wr_r <= 1'b1;\n if (wr_ack2)\n wr_r <= 1'b0;\n \n if (wr)\n wr_fifo_cnt <= 1'b1;\n if ({rd_syn2, rd_syn1} == 2'b01)\n wr_fifo_cnt <= 1'b0;\n \n // register write data on write\n if (wr)\n wr_data_r <= wr_data;\n\n end\n\n\nendmodule" }, { "path": "rtl/sdram_controller.v", "content": "/**\n * simple controller for ISSI IS42S16160G-7 SDRAM found in De0 Nano\n * 16Mbit x 16 data bit bus (32 megabytes)\n * Default options\n * 133Mhz\n * CAS 3\n *\n * Very simple host interface\n * * No burst support\n * * haddr - address for reading and wriging 16 bits of data\n * * data_input - data for writing, latched in when wr_enable is highz0\n * * data_output - data for reading, comes available sometime\n * *few clocks* after rd_enable and address is presented on bus\n * * rst_n - start init ram process\n * * rd_enable - read enable, on clk posedge haddr will be latched in,\n * after *few clocks* data will be available on the data_output port\n * * wr_enable - write enable, on clk posedge haddr and data_input will\n * be latched in, after *few clocks* data will be written to sdram\n *\n * Theory\n * This simple host interface has a busy signal to tell you when you are\n * not able to issue commands.\n */\n\nmodule sdram_controller (\n /* HOST INTERFACE */\n wr_addr,\n wr_data,\n wr_enable,\n\n rd_addr,\n rd_data,\n rd_ready,\n rd_enable,\n\n busy, rst_n, clk,\n\n /* SDRAM SIDE */\n addr, bank_addr, data, clock_enable, cs_n, ras_n, cas_n, we_n,\n data_mask_low, data_mask_high\n);\n\n/* Internal Parameters */\nparameter ROW_WIDTH = 13;\nparameter COL_WIDTH = 9;\nparameter BANK_WIDTH = 2;\n\nparameter SDRADDR_WIDTH = ROW_WIDTH > COL_WIDTH ? ROW_WIDTH : COL_WIDTH;\nparameter HADDR_WIDTH = BANK_WIDTH + ROW_WIDTH + COL_WIDTH;\n\nparameter CLK_FREQUENCY = 133; // Mhz\nparameter REFRESH_TIME = 32; // ms (how often we need to refresh)\nparameter REFRESH_COUNT = 8192; // cycles (how many refreshes required per refresh time)\n\n// clk / refresh = clk / sec\n// , sec / refbatch\n// , ref / refbatch\nlocalparam CYCLES_BETWEEN_REFRESH = ( CLK_FREQUENCY\n * 1_000\n * REFRESH_TIME\n ) / REFRESH_COUNT;\n\n// STATES - State\nlocalparam IDLE = 5'b00000;\n\nlocalparam INIT_NOP1 = 5'b01000,\n INIT_PRE1 = 5'b01001,\n INIT_NOP1_1=5'b00101,\n INIT_REF1 = 5'b01010,\n INIT_NOP2 = 5'b01011,\n INIT_REF2 = 5'b01100,\n INIT_NOP3 = 5'b01101,\n INIT_LOAD = 5'b01110,\n INIT_NOP4 = 5'b01111;\n\nlocalparam REF_PRE = 5'b00001,\n REF_NOP1 = 5'b00010,\n REF_REF = 5'b00011,\n REF_NOP2 = 5'b00100;\n\nlocalparam READ_ACT = 5'b10000,\n READ_NOP1 = 5'b10001,\n READ_CAS = 5'b10010,\n READ_NOP2 = 5'b10011,\n READ_READ = 5'b10100;\n\nlocalparam WRIT_ACT = 5'b11000,\n WRIT_NOP1 = 5'b11001,\n WRIT_CAS = 5'b11010,\n WRIT_NOP2 = 5'b11011;\n\n// Commands CCRCWBBA\n// ESSSE100\nlocalparam CMD_PALL = 8'b10010001,\n CMD_REF = 8'b10001000,\n CMD_NOP = 8'b10111000,\n CMD_MRS = 8'b1000000x,\n CMD_BACT = 8'b10011xxx,\n CMD_READ = 8'b10101xx1,\n CMD_WRIT = 8'b10100xx1;\n\n/* Interface Definition */\n/* HOST INTERFACE */\ninput [HADDR_WIDTH-1:0] wr_addr;\ninput [15:0] wr_data;\ninput wr_enable;\n\ninput [HADDR_WIDTH-1:0] rd_addr;\noutput [15:0] rd_data;\ninput rd_enable;\noutput rd_ready;\n\noutput busy;\ninput rst_n;\ninput clk;\n\n/* SDRAM SIDE */\noutput [SDRADDR_WIDTH-1:0] addr;\noutput [BANK_WIDTH-1:0] bank_addr;\ninout [15:0] data;\noutput clock_enable;\noutput cs_n;\noutput ras_n;\noutput cas_n;\noutput we_n;\noutput data_mask_low;\noutput data_mask_high;\n\n/* I/O Registers */\n\nreg [HADDR_WIDTH-1:0] haddr_r;\nreg [15:0] wr_data_r;\nreg [15:0] rd_data_r;\nreg busy;\nreg data_mask_low_r;\nreg data_mask_high_r;\nreg [SDRADDR_WIDTH-1:0] addr_r;\nreg [BANK_WIDTH-1:0] bank_addr_r;\nreg rd_ready_r;\n\nwire [15:0] data_output;\nwire data_mask_low, data_mask_high;\n\nassign data_mask_high = data_mask_high_r;\nassign data_mask_low = data_mask_low_r;\nassign rd_data = rd_data_r;\n\n/* Internal Wiring */\nreg [3:0] state_cnt;\nreg [9:0] refresh_cnt;\n\nreg [7:0] command;\nreg [4:0] state;\n\n// TODO output addr[6:4] when programming mode register\n\nreg [7:0] command_nxt;\nreg [3:0] state_cnt_nxt;\nreg [4:0] next;\n\nassign {clock_enable, cs_n, ras_n, cas_n, we_n} = command[7:3];\n// state[4] will be set if mode is read/write\nassign bank_addr = (state[4]) ? bank_addr_r : command[2:1];\nassign addr = (state[4] | state == INIT_LOAD) ? addr_r : { {SDRADDR_WIDTH-11{1'b0}}, command[0], 10'd0 };\n\nassign data = (state == WRIT_CAS) ? wr_data_r : 16'bz;\nassign rd_ready = rd_ready_r;\n\n// HOST INTERFACE\n// all registered on posedge\nalways @ (posedge clk)\n if (~rst_n)\n begin\n state <= INIT_NOP1;\n command <= CMD_NOP;\n state_cnt <= 4'hf;\n\n haddr_r <= {HADDR_WIDTH{1'b0}};\n wr_data_r <= 16'b0;\n rd_data_r <= 16'b0;\n busy <= 1'b0;\n end\n else\n begin\n\n state <= next;\n command <= command_nxt;\n\n if (!state_cnt)\n state_cnt <= state_cnt_nxt;\n else\n state_cnt <= state_cnt - 1'b1;\n\n if (wr_enable)\n wr_data_r <= wr_data;\n\n if (state == READ_READ)\n begin\n rd_data_r <= data;\n rd_ready_r <= 1'b1;\n end\n else\n rd_ready_r <= 1'b0;\n\n busy <= state[4];\n\n if (rd_enable)\n haddr_r <= rd_addr;\n else if (wr_enable)\n haddr_r <= wr_addr;\n\n end\n\n// Handle refresh counter\nalways @ (posedge clk)\n if (~rst_n)\n refresh_cnt <= 10'b0;\n else\n if (state == REF_NOP2)\n refresh_cnt <= 10'b0;\n else\n refresh_cnt <= refresh_cnt + 1'b1;\n\n\n/* Handle logic for sending addresses to SDRAM based on current state*/\nalways @*\nbegin\n if (state[4])\n {data_mask_low_r, data_mask_high_r} = 2'b00;\n else\n {data_mask_low_r, data_mask_high_r} = 2'b11;\n\n bank_addr_r = 2'b00;\n addr_r = {SDRADDR_WIDTH{1'b0}};\n\n if (state == READ_ACT | state == WRIT_ACT)\n begin\n bank_addr_r = haddr_r[HADDR_WIDTH-1:HADDR_WIDTH-(BANK_WIDTH)];\n addr_r = haddr_r[HADDR_WIDTH-(BANK_WIDTH+1):HADDR_WIDTH-(BANK_WIDTH+ROW_WIDTH)];\n end\n else if (state == READ_CAS | state == WRIT_CAS)\n begin\n // Send Column Address\n // Set bank to bank to precharge\n bank_addr_r = haddr_r[HADDR_WIDTH-1:HADDR_WIDTH-(BANK_WIDTH)];\n\n // Examples for math\n // BANK ROW COL\n // HADDR_WIDTH 2 + 13 + 9 = 24\n // SDRADDR_WIDTH 13\n\n // Set CAS address to:\n // 0s,\n // 1 (A10 is always for auto precharge),\n // 0s,\n // column address\n addr_r = {\n {SDRADDR_WIDTH-(11){1'b0}},\n 1'b1, /* A10 */\n {10-COL_WIDTH{1'b0}},\n haddr_r[COL_WIDTH-1:0]\n };\n end\n else if (state == INIT_LOAD)\n begin\n // Program mode register during load cycle\n // B C SB\n // R A EUR\n // S S-3Q ST\n // T 654L210\n addr_r = {{SDRADDR_WIDTH-10{1'b0}}, 10'b1000110000};\n end\nend\n\n// Next state logic\nalways @*\nbegin\n state_cnt_nxt = 4'd0;\n command_nxt = CMD_NOP;\n if (state == IDLE)\n // Monitor for refresh or hold\n if (refresh_cnt >= CYCLES_BETWEEN_REFRESH)\n begin\n next = REF_PRE;\n command_nxt = CMD_PALL;\n end\n else if (rd_enable)\n begin\n next = READ_ACT;\n command_nxt = CMD_BACT;\n end\n else if (wr_enable)\n begin\n next = WRIT_ACT;\n command_nxt = CMD_BACT;\n end\n else\n begin\n // HOLD\n next = IDLE;\n end\n else\n if (!state_cnt)\n case (state)\n // INIT ENGINE\n INIT_NOP1:\n begin\n next = INIT_PRE1;\n command_nxt = CMD_PALL;\n end\n INIT_PRE1:\n begin\n next = INIT_NOP1_1;\n end\n INIT_NOP1_1:\n begin\n next = INIT_REF1;\n command_nxt = CMD_REF;\n end\n INIT_REF1:\n begin\n next = INIT_NOP2;\n state_cnt_nxt = 4'd7;\n end\n INIT_NOP2:\n begin\n next = INIT_REF2;\n command_nxt = CMD_REF;\n end\n INIT_REF2:\n begin\n next = INIT_NOP3;\n state_cnt_nxt = 4'd7;\n end\n INIT_NOP3:\n begin\n next = INIT_LOAD;\n command_nxt = CMD_MRS;\n end\n INIT_LOAD:\n begin\n next = INIT_NOP4;\n state_cnt_nxt = 4'd1;\n end\n // INIT_NOP4: default - IDLE\n\n // REFRESH\n REF_PRE:\n begin\n next = REF_NOP1;\n end\n REF_NOP1:\n begin\n next = REF_REF;\n command_nxt = CMD_REF;\n end\n REF_REF:\n begin\n next = REF_NOP2;\n state_cnt_nxt = 4'd7;\n end\n // REF_NOP2: default - IDLE\n\n // WRITE\n WRIT_ACT:\n begin\n next = WRIT_NOP1;\n state_cnt_nxt = 4'd1;\n end\n WRIT_NOP1:\n begin\n next = WRIT_CAS;\n command_nxt = CMD_WRIT;\n end\n WRIT_CAS:\n begin\n next = WRIT_NOP2;\n state_cnt_nxt = 4'd1;\n end\n // WRIT_NOP2: default - IDLE\n\n // READ\n READ_ACT:\n begin\n next = READ_NOP1;\n state_cnt_nxt = 4'd1;\n end\n READ_NOP1:\n begin\n next = READ_CAS;\n command_nxt = CMD_READ;\n end\n READ_CAS:\n begin\n next = READ_NOP2;\n state_cnt_nxt = 4'd1;\n end\n READ_NOP2:\n begin\n next = READ_READ;\n end\n // READ_READ: default - IDLE\n\n default:\n begin\n next = IDLE;\n end\n endcase\n else\n begin\n // Counter Not Reached - HOLD\n next = state;\n command_nxt = command;\n end\nend\n\nendmodule\n" }, { "path": "rtl/toplevel.sdc", "content": "create_clock -period \"20ns\" CLOCK_50\nderive_pll_clocks\nderive_clock_uncertainty\n" }, { "path": "rtl/toplevel.v", "content": "//////////////////////////////////////////////////////////////////////\n//\n// toplevel for dram controller de0 nano board\n//\n//////////////////////////////////////////////////////////////////////\n//\n// This source file may be used and distributed without\n// restriction provided that this copyright statement is not\n// removed from the file and that any derivative work contains\n// the original copyright notice and the associated disclaimer.\n//\n// This source file is free software; you can redistribute it\n// and/or modify it under the terms of the GNU Lesser General\n// Public License as published by the Free Software Foundation;\n// either version 2.1 of the License, or (at your option) any\n// later version.\n//\n// This source is distributed in the hope that it will be\n// useful, but WITHOUT ANY WARRANTY; without even the implied\n// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR\n// PURPOSE. See the GNU Lesser General Public License for more\n// details.\n//\n// You should have received a copy of the GNU Lesser General\n// Public License along with this source; if not, download it\n// from http://www.opencores.org/lgpl.shtml\n//\n//////////////////////////////////////////////////////////////////////\n\nmodule toplevel (\n input sys_clk_pad_i,\n input rst_n_pad_i,\n input btn_n_pad_i,\n\n output [1:0] sdram_ba_pad_o,\n output [12:0] sdram_a_pad_o,\n output sdram_cs_n_pad_o,\n output sdram_ras_pad_o,\n output sdram_cas_pad_o,\n output sdram_we_pad_o,\n inout [15:0] sdram_dq_pad_io,\n output [1:0] sdram_dqm_pad_o,\n output sdram_cke_pad_o,\n output sdram_clk_pad_o,\n\n inout [7:0] gpio0_io, /* LEDs */\n input [3:0] gpio1_i /* DIPs */\n);\n\nwire clk100m;\nwire clk1m;\n\nassign sdram_clk_pad_o = clk100m;\n\n// PLLs\npll_100m pll_100mi (\n .inclk0 (sys_clk_pad_i),\n .c0 (clk100m)\n);\n\npll_1m pll_1mi (\n .inclk0 (sys_clk_pad_i),\n .c0 (clk1m)\n);\n\n// Cross Clock FIFOs\n/* Address 24-bit and 16-bit Data transfers from in:1m out:100m */\n\n/* 1 mhz side wires */\nwire [39:0] wr_fifo;\nwire wr_enable; /* wr_enable ] <-> [ wr : wr_enable to push fifo */\nwire wr_full; /* wr_full ] <-> [ full : signal that we are full */\n/* 100mhz side wires */\nwire [39:0] wro_fifo;\nwire ctrl_busy; /* rd ] <-> [ busy : pop fifo when ctrl not busy */\nwire ctrl_wr_enable; /* .empty_n-wr_enable : signal ctrl data is ready */\n\nfifo #(.BUS_WIDTH(40)) wr_fifoi (\n .wr_clk (clk1m),\n .rd_clk (clk100m),\n .wr_data (wr_fifo),\n .rd_data (wro_fifo),\n .rd (ctrl_busy),\n .wr (wr_enable),\n .full (wr_full),\n .empty_n (ctrl_wr_enable),\n .rst_n (rst_n_pad_i)\n);\n\n/* Address 24-bit transfers from in:1m out:100m */\n/* 1 mhz side wires */\nwire rd_enable; /* rd_enable -wr : rd_enable to push rd addr to fifo */\nwire rdaddr_full;/* rdaddr_full-full : signal we cannot read more */\n\n/* 100mhz side wires */\nwire [23:0] rdao_fifo;\nwire ctrl_rd_enable; /* empty_n - rd_enable: signal ctrl addr ready */\n\nfifo #(.BUS_WIDTH(24)) rdaddr_fifoi (\n .wr_clk (clk1m),\n .rd_clk (clk100m),\n .wr_data (wr_fifo[39:16]),\n .rd_data (rdao_fifo),\n .rd (ctrl_busy),\n .wr (rd_enable),\n .full (rdaddr_full),\n .empty_n (ctrl_rd_enable),\n .rst_n (rst_n_pad_i)\n);\n\n/* 100mhz side wires */\nwire [15:0] rddo_fifo;\nwire ctrl_rd_ready; /* wr - rd_ready - push data from dram to fifo */\n\n/* 1mhz side wires */\nwire [15:0] rddata_fifo;\nwire rd_ready; /* rd_ready-empty_n- signal interface data ready */\nwire rd_ack; /* rd_ack - rd - pop fifo after data read */\n\n/* Incoming 16-bit data transfers from in:100m out:1m */\nfifo #(.BUS_WIDTH(16)) rddata_fifoi (\n .wr_clk (clk100m),\n .rd_clk (clk1m),\n .wr_data (rddo_fifo),\n .rd_data (rddata_fifo),\n .rd (rd_ack),\n .wr (ctrl_rd_ready),\n .full (),\n .empty_n (rd_ready),\n .rst_n (rst_n_pad_i)\n);\n\n\n/* SDRAM */\n\n\nsdram_controller sdram_controlleri (\n /* HOST INTERFACE */\n .wr_addr (wro_fifo[39:16]),\n .wr_data (wro_fifo[15:0]),\n .wr_enable (ctrl_wr_enable), \n\n .rd_addr (rdao_fifo), \n .rd_data (rddo_fifo),\n .rd_ready (ctrl_rd_ready),\n .rd_enable (ctrl_rd_enable),\n \n .busy (ctrl_busy),\n .rst_n (rst_n_pad_i),\n .clk (clk100m),\n\n /* SDRAM SIDE */\n .addr (sdram_a_pad_o),\n .bank_addr (sdram_ba_pad_o),\n .data (sdram_dq_pad_io),\n .clock_enable (sdram_cke_pad_o),\n .cs_n (sdram_cs_n_pad_o),\n .ras_n (sdram_ras_pad_o),\n .cas_n (sdram_cas_pad_o),\n .we_n (sdram_we_pad_o),\n .data_mask_low (sdram_dqm_pad_o[0]),\n .data_mask_high(sdram_dqm_pad_o[1])\n);\n\nwire busy;\n\nassign busy = wr_full | rdaddr_full;\n\ndnano_interface #(.HADDR_WIDTH(24)) dnano_interfacei (\n /* Human Interface */\n .button_n (btn_n_pad_i), \n .dip (gpio1_i),\n .leds (gpio0_io),\n\n /* Controller Interface */\n .haddr (wr_fifo[39:16]),// RW-FIFO- data1\n .busy (busy), // RW-FIFO- full\n \n .wr_enable (wr_enable), // WR-FIFO- write\n .wr_data (wr_fifo[15:00]),// WR-FIFO- data2\n \n .rd_enable (rd_enable), // RO-FIFO- write\n \n .rd_data (rddata_fifo), // RI-FIFO- data\n .rd_rdy (rd_ready), // RI-FIFO-~empty\n .rd_ack (rd_ack), // RI-FIFO- read\n\n /* basics */\n .rst_n (rst_n_pad_i), \n .clk (clk1m)\n\n);\n\nendmodule // toplevel\n" } ]