Repository: suhetao/stm32f4_mpu9250 Branch: master Commit: b86160c2b781 Files: 201 Total size: 4.5 MB Directory structure: gitextract_61j4xxir/ ├── .gitignore ├── Algorithm/ │ ├── inc/ │ │ ├── CKF.h │ │ ├── Control.h │ │ ├── Double.h │ │ ├── EKF.h │ │ ├── INS_EKF.h │ │ ├── PID.h │ │ ├── Quaternion.h │ │ ├── SRCKF.h │ │ └── UKF.h │ └── src/ │ ├── CKF.C │ ├── Control.c │ ├── EKF.c │ ├── INS_EKF.c │ ├── PID.c │ ├── Quaternion.c │ ├── SRCKF.c │ └── UKF.c ├── Application/ │ ├── inc/ │ │ ├── stm32f4_common.h │ │ ├── stm32f4_crc.h │ │ ├── stm32f4_delay.h │ │ ├── stm32f4_dmp.h │ │ ├── stm32f4_exti.h │ │ ├── stm32f4_gps.h │ │ ├── stm32f4_mpu9250.h │ │ ├── stm32f4_ms5611.h │ │ ├── stm32f4_rcc.h │ │ ├── stm32f4_serial.h │ │ ├── stm32f4_string.h │ │ ├── stm32f4_ublox.h │ │ ├── stm32f4xx_conf.h │ │ └── stm32f4xx_it.h │ └── src/ │ ├── main.c │ ├── stm32f4_delay.c │ ├── stm32f4_exti.c │ ├── stm32f4_gps.c │ ├── stm32f4_mpu9250.c │ ├── stm32f4_ms5611.c │ ├── stm32f4_rcc.c │ ├── stm32f4_serial.c │ ├── stm32f4_string.c │ ├── stm32f4_ublox.c │ └── system_stm32f4xx.c ├── Common/ │ ├── inc/ │ │ └── Memory.h │ └── src/ │ └── Memory.c ├── Data/ │ ├── inc/ │ │ ├── Fifo.h │ │ └── Queue.h │ └── src/ │ ├── Fifo.c │ └── Queue.c ├── Drivers/ │ ├── inc/ │ │ ├── stm32f4_exti.h │ │ ├── stm32f4_gpio.h │ │ ├── stm32f4_spi.h │ │ └── stm32f4_usart.h │ └── src/ │ ├── stm32f4_exti.c │ ├── stm32f4_gpio.c │ ├── stm32f4_spi.c │ └── stm32f4_usart.c ├── Gps/ │ ├── inc/ │ │ ├── Map.h │ │ └── Nema.h │ └── src/ │ ├── Map.c │ └── Nema.c ├── LICENSE ├── Libraries/ │ ├── CMSIS/ │ │ ├── Device/ │ │ │ └── ST/ │ │ │ └── STM32F4xx/ │ │ │ ├── Include/ │ │ │ │ ├── stm32f4xx.h │ │ │ │ └── system_stm32f4xx.h │ │ │ ├── Release_Notes.html │ │ │ └── Source/ │ │ │ └── Templates/ │ │ │ ├── TASKING/ │ │ │ │ └── cstart_thumb2.asm │ │ │ ├── TrueSTUDIO/ │ │ │ │ ├── startup_stm32f401xx.s │ │ │ │ ├── startup_stm32f40_41xxx.s │ │ │ │ ├── startup_stm32f40xx.s │ │ │ │ ├── startup_stm32f427_437xx.s │ │ │ │ ├── startup_stm32f427xx.s │ │ │ │ └── startup_stm32f429_439xx.s │ │ │ ├── arm/ │ │ │ │ ├── startup_stm32f401xx.s │ │ │ │ ├── startup_stm32f40_41xxx.s │ │ │ │ ├── startup_stm32f40xx.s │ │ │ │ ├── startup_stm32f427_437xx.s │ │ │ │ ├── startup_stm32f427x.s │ │ │ │ └── startup_stm32f429_439xx.s │ │ │ ├── gcc_ride7/ │ │ │ │ ├── startup_stm32f401xx.s │ │ │ │ ├── startup_stm32f40_41xxx.s │ │ │ │ ├── startup_stm32f40xx.s │ │ │ │ ├── startup_stm32f427_437xx.s │ │ │ │ ├── startup_stm32f427x.s │ │ │ │ └── startup_stm32f429_439xx.s │ │ │ ├── iar/ │ │ │ │ ├── startup_stm32f401xx.s │ │ │ │ ├── startup_stm32f40_41xxx.s │ │ │ │ ├── startup_stm32f40xx.s │ │ │ │ ├── startup_stm32f427_437xx.s │ │ │ │ ├── startup_stm32f427x.s │ │ │ │ └── startup_stm32f429_439xx.s │ │ │ └── system_stm32f4xx.c │ │ ├── Include/ │ │ │ ├── arm_common_tables.h │ │ │ ├── arm_const_structs.h │ │ │ ├── arm_math.h │ │ │ ├── core_cm0.h │ │ │ ├── core_cm0plus.h │ │ │ ├── core_cm3.h │ │ │ ├── core_cm4.h │ │ │ ├── core_cm4_simd.h │ │ │ ├── core_cmFunc.h │ │ │ ├── core_cmInstr.h │ │ │ ├── core_sc000.h │ │ │ └── core_sc300.h │ │ ├── README.txt │ │ └── index.html │ ├── STM32F4xx_StdPeriph_Driver/ │ │ ├── Release_Notes.html │ │ ├── inc/ │ │ │ ├── misc.h │ │ │ ├── stm32f4xx_adc.h │ │ │ ├── stm32f4xx_can.h │ │ │ ├── stm32f4xx_crc.h │ │ │ ├── stm32f4xx_cryp.h │ │ │ ├── stm32f4xx_dac.h │ │ │ ├── stm32f4xx_dbgmcu.h │ │ │ ├── stm32f4xx_dcmi.h │ │ │ ├── stm32f4xx_dma.h │ │ │ ├── stm32f4xx_dma2d.h │ │ │ ├── stm32f4xx_exti.h │ │ │ ├── stm32f4xx_flash.h │ │ │ ├── stm32f4xx_fmc.h │ │ │ ├── stm32f4xx_fsmc.h │ │ │ ├── stm32f4xx_gpio.h │ │ │ ├── stm32f4xx_hash.h │ │ │ ├── stm32f4xx_i2c.h │ │ │ ├── stm32f4xx_iwdg.h │ │ │ ├── stm32f4xx_ltdc.h │ │ │ ├── stm32f4xx_pwr.h │ │ │ ├── stm32f4xx_rcc.h │ │ │ ├── stm32f4xx_rng.h │ │ │ ├── stm32f4xx_rtc.h │ │ │ ├── stm32f4xx_sai.h │ │ │ ├── stm32f4xx_sdio.h │ │ │ ├── stm32f4xx_spi.h │ │ │ ├── stm32f4xx_syscfg.h │ │ │ ├── stm32f4xx_tim.h │ │ │ ├── stm32f4xx_usart.h │ │ │ └── stm32f4xx_wwdg.h │ │ └── src/ │ │ ├── misc.c │ │ ├── stm32f4xx_adc.c │ │ ├── stm32f4xx_can.c │ │ ├── stm32f4xx_crc.c │ │ ├── stm32f4xx_cryp.c │ │ ├── stm32f4xx_cryp_aes.c │ │ ├── stm32f4xx_cryp_des.c │ │ ├── stm32f4xx_cryp_tdes.c │ │ ├── stm32f4xx_dac.c │ │ ├── stm32f4xx_dbgmcu.c │ │ ├── stm32f4xx_dcmi.c │ │ ├── stm32f4xx_dma.c │ │ ├── stm32f4xx_dma2d.c │ │ ├── stm32f4xx_exti.c │ │ ├── stm32f4xx_flash.c │ │ ├── stm32f4xx_fmc.c │ │ ├── stm32f4xx_fsmc.c │ │ ├── stm32f4xx_gpio.c │ │ ├── stm32f4xx_hash.c │ │ ├── stm32f4xx_hash_md5.c │ │ ├── stm32f4xx_hash_sha1.c │ │ ├── stm32f4xx_i2c.c │ │ ├── stm32f4xx_iwdg.c │ │ ├── stm32f4xx_ltdc.c │ │ ├── stm32f4xx_pwr.c │ │ ├── stm32f4xx_rcc.c │ │ ├── stm32f4xx_rng.c │ │ ├── stm32f4xx_rtc.c │ │ ├── stm32f4xx_sai.c │ │ ├── stm32f4xx_sdio.c │ │ ├── stm32f4xx_spi.c │ │ ├── stm32f4xx_syscfg.c │ │ ├── stm32f4xx_tim.c │ │ ├── stm32f4xx_usart.c │ │ └── stm32f4xx_wwdg.c │ └── eMPL/ │ ├── dmpKey.h │ ├── dmpmap.h │ ├── inv_mpu.c │ ├── inv_mpu.h │ ├── inv_mpu_dmp_motion_driver.c │ └── inv_mpu_dmp_motion_driver.h ├── Math/ │ ├── inc/ │ │ └── FastMath.h │ └── src/ │ └── FastMath.c ├── Matrix/ │ ├── inc/ │ │ ├── DoubleMatrix.h │ │ └── Matrix.h │ └── src/ │ ├── DoubleMatrix.c │ └── Matrix.c ├── Project/ │ ├── JLinkLog.txt │ ├── JLinkSettings.ini │ ├── stm32f4_dmp.uvopt │ └── stm32f4_dmp.uvproj ├── README.md ├── miniAHRS/ │ ├── miniAHRS.c │ └── miniAHRS.h └── miniIMU/ ├── FP/ │ ├── FP_Math.c │ ├── FP_Math.h │ ├── FP_Matrix.c │ ├── FP_Matrix.h │ ├── FP_miniIMU.c │ └── FP_miniIMU.h ├── Usage.txt ├── miniIMU.c ├── miniIMU.h ├── miniMatrix.c └── miniMatrix.h ================================================ FILE CONTENTS ================================================ ================================================ FILE: .gitignore ================================================ # Object files *.o *.ko *.obj *.elf # Precompiled Headers *.gch *.pch # Libraries *.lib *.a *.la *.lo # Shared objects (inc. Windows DLLs) *.dll *.so *.so.* *.dylib # Executables *.exe *.out *.app *.i*86 *.x86_64 *.hex ================================================ FILE: Algorithm/inc/CKF.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _CKF_H #define _CKF_H #include "Matrix.h" //7-state q0 q1 q2 q3 wx wy wz #define CKF_STATE_DIM 7 //13-measurement q0 q1 q2 q3 ax ay az wx wy wz mx my mz #define CKF_MEASUREMENT_DIM 13 #define CKF_CP_POINTS 14//(2 * CKF_STATE_DIM) #define CKF_HALFPI 1.5707963267948966192313216916398f #define CKF_PI 3.1415926535897932384626433832795f #define CKF_TWOPI 6.283185307179586476925286766559f #define CKF_TODEG(x) ((x) * 57.2957796f) typedef struct CKF_FILTER_T{ //weights float32_t W; //Kesi float32_t Kesi_f32[CKF_STATE_DIM * CKF_CP_POINTS]; float32_t iKesi_f32[CKF_STATE_DIM]; //state covariance float32_t P_f32[CKF_STATE_DIM * CKF_STATE_DIM]; float32_t PX_f32[CKF_STATE_DIM * CKF_STATE_DIM]; float32_t PY_f32[CKF_MEASUREMENT_DIM * CKF_MEASUREMENT_DIM]; float32_t tmpPY_f32[CKF_MEASUREMENT_DIM * CKF_MEASUREMENT_DIM]; float32_t PXY_f32[CKF_STATE_DIM * CKF_MEASUREMENT_DIM]; float32_t tmpPXY_f32[CKF_STATE_DIM * CKF_MEASUREMENT_DIM]; float32_t Q_f32[CKF_STATE_DIM * CKF_STATE_DIM]; float32_t R_f32[CKF_MEASUREMENT_DIM * CKF_MEASUREMENT_DIM]; //cubature points float32_t XCP_f32[CKF_STATE_DIM * CKF_CP_POINTS]; float32_t XminusCP_f32[CKF_STATE_DIM * CKF_CP_POINTS]; float32_t YSP_f32[CKF_MEASUREMENT_DIM * CKF_CP_POINTS]; //Kalman gain float32_t K_f32[CKF_STATE_DIM * CKF_MEASUREMENT_DIM]; float32_t KT_f32[CKF_MEASUREMENT_DIM * CKF_STATE_DIM]; //state vector float32_t X_f32[CKF_STATE_DIM]; float32_t XT_f32[CKF_STATE_DIM]; float32_t Xminus_f32[CKF_STATE_DIM]; float32_t XminusT_f32[CKF_STATE_DIM]; float32_t tmpX_f32[CKF_STATE_DIM]; float32_t tmpS_f32[CKF_STATE_DIM]; //measurement vector float32_t Y_f32[CKF_MEASUREMENT_DIM]; float32_t YT_f32[CKF_MEASUREMENT_DIM]; float32_t Yminus_f32[CKF_MEASUREMENT_DIM]; float32_t YminusT_f32[CKF_MEASUREMENT_DIM]; float32_t tmpY_f32[CKF_MEASUREMENT_DIM]; // arm_matrix_instance_f32 Kesi; arm_matrix_instance_f32 iKesi; arm_matrix_instance_f32 P; arm_matrix_instance_f32 PX; arm_matrix_instance_f32 PY; arm_matrix_instance_f32 tmpPY; arm_matrix_instance_f32 PXY; arm_matrix_instance_f32 tmpPXY; arm_matrix_instance_f32 Q; arm_matrix_instance_f32 R; // arm_matrix_instance_f32 XCP; arm_matrix_instance_f32 XminusCP; arm_matrix_instance_f32 YCP; // arm_matrix_instance_f32 K; arm_matrix_instance_f32 KT; // arm_matrix_instance_f32 X; arm_matrix_instance_f32 XT; arm_matrix_instance_f32 Xminus; arm_matrix_instance_f32 XminusT; arm_matrix_instance_f32 tmpX; arm_matrix_instance_f32 tmpS; arm_matrix_instance_f32 Y; arm_matrix_instance_f32 YT; arm_matrix_instance_f32 Yminus; arm_matrix_instance_f32 YminusT; arm_matrix_instance_f32 tmpY; }CKF_Filter; void CKF_New(CKF_Filter* ckf); void CKF_Init(CKF_Filter* ckf, float32_t *q, float32_t *gyro); void CKF_Update(CKF_Filter* ckf, float32_t *q, float32_t *gyro, float32_t *accel, float32_t *mag, float32_t dt); void CKF_GetAngle(CKF_Filter* ckf, float32_t* rpy); __inline void CKF_GetQ(CKF_Filter* ckf, float32_t* Q) { Q[0] = ckf->X_f32[0]; Q[1] = ckf->X_f32[1]; Q[2] = ckf->X_f32[2]; Q[3] = ckf->X_f32[3]; } #endif ================================================ FILE: Algorithm/inc/Control.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _CONTROL_H_ #define _CONTROL_H_ #include "PID.h" //Modelling, Identification and Control of a Quadrotor Helicopter #define PI (3.1415926535897932384626433832795f) #define PI_6 (0.52359877559829887307710723054658f) #define MIN_ANG (-PI_6) #define MAX_ANG PI_6 typedef struct CONTROLLERPARAMETER_T { float m; //mass of the quadrotor float Ixx; //body moment of inertia around the x-axis float Iyy; //body moment of inertia around the y-axis float Izz; //body moment of inertia around the z-axis float I[9]; //body inertia matrix float d; //drag factor float b; //thrust factor float l; //center of quadrotor to center of propeller distance float X; float Y; float Z; PIDController PostionX; PIDController PostionY; PIDController PostionZ; // not use yet float g; //acceleration due to gravity float n; //number of data acquired float N; //gear box reduction ratio float h; //PWM code vector float R; //motor resistance float Jtp; //total rotational moment of inertia around the propeller axis float Ke; //electric motor constant float Km; //mechanic motor constant float L; //motor inductance }QuadrotorParameter; typedef enum TRAJECTORY_T{ X = 0, Y = 1, Z = 2, PSI = 3 }Trajectory; typedef enum EULER_T{ ROLL = 0, PITCH = 1, YAW = 2 }Euler; void EulerConv(float* dt, float *deta); void TorqueConv(float *eta, float *deta, float *dt); void ForceConv(float *eta, float dz, float *df); void TorqueInv(float *dt, float df, float *domega); #endif ================================================ FILE: Algorithm/inc/Double.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _DOUBLE_H #define _DOUBLE_H ////////////////////////////////////////////////////////////////////////// //algorithm from the book //<> //References: //Emulated double precision Double single routine from nvidia developer zone ////////////////////////////////////////////////////////////////////////// //define my own double struct typedef struct { float hi; float lo; } Double; ////////////////////////////////////////////////////////////////////////// //transmit double precision float to my own Double __inline Double intToDouble(int A) { Double B; B.hi = (float)A; B.lo = 0.0f; return B; } // __inline Double floatToDouble(float A) { Double B; B.hi = A; B.lo = 0.0f; return B; } // __inline Double doubleToDouble(double A) { Double B; B.hi = (float)A; B.lo = (float)(A - (double)B.hi); return B; } //transmit my own Double to double precision float __inline double DoubleTodouble(Double B) { double A; A = B.hi; A += B.lo; return A; } //addition: Double + Double __inline Double DoubleAdd(Double A, Double B) { Double C; float t1, t2, e; //Compute high order sum and error t1 = A.hi + B.hi; e = t1 - A.hi; //Compute low order term, including error and overflows t2 = ((B.hi - e) + ( A.hi - (t1 - e))) + A.lo + B.lo; //Normalise to get final result C.hi = t1 + t2; C.lo = t2 -(C.hi - t1); return C; } //Subtraction: Double - Double __inline Double DoubleSub(Double A, Double B) { Double C; float t1, t2, e; //Compute high order sub and error t1 = A.hi - B.hi; e = t1 - A.hi; //Compute low order term, including error and overflows t2 = ((-B.hi - e) + ( A.hi - (t1 - e))) + A.lo - B.lo; //Normalise to get final result C.hi = t1 + t2; C.lo = t2 -(C.hi - t1); return C; } //multiplication: Double * Double __inline Double DoubleMul(Double A, Double B) { Double C; float cona, conb, a1, a2, b1, b2; float c11, c21, c2, e, t1, t2; //Compute initial high order approximation and error //If a fused multiply-add is available //c11 = A.hi * B.hi; //c21 = A.hi * B.hi - c11; //If no fused multiply-add is available cona = A.hi * 8193.0f; conb = B.hi * 8193.0f; a1 = cona - (cona - A.hi); b1 = conb - (conb - B.hi); a2 = A.hi - a1; b2 = B.hi - b1; c11 = A.hi * B.hi; c21 = (((a1 * b1 - c11) + a1 * b2) + a2 * b1) + a2 * b2; //Compute high order word of mixed term: c2 = A.hi * B.lo + A.lo * B.hi; //Compute (c11, c21) + c2 using Knuth's trick, including low order product t1 = c11 + c2; e = t1 - c11; t2 = ((c2-e) + (c11 - (t1 -e))) + c21 + A.lo * B.lo; //Normalise to get final result C.hi = t1 + t2; C.lo = t2 - ( C.hi - t1); return C; } //divides: Double / Double __inline Double DoubleDiv(Double A, Double B) { Double C; float a1, a2, b1, b2, cona, conb, c11, c2, c21, e, s1, s2; float t1, t2, t11, t12, t21, t22; // Compute a DP approximation to the quotient. s2 = 1.0f / B.hi; s1 = A.hi * s2; //This splits s1 and b.x into high-order and low-order words. cona = s1 * 8193.0f; conb = B.hi * 8193.0f; a1 = cona - (cona - s1); b1 = conb - (conb - B.hi); a2 = s1 -a1; b2 = B.hi - b1; //Multiply s1 * dsb(1) using Dekker's method. c11 = s1 * B.hi; c21 = (((a1 * b1 - c11) + a1 * b2) + a2 * b1) + a2 * b2; //Compute s1 * b.lo (only high-order word is needed). c2 = s1 * B.lo; //Compute (c11, c21) + c2 using Knuth's trick. t1 = c11 + c2; e = t1 - c11; t2 = ((c2 - e) + (c11 - (t1 - e))) + c21; //The result is t1 + t2, after normalization. t12 = t1 + t2; t22 = t2 - (t12 - t1); //Compute dsa - (t12, t22) using Knuth's trick. t11 = A.hi - t12; e = t11 - A.hi; t21 = ((-t12 - e) + (A.hi - (t11 - e))) + A.lo - t22; //Compute high-order word of (t11, t21) and divide by b.hi. s2 *= (t11 + t21); //The result is s1 + s2, after normalization. C.hi = s1 + s2; C.lo = s2 - (C.hi - s1); return C; } #endif ================================================ FILE: Algorithm/inc/EKF.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _EKF_H #define _EKF_H #include "Matrix.h" //7-state q0 q1 q2 q3 wx wy wz #define EKF_STATE_DIM 7 //13-measurement q0 q1 q2 q3 ax ay az wx wy wz mx my mz #define EKF_MEASUREMENT_DIM 13 #define EKF_HALFPI 1.5707963267948966192313216916398f #define EKF_PI 3.1415926535897932384626433832795f #define EKF_TWOPI 6.283185307179586476925286766559f #define EKF_TODEG(x) ((x) * 57.2957796f) typedef struct EKF_FILTER_T{ //state covariance float32_t P_f32[EKF_STATE_DIM * EKF_STATE_DIM]; float32_t Q_f32[EKF_STATE_DIM * EKF_STATE_DIM]; float32_t R_f32[EKF_MEASUREMENT_DIM * EKF_MEASUREMENT_DIM]; //Kalman gain float32_t K_f32[EKF_STATE_DIM * EKF_MEASUREMENT_DIM]; float32_t KT_f32[EKF_MEASUREMENT_DIM * EKF_STATE_DIM]; //Measurement covariance float32_t S_f32[EKF_MEASUREMENT_DIM * EKF_MEASUREMENT_DIM]; //The H matrix maps the measurement to the states float32_t F_f32[EKF_STATE_DIM * EKF_STATE_DIM]; float32_t FT_f32[EKF_STATE_DIM * EKF_STATE_DIM]; float32_t H_f32[EKF_MEASUREMENT_DIM * EKF_STATE_DIM]; float32_t HT_f32[EKF_STATE_DIM * EKF_MEASUREMENT_DIM]; float32_t I_f32[EKF_STATE_DIM * EKF_STATE_DIM]; //state vector float32_t X_f32[EKF_STATE_DIM]; //measurement vector float32_t Y_f32[EKF_MEASUREMENT_DIM]; // float32_t tmpP_f32[EKF_STATE_DIM * EKF_STATE_DIM]; float32_t tmpS_f32[EKF_MEASUREMENT_DIM * EKF_MEASUREMENT_DIM]; float32_t tmpX_f32[EKF_STATE_DIM]; float32_t tmpXX_f32[EKF_STATE_DIM * EKF_STATE_DIM]; float32_t tmpXXT_f32[EKF_STATE_DIM * EKF_STATE_DIM]; float32_t tmpXY_f32[EKF_STATE_DIM * EKF_MEASUREMENT_DIM]; float32_t tmpYX_f32[EKF_MEASUREMENT_DIM * EKF_STATE_DIM]; arm_matrix_instance_f32 P; arm_matrix_instance_f32 Q; arm_matrix_instance_f32 R; arm_matrix_instance_f32 K; arm_matrix_instance_f32 KT; arm_matrix_instance_f32 S; arm_matrix_instance_f32 F; arm_matrix_instance_f32 FT; arm_matrix_instance_f32 H; arm_matrix_instance_f32 HT; arm_matrix_instance_f32 I; // arm_matrix_instance_f32 X; arm_matrix_instance_f32 Y; // arm_matrix_instance_f32 tmpP; arm_matrix_instance_f32 tmpX; arm_matrix_instance_f32 tmpYX; arm_matrix_instance_f32 tmpXY; arm_matrix_instance_f32 tmpXX; arm_matrix_instance_f32 tmpXXT; arm_matrix_instance_f32 tmpS; }EKF_Filter; void EKF_New(EKF_Filter* ekf); void EKF_Init(EKF_Filter* ekf, float32_t *q, float32_t *gyro); void EFK_Update(EKF_Filter* ekf, float32_t *q, float32_t *gyro, float32_t *accel, float32_t *mag, float32_t dt); void EKF_GetAngle(EKF_Filter* ekf, float32_t* rpy); __inline void EKF_GetQ(EKF_Filter* efk, float32_t* Q) { Q[0] = efk->X_f32[0]; Q[1] = efk->X_f32[1]; Q[2] = efk->X_f32[2]; Q[3] = efk->X_f32[3]; } #endif ================================================ FILE: Algorithm/inc/INS_EKF.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _INS_EKF_H_ #define _INS_EKF_H_ #include "Matrix.h" //16-state q0 q1 q2 q3 Pn Pe Alt Vn Ve Vd bwx bwy bwz bax bay baz #define INS_EKF_STATE_DIM 16 //9-measurement mx my mz (3D magnetometer) Pn Pe Alt Vn Ve Vd //unit vector pointing to MagNorth in body coords //north pos, east pos, altitude //north vel, east vel, down velocity #define INS_EKF_MEASUREMENT_DIM 9 #define INS_EKF_HALFPI 1.5707963267948966192313216916398f #define INS_EKF_PI 3.1415926535897932384626433832795f #define INS_EKF_TWOPI 6.283185307179586476925286766559f #define INS_EKF_TODEG(x) ((x) * 57.2957796f) typedef struct INS_EKF_FILTER_T{ //state covariance float32_t P_f32[INS_EKF_STATE_DIM * INS_EKF_STATE_DIM]; float32_t PX_f32[INS_EKF_STATE_DIM * INS_EKF_STATE_DIM]; float32_t PHT_f32[INS_EKF_STATE_DIM * INS_EKF_MEASUREMENT_DIM]; float32_t Q_f32[INS_EKF_STATE_DIM * INS_EKF_STATE_DIM]; float32_t R_f32[INS_EKF_MEASUREMENT_DIM * INS_EKF_MEASUREMENT_DIM]; float32_t K_f32[INS_EKF_STATE_DIM * INS_EKF_MEASUREMENT_DIM]; float32_t KH_f32[INS_EKF_STATE_DIM * INS_EKF_STATE_DIM]; float32_t KHP_f32[INS_EKF_STATE_DIM * INS_EKF_STATE_DIM]; float32_t KY_f32[INS_EKF_STATE_DIM]; float32_t F_f32[INS_EKF_STATE_DIM * INS_EKF_STATE_DIM]; float32_t FT_f32[INS_EKF_STATE_DIM * INS_EKF_STATE_DIM]; //The H matrix maps the measurement to the states float32_t H_f32[INS_EKF_MEASUREMENT_DIM * INS_EKF_STATE_DIM]; float32_t HT_f32[INS_EKF_STATE_DIM * INS_EKF_MEASUREMENT_DIM]; float32_t HP_f32[INS_EKF_MEASUREMENT_DIM * INS_EKF_STATE_DIM]; float32_t S_f32[INS_EKF_MEASUREMENT_DIM * INS_EKF_MEASUREMENT_DIM]; float32_t SI_f32[INS_EKF_MEASUREMENT_DIM * INS_EKF_MEASUREMENT_DIM]; //state vector float32_t X_f32[INS_EKF_STATE_DIM]; //measurement vector float32_t Y_f32[INS_EKF_MEASUREMENT_DIM]; arm_matrix_instance_f32 P; arm_matrix_instance_f32 PX; arm_matrix_instance_f32 PHT; arm_matrix_instance_f32 Q; arm_matrix_instance_f32 R; arm_matrix_instance_f32 K; arm_matrix_instance_f32 KH; arm_matrix_instance_f32 KHP; arm_matrix_instance_f32 KY; arm_matrix_instance_f32 F; arm_matrix_instance_f32 FT; arm_matrix_instance_f32 H; arm_matrix_instance_f32 HT; arm_matrix_instance_f32 HP; arm_matrix_instance_f32 S; arm_matrix_instance_f32 SI; arm_matrix_instance_f32 X; arm_matrix_instance_f32 Y; float32_t declination; float32_t gravity; //m/s^2 }INS_EKF_Filter; void INS_EKF_New(INS_EKF_Filter* ins); void INS_EKF_Init(INS_EKF_Filter* ins, float32_t *p, float32_t *v, float32_t *accel, float32_t *mag); void INS_EFK_Update(INS_EKF_Filter* ins, float32_t *mag, float32_t *p, float32_t *v, float32_t *gyro, float32_t *accel, float32_t dt); void INS_EKF_GetAngle(INS_EKF_Filter* ins, float32_t* rpy); #endif ================================================ FILE: Algorithm/inc/PID.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _PID_H_ #define _PID_H_ typedef struct PIDCONTROLLER_T { float A0; // < The derived gain, A0 = Kp + Ki + Kd . float A1; // < The derived gain, A1 = -Kp - 2Kd. float A2; // < The derived gain, A2 = Kd . float state[3]; // < The state array of length 3. float Kp; // < The proportional gain. float Ki; // < The integral gain. float Kd; // < The derivative gain. } PIDController; __inline float PID_Calculate(PIDController *S, float in) { float out; // y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] out = (S->A0 * in) + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); // Update state S->state[1] = S->state[0]; S->state[0] = in; S->state[2] = out; // return to application return (out); } __inline void PID_Init(PIDController *S) { //Derived coefficient A0 S->A0 = S->Kp + S->Ki + S->Kd; //Derived coefficient A1 S->A1 = (-S->Kp) - ((float) 2.0 * S->Kd); //Derived coefficient A2 S->A2 = S->Kd; S->state[0] = 0.0f; S->state[1] = 0.0f; S->state[2] = 0.0f; } __inline void PID_Reset(PIDController *S) { S->state[0] = 0.0f; S->state[1] = 0.0f; S->state[2] = 0.0f; } #endif ================================================ FILE: Algorithm/inc/Quaternion.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _QUATERNION_H_ #define _QUATERNION_H_ #include "FastMath.h" __inline void Quaternion_Add(float *r, float *a, float *b) { r[0] = a[0] + b[0]; r[1] = a[1] + b[1]; r[2] = a[2] + b[2]; r[3] = a[3] + b[3]; } __inline void Quaternion_Sub(float *r, float *a, float *b) { r[0] = a[0] - b[0]; r[1] = a[1] - b[1]; r[2] = a[2] - b[2]; r[3] = a[3] - b[3]; } __inline void Quaternion_Multiply(float *r, float *a, float *b) { r[0] = a[0] * b[0] - a[1] * b[1] - a[2] * b[2] - a[3] * b[3]; r[1] = a[0] * b[1] + a[1] * b[0] + a[2] * b[3] - a[3] * b[2]; r[2] = a[0] * b[2] - a[1] * b[3] + a[2] * b[0] + a[3] * b[1]; r[3] = a[0] * b[3] + a[1] * b[2] - a[2] * b[1] + a[3] * b[0]; } __inline void Quaternion_Conjugate(float *r, float *a) { r[0] = a[0]; r[1] = -a[1]; r[2] = -a[2]; r[3] = -a[3]; } __inline void Quaternion_Scalar(float *r, float *q, float scalar) { r[0] = q[0] * scalar; r[1] = q[1] * scalar; r[2] = q[2] * scalar; r[3] = q[3] * scalar; } void Quaternion_Normalize(float *q); void Quaternion_FromEuler(float *q, float *rpy); void Quaternion_ToEuler(float *q, float* rpy); void Quaternion_FromRotationMatrix(float *R, float *Q); void Quaternion_RungeKutta4(float *q, float *w, float dt, int normalize); void Quaternion_From6AxisData(float* q, float *accel, float *mag); #endif ================================================ FILE: Algorithm/inc/SRCKF.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _SRCKF_H #define _SRCKF_H #include "Matrix.h" //7-state q0 q1 q2 q3 wbx wby wbz #define SRCKF_STATE_DIM 7 //6-measurement ax ay az mx my mz #define SRCKF_MEASUREMENT_DIM 6 #define SRCKF_CP_POINTS 14//(2 * SRCKF_STATE_DIM) #define SRCKF_HALFPI 1.5707963267948966192313216916398f #define SRCKF_PI 3.1415926535897932384626433832795f #define SRCKF_TWOPI 6.283185307179586476925286766559f #define SRCKF_TODEG(x) ((x) * 57.2957796f) typedef struct SRCKF_FILTER_T{ //weights float32_t W; float32_t SW; //Kesi float32_t Kesi_f32[SRCKF_STATE_DIM * SRCKF_CP_POINTS]; float32_t iKesi_f32[SRCKF_STATE_DIM]; //state covariance float32_t S_f32[SRCKF_STATE_DIM * SRCKF_STATE_DIM]; float32_t ST_f32[SRCKF_STATE_DIM * SRCKF_STATE_DIM]; //measurement covariance float32_t SY_f32[SRCKF_MEASUREMENT_DIM * SRCKF_MEASUREMENT_DIM]; float32_t SYI_f32[SRCKF_MEASUREMENT_DIM * SRCKF_MEASUREMENT_DIM]; float32_t SYT_f32[SRCKF_MEASUREMENT_DIM * SRCKF_MEASUREMENT_DIM]; float32_t SYTI_f32[SRCKF_MEASUREMENT_DIM * SRCKF_MEASUREMENT_DIM]; //cross covariance float32_t PXY_f32[SRCKF_STATE_DIM * SRCKF_MEASUREMENT_DIM]; float32_t tmpPXY_f32[SRCKF_STATE_DIM * SRCKF_MEASUREMENT_DIM]; // float32_t SQ_f32[SRCKF_STATE_DIM * SRCKF_STATE_DIM]; float32_t SR_f32[SRCKF_MEASUREMENT_DIM * SRCKF_MEASUREMENT_DIM]; //cubature points float32_t XCP_f32[SRCKF_STATE_DIM * SRCKF_CP_POINTS]; //propagated cubature points float32_t XPCP_f32[SRCKF_STATE_DIM * SRCKF_CP_POINTS]; float32_t YPCP_f32[SRCKF_MEASUREMENT_DIM * SRCKF_CP_POINTS]; //centered matrix float32_t XCPCM_f32[SRCKF_STATE_DIM * SRCKF_CP_POINTS]; float32_t tmpXCPCM_f32[SRCKF_STATE_DIM * SRCKF_CP_POINTS]; float32_t YCPCM_f32[SRCKF_MEASUREMENT_DIM * SRCKF_CP_POINTS]; float32_t YCPCMT_f32[SRCKF_CP_POINTS * SRCKF_MEASUREMENT_DIM]; float32_t XCM_f32[SRCKF_STATE_DIM * (SRCKF_CP_POINTS + SRCKF_STATE_DIM)]; float32_t YCM_f32[SRCKF_MEASUREMENT_DIM * (SRCKF_CP_POINTS + SRCKF_MEASUREMENT_DIM)]; float32_t XYCM_f32[SRCKF_STATE_DIM * (SRCKF_CP_POINTS + SRCKF_MEASUREMENT_DIM)]; //Kalman gain float32_t K_f32[SRCKF_STATE_DIM * SRCKF_MEASUREMENT_DIM]; //state vector float32_t X_f32[SRCKF_STATE_DIM]; float32_t tmpX_f32[SRCKF_STATE_DIM]; //measurement vector float32_t Y_f32[SRCKF_MEASUREMENT_DIM]; float32_t tmpY_f32[SRCKF_MEASUREMENT_DIM]; // //stuff //Kesi arm_matrix_instance_f32 Kesi; arm_matrix_instance_f32 iKesi; //state covariance arm_matrix_instance_f32 S; arm_matrix_instance_f32 ST; //measurement covariance arm_matrix_instance_f32 SY; arm_matrix_instance_f32 SYI; arm_matrix_instance_f32 SYT; arm_matrix_instance_f32 SYTI; //cross covariance arm_matrix_instance_f32 PXY; arm_matrix_instance_f32 tmpPXY; // arm_matrix_instance_f32 SQ; arm_matrix_instance_f32 SR; //cubature points arm_matrix_instance_f32 XCP; //propagated cubature points arm_matrix_instance_f32 XPCP; arm_matrix_instance_f32 YPCP; //centered matrix arm_matrix_instance_f32 XCPCM; arm_matrix_instance_f32 tmpXCPCM; arm_matrix_instance_f32 YCPCM; arm_matrix_instance_f32 YCPCMT; arm_matrix_instance_f32 XCM; arm_matrix_instance_f32 YCM; arm_matrix_instance_f32 XYCM; //Kalman gain arm_matrix_instance_f32 K; //state vector arm_matrix_instance_f32 X; arm_matrix_instance_f32 tmpX; //measurement vector arm_matrix_instance_f32 Y; arm_matrix_instance_f32 tmpY; float32_t declination; }SRCKF_Filter; void SRCKF_New(SRCKF_Filter* srckf); void SRCKF_Init(SRCKF_Filter* srckf, float32_t *accel, float32_t *mag); void SRCKF_Update(SRCKF_Filter* srckf, float32_t *gyro, float32_t *accel, float32_t *mag, float32_t dt); void SRCKF_GetAngle(SRCKF_Filter* srckf, float32_t* rpy); __inline void SRCKF_GetQ(SRCKF_Filter* srckf, float32_t* Q) { Q[0] = srckf->X_f32[0]; Q[1] = srckf->X_f32[1]; Q[2] = srckf->X_f32[2]; Q[3] = srckf->X_f32[3]; } #endif ================================================ FILE: Algorithm/inc/UKF.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _UKF_H #define _UKF_H #include "Matrix.h" //7-state q0 q1 q2 q3 wx wy wz #define UKF_STATE_DIM 7 //13-measurement q0 q1 q2 q3 ax ay az wx wy wz mx my mz #define UKF_MEASUREMENT_DIM 13 #define UKF_SP_POINTS 15//(2 * UKF_STATE_DIM + 1) #define UKF_HALFPI 1.5707963267948966192313216916398f #define UKF_PI 3.1415926535897932384626433832795f #define UKF_TWOPI 6.283185307179586476925286766559f #define UKF_TODEG(x) ((x) * 57.2957796f) typedef struct UKF_FILTER_T{ //scaling factor float32_t gamma; //weights for means float32_t Wm0, Wmi; //weights for covariance float32_t Wc_f32[UKF_SP_POINTS * UKF_SP_POINTS]; //state covariance float32_t P_f32[UKF_STATE_DIM * UKF_STATE_DIM]; float32_t PX_f32[UKF_STATE_DIM * UKF_STATE_DIM]; float32_t PY_f32[UKF_MEASUREMENT_DIM * UKF_MEASUREMENT_DIM]; float32_t tmpPY_f32[UKF_MEASUREMENT_DIM * UKF_MEASUREMENT_DIM]; float32_t PXY_f32[UKF_STATE_DIM * UKF_MEASUREMENT_DIM]; float32_t PXYT_f32[UKF_MEASUREMENT_DIM * UKF_STATE_DIM]; float32_t Q_f32[UKF_STATE_DIM * UKF_STATE_DIM]; float32_t R_f32[UKF_MEASUREMENT_DIM * UKF_MEASUREMENT_DIM]; //Sigma points float32_t XSP_f32[UKF_STATE_DIM * UKF_SP_POINTS]; float32_t tmpXSP_f32[UKF_STATE_DIM * UKF_SP_POINTS]; float32_t tmpXSPT_f32[UKF_SP_POINTS * UKF_STATE_DIM]; float32_t tmpWcXSP_f32[UKF_STATE_DIM * UKF_SP_POINTS]; float32_t tmpWcYSP_f32[UKF_MEASUREMENT_DIM * UKF_SP_POINTS]; float32_t YSP_f32[UKF_MEASUREMENT_DIM * UKF_SP_POINTS]; float32_t tmpYSP_f32[UKF_MEASUREMENT_DIM * UKF_SP_POINTS]; float32_t tmpYSPT_f32[UKF_SP_POINTS * UKF_MEASUREMENT_DIM]; //Kalman gain float32_t K_f32[UKF_STATE_DIM * UKF_MEASUREMENT_DIM]; float32_t KT_f32[UKF_MEASUREMENT_DIM * UKF_STATE_DIM]; //state vector float32_t X_f32[UKF_STATE_DIM]; float32_t tmpX_f32[UKF_STATE_DIM]; //measurement vector float32_t Y_f32[UKF_MEASUREMENT_DIM]; float32_t tmpY_f32[UKF_MEASUREMENT_DIM]; // arm_matrix_instance_f32 Wc; arm_matrix_instance_f32 P; arm_matrix_instance_f32 PX; arm_matrix_instance_f32 PY; arm_matrix_instance_f32 tmpPY; arm_matrix_instance_f32 PXY; arm_matrix_instance_f32 PXYT; arm_matrix_instance_f32 Q; arm_matrix_instance_f32 R; // arm_matrix_instance_f32 XSP; arm_matrix_instance_f32 tmpXSP; arm_matrix_instance_f32 tmpXSPT; arm_matrix_instance_f32 tmpWcXSP; arm_matrix_instance_f32 tmpWcYSP; arm_matrix_instance_f32 YSP; arm_matrix_instance_f32 tmpYSP; arm_matrix_instance_f32 tmpYSPT; // arm_matrix_instance_f32 K; arm_matrix_instance_f32 KT; // arm_matrix_instance_f32 X; arm_matrix_instance_f32 tmpX; arm_matrix_instance_f32 Y; arm_matrix_instance_f32 tmpY; }UKF_Filter; void UKF_New(UKF_Filter* UKF); void UKF_Init(UKF_Filter* UKF, float32_t *q, float32_t *gyro); void UKF_Update(UKF_Filter* UKF, float32_t *q, float32_t *gyro, float32_t *accel, float32_t *mag, float32_t dt); void UKF_GetAngle(UKF_Filter* UKF, float32_t* rpy); __inline void UKF_GetQ(UKF_Filter* ukf, float32_t* Q) { Q[0] = ukf->X_f32[0]; Q[1] = ukf->X_f32[1]; Q[2] = ukf->X_f32[2]; Q[3] = ukf->X_f32[3]; } #endif ================================================ FILE: Algorithm/src/CKF.C ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "CKF.h" #include "FastMath.h" #include "Quaternion.h" #define USE_4TH_RUNGE_KUTTA ////////////////////////////////////////////////////////////////////////// //all parameters below need to be tune including the weight #define CKF_PQ_INITIAL 0.000001f #define CKF_PW_INITIAL 0.000001f #define CKF_QQ_INITIAL 0.0000045f #define CKF_QW_INITIAL 0.0000025f #define CKF_RQ_INITIAL 0.000001f #define CKF_RA_INITIAL 0.07f #define CKF_RW_INITIAL 0.0525f #define CKF_RM_INITIAL 0.105f ////////////////////////////////////////////////////////////////////////// // void CKF_New(CKF_Filter* ckf) { float32_t *P = ckf->P_f32; float32_t *Q = ckf->Q_f32; float32_t *R = ckf->R_f32; ////////////////////////////////////////////////////////////////////////// //initialise kesi //generate the cubature point float32_t kesi = (float32_t)CKF_STATE_DIM; arm_matrix_instance_f32 KesiPuls, KesiMinu; float32_t KesiPuls_f32[CKF_STATE_DIM * CKF_STATE_DIM], KesiMinus_f32[CKF_STATE_DIM * CKF_STATE_DIM]; arm_sqrt_f32(kesi, &kesi); arm_mat_init_f32(&KesiPuls, CKF_STATE_DIM, CKF_STATE_DIM, KesiPuls_f32); arm_mat_zero_f32(&KesiPuls); arm_mat_init_f32(&KesiMinu, CKF_STATE_DIM, CKF_STATE_DIM, KesiMinus_f32); arm_mat_zero_f32(&KesiMinu); arm_mat_identity_f32(&KesiPuls, kesi); arm_mat_identity_f32(&KesiMinu, -kesi); arm_mat_init_f32(&ckf->Kesi, CKF_STATE_DIM, CKF_CP_POINTS, ckf->Kesi_f32); arm_mat_setsubmatrix_f32(&ckf->Kesi, &KesiPuls, 0, 0); arm_mat_setsubmatrix_f32(&ckf->Kesi, &KesiMinu, 0, CKF_STATE_DIM); arm_mat_init_f32(&ckf->iKesi, CKF_STATE_DIM, 1, ckf->iKesi_f32); arm_mat_zero_f32(&ckf->iKesi); //initialise weight ckf->W = 1.0f / (float32_t)CKF_CP_POINTS; //initialise P arm_mat_init_f32(&ckf->P, CKF_STATE_DIM, CKF_STATE_DIM, ckf->P_f32); arm_mat_zero_f32(&ckf->P); P[0] = P[8] = P[16] = P[24] = CKF_PQ_INITIAL; P[32] = P[40] = P[48] = CKF_PW_INITIAL; arm_mat_init_f32(&ckf->PX, CKF_STATE_DIM, CKF_STATE_DIM, ckf->PX_f32); arm_mat_init_f32(&ckf->PY, CKF_MEASUREMENT_DIM, CKF_MEASUREMENT_DIM, ckf->PY_f32); arm_mat_init_f32(&ckf->tmpPY, CKF_MEASUREMENT_DIM, CKF_MEASUREMENT_DIM, ckf->tmpPY_f32); arm_mat_init_f32(&ckf->PXY, CKF_STATE_DIM, CKF_MEASUREMENT_DIM, ckf->PXY_f32); arm_mat_init_f32(&ckf->tmpPXY, CKF_STATE_DIM, CKF_MEASUREMENT_DIM, ckf->tmpPXY_f32); //initialise Q arm_mat_init_f32(&ckf->Q, CKF_STATE_DIM, CKF_STATE_DIM, ckf->Q_f32); arm_mat_zero_f32(&ckf->Q); Q[0] = Q[8] = Q[16] = Q[24] = CKF_QQ_INITIAL; Q[32] = Q[40] = Q[48] = CKF_QW_INITIAL; //initialise R arm_mat_init_f32(&ckf->R, CKF_MEASUREMENT_DIM, CKF_MEASUREMENT_DIM, ckf->R_f32); arm_mat_zero_f32(&ckf->R); R[0] = R[14] = R[28] = R[42] = CKF_RQ_INITIAL; R[56] = R[70] = R[84] = CKF_RA_INITIAL; R[98] = R[112] = R[126] = CKF_RW_INITIAL; R[140] = R[154] = R[168] = CKF_RM_INITIAL; //other stuff arm_mat_init_f32(&ckf->XCP, CKF_STATE_DIM, CKF_CP_POINTS, ckf->XCP_f32); arm_mat_init_f32(&ckf->XminusCP, CKF_STATE_DIM, CKF_CP_POINTS, ckf->XminusCP_f32); arm_mat_init_f32(&ckf->YCP, CKF_MEASUREMENT_DIM, CKF_CP_POINTS, ckf->YSP_f32); ////////////////////////////////////////////////////////////////////////// arm_mat_init_f32(&ckf->K, CKF_STATE_DIM, CKF_MEASUREMENT_DIM, ckf->K_f32); arm_mat_init_f32(&ckf->KT, CKF_MEASUREMENT_DIM, CKF_STATE_DIM, ckf->KT_f32); ////////////////////////////////////////////////////////////////////////// arm_mat_init_f32(&ckf->X, CKF_STATE_DIM, 1, ckf->X_f32); arm_mat_zero_f32(&ckf->X); arm_mat_init_f32(&ckf->XT, 1, CKF_STATE_DIM, ckf->XT_f32); arm_mat_zero_f32(&ckf->XT); arm_mat_init_f32(&ckf->Xminus, CKF_STATE_DIM, 1, ckf->Xminus_f32); arm_mat_zero_f32(&ckf->Xminus); arm_mat_init_f32(&ckf->XminusT, 1, CKF_STATE_DIM, ckf->XminusT_f32); arm_mat_zero_f32(&ckf->XminusT); arm_mat_init_f32(&ckf->tmpX, CKF_STATE_DIM, 1, ckf->tmpX_f32); arm_mat_zero_f32(&ckf->tmpX); arm_mat_init_f32(&ckf->tmpS, CKF_STATE_DIM, 1, ckf->tmpS_f32); arm_mat_zero_f32(&ckf->tmpS); ////////////////////////////////////////////////////////////////////////// arm_mat_init_f32(&ckf->Y, CKF_MEASUREMENT_DIM, 1, ckf->Y_f32); arm_mat_zero_f32(&ckf->Y); arm_mat_init_f32(&ckf->YT, 1, CKF_MEASUREMENT_DIM, ckf->YT_f32); arm_mat_zero_f32(&ckf->YT); arm_mat_init_f32(&ckf->Yminus, CKF_MEASUREMENT_DIM, 1, ckf->Yminus_f32); arm_mat_zero_f32(&ckf->Yminus); arm_mat_init_f32(&ckf->YminusT, 1, CKF_MEASUREMENT_DIM, ckf->YminusT_f32); arm_mat_zero_f32(&ckf->YminusT); arm_mat_init_f32(&ckf->tmpY, CKF_MEASUREMENT_DIM, 1, ckf->tmpY_f32); arm_mat_zero_f32(&ckf->tmpY); ////////////////////////////////////////////////////////////////////////// } void CKF_Init(CKF_Filter* ckf, float32_t *q, float32_t *gyro) { float32_t *X = ckf->X_f32; float32_t norm; //initialise quaternion state X[0] = q[0]; X[1] = q[1]; X[2] = q[2]; X[3] = q[3]; norm = FastSqrtI(X[0] * X[0] + X[1] * X[1] + X[2] * X[2] + X[3] * X[3]); X[0] *= norm; X[1] *= norm; X[2] *= norm; X[3] *= norm; //initialise gyro state X[4] = gyro[0]; X[5] = gyro[1]; X[6] = gyro[2]; } void CKF_Update(CKF_Filter* ckf, float32_t *q, float32_t *gyro, float32_t *accel, float32_t *mag, float32_t dt) { int col, row; float32_t norm; #ifndef USE_4TH_RUNGE_KUTTA float32_t halfdx, halfdy, halfdz; float32_t halfdt = 0.5f * dt; #endif ////////////////////////////////////////////////////////////////////////// float32_t q0q0, q0q1, q0q2, q0q3, q1q1, q1q2, q1q3, q2q2, q2q3, q3q3; // float32_t hx, hy, hz; float32_t bx, bz; float32_t _2mx, _2my, _2mz; // float32_t *X = ckf->X_f32, *Y = ckf->Y_f32; float32_t *tmpX = ckf->tmpX_f32, *tmpY = ckf->tmpY_f32; float32_t *iKesi = ckf->iKesi_f32; float32_t *Xminus = ckf->Xminus_f32; float32_t *Yminus = ckf->Yminus_f32; float32_t *tmpS = ckf->tmpS_f32; float32_t tmpQ[4]; ////////////////////////////////////////////////////////////////////////// //time update //evaluate the cholesky factor arm_mat_chol_f32(&ckf->P); arm_mat_remainlower_f32(&ckf->P); //evaluate the cubature points arm_mat_getcolumn_f32(&ckf->Kesi, iKesi, 0); arm_mat_mult_f32(&ckf->P, &ckf->iKesi, &ckf->tmpX); arm_mat_add_f32(&ckf->tmpX, &ckf->X, &ckf->tmpX); arm_mat_setcolumn_f32(&ckf->XCP, tmpX, 0); // //evaluate the propagated cubature points #ifdef USE_4TH_RUNGE_KUTTA tmpQ[0] = 0; tmpQ[1] = tmpX[4]; tmpQ[2] = tmpX[5]; tmpQ[3] = tmpX[6]; Quaternion_RungeKutta4(tmpX, tmpQ, dt, 1); #else halfdx = halfdt * tmpX[4]; halfdy = halfdt * tmpX[5]; halfdz = halfdt * tmpX[6]; // tmpQ[0] = tmpX[0]; tmpQ[1] = tmpX[1]; tmpQ[2] = tmpX[2]; tmpQ[3] = tmpX[3]; //model prediction //simple way, pay attention!!! //according to the actual gyroscope output //and coordinate system definition tmpX[0] = tmpQ[0] + (halfdx * tmpQ[1] + halfdy * tmpQ[2] + halfdz * tmpQ[3]); tmpX[1] = tmpQ[1] - (halfdx * tmpQ[0] + halfdy * tmpQ[3] - halfdz * tmpQ[2]); tmpX[2] = tmpQ[2] + (halfdx * tmpQ[3] - halfdy * tmpQ[0] - halfdz * tmpQ[1]); tmpX[3] = tmpQ[3] - (halfdx * tmpQ[2] - halfdy * tmpQ[1] + halfdz * tmpQ[0]); ////////////////////////////////////////////////////////////////////////// //re-normalize quaternion norm = FastSqrtI(tmpX[0] * tmpX[0] + tmpX[1] * tmpX[1] + tmpX[2] * tmpX[2] + tmpX[3] * tmpX[3]); tmpX[0] *= norm; tmpX[1] *= norm; tmpX[2] *= norm; tmpX[3] *= norm; // #endif arm_mat_setcolumn_f32(&ckf->XminusCP, tmpX, 0); for(row = 0; row < CKF_STATE_DIM; row++){ tmpS[row] = tmpX[row]; } for(col = 1; col < CKF_CP_POINTS; col++){ //evaluate the cubature points arm_mat_getcolumn_f32(&ckf->Kesi, iKesi, col); arm_mat_mult_f32(&ckf->P, &ckf->iKesi, &ckf->tmpX); arm_mat_add_f32(&ckf->tmpX, &ckf->X, &ckf->tmpX); arm_mat_setcolumn_f32(&ckf->XCP, tmpX, col); // //evaluate the propagated cubature points #ifdef USE_4TH_RUNGE_KUTTA tmpQ[0] = 0; tmpQ[1] = tmpX[4]; tmpQ[2] = tmpX[5]; tmpQ[3] = tmpX[6]; Quaternion_RungeKutta4(tmpX, tmpQ, dt, 1); #else halfdx = halfdt * tmpX[4]; halfdy = halfdt * tmpX[5]; halfdz = halfdt * tmpX[6]; // tmpQ[0] = tmpX[0]; tmpQ[1] = tmpX[1]; tmpQ[2] = tmpX[2]; tmpQ[3] = tmpX[3]; //model prediction //simple way, pay attention!!! //according to the actual gyroscope output //and coordinate system definition tmpX[0] = tmpQ[0] + (halfdx * tmpQ[1] + halfdy * tmpQ[2] + halfdz * tmpQ[3]); tmpX[1] = tmpQ[1] - (halfdx * tmpQ[0] + halfdy * tmpQ[3] - halfdz * tmpQ[2]); tmpX[2] = tmpQ[2] + (halfdx * tmpQ[3] - halfdy * tmpQ[0] - halfdz * tmpQ[1]); tmpX[3] = tmpQ[3] - (halfdx * tmpQ[2] - halfdy * tmpQ[1] + halfdz * tmpQ[0]); ////////////////////////////////////////////////////////////////////////// //re-normalize quaternion norm = FastSqrtI(tmpX[0] * tmpX[0] + tmpX[1] * tmpX[1] + tmpX[2] * tmpX[2] + tmpX[3] * tmpX[3]); tmpX[0] *= norm; tmpX[1] *= norm; tmpX[2] *= norm; tmpX[3] *= norm; #endif // arm_mat_setcolumn_f32(&ckf->XminusCP, tmpX, col); for(row = 0; row < CKF_STATE_DIM; row++){ tmpS[row] += tmpX[row]; } } //estimate the predicted state arm_mat_scale_f32(&ckf->tmpS, ckf->W, &ckf->X); //estimate the predicted error covariance arm_mat_getcolumn_f32(&ckf->XminusCP, Xminus, 0); arm_mat_trans_f32(&ckf->Xminus, &ckf->XminusT); arm_mat_mult_f32(&ckf->Xminus, &ckf->XminusT, &ckf->P); for(col = 1; col < CKF_CP_POINTS; col++){ arm_mat_getcolumn_f32(&ckf->XminusCP, Xminus, col); arm_mat_trans_f32(&ckf->Xminus, &ckf->XminusT); arm_mat_mult_f32(&ckf->Xminus, &ckf->XminusT, &ckf->PX); arm_mat_add_f32(&ckf->P, &ckf->PX, &ckf->P); } arm_mat_scale_f32(&ckf->P, ckf->W, &ckf->P); arm_mat_trans_f32(&ckf->X, &ckf->XT); arm_mat_mult_f32(&ckf->X, &ckf->XT, &ckf->PX); arm_mat_sub_f32(&ckf->P, &ckf->PX, &ckf->P); arm_mat_add_f32(&ckf->P, &ckf->Q, &ckf->P); ////////////////////////////////////////////////////////////////////////// //measurement update //evaluate the cholesky factor arm_mat_chol_f32(&ckf->P); arm_mat_remainlower_f32(&ckf->P); //evaluate the cubature points arm_mat_getcolumn_f32(&ckf->Kesi, iKesi, 0); arm_mat_mult_f32(&ckf->P, &ckf->iKesi, &ckf->tmpX); arm_mat_add_f32(&ckf->tmpX, &ckf->X, &ckf->tmpX); arm_mat_setcolumn_f32(&ckf->XCP, tmpX, 0); //normalize accel and mag norm = FastSqrtI(accel[0] * accel[0] + accel[1] * accel[1] + accel[2] * accel[2]); accel[0] *= norm; accel[1] *= norm; accel[2] *= norm; ////////////////////////////////////////////////////////////////////////// norm = FastSqrtI(mag[0] * mag[0] + mag[1] * mag[1] + mag[2] * mag[2]); mag[0] *= norm; mag[1] *= norm; mag[2] *= norm; _2mx = 2.0f * mag[0]; _2my = 2.0f * mag[1]; _2mz = 2.0f * mag[2]; //auxiliary variables to avoid repeated arithmetic // q0q0 = tmpX[0] * tmpX[0]; q0q1 = tmpX[0] * tmpX[1]; q0q2 = tmpX[0] * tmpX[2]; q0q3 = tmpX[0] * tmpX[3]; q1q1 = tmpX[1] * tmpX[1]; q1q2 = tmpX[1] * tmpX[2]; q1q3 = tmpX[1] * tmpX[3]; q2q2 = tmpX[2] * tmpX[2]; q2q3 = tmpX[2] * tmpX[3]; q3q3 = tmpX[3] * tmpX[3]; //reference direction of earth's magnetic field hx = _2mx * (0.5f - q2q2 - q3q3) + _2my * (q1q2 - q0q3) + _2mz *(q1q3 + q0q2); hy = _2mx * (q1q2 + q0q3) + _2my * (0.5f - q1q1 - q3q3) + _2mz * (q2q3 - q0q1); hz = _2mx * (q1q3 - q0q2) + _2my * (q2q3 + q0q1) + _2mz *(0.5f - q1q1 - q2q2); arm_sqrt_f32(hx * hx + hy * hy, &bx); bz = hz; tmpY[0] = tmpX[0]; tmpY[1] = tmpX[1]; tmpY[2] = tmpX[2]; tmpY[3] = tmpX[3]; tmpY[4] = 2.0f * (q1q3 - q0q2); tmpY[5] = 2.0f * (q2q3 + q0q1); tmpY[6] = -1.0f + 2.0f * (q0q0 + q3q3); tmpY[7] = tmpX[4]; tmpY[8] = tmpX[5]; tmpY[9] = tmpX[6]; tmpY[10] = bx * (1.0f - 2.0f * (q2q2 + q3q3)) + bz * ( 2.0f * (q1q3 - q0q2)); tmpY[11] = bx * (2.0f * (q1q2 - q0q3)) + bz * (2.0f * (q2q3 + q0q1)); tmpY[12] = bx * (2.0f * (q1q3 + q0q2)) + bz * (1.0f - 2.0f * (q1q1 + q2q2)); arm_mat_setcolumn_f32(&ckf->YCP, tmpY, 0); for(row = 0; row < CKF_MEASUREMENT_DIM; row++){ Y[row] = tmpY[row]; } for(col = 1; col < CKF_CP_POINTS; col++){ //evaluate the cubature points arm_mat_getcolumn_f32(&ckf->Kesi, iKesi, col); arm_mat_mult_f32(&ckf->P, &ckf->iKesi, &ckf->tmpX); arm_mat_add_f32(&ckf->tmpX, &ckf->X, &ckf->tmpX); arm_mat_setcolumn_f32(&ckf->XCP, tmpX, col); //auxiliary variables to avoid repeated arithmetic // q0q0 = tmpX[0] * tmpX[0]; q0q1 = tmpX[0] * tmpX[1]; q0q2 = tmpX[0] * tmpX[2]; q0q3 = tmpX[0] * tmpX[3]; q1q1 = tmpX[1] * tmpX[1]; q1q2 = tmpX[1] * tmpX[2]; q1q3 = tmpX[1] * tmpX[3]; q2q2 = tmpX[2] * tmpX[2]; q2q3 = tmpX[2] * tmpX[3]; q3q3 = tmpX[3] * tmpX[3]; //reference direction of earth's magnetic field hx = _2mx * (0.5f - q2q2 - q3q3) + _2my * (q1q2 - q0q3) + _2mz *(q1q3 + q0q2); hy = _2mx * (q1q2 + q0q3) + _2my * (0.5f - q1q1 - q3q3) + _2mz * (q2q3 - q0q1); hz = _2mx * (q1q3 - q0q2) + _2my * (q2q3 + q0q1) + _2mz *(0.5f - q1q1 - q2q2); arm_sqrt_f32(hx * hx + hy * hy, &bx); bz = hz; tmpY[0] = tmpX[0]; tmpY[1] = tmpX[1]; tmpY[2] = tmpX[2]; tmpY[3] = tmpX[3]; tmpY[4] = 2.0f * (q1q3 - q0q2); tmpY[5] = 2.0f * (q2q3 + q0q1); tmpY[6] = -1.0f + 2.0f * (q0q0 + q3q3); tmpY[7] = tmpX[4]; tmpY[8] = tmpX[5]; tmpY[9] = tmpX[6]; tmpY[10] = bx * (1.0f - 2.0f * (q2q2 + q3q3)) + bz * ( 2.0f * (q1q3 - q0q2)); tmpY[11] = bx * (2.0f * (q1q2 - q0q3)) + bz * (2.0f * (q2q3 + q0q1)); tmpY[12] = bx * (2.0f * (q1q3 + q0q2)) + bz * (1.0f - 2.0f * (q1q1 + q2q2)); arm_mat_setcolumn_f32(&ckf->YCP, tmpY, col); for(row = 0; row < CKF_MEASUREMENT_DIM; row++){ Y[row] += tmpY[row]; } } //estimate the predicted measurement arm_mat_scale_f32(&ckf->Y, ckf->W, &ckf->Y); //estimate the innovation covariance matrix arm_mat_getcolumn_f32(&ckf->YCP, Yminus, 0); arm_mat_trans_f32(&ckf->Yminus, &ckf->YminusT); arm_mat_mult_f32(&ckf->Yminus, &ckf->YminusT, &ckf->PY); for(col = 1; col < CKF_CP_POINTS; col++){ arm_mat_getcolumn_f32(&ckf->YCP, Yminus, col); arm_mat_trans_f32(&ckf->Yminus, &ckf->YminusT); arm_mat_mult_f32(&ckf->Yminus, &ckf->YminusT, &ckf->tmpPY); arm_mat_add_f32(&ckf->PY, &ckf->tmpPY, &ckf->PY); } arm_mat_scale_f32(&ckf->PY, ckf->W, &ckf->PY); arm_mat_trans_f32(&ckf->Y, &ckf->YT); arm_mat_mult_f32(&ckf->Y, &ckf->YT, &ckf->tmpPY); arm_mat_sub_f32(&ckf->PY, &ckf->tmpPY, &ckf->PY); arm_mat_add_f32(&ckf->PY, &ckf->R, &ckf->PY); //estimate the cross-covariance matrix arm_mat_getcolumn_f32(&ckf->XCP, Xminus, 0); arm_mat_getcolumn_f32(&ckf->YCP, Yminus, 0); arm_mat_trans_f32(&ckf->Yminus, &ckf->YminusT); arm_mat_mult_f32(&ckf->Xminus, &ckf->YminusT, &ckf->PXY); arm_mat_scale_f32(&ckf->PXY, ckf->W, &ckf->PXY); for(col = 1; col < CKF_CP_POINTS; col++){ arm_mat_getcolumn_f32(&ckf->XCP, Xminus, col); arm_mat_getcolumn_f32(&ckf->YCP, Yminus, col); arm_mat_trans_f32(&ckf->Yminus, &ckf->YminusT); arm_mat_mult_f32(&ckf->Xminus, &ckf->YminusT, &ckf->tmpPXY); arm_mat_scale_f32(&ckf->tmpPXY, ckf->W, &ckf->tmpPXY); arm_mat_add_f32(&ckf->PXY, &ckf->tmpPXY, &ckf->PXY); } //arm_mat_scale_f32(&ckf->PXY, ckf->W, &ckf->PXY); arm_mat_trans_f32(&ckf->Y, &ckf->YT); arm_mat_mult_f32(&ckf->X, &ckf->YT, &ckf->tmpPXY); arm_mat_sub_f32(&ckf->PXY, &ckf->tmpPXY, &ckf->PXY); //estimate the kalman gain //K = PXY * inv(PY); arm_mat_inverse_f32(&ckf->PY, &ckf->tmpPY); arm_mat_mult_f32(&ckf->PXY, &ckf->tmpPY, &ckf->K); //estimate the updated state //X = X + K*(z - Y); Y[0] = q[0] - Y[0]; Y[1] = q[1] - Y[1]; Y[2] = q[2] - Y[2]; Y[3] = q[3] - Y[3]; // Y[4] = accel[0] - Y[4]; Y[5] = accel[1] - Y[5]; Y[6] = accel[2] - Y[6]; Y[7] = gyro[0] - Y[7]; Y[8] = gyro[1] - Y[8]; Y[9] = gyro[2] - Y[9]; ////////////////////////////////////////////////////////////////////////// Y[10] = mag[0] - Y[10]; Y[11] = mag[1] - Y[11]; Y[12] = mag[2] - Y[12]; arm_mat_mult_f32(&ckf->K, &ckf->Y, &ckf->tmpX); arm_mat_add_f32(&ckf->X, &ckf->tmpX, &ckf->X); //normalize quaternion norm = FastSqrtI(X[0] * X[0] + X[1] * X[1] + X[2] * X[2] + X[3] * X[3]); X[0] *= norm; X[1] *= norm; X[2] *= norm; X[3] *= norm; //estimate the corresponding error covariance //the default tuning parameters don't work properly //must tune the P,Q,R and calibrate the sensor data //P = P - K * PY * K' arm_mat_trans_f32(&ckf->K, &ckf->KT); arm_mat_mult_f32(&ckf->K, &ckf->PY, &ckf->PXY); arm_mat_mult_f32(&ckf->PXY, &ckf->KT, &ckf->PX); arm_mat_sub_f32(&ckf->P, &ckf->PX, &ckf->P); } void CKF_GetAngle(CKF_Filter* ckf, float32_t* rpy) { float32_t R[3][3]; float32_t *X = ckf->X_f32; //Z-Y-X R[0][0] = 2.0f * (X[0] * X[0] + X[1] * X[1]) - 1.0f; R[0][1] = 2.0f * (X[1] * X[2] + X[0] * X[3]); R[0][2] = 2.0f * (X[1] * X[3] - X[0] * X[2]); //R[1][0] = 2.0f * (X[1] * X[2] - X[0] * X[3]); //R[1][1] = 2.0f * (X[0] * X[0] + X[2] * X[2]) - 1.0f; R[1][2] = 2.0f * (X[2] * X[3] + X[0] * X[1]); //R[2][0] = 2.0f * (X[1] * X[3] + X[0] * X[2]); //R[2][1] = 2.0f * (X[2] * X[3] - X[0] * X[1]); R[2][2] = 2.0f * (X[0] * X[0] + X[3] * X[3]) - 1.0f; //roll rpy[0] = FastAtan2(R[1][2], R[2][2]); if (rpy[0] == CKF_PI) rpy[0] = -CKF_PI; //pitch if (R[0][2] >= 1.0f) rpy[1] = -CKF_HALFPI; else if (R[0][2] <= -1.0f) rpy[1] = CKF_HALFPI; else rpy[1] = FastAsin(-R[0][2]); //yaw rpy[2] = FastAtan2(R[0][1], R[0][0]); if (rpy[2] < 0.0f){ rpy[2] += CKF_TWOPI; } if (rpy[2] > CKF_TWOPI){ rpy[2] = 0.0f; } rpy[0] = CKF_TODEG(rpy[0]); rpy[1] = CKF_TODEG(rpy[1]); rpy[2] = CKF_TODEG(rpy[2]); } ================================================ FILE: Algorithm/src/Control.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "Control.h" #include "FastMath.h" int Matrix_Inv3x3(float* A) { // det = a11(a33a22-a32a23)-a21(a33a12-a32a13)+a31(a23a12-a22a13) // det = a00(a22a11-a21a12)-a10(a22a01-a21a02)+a20(a12a01-a11a02) float det; float M[9]; // Invert the matrix /* | a11 a12 a13 |-1 | a33a22-a32a23 -(a33a12-a32a13) a23a12-a22a13 | | a21 a22 a23 | = 1/DET * | -(a33a21-a31a23) a33a11-a31a13 -(a23a11-a21a13) | | a31 a32 a33 | | a32a21-a31a22 -(a32a11-a31a12) a22a11-a21a12 | | a00 a01 a02 |-1 | a22a11-a21a12 -(a22a01-a21a02) a12a01-a11a02 | | a10 a11 a12 | = 1/DET * | -(a22a10-a20a12) a22a00-a20a02 -(a12a00-a10a02) | | a20 a21 a22 | | a21a10-a20a11 -(a21a00-a20a01) a11a00-a10a01 | */ det = A[0] * (A[8] * A[4] - A[7] * A[5]) - A[3] * (A[8] * A[1] - A[7] * A[2]) + A[6] * (A[5] * A[1] - A[4] * A[2]); // Row 1 // M[0] = (a22a11-a21a12)/det; M[0] = (A[8] * A[4] - A[7] * A[5]) / det; // M[1] = -(a22a01-a21a02)/det; M[1] = -(A[8] * A[1] - A[7] * A[2]) / det; // M[2] = (a12a01-a11a02)/det; M[2] = (A[5] * A[1] - A[4] * A[2]) / det; // Row 2 // M[3] = -(a22a10-a20a12)/det; M[3] = -(A[8] * A[3] - A[6] * A[5]) / det; // M[4] = (a22a00-a20a02)/det; M[4] = (A[8] * A[0] - A[6] * A[2]) / det; // M[5] = -(a12a00-a10a02)/det; M[5] = -(A[5] * A[0] - A[3] * A[2]) / det; // Row 3 // M[6] = (a21a10-a20a11)/det; M[6] = (A[7] * A[3] - A[6] * A[4]) / det; // M[7] = -(a21a00-a20a01)/det; M[7] = -(A[7] * A[0] - A[6] * A[1]) / det; // M[8] = (a11a00-a10a01)/det; M[8] = (A[4] * A[0] - A[3] * A[1]) / det; A[0] = M[0]; A[1] = M[1]; A[2] = M[2]; A[3] = M[3]; A[4] = M[4]; A[5] = M[5]; A[6] = M[6]; A[7] = M[7]; A[8] = M[8]; return 1; } //sweep void Matrix_Inv(float *A, int n) { float d; int i, j, k; int kn, kk; int ln, lk; for (k = 0; k < n; ++k){ kn = k * n; kk = kn + k; d = 1.0f / A[kk]; A[kk] = d; for (i = 0; i < n; ++i){ if (i != k){ A[kn + i] *= -d; } } for (i = 0; i < n; ++i){ if ( i != k){ A[i * n + k] *= d; } } for (i = 0; i < n; ++i){ if (i != k){ ln = i * n; lk = ln + k; for (j = 0; j < n; ++j){ if (j != k ){ A[ln + j] += A[lk] * A[kn + j] / d; } } } } } } static QuadrotorParameter gQuadrotorParameter = { 0, }; void EulerConv(float* dt, float *deta) { float dx = dt[X]; float dy = dt[Y]; float dz = dt[Z]; float psi = dt[PSI]; float d; float spsi, cpsi; FastSinCos(psi, &spsi, &cpsi); d = FastSqrt(dx * dx + dy * dy + dz * dz); if (-0.001f < d && d < 0.001f){ deta[ROLL] = 0; } else{ deta[ROLL] = FastAsin((dx * spsi - dy * cpsi)/d); } deta[PITCH] = FastAtan2(dx * cpsi + dy * spsi, dz); if(deta[ROLL] < MIN_ANG){ deta[ROLL] = MIN_ANG; } else if(deta[ROLL] > MAX_ANG){ deta[ROLL] = MAX_ANG; } if(deta[PITCH] < MIN_ANG){ deta[PITCH] = MIN_ANG; } else if(deta[PITCH] > MAX_ANG){ deta[PITCH] = MAX_ANG; } deta[YAW] = psi; } void TorqueConv(float *eta, float *deta, float *dt) { float sphi, cphi; float stht, ctht; float spsi, cpsi; float C[9]; float sum[9]; float* I = gQuadrotorParameter.I; FastSinCos(eta[ROLL], &sphi, &cphi); FastSinCos(eta[PITCH], &stht, &ctht); FastSinCos(eta[YAW], &spsi, &cpsi); C[0] = 1; C[1] = 0; C[2] = -stht; C[3] = 0; C[4] = cphi; C[5] = sphi * ctht; C[6] = 0; C[7] = -sphi; C[8] = cphi * ctht; //torque = I * C * euler; sum[0] = I[0] * C[0] + I[1] * C[3] + I[2] * C[6]; sum[1] = I[0] * C[1] + I[1] * C[4] + I[2] * C[7]; sum[2] = I[0] * C[2] + I[1] * C[5] + I[2] * C[8]; sum[3] = I[3] * C[0] + I[4] * C[3] + I[5] * C[6]; sum[4] = I[3] * C[1] + I[4] * C[4] + I[5] * C[7]; sum[5] = I[3] * C[2] + I[4] * C[5] + I[5] * C[8]; sum[6] = I[6] * C[0] + I[7] * C[3] + I[8] * C[6]; sum[7] = I[6] * C[1] + I[7] * C[4] + I[8] * C[7]; sum[8] = I[6] * C[2] + I[7] * C[5] + I[8] * C[8]; dt[0] = sum[0] * deta[ROLL] + sum[1] * deta[PITCH] + sum[2] * deta[YAW]; dt[1] = sum[0] * deta[ROLL] + sum[1] * deta[PITCH] + sum[2] * deta[YAW]; dt[2] = sum[0] * deta[ROLL] + sum[1] * deta[PITCH] + sum[2] * deta[YAW]; } void ForceConv(float *eta, float dz, float *df) { float sphi, cphi; float stht, ctht; float spsi, cpsi; float R[9]; float m = gQuadrotorParameter.m; FastSinCos(eta[ROLL], &sphi, &cphi); FastSinCos(eta[PITCH], &stht, &ctht); FastSinCos(eta[YAW], &spsi, &cpsi); R[0] = cpsi * ctht; R[1] = cpsi * stht * sphi - spsi * cphi; R[2] = cpsi * stht * cphi + spsi * sphi; R[3] = spsi * ctht; R[4] = spsi * stht * sphi + cpsi * cphi; R[5] = spsi * stht * cphi - cpsi * sphi; R[6] = -stht; R[7] = ctht * sphi; R[8] = ctht * cphi; Matrix_Inv3x3(R); //u = {0, 0, dz}; //d = m * inv(R) * u; //fd = d[2]; R[8] *= m; *df = R[8] * dz; } void TorqueInv(float *dt, float df, float *domega) { float T[16]; float u[4]; float b = gQuadrotorParameter.b; float d = gQuadrotorParameter.d; float l = gQuadrotorParameter.l; T[0] = b; T[1] = b; T[2] = b; T[3] = b; T[4] = 0; T[5] = -l * b; T[6] = 0; T[7] = l * b; T[8] = -l * b; T[9] = 0; T[10] = l * b; T[11] = 0; T[12] = -d; T[13] = d; T[14] = -d; T[15] = d; u[0] = df; u[1] = dt[0]; u[2] = dt[1]; u[3] = dt[2]; //omega = inv(T) * u; Matrix_Inv(T, 4); domega[0] = T[0] * u[0] + T[1] * u[1] + T[2] * u[2] + T[3] * u[3]; domega[1] = T[4] * u[0] + T[5] * u[1] + T[6] * u[2] + T[7] * u[3]; domega[2] = T[8] * u[0] + T[9] * u[1] + T[10] * u[2] + T[11] * u[3]; domega[3] = T[12] * u[0] + T[13] * u[1] + T[14] * u[2] + T[15] * u[3]; } // Newton-Euler model void QuadrotorControl(float* task, float *q, float *u) { task[0] = PID_Calculate(&gQuadrotorParameter.PostionX, gQuadrotorParameter.X - task[0]); task[1] = PID_Calculate(&gQuadrotorParameter.PostionY, gQuadrotorParameter.Y - task[1]); task[2] = PID_Calculate(&gQuadrotorParameter.PostionZ, gQuadrotorParameter.Z - task[2]); //EulerConv( // quadrotor linear acceleration along zE WRT E-frame // quadrotor angular acceleration around x2 WRT E-frame (roll) // theta quadrotor angular acceleration around y1 WRT E-frame (pitch) // quadrotor angular acceleration around zE WRT E-frame (yaw) // The first one shows how the quadrotor accelerates according to // the basic movement commands given. // The second system of equations explains how the basic movements are related // to the propellers squared speed. // The third equation takes into accounts the motors dynamics and shows the // relation between propellers speed and motors voltage. } ================================================ FILE: Algorithm/src/EKF.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "EKF.h" #include "FastMath.h" #include "Quaternion.h" #define USE_4TH_RUNGE_KUTTA ////////////////////////////////////////////////////////////////////////// //all parameters below need to be tune #define EKF_PQ_INITIAL 0.000001f #define EKF_PW_INITIAL 0.000010f #define EKF_QQ_INITIAL 0.000045f #define EKF_QW_INITIAL 0.00025f #define EKF_RQ_INITIAL 0.000001f #define EKF_RA_INITIAL 0.07f #define EKF_RW_INITIAL 0.525f #define EKF_RM_INITIAL 0.105f ////////////////////////////////////////////////////////////////////////// void EKF_New(EKF_Filter* ekf) { float32_t *H = ekf->H_f32; float32_t *P = ekf->P_f32; float32_t *Q = ekf->Q_f32; float32_t *R = ekf->R_f32; ////////////////////////////////////////////////////////////////////////// arm_mat_init_f32(&ekf->P, EKF_STATE_DIM, EKF_STATE_DIM, ekf->P_f32); arm_mat_zero_f32(&ekf->P); P[0] = P[8] = P[16] = P[24] = EKF_PQ_INITIAL; P[32] = P[40] = P[48] = EKF_PW_INITIAL; // arm_mat_init_f32(&ekf->Q, EKF_STATE_DIM, EKF_STATE_DIM, ekf->Q_f32); arm_mat_zero_f32(&ekf->Q); Q[0] = Q[8] = Q[16] = Q[24] = EKF_QQ_INITIAL; Q[32] = Q[40] = Q[48] = EKF_QW_INITIAL; // arm_mat_init_f32(&ekf->R, EKF_MEASUREMENT_DIM, EKF_MEASUREMENT_DIM, ekf->R_f32); arm_mat_zero_f32(&ekf->R); R[0] = R[14] = R[28] = R[42] = EKF_RQ_INITIAL; R[56] = R[70] = R[84] = EKF_RA_INITIAL; R[98] = R[112] = R[126] = EKF_RW_INITIAL; R[140] = R[154] = R[168] = EKF_RM_INITIAL; ////////////////////////////////////////////////////////////////////////// arm_mat_init_f32(&ekf->K, EKF_STATE_DIM, EKF_MEASUREMENT_DIM, ekf->K_f32); arm_mat_init_f32(&ekf->KT, EKF_MEASUREMENT_DIM, EKF_STATE_DIM, ekf->KT_f32); arm_mat_init_f32(&ekf->S, EKF_MEASUREMENT_DIM, EKF_MEASUREMENT_DIM, ekf->S_f32); // arm_mat_init_f32(&ekf->F, EKF_STATE_DIM, EKF_STATE_DIM, ekf->F_f32); arm_mat_zero_f32(&ekf->F); arm_mat_identity_f32(&ekf->F, 1.0f); // arm_mat_init_f32(&ekf->FT, EKF_STATE_DIM, EKF_STATE_DIM, ekf->FT_f32); // arm_mat_init_f32(&ekf->H, EKF_MEASUREMENT_DIM, EKF_STATE_DIM, H); arm_mat_zero_f32(&ekf->H); H[0] = H[8] = H[16] = H[24] = 1.0f; //q row 0~3, col 0~3 H[53] = H[61] = H[69] = 1.0f; //w row 7~9, col 4~6 // arm_mat_init_f32(&ekf->HT, EKF_STATE_DIM, EKF_MEASUREMENT_DIM, ekf->HT_f32); ////////////////////////////////////////////////////////////////////////// arm_mat_init_f32(&ekf->I, EKF_STATE_DIM, EKF_STATE_DIM, ekf->I_f32); arm_mat_zero_f32(&ekf->I); arm_mat_identity_f32(&ekf->I, 1.0f); ////////////////////////////////////////////////////////////////////////// arm_mat_init_f32(&ekf->X, EKF_STATE_DIM, 1, ekf->X_f32); arm_mat_zero_f32(&ekf->X); ////////////////////////////////////////////////////////////////////////// arm_mat_init_f32(&ekf->Y, EKF_MEASUREMENT_DIM, 1, ekf->Y_f32); arm_mat_zero_f32(&ekf->Y); ////////////////////////////////////////////////////////////////////////// // arm_mat_init_f32(&ekf->tmpP, EKF_STATE_DIM, EKF_STATE_DIM, ekf->tmpP_f32); arm_mat_init_f32(&ekf->tmpX, EKF_STATE_DIM, 1, ekf->tmpX_f32); arm_mat_init_f32(&ekf->tmpYX, EKF_MEASUREMENT_DIM, EKF_STATE_DIM, ekf->tmpYX_f32); arm_mat_init_f32(&ekf->tmpXY, EKF_STATE_DIM, EKF_MEASUREMENT_DIM, ekf->tmpXY_f32); arm_mat_init_f32(&ekf->tmpXX, EKF_STATE_DIM, EKF_STATE_DIM, ekf->tmpXX_f32); arm_mat_init_f32(&ekf->tmpXXT, EKF_STATE_DIM, EKF_STATE_DIM, ekf->tmpXXT_f32); arm_mat_init_f32(&ekf->tmpS, EKF_MEASUREMENT_DIM, EKF_MEASUREMENT_DIM, ekf->tmpS_f32); ////////////////////////////////////////////////////////////////////////// } void EKF_Init(EKF_Filter* ekf, float32_t *q, float32_t *gyro) { float32_t *X = ekf->X_f32; float32_t norm; X[0] = q[0]; X[1] = q[1]; X[2] = q[2]; X[3] = q[3]; norm = FastSqrtI(X[0] * X[0] + X[1] * X[1] + X[2] * X[2] + X[3] * X[3]); X[0] *= norm; X[1] *= norm; X[2] *= norm; X[3] *= norm; X[4] = gyro[0]; X[5] = gyro[1]; X[6] = gyro[2]; } void EFK_Update(EKF_Filter* ekf, float32_t *q, float32_t *gyro, float32_t *accel, float32_t *mag, float32_t dt) { float32_t norm; float32_t h[EKF_MEASUREMENT_DIM]; float32_t halfdx, halfdy, halfdz; float32_t neghalfdx, neghalfdy, neghalfdz; float32_t halfdtq0, halfdtq1, neghalfdtq1, halfdtq2, neghalfdtq2, halfdtq3, neghalfdtq3; float32_t halfdt = 0.5f * dt; #ifdef USE_4TH_RUNGE_KUTTA float32_t tmpW[4]; #endif ////////////////////////////////////////////////////////////////////////// float32_t q0q0, q0q1, q0q2, q0q3, q1q1, q1q2, q1q3, q2q2, q2q3, q3q3; float32_t _2q0,_2q1,_2q2,_2q3; float32_t q0, q1, q2, q3; // float32_t hx, hy, hz; float32_t bx, bz; float32_t _2mx, _2my, _2mz; // float32_t *H = ekf->H_f32, *F = ekf->F_f32; float32_t *X = ekf->X_f32, *Y = ekf->Y_f32; ////////////////////////////////////////////////////////////////////////// halfdx = halfdt * X[4]; neghalfdx = -halfdx; halfdy = halfdt * X[5]; neghalfdy = -halfdy; halfdz = halfdt * X[6]; neghalfdz = -halfdz; // q0 = X[0]; q1 = X[1]; q2 = X[2]; q3 = X[3]; halfdtq0 = halfdt * q0; halfdtq1 = halfdt * q1; neghalfdtq1 = -halfdtq1; halfdtq2 = halfdt * q2; neghalfdtq2 = -halfdtq2; halfdtq3 = halfdt * q3; neghalfdtq3 = -halfdtq3; //F[0] = 1.0f; F[1] = neghalfdx; F[2] = neghalfdy; F[3] = neghalfdz; F[4] = neghalfdtq1; F[5] = neghalfdtq2; F[6] = neghalfdtq3; F[7] = halfdx; //F[8] = 1.0f; F[9] = neghalfdz; F[10] = halfdy; F[11] = halfdtq0; F[12] = halfdtq3; F[13] = neghalfdtq2; F[14] = halfdy; F[15] = halfdz; //F[16] = 1.0f; F[17] = neghalfdx; F[18] = neghalfdtq3; F[19] = halfdtq0; F[20] = neghalfdtq1; F[21] = halfdz; F[22] = neghalfdy; F[23] = halfdx; //F[24] = 1.0f; F[25] = halfdtq2; F[26] = neghalfdtq1; F[27] = halfdtq0; //model prediction //simple way, pay attention!!! //according to the actual gyroscope output //and coordinate system definition #ifdef USE_4TH_RUNGE_KUTTA tmpW[0] = 0; tmpW[1] = X[4]; tmpW[2] = X[5]; tmpW[3] = X[6]; Quaternion_RungeKutta4(X, tmpW, dt, 1); #else X[0] = q0 - (halfdx * q1 + halfdy * q2 + halfdz * q3); X[1] = q1 + (halfdx * q0 + halfdy * q3 - halfdz * q2); X[2] = q2 - (halfdx * q3 - halfdy * q0 - halfdz * q1); X[3] = q3 + (halfdx * q2 - halfdy * q1 + halfdz * q0); ////////////////////////////////////////////////////////////////////////// //Re-normalize Quaternion norm = FastSqrtI(X[0] * X[0] + X[1] * X[1] + X[2] * X[2] + X[3] * X[3]); X[0] *= norm; X[1] *= norm; X[2] *= norm; X[3] *= norm; #endif //X covariance matrix update based on model //P = F*P*F' + Q; arm_mat_trans_f32(&ekf->F, &ekf->FT); arm_mat_mult_f32(&ekf->F, &ekf->P, &ekf->tmpP); arm_mat_mult_f32(&ekf->tmpP, &ekf->FT, &ekf->P); arm_mat_add_f32(&ekf->P, &ekf->Q, &ekf->tmpP); ////////////////////////////////////////////////////////////////////////// //model and measurement differences //normalize acc and mag measurements norm = FastSqrtI(accel[0] * accel[0] + accel[1] * accel[1] + accel[2] * accel[2]); accel[0] *= norm; accel[1] *= norm; accel[2] *= norm; ////////////////////////////////////////////////////////////////////////// norm = FastSqrtI(mag[0] * mag[0] + mag[1] * mag[1] + mag[2] * mag[2]); mag[0] *= norm; mag[1] *= norm; mag[2] *= norm; //Auxiliary variables to avoid repeated arithmetic _2q0 = 2.0f * X[0]; _2q1 = 2.0f * X[1]; _2q2 = 2.0f * X[2]; _2q3 = 2.0f * X[3]; // q0q0 = X[0] * X[0]; q0q1 = X[0] * X[1]; q0q2 = X[0] * X[2]; q0q3 = X[0] * X[3]; q1q1 = X[1] * X[1]; q1q2 = X[1] * X[2]; q1q3 = X[1] * X[3]; q2q2 = X[2] * X[2]; q2q3 = X[2] * X[3]; q3q3 = X[3] * X[3]; _2mx = 2.0f * mag[0]; _2my = 2.0f * mag[1]; _2mz = 2.0f * mag[2]; //Reference direction of Earth's magnetic field hx = _2mx * (0.5f - q2q2 - q3q3) + _2my * (q1q2 - q0q3) + _2mz *(q1q3 + q0q2); hy = _2mx * (q1q2 + q0q3) + _2my * (0.5f - q1q1 - q3q3) + _2mz * (q2q3 - q0q1); hz = _2mx * (q1q3 - q0q2) + _2my * (q2q3 + q0q1) + _2mz *(0.5f - q1q1 - q2q2); arm_sqrt_f32(hx * hx + hy * hy, &bx); bz = hz; h[0] = X[0]; h[1] = X[1]; h[2] = X[2]; h[3] = X[3]; h[4] = 2.0f * (q1q3 - q0q2); h[5] = 2.0f * (q2q3 + q0q1); h[6] = -1.0f + 2.0f * (q0q0 + q3q3); h[7] = X[4]; h[8] = X[5]; h[9] = X[6]; h[10] = bx * (1.0f - 2.0f * (q2q2 + q3q3)) + bz * ( 2.0f * (q1q3 - q0q2)); h[11] = bx * (2.0f * (q1q2 - q0q3)) + bz * (2.0f * (q2q3 + q0q1)); h[12] = bx * (2.0f * (q1q3 + q0q2)) + bz * (1.0f - 2.0f * (q1q1 + q2q2)); ///////////////////////////////////////////////////////////////////////// //The H matrix maps the measurement to the states 13 x 7 //row started from 0 to 12, col started from 0 to 6 //row 4, col 0~3 H[28] = -_2q2; H[29] = _2q3; H[30] = -_2q0; H[31] = _2q1; //row 5, col 0~3 H[35] = _2q1; H[36] = _2q0; H[37] = _2q3; H[38] = _2q2; //row 6, col 0~3 H[42] = _2q0; H[43] = -_2q1; H[44] = -_2q2; H[45] = _2q3; //row 10, col 0~3 H[70] = bx * _2q0 - bz * _2q2; H[71] = bx * _2q1 + bz * _2q3; H[72] = -bx * _2q2 - bz * _2q0; H[73] = bz * _2q1 - bx * _2q3; //row 11, col 0~3 H[77] = bz * _2q1 - bx * _2q3; H[78] = bx * _2q2 + bz * _2q0; H[79] = bx * _2q1 + bz * _2q3; H[80] = bz * _2q2 - bx * _2q0; //row 12, col 0~3 H[84] = bx * _2q2 + bz * _2q0; H[85] = bx * _2q3 - bz * _2q1; H[86] = bx * _2q0 - bz * _2q2; H[87] = bx * _2q1 + bz * _2q3; // //y = z - h; Y[0] = q[0] - h[0]; Y[1] = q[1] - h[1]; Y[2] = q[2] - h[2]; Y[3] = q[3] - h[3]; // Y[4] = accel[0] - h[4]; Y[5] = accel[1] - h[5]; Y[6] = accel[2] - h[6]; Y[7] = gyro[0] - h[7]; Y[8] = gyro[1] - h[8]; Y[9] = gyro[2] - h[9]; ////////////////////////////////////////////////////////////////////////// Y[10] = mag[0] - h[10]; Y[11] = mag[1] - h[11]; Y[12] = mag[2] - h[12]; ////////////////////////////////////////////////////////////////////////// //Measurement covariance update //S = H*P*H' + R; arm_mat_trans_f32(&ekf->H, &ekf->HT); arm_mat_mult_f32(&ekf->H, &ekf->tmpP, &ekf->tmpYX); arm_mat_mult_f32(&ekf->tmpYX, &ekf->HT, &ekf->S); arm_mat_add_f32(&ekf->S, &ekf->R, &ekf->tmpS); //Calculate Kalman gain //K = P*H'/S; arm_mat_inverse_f32(&ekf->tmpS, &ekf->S); arm_mat_mult_f32(&ekf->tmpP, &ekf->HT, &ekf->tmpXY); arm_mat_mult_f32(&ekf->tmpXY, &ekf->S, &ekf->K); //Corrected model prediction //S = S + K*y; arm_mat_mult_f32(&ekf->K, &ekf->Y, &ekf->tmpX); arm_mat_add_f32(&ekf->X, &ekf->tmpX, &ekf->X); //normalize quaternion norm = FastSqrtI(X[0] * X[0] + X[1] * X[1] + X[2] * X[2] + X[3] * X[3]); X[0] *= norm; X[1] *= norm; X[2] *= norm; X[3] *= norm; //Update state covariance with new knowledge //option: P = P - K*H*P or P = (I - K*H)*P*(I - K*H)' + K*R*K' #if 0 //P = P - K*H*P //simple but it can't ensure the matrix will be a positive definite matrix arm_mat_mult_f32(&ekf->K, &ekf->H, &ekf->tmpXX); arm_mat_mult_f32(&ekf->tmpXX, &ekf->tmpP, &ekf->P); arm_mat_sub_f32(&ekf->tmpP, &ekf->P, &ekf->P); #else //P=(I - K*H)*P*(I - K*H)' + K*R*K' arm_mat_mult_f32(&ekf->K, &ekf->H, &ekf->tmpXX); arm_mat_sub_f32(&ekf->I, &ekf->tmpXX, &ekf->tmpXX); arm_mat_trans_f32(&ekf->tmpXX, &ekf->tmpXXT); arm_mat_mult_f32(&ekf->tmpXX, &ekf->tmpP, &ekf->P); arm_mat_mult_f32(&ekf->P, &ekf->tmpXXT, &ekf->tmpP); arm_mat_trans_f32(&ekf->K, &ekf->KT); arm_mat_mult_f32(&ekf->K, &ekf->R, &ekf->tmpXY); arm_mat_mult_f32(&ekf->tmpXY, &ekf->KT, &ekf->tmpXX); arm_mat_add_f32(&ekf->tmpP, &ekf->tmpXX, &ekf->P); #endif } void EKF_GetAngle(EKF_Filter* ekf, float32_t* rpy) { float32_t R[3][3]; float32_t *X = ekf->X_f32; //Z-Y-X R[0][0] = 2.0f * (X[0] * X[0] + X[1] * X[1]) - 1.0f; R[0][1] = 2.0f * (X[1] * X[2] + X[0] * X[3]); R[0][2] = 2.0f * (X[1] * X[3] - X[0] * X[2]); //R[1][0] = 2.0f * (X[1] * X[2] - X[0] * X[3]); //R[1][1] = 2.0f * (X[0] * X[0] + X[2] * X[2]) - 1.0f; R[1][2] = 2.0f * (X[2] * X[3] + X[0] * X[1]); //R[2][0] = 2.0f * (X[1] * X[3] + X[0] * X[2]); //R[2][1] = 2.0f * (X[2] * X[3] - X[0] * X[1]); R[2][2] = 2.0f * (X[0] * X[0] + X[3] * X[3]) - 1.0f; //roll rpy[0] = FastAtan2(R[1][2], R[2][2]); if (rpy[0] == EKF_PI) rpy[0] = -EKF_PI; //pitch if (R[0][2] >= 1.0f) rpy[1] = -EKF_HALFPI; else if (R[0][2] <= -1.0f) rpy[1] = EKF_HALFPI; else rpy[1] = FastAsin(-R[0][2]); //yaw rpy[2] = FastAtan2(R[0][1], R[0][0]); if (rpy[2] < 0.0f){ rpy[2] += EKF_TWOPI; } if (rpy[2] > EKF_TWOPI){ rpy[2] = 0.0f; } rpy[0] = EKF_TODEG(rpy[0]); rpy[1] = EKF_TODEG(rpy[1]); rpy[2] = EKF_TODEG(rpy[2]); } ================================================ FILE: Algorithm/src/INS_EKF.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "INS_EKF.h" #include "FastMath.h" #include "Quaternion.h" #define USE_4TH_RUNGE_KUTTA ////////////////////////////////////////////////////////////////////////// //all parameters below need to be tune #define INS_EKF_PQ_INITIAL 0.1f //init quaternion (NED-to-body) uncertainty #define INS_EKF_PP_INITIAL 100.0f //init North-East-Alt position uncertainties, m #define INS_EKF_PV_INITIAL 10.0f //init NED velocity uncertainties, m/s #define INS_EKF_PW_INITIAL 0.01f //init XYZ gyro bias uncertainties, rad/s #define INS_EKF_PA_INITIAL 0.1f //init XYZ accel bias uncertainties, m/s^2 #define INS_EKF_QQ_INITIAL 0.001f //quaternion process noise #define INS_EKF_QP_INITIAL 0.0f //position process noise, m #define INS_EKF_QV_INITIAL 2.0f //velocity process noise, m/s #define INS_EKF_QW_INITIAL 0.000001f //gyro bias process noise, rad/s #define INS_EKF_QA_INITIAL 0.000001f //accel bias process noise, m/s^2 #define INS_EKF_RM_INITIAL 0.025f #define INS_EKF_RP_INITIAL 2.0f #define INS_EKF_RV_INITIAL 1.0f #define INS_EKF_GRAVITY 9.81f //local gravity m/s^2 //local magnetic declination #define INS_EKF_DECLINATION (47.888f / 180.0f * INS_EKF_PI) //47.888f DIP in shenzhen ////////////////////////////////////////////////////////////////////////// void INS_EKF_New(INS_EKF_Filter* ins) { float32_t *F = ins->F_f32; float32_t *H = ins->H_f32; float32_t *P = ins->P_f32; float32_t *Q = ins->Q_f32; float32_t *R = ins->R_f32; ////////////////////////////////////////////////////////////////////////// arm_mat_init_f32(&ins->P, INS_EKF_STATE_DIM, INS_EKF_STATE_DIM, ins->P_f32); arm_mat_zero_f32(&ins->P); //quaternion P[0] = P[17] = P[34] = P[51] = INS_EKF_PQ_INITIAL; //position P[68] = P[85] = P[102] = INS_EKF_PP_INITIAL; //velocity P[119] = P[136] = P[153] = INS_EKF_PV_INITIAL; //gyro bias P[170] = P[187] = P[204] = INS_EKF_PW_INITIAL; //accel bias P[221] = P[238] = P[255] = INS_EKF_PA_INITIAL; arm_mat_init_f32(&ins->PX, INS_EKF_STATE_DIM, INS_EKF_STATE_DIM, ins->PX_f32); arm_mat_init_f32(&ins->PHT, INS_EKF_STATE_DIM, INS_EKF_MEASUREMENT_DIM, ins->PHT_f32); arm_mat_init_f32(&ins->Q, INS_EKF_STATE_DIM, INS_EKF_STATE_DIM, ins->Q_f32); arm_mat_zero_f32(&ins->Q); //quaternion Q[0] = Q[17] = Q[34] = Q[51] = INS_EKF_QQ_INITIAL; //position Q[68] = Q[85] = Q[102] = INS_EKF_QP_INITIAL; //velocity Q[119] = Q[136] = Q[153] = INS_EKF_QV_INITIAL; //gyro bias Q[170] = Q[187] = Q[204] = INS_EKF_QW_INITIAL; //accel bias Q[221] = Q[238] = Q[255] = INS_EKF_QA_INITIAL; arm_mat_init_f32(&ins->R, INS_EKF_MEASUREMENT_DIM, INS_EKF_MEASUREMENT_DIM, ins->R_f32); arm_mat_zero_f32(&ins->R); R[0] = R[10] = R[20] = INS_EKF_RM_INITIAL; R[30] = R[40] = R[50] = INS_EKF_RP_INITIAL; R[60] = R[70] = R[80] = INS_EKF_RV_INITIAL; ////////////////////////////////////////////////////////////////////////// arm_mat_init_f32(&ins->K, INS_EKF_STATE_DIM, INS_EKF_MEASUREMENT_DIM, ins->K_f32); arm_mat_init_f32(&ins->KH, INS_EKF_STATE_DIM, INS_EKF_STATE_DIM, ins->KH_f32); arm_mat_init_f32(&ins->KHP, INS_EKF_STATE_DIM, INS_EKF_STATE_DIM, ins->KHP_f32); arm_mat_init_f32(&ins->KY, INS_EKF_STATE_DIM, 1, ins->KY_f32); arm_mat_init_f32(&ins->F, INS_EKF_STATE_DIM, INS_EKF_STATE_DIM, ins->F_f32); arm_mat_zero_f32(&ins->F); arm_mat_identity_f32(&ins->F, 1.0f); F[71] = 1.0f; F[88] = 1.0f; F[105] = -1.0f; // arm_mat_init_f32(&ins->FT, INS_EKF_STATE_DIM, INS_EKF_STATE_DIM, ins->FT_f32); // arm_mat_init_f32(&ins->H, INS_EKF_MEASUREMENT_DIM, INS_EKF_STATE_DIM, H); arm_mat_zero_f32(&ins->H); H[52] = 1.0f; H[69] = 1.0f; H[86] = 1.0f; H[103] = 1.0f; H[120] = 1.0f; H[137] = 1.0f; arm_mat_init_f32(&ins->HT, INS_EKF_STATE_DIM, INS_EKF_MEASUREMENT_DIM, ins->HT_f32); arm_mat_init_f32(&ins->HP, INS_EKF_MEASUREMENT_DIM, INS_EKF_STATE_DIM, ins->HP_f32); ////////////////////////////////////////////////////////////////////////// arm_mat_init_f32(&ins->S, INS_EKF_MEASUREMENT_DIM, INS_EKF_MEASUREMENT_DIM, ins->S_f32); arm_mat_init_f32(&ins->SI, INS_EKF_MEASUREMENT_DIM, INS_EKF_MEASUREMENT_DIM, ins->SI_f32); arm_mat_init_f32(&ins->X, INS_EKF_STATE_DIM, 1, ins->X_f32); arm_mat_zero_f32(&ins->X); ////////////////////////////////////////////////////////////////////////// arm_mat_init_f32(&ins->Y, INS_EKF_MEASUREMENT_DIM, 1, ins->Y_f32); arm_mat_zero_f32(&ins->Y); ////////////////////////////////////////////////////////////////////////// // } void INS_EKF_Init(INS_EKF_Filter* ins, float32_t *p, float32_t *v, float32_t *accel, float32_t *mag) { float32_t *X = ins->X_f32; // local variables float32_t norma, normm, normx, normy; float32_t declination; //3x3 rotation matrix float32_t R[9]; // place the un-normalized gravity and geomagnetic vectors into // the rotation matrix z and x axes R[2] = accel[0]; R[5] = accel[1]; R[8] = accel[2]; R[0] = mag[0]; R[3] = mag[1]; R[6] = mag[2]; // set y vector to vector product of z and x vectors R[1] = R[5] * R[6] - R[8] * R[3]; R[4] = R[8] * R[0] - R[2] * R[6]; R[7] = R[2] * R[3] - R[5] * R[0]; // set x vector to vector product of y and z vectors R[0] = R[4] * R[8] - R[7] * R[5]; R[3] = R[7] * R[2] - R[1] * R[8]; R[6] = R[1] * R[5] - R[4] * R[2]; // calculate the vector moduli invert norma = FastSqrtI(accel[0] * accel[0] + accel[1] * accel[1] + accel[2] * accel[2]); normm = FastSqrtI(mag[0] * mag[0] + mag[1] * mag[1] + mag[2] * mag[2]); normx = FastSqrtI(R[0] * R[0] + R[3] * R[3] + R[6] * R[6]); normy = FastSqrtI(R[1] * R[1] + R[4] * R[4] + R[7] * R[7]); // normalize the rotation matrix // normalize x axis R[0] *= normx; R[3] *= normx; R[6] *= normx; // normalize y axis R[1] *= normy; R[4] *= normy; R[7] *= normy; // normalize z axis R[2] *= norma; R[5] *= norma; R[8] *= norma; ////////////////////////////////////////////////////////////////////////// //estimate the declination declination = (accel[0] * mag[0] + accel[1] * mag[1] + accel[2] * mag[2]) * norma * normm; ins->declination = FastAsin(declination); //ins->declination = INS_EKF_DECLINATION; ins->gravity = INS_EKF_GRAVITY; Quaternion_FromRotationMatrix(R, X); X[4] = p[0]; X[5] = p[1]; X[6] = p[2]; X[7] = v[0]; X[8] = v[1]; X[9] = v[2]; } ////////////////////////////////////////////////////////////////////////// //additional input for calculate F and H with gyroscope, accelerometer and delta time void INS_EFK_Update(INS_EKF_Filter* ins, float32_t *mag, float32_t *p, float32_t *v, float32_t *gyro, float32_t *accel, float32_t dt) { float32_t *F = ins->F_f32; float32_t *H = ins->H_f32; float32_t *X = ins->X_f32; float32_t *Y = ins->Y_f32; ////////////////////////////////////////////////////////////////////////// float32_t q0, q1, q2, q3; //w x y z //float32_t halfq0,halfq1,halfq2,halfq3; float32_t halfdtq0,halfdtq1,halfdtq2,halfdtq3; float32_t /*q0q0,*/ q0q1, q0q2, q0q3, q1q1, q1q2, q1q3, q2q2, q2q3, q3q3; float32_t _2q0, _2q1, _2q2, _2q3; float32_t /*_4q0,*/ _4q1, _4q2, _4q3; float32_t halfgx, halfgy, halfgz; //float32_t halfdgx, halfdgy, halfdgz; float32_t dax, day, daz; float32_t ax, ay, az; float32_t dtdvx, dtdvy, dtdvz; float32_t halfdt = 0.5f * dt; ////////////////////////////////////////////////////////////////////////// float32_t Cbn[9];//Cnb[9]; float32_t sdeclination, cdeclination; //stuff float32_t norm; ////////////////////////////////////////////////////////////////////////// //halfdgx = 0.5f * (gyro[0] - X[10]); //halfdgy = 0.5f * (gyro[1] - X[11]); //halfdgz = 0.5f * (gyro[2] - X[12]); halfgx = halfdt * (gyro[0] - X[10]); halfgy = halfdt * (gyro[1] - X[11]); halfgz = halfdt * (gyro[2] - X[12]); // dax = accel[0] - X[13]; day = accel[1] - X[14]; daz = accel[2] - X[15]; // dtdvx = dax * dt; dtdvy = day * dt; dtdvz = daz * dt; ///////////////////////////////////////////////////////////////////////// q0 = X[0]; q1 = X[1]; q2 = X[2]; q3 = X[3]; //halfq0 = 0.5f * q0; halfq1 = 0.5f * q1; halfq2 = 0.5f * q2; halfq3 = 0.5f * q3; halfdtq0 = halfdt * q0; halfdtq1 = halfdt * q1; halfdtq2 = halfdt * q2; halfdtq3 = halfdt * q3; /*q0q0 = q0 * q0;*/ q0q1 = q0 * q1; q0q2 = q0 * q2; q0q3 = q0 * q3; q1q1 = q1 * q1; q1q2 = q1 * q2; q1q3 = q1 * q3; q2q2 = q2 * q2; q2q3 = q2 * q3; q3q3 = q3 * q3; _2q0 = 2.0f * q0; _2q1 = 2.0f * q1; _2q2 = 2.0f * q2; _2q3 = 2.0f * q3; /*_4q0 = 4.0f * q0;*/ _4q1 = 4.0f * q1; _4q2 = 4.0f * q2; _4q3 = 4.0f * q3; ////////////////////////////////////////////////////////////////////////// //accel b frame to reference frame Cbn[0] = 1.0f - 2.0f *(q2q2 + q3q3); Cbn[1] = 2.0f *(q1q2 - q0q3); Cbn[2] = 2.0f * (q1q3 + q0q2); Cbn[3] = 2.0f * (q1q2 + q0q3); Cbn[4] = 1.0f - 2.0f * (q1q1 + q3q3); Cbn[5] = 2.0f * (q2q3 - q0q1); Cbn[6] = 2.0f * (q1q3 - q0q2); Cbn[7] = 2.0f *(q2q3 + q0q1); Cbn[8] = 1.0f - 2.0f * (q1q1 + q2q2); ax = Cbn[0] * dax + Cbn[1] * day + Cbn[2] * daz; ay = Cbn[3] * dax + Cbn[4] * day + Cbn[5] * daz; az = Cbn[6] * dax + Cbn[7] * day + Cbn[8] * daz; az = az + ins->gravity; ////////////////////////////////////////////////////////////////////////// //X = X + dX * dt; //quaternion X[0] = q0 - halfgx * q1 - halfgy * q2 - halfgz * q3; X[1] = q1 + halfgx * q0 - halfgy * q3 + halfgz * q2; X[2] = q2 + halfgx * q3 + halfgy * q0 - halfgz * q1; X[3] = q3 - halfgx * q2 + halfgy * q1 + halfgz * q0; //North-East-Alt position X[4] = X[4] + X[7] * dt; X[5] = X[5] + X[8] * dt; X[6] = X[6] - X[9] * dt; //NED velocity X[7] = X[7] + ax * dt; X[8] = X[8] + ay * dt; X[9] = X[9] + az * dt; ////////////////////////////////////////////////////////////////////////// //calculate linearized state dynamics, f = d(xdot)/dx /* F[0] = 0.0f; F[1] = -halfdgx; F[2] = -halfdgy; F[3] = -halfdgz; F[4] = 0; F[5] = 0; F[6] = 0; F[7] = 0; F[8] = 0; F[9] = 0; F[10] = halfq1; F[11] = halfq2; F[12] = halfq3; F[13] = 0; F[14] = 0; F[15] = 0; F[16] = halfdgx; F[17] = 0; F[18] = halfdgz; F[19] = -halfdgy; F[20] = 0; F[21] = 0; F[22] = 0; F[23] = 0; F[24] = 0; F[25] = 0; F[26] = -halfq0; F[27] = halfq3; F[28] = -halfq2; F[29] = 0; F[30] = 0; F[31] = 0; F[32] = halfdgy; F[33] = -halfdgz; F[34] = 0; F[35] = halfdgx; F[36] = 0; F[37] = 0; F[38] = 0; F[39] = 0; F[40] = 0; F[41] = 0; F[42] = -halfq3; F[43] = -halfq0; F[44] = halfq1; F[45] = 0; F[46] = 0; F[47] = 0; F[48] = halfdgz; F[49] = halfdgy; F[50] = -halfdgx; F[51] = 0; F[52] = 0; F[53] = 0; F[54] = 0; F[55] = 0; F[56] = 0; F[57] = 0; F[58] = halfq2; F[59] = -halfq1; F[60] = -halfq0; F[61] = 0; F[62] = 0; F[63] = 0; F[64] = 0; F[65] = 0; F[66] = 0; F[67] = 0; F[68] = 0; F[69] = 0; F[70] = 0; F[71] = 1.0f; F[72] = 0; F[73] = 0; F[74] = 0; F[75] = 0; F[76] = 0; F[77] = 0; F[78] = 0; F[79] = 0; F[80] = 0; F[81] = 0; F[82] = 0; F[83] = 0; F[84] = 0; F[85] = 0; F[86] = 0; F[87] = 0; F[88] = 1.0f; F[89] = 0; F[90] = 0; F[91] = 0; F[92] = 0; F[93] = 0; F[94] = 0; F[95] = 0; F[96] = 0; F[97] = 0; F[98] = 0; F[99] = 0; F[100] = 0; F[101] = 0; F[102] = 0; F[103] = 0; F[104] = 0; F[105] = -1.0f; F[106] = 0; F[107] = 0; F[108] = 0; F[109] = 0; F[110] = 0; F[111] = 0; F[112] = -_2q3 * day + _2q2 * daz; F[113] = _2q2 * day + _2q3 * daz; F[114] = -_4q2 * dax + _2q1 * day + _2q0 * daz; F[115] = -_2q0 * day - _4q3 * dax + _2q1 * daz; F[116] = 0; F[117] = 0; F[118] = 0; F[119] = 0; F[120] = 0; F[121] = 0; F[122] = 0; F[123] = 0; F[124] = 0; F[125] = -Cbn[0]; F[126] = -Cbn[1]; F[127] = -Cbn[2]; F[128] = -_2q1 * daz + _2q3 * dax; F[129] = -_4q1 * day + _2q2 * dax - _2q0 * daz; F[130] = _2q1 * dax + _2q3 * daz; F[131] = -_4q3 * day + _2q0 * dax + _2q2 * daz; F[132] = 0; F[133] = 0; F[134] = 0; F[135] = 0; F[136] = 0; F[137] = 0; F[138] = 0; F[139] = 0; F[140] = 0; F[141] = -Cbn[3]; F[142] = -Cbn[4]; F[143] = -Cbn[5]; F[144] = -_2q2 * dax + _2q1 * day; F[145] = -_4q1 * daz + _2q3 * dax + _2q0 * day; F[146] = -_2q0 * dax + _2q3 * day - _4q2 * daz; F[147] = _2q1 * dax + _2q2 * day; F[148] = 0; F[149] = 0; F[150] = 0; F[151] = 0; F[152] = 0; F[153] = 0; F[154] = 0; F[155] = 0; F[156] = 0; F[157] = -Cbn[6]; F[158] = -Cbn[7]; F[159] = -Cbn[8]; F[160] = 0; F[161] = 0; F[162] = 0; F[163] = 0; F[164] = 0; F[165] = 0; F[166] = 0; F[167] = 0; F[168] = 0; F[169] = 0; F[170] = 0; F[171] = 0; F[172] = 0; F[173] = 0; F[174] = 0; F[175] = 0; F[176] = 0; F[177] = 0; F[178] = 0; F[179] = 0; F[180] = 0; F[181] = 0; F[182] = 0; F[183] = 0; F[184] = 0; F[185] = 0; F[186] = 0; F[187] = 0; F[188] = 0; F[189] = 0; F[190] = 0; F[191] = 0; F[192] = 0; F[193] = 0; F[194] = 0; F[195] = 0; F[196] = 0; F[197] = 0; F[198] = 0; F[199] = 0; F[200] = 0; F[201] = 0; F[202] = 0; F[203] = 0; F[204] = 0; F[205] = 0; F[206] = 0; F[207] = 0; F[208] = 0; F[209] = 0; F[210] = 0; F[211] = 0; F[212] = 0; F[213] = 0; F[214] = 0; F[215] = 0; F[216] = 0; F[217] = 0; F[218] = 0; F[219] = 0; F[220] = 0; F[221] = 0; F[222] = 0; F[223] = 0; F[224] = 0; F[225] = 0; F[226] = 0; F[227] = 0; F[228] = 0; F[229] = 0; F[230] = 0; F[231] = 0; F[232] = 0; F[233] = 0; F[234] = 0; F[235] = 0; F[236] = 0; F[237] = 0; F[238] = 0; F[239] = 0; F[240] = 0; F[241] = 0; F[242] = 0; F[243] = 0; F[244] = 0; F[245] = 0; F[246] = 0; F[247] = 0; F[248] = 0; F[249] = 0; F[250] = 0; F[251] = 0; F[252] = 0; F[253] = 0; F[254] = 0; F[255] = 0; */ ////////////////////////////////////////////////////////////////////////// //convert from linearized continuous-domain state model (F,Q(t)), into discrete-domain state transformation (FT[k] & Q[k]) //simple take two items from taylor series or you can try another way //FT[k] = (I + F'* dt)' = I' + (F' * dt)' = I + F * dt; //F[0] = F[17] = F[34] = F[51] = F[68] = F[85] = F[102] = F[119] = F[136] = F[153] = F[170] = F[187] = F[204] = F[221] = F[238] = F[255] = 1.0f; F[1] = -halfgx; F[2] = -halfgy; F[3] = -halfgz;F[10] = halfdtq1; F[11] = halfdtq2; F[12] = halfdtq3; F[16] = halfgx; F[18] = halfgz; F[19] = -halfgy; F[26] = -halfdtq0; F[27] = halfdtq3; F[28] = -halfdtq2; F[32] = halfgy; F[33] = -halfgz; F[35] = halfgx; F[42] = -halfdtq3; F[43] = -halfdtq0; F[44] = halfdtq1; F[48] = halfgz; F[49] = halfgy; F[50] = -halfgx; F[58] = halfdtq2; F[59] = -halfdtq1; F[60] = -halfdtq0; F[112] = -_2q3 * dtdvy + _2q2 * dtdvz; F[113] = _2q2 * dtdvy + _2q3 * dtdvz; F[114] = -_4q2 * dtdvx + _2q1 * dtdvy + _2q0 * dtdvz; F[115] = -_2q0 * dtdvy - _4q3 * dtdvx + _2q1 * dtdvz; F[125] = -Cbn[0] * dt; F[126] = -Cbn[1] * dt; F[127] = -Cbn[2] * dt; F[128] = -_2q1 * dtdvz + _2q3 * dtdvx; F[129] = -_4q1 * dtdvy + _2q2 * dtdvx - _2q0 * dtdvz; F[130] = _2q1 * dtdvx + _2q3 * dtdvz; F[131] = -_4q3 * dtdvy + _2q0 * dtdvx + _2q2 * dtdvz; F[141] = -Cbn[3] * dt; F[142] = -Cbn[4] * dt; F[143] = -Cbn[5] * dt; F[144] = -_2q2 * dtdvx + _2q1 * dtdvy; F[145] = -_4q1 * dtdvz + _2q3 * dtdvx + _2q0 * dtdvy; F[146] = -_2q0 * dtdvx + _2q3 * dtdvy - _4q2 * dtdvz; F[147] = _2q1 * dtdvx + _2q2 * dtdvy; F[157] = -Cbn[6] * dt; F[158] = -Cbn[7] * dt; F[159] = -Cbn[8] * dt; // //Q[k] = FT[k] * inv(FT[k]) * Q(t) ////////////////////////////////////////////////////////////////////////// //P = F * P * F' + Q[k] arm_mat_trans_f32(&ins->F, &ins->FT); arm_mat_mult_f32(&ins->F, &ins->P, &ins->PX); arm_mat_mult_f32(&ins->PX, &ins->FT, &ins->P); arm_mat_add_f32(&ins->P, &ins->Q, &ins->P); ////////////////////////////////////////////////////////////////////////// q0 = X[0]; q1 = X[1]; q2 = X[2]; q3 = X[3]; _2q0 = 2.0f * q0; _2q1 = 2.0f * q1; _2q2 = 2.0f * q2; _2q3 = 2.0f * q3; /*_4q0 = 4.0f * q0;*/ _4q1 = 4.0f * q1; _4q2 = 4.0f * q2; _4q3 = 4.0f * q3; ////////////////////////////////////////////////////////////////////////// //magnetic declination FastSinCos(ins->declination, &sdeclination, &cdeclination); ////////////////////////////////////////////////////////////////////////// //Cnb[0] = 1.0f - 2.0f *(q2 * q2 + q3 * q3); Cnb[1] = 2.0f * (q1 * q2 + q3 * q0); Cnb[2] = 2.0f * (q1 * q3 - q2 * q0); //Cnb[3] = 2.0f * (q1 * q2 - q3 * q0); Cnb[4] = 1.0f - 2.0f *(q1 * q1 + q3 * q3); Cnb[5] = 2.0f * (q2 * q3 + q1 * q0); //Cnb[6] = 2.0f * (q1 * q3 + q2 * q0); Cnb[7] = 2.0f * (q2 * q3 - q1 * q0); Cnb[8] = 1.0f - 2.0f * (q1 * q1 + q2 * q2); //Cmn[0] = cdeclination; Cmn[1] = -sdeclination; Cmn[2] = 0; //Cmn[3] = sdeclination; Cmn[4] = cdeclination; Cmn[5] = 0; //Cmn[6] = 0; Cmn[7] = 0; Cmn[8] = 1.0f; //mn[3] = {1.0, 0, 0}; 3D mag ned unit calculate by Cnb * Cmn * mn; (in body) Y[0] = (1.0f - 2.0f *(q2 * q2 + q3 * q3)) * cdeclination + 2.0f * (q1 * q2 + q3 * q0) * sdeclination; Y[1] = 2.0f * (q1 * q2 - q3 * q0) * cdeclination + (1.0f - 2.0f *(q1 * q1 + q3 * q3)) * sdeclination; Y[2] = 2.0f * (q1 * q3 + q2 * q0) * cdeclination + 2.0f * (q2 * q3 - q1 * q0) * sdeclination; //postion Y[3] = X[4]; Y[4] = X[5]; Y[5] = X[6]; //velocity Y[6] = X[7]; Y[7] = X[8]; Y[8] = X[9]; H[0] = _2q3 * sdeclination; H[1] = _2q2 * sdeclination; H[2] = _2q1 * sdeclination - _4q2 * cdeclination; H[3] = _2q0 * sdeclination - _4q3 * cdeclination; /*H[4] = 0; H[5] = 0; H[6] = 0; H[7] = 0; H[8] = 0; H[9] = 0; H[10] = 0; H[11] = 0; H[12] = 0; H[13] = 0; H[14] = 0; H[15] = 0;*/ H[16] = -_2q3 * cdeclination; H[17] = _2q2 * cdeclination - _4q1 * sdeclination; H[18] = _2q1 * cdeclination; H[19] = - _2q0 * cdeclination - _4q3* sdeclination; /*H[20] = 0; H[21] = 0; H[22] = 0; H[23] = 0; H[24] = 0; H[25] = 0; H[26] = 0; H[27] = 0; H[28] = 0; H[29] = 0; H[30] = 0; H[31] = 0;*/ H[32] = _2q2 * cdeclination - _2q1 * sdeclination; H[33] = _2q3 * cdeclination - _2q0 * sdeclination; H[34] = _2q0 * cdeclination + _2q3 * sdeclination; H[35] = _2q1 * cdeclination + _2q2 * sdeclination; /*H[36] = 0; H[37] = 0; H[38] = 0; H[39] = 0; H[40] = 0; H[41] = 0; H[42] = 0; H[43] = 0; H[44] = 0; H[45] = 0; H[46] = 0; H[47] = 0;*/ /*H[48] = 0; H[49] = 0; H[50] = 0; H[51] = 0; H[52] = 1.0f; H[53] = 0; H[54] = 0; H[55] = 0; H[56] = 0; H[57] = 0; H[58] = 0; H[59] = 0; H[60] = 0; H[61] = 0; H[62] = 0; H[63] = 0;*/ /*H[64] = 0; H[65] = 0; H[66] = 0; H[67] = 0; H[68] = 0; H[69] = 1.0f; H[70] = 0; H[71] = 0; H[72] = 0; H[73] = 0; H[74] = 0; H[75] = 0; H[76] = 0; H[77] = 0; H[78] = 0; H[79] = 0;*/ /*H[80] = 0; H[81] = 0; H[82] = 0; H[83] = 0; H[84] = 0; H[85] = 0; H[86] = 1.0f; H[87] = 0; H[88] = 0; H[89] = 0; H[90] = 0; H[91] = 0; H[92] = 0; H[93] = 0; H[94] = 0; H[95] = 0;*/ /*H[96] = 0; H[97] = 0; H[98] = 0; H[99] = 0; H[100] = 0; H[101] = 0; H[102] = 0; H[103] = 1.0f; H[104] = 0; H[105] = 0; H[106] = 0; H[107] = 0; H[108] = 0; H[109] = 0; H[110] = 0; H[111] = 0;*/ /*H[112] = 0; H[113] = 0; H[114] = 0; H[115] = 0; H[116] = 0; H[117] = 0; H[118] = 0; H[119] = 0; H[120] = 1.0f; H[121] = 0; H[122] = 0; H[123] = 0; H[124] = 0; H[125] = 0; H[126] = 0; H[127] = 0;*/ /*H[128] = 0; H[129] = 0; H[130] = 0; H[131] = 0; H[132] = 0; H[133] = 0; H[134] = 0; H[135] = 0; H[136] = 0; H[137] = 1.0f; H[138] = 0; H[139] = 0; H[140] = 0; H[141] = 0; H[142] = 0; H[143] = 0;*/ ////////////////////////////////////////////////////////////////////////// //K = (P * H') / (H * P * H'+ R) //S = H * P * H' + R; arm_mat_trans_f32(&ins->H, &ins->HT); arm_mat_mult_f32(&ins->H, &ins->P, &ins->HP); arm_mat_mult_f32(&ins->HP, &ins->HT, &ins->S); arm_mat_add_f32(&ins->S, &ins->R, &ins->S); //calculate Kalman gain //K = P * H'/ S; arm_mat_inverse_f32(&ins->S, &ins->SI); arm_mat_mult_f32(&ins->P, &ins->HT, &ins->PHT); arm_mat_mult_f32(&ins->PHT, &ins->SI, &ins->K); ////////////////////////////////////////////////////////////////////////// // norm = FastSqrtI(mag[0] * mag[0] + mag[1] * mag[1] + mag[2] * mag[2]); mag[0] *= norm; mag[1] *= norm; mag[2] *= norm; //unit vector pointing to magnetic North in body coords Y[0] = mag[0] - Y[0]; Y[1] = mag[1] - Y[1]; Y[2] = mag[2] - Y[2]; //north pos, east pos, altitude Y[3] = p[0] - Y[3]; Y[4] = p[1] - Y[4]; Y[5] = p[2] - Y[5]; //north vel, east vel, down velocity Y[6] = v[0] - Y[6]; Y[7] = v[1] - Y[7]; Y[8] = v[2] - Y[8]; //X = X + K * y arm_mat_mult_f32(&ins->K, &ins->Y, &ins->KY); arm_mat_add_f32(&ins->X, &ins->KY, &ins->X); ////////////////////////////////////////////////////////////////////////// //P = (I - K * H) * P //P = P - K * H * P arm_mat_mult_f32(&ins->K, &ins->H, &ins->KH); arm_mat_mult_f32(&ins->KH, &ins->P, &ins->KHP); arm_mat_sub_f32(&ins->P, &ins->KHP, &ins->P); ////////////////////////////////////////////////////////////////////////// //normalize quaternion norm = FastSqrtI(X[0] * X[0] + X[1] * X[1] + X[2] * X[2] + X[3] * X[3]); X[0] *= norm; X[1] *= norm; X[2] *= norm; X[3] *= norm; } void INS_EKF_GetAngle(INS_EKF_Filter* ins, float32_t* rpy) { float32_t Cnb[9]; float32_t *X = ins->X_f32; //Cnb Cnb[0] = 2.0f * (X[0] * X[0] + X[1] * X[1]) - 1.0f; Cnb[1] = 2.0f * (X[1] * X[2] + X[0] * X[3]); Cnb[2] = 2.0f * (X[1] * X[3] - X[0] * X[2]); //Cnb[3] = 2.0f * (X[1] * X[2] - X[0] * X[3]); //Cnb[4] = 2.0f * (X[0] * X[0] + X[2] * X[2]) - 1.0f; Cnb[5] = 2.0f * (X[2] * X[3] + X[0] * X[1]); //Cnb[6] = 2.0f * (X[1] * X[3] + X[0] * X[2]); //Cnb[7] = 2.0f * (X[2] * X[3] - X[0] * X[1]); Cnb[8] = 2.0f * (X[0] * X[0] + X[3] * X[3]) - 1.0f; //roll rpy[0] = FastAtan2(Cnb[5], Cnb[8]); if (rpy[0] == INS_EKF_PI) rpy[0] = -INS_EKF_PI; //pitch if (Cnb[2] >= 1.0f) rpy[1] = -INS_EKF_HALFPI; else if (Cnb[2] <= -1.0f) rpy[1] = INS_EKF_HALFPI; else rpy[1] = FastAsin(-Cnb[2]); //yaw rpy[2] = FastAtan2(Cnb[1], Cnb[0]); if (rpy[2] < 0.0f){ rpy[2] += INS_EKF_TWOPI; } if (rpy[2] > INS_EKF_TWOPI){ rpy[2] = 0.0f; } rpy[0] = INS_EKF_TODEG(rpy[0]); rpy[1] = INS_EKF_TODEG(rpy[1]); rpy[2] = INS_EKF_TODEG(rpy[2]); } ================================================ FILE: Algorithm/src/PID.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "PID.h" ================================================ FILE: Algorithm/src/Quaternion.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "Quaternion.h" #include "FastMath.h" void Quaternion_Normalize(float *q) { float norm = FastSqrtI(q[0] * q[0] + q[1] * q[1] + q[2] * q[2] + q[3] * q[3]); q[0] *= norm; q[1] *= norm; q[2] *= norm; q[3] *= norm; } void Quaternion_FromEuler(float *q, float *rpy) { float sPhi2, cPhi2; // sin(phi/2) and cos(phi/2) float sThe2, cThe2; // sin(theta/2) and cos(theta/2) float sPsi2, cPsi2; // sin(psi/2) and cos(psi/2) // calculate sines and cosines FastSinCos(0.5f * rpy[0], &sPhi2, &cPhi2); FastSinCos(0.5f * rpy[1], &sThe2, &cThe2); FastSinCos(0.5f * rpy[2], &sPsi2, &cPsi2); // compute the quaternion elements q[0] = cPsi2 * cThe2 * cPhi2 + sPsi2 * sThe2 * sPhi2; q[1] = cPsi2 * cThe2 * sPhi2 - sPsi2 * sThe2 * cPhi2; q[2] = cPsi2 * sThe2 * cPhi2 + sPsi2 * cThe2 * sPhi2; q[3] = sPsi2 * cThe2 * cPhi2 - cPsi2 * sThe2 * sPhi2; } void Quaternion_ToEuler(float *q, float* rpy) { float R[3][3]; //Z-Y-X R[0][0] = 2.0f * (q[0] * q[0] + q[1] * q[1]) - 1.0f; R[0][1] = 2.0f * (q[1] * q[2] + q[0] * q[3]); R[0][2] = 2.0f * (q[1] * q[3] - q[0] * q[2]); //R[1][0] = 2.0f * (q[1] * q[2] - q[0] * q[3]); //R[1][1] = 2.0f * (q[0] * q[0] + q[2] * q[2]) - 1.0f; R[1][2] = 2.0f * (q[2] * q[3] + q[0] * q[1]); //R[2][0] = 2.0f * (q[1] * q[3] + q[0] * q[2]); //R[2][1] = 2.0f * (q[2] * q[3] - q[0] * q[1]); R[2][2] = 2.0f * (q[0] * q[0] + q[3] * q[3]) - 1.0f; //roll rpy[0] = FastAtan2(R[1][2], R[2][2]); if (rpy[0] == PI) rpy[0] = -PI_2; //pitch if (R[0][2] >= 1.0f) rpy[1] = -PI_2; else if (R[0][2] <= -1.0f) rpy[1] = PI_2; else rpy[1] = FastAsin(-R[0][2]); //yaw rpy[2] = FastAtan2(R[0][1], R[0][0]); if (rpy[2] < 0.0f){ rpy[2] += _2_PI; } if (rpy[2] > _2_PI){ rpy[2] = 0.0f; } //rpy[0] = RADTODEG(rpy[0]); //rpy[1] = RADTODEG(rpy[1]); //rpy[2] = RADTODEG(rpy[2]); } void Quaternion_FromRotationMatrix(float *R, float *Q) { #if 0 // calculate the trace of the matrix float trace = R[0] + R[4] + R[8]; float s; if(trace > 0){ s = 0.5f * FastSqrt(trace + 1.0f); Q[0] = 0.25f / s; Q[1] = (R[7] - R[5]) * s; Q[2] = (R[2] - R[6]) * s; Q[3] = (R[3] - R[1]) * s; } else{ if(R[0] > R[4] && R[0] > R[8] ){ s = 0.5f * FastSqrtI(1.0f + R[0] - R[4] - R[8]); Q[0] = (R[7] - R[5]) * s; Q[1] = 0.25f / s; Q[2] = (R[1] + R[3]) * s; Q[3] = (R[2] + R[6]) * s; } else if(R[4] > R[8]) { s = 0.5f * FastSqrtI(1.0f + R[4] - R[0] - R[8]); Q[0] = (R[2] - R[6]) * s; Q[1] = (R[1] + R[3]) * s; Q[2] = 0.25f / s; Q[3] = (R[5] + R[7]) * s; } else{ s = 0.5f * FastSqrtI(1.0f + R[8] - R[0] - R[4]); Q[0] = (R[3] - R[1]) * s; Q[1] = (R[2] + R[6]) * s; Q[2] = (R[5] + R[7]) * s; Q[3] = 0.25f / s; } } #else // get the instantaneous orientation quaternion float fq0sq; // q0^2 float recip4q0; // 1/4q0 float fmag; // quaternion magnitude #define SMALLQ0 0.01F // limit where rounding errors may appear // get q0^2 and q0 fq0sq = 0.25f * (1.0f + R[0] + R[4] + R[8]); Q[0] = (float)FastSqrt(FastAbs(fq0sq)); // normal case when q0 is not small meaning rotation angle not near 180 deg if (Q[0] > SMALLQ0){ // calculate q1 to q3 recip4q0 = 0.25F / Q[0]; Q[1] = recip4q0 * (R[5] - R[7]); Q[2] = recip4q0 * (R[6] - R[2]); Q[3] = recip4q0 * (R[1] - R[3]); } else{ // special case of near 180 deg corresponds to nearly symmetric matrix // which is not numerically well conditioned for division by small q0 // instead get absolute values of q1 to q3 from leading diagonal Q[1] = FastSqrt(FastAbs(0.5f * (1.0f + R[0]) - fq0sq)); Q[2] = FastSqrt(FastAbs(0.5f * (1.0f + R[4]) - fq0sq)); Q[3] = FastSqrt(FastAbs(0.5f * (1.0f + R[8]) - fq0sq)); // first assume q1 is positive and ensure q2 and q3 are consistent with q1 if ((R[1] + R[3]) < 0.0f){ // q1*q2 < 0 so q2 is negative Q[2] = -Q[2]; if ((R[5] + R[7]) > 0.0f){ // q1*q2 < 0 and q2*q3 > 0 so q3 is also both negative Q[3] = -Q[3]; } } else if ((R[1] + R[3]) > 0.0f){ if ((R[5] + R[7]) < 0.0f){ // q1*q2 > 0 and q2*q3 < 0 so q3 is negative Q[3] = -Q[3]; } } // negate the vector components if q1 should be negative if ((R[5] - R[7]) < 0.0f){ Q[1] = -Q[1]; Q[2] = -Q[2]; Q[3] = -Q[3]; } } // finally re-normalize fmag = FastSqrtI(Q[0] * Q[0] + Q[1] * Q[1] + Q[2] * Q[2] + Q[3] * Q[3]); Q[0] *= fmag; Q[1] *= fmag; Q[2] *= fmag; Q[3] *= fmag; #endif } void Quaternion_RungeKutta4(float *q, float *w, float dt, int normalize) { float half = 0.5f; float two = 2.0f; float qw[4], k2[4], k3[4], k4[4]; float tmpq[4], tmpk[4]; //qw = q * w * half; Quaternion_Multiply(qw, q, w); Quaternion_Scalar(qw, qw, half); //k2 = (q + qw * dt * half) * w * half; Quaternion_Scalar(tmpk, qw, dt * half); Quaternion_Add(tmpk, q, tmpk); Quaternion_Multiply(k2, tmpk, w); Quaternion_Scalar(k2, k2, half); //k3 = (q + k2 * dt * half) * w * half; Quaternion_Scalar(tmpk, k2, dt * half); Quaternion_Add(tmpk, q, tmpk); Quaternion_Multiply(k3, tmpk, w); Quaternion_Scalar(k3, k3, half); //k4 = (q + k3 * dt) * w * half; Quaternion_Scalar(tmpk, k3, dt); Quaternion_Add(tmpk, q, tmpk); Quaternion_Multiply(k4, tmpk, w); Quaternion_Scalar(k4, k4, half); //q += (qw + k2 * two + k3 * two + k4) * (dt / 6); Quaternion_Scalar(tmpk, k2, two); Quaternion_Add(tmpq, qw, tmpk); Quaternion_Scalar(tmpk, k3, two); Quaternion_Add(tmpq, tmpq, tmpk); Quaternion_Add(tmpq, tmpq, k4); Quaternion_Scalar(tmpq, tmpq, dt / 6.0f); Quaternion_Add(q, q, tmpq); if (normalize){ Quaternion_Normalize(q); } } void Quaternion_From6AxisData(float* q, float *accel, float *mag) { // local variables float norma, normx, normy; //float normm; //3x3 rotation matrix float R[9]; // place the un-normalized gravity and geomagnetic vectors into // the rotation matrix z and x axes R[2] = accel[0]; R[5] = accel[1]; R[8] = accel[2]; R[0] = mag[0]; R[3] = mag[1]; R[6] = mag[2]; // set y vector to vector product of z and x vectors R[1] = R[5] * R[6] - R[8] * R[3]; R[4] = R[8] * R[0] - R[2] * R[6]; R[7] = R[2] * R[3] - R[5] * R[0]; // set x vector to vector product of y and z vectors R[0] = R[4] * R[8] - R[7] * R[5]; R[3] = R[7] * R[2] - R[1] * R[8]; R[6] = R[1] * R[5] - R[4] * R[2]; // calculate the vector moduli invert norma = FastSqrtI(accel[0] * accel[0] + accel[1] * accel[1] + accel[2] * accel[2]); //normm = FastSqrtI(mag[0] * mag[0] + mag[1] * mag[1] + mag[2] * mag[2]); normx = FastSqrtI(R[0] * R[0] + R[3] * R[3] + R[6] * R[6]); normy = FastSqrtI(R[1] * R[1] + R[4] * R[4] + R[7] * R[7]); // normalize the rotation matrix // normalize x axis R[0] *= normx; R[3] *= normx; R[6] *= normx; // normalize y axis R[1] *= normy; R[4] *= normy; R[7] *= normy; // normalize z axis R[2] *= norma; R[5] *= norma; R[8] *= norma; Quaternion_FromRotationMatrix(R, q); } ================================================ FILE: Algorithm/src/SRCKF.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "SRCKF.h" #include "FastMath.h" #include "Quaternion.h" ////////////////////////////////////////////////////////////////////////// //all parameters below need to be tune #define SRCKF_PQ_INITIAL 0.000001f #define SRCKF_PW_INITIAL 0.000001f #define SRCKF_QQ_INITIAL 0.0000045f #define SRCKF_QW_INITIAL 0.0000025f #define SRCKF_RA_INITIAL 0.07f #define SRCKF_RM_INITIAL 0.105f ////////////////////////////////////////////////////////////////////////// // void SRCKF_New(SRCKF_Filter* srckf) { float32_t kesi; arm_matrix_instance_f32 KesiPuls, KesiMinu; float32_t KesiPuls_f32[SRCKF_STATE_DIM * SRCKF_STATE_DIM], KesiMinus_f32[SRCKF_STATE_DIM * SRCKF_STATE_DIM]; float32_t *S = srckf->S_f32; float32_t *SQ = srckf->SQ_f32; float32_t *SR = srckf->SR_f32; ////////////////////////////////////////////////////////////////////////// //initialise weight srckf->W = 1.0f / (float32_t)SRCKF_CP_POINTS; arm_sqrt_f32(srckf->W, &srckf->SW); //initialise kesi //generate the cubature point kesi = (float32_t)SRCKF_STATE_DIM; arm_sqrt_f32(kesi, &kesi); arm_mat_init_f32(&KesiPuls, SRCKF_STATE_DIM, SRCKF_STATE_DIM, KesiPuls_f32); arm_mat_zero_f32(&KesiPuls); arm_mat_init_f32(&KesiMinu, SRCKF_STATE_DIM, SRCKF_STATE_DIM, KesiMinus_f32); arm_mat_zero_f32(&KesiMinu); arm_mat_identity_f32(&KesiPuls, kesi); arm_mat_identity_f32(&KesiMinu, -kesi); arm_mat_init_f32(&srckf->Kesi, SRCKF_STATE_DIM, SRCKF_CP_POINTS, srckf->Kesi_f32); arm_mat_setsubmatrix_f32(&srckf->Kesi, &KesiPuls, 0, 0); arm_mat_setsubmatrix_f32(&srckf->Kesi, &KesiMinu, 0, SRCKF_STATE_DIM); arm_mat_init_f32(&srckf->iKesi, SRCKF_STATE_DIM, 1, srckf->iKesi_f32); arm_mat_zero_f32(&srckf->iKesi); //initialise state covariance arm_mat_init_f32(&srckf->S, SRCKF_STATE_DIM, SRCKF_STATE_DIM, srckf->S_f32); arm_mat_zero_f32(&srckf->S); S[0] = S[8] = S[16] = S[24] = SRCKF_PQ_INITIAL; S[32] = S[40] = S[48] = SRCKF_PW_INITIAL; arm_mat_init_f32(&srckf->ST, SRCKF_STATE_DIM, SRCKF_STATE_DIM, srckf->ST_f32); //initialise measurement covariance arm_mat_init_f32(&srckf->SY, SRCKF_MEASUREMENT_DIM, SRCKF_MEASUREMENT_DIM, srckf->SY_f32); arm_mat_init_f32(&srckf->SYI, SRCKF_MEASUREMENT_DIM, SRCKF_MEASUREMENT_DIM, srckf->SYI_f32); arm_mat_init_f32(&srckf->SYT, SRCKF_MEASUREMENT_DIM, SRCKF_MEASUREMENT_DIM, srckf->SYT_f32); arm_mat_init_f32(&srckf->SYTI, SRCKF_MEASUREMENT_DIM, SRCKF_MEASUREMENT_DIM, srckf->SYTI_f32); arm_mat_init_f32(&srckf->PXY, SRCKF_STATE_DIM, SRCKF_MEASUREMENT_DIM, srckf->PXY_f32); arm_mat_init_f32(&srckf->tmpPXY, SRCKF_STATE_DIM, SRCKF_MEASUREMENT_DIM, srckf->tmpPXY_f32); //initialise SQ arm_mat_init_f32(&srckf->SQ, SRCKF_STATE_DIM, SRCKF_STATE_DIM, srckf->SQ_f32); arm_mat_zero_f32(&srckf->SQ); SQ[0] = SQ[8] = SQ[16] = SQ[24] = SRCKF_QQ_INITIAL; SQ[32] = SQ[40] = SQ[48] = SRCKF_QW_INITIAL; //initialise SR arm_mat_init_f32(&srckf->SR, SRCKF_MEASUREMENT_DIM, SRCKF_MEASUREMENT_DIM, srckf->SR_f32); arm_mat_zero_f32(&srckf->SR); SR[0] = SR[7] = SR[14] = SRCKF_RA_INITIAL; SR[21] = SR[28] = SR[35] = SRCKF_RM_INITIAL; //other stuff //cubature points arm_mat_init_f32(&srckf->XCP, SRCKF_STATE_DIM, SRCKF_CP_POINTS, srckf->XCP_f32); //propagated cubature points arm_mat_init_f32(&srckf->XPCP, SRCKF_STATE_DIM, SRCKF_CP_POINTS, srckf->XPCP_f32); arm_mat_init_f32(&srckf->YPCP, SRCKF_MEASUREMENT_DIM, SRCKF_CP_POINTS, srckf->YPCP_f32); arm_mat_init_f32(&srckf->XCPCM, SRCKF_STATE_DIM, SRCKF_CP_POINTS, srckf->XCPCM_f32); arm_mat_init_f32(&srckf->tmpXCPCM, SRCKF_STATE_DIM, SRCKF_CP_POINTS, srckf->tmpXCPCM_f32); arm_mat_init_f32(&srckf->YCPCM, SRCKF_MEASUREMENT_DIM, SRCKF_CP_POINTS, srckf->YCPCM_f32); arm_mat_init_f32(&srckf->YCPCMT, SRCKF_CP_POINTS, SRCKF_MEASUREMENT_DIM, srckf->YCPCMT_f32); arm_mat_init_f32(&srckf->XCM, SRCKF_STATE_DIM, SRCKF_CP_POINTS + SRCKF_STATE_DIM, srckf->XCM_f32); //initialise fill SQ arm_mat_setsubmatrix_f32(&srckf->XCM, &srckf->SQ, 0, SRCKF_CP_POINTS); arm_mat_init_f32(&srckf->YCM, SRCKF_MEASUREMENT_DIM, SRCKF_CP_POINTS + SRCKF_MEASUREMENT_DIM, srckf->YCM_f32); //initialise fill SR arm_mat_setsubmatrix_f32(&srckf->YCM, &srckf->SR, 0, SRCKF_CP_POINTS); arm_mat_init_f32(&srckf->XYCM, SRCKF_STATE_DIM, SRCKF_CP_POINTS + SRCKF_MEASUREMENT_DIM, srckf->XYCM_f32); //Kalman gain arm_mat_init_f32(&srckf->K, SRCKF_STATE_DIM, SRCKF_MEASUREMENT_DIM, srckf->K_f32); ////////////////////////////////////////////////////////////////////////// //state vector arm_mat_init_f32(&srckf->X, SRCKF_STATE_DIM, 1, srckf->X_f32); arm_mat_zero_f32(&srckf->X); arm_mat_init_f32(&srckf->tmpX, SRCKF_STATE_DIM, 1, srckf->tmpX_f32); arm_mat_zero_f32(&srckf->tmpX); //measurement vector arm_mat_init_f32(&srckf->Y, SRCKF_MEASUREMENT_DIM, 1, srckf->Y_f32); arm_mat_zero_f32(&srckf->Y); arm_mat_init_f32(&srckf->tmpY, SRCKF_MEASUREMENT_DIM, 1, srckf->tmpY_f32); arm_mat_zero_f32(&srckf->tmpY); } void SRCKF_Init(SRCKF_Filter* srckf, float32_t *accel, float32_t *mag) { float32_t *X = srckf->X_f32; // local variables float32_t norma, normx, normy; //3x3 rotation matrix float32_t R[9]; // place the un-normalized gravity and geomagnetic vectors into // the rotation matrix z and x axes R[2] = accel[0]; R[5] = accel[1]; R[8] = accel[2]; R[0] = mag[0]; R[3] = mag[1]; R[6] = mag[2]; // set y vector to vector product of z and x vectors R[1] = R[5] * R[6] - R[8] * R[3]; R[4] = R[8] * R[0] - R[2] * R[6]; R[7] = R[2] * R[3] - R[5] * R[0]; // set x vector to vector product of y and z vectors R[0] = R[4] * R[8] - R[7] * R[5]; R[3] = R[7] * R[2] - R[1] * R[8]; R[6] = R[1] * R[5] - R[4] * R[2]; // calculate the vector moduli invert norma = FastSqrtI(accel[0] * accel[0] + accel[1] * accel[1] + accel[2] * accel[2]); normx = FastSqrtI(R[0] * R[0] + R[3] * R[3] + R[6] * R[6]); normy = FastSqrtI(R[1] * R[1] + R[4] * R[4] + R[7] * R[7]); // normalize the rotation matrix // normalize x axis R[0] *= normx; R[3] *= normx; R[6] *= normx; // normalize y axis R[1] *= normy; R[4] *= normy; R[7] *= normy; // normalize z axis R[2] *= norma; R[5] *= norma; R[8] *= norma; Quaternion_FromRotationMatrix(R, X); } void SRCKF_Update(SRCKF_Filter* srckf, float32_t *gyro, float32_t *accel, float32_t *mag, float32_t dt) { ////////////////////////////////////////////////////////////////////////// float32_t q0q0, q0q1, q0q2, q0q3, q1q1, q1q2, q1q3, q2q2, q2q3, q3q3; // float32_t hx, hy, hz; float32_t bx, bz; float32_t _2mx, _2my, _2mz; // int col; float32_t dQ[4]; float32_t norm; float32_t *X = srckf->X_f32, *Y = srckf->Y_f32; float32_t *tmpX = srckf->tmpX_f32, *tmpY = srckf->tmpY_f32; float32_t *iKesi = srckf->iKesi_f32; dQ[0] = 0.0f; dQ[1] = (gyro[0] - X[4]); dQ[2] = (gyro[1] - X[5]); dQ[3] = (gyro[2] - X[6]); ////////////////////////////////////////////////////////////////////////// //time update for(col = 0; col < SRCKF_CP_POINTS; col++){ //evaluate the cubature points arm_mat_getcolumn_f32(&srckf->Kesi, iKesi, col); arm_mat_mult_f32(&srckf->S, &srckf->iKesi, &srckf->tmpX); arm_mat_add_f32(&srckf->tmpX, &srckf->X, &srckf->tmpX); arm_mat_setcolumn_f32(&srckf->XCP, tmpX, col); //evaluate the propagated cubature points Quaternion_RungeKutta4(tmpX, dQ, dt, 1); arm_mat_setcolumn_f32(&srckf->XPCP, tmpX, col); } //estimate the predicted state arm_mat_cumsum_f32(&srckf->XPCP, tmpX, X); arm_mat_scale_f32(&srckf->X, srckf->W, &srckf->X); //estimate the square-root factor of the predicted error covariance for(col = 0; col < SRCKF_CP_POINTS; col++){ arm_mat_getcolumn_f32(&srckf->XPCP, tmpX, col); arm_mat_sub_f32(&srckf->tmpX, &srckf->X, &srckf->tmpX); arm_mat_scale_f32(&srckf->tmpX, srckf->SW, &srckf->tmpX); arm_mat_setcolumn_f32(&srckf->XCM, tmpX, col); } //XCM[XPCP, SQ], SQ fill already arm_mat_qr_decompositionT_f32(&srckf->XCM, &srckf->ST); arm_mat_trans_f32(&srckf->ST, &srckf->S); ////////////////////////////////////////////////////////////////////////// //measurement update //normalize accel and magnetic norm = FastSqrtI(accel[0] * accel[0] + accel[1] * accel[1] + accel[2] * accel[2]); accel[0] *= norm; accel[1] *= norm; accel[2] *= norm; ////////////////////////////////////////////////////////////////////////// norm = FastSqrtI(mag[0] * mag[0] + mag[1] * mag[1] + mag[2] * mag[2]); mag[0] *= norm; mag[1] *= norm; mag[2] *= norm; _2mx = 2.0f * mag[0]; _2my = 2.0f * mag[1]; _2mz = 2.0f * mag[2]; for(col = 0; col < SRCKF_CP_POINTS; col++){ //evaluate the cubature points arm_mat_getcolumn_f32(&srckf->Kesi, iKesi, col); arm_mat_mult_f32(&srckf->S, &srckf->iKesi, &srckf->tmpX); arm_mat_add_f32(&srckf->tmpX, &srckf->X, &srckf->tmpX); arm_mat_setcolumn_f32(&srckf->XCP, tmpX, col); //evaluate the propagated cubature points //auxiliary variables to avoid repeated arithmetic q0q0 = tmpX[0] * tmpX[0]; q0q1 = tmpX[0] * tmpX[1]; q0q2 = tmpX[0] * tmpX[2]; q0q3 = tmpX[0] * tmpX[3]; q1q1 = tmpX[1] * tmpX[1]; q1q2 = tmpX[1] * tmpX[2]; q1q3 = tmpX[1] * tmpX[3]; q2q2 = tmpX[2] * tmpX[2]; q2q3 = tmpX[2] * tmpX[3]; q3q3 = tmpX[3] * tmpX[3]; //reference direction of earth's magnetic field hx = _2mx * (0.5f - q2q2 - q3q3) + _2my * (q1q2 - q0q3) + _2mz *(q1q3 + q0q2); hy = _2mx * (q1q2 + q0q3) + _2my * (0.5f - q1q1 - q3q3) + _2mz * (q2q3 - q0q1); hz = _2mx * (q1q3 - q0q2) + _2my * (q2q3 + q0q1) + _2mz *(0.5f - q1q1 - q2q2); arm_sqrt_f32(hx * hx + hy * hy, &bx); bz = hz; tmpY[0] = 2.0f * (q1q3 - q0q2); tmpY[1] = 2.0f * (q2q3 + q0q1); tmpY[2] = -1.0f + 2.0f * (q0q0 + q3q3); tmpY[3] = bx * (1.0f - 2.0f * (q2q2 + q3q3)) + bz * ( 2.0f * (q1q3 - q0q2)); tmpY[4] = bx * (2.0f * (q1q2 - q0q3)) + bz * (2.0f * (q2q3 + q0q1)); tmpY[5] = bx * (2.0f * (q1q3 + q0q2)) + bz * (1.0f - 2.0f * (q1q1 + q2q2)); arm_mat_setcolumn_f32(&srckf->YPCP, tmpY, col); } //estimate the predicted measurement arm_mat_cumsum_f32(&srckf->YPCP, tmpY, Y); arm_mat_scale_f32(&srckf->Y, srckf->W, &srckf->Y); //estimate the square-root of the innovation covariance matrix for(col = 0; col < SRCKF_CP_POINTS; col++){ arm_mat_getcolumn_f32(&srckf->YPCP, tmpY, col); arm_mat_sub_f32(&srckf->tmpY, &srckf->Y, &srckf->tmpY); arm_mat_scale_f32(&srckf->tmpY, srckf->SW, &srckf->tmpY); arm_mat_setcolumn_f32(&srckf->YCPCM, tmpY, col); arm_mat_setcolumn_f32(&srckf->YCM, tmpY, col); } //YCM[YPCP, SR], SR fill already arm_mat_qr_decompositionT_f32(&srckf->YCM, &srckf->SYT); //estimate the cross-covariance matrix for(col = 0; col < SRCKF_CP_POINTS; col++){ arm_mat_getcolumn_f32(&srckf->XCP, tmpX, col); arm_mat_sub_f32(&srckf->tmpX, &srckf->X, &srckf->tmpX); arm_mat_scale_f32(&srckf->tmpX, srckf->SW, &srckf->tmpX); arm_mat_setcolumn_f32(&srckf->XCPCM, tmpX, col); } arm_mat_trans_f32(&srckf->YCPCM, &srckf->YCPCMT); arm_mat_mult_f32(&srckf->XCPCM, &srckf->YCPCMT, &srckf->PXY); //estimate the kalman gain arm_mat_trans_f32(&srckf->SYT, &srckf->SY); arm_mat_inverse_f32(&srckf->SYT, &srckf->SYTI); arm_mat_inverse_f32(&srckf->SY, &srckf->SYI); arm_mat_mult_f32(&srckf->PXY, &srckf->SYTI, &srckf->tmpPXY); arm_mat_mult_f32(&srckf->tmpPXY, &srckf->SYI, &srckf->K); //estimate the updated state Y[0] = accel[0] - Y[0]; Y[1] = accel[1] - Y[1]; Y[2] = accel[2] - Y[2]; Y[3] = mag[0] - Y[3]; Y[4] = mag[1] - Y[4]; Y[5] = mag[2] - Y[5]; arm_mat_mult_f32(&srckf->K, &srckf->Y, &srckf->tmpX); arm_mat_add_f32(&srckf->X, &srckf->tmpX, &srckf->X); //normalize quaternion norm = FastSqrtI(X[0] * X[0] + X[1] * X[1] + X[2] * X[2] + X[3] * X[3]); X[0] *= norm; X[1] *= norm; X[2] *= norm; X[3] *= norm; //estimate the square-root factor of the corresponding error covariance arm_mat_mult_f32(&srckf->K, &srckf->YCPCM, &srckf->tmpXCPCM); arm_mat_sub_f32(&srckf->XCPCM, &srckf->tmpXCPCM, &srckf->XCPCM); arm_mat_setsubmatrix_f32(&srckf->XYCM, &srckf->XCPCM, 0, 0); arm_mat_mult_f32(&srckf->K, &srckf->SR, &srckf->tmpPXY); arm_mat_setsubmatrix_f32(&srckf->XYCM, &srckf->tmpPXY, 0, SRCKF_CP_POINTS); arm_mat_qr_decompositionT_f32(&srckf->XYCM, &srckf->ST); arm_mat_trans_f32(&srckf->ST, &srckf->S); } void SRCKF_GetAngle(SRCKF_Filter* srckf, float32_t* rpy) { float32_t R[3][3]; float32_t *X = srckf->X_f32; //Z-Y-X R[0][0] = 2.0f * (X[0] * X[0] + X[1] * X[1]) - 1.0f; R[0][1] = 2.0f * (X[1] * X[2] + X[0] * X[3]); R[0][2] = 2.0f * (X[1] * X[3] - X[0] * X[2]); //R[1][0] = 2.0f * (X[1] * X[2] - X[0] * X[3]); //R[1][1] = 2.0f * (X[0] * X[0] + X[2] * X[2]) - 1.0f; R[1][2] = 2.0f * (X[2] * X[3] + X[0] * X[1]); //R[2][0] = 2.0f * (X[1] * X[3] + X[0] * X[2]); //R[2][1] = 2.0f * (X[2] * X[3] - X[0] * X[1]); R[2][2] = 2.0f * (X[0] * X[0] + X[3] * X[3]) - 1.0f; //roll rpy[0] = FastAtan2(R[1][2], R[2][2]); if (rpy[0] == SRCKF_PI) rpy[0] = -SRCKF_PI; //pitch if (R[0][2] >= 1.0f) rpy[1] = -SRCKF_HALFPI; else if (R[0][2] <= -1.0f) rpy[1] = SRCKF_HALFPI; else rpy[1] = FastAsin(-R[0][2]); //yaw rpy[2] = FastAtan2(R[0][1], R[0][0]); if (rpy[2] < 0.0f){ rpy[2] += SRCKF_TWOPI; } if (rpy[2] > SRCKF_TWOPI){ rpy[2] = 0.0f; } rpy[0] = SRCKF_TODEG(rpy[0]); rpy[1] = SRCKF_TODEG(rpy[1]); rpy[2] = SRCKF_TODEG(rpy[2]); } ================================================ FILE: Algorithm/src/UKF.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "UKF.h" #include "FastMath.h" #include "Quaternion.h" #define USE_4TH_RUNGE_KUTTA ////////////////////////////////////////////////////////////////////////// //all parameters below need to be tune #define UKF_PQ_INITIAL 0.000001f #define UKF_PW_INITIAL 0.000001f #define UKF_QQ_INITIAL 0.0000045f #define UKF_QW_INITIAL 0.0000025f #define UKF_RQ_INITIAL 0.000001f #define UKF_RA_INITIAL 0.07f #define UKF_RW_INITIAL 0.0525f #define UKF_RM_INITIAL 0.105f #define UKF_alpha (1.0f) #define UKF_beta (2.0f) #define UKF_kappa (-1.0f) ////////////////////////////////////////////////////////////////////////// // static void UKF_GenerateSigmaPoints(UKF_Filter* ukf) { int cols = 0; //state float32_t *X = ukf->X_f32; float32_t *tmpX = ukf->tmpX_f32; //need to tune!!! //covariance //c*chol(P)' arm_mat_chol_f32(&ukf->P); arm_mat_scale_f32(&ukf->P, ukf->gamma, &ukf->P); ////////////////////////////////////////////////////////////////////////// //generate sigma points arm_mat_setcolumn_f32(&ukf->XSP, X, cols); for(cols = 1; cols <= UKF_STATE_DIM; cols++){ arm_mat_getcolumn_f32(&ukf->P, tmpX, cols - 1); arm_mat_add_f32(&ukf->X, &ukf->tmpX, &ukf->tmpX); arm_mat_setcolumn_f32(&ukf->XSP, tmpX, cols); } for(cols = UKF_STATE_DIM + 1; cols < UKF_SP_POINTS; cols++){ arm_mat_getcolumn_f32(&ukf->P, tmpX, cols - 8/*UKF_STATE_DIM + 1*/); arm_mat_sub_f32(&ukf->X, &ukf->tmpX, &ukf->tmpX); arm_mat_setcolumn_f32(&ukf->XSP, tmpX, cols); } } void UKF_New(UKF_Filter* ukf) { float32_t *P = ukf->P_f32; float32_t *Q = ukf->Q_f32; float32_t *R = ukf->R_f32; float32_t *Wc = ukf->Wc_f32; //scaling factor float32_t lambda = UKF_alpha * UKF_alpha *((float32_t)UKF_STATE_DIM + UKF_kappa) - (float32_t)UKF_STATE_DIM; float32_t gamma = (float32_t)UKF_STATE_DIM + lambda; //weights for means ukf->Wm0 = lambda / gamma; ukf->Wmi = 0.5f / gamma; //weights for covariance arm_mat_init_f32(&ukf->Wc, UKF_SP_POINTS, UKF_SP_POINTS, ukf->Wc_f32); arm_mat_identity_f32(&ukf->Wc, ukf->Wmi); Wc[0] = ukf->Wm0 + (1.0f - UKF_alpha * UKF_alpha + UKF_beta); //scaling factor need to tune! arm_sqrt_f32(gamma, &ukf->gamma); ////////////////////////////////////////////////////////////////////////// //initialise P arm_mat_init_f32(&ukf->P, UKF_STATE_DIM, UKF_STATE_DIM, ukf->P_f32); arm_mat_identity_f32(&ukf->P, 1.0f); P[0] = P[8] = P[16] = P[24] = UKF_PQ_INITIAL; P[32] = P[40] = P[48] = UKF_PW_INITIAL; arm_mat_init_f32(&ukf->PX, UKF_STATE_DIM, UKF_STATE_DIM, ukf->PX_f32); arm_mat_init_f32(&ukf->PY, UKF_MEASUREMENT_DIM, UKF_MEASUREMENT_DIM, ukf->PY_f32); arm_mat_init_f32(&ukf->tmpPY, UKF_MEASUREMENT_DIM, UKF_MEASUREMENT_DIM, ukf->tmpPY_f32); arm_mat_init_f32(&ukf->PXY, UKF_STATE_DIM, UKF_MEASUREMENT_DIM, ukf->PXY_f32); arm_mat_init_f32(&ukf->PXYT, UKF_MEASUREMENT_DIM, UKF_STATE_DIM, ukf->PXYT_f32); //initialise Q arm_mat_init_f32(&ukf->Q, UKF_STATE_DIM, UKF_STATE_DIM, ukf->Q_f32); Q[0] = Q[8] = Q[16] = Q[24] = UKF_QQ_INITIAL; Q[32] = Q[40] = Q[48] = UKF_QW_INITIAL; //initialise R arm_mat_init_f32(&ukf->R, UKF_MEASUREMENT_DIM, UKF_MEASUREMENT_DIM, ukf->R_f32); R[0] = R[14] = R[28] = R[42] = UKF_RQ_INITIAL; R[56] = R[70] = R[84] = UKF_RA_INITIAL; R[98] = R[112] = R[126] = UKF_RW_INITIAL; R[140] = R[154] = R[168] = UKF_RM_INITIAL; arm_mat_init_f32(&ukf->XSP, UKF_STATE_DIM, UKF_SP_POINTS, ukf->XSP_f32); arm_mat_init_f32(&ukf->tmpXSP, UKF_STATE_DIM, UKF_SP_POINTS, ukf->tmpXSP_f32); arm_mat_init_f32(&ukf->tmpXSPT, UKF_SP_POINTS, UKF_STATE_DIM, ukf->tmpXSPT_f32); arm_mat_init_f32(&ukf->tmpWcXSP, UKF_STATE_DIM, UKF_SP_POINTS, ukf->tmpWcXSP_f32); arm_mat_init_f32(&ukf->tmpWcYSP, UKF_MEASUREMENT_DIM, UKF_SP_POINTS, ukf->tmpWcYSP_f32); arm_mat_init_f32(&ukf->YSP, UKF_MEASUREMENT_DIM, UKF_SP_POINTS, ukf->YSP_f32); arm_mat_init_f32(&ukf->tmpYSP, UKF_MEASUREMENT_DIM, UKF_SP_POINTS, ukf->tmpYSP_f32); arm_mat_init_f32(&ukf->tmpYSPT, UKF_SP_POINTS, UKF_MEASUREMENT_DIM, ukf->tmpYSPT_f32); ////////////////////////////////////////////////////////////////////////// arm_mat_init_f32(&ukf->K, UKF_STATE_DIM, UKF_MEASUREMENT_DIM, ukf->K_f32); arm_mat_init_f32(&ukf->KT, UKF_MEASUREMENT_DIM, UKF_STATE_DIM, ukf->KT_f32); ////////////////////////////////////////////////////////////////////////// arm_mat_init_f32(&ukf->X, UKF_STATE_DIM, 1, ukf->X_f32); arm_mat_zero_f32(&ukf->X); arm_mat_init_f32(&ukf->tmpX, UKF_STATE_DIM, 1, ukf->tmpX_f32); arm_mat_zero_f32(&ukf->tmpX); ////////////////////////////////////////////////////////////////////////// arm_mat_init_f32(&ukf->Y, UKF_MEASUREMENT_DIM, 1, ukf->Y_f32); arm_mat_zero_f32(&ukf->Y); arm_mat_init_f32(&ukf->tmpY, UKF_MEASUREMENT_DIM, 1, ukf->tmpY_f32); arm_mat_zero_f32(&ukf->tmpY); ////////////////////////////////////////////////////////////////////////// } void UKF_Init(UKF_Filter* ukf, float32_t *q, float32_t *gyro) { float32_t *X = ukf->X_f32; float32_t norm; X[0] = q[0]; X[1] = q[1]; X[2] = q[2]; X[3] = q[3]; norm = FastSqrtI(X[0] * X[0] + X[1] * X[1] + X[2] * X[2] + X[3] * X[3]); X[0] *= norm; X[1] *= norm; X[2] *= norm; X[3] *= norm; X[4] = gyro[0]; X[5] = gyro[1]; X[6] = gyro[2]; } void UKF_Update(UKF_Filter* ukf, float32_t *q, float32_t *gyro, float32_t *accel, float32_t *mag, float32_t dt) { int col, row; float32_t norm; #ifndef USE_4TH_RUNGE_KUTTA float32_t halfdx, halfdy, halfdz; float32_t halfdt = 0.5f * dt; #endif ////////////////////////////////////////////////////////////////////////// float32_t q0q0, q0q1, q0q2, q0q3, q1q1, q1q2, q1q3, q2q2, q2q3, q3q3; // float32_t hx, hy, hz; float32_t bx, bz; float32_t _2mx, _2my, _2mz; // float32_t *X = ukf->X_f32, *Y = ukf->Y_f32; float32_t *tmpX = ukf->tmpX_f32, *tmpY = ukf->tmpY_f32; float32_t tmpQ[4]; ////////////////////////////////////////////////////////////////////////// //calculate sigma points UKF_GenerateSigmaPoints(ukf); //time update //unscented transformation of process arm_mat_getcolumn_f32(&ukf->XSP, tmpX, 0); #ifdef USE_4TH_RUNGE_KUTTA tmpQ[0] = 0; tmpQ[1] = tmpX[4]; tmpQ[2] = tmpX[5]; tmpQ[3] = tmpX[6]; Quaternion_RungeKutta4(tmpX, tmpQ, dt, 1); #else // halfdx = halfdt * tmpX[4]; halfdy = halfdt * tmpX[5]; halfdz = halfdt * tmpX[6]; // tmpQ[0] = tmpX[0]; tmpQ[1] = tmpX[1]; tmpQ[2] = tmpX[2]; tmpQ[3] = tmpX[3]; //model prediction //simple way, pay attention!!! //according to the actual gyroscope output //and coordinate system definition tmpX[0] = tmpQ[0] + (halfdx * tmpQ[1] + halfdy * tmpQ[2] + halfdz * tmpQ[3]); tmpX[1] = tmpQ[1] - (halfdx * tmpQ[0] + halfdy * tmpQ[3] - halfdz * tmpQ[2]); tmpX[2] = tmpQ[2] + (halfdx * tmpQ[3] - halfdy * tmpQ[0] - halfdz * tmpQ[1]); tmpX[3] = tmpQ[3] - (halfdx * tmpQ[2] - halfdy * tmpQ[1] + halfdz * tmpQ[0]); ////////////////////////////////////////////////////////////////////////// //Re-normalize Quaternion norm = FastSqrtI(tmpX[0] * tmpX[0] + tmpX[1] * tmpX[1] + tmpX[2] * tmpX[2] + tmpX[3] * tmpX[3]); tmpX[0] *= norm; tmpX[1] *= norm; tmpX[2] *= norm; tmpX[3] *= norm; #endif // arm_mat_setcolumn_f32(&ukf->XSP, tmpX, 0); for(row = 0; row < UKF_STATE_DIM; row++){ X[row] = ukf->Wm0 * tmpX[row]; } for(col = 1; col < UKF_SP_POINTS; col++){ // arm_mat_getcolumn_f32(&ukf->XSP, tmpX, col); // #ifdef USE_4TH_RUNGE_KUTTA tmpQ[0] = 0; tmpQ[1] = tmpX[4]; tmpQ[2] = tmpX[5]; tmpQ[3] = tmpX[6]; Quaternion_RungeKutta4(tmpX, tmpQ, dt, 1); #else halfdx = halfdt * tmpX[4]; halfdy = halfdt * tmpX[5]; halfdz = halfdt * tmpX[6]; // tmpQ[0] = tmpX[0]; tmpQ[1] = tmpX[1]; tmpQ[2] = tmpX[2]; tmpQ[3] = tmpX[3]; //model prediction //simple way, pay attention!!! //according to the actual gyroscope output //and coordinate system definition tmpX[0] = tmpQ[0] + (halfdx * tmpQ[1] + halfdy * tmpQ[2] + halfdz * tmpQ[3]); tmpX[1] = tmpQ[1] - (halfdx * tmpQ[0] + halfdy * tmpQ[3] - halfdz * tmpQ[2]); tmpX[2] = tmpQ[2] + (halfdx * tmpQ[3] - halfdy * tmpQ[0] - halfdz * tmpQ[1]); tmpX[3] = tmpQ[3] - (halfdx * tmpQ[2] - halfdy * tmpQ[1] + halfdz * tmpQ[0]); ////////////////////////////////////////////////////////////////////////// //re-normalize quaternion norm = FastSqrtI(tmpX[0] * tmpX[0] + tmpX[1] * tmpX[1] + tmpX[2] * tmpX[2] + tmpX[3] * tmpX[3]); tmpX[0] *= norm; tmpX[1] *= norm; tmpX[2] *= norm; tmpX[3] *= norm; #endif // arm_mat_setcolumn_f32(&ukf->XSP, tmpX, col); for(row = 0; row < UKF_STATE_DIM; row++){ X[row] += ukf->Wmi * tmpX[row]; } } for(col = 0; col < UKF_SP_POINTS; col++){ arm_mat_getcolumn_f32(&ukf->XSP, tmpX, col); arm_mat_sub_f32(&ukf->tmpX, &ukf->X, &ukf->tmpX); arm_mat_setcolumn_f32(&ukf->tmpXSP, tmpX, col); } arm_mat_trans_f32(&ukf->tmpXSP, &ukf->tmpXSPT); arm_mat_mult_f32(&ukf->tmpXSP, &ukf->Wc, &ukf->tmpWcXSP); arm_mat_mult_f32(&ukf->tmpWcXSP, &ukf->tmpXSPT, &ukf->PX); arm_mat_add_f32(&ukf->PX, &ukf->Q, &ukf->PX); ////////////////////////////////////////////////////////////////////////// //recalculate sigma points //UKF_GenerateSigmaPoints(ukf); //measurement update //unscented transformation of measurments ////////////////////////////////////////////////////////////////////////// //Normalize accel and mag norm = FastSqrtI(accel[0] * accel[0] + accel[1] * accel[1] + accel[2] * accel[2]); accel[0] *= norm; accel[1] *= norm; accel[2] *= norm; ////////////////////////////////////////////////////////////////////////// norm = FastSqrtI(mag[0] * mag[0] + mag[1] * mag[1] + mag[2] * mag[2]); mag[0] *= norm; mag[1] *= norm; mag[2] *= norm; _2mx = 2.0f * mag[0]; _2my = 2.0f * mag[1]; _2mz = 2.0f * mag[2]; arm_mat_getcolumn_f32(&ukf->XSP, tmpX, 0); //Auxiliary variables to avoid repeated arithmetic // q0q0 = tmpX[0] * tmpX[0]; q0q1 = tmpX[0] * tmpX[1]; q0q2 = tmpX[0] * tmpX[2]; q0q3 = tmpX[0] * tmpX[3]; q1q1 = tmpX[1] * tmpX[1]; q1q2 = tmpX[1] * tmpX[2]; q1q3 = tmpX[1] * tmpX[3]; q2q2 = tmpX[2] * tmpX[2]; q2q3 = tmpX[2] * tmpX[3]; q3q3 = tmpX[3] * tmpX[3]; //Reference direction of Earth's magnetic field hx = _2mx * (0.5f - q2q2 - q3q3) + _2my * (q1q2 - q0q3) + _2mz *(q1q3 + q0q2); hy = _2mx * (q1q2 + q0q3) + _2my * (0.5f - q1q1 - q3q3) + _2mz * (q2q3 - q0q1); hz = _2mx * (q1q3 - q0q2) + _2my * (q2q3 + q0q1) + _2mz *(0.5f - q1q1 - q2q2); arm_sqrt_f32(hx * hx + hy * hy, &bx); bz = hz; tmpY[0] = tmpX[0]; tmpY[1] = tmpX[1]; tmpY[2] = tmpX[2]; tmpY[3] = tmpX[3]; tmpY[4] = 2.0f * (q1q3 - q0q2); tmpY[5] = 2.0f * (q2q3 + q0q1); tmpY[6] = -1.0f + 2.0f * (q0q0 + q3q3); tmpY[7] = tmpX[4]; tmpY[8] = tmpX[5]; tmpY[9] = tmpX[6]; tmpY[10] = bx * (1.0f - 2.0f * (q2q2 + q3q3)) + bz * ( 2.0f * (q1q3 - q0q2)); tmpY[11] = bx * (2.0f * (q1q2 - q0q3)) + bz * (2.0f * (q2q3 + q0q1)); tmpY[12] = bx * (2.0f * (q1q3 + q0q2)) + bz * (1.0f - 2.0f * (q1q1 + q2q2)); arm_mat_setcolumn_f32(&ukf->YSP, tmpY, 0); for(row = 0; row < UKF_MEASUREMENT_DIM; row++){ Y[row] = ukf->Wm0 * tmpY[row]; } for(col = 1; col < UKF_SP_POINTS; col++){ arm_mat_getcolumn_f32(&ukf->XSP, tmpX, col); //Auxiliary variables to avoid repeated arithmetic // q0q0 = tmpX[0] * tmpX[0]; q0q1 = tmpX[0] * tmpX[1]; q0q2 = tmpX[0] * tmpX[2]; q0q3 = tmpX[0] * tmpX[3]; q1q1 = tmpX[1] * tmpX[1]; q1q2 = tmpX[1] * tmpX[2]; q1q3 = tmpX[1] * tmpX[3]; q2q2 = tmpX[2] * tmpX[2]; q2q3 = tmpX[2] * tmpX[3]; q3q3 = tmpX[3] * tmpX[3]; //Reference direction of Earth's magnetic field hx = _2mx * (0.5f - q2q2 - q3q3) + _2my * (q1q2 - q0q3) + _2mz *(q1q3 + q0q2); hy = _2mx * (q1q2 + q0q3) + _2my * (0.5f - q1q1 - q3q3) + _2mz * (q2q3 - q0q1); hz = _2mx * (q1q3 - q0q2) + _2my * (q2q3 + q0q1) + _2mz *(0.5f - q1q1 - q2q2); arm_sqrt_f32(hx * hx + hy * hy, &bx); bz = hz; tmpY[0] = tmpX[0]; tmpY[1] = tmpX[1]; tmpY[2] = tmpX[2]; tmpY[3] = tmpX[3]; tmpY[4] = 2.0f * (q1q3 - q0q2); tmpY[5] = 2.0f * (q2q3 + q0q1); tmpY[6] = -1.0f + 2.0f * (q0q0 + q3q3); tmpY[7] = tmpX[4]; tmpY[8] = tmpX[5]; tmpY[9] = tmpX[6]; tmpY[10] = bx * (1.0f - 2.0f * (q2q2 + q3q3)) + bz * ( 2.0f * (q1q3 - q0q2)); tmpY[11] = bx * (2.0f * (q1q2 - q0q3)) + bz * (2.0f * (q2q3 + q0q1)); tmpY[12] = bx * (2.0f * (q1q3 + q0q2)) + bz * (1.0f - 2.0f * (q1q1 + q2q2)); arm_mat_setcolumn_f32(&ukf->YSP, tmpY, col); for(row = 0; row < UKF_MEASUREMENT_DIM; row++){ Y[row] += ukf->Wmi * tmpY[row]; } } for(col = 0; col < UKF_SP_POINTS; col++){ arm_mat_getcolumn_f32(&ukf->YSP, tmpY, col); arm_mat_sub_f32(&ukf->tmpY, &ukf->Y, &ukf->tmpY); arm_mat_setcolumn_f32(&ukf->tmpYSP, tmpY, col); } arm_mat_trans_f32(&ukf->tmpYSP, &ukf->tmpYSPT); arm_mat_mult_f32(&ukf->tmpYSP, &ukf->Wc, &ukf->tmpWcYSP); arm_mat_mult_f32(&ukf->tmpWcYSP, &ukf->tmpYSPT, &ukf->PY); arm_mat_add_f32(&ukf->PY, &ukf->R, &ukf->PY); //transformed cross-covariance arm_mat_mult_f32(&ukf->tmpWcXSP, &ukf->tmpYSPT, &ukf->PXY); //calculate kalman gate //K = PXY * inv(PY); arm_mat_inverse_f32(&ukf->PY, &ukf->tmpPY); arm_mat_mult_f32(&ukf->PXY, &ukf->tmpPY, &ukf->K); //state update //X = X + K*(z - Y); Y[0] = q[0] - Y[0]; Y[1] = q[1] - Y[1]; Y[2] = q[2] - Y[2]; Y[3] = q[3] - Y[3]; // Y[4] = accel[0] - Y[4]; Y[5] = accel[1] - Y[5]; Y[6] = accel[2] - Y[6]; Y[7] = gyro[0] - Y[7]; Y[8] = gyro[1] - Y[8]; Y[9] = gyro[2] - Y[9]; ////////////////////////////////////////////////////////////////////////// Y[10] = mag[0] - Y[10]; Y[11] = mag[1] - Y[11]; Y[12] = mag[2] - Y[12]; arm_mat_mult_f32(&ukf->K, &ukf->Y, &ukf->tmpX); arm_mat_add_f32(&ukf->X, &ukf->tmpX, &ukf->X); //normalize quaternion norm = FastSqrtI(X[0] * X[0] + X[1] * X[1] + X[2] * X[2] + X[3] * X[3]); X[0] *= norm; X[1] *= norm; X[2] *= norm; X[3] *= norm; //covariance update #if 0 //the default tuning parameters don't work properly //so that use the simple update method below //original update method //P = PX - K * PY * K' arm_mat_trans_f32(&ukf->K, &ukf->KT); arm_mat_mult_f32(&ukf->K, &ukf->PY, &ukf->PXY); arm_mat_mult_f32(&ukf->PXY, &ukf->KT, &ukf->P); arm_mat_sub_f32(&ukf->PX, &ukf->P, &ukf->P); #else //must tune the P,Q,R //simple update method //P = PX - K * PXY' arm_mat_trans_f32(&ukf->PXY, &ukf->PXYT); arm_mat_mult_f32(&ukf->K, &ukf->PXYT, &ukf->P); arm_mat_sub_f32(&ukf->PX, &ukf->P, &ukf->P); #endif } void UKF_GetAngle(UKF_Filter* ukf, float32_t* rpy) { float32_t R[3][3]; float32_t *X = ukf->X_f32; //Z-Y-X R[0][0] = 2.0f * (X[0] * X[0] + X[1] * X[1]) - 1.0f; R[0][1] = 2.0f * (X[1] * X[2] + X[0] * X[3]); R[0][2] = 2.0f * (X[1] * X[3] - X[0] * X[2]); //R[1][0] = 2.0f * (X[1] * X[2] - X[0] * X[3]); //R[1][1] = 2.0f * (X[0] * X[0] + X[2] * X[2]) - 1.0f; R[1][2] = 2.0f * (X[2] * X[3] + X[0] * X[1]); //R[2][0] = 2.0f * (X[1] * X[3] + X[0] * X[2]); //R[2][1] = 2.0f * (X[2] * X[3] - X[0] * X[1]); R[2][2] = 2.0f * (X[0] * X[0] + X[3] * X[3]) - 1.0f; //roll rpy[0] = FastAtan2(R[1][2], R[2][2]); if (rpy[0] == UKF_PI) rpy[0] = -UKF_PI; //pitch if (R[0][2] >= 1.0f) rpy[1] = -UKF_HALFPI; else if (R[0][2] <= -1.0f) rpy[1] = UKF_HALFPI; else rpy[1] = FastAsin(-R[0][2]); //yaw rpy[2] = FastAtan2(R[0][1], R[0][0]); if (rpy[2] < 0.0f){ rpy[2] += UKF_TWOPI; } if (rpy[2] > UKF_TWOPI){ rpy[2] = 0.0f; } rpy[0] = UKF_TODEG(rpy[0]); rpy[1] = UKF_TODEG(rpy[1]); rpy[2] = UKF_TODEG(rpy[2]); } ================================================ FILE: Application/inc/stm32f4_common.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _STM32F4_COMMON_H #define _STM32F4_COMMON_H #include "stm32f4xx.h" #endif ================================================ FILE: Application/inc/stm32f4_crc.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __STM32F4_CRC_H #define __STM32F4_CRC_H // Includes #include "stm32f4xx.h" u16 CRC_Cal16(u8 *puchMsg, u16 usDataLen); #endif ================================================ FILE: Application/inc/stm32f4_delay.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef STM32F4_DELAY_H #define STM32F4_DELAY_H #include "stm32f4xx.h" void Delay_Init(void); void Delay_Ms(u32 ms); void Delay_Us(u32 value); int Get_Ms(unsigned long *count); u32 Micros(void); u32 Millis(void); #endif ================================================ FILE: Application/inc/stm32f4_dmp.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #define DEFAULT_MPU_HZ (200) __inline unsigned short inv_row_2_scale(const signed char *row) { unsigned short b; if (row[0] > 0) b = 0; else if (row[0] < 0) b = 4; else if (row[1] > 0) b = 1; else if (row[1] < 0) b = 5; else if (row[2] > 0) b = 2; else if (row[2] < 0) b = 6; else b = 7; // error return b; } static __inline unsigned short inv_orientation_matrix_to_scalar(const signed char *mtx){ unsigned short scalar; /* XYZ 010_001_000 Identity Matrix XZY 001_010_000 YXZ 010_000_001 YZX 000_010_001 ZXY 001_000_010 ZYX 000_001_010 */ scalar = inv_row_2_scale(mtx); scalar |= inv_row_2_scale(mtx + 3) << 3; scalar |= inv_row_2_scale(mtx + 6) << 6; return scalar; } ================================================ FILE: Application/inc/stm32f4_exti.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _STM32F4_EXTI_H #define _STM32F4_EXTI_H #include "stm32f4xx.h" //Define the Interrupt pin #define INTERRUPT_PIN GPIO_Pin_8 #define INTERRUPT_GPIO_PORT GPIOB #define INTERRUPT_GPIO_CLK RCC_AHB1Periph_GPIOB #define INTERRUPT_EXTI_LINE EXTI_Line8 #define INTERRUPT_EXTI_PORT_SOURCE EXTI_PortSourceGPIOB #define INTERRUPT_EXTI_PIN_SOURCE GPIO_PinSource8 #define INTERRUPT_EDGE EXTI_Trigger_Rising #define INTERRUPT_EXTI_IRQN EXTI9_5_IRQn #define INTERRUPT_EXTI_PREEMPTION_PRIORITY 14 #define INTERRUPT_EXTI_SUB_PRIORITY 0 void Interrupt_Init(void); u8 Interrupt_GetState(void); #endif ================================================ FILE: Application/inc/stm32f4_gps.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _STM32F4_GPS_H #define _STM32F4_GPS_H #endif ================================================ FILE: Application/inc/stm32f4_mpu9250.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _STM32F4_MPU9250_H #define _STM32F4_MPU9250_H #include "stm32f4xx.h" ////////////////////////////////////////////////////////////////////////// //Register Map for Gyroscope and Accelerometer #define MPU9250_SELF_TEST_X_GYRO 0x00 #define MPU9250_SELF_TEST_Y_GYRO 0x01 #define MPU9250_SELF_TEST_Z_GYRO 0x02 #define MPU9250_SELF_TEST_X_ACCEL 0x0D #define MPU9250_SELF_TEST_Y_ACCEL 0x0E #define MPU9250_SELF_TEST_Z_ACCEL 0x0F #define MPU9250_XG_OFFSET_H 0x13 #define MPU9250_XG_OFFSET_L 0x14 #define MPU9250_YG_OFFSET_H 0x15 #define MPU9250_YG_OFFSET_L 0x16 #define MPU9250_ZG_OFFSET_H 0x17 #define MPU9250_ZG_OFFSET_L 0x18 #define MPU9250_SMPLRT_DIV 0x19 #define MPU9250_CONFIG 0x1A #define MPU9250_GYRO_CONFIG 0x1B #define MPU9250_ACCEL_CONFIG 0x1C #define MPU9250_ACCEL_CONFIG2 0x1D #define MPU9250_LP_ACCEL_ODR 0x1E #define MPU9250_WOM_THR 0x1F #define MPU9250_FIFO_EN 0x23 #define MPU9250_I2C_MST_CTRL 0x24 #define MPU9250_I2C_SLV0_ADDR 0x25 #define MPU9250_I2C_SLV0_REG 0x26 #define MPU9250_I2C_SLV0_CTRL 0x27 #define MPU9250_I2C_SLV1_ADDR 0x28 #define MPU9250_I2C_SLV1_REG 0x29 #define MPU9250_I2C_SLV1_CTRL 0x2A #define MPU9250_I2C_SLV2_ADDR 0x2B #define MPU9250_I2C_SLV2_REG 0x2C #define MPU9250_I2C_SLV2_CTRL 0x2D #define MPU9250_I2C_SLV3_ADDR 0x2E #define MPU9250_I2C_SLV3_REG 0x2F #define MPU9250_I2C_SLV3_CTRL 0x30 #define MPU9250_I2C_SLV4_ADDR 0x31 #define MPU9250_I2C_SLV4_REG 0x32 #define MPU9250_I2C_SLV4_DO 0x33 #define MPU9250_I2C_SLV4_CTRL 0x34 #define MPU9250_I2C_SLV4_DI 0x35 #define MPU9250_I2C_MST_STATUS 0x36 #define MPU9250_INT_PIN_CFG 0x37 #define MPU9250_INT_ENABLE 0x38 #define MPU9250_INT_STATUS 0x3A #define MPU9250_ACCEL_XOUT_H 0x3B #define MPU9250_ACCEL_XOUT_L 0x3C #define MPU9250_ACCEL_YOUT_H 0x3D #define MPU9250_ACCEL_YOUT_L 0x3E #define MPU9250_ACCEL_ZOUT_H 0x3F #define MPU9250_ACCEL_ZOUT_L 0x40 #define MPU9250_TEMP_OUT_H 0x41 #define MPU9250_TEMP_OUT_L 0x42 #define MPU9250_GYRO_XOUT_H 0x43 #define MPU9250_GYRO_XOUT_L 0x44 #define MPU9250_GYRO_YOUT_H 0x45 #define MPU9250_GYRO_YOUT_L 0x46 #define MPU9250_GYRO_ZOUT_H 0x47 #define MPU9250_GYRO_ZOUT_L 0x48 #define MPU9250_EXT_SENS_DATA_00 0x49 #define MPU9250_EXT_SENS_DATA_01 0x4A #define MPU9250_EXT_SENS_DATA_02 0x4B #define MPU9250_EXT_SENS_DATA_03 0x4C #define MPU9250_EXT_SENS_DATA_04 0x4D #define MPU9250_EXT_SENS_DATA_05 0x4E #define MPU9250_EXT_SENS_DATA_06 0x4F #define MPU9250_EXT_SENS_DATA_07 0x50 #define MPU9250_EXT_SENS_DATA_08 0x51 #define MPU9250_EXT_SENS_DATA_09 0x52 #define MPU9250_EXT_SENS_DATA_10 0x53 #define MPU9250_EXT_SENS_DATA_11 0x54 #define MPU9250_EXT_SENS_DATA_12 0x55 #define MPU9250_EXT_SENS_DATA_13 0x56 #define MPU9250_EXT_SENS_DATA_14 0x57 #define MPU9250_EXT_SENS_DATA_15 0x58 #define MPU9250_EXT_SENS_DATA_16 0x59 #define MPU9250_EXT_SENS_DATA_17 0x5A #define MPU9250_EXT_SENS_DATA_18 0x5B #define MPU9250_EXT_SENS_DATA_19 0x5C #define MPU9250_EXT_SENS_DATA_20 0x5D #define MPU9250_EXT_SENS_DATA_21 0x5E #define MPU9250_EXT_SENS_DATA_22 0x5F #define MPU9250_EXT_SENS_DATA_23 0x60 #define MPU9250_I2C_SLV0_DO 0x63 #define MPU9250_I2C_SLV1_DO 0x64 #define MPU9250_I2C_SLV2_DO 0x65 #define MPU9250_I2C_SLV3_DO 0x66 #define MPU9250_I2C_MST_DELAY_CTRL 0x67 #define MPU9250_SIGNAL_PATH_RESET 0x68 #define MPU9250_MOT_DETECT_CTRL 0x69 #define MPU9250_USER_CTRL 0x6A #define MPU9250_PWR_MGMT_1 0x6B #define MPU9250_PWR_MGMT_2 0x6C #define MPU9250_FIFO_COUNTH 0x72 #define MPU9250_FIFO_COUNTL 0x73 #define MPU9250_FIFO_R_W 0x74 #define MPU9250_WHO_AM_I 0x75 #define MPU9250_XA_OFFSET_H 0x77 #define MPU9250_XA_OFFSET_L 0x78 #define MPU9250_YA_OFFSET_H 0x7A #define MPU9250_YA_OFFSET_L 0x7B #define MPU9250_ZA_OFFSET_H 0x7D #define MPU9250_ZA_OFFSET_L 0x7E // #define MPU9250_I2C_READ 0x80 //Magnetometer register maps #define MPU9250_AK8963_WIA 0x00 #define MPU9250_AK8963_INFO 0x01 #define MPU9250_AK8963_ST1 0x02 #define MPU9250_AK8963_XOUT_L 0x03 #define MPU9250_AK8963_XOUT_H 0x04 #define MPU9250_AK8963_YOUT_L 0x05 #define MPU9250_AK8963_YOUT_H 0x06 #define MPU9250_AK8963_ZOUT_L 0x07 #define MPU9250_AK8963_ZOUT_H 0x08 #define MPU9250_AK8963_ST2 0x09 #define MPU9250_AK8963_CNTL 0x0A #define MPU9250_AK8963_CNTL2 0x0B #define MPU9250_AK8963_RSV 0x0B //DO NOT ACCESS #define MPU9250_AK8963_ASTC 0x0C #define MPU9250_AK8963_TS1 0x0D //DO NOT ACCESS #define MPU9250_AK8963_TS2 0x0E //DO NOT ACCESS #define MPU9250_AK8963_I2CDIS 0x0F #define MPU9250_AK8963_ASAX 0x10 #define MPU9250_AK8963_ASAY 0x11 #define MPU9250_AK8963_ASAZ 0x12 #define MPU9250_AK8963_I2C_ADDR 0x0C #define MPU9250_AK8963_POWER_DOWN 0x10 #define MPU9250_AK8963_FUSE_ROM_ACCESS 0x1F #define MPU9250_AK8963_SINGLE_MEASUREMENT 0x11 #define MPU9250_AK8963_CONTINUOUS_MEASUREMENT 0x16 //MODE 2 #define MPU9250_AK8963_DATA_READY (0x01) #define MPU9250_AK8963_DATA_OVERRUN (0x02) #define MPU9250_AK8963_OVERFLOW (0x80) #define MPU9250_AK8963_DATA_ERROR (0x40) #define MPU9250_AK8963_CNTL2_SRST 0x01 // #define MPU9250_I2C_SLV4_EN 0x80 #define MPU9250_I2C_SLV4_DONE 0x40 #define MPU9250_I2C_SLV4_NACK 0x10 // #define MPU9250_I2C_IF_DIS (0x10) #define MPU9250_I2C_MST_EN (0x20) #define MPU9250_FIFO_RST (0x04) #define MPU9250_FIFO_ENABLE (0x40) // #define MPU9250_RESET 0x80 #define MPU9250_CLOCK_MASK 0xF8 #define MPU9250_CLOCK_INTERNAL 0x00 #define MPU9250_CLOCK_PLL 0x01 #define MPU9250_CLOCK_PLLGYROZ 0x03 #define MPU9250_FS_SEL_MASK 0xE7 #define MPU9250_SLEEP_MASK 0x40 // #define MPU9250_XYZ_GYRO 0xC7 #define MPU9250_XYZ_ACCEL 0xF8 // #define MPU9250_RAW_RDY_EN (0x01) #define MPU9250_RAW_DATA_RDY_INT (0x01) #define MPU9250_FIFO_OVERFLOW (0x10) // #define MPU9250_INT_ANYRD_2CLEAR (0x10) #define MPU9250_LATCH_INT_EN (0x20) // #define MPU9250_MAX_FIFO (1024) #define MPU9250_FIFO_SIZE_1024 (0x40) #define MPU9250_FIFO_SIZE_2048 (0x80) #define MPU9250_FIFO_SIZE_4096 (0xC0) #define MPU9250_TEMP_OUT (0x80) #define MPU9250_GYRO_XOUT (0x40) #define MPU9250_GYRO_YOUT (0x20) #define MPU9250_GYRO_ZOUT (0x10) #define MPU9250_ACCEL (0x08) // #define SMPLRT_DIV 0 #define MPU9250_SPIx_ADDR 0x00 ////////////////////////////////////////////////////////////////////////// // enum MPU9250_GYRO_DLPF { MPU9250_GYRO_DLPF_250HZ = 0, MPU9250_GYRO_DLPF_184HZ, MPU9250_GYRO_DLPF_92HZ, MPU9250_GYRO_DLPF_41HZ, MPU9250_GYRO_DLPF_20HZ, MPU9250_GYRO_DLPF_10HZ, MPU9250_GYRO_DLPF_5HZ, MPU9250_GYRO_DLPF_3600HZ, NUM_GYRO_DLPF }; enum MPU9250_GYRO_FSR { MPU9250_FSR_250DPS = 0, MPU9250_FSR_500DPS, MPU9250_FSR_1000DPS, MPU9250_FSR_2000DPS, MPU9250_NUM_GYRO_FSR }; enum MPU9250_ACCEL_DLPF { MPU9250_ACCEL_DLPF_460HZ = 0, MPU9250_ACCEL_DLPF_184HZ, MPU9250_ACCEL_DLPF_92HZ, MPU9250_ACCEL_DLPF_41HZ, MPU9250_ACCEL_DLPF_20HZ, MPU9250_ACCEL_DLPF_10HZ, MPU9250_ACCEL_DLPF_5HZ, MPU9250_ACCEL_DLPF_460HZ2, MPU9250_NUM_ACCEL_DLPF }; enum MPU9250_ACCEL_FSR { MPU9250_FSR_2G = 0, MPU9250_FSR_4G, MPU9250_FSR_8G, MPU9250_FSR_16G, MPU9250_NUM_ACCEL_FSR }; enum MPU9250_CLK { MPU9250_CLK_INTERNAL = 0, MPU9250_CLK_PLL, MPU9250_NUM_CLK }; ////////////////////////////////////////////////////////////////////////// //low hardware functions void MPU9250_Init(void); u8 MPU9250_SPIx_SendByte(u8 data); void MPU9250_SPIx_SetDivisor(u16 data); // u8 MPU9250_SPIx_Read(u8 addr, u8 reg_addr); int MPU9250_SPIx_Reads(u8 addr, u8 reg_addr, u8 len, u8* data); int MPU9250_SPIx_Write(u8 addr, u8 reg_addr, u8 data); int MPU9250_SPIx_Writes(u8 addr, u8 reg_addr, u8 len, u8* data); //global function use for eMPL int MPU9250_AK8963_SPIx_Read(u8 akm_addr, u8 reg_addr, u8* data); int MPU9250_AK8963_SPIx_Reads(u8 akm_addr, u8 reg_addr, u8 len, u8* data); int MPU9250_AK8963_SPIx_Write(u8 akm_addr, u8 reg_addr, u8 data); int MPU9250_AK8963_SPIx_Writes(u8 akm_addr, u8 reg_addr, u8 len, u8* data); //data functions void MPU9250_Get9AxisRawData(short *accel, short * gyro, short * mag); void MPU9250_Get6AxisRawData(short* accel, short* gyro); void MPU9250_Get3AxisAccelRawData(short * accel); void MPU9250_Get3AxisGyroRawData(short* gyro); void MPU9250_Get3AxisMagnetRawData(short *mag); void MPU9250_GetTemperatureRawData(long *temperature); int MPU9250_IsDataReady(void); #endif ================================================ FILE: Application/inc/stm32f4_ms5611.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef STM32F4_MS5611_H #define STM32F4_MS5611_H #include "stm32f4xx.h" // #define MS5611_RESET 0x1E #define MS5611_READ_ADC 0x00 #define MS5611_READ 0x00 //OSR 256 0.60 mSec conversion time (1666.67 Hz) //OSR 512 1.17 mSec conversion time ( 854.70 Hz) //OSR 1024 2.28 mSec conversion time ( 357.14 Hz) //OSR 2048 4.54 mSec conversion time ( 220.26 Hz) //OSR 4096 9.04 mSec conversion time ( 110.62 Hz) #define D1_OSR_256 0x40 #define D1_OSR_512 0x42 #define D1_OSR_1024 0x44 #define D1_OSR_2048 0x46 #define D1_OSR_4096 0x48 #define D2_OSR_256 0x50 #define D2_OSR_512 0x52 #define D2_OSR_1024 0x54 #define D2_OSR_2048 0x56 #define D2_OSR_4096 0x58 #define MS5611_READ_PROM_RSV 0xA0 //0xA0 to 0xAE #define MS5611_READ_PROM_C1 0xA2 #define MS5611_READ_PROM_C2 0xA4 #define MS5611_READ_PROM_C3 0xA6 #define MS5611_READ_PROM_C4 0xA8 #define MS5611_READ_PROM_C5 0xAA #define MS5611_READ_PROM_C6 0xAC #define MS5611_READ_PROM_CRC 0xAE u8 MS5611_SPIx_SendByte(u8); void MS5611_Init(void); void MS5611_GetTemperatureAndPressure(s32* TEMP, s32 *P); #endif ================================================ FILE: Application/inc/stm32f4_rcc.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _STM32F4_RCC_H #define _STM32F4_RCC_H #include "stm32f4xx.h" typedef struct PLL_PARAMS_T { uint32_t PLLM; uint32_t PLLN; uint32_t PLLP; uint32_t PLLQ; } PLL_PARAMS; typedef void (*RCC_AXXPeriphClockCmd)(uint32_t RCC_AXXPeriph, FunctionalState NewState); void RCC_SystemCoreClockUpdate(PLL_PARAMS params); #endif ================================================ FILE: Application/inc/stm32f4_serial.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _STM32F4_SERIAL_H #define _STM32F4_SERIAL_H #include "stm32f4xx.h" #define PACKET_LENGTH (46) //low function void Serial_Init(void); void Serial_SendByte(uint8_t byte); void Serial_SendBytes(uint8_t* buffer, uint8_t length); // void Serial_Upload(short accel[3], short gyro[3], short compass[3], long quat[4], long temperature, long pressure); #endif ================================================ FILE: Application/inc/stm32f4_string.h ================================================ #ifndef _STM32F4_STRING_H_ #define _STM32F4_STRING_H_ #include "stm32f4xx.h" void FastMemCpy(uint8_t* dest, uint8_t* src, uint16_t size); #endif ================================================ FILE: Application/inc/stm32f4_ublox.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _STM32F4_UBLOX_H #define _STM32F4_UBLOX_H #include "stm32f4xx.h" #include "Nema.h" #define UBLOX_DEFAULT_BAUDRATE (9600) #define UBLOX_DEFAULT_TX_BUFFERSIZE (64) #define UBLOX_DEFAULT_RX_BUFFERSIZE (512) #define UBLOX_DEFAULT_PARSER_MAXSIZE (128) typedef struct UBLOX_PARSERBUFF { s8 *Data; u16 Size; u16 Need; u16 Left; }Ublox_ParserBuff; void Ublox_Init(void); void Ublox_GetMessage(void); void Ublox_GetPostion(double *x, double *y, double *z); #endif ================================================ FILE: Application/inc/stm32f4xx_conf.h ================================================ /** ****************************************************************************** * @file stm32f4xx_conf.h * @author MCD Application Team * @version V1.0.0 * @date 19-September-2011 * @brief Library configuration file. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * *

© COPYRIGHT 2011 STMicroelectronics

****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_CONF_H #define __STM32F4xx_CONF_H #if defined (HSE_VALUE) /* Redefine the HSE value; it's equal to 12 MHz on the STM32F4-DISCOVERY Kit */ #undef HSE_VALUE #define HSE_VALUE ((uint32_t)12000000) #endif /* HSE_VALUE */ /* Includes ------------------------------------------------------------------*/ /* Uncomment the line below to enable peripheral header file inclusion */ // #include "stm32f4xx_adc.h" // #include "stm32f4xx_can.h" //#include "stm32f4xx_crc.h" // #include "stm32f4xx_cryp.h" // #include "stm32f4xx_dac.h" // #include "stm32f4xx_dbgmcu.h" // #include "stm32f4xx_dcmi.h" #include "stm32f4xx_dma.h" #include "stm32f4xx_exti.h" #include "stm32f4xx_flash.h" // #include "stm32f4xx_fsmc.h" // #include "stm32f4xx_hash.h" #include "stm32f4xx_gpio.h" //#include "stm32f4xx_i2c.h" // #include "stm32f4xx_iwdg.h" // #include "stm32f4xx_pwr.h" #include "stm32f4xx_rcc.h" // #include "stm32f4xx_rng.h" // #include "stm32f4xx_rtc.h" // #include "stm32f4xx_sdio.h" #include "stm32f4xx_spi.h" #include "stm32f4xx_syscfg.h" //#include "stm32f4xx_tim.h" #include "stm32f4xx_usart.h" // #include "stm32f4xx_wwdg.h" #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* If an external clock source is used, then the value of the following define should be set to the value of the external clock source, else, if no external clock is used, keep this define commented */ /*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ /* Uncomment the line below to expanse the "assert_param" macro in the Standard Peripheral Library drivers code */ /* #define USE_FULL_ASSERT 1 */ /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT /** * @brief The assert_param macro is used for function's parameters check. * @param expr: If expr is false, it calls assert_failed function * which reports the name of the source file and the source * line number of the call that failed. * If expr is true, it returns no value. * @retval None */ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ void assert_failed(uint8_t* file, uint32_t line); #else #define assert_param(expr) ((void)0) #endif /* USE_FULL_ASSERT */ #endif /* __STM32F4xx_CONF_H */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ ================================================ FILE: Application/inc/stm32f4xx_it.h ================================================ /** ****************************************************************************** * @file USART/USART_TwoBoards/USART_DataExchangeDMA/stm32f4xx_it.h * @author MCD Application Team * @version V1.4.0 * @date 04-August-2014 * @brief This file contains the headers of the interrupt handlers. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_IT_H #define __STM32F4xx_IT_H /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ void NMI_Handler(void); void HardFault_Handler(void); void MemManage_Handler(void); void BusFault_Handler(void); void UsageFault_Handler(void); void SVC_Handler(void); void DebugMon_Handler(void); void PendSV_Handler(void); void SysTick_Handler(void); #endif /* __STM32F4xx_IT_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Application/src/main.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ ////////////////////////////////////////////////////////////////////////// //header #include "stm32f4_delay.h" #include "stm32f4_serial.h" #include "stm32f4_rcc.h" #include "stm32f4_mpu9250.h" #include "stm32f4_ms5611.h" #include "stm32f4_ublox.h" ////////////////////////////////////////////////////////////////////////// // #include "Quaternion.h" ////////////////////////////////////////////////////////////////////////// //dmp //#define USE_DMP #include "stm32f4_dmp.h" #include "inv_mpu.h" #include "inv_mpu_dmp_motion_driver.h" ////////////////////////////////////////////////////////////////////////// //uncomment one //#define USE_EKF //#define USE_UKF //#define USE_CKF #define USE_SRCKF //#define USE_9AXIS_EKF //for doctor's mini Quadrotor //#define USE_6AXIS_EKF //#define USE_6AXIS_FP_EKF ////////////////////////////////////////////////////////////////////////// #ifdef USE_EKF #include "EKF.h" #elif defined USE_UKF #include "UKF.h" #elif defined USE_CKF #include "CKF.h" #elif defined USE_SRCKF #include "SRCKF.H" #elif defined USE_6AXIS_EKF #include "miniIMU.h" #elif defined USE_6AXIS_FP_EKF #include "FP_miniIMU.h" #elif defined USE_9AXIS_EKF #include "miniAHRS.h" #endif int main(void) { //PLL_M PLL_N PLL_P PLL_Q //PLL_PARAMS pFreq120M = {12, 240, 2, 5}; PLL_PARAMS pFreq128M = {12, 256, 2, 6}; //PLL_PARAMS pFreq168M = {12, 336, 2, 7}; s8 gyro_orientation[9] = { 0, 1, 0, 1, 0, 0, 0, 0, 1 }; s32 s32Result; struct int_param_s pInitParam = {0}; u8 u8AccelFsr = 0; u16 u16GyroRate = 0; u16 u16GyroFsr = 0; //u16 u16DmpFeatures = DMP_FEATURE_6X_LP_QUAT | DMP_FEATURE_SEND_RAW_ACCEL | DMP_FEATURE_SEND_CAL_GYRO | //DMP_FEATURE_GYRO_CAL; u16 u16DmpFeatures = DMP_FEATURE_6X_LP_QUAT | DMP_FEATURE_SEND_RAW_ACCEL | DMP_FEATURE_SEND_CAL_GYRO; s16 s16Gyro[3] = {0}, s16Accel[3] = {0}, s16Mag[3] = {0}; float fRealGyro[3] = {0}, fRealAccel[3] = {0}; #if !defined USE_6AXIS_EKF && !defined USE_6AXIS_FP_EKF float fRealMag[3] = {0}, fRealQ[4] = {0}; #endif s16 s16Sensors = 0; u8 u8More = 0; long lQuat[4] = {0}; unsigned long ulTimeStamp = 0; float fRPY[3] = {0}; float fQ[4] = {0}; //position double dX, dY, dZ; // s32 s32Temperature = 0, s32Pressure = 0; float fAltNow = 0.0f, fAltLast = 0.0f; // #ifdef USE_EKF EKF_Filter ekf; #elif defined USE_UKF UKF_Filter ukf; #elif defined USE_CKF CKF_Filter ckf; #elif defined USE_SRCKF SRCKF_Filter srckf; #endif unsigned long ulNowTime = 0; unsigned long ulLastTime = 0; unsigned long ulSendTime = 0; unsigned long ulGPSUpdateTime = 0; float fDeltaTime = 0.0f; u32 u32KFState = 0; //Reduced frequency //128 / 4 = 32Mhz APB1, 32/32 = 1MHz SPI Clock //1Mhz SPI Clock for read/write RCC_SystemCoreClockUpdate(pFreq128M); Delay_Init(); MPU9250_Init(); MS5611_Init(); Ublox_Init(); #ifdef USE_EKF //Create a new EKF object; EKF_New(&ekf); #elif defined USE_UKF //Create a new UKF object; UKF_New(&ukf); #elif defined USE_CKF //Create a new CKF object; CKF_New(&ckf); #elif defined USE_SRCKF SRCKF_New(&srckf); #endif #ifdef USE_DMP ////////////////////////////////////////////////////////////////////////// //Init DMP s32Result = mpu_init(&pInitParam); s32Result = mpu_set_sensors(INV_XYZ_GYRO | INV_XYZ_ACCEL | INV_XYZ_COMPASS); s32Result = mpu_configure_fifo(INV_XYZ_GYRO | INV_XYZ_ACCEL); s32Result = mpu_set_sample_rate(DEFAULT_MPU_HZ); s32Result = mpu_get_sample_rate(&u16GyroRate); s32Result = mpu_get_gyro_fsr(&u16GyroFsr); s32Result = mpu_get_accel_fsr(&u8AccelFsr); s32Result = dmp_load_motion_driver_firmware(); // s32Result = dmp_set_orientation(inv_orientation_matrix_to_scalar(gyro_orientation)); // s32Result = dmp_enable_feature(u16DmpFeatures); s32Result = dmp_set_fifo_rate(DEFAULT_MPU_HZ); s32Result = mpu_set_dmp_state(1); #endif ////////////////////////////////////////////////////////////////////////// //Recover frequency //why DMP fifo must be reset when it overflows. //SPI write operation occur, when you reset DMP fifo, //but it can' write at 20Mhz SPI Clock? Fix me! //RCC_SystemCoreClockUpdate(pFreq168M); //Delay_Init(); //MPU9250_Init(); //42Mhz APB1, 42/2 = 21 MHz SPI Clock //MPU9250_SPIx_SetDivisor(SPI_BaudRatePrescaler_2); Serial_Init(); for(;;){ //// Get_Ms(&ulNowTime); if (MPU9250_IsDataReady()){ #ifdef USE_DMP s32Result = dmp_read_fifo(s16Gyro, s16Accel, lQuat, &ulTimeStamp, &s16Sensors, &u8More); if(s32Result < 0){ continue; } //because 20Mhz SPI Clock satisfy MPU9250 with read condition //so that you can't use I2C Master mode read/write from SPI at 20Mhz SPI Clock //and dmp fifo can't use for Magnetometer, but you can use this function below s32Result = mpu_get_compass_reg(s16Mag, &ulTimeStamp); #else MPU9250_Get9AxisRawData(s16Accel, s16Gyro, s16Mag); #endif //must calibrate gryo, accel, magnetic data //ned coordinate system //todo fRealGyro[0] = DEGTORAD(s16Gyro[0]) * 0.06097560975609756097560975609756f; fRealGyro[1] = DEGTORAD(s16Gyro[1]) * 0.06097560975609756097560975609756f; fRealGyro[2] = DEGTORAD(s16Gyro[2]) * 0.06097560975609756097560975609756f; fRealAccel[0] = s16Accel[0] / 16384.0f; fRealAccel[1] = s16Accel[1] / 16384.0f; fRealAccel[2] = s16Accel[2] / 16384.0f; #if !defined USE_6AXIS_EKF && !defined USE_6AXIS_FP_EKF if(!s32Result){ fRealMag[0] = s16Mag[0]; fRealMag[1] = s16Mag[1]; fRealMag[2] = s16Mag[2]; } #ifdef USE_DMP //q30 to float fRealQ[0] = (float)lQuat[0] / 1073741824.0f; fRealQ[1] = (float)lQuat[1] / 1073741824.0f; fRealQ[2] = (float)lQuat[2] / 1073741824.0f; fRealQ[3] = (float)lQuat[3] / 1073741824.0f; #else Quaternion_From6AxisData(fRealQ, fRealAccel, fRealMag); #endif #endif if(!u32KFState){ if(s32Result < 0){ continue; } #ifdef USE_EKF EKF_Init(&ekf, fRealQ, fRealGyro); #elif defined USE_UKF UKF_Init(&ukf, fRealQ, fRealGyro); #elif defined USE_CKF CKF_Init(&ckf, fRealQ, fRealGyro); #elif defined USE_SRCKF SRCKF_Init(&srckf, fRealAccel, fRealMag); #elif defined USE_6AXIS_EKF EKF_IMUInit(fRealAccel, fRealGyro); #elif defined USE_6AXIS_FP_EKF FP_EKF_IMUInit(fRealAccel, fRealGyro); #elif defined USE_9AXIS_EKF EKF_AHRSInit(fRealAccel, fRealMag); #endif ulLastTime = ulNowTime; ulSendTime = ulNowTime; u32KFState = 1; } else{ fDeltaTime = 0.001f * (float)(ulNowTime - ulLastTime); #ifdef USE_EKF EFK_Update(&ekf, fRealQ, fRealGyro, fRealAccel, fRealMag, fDeltaTime); #elif defined USE_UKF UKF_Update(&ukf, fRealQ, fRealGyro, fRealAccel, fRealMag, fDeltaTime); #elif defined USE_CKF CKF_Update(&ckf, fRealQ, fRealGyro, fRealAccel, fRealMag, fDeltaTime); #elif defined USE_SRCKF SRCKF_Update(&srckf, fRealGyro, fRealAccel, fRealMag, fDeltaTime); #elif defined USE_6AXIS_EKF EKF_IMUUpdate(fRealGyro, fRealAccel, fDeltaTime); #elif defined USE_6AXIS_FP_EKF FP_EKF_IMUUpdate(fRealGyro, fRealAccel, fDeltaTime); #elif defined USE_9AXIS_EKF EKF_AHRSUpdate(fRealGyro, fRealAccel, fRealMag, fDeltaTime); #endif } #ifdef USE_EKF EKF_GetAngle(&ekf, fRPY); EKF_GetQ(&ekf, fQ); #elif defined USE_UKF UKF_GetAngle(&ukf, fRPY); UKF_GetQ(&ukf, fQ); #elif defined USE_CKF CKF_GetAngle(&ckf, fRPY); CKF_GetQ(&ckf, fQ); #elif defined USE_SRCKF SRCKF_GetAngle(&srckf, fRPY); SRCKF_GetQ(&srckf, fQ); #elif defined USE_6AXIS_EKF EKF_IMUGetAngle(fRPY); EKF_IMUGetQ(fQ); #elif defined USE_6AXIS_FP_EKF FP_EKF_IMUGetAngle(fRPY); FP_EKF_IMUGetQ(fQ); #elif defined USE_9AXIS_EKF EKF_AHRSGetAngle(fRPY); EKF_AHRSGetQ(fQ); #endif //transmit Quaternion float format to Q31 lQuat[0] = (long)(fQ[0] * 2147483648.0f); lQuat[1] = (long)(fQ[1] * 2147483648.0f); lQuat[2] = (long)(fQ[2] * 2147483648.0f); lQuat[3] = (long)(fQ[3] * 2147483648.0f); //todo ulLastTime = ulNowTime; } ////////////////////////////////////////////////////////////////////////// //ublox default 250ms up //1000 / 100 = 10HZ if(ulNowTime - ulGPSUpdateTime > 99){ Ublox_GetMessage(); Ublox_GetPostion(&dX, &dY, &dZ); ulGPSUpdateTime = ulNowTime; } ////////////////////////////////////////////////////////////////////////// //transmit the gyro, accel, mag, quat roll pitch yaw to anywhere //1000 / 10 = 100HZ if(ulNowTime - ulSendTime > 9){ MS5611_GetTemperatureAndPressure(&s32Temperature, &s32Pressure); //fRealTemperature = (float)s32Temperature * 0.01f; ////////////////////////////////////////////////////////////////////////// //simple Low pass filter, K = 0.125f fAltLast = 44330.8f - 4946.54f * FastPow((float)s32Pressure, 0.1902632f); fAltNow = fAltNow * 0.875f + fAltLast * 0.125f; ////////////////////////////////////////////////////////////////////////// Serial_Upload(s16Accel, s16Gyro, s16Mag, lQuat, s32Temperature, s32Pressure); ulSendTime = ulNowTime; } } } ================================================ FILE: Application/src/stm32f4_delay.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include"stm32f4_delay.h" //Cycles per microsecond static __IO uint32_t us_ticks = 0; static __IO uint32_t uptime_ticks = 0; static __IO uint32_t cycle_ticks = 0; void Delay_Init() { RCC_ClocksTypeDef RCC_Clocks; RCC_GetClocksFreq(&RCC_Clocks); us_ticks = RCC_Clocks.SYSCLK_Frequency / 1000000u; //enable DWT access CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk; CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; //enable the CPU cycle counter DWT->CTRL &= ~DWT_CTRL_CYCCNTENA_Msk; DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; //Reset counter DWT->CYCCNT = 0u; if(SysTick_Config(RCC_Clocks.HCLK_Frequency / 1000u)){ while (1); // Handle Error } } __inline uint32_t Millis(void) { return uptime_ticks; } u32 Micros(void) { register uint32_t old_cycle, cycle, timeMs; do{ timeMs = __LDREXW(&uptime_ticks); cycle = DWT->CYCCNT; old_cycle = cycle_ticks; } while ( __STREXW( timeMs , &uptime_ticks ) ); return (timeMs * 1000) + (cycle - old_cycle) / us_ticks; } void Delay_Ms(u32 ms) { while (ms--){ Delay_Us(1000); } } void Delay_Us(u32 us) { uint32_t elapsed = 0; uint32_t elapsed_us = 0; uint32_t lastCount = DWT->CYCCNT; register uint32_t current_count = DWT->CYCCNT; for (;;) { current_count = DWT->CYCCNT; elapsed += current_count - lastCount; lastCount = current_count; elapsed_us = elapsed / us_ticks; if (elapsed_us >= us){ break; } us -= elapsed_us; elapsed %= us_ticks; } } int Get_Ms(unsigned long *count) { count[0] = uptime_ticks; return 0; } void SysTick_Handler(void) { cycle_ticks = DWT->CYCCNT; uptime_ticks++; } ================================================ FILE: Application/src/stm32f4_exti.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "stm32f4_exti.h" #include "stm32f4_mpu9250.h" static __IO u8 gu8InterruptState = 0; void Interrupt_Init() { GPIO_InitTypeDef GPIO_InitStructure; EXTI_InitTypeDef EXTI_InitStructure; NVIC_InitTypeDef NVIC_InitStructure; //Enable MPU9250int GPIO clocks RCC_AHB1PeriphClockCmd(INTERRUPT_GPIO_CLK, ENABLE); //Enable SYSCFG clock RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); //Configure MPU9250int pin as input floating GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_InitStructure.GPIO_Pin = INTERRUPT_PIN; GPIO_Init(INTERRUPT_GPIO_PORT, &GPIO_InitStructure); //Connect MPU9250int EXTI Line to MPU9250int GPIO Pin SYSCFG_EXTILineConfig(INTERRUPT_EXTI_PORT_SOURCE, INTERRUPT_EXTI_PIN_SOURCE); //Configure MPU9250int EXTI line EXTI_InitStructure.EXTI_Line = INTERRUPT_EXTI_LINE; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_Init(&EXTI_InitStructure); //Enable and set MPU9250int EXTI Interrupt priority NVIC_InitStructure.NVIC_IRQChannel = INTERRUPT_EXTI_IRQN; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = INTERRUPT_EXTI_PREEMPTION_PRIORITY; NVIC_InitStructure.NVIC_IRQChannelSubPriority = INTERRUPT_EXTI_SUB_PRIORITY; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); } void EXTI9_5_IRQHandler(void) { gu8InterruptState = 1; EXTI_ClearITPendingBit(EXTI_Line8); } u8 Interrupt_GetState(void){ u8 u8State = gu8InterruptState; gu8InterruptState = 0; return u8State; } ================================================ FILE: Application/src/stm32f4_gps.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "stm32f4_gps.h" ================================================ FILE: Application/src/stm32f4_mpu9250.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "stm32f4_mpu9250.h" #include "stm32f4_exti.h" #include "stm32f4_spi.h" #include "stm32f4_delay.h" ////////////////////////////////////////////////////////////////////////// // static s16 MPU9250_AK8963_ASA[3] = {0, 0, 0}; ////////////////////////////////////////////////////////////////////////// //basic SPI driver for MPU9250 static SPI_Driver mMPU9250 = { SPI2, RCC_APB1PeriphClockCmd, RCC_APB1Periph_SPI2, GPIOB, RCC_AHB1PeriphClockCmd, RCC_AHB1Periph_GPIOB, GPIOB, RCC_AHB1PeriphClockCmd, RCC_AHB1Periph_GPIOB, GPIO_Pin_12, GPIO_Pin_13, GPIO_Pin_14, GPIO_Pin_15, GPIO_PinSource13, GPIO_PinSource14, GPIO_PinSource15, #ifdef SPIx_USE_DMA #endif { SPI_Direction_2Lines_FullDuplex, SPI_Mode_Master, SPI_DataSize_8b, SPI_CPOL_High, SPI_CPHA_2Edge, SPI_NSS_Soft, SPI_BaudRatePrescaler_32, SPI_FirstBit_MSB, 7 }, GPIO_AF_SPI2 }; static SPI_Driver* pMPU9250 = &mMPU9250; // static EXTI_Driver mMPU9250INT= { GPIOB, RCC_AHB1PeriphClockCmd, RCC_AHB1Periph_GPIOB, GPIO_Pin_8, EXTI_PortSourceGPIOB, EXTI_PinSource8, { EXTI_Line8, EXTI_Mode_Interrupt, EXTI_Trigger_Rising, ENABLE }, { EXTI9_5_IRQn, 14, 0, ENABLE } }; static EXTI_Driver* pMPU9250INT = &mMPU9250INT; ////////////////////////////////////////////////////////////////////////// // #define MPU9250_SPIx_SendByte(byte) SPIx_SendByte(pMPU9250, byte); #define MPU9250_SPIx_SetDivisor(divisor) SPIx_SetDivisor(pMPU9250, divisor); ////////////////////////////////////////////////////////////////////////// //init void MPU9250_Init(void) { u8 data = 0, state = 0; uint8_t response[3] = {0, 0, 0}; //Lower level hardware Init SPIx_Init(pMPU9250); EXTIx_Init(pMPU9250INT); ////////////////////////////////////////////////////////////////////////// //MPU9250 Reset MPU9250_SPIx_Write(MPU9250_SPIx_ADDR, MPU9250_PWR_MGMT_1, MPU9250_RESET); Delay_Ms(100); //MPU9250 Set Clock Source MPU9250_SPIx_Write(MPU9250_SPIx_ADDR, MPU9250_PWR_MGMT_1, MPU9250_CLOCK_PLLGYROZ); Delay_Ms(1); //MPU9250 Set Interrupt MPU9250_SPIx_Write(MPU9250_SPIx_ADDR, MPU9250_INT_PIN_CFG, MPU9250_INT_ANYRD_2CLEAR); Delay_Ms(1); MPU9250_SPIx_Write(MPU9250_SPIx_ADDR, MPU9250_INT_ENABLE, ENABLE); Delay_Ms(1); //MPU9250 Set Sensors MPU9250_SPIx_Write(MPU9250_SPIx_ADDR, MPU9250_PWR_MGMT_2, MPU9250_XYZ_GYRO & MPU9250_XYZ_ACCEL); Delay_Ms(1); //MPU9250 Set SampleRate //SAMPLE_RATE = Internal_Sample_Rate / (1 + SMPLRT_DIV) MPU9250_SPIx_Write(MPU9250_SPIx_ADDR, MPU9250_SMPLRT_DIV, SMPLRT_DIV); Delay_Ms(1); //MPU9250 Set Full Scale Gyro Range //Fchoice_b[1:0] = [00] enable DLPF MPU9250_SPIx_Write(MPU9250_SPIx_ADDR, MPU9250_GYRO_CONFIG, (MPU9250_FSR_2000DPS << 3)); Delay_Ms(1); //MPU9250 Set Full Scale Accel Range PS:2G MPU9250_SPIx_Write(MPU9250_SPIx_ADDR, MPU9250_ACCEL_CONFIG, (MPU9250_FSR_2G << 3)); Delay_Ms(1); //MPU9250 Set Accel DLPF data = MPU9250_SPIx_Read(MPU9250_SPIx_ADDR, MPU9250_ACCEL_CONFIG2); data |= MPU9250_ACCEL_DLPF_41HZ; Delay_Ms(1); MPU9250_SPIx_Write(MPU9250_SPIx_ADDR, MPU9250_ACCEL_CONFIG2, data); Delay_Ms(1); //MPU9250 Set Gyro DLPF MPU9250_SPIx_Write(MPU9250_SPIx_ADDR, MPU9250_CONFIG, MPU9250_GYRO_DLPF_41HZ); Delay_Ms(1); //MPU9250 Set SPI Mode state = MPU9250_SPIx_Read(MPU9250_SPIx_ADDR, MPU9250_USER_CTRL); Delay_Ms(1); MPU9250_SPIx_Write(MPU9250_SPIx_ADDR, MPU9250_USER_CTRL, state | MPU9250_I2C_IF_DIS); Delay_Ms(1); state = MPU9250_SPIx_Read(MPU9250_SPIx_ADDR, MPU9250_USER_CTRL); Delay_Ms(1); MPU9250_SPIx_Write(MPU9250_SPIx_ADDR, MPU9250_USER_CTRL, state | MPU9250_I2C_MST_EN); Delay_Ms(1); ////////////////////////////////////////////////////////////////////////// //AK8963 Setup //reset AK8963 MPU9250_AK8963_SPIx_Write(MPU9250_AK8963_I2C_ADDR, MPU9250_AK8963_CNTL2, MPU9250_AK8963_CNTL2_SRST); Delay_Ms(2); MPU9250_AK8963_SPIx_Write(MPU9250_AK8963_I2C_ADDR, MPU9250_AK8963_CNTL, MPU9250_AK8963_POWER_DOWN); Delay_Ms(1); MPU9250_AK8963_SPIx_Write(MPU9250_AK8963_I2C_ADDR, MPU9250_AK8963_CNTL, MPU9250_AK8963_FUSE_ROM_ACCESS); Delay_Ms(1); // //AK8963 get calibration data MPU9250_AK8963_SPIx_Reads(MPU9250_AK8963_I2C_ADDR, MPU9250_AK8963_ASAX, 3, response); //AK8963_SENSITIVITY_SCALE_FACTOR //AK8963_ASA[i++] = (s16)((data - 128.0f) / 256.0f + 1.0f) ; MPU9250_AK8963_ASA[0] = (s16)(response[0]) + 128; MPU9250_AK8963_ASA[1] = (s16)(response[1]) + 128; MPU9250_AK8963_ASA[2] = (s16)(response[2]) + 128; Delay_Ms(1); MPU9250_AK8963_SPIx_Write(MPU9250_AK8963_I2C_ADDR, MPU9250_AK8963_CNTL, MPU9250_AK8963_POWER_DOWN); Delay_Ms(1); // MPU9250_SPIx_Write(MPU9250_SPIx_ADDR, MPU9250_I2C_MST_CTRL, 0x5D); Delay_Ms(1); MPU9250_SPIx_Write(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV0_ADDR, MPU9250_AK8963_I2C_ADDR | MPU9250_I2C_READ); Delay_Ms(1); MPU9250_SPIx_Write(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV0_REG, MPU9250_AK8963_ST1); Delay_Ms(1); MPU9250_SPIx_Write(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV0_CTRL, 0x88); Delay_Ms(1); // MPU9250_AK8963_SPIx_Write(MPU9250_AK8963_I2C_ADDR, MPU9250_AK8963_CNTL, MPU9250_AK8963_CONTINUOUS_MEASUREMENT); Delay_Ms(1); // MPU9250_SPIx_Write(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_CTRL, 0x09); Delay_Ms(1); // MPU9250_SPIx_Write(MPU9250_SPIx_ADDR, MPU9250_I2C_MST_DELAY_CTRL, 0x81); Delay_Ms(100); } int MPU9250_SPIx_Write(u8 addr, u8 reg_addr, u8 data){ Chip_Select(pMPU9250); MPU9250_SPIx_SendByte(reg_addr); MPU9250_SPIx_SendByte(data); Chip_DeSelect(pMPU9250); return 0; } int MPU9250_SPIx_Writes(u8 addr, u8 reg_addr, u8 len, u8* data){ u32 i = 0; Chip_Select(pMPU9250); MPU9250_SPIx_SendByte(reg_addr); while(i < len){ MPU9250_SPIx_SendByte(data[i++]); } Chip_DeSelect(pMPU9250); return 0; } u8 MPU9250_SPIx_Read(u8 addr, u8 reg_addr) { u8 dummy = 0; u8 data = 0; Chip_Select(pMPU9250); MPU9250_SPIx_SendByte(0x80 | reg_addr); data = MPU9250_SPIx_SendByte(dummy); Chip_DeSelect(pMPU9250); return data; } int MPU9250_SPIx_Reads(u8 addr, u8 reg_addr, u8 len, u8* data){ u32 i = 0; u8 dummy = 0x00; Chip_Select(pMPU9250); MPU9250_SPIx_SendByte(MPU9250_I2C_READ | reg_addr); while(i < len){ data[i++] = MPU9250_SPIx_SendByte(dummy); } Chip_DeSelect(pMPU9250); return 0; } int MPU9250_AK8963_SPIx_Read(u8 akm_addr, u8 reg_addr, u8* data) { u8 status = 0; u32 timeout = 0; MPU9250_SPIx_Writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_REG, 1, ®_addr); Delay_Ms(1); reg_addr = akm_addr | MPU9250_I2C_READ; MPU9250_SPIx_Writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_ADDR, 1, ®_addr); Delay_Ms(1); reg_addr = MPU9250_I2C_SLV4_EN; MPU9250_SPIx_Writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_CTRL, 1, ®_addr); Delay_Ms(1); do { if (timeout++ > 50){ return -2; } MPU9250_SPIx_Reads(MPU9250_SPIx_ADDR, MPU9250_I2C_MST_STATUS, 1, &status); Delay_Ms(1); } while ((status & MPU9250_I2C_SLV4_DONE) == 0); MPU9250_SPIx_Reads(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_DI, 1, data); return 0; } int MPU9250_AK8963_SPIx_Reads(u8 akm_addr, u8 reg_addr, u8 len, u8* data){ u8 index = 0; u8 status = 0; u32 timeout = 0; u8 tmp = 0; tmp = akm_addr | MPU9250_I2C_READ; MPU9250_SPIx_Writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_ADDR, 1, &tmp); Delay_Ms(1); while(index < len){ tmp = reg_addr + index; MPU9250_SPIx_Writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_REG, 1, &tmp); Delay_Ms(1); tmp = MPU9250_I2C_SLV4_EN; MPU9250_SPIx_Writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_CTRL, 1, &tmp); Delay_Ms(1); do { if (timeout++ > 50){ return -2; } MPU9250_SPIx_Reads(MPU9250_SPIx_ADDR, MPU9250_I2C_MST_STATUS, 1, &status); Delay_Ms(2); } while ((status & MPU9250_I2C_SLV4_DONE) == 0); MPU9250_SPIx_Reads(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_DI, 1, data + index); Delay_Ms(1); index++; } return 0; } int MPU9250_AK8963_SPIx_Write(u8 akm_addr, u8 reg_addr, u8 data) { u32 timeout = 0; uint8_t status = 0; u8 tmp = 0; tmp = akm_addr; MPU9250_SPIx_Writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_ADDR, 1, &tmp); Delay_Ms(1); tmp = reg_addr; MPU9250_SPIx_Writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_REG, 1, &tmp); Delay_Ms(1); tmp = data; MPU9250_SPIx_Writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_DO, 1, &tmp); Delay_Ms(1); tmp = MPU9250_I2C_SLV4_EN; MPU9250_SPIx_Writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_CTRL, 1, &tmp); Delay_Ms(1); do { if (timeout++ > 50) return -2; MPU9250_SPIx_Reads(MPU9250_SPIx_ADDR, MPU9250_I2C_MST_STATUS, 1, &status); Delay_Ms(1); } while ((status & MPU9250_I2C_SLV4_DONE) == 0); if (status & MPU9250_I2C_SLV4_NACK) return -3; return 0; } int MPU9250_AK8963_SPIx_Writes(u8 akm_addr, u8 reg_addr, u8 len, u8* data) { u32 timeout = 0; uint8_t status = 0; u8 tmp = 0; u8 index = 0; tmp = akm_addr; MPU9250_SPIx_Writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_ADDR, 1, &tmp); Delay_Ms(1); while(index < len){ tmp = reg_addr + index; MPU9250_SPIx_Writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_REG, 1, &tmp); Delay_Ms(1); MPU9250_SPIx_Writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_DO, 1, data + index); Delay_Ms(1); tmp = MPU9250_I2C_SLV4_EN; MPU9250_SPIx_Writes(MPU9250_SPIx_ADDR, MPU9250_I2C_SLV4_CTRL, 1, &tmp); Delay_Ms(1); do { if (timeout++ > 50) return -2; MPU9250_SPIx_Reads(MPU9250_SPIx_ADDR, MPU9250_I2C_MST_STATUS, 1, &status); Delay_Ms(1); } while ((status & MPU9250_I2C_SLV4_DONE) == 0); if (status & MPU9250_I2C_SLV4_NACK) return -3; index++; } return 0; } ////////////////////////////////////////////////////////////////////////// // void MPU9250_Get9AxisRawData(short *accel, short * gyro, short * mag) { u8 data[22]; MPU9250_SPIx_Reads(MPU9250_SPIx_ADDR, MPU9250_ACCEL_XOUT_H, 22, data); accel[0] = (data[0] << 8) | data[1]; accel[1] = (data[2] << 8) | data[3]; accel[2] = (data[4] << 8) | data[5]; gyro[0] = (data[8] << 8) | data[9]; gyro[1] = (data[10] << 8) | data[11]; gyro[2] = (data[12] << 8) | data[13]; if (!(data[14] & MPU9250_AK8963_DATA_READY) || (data[14] & MPU9250_AK8963_DATA_OVERRUN)){ return; } if (data[21] & MPU9250_AK8963_OVERFLOW){ return; } mag[0] = (data[16] << 8) | data[15]; mag[1] = (data[18] << 8) | data[17]; mag[2] = (data[20] << 8) | data[19]; //ned x,y,z mag[0] = ((long)mag[0] * MPU9250_AK8963_ASA[0]) >> 8; mag[1] = ((long)mag[1] * MPU9250_AK8963_ASA[1]) >> 8; mag[2] = ((long)mag[2] * MPU9250_AK8963_ASA[2]) >> 8; } ////////////////////////////////////////////////////////////////////////// // void MPU9250_Get6AxisRawData(short *accel, short * gyro) { u8 data[14]; MPU9250_SPIx_Reads(MPU9250_SPIx_ADDR, MPU9250_ACCEL_XOUT_H, 14, data); accel[0] = (data[0] << 8) | data[1]; accel[1] = (data[2] << 8) | data[3]; accel[2] = (data[4] << 8) | data[5]; gyro[0] = (data[8] << 8) | data[9]; gyro[1] = (data[10] << 8) | data[11]; gyro[2] = (data[12] << 8) | data[13]; } ////////////////////////////////////////////////////////////////////////// // void MPU9250_Get3AxisAccelRawData(short * accel) { u8 data[6]; MPU9250_SPIx_Reads(MPU9250_SPIx_ADDR, MPU9250_ACCEL_XOUT_H, 6, data); accel[0] = (data[0] << 8) | data[1]; accel[1] = (data[2] << 8) | data[3]; accel[2] = (data[4] << 8) | data[5]; } ////////////////////////////////////////////////////////////////////////// // void MPU9250_Get3AxisGyroRawData(short * gyro) { u8 data[6]; MPU9250_SPIx_Reads(MPU9250_SPIx_ADDR, MPU9250_GYRO_XOUT_H, 6, data); gyro[0] = (data[0] << 8) | data[1]; gyro[1] = (data[2] << 8) | data[3]; gyro[2] = (data[4] << 8) | data[5]; } ////////////////////////////////////////////////////////////////////////// // void MPU9250_Get3AxisMagnetRawData(short *mag) { u8 data[8]; MPU9250_SPIx_Reads(MPU9250_SPIx_ADDR, MPU9250_EXT_SENS_DATA_00, 8, data); if (!(data[0] & MPU9250_AK8963_DATA_READY) || (data[0] & MPU9250_AK8963_DATA_OVERRUN)){ return; } if (data[7] & MPU9250_AK8963_OVERFLOW){ return; } mag[0] = (data[2] << 8) | data[1]; mag[1] = (data[4] << 8) | data[3]; mag[2] = (data[6] << 8) | data[5]; mag[0] = ((long)mag[0] * MPU9250_AK8963_ASA[0]) >> 8; mag[1] = ((long)mag[1] * MPU9250_AK8963_ASA[1]) >> 8; mag[2] = ((long)mag[2] * MPU9250_AK8963_ASA[2]) >> 8; } ////////////////////////////////////////////////////////////////////////// // void MPU9250_GetTemperatureRawData(long *temperature) { u8 data[2]; MPU9250_SPIx_Reads(MPU9250_SPIx_ADDR, MPU9250_TEMP_OUT_H, 2, data); temperature[0] = (((s16)data[0]) << 8) | data[1]; } static vu8 MPU9250_IsNewData = 0; int MPU9250_IsDataReady(void) { int isNewData = MPU9250_IsNewData; MPU9250_IsNewData = 0; return isNewData; } ////////////////////////////////////////////////////////////////////////// // void EXTI9_5_IRQHandler(void) { if(EXTI_GetITStatus(EXTI_Line8) != RESET){ EXTI_ClearITPendingBit(EXTI_Line8); MPU9250_IsNewData = 1; } } ================================================ FILE: Application/src/stm32f4_ms5611.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "stm32f4_ms5611.h" #include "stm32f4_spi.h" #include "stm32f4_delay.h" ////////////////////////////////////////////////////////////////////////// //basic SPI driver for ms5611 static SPI_Driver mMS5611 = { SPI1, RCC_APB2PeriphClockCmd, RCC_APB2Periph_SPI1, GPIOA, RCC_AHB1PeriphClockCmd, RCC_AHB1Periph_GPIOA, GPIOA, RCC_AHB1PeriphClockCmd, RCC_AHB1Periph_GPIOA, GPIO_Pin_4, GPIO_Pin_5, GPIO_Pin_6, GPIO_Pin_7, GPIO_PinSource5, GPIO_PinSource6, GPIO_PinSource7, #ifdef SPIx_USE_DMA #endif { SPI_Direction_2Lines_FullDuplex, SPI_Mode_Master, SPI_DataSize_8b, SPI_CPOL_High, SPI_CPHA_2Edge, SPI_NSS_Soft, SPI_BaudRatePrescaler_4, SPI_FirstBit_MSB, 7 }, GPIO_AF_SPI1 }; static SPI_Driver* pMS5611 = &mMS5611; __IO u16 MS5611_C1 = 0, MS5611_C2 = 0, MS5611_C3 = 0, MS5611_C4 = 0, MS5611_C5 = 0, MS5611_C6 = 0; void MS5611_Reset(SPI_Driver *MS5611) { // Chip Select low Chip_Select(MS5611); SPIx_SendByte(MS5611, MS5611_RESET); Delay_Ms(3); //2.8ms reload from datasheet // Chip Select high Chip_DeSelect(MS5611); } u16 MS5611_SPIx_ReadWord(SPI_Driver *MS5611, u8 addr) { u8 data[2] = {0}; u16 value = 0; // Chip Select low Chip_Select(MS5611); SPIx_SendByte(MS5611, addr); data[0] = SPIx_SendByte(MS5611, MS5611_READ); data[1] = SPIx_SendByte(MS5611, MS5611_READ); // Chip Select high Chip_DeSelect(MS5611); value = data[0] << 8 | data[1]; return value; } void MS5611_SPIx_ReadADC(SPI_Driver *MS5611, u8 osr, u32* value) { u8 data[3] = {0}; // Chip Select low Chip_Select(MS5611); SPIx_SendByte(MS5611, osr); // Chip Select high Chip_DeSelect(MS5611); Delay_Ms(1); // Chip Select low Chip_Select(MS5611); SPIx_SendByte(MS5611, MS5611_READ_ADC); data[0] = SPIx_SendByte(MS5611, MS5611_READ_ADC); data[1] = SPIx_SendByte(MS5611, MS5611_READ_ADC); data[2] = SPIx_SendByte(MS5611, MS5611_READ_ADC); // Chip Select high Chip_DeSelect(MS5611); *value = data[0] << 16 | data[1] << 8 | data[2]; } void MS5611_ReadPROM(SPI_Driver *MS5611) { // Read Calibration Data C1 MS5611_C1 = MS5611_SPIx_ReadWord(MS5611, MS5611_READ_PROM_C1); Delay_Ms(1); // Read Calibration Data C2 MS5611_C2 = MS5611_SPIx_ReadWord(MS5611, MS5611_READ_PROM_C2); Delay_Ms(1); // Read Calibration Data C3 MS5611_C3 = MS5611_SPIx_ReadWord(MS5611, MS5611_READ_PROM_C3); Delay_Ms(1); // Read Calibration Data C4 MS5611_C4 = MS5611_SPIx_ReadWord(MS5611, MS5611_READ_PROM_C4); Delay_Ms(1); // Read Calibration Data C5 MS5611_C5 = MS5611_SPIx_ReadWord(MS5611, MS5611_READ_PROM_C5); Delay_Ms(1); // Read Calibration Data C6 MS5611_C6 = MS5611_SPIx_ReadWord(MS5611, MS5611_READ_PROM_C6); Delay_Ms(1); } typedef uint64_t u64; typedef int64_t s64; void MS5611_GetTemperatureAndPressure(s32* T, s32 *P) { u32 D1, D2; s32 dT, TEMP, T2 = 0; s64 OFF, SENS, OFF2 = 0, SENS2 = 0; s32 lowTEMP, verylowTemp; MS5611_SPIx_ReadADC(pMS5611, D1_OSR_256, &D1); MS5611_SPIx_ReadADC(pMS5611, D2_OSR_256, &D2); ////////////////////////////////////////////////////////////////////////// // dT = D2 - ((u32)MS5611_C5 << 8); TEMP = 2000 + (((s64)dT * MS5611_C6) >> 23); OFF = ((u32)MS5611_C2 << 16) + ((MS5611_C4 * (s64)dT) >> 7); SENS = ((u32)MS5611_C1 << 15) + ((MS5611_C3 * (s64)dT) >> 8); // *T = TEMP; ////////////////////////////////////////////////////////////////////////// //second order temperature compensation if(TEMP < 2000){ T2 = (s64)((s64)dT * (s64)dT) >> 31; lowTEMP = TEMP - 2000; lowTEMP *= lowTEMP; OFF2 = (5 * lowTEMP) >> 1; SENS2 = (5 * lowTEMP) >> 2; if(TEMP < -1500){ verylowTemp = TEMP + 1500; verylowTemp *= verylowTemp; OFF2 = OFF2 + 7 * verylowTemp; SENS2 = SENS2 + ((11 * verylowTemp) >> 1); } // OFF = OFF - OFF2; SENS = SENS - SENS2; *T = TEMP - T2; } ////////////////////////////////////////////////////////////////////////// *P = ((((u64)D1 * SENS) >> 21) - OFF) >> 15; } void MS5611_Cal(s32* T, s32 *P) { u32 D1, D2; s32 dT, TEMP, T2 = 0; s64 OFF, SENS, OFF2 = 0, SENS2 = 0; s32 lowTEMP, verylowTemp; MS5611_SPIx_ReadADC(pMS5611, D1_OSR_256, &D1); MS5611_SPIx_ReadADC(pMS5611, D2_OSR_256, &D2); ////////////////////////////////////////////////////////////////////////// // dT = D2 - ((u32)MS5611_C5 << 8); TEMP = 2000 + (((s64)dT * MS5611_C6) >> 23); OFF = ((u32)MS5611_C2 << 16) + ((MS5611_C4 * (s64)dT) >> 7); SENS = ((u32)MS5611_C1 << 15) + ((MS5611_C3 * (s64)dT) >> 8); // *T = TEMP; ////////////////////////////////////////////////////////////////////////// //second order temperature compensation if(TEMP < 2000){ T2 = (s64)((s64)dT * (s64)dT) >> 31; lowTEMP = TEMP - 2000; lowTEMP *= lowTEMP; OFF2 = (5 * lowTEMP) >> 1; SENS2 = (5 * lowTEMP) >> 2; if(TEMP < -1500){ verylowTemp = TEMP + 1500; verylowTemp *= verylowTemp; OFF2 = OFF2 + 7 * verylowTemp; SENS2 = SENS2 + ((11 * verylowTemp) >> 1); } // OFF = OFF - OFF2; SENS = SENS - SENS2; *T = TEMP - T2; } ////////////////////////////////////////////////////////////////////////// *P = ((((u64)D1 * SENS) >> 21) - OFF) >> 15; } u8 MS5611_CRC4(u32 n_prom[]) { int cnt; // simple counter u32 n_rem; // crc reminder u32 crc_read; // original value of the crc u8 n_bit; n_rem = 0x00; crc_read = n_prom[7]; //save read CRC n_prom[7]=(0xFF00 & (n_prom[7])); //CRC byte is replaced by 0 for(cnt = 0; cnt < 16; cnt++){ // operation is performed on bytes // choose LSB or MSB if((cnt & 0x01) == 1){ n_rem ^= (u16)((n_prom[cnt >> 1]) & 0x00FF); } else{ n_rem ^= (u16)(n_prom[cnt >> 1] >> 8); } for(n_bit = 8; n_bit > 0; n_bit--){ if(n_rem & (0x8000)){ n_rem = (n_rem << 1) ^ 0x3000; } else{ n_rem = (n_rem << 1); } } } n_rem = (0x000F & (n_rem >> 12)); // // final 4-bit reminder is CRC code n_prom[7] =crc_read; // restore the crc_read to its original place return (n_rem ^ 0x00); } void MS5611_Init(void) { SPIx_Init(pMS5611); MS5611_Reset(pMS5611); Delay_Ms(1); MS5611_ReadPROM(pMS5611); Delay_Ms(1); } ================================================ FILE: Application/src/stm32f4_rcc.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "stm32f4_rcc.h" void RCC_SystemCoreClockUpdate(PLL_PARAMS params) { //reset RCC RCC_DeInit(); //start HSI, wait until up RCC_HSICmd(ENABLE); while(RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET); //switch the system clock to HSI RCC_SYSCLKConfig(RCC_SYSCLKSource_HSI); while(RCC_GetSYSCLKSource() != 0x00); //stop PLL, wait until down RCC_PLLCmd(DISABLE); while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == SET); //start HSE, wait until up RCC_HSEConfig(RCC_HSE_ON); while(RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET); //change PLL params; RCC_HCLKConfig(RCC_SYSCLK_Div1); RCC_PCLK1Config(RCC_HCLK_Div4); RCC_PCLK2Config(RCC_HCLK_Div2); RCC_PLLConfig(RCC_PLLSource_HSE, params.PLLM, params.PLLN, params.PLLP, params.PLLQ); //start PLL, wait until up RCC_PLLCmd(ENABLE); while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET); //switch system clock to PLL, wait until switched RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); while(RCC_GetSYSCLKSource() != 0x08); //update SystemCoreClockUpdate(); } ================================================ FILE: Application/src/stm32f4_serial.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "stm32f4_serial.h" #include "stm32f4_usart.h" #include "Memory.h" #ifdef USARTx_USE_DMA static uint8_t DMA_TxBuffer[DEFAULT_BUFFERSIZE]; static uint8_t DMA_RxBuffer[DEFAULT_BUFFERSIZE]; //static uint8_t USARTx_Rx_Buffer[DEFAULT_BUFFERSIZE]; #endif static USART_Driver Serial = { USART1, RCC_APB2PeriphClockCmd, RCC_APB2Periph_USART1, DEFAULT_BAUDRATE, GPIOA, RCC_AHB1PeriphClockCmd , RCC_AHB1Periph_GPIOA, GPIO_Pin_9, GPIO_PinSource9, GPIOA, RCC_AHB1PeriphClockCmd , RCC_AHB1Periph_GPIOA, GPIO_Pin_10, GPIO_PinSource10, #ifdef USARTx_USE_DMA { USART1_IRQn, 1, 2, ENABLE }, { DMA2_Stream7_IRQn, 1, 3, ENABLE }, RCC_AHB1PeriphClockCmd, RCC_AHB1Periph_DMA2, DEFAULT_BUFFERSIZE, DMA_TxBuffer, DMA2_Stream7, DMA_Channel_4, DEFAULT_BUFFERSIZE, DMA_RxBuffer, DMA2_Stream5, DMA_Channel_4, #endif GPIO_AF_USART1 }; static USART_Driver* pSerial = &Serial; void Serial_Init(void) { USARTx_Init(pSerial); } void Serial_SendByte(uint8_t byte) { USARTx_SendByte(pSerial, byte); } void Serial_SendBytes(uint8_t* buffer, uint8_t length) { #ifdef USARTx_USE_DMA USARTx_DMA_SendBytes(pSerial, buffer, length); #else USARTx_SendBytes(pSerial, buffer, length); #endif } void Serial_Upload(short accel[3], short gyro[3], short compass[3], long quat[4], long temperature, long pressure) { //must 4-bytes alignment uint8_t out[PACKET_LENGTH]; short* sDest = (short*)out; long* lDest; //uint8_t count = 0; //memset(out, 0, PACKET_LENGTH); //out[0] = 0x55; //out[1] = 0xAA; *sDest++ = 0xAA55; //accel /* out[4] = (uint8_t)accel[0]; out[5] = (uint8_t)(accel[0] >> 8); out[6] = (uint8_t)accel[1]; out[7] = (uint8_t)(accel[1] >> 8); out[8] = (uint8_t)accel[2]; out[9] = (uint8_t)(accel[2] >> 8); */ *sDest++ = accel[0]; *sDest++ = accel[1]; *sDest++ = accel[2]; //gyro /* out[10] = (uint8_t)gyro[0]; out[11] = (uint8_t)(gyro[0] >> 8); out[12] = (uint8_t)gyro[1]; out[13] = (uint8_t)(gyro[1] >> 8); out[14] = (uint8_t)gyro[2]; out[15] = (uint8_t)(gyro[2] >> 8); */ *sDest++ = gyro[0]; *sDest++ = gyro[1]; *sDest++ = gyro[2]; //compass /* out[16] = (uint8_t)compass[0]; out[17] = (uint8_t)(compass[0] >> 8); out[18] = (uint8_t)compass[1]; out[19] = (uint8_t)(compass[1] >> 8); out[20] = (uint8_t)compass[2]; out[21] = (uint8_t)(compass[2] >> 8); */ *sDest++ = compass[0]; *sDest++ = compass[1]; *sDest++ = compass[2]; //quat /* out[22] = (uint8_t)quat[0]; out[23] = (uint8_t)(quat[0] >> 8); out[24] = (uint8_t)(quat[0] >> 16); out[25] = (uint8_t)(quat[0] >> 24); out[26] = (uint8_t)quat[1]; out[27] = (uint8_t)(quat[1] >> 8); out[28] = (uint8_t)(quat[1] >> 16); out[29] = (uint8_t)(quat[1] >> 24); out[30] = (uint8_t)quat[2]; out[31] = (uint8_t)(quat[2] >> 8); out[32] = (uint8_t)(quat[2] >> 16); out[33] = (uint8_t)(quat[2] >> 24); out[34] = (uint8_t)quat[3]; out[35] = (uint8_t)(quat[3] >> 8); out[36] = (uint8_t)(quat[3] >> 16); out[37] = (uint8_t)(quat[3] >> 24); */ lDest = (long*)sDest; *lDest++ = quat[0]; *lDest++ = quat[1]; *lDest++ = quat[2]; *lDest++ = quat[3]; //tempperature /* out[38] = (uint8_t)temperature; out[39] = (uint8_t)(temperature >> 8); out[40] = (uint8_t)(temperature >> 16); out[41] = (uint8_t)(temperature >> 24); */ *lDest++ = temperature; //pressure /* out[42] = (uint8_t)pressure; out[43] = (uint8_t)(pressure >> 8); out[44] = (uint8_t)(pressure >> 16); out[45] = (uint8_t)(pressure >> 24); */ *lDest++ = pressure; //out[44] = '\r'; //out[45] = '\n'; sDest = (short*)lDest; *sDest = 0x0A0D; Serial_SendBytes((uint8_t*)out, PACKET_LENGTH); } #ifdef USARTx_USE_DMA //according to the hardware //such as using usart1, DMA2_Stream7 for tx, DMA2_Stream5 for rx void USART1_IRQHandler(void) { //u16 DATA_LEN = 0; if(USART_GetITStatus(USART1, USART_IT_TC) != RESET){ USART_ITConfig(USART1, USART_IT_TC, DISABLE); } else if(USART_GetITStatus(USART1, USART_IT_IDLE) != RESET){ USART1->SR; USART1->DR; DMA_Cmd(DMA2_Stream5, DISABLE); DMA_ClearFlag(DMA2_Stream5, DMA_FLAG_TCIF5); //DATA_LEN = DEFAULT_BUFFERSIZE - DMA_GetCurrDataCounter(DMA2_Stream5); //FastMemCpy(USARTx_Rx_Buffer, DMA_RxBuffer, DATA_LEN); DMA_SetCurrDataCounter(DMA2_Stream5, DEFAULT_BUFFERSIZE); DMA_Cmd(DMA2_Stream5, ENABLE); } } //TX void DMA2_Stream7_IRQHandler(void) { if(DMA_GetITStatus(DMA2_Stream7, DMA_IT_TCIF7)){ DMA_ClearITPendingBit(DMA2_Stream7, DMA_IT_TCIF7); DMA_Cmd(DMA2_Stream7, DISABLE); USART_ITConfig(USART1, USART_IT_TC, ENABLE); } } #endif ================================================ FILE: Application/src/stm32f4_string.c ================================================ #include "stm32f4_string.h" //make sure 4-bytes aligned __asm void FastMemCpy(uint8_t* dest, uint8_t* src, uint16_t size) { push {r4-r11}; lsr r3, r2, #5; 32 bytes cmp r3, #0; beq notenough_32; and r2, r2, #31; left bytes loop_32 ldmia r1!, {r4-r11}; stmia r0!, {r4-r11}; subs r3, r3, #1; bne loop_32; notenough_32 lsr r3, r2, #4; 16 bytes cmp r3, #0; beq notenough_16; and r2, r2, #15; left bytes loop_16 ldmia r1!, {r4-r7}; stmia r0!, {r4-r7}; subs r3, r3, #1; bne loop_16; notenough_16 lsr r3, r2, #3; 8 bytes cmp r3, #0; beq notenough_8; and r2, r2, #7; left bytes loop_8 ldmia r1!, {r4-r5}; stmia r0!, {r4-r5}; subs r3, r3, #1; bne loop_8; notenough_8 lsr r3, r2, #2; 4 bytes cmp r3, #0; beq notenough_4; and r2, r2, #3; left bytes loop_4 ldmia r1!, {r4}; stmia r0!, {r4}; subs r3, r3, #1; bne loop_4; notenough_4 cmp r2, #0; beq exit loop_1 subs r2, r2, #1; ldrb r3, [r1, r2] strb r3, [r0, r2] cmp r2, #0 bne loop_1; exit pop {r4-r11} bx lr } ================================================ FILE: Application/src/stm32f4_ublox.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "stm32f4_ublox.h" #include "stm32f4_usart.h" // #include "Map.h" #include "Memory.h" #include "Fifo.h" //ungly implement: the max size of the data //max(sizeof(nmeaGPGGA), sizeof(nmeaGPGSA), sizeof(nmeaGPRMC), sizeof(nmeaGPVTG)) #define UBLOX_MAX_MESSAGESIZE sizeof(nmeaGPGGA) ////////////////////////////////////////////////////////////////////////// //UBlox Driver #ifdef USARTx_USE_DMA static uint8_t DMA_TxBuffer[UBLOX_DEFAULT_TX_BUFFERSIZE]; static uint8_t DMA_RxBuffer[UBLOX_DEFAULT_RX_BUFFERSIZE]; static uint8_t USARTx_Rx_Buffer[UBLOX_DEFAULT_RX_BUFFERSIZE]; #endif static USART_Driver Ublox = { UART4, RCC_APB1PeriphClockCmd, RCC_APB1Periph_UART4, UBLOX_DEFAULT_BAUDRATE, GPIOC, RCC_AHB1PeriphClockCmd , RCC_AHB1Periph_GPIOC, GPIO_Pin_10, GPIO_PinSource10, GPIOC, RCC_AHB1PeriphClockCmd , RCC_AHB1Periph_GPIOC, GPIO_Pin_11, GPIO_PinSource11, #ifdef USARTx_USE_DMA { UART4_IRQn, 1, 2, ENABLE }, { DMA1_Stream4_IRQn, 1, 3, ENABLE }, RCC_AHB1PeriphClockCmd, RCC_AHB1Periph_DMA2, UBLOX_DEFAULT_TX_BUFFERSIZE, DMA_TxBuffer, DMA1_Stream4, DMA_Channel_4, UBLOX_DEFAULT_RX_BUFFERSIZE, DMA_RxBuffer, DMA1_Stream2, DMA_Channel_4, #endif GPIO_AF_UART4 }; // static USART_Driver* pUblox = &Ublox; ////////////////////////////////////////////////////////////////////////// //Fifo static Fifo UbloxFifo; static Fifo* pUbloxFifo = &UbloxFifo; ////////////////////////////////////////////////////////////////////////// //Ublox GPS Parser static s8 _ParserBuff[UBLOX_DEFAULT_PARSER_MAXSIZE]; static Ublox_ParserBuff ParserBuffer = {_ParserBuff, UBLOX_DEFAULT_PARSER_MAXSIZE, UBLOX_DEFAULT_PARSER_MAXSIZE, 0}; static s8 Message[UBLOX_MAX_MESSAGESIZE]; static nmeaINFO uBloxInfo = {0}; static Map UbloxMap = {0}; static Map *pUbloxMap = &UbloxMap; ////////////////////////////////////////////////////////////////////////// void Ublox_Init(void) { Fifo_Init(pUbloxFifo, USARTx_Rx_Buffer, UBLOX_DEFAULT_RX_BUFFERSIZE); USARTx_Init(pUblox); //must init with local two reference points including lat, lon and the length //betweeb two reference points //Map_Init(pUbloxMap, first_lat, first_lon, second_lat, second_lon, length); } void Ublox_SendBytes(uint8_t* buffer, uint8_t length) { #ifdef USARTx_USE_DMA USARTx_DMA_SendBytes(pUblox, buffer, length); #else USARTx_SendBytes(pUblox, buffer, length); #endif } void Ublox_ParserMessage() { u16 useSize; ////////////////////////////////////////////////////////////////////////// //read fully UBLOX_DEFAULT_PARSER_MAXSIZE from fifo useSize = Fifo_Get(pUbloxFifo, (u8*)(ParserBuffer.Data + ParserBuffer.Left), ParserBuffer.Need); ParserBuffer.Need -= useSize; ParserBuffer.Left += useSize; if(0 == ParserBuffer.Need){ useSize = NEMA_Parser(ParserBuffer.Data, UBLOX_DEFAULT_PARSER_MAXSIZE); ParserBuffer.Left = UBLOX_DEFAULT_PARSER_MAXSIZE - useSize; MemMove((u8*)ParserBuffer.Data, (u8*)(ParserBuffer.Data + useSize), ParserBuffer.Left); ParserBuffer.Need = useSize; } } void Ublox_GetMessage() { s32 iMessageType; s16 ret = 0; Ublox_ParserMessage(); ret = NEMA_GetMessage(Message, &iMessageType); if(ret <= 0){ return; } switch(iMessageType){ case GPNON: break; case GPGGA: uBloxInfo.lat = NMEA_Convert2Degrees(((PnmeaGPGGA)Message)->lat); uBloxInfo.lon = NMEA_Convert2Degrees(((PnmeaGPGGA)Message)->lon); uBloxInfo.alt = ((PnmeaGPGGA)Message)->alt; break; case GPGSA: break; case GPRMC: uBloxInfo.lat = NMEA_Convert2Degrees(((PnmeaGPRMC)Message)->lat); uBloxInfo.lon = NMEA_Convert2Degrees(((PnmeaGPRMC)Message)->lon); uBloxInfo.spd = ((PnmeaGPRMC)Message)->spd; uBloxInfo.cog = ((PnmeaGPRMC)Message)->cog; break; case GPVTG: break; } } void Ublox_GetPostion(double *x, double *y, double *z) { Map_GetXY(pUbloxMap, uBloxInfo.lat, uBloxInfo.lon, x, y); *z = uBloxInfo.alt; } #ifdef USARTx_USE_DMA //according to the hardware //such as using uart4, DMA1_Stream4 for tx, DMA1_Stream2 for rx void UART4_IRQHandler(void) { u16 DATA_LEN = 0; if(USART_GetITStatus(UART4, USART_IT_TC) != RESET){ USART_ITConfig(UART4, USART_IT_TC, DISABLE); } else if(USART_GetITStatus(UART4, USART_IT_IDLE) != RESET){ UART4->SR; UART4->DR; DMA_Cmd(DMA1_Stream2, DISABLE); DMA_ClearFlag(DMA1_Stream2, DMA_FLAG_TCIF2); DATA_LEN = UBLOX_DEFAULT_RX_BUFFERSIZE - DMA_GetCurrDataCounter(DMA1_Stream2); ////////////////////////////////////////////////////////////////////////// //put DMA data to FIFO Fifo_Put(pUbloxFifo, DMA_RxBuffer, DATA_LEN); ////////////////////////////////////////////////////////////////////////// DMA_SetCurrDataCounter(DMA1_Stream2, DEFAULT_BUFFERSIZE); DMA_Cmd(DMA1_Stream2, ENABLE); } } //TX void DMA1_Stream4_IRQHandler(void) { if(DMA_GetITStatus(DMA1_Stream4, DMA_IT_TCIF4)){ DMA_ClearITPendingBit(DMA1_Stream4, DMA_IT_TCIF4); DMA_Cmd(DMA1_Stream4, DISABLE); USART_ITConfig(UART4, USART_IT_TC, ENABLE); } } #endif ================================================ FILE: Application/src/system_stm32f4xx.c ================================================ /** ****************************************************************************** * @file system_stm32f4xx.c * @author MCD Application Team * @version V1.1.0 * @date 21-August-2014 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * This file contains the system clock configuration for STM32F4xx devices, * and is generated by the clock configuration tool * stm32f4xx_Clock_Configuration_V1.1.0.xls * * 1. This file provides two functions and one global variable to be called from * user application: * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier * and Divider factors, AHB/APBx prescalers and Flash settings), * depending on the configuration made in the clock xls tool. * This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32f4xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * by the user application to setup the SysTick * timer or configure other parameters. * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. * * 2. After each device reset the HSI (16 MHz) is used as system clock source. * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to * configure the system clock before to branch to main program. * * 3. If the system clock source selected by user fails to startup, the SystemInit() * function will do nothing and HSI still used as system clock source. User can * add some code to deal with this issue inside the SetSysClock() function. * * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or * through PLL, and you are using different crystal you have to adapt the HSE * value to your own configuration. * * 5. This file configures the system clock as follows: *============================================================================= *============================================================================= * Supported STM32F40xx/41xx/427x/437x devices *----------------------------------------------------------------------------- * System Clock source | PLL (HSE) *----------------------------------------------------------------------------- * SYSCLK(Hz) | 168000000 *----------------------------------------------------------------------------- * HCLK(Hz) | 168000000 *----------------------------------------------------------------------------- * AHB Prescaler | 1 *----------------------------------------------------------------------------- * APB1 Prescaler | 4 *----------------------------------------------------------------------------- * APB2 Prescaler | 2 *----------------------------------------------------------------------------- * HSE Frequency(Hz) | 12000000 *----------------------------------------------------------------------------- * PLL_M | 12 *----------------------------------------------------------------------------- * PLL_N | 336 *----------------------------------------------------------------------------- * PLL_P | 2 *----------------------------------------------------------------------------- * PLL_Q | 7 *----------------------------------------------------------------------------- * PLLI2S_N | NA *----------------------------------------------------------------------------- * PLLI2S_R | NA *----------------------------------------------------------------------------- * I2S input clock | NA *----------------------------------------------------------------------------- * VDD(V) | 3.3 *----------------------------------------------------------------------------- * Main regulator output voltage | Scale1 mode *----------------------------------------------------------------------------- * Flash Latency(WS) | 5 *----------------------------------------------------------------------------- * Prefetch Buffer | OFF *----------------------------------------------------------------------------- * Instruction cache | ON *----------------------------------------------------------------------------- * Data cache | ON *----------------------------------------------------------------------------- * Require 48MHz for USB OTG FS, | Enabled * SDIO and RNG clock | *----------------------------------------------------------------------------- *============================================================================= ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f4xx_system * @{ */ /** @addtogroup STM32F4xx_System_Private_Includes * @{ */ #include "stm32f4xx.h" /** * @} */ /** @addtogroup STM32F4xx_System_Private_TypesDefinitions * @{ */ /** * @} */ /** @addtogroup STM32F4xx_System_Private_Defines * @{ */ /************************* Miscellaneous Configuration ************************/ /*!< Uncomment the following line if you need to use external SRAM mounted on STM324xG_EVAL/STM324x7I_EVAL board as data memory */ /* #define DATA_IN_ExtSRAM */ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ /******************************************************************************/ /************************* PLL Parameters *************************************/ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ #define PLL_M 12 #define PLL_N 336 /* SYSCLK = PLL_VCO / PLL_P */ #define PLL_P 2 /* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ #define PLL_Q 7 /******************************************************************************/ /** * @} */ /** @addtogroup STM32F4xx_System_Private_Macros * @{ */ /** * @} */ /** @addtogroup STM32F4xx_System_Private_Variables * @{ */ uint32_t SystemCoreClock = 168000000; __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} */ /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes * @{ */ static void SetSysClock(void); #ifdef DATA_IN_ExtSRAM static void SystemInit_ExtMemCtl(void); #endif /* DATA_IN_ExtSRAM */ /** * @} */ /** @addtogroup STM32F4xx_System_Private_Functions * @{ */ /** * @brief Setup the microcontroller system * Initialize the Embedded Flash Interface, the PLL and update the * SystemFrequency variable. * @param None * @retval None */ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; /* Reset CFGR register */ RCC->CFGR = 0x00000000; /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFFF; /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x24003010; /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; /* Disable all interrupts */ RCC->CIR = 0x00000000; #ifdef DATA_IN_ExtSRAM SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM */ /* Configure the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings ----------------------------------*/ SetSysClock(); /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ #endif } /** * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration * based on this variable will be incorrect. * * @note - The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) * * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. * * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value * 16 MHz) but the real value may vary depending on the variations * in voltage and temperature. * * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value * 25 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. * * - The result of this function could be not correct when using fractional * value for HSE crystal. * * @param None * @retval None */ void SystemCoreClockUpdate(void) { uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { case 0x00: /* HSI used as system clock source */ SystemCoreClock = HSI_VALUE; break; case 0x04: /* HSE used as system clock source */ SystemCoreClock = HSE_VALUE; break; case 0x08: /* PLL used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N SYSCLK = PLL_VCO / PLL_P */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; if (pllsource != 0) { /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } else { /* HSI used as PLL clock source */ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; SystemCoreClock = pllvco/pllp; break; default: SystemCoreClock = HSI_VALUE; break; } /* Compute HCLK frequency --------------------------------------------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; /* HCLK frequency */ SystemCoreClock >>= tmp; } /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings * @Note This function should be called only once the RCC clock configuration * is reset to the default reset state (done in SystemInit() function). * @param None * @retval None */ static void SetSysClock(void) { /******************************************************************************/ /* PLL (clocked by HSE) used as System clock source */ /******************************************************************************/ __IO uint32_t StartUpCounter = 0, HSEStatus = 0; /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CR & RCC_CR_HSERDY) != RESET) { HSEStatus = (uint32_t)0x01; } else { HSEStatus = (uint32_t)0x00; } if (HSEStatus == (uint32_t)0x01) { /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */ RCC->APB1ENR |= RCC_APB1ENR_PWREN; PWR->CR |= PWR_CR_VOS; /* HCLK = SYSCLK / 1*/ RCC->CFGR |= RCC_CFGR_HPRE_DIV1; /* PCLK2 = HCLK / 2*/ RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; /* PCLK1 = HCLK / 4*/ RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; /* Configure the main PLL */ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); /* Enable the main PLL */ RCC->CR |= RCC_CR_PLLON; /* Wait till the main PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) { } /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; /* Select the main PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= RCC_CFGR_SW_PLL; /* Wait till the main PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } /** * @brief Setup the external memory controller. Called in startup_stm32f4xx.s * before jump to __main * @param None * @retval None */ #ifdef DATA_IN_ExtSRAM /** * @brief Setup the external memory controller. * Called in startup_stm32f4xx.s before jump to main. * This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I_EVAL board * This SRAM will be used as program data memory (including heap and stack). * @param None * @retval None */ void SystemInit_ExtMemCtl(void) { /*-- GPIOs Configuration -----------------------------------------------------*/ /* +-------------------+--------------------+------------------+------------------+ + SRAM pins assignment + +-------------------+--------------------+------------------+------------------+ | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | | PD4 <-> FSMC_NOE | PE2 <-> FSMC_A23 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | | PD5 <-> FSMC_NWE | PE3 <-> FSMC_A19 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | | PD8 <-> FSMC_D13 | PE4 <-> FSMC_A20 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | | PD9 <-> FSMC_D14 | PE5 <-> FSMC_A21 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | | PD10 <-> FSMC_D15 | PE6 <-> FSMC_A22 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | | PD11 <-> FSMC_A16 | PE7 <-> FSMC_D4 | PF13 <-> FSMC_A7 |------------------+ | PD12 <-> FSMC_A17 | PE8 <-> FSMC_D5 | PF14 <-> FSMC_A8 | | PD13 <-> FSMC_A18 | PE9 <-> FSMC_D6 | PF15 <-> FSMC_A9 | | PD14 <-> FSMC_D0 | PE10 <-> FSMC_D7 |------------------+ | PD15 <-> FSMC_D1 | PE11 <-> FSMC_D8 | +-------------------| PE12 <-> FSMC_D9 | | PE13 <-> FSMC_D10 | | PE14 <-> FSMC_D11 | | PE15 <-> FSMC_D12 | +--------------------+ */ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ RCC->AHB1ENR |= 0x00000078; /* Connect PDx pins to FSMC Alternate function */ GPIOD->AFR[0] = 0x00cc00cc; GPIOD->AFR[1] = 0xcccccccc; /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xaaaa0a0a; /* Configure PDx pins speed to 100 MHz */ GPIOD->OSPEEDR = 0xffff0f0f; /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FSMC Alternate function */ GPIOE->AFR[0] = 0xcccccccc; GPIOE->AFR[1] = 0xcccccccc; /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xaaaaaaaa; /* Configure PEx pins speed to 100 MHz */ GPIOE->OSPEEDR = 0xffffffff; /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FSMC Alternate function */ GPIOF->AFR[0] = 0x00cccccc; GPIOF->AFR[1] = 0xcccc0000; /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xaa000aaa; /* Configure PFx pins speed to 100 MHz */ GPIOF->OSPEEDR = 0xff000fff; /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FSMC Alternate function */ GPIOG->AFR[0] = 0x00cccccc; GPIOG->AFR[1] = 0x000000c0; /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0x00080aaa; /* Configure PGx pins speed to 100 MHz */ GPIOG->OSPEEDR = 0x000c0fff; /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; /*-- FSMC Configuration ------------------------------------------------------*/ /* Enable the FSMC interface clock */ RCC->AHB3ENR |= 0x00000001; /* Configure and enable Bank1_SRAM2 */ FSMC_Bank1->BTCR[2] = 0x00001011; FSMC_Bank1->BTCR[3] = 0x00000201; FSMC_Bank1E->BWTR[2] = 0x0fffffff; /* Bank1_SRAM2 is configured as follow: p.FSMC_AddressSetupTime = 1; p.FSMC_AddressHoldTime = 0; p.FSMC_DataSetupTime = 2; p.FSMC_BusTurnAroundDuration = 0; p.FSMC_CLKDivision = 0; p.FSMC_DataLatency = 0; p.FSMC_AccessMode = FSMC_AccessMode_A; FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; */ } #endif /* DATA_IN_ExtSRAM */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Common/inc/Memory.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _MEMORY_H_ #define _MEMORY_H_ #include "stm32f4xx.h" void FastMemCpy(u8* dest, u8* src, u16 size); void *MemCpy(u8* dest, u8* src, u16 size); void *MemMove(u8* dest, u8* src, u16 size); s32 MemCmp(u8 *dest, u8 *src, u16 n); #endif ================================================ FILE: Common/src/Memory.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "Memory.h" //make sure 4-bytes aligned __asm void FastMemCpy(u8* dest, u8* src, u16 size) { movs r3, r2, asr #5 ;any chunks of 8 words? beq copywords ;jump if no 8-word chunks and r2, r2, #0x1f ;subtract chunks from size stmfd sp!, {r4-r11} ;save working registers octcopy ldmia r1!, {r4-r11}; ;load 8 words from src stmia r0!, {r4-r11}; ;write 8 words to dest subs r3, r3, #1; ;more 8-word chunks to move? bne octcopy; ;loop if more chunks ldmfd sp!, {r4-r11} ;restore working registers copywords movs r3, r2, asr #2 ;any more whole words to move? beq copybytes ;jump if no more whole words stmdb sp!, {lr} ;push return address wordcopy ldr lr, [r1], #4 ;read next word from src str lr, [r0], #4 ;write next word to dest subs r3, r3, #1 ;decrement word count bne wordcopy ;loop while more words to move ldmia sp!, {lr} ;pop return address copybytes ands r2, r2, #3 ;any last bytes to transfer? beq done ;return if already done bytecopy ldrb r3, [r1], #1 ;read byte from src strb r3, [r0], #1 ;write byte to dest subs r2, r2, #1 ;--size (decrement loop count) bne bytecopy ;loop if more bytes to move done bx lr; ;return to caller } __asm void *MemCpy(u8* dest, u8* src, u16 size) { teq r2, #0 ;is arg n == 0 ? bne start ;if n == 0, return bx lr; start stmdb sp!, {lr} ;push return address mov r12, r0 ;copy pointer p1 cmp r2, #0x8 ;is string long or short? ble ByteSerial ;jump if long string sub r3, r0, r1 ;compare pointers p1, p2 tst r3, #3 ;strings aligned same? bne ByteSerial ;jump if strings not aligned ;Both strings are similarly aligned WRT word boundaries. ;At least a portion of the data can be copied an entire ;word at a time, which is faster than copying bytes. WordSerial ands r3, r0, #3 ;check byte alignment beq WordAligned ;jump if p1, p2 word-aligned rsb r3, r3, #4 ;m = no. of odd initial bytes sub r2, r2, r3 ;n = n - m ;If the two strings do not begin on word boundaries, begin ;by copying the odd bytes that precede the first full word. PreLoop ldrb lr, [r1], #1 ;read byte from src subs r3, r3, #1 ;--m (decrement loop count) strb lr, [r12], #1 ;write byte to dest bne PreLoop ;loop if more bytes to move WordAligned movs r3, r2, asr #5 ;any chunks of 8 words? beq OctsDone ;jump if no 8-word chunks and r2, r2, #0x1f ;subtract chunks from size stmdb sp!, {r4-r10} ;save registers on stack ;The strings are long enough that we can transfer at least ;some portion of the data in 8-word chunks. OctLoop ldmia r1!, {r4-r10, lr} ;load 8 words from src subs r3, r3, #1 ;more 8-word chunks to move? stmia r12!, {r4-r10, lr} ;write 8 words to dest bne OctLoop ;loop if more chunks ldmia sp!,{r4-r10} ;restore registers from stack OctsDone movs r3,r2,asr #2 ;any more whole words to move? beq WordsDone ;jump if no more whole words ;Copy as much of the remaining data as possible one word at a time. WordLoop2 ldr lr, [r1], #4 ;read next word from src subs r3, r3, #1 ;decrement word count str lr, [r12], #4 ;write next word to dest bne WordLoop2 ;loop while more words to move WordsDone ands r2,r2,#3 ;any last bytes to transfer? ldmeqia sp!,{pc} ;return if already done ;The two strings do not end on word boundaries. ;Copy the remaining data one byte at a time. ByteSerial ldrb lr,[r1],#1 ;read byte from src subs r2,r2,#1 ;--size (decrement loop count) strb lr,[r12],#1 ;write byte to dest bne ByteSerial ;loop if more bytes to move ldmia sp!,{pc} ;return to caller } __asm void *MemMove(u8* dest, u8* src, u16 size) { cmp r0,r1 ;is d > s ? bls MemCpy ;jump to MemCpy if d <= s ;Need to copy backwards, starting at tail ends of source and ;destination arrays. Copy a word or a byte at a time? orr r3, r1, r0 ;tmp = s | d orr r3, r3, r2 ;tmp = s | d | c ands r3, r3, #3 ;is tmp even multiple of 4? add r1, r1, r2 ;s + c (end of source buffer) add r2, r2, r0 ;d + c (end of dest nth buffer) beq MOVE1 ;jump if tmp is multiple of 4 b MOVE2 ;because count c is an even multiple of 4 and the source ;and destination arrays begin on even word boundaries, move ;an entire word at a time from source to destination. MOVE3 ldrb r3, [r1, #-1]! ;load next byte from source strb r3, [r2, #-1]! ;store next byte to dest Nth MOVE2 teq r0, r2 ;more bytes to move? bne MOVE3 ;jump if more bytes bx lr ;all done ;Because the source and destination arrays are not aligned to even ;word boundaries in memory, transfer only a byte at a time. MOVE4 ldr r3, [r1, #-4]! ;load next word from source str r3, [r2, #-4]! ;store next word to dest Nth MOVE1 teq r0, r2 ;more words to move? bne MOVE4 ;jump if more words bx lr ;all done } __asm s32 MemCmp(u8 *dest, u8 *src, u16 n) { stmdb sp!,{r4-r6,lr} ;save registers on stack mov r3,r0 ;copy 1st arg, p1 mov r0,#0 ;set return value = 0 teq r2,#0 ;is n == 0 ? ldmeqia sp!,{r4-r6,pc} ;return if n == 0 cmp r2,#12 ;is n > 12 ble ByteLoop ;if n <= 12, jump sub r0,r3,r1 ;p1 - p2 ands r0,r0,#3 ;(p1 - p2) & 3 beq WordCompare ;jump if byte offsets match ;The strings begin at different byte offsets WRT word boundaries. ;Loop below processes only a single pair of bytes per iteration. ByteLoop ldrb r0,[r3],#1 ;b1 = next byte from string 1 ldrb r4,[r1],#1 ;b2 = next byte from string 2 subs r0,r0,r4 ;b1 - b2 bne ByteBreak ;if b1 != b2, break out of loop subs r2,r2,#1 ;--n (decrement loop counter) bne ByteLoop ;loop again if n > 0 ByteBreak ldmia sp!,{r4-r6,pc} ;return to caller (ret val = b1-b2) ;The two strings have same starting byte alignment WRT word boundary. ;Set up inner loop that compares a pair of words per iteration. WordCompare add r5,r3,r2 ;e1 = p1 + n (point to trailing byte) and lr,r3,#3 ;align = p1 & 3 (initial byte offset) bic r3,r3,#3 ;p1 &= ~3 (point to word boundary) bic r1,r1,#3 ;p2 &= ~3 add r2,r5,#3 ;e1 + 3 sub r2,r2,r3 ;e1 + 3 - p1 mov r2,r2,lsr #2 ;nWords = (e1 + 3 - p1) >> 2 mvn r6,#0 ;initialize mask to all 1s mov r0,lr,lsl #3 ;convert byte offset to bit offset mov r6,r6,lsl r0 ;poke holes in mask for invalid bytes ldr r0,[r3],#4 ;w1 = *p1++ and r0,r0,r6 ;isolate starting bytes in 1st string ldr r4,[r1],#4 ;w2 = *p2++ and r4,r4,r6 ;isolate starting bytes in 2nd string ;Inner loop: Compare the two strings one word at a time to look for ;a mismatch. If the two strings match, return 0. WordLoop subs r0,r0,r4 ;w1 - w2 bne WordBreak ;if w1 != w2, break out of loop ldr r0,[r3],#4 ;w1 = *p1++ subs r2,r2,#1 ;--nWords ldr r4,[r1],#4 ;w2 = *p2++ bne WordLoop ;loop again if more words in string mov r0,#0 ;set return argument = 0 ldmia sp!,{r4-r6,pc} ;all done -- return to caller ;The strings may still match if the apparent mismatch happened in ;the final pair of words from the two strings (in trailing bytes). WordBreak teq r2,#1 ;nWords == 1? (mismatch at EOS?) bne FindMismatch ;jump if nWords != 1 ands r5,r5,#3 ;is trailing byte word-aligned? beq FindMismatch ;jump if word-aligned (real mismatch) mvn r6,#0 ;initialize mask to all 1s mov r5,r5,lsl #3 ;convert byte offset to bit offset mov r6,r6,lsl r5 mvn r6, r6 ;poke holes in mask for invalid bytes ands r0,r0,r6 ;mask off trailing bytes, string 1 ldmeqia sp!,{r4-r6,pc} ;if w1 == w2, return val = 0 ;We detected a mismatch in the current pair of words from the strings. ;But in which byte position within the words did the mismatch occur? FindMismatch add r3,r0,r4 ;restore value w1 NextByte and r0,r3,#0xff ;b1 = w1 & 0xff (isolate byte) and r2,r4,#0xff ;b2 = w2 & 0xff subs r0,r0,r2 ;return val = b1 - b2 ? ldmneia sp!,{r4-r6,pc} ;if val != 0, return to caller mov r3,r3,lsr #8 ;w1 >>= 8 (position next byte) mov r4,r4,lsr #8 ;w2 >>= 8 b NextByte ;if b1 != b2, loop again } ================================================ FILE: Data/inc/Fifo.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _FIFO_H #define _FIFO_H #include "stm32f4xx.h" #define MIN(a,b) ((a) < (b) ? (a) : (b)) typedef struct FIFO_T { u8 *Data; u16 Size; u16 In, Out; }Fifo; void Fifo_Init(Fifo* fifo, u8 *buff, u16 len); u16 Fifo_Get(Fifo* fifo, u8 *buff, u16 len); void Fifo_Put(Fifo *fifo, u8 *buff, u16 len); #endif ================================================ FILE: Data/inc/Queue.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _QUEUE_H #define _QUEUE_H #include "stm32f4xx.h" #define MAX_MESSAGE_LEN (10) #define MAX_QUEUE_LEN (32) #define MAX_QUEUE_MASK (31) typedef struct Buff_T { s8 Buff[MAX_MESSAGE_LEN]; u16 Len; }Buff; typedef struct QUEUE_T { Buff Buffs[MAX_QUEUE_LEN]; u16 Head; u16 Tail; u16 Size; }Queue, *PQueue; __inline s32 Queue_IsFull(PQueue queue) { return (queue->Size == MAX_QUEUE_LEN); } __inline u16 Queue_Size(PQueue queue) { return queue->Size; } __inline s32 Queue_IsEmpty(PQueue queue) { return (queue->Size == 0); } s32 Queue_Enqueue(PQueue queue, s8* string, u16 len); s32 Queue_Dequeue(PQueue queue, Buff* buff); #endif ================================================ FILE: Data/src/Fifo.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "Fifo.h" #include "Memory.h" void Fifo_Init(Fifo* fifo, u8 *buff, u16 len) { fifo->Data = buff; fifo->Size = len; fifo->In = fifo->Out = 0; } u16 Fifo_Get(Fifo* fifo, u8 *buff, u16 len) { u16 l; len = MIN(len, fifo->In - fifo->Out); l = MIN(len, fifo->Size - (fifo->Out & (fifo->Size - 1))); MemCpy(buff, fifo->Data + (fifo->Out & (fifo->Size - 1)), l); MemCpy(buff + l, fifo->Data, len - l); fifo->Out += len; return len; } void Fifo_Put(Fifo *fifo, u8 *buff, u16 len) { u16 fixLen; ////////////////////////////////////////////////////////////////////////// len = MIN(len, fifo->Size - fifo->In + fifo->Out); fixLen = MIN(len, fifo->Size - (fifo->In & (fifo->Size - 1))); MemCpy(fifo->Data + (fifo->In & (fifo->Size - 1)), buff, fixLen); MemCpy(fifo->Data, buff + fixLen, len - fixLen); fifo->In += len; } ================================================ FILE: Data/src/Queue.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "Queue.h" #include "Memory.h" s32 Queue_Enqueue(PQueue queue, s8* string, u16 len) { if(Queue_IsFull(queue)){ return -1; } queue->Size++; ////////////////////////////////////////////////////////////////////////// queue->Buffs[queue->Tail].Len = len; MemCpy((u8*)queue->Buffs[queue->Tail].Buff, (u8*)string, len); ////////////////////////////////////////////////////////////////////////// queue->Tail++; queue->Tail &= MAX_QUEUE_MASK; return 0; } s32 Queue_Dequeue(PQueue queue, Buff* buff) { if(Queue_IsEmpty(queue)){ return -1; } queue->Size--; ////////////////////////////////////////////////////////////////////////// *buff = queue->Buffs[queue->Head]; ////////////////////////////////////////////////////////////////////////// queue->Head++; queue->Head &= MAX_QUEUE_MASK; return 0; } ================================================ FILE: Drivers/inc/stm32f4_exti.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _STM32F4_EXTI_H #define _STM32F4_EXTI_H #include "stm32f4xx.h" #include "stm32f4_rcc.h" typedef struct EXTI_DRIVER_T { GPIO_TypeDef* Gpio; RCC_AXXPeriphClockCmd GPIO_CLK; uint32_t GPIO_Func; uint16_t GPIO_Pin; uint8_t EXTI_PortSourceGPIO; uint8_t EXTI_PinSource; EXTI_InitTypeDef EXIT_Init; NVIC_InitTypeDef NVIC_Init; }EXTI_Driver; void EXTIx_Init(EXTI_Driver* EXTIx); #endif ================================================ FILE: Drivers/inc/stm32f4_gpio.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __STM32F4_GPIO_H #define __STM32F4_GPIO_H // Includes #include "stm32f4xx.h" #include "stm32f4_rcc.h" typedef struct GPIO_DRIVER_T { GPIO_TypeDef* Gpio; RCC_AXXPeriphClockCmd GPIO_CLK; uint32_t GPIO_Func; GPIO_InitTypeDef GPIO_Init; }GPIO_Driver; void GPIOx_Init(GPIO_Driver* GPIOx); __inline void GPIOx_SetLow(GPIO_Driver* GPIOx) { GPIO_ResetBits(GPIOx->Gpio, GPIOx->GPIO_Init.GPIO_Pin); } __inline void GPIOx_SetHigh(GPIO_Driver* GPIOx){ GPIO_SetBits(GPIOx->Gpio, GPIOx->GPIO_Init.GPIO_Pin); } #endif ================================================ FILE: Drivers/inc/stm32f4_spi.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __STM32F4_SPI_H #define __STM32F4_SPI_H // Includes #include "stm32f4xx.h" #include "stm32f4_rcc.h" //#define SPIx_USE_DMA #define SPIx_BR_CLEAR_MASK ((uint16_t)(0xFFC7)) typedef struct SPI_DRIVER_T { SPI_TypeDef* SPI; RCC_AXXPeriphClockCmd SPI_CLK; uint32_t SPI_Func; GPIO_TypeDef* Gpio; RCC_AXXPeriphClockCmd GPIO_CLK; uint32_t GPIO_Func; GPIO_TypeDef* Gpio_CS; RCC_AXXPeriphClockCmd GPIO_CS_CLK; uint32_t CS_Func; uint16_t CS_Pin; uint16_t SCK_Pin; uint16_t MISO_Pin; uint16_t MOSI_Pin; uint16_t SCK_Src; uint16_t MISO_Src; uint16_t MOSI_Src; SPI_InitTypeDef SPI_Init; #ifdef SPIx_USE_DMA RCC_AXXPeriphClockCmd DMA_CLK; uint32_t DMA_Func; DMA_TypeDef* DMA_TX; DMA_Stream_TypeDef* DMA_TX_Stream; NVIC_InitTypeDef NVIC_DMA_TX; uint32_t DMA_TX_CH; uint32_t DMA_TX_Flag; DMA_TypeDef* DMA_RX; DMA_Stream_TypeDef* DMA_RX_Stream; NVIC_InitTypeDef NVIC_DMA_RX; uint32_t DMA_RX_CH; uint32_t DMA_RX_Flag; #endif uint8_t GPIO_AF_SPI; }SPI_Driver; __inline void Chip_Select(SPI_Driver* SPIx) { GPIO_ResetBits((SPIx)->Gpio_CS, (SPIx)->CS_Pin); } __inline void Chip_DeSelect(SPI_Driver* SPIx){ GPIO_SetBits((SPIx)->Gpio_CS, (SPIx)->CS_Pin); } void SPIx_Init(SPI_Driver* SPIx); void SPIx_DeInit(SPI_Driver* SPIx); uint8_t SPIx_Read_Reg(SPI_Driver* SPIx, uint8_t reg); void SPIx_Write_Reg(SPI_Driver* SPIx, uint8_t regAddr, uint8_t data); void SPIx_Read_Regs(SPI_Driver* SPIx, uint8_t regAddr, uint8_t length, uint8_t* buffer); #ifdef SPIx_USE_DMA void SPIx_DMA_Read_Regs(SPI_Driver* SPIx, uint8_t regAddr, uint8_t length, uint8_t* buffer); #endif uint8_t SPIx_SendByte(SPI_Driver* SPIx, uint8_t byte); uint16_t SPIx_SendWord(SPI_Driver* SPIx, uint16_t word); void SPIx_ReadBytes(SPI_Driver* SPIx, uint8_t length, uint8_t* buffer); void SPIx_SetDivisor(SPI_Driver* SPIx, uint16_t Prescaler); #endif ================================================ FILE: Drivers/inc/stm32f4_usart.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef __STM32F4_USART_H #define __STM32F4_USART_H // include #include "stm32f4xx.h" #include "stm32f4_rcc.h" #define DEFAULT_BAUDRATE 115200 #define USARTx_USE_DMA #ifdef USARTx_USE_DMA #define DEFAULT_BUFFERSIZE 256 #endif typedef struct USART_DRIVER_T { USART_TypeDef* USART; RCC_AXXPeriphClockCmd USART_CLK; uint32_t USART_Func; uint32_t USART_BaudRate; GPIO_TypeDef* TX_GPIO; RCC_AXXPeriphClockCmd TX_GPIOClk; uint32_t TX_GPIOFunc; uint16_t TX_Pin; uint16_t TX_Src; GPIO_TypeDef* RX_GPIO; RCC_AXXPeriphClockCmd RX_GPIOClk; uint32_t RX_GPIOFunc; uint16_t RX_Pin; uint16_t RX_Src; #ifdef USARTx_USE_DMA NVIC_InitTypeDef NVIC_USART; NVIC_InitTypeDef NVIC_DMA_TX; RCC_AXXPeriphClockCmd DMA_CLK; uint32_t DMA_Func; uint32_t DMA_TX_Size; uint8_t* DMA_TX_Buffer; DMA_Stream_TypeDef* DMA_TX_Stream; uint32_t DMA_TX_CH; uint32_t DMA_RX_Size; uint8_t* DMA_RX_Buffer; DMA_Stream_TypeDef* DMA_RX_Stream; uint32_t DMA_RX_CH; #endif uint8_t GPIO_AF_USART; }USART_Driver; void USARTx_Init(USART_Driver* USARTx); void USARTx_DeInit(USART_Driver* USARTx); void USARTx_SendByte(USART_Driver* USARTx, uint8_t byte); void USARTx_SendBytes(USART_Driver* USARTx, uint8_t* buffer, uint8_t length); #ifdef USARTx_USE_DMA void USARTx_DMA_SendBytes(USART_Driver* USARTx, uint8_t* buffer, uint8_t length); #endif #endif ================================================ FILE: Drivers/src/stm32f4_exti.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "stm32f4_exti.h" void EXTIx_Init(EXTI_Driver* EXTIx) { GPIO_InitTypeDef GPIO_InitStructure; //Enable GPIO clocks EXTIx->GPIO_CLK(EXTIx->GPIO_Func, ENABLE); //Enable SYSCFG clock RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); //Configure GPIO pin as input floating GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_InitStructure.GPIO_Pin = EXTIx->GPIO_Pin; GPIO_Init(EXTIx->Gpio, &GPIO_InitStructure); //Connect EXTI Line to GPIO Pin SYSCFG_EXTILineConfig(EXTIx->EXTI_PortSourceGPIO, EXTIx->EXTI_PinSource); //Configure EXTI line EXTI_Init(&EXTIx->EXIT_Init); //Enable and set EXTI Interrupt priority NVIC_Init(&EXTIx->NVIC_Init); } ================================================ FILE: Drivers/src/stm32f4_gpio.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ // Includes #include "stm32f4_gpio.h" void GPIOx_Init(GPIO_Driver* GPIOx) { GPIOx->GPIO_CLK(GPIOx->GPIO_Func, ENABLE); GPIO_Init(GPIOx->Gpio, &GPIOx->GPIO_Init); } ================================================ FILE: Drivers/src/stm32f4_spi.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "stm32f4_spi.h" static uint8_t DUMMY_BYTE = 0xA5; void SPIx_Init(SPI_Driver* SPIx) { GPIO_InitTypeDef GPIO_InitStructure; #ifdef SPIx_USE_DMA DMA_InitTypeDef DMA_InitStructure; #endif // Enable SPI and GPIO clocks SPIx->SPI_CLK(SPIx->SPI_Func, ENABLE); SPIx->GPIO_CLK(SPIx->GPIO_Func, ENABLE); // Connect SPI pins to AF GPIO_PinAFConfig(SPIx->Gpio, SPIx->SCK_Src, SPIx->GPIO_AF_SPI); GPIO_PinAFConfig(SPIx->Gpio, SPIx->MISO_Src, SPIx->GPIO_AF_SPI); GPIO_PinAFConfig(SPIx->Gpio, SPIx->MOSI_Src, SPIx->GPIO_AF_SPI); // SPI SCK/MISO/MOSI pin configuration GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_InitStructure.GPIO_Pin = SPIx->SCK_Pin | SPIx->MISO_Pin | SPIx->MOSI_Pin; GPIO_Init(SPIx->Gpio, &GPIO_InitStructure); SPIx->GPIO_CS_CLK(SPIx->CS_Func, ENABLE); // Configure GPIO PIN for Chip select GPIO_InitStructure.GPIO_Pin = SPIx->CS_Pin; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_Init(SPIx->Gpio_CS, &GPIO_InitStructure); // Chip DeSelect high Chip_DeSelect(SPIx); //SPI configuration -------------------------------------------------------*/ SPI_I2S_DeInit(SPIx->SPI); SPI_Init(SPIx->SPI, &SPIx->SPI_Init); SPI_CalculateCRC(SPIx->SPI, DISABLE); //Enable SPI SPI_Cmd(SPIx->SPI, ENABLE); while (SPI_I2S_GetFlagStatus(SPIx->SPI, SPI_I2S_FLAG_TXE) == RESET); SPI_I2S_ReceiveData(SPIx->SPI); #ifdef SPIx_USE_DMA // Enable DMA clock SPIx->DMA_CLK(SPIx->DMA_Func, ENABLE); //Enable the SPIx_RX_DMA_CHANNEL (SPIx_RX) Interrupt NVIC_Init(&SPIx->NVIC_DMA_TX); //Enable the SPIx_TX_DMA_CHANNEL (SPIx_TX) Interrupt NVIC_Init(&SPIx->NVIC_DMA_RX); // Deinitialize DMA Streams DMA_DeInit(SPIx->DMA_TX_Stream); while (DMA_GetCmdStatus(SPIx->DMA_TX_Stream) != DISABLE); DMA_Cmd(SPIx->DMA_TX_Stream, DISABLE); DMA_DeInit(SPIx->DMA_RX_Stream); while (DMA_GetCmdStatus(SPIx->DMA_RX_Stream) != DISABLE); DMA_Cmd(SPIx->DMA_RX_Stream, DISABLE); // Configure DMA Initialization Structure DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)(&(SPIx->SPI->DR)); DMA_InitStructure.DMA_BufferSize = 0; DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull; DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; DMA_InitStructure.DMA_Priority = DMA_Priority_High; // Configure TX DMA DMA_InitStructure.DMA_Channel = SPIx->DMA_TX_CH; DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; DMA_InitStructure.DMA_Memory0BaseAddr =(uint32_t)0; DMA_Init(SPIx->DMA_TX_Stream, &DMA_InitStructure); // Configure RX DMA DMA_InitStructure.DMA_Channel = SPIx->DMA_RX_CH; DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)0; DMA_Init(SPIx->DMA_RX_Stream, &DMA_InitStructure); SPI_DMACmd(SPIx->SPI, SPI_DMAReq_Rx, ENABLE); SPI_DMACmd(SPIx->SPI, SPI_DMAReq_Tx, ENABLE); DMA_ClearFlag(SPIx->DMA_TX_Stream, SPIx->DMA_TX_Flag); DMA_ClearFlag(SPIx->DMA_RX_Stream, SPIx->DMA_RX_Flag); DMA_ITConfig(SPIx->DMA_TX_Stream, DMA_IT_TC | DMA_IT_TE, ENABLE); DMA_ITConfig(SPIx->DMA_RX_Stream, DMA_IT_TC | DMA_IT_TE, ENABLE); DMA_Cmd(SPIx->DMA_TX_Stream, DISABLE); DMA_Cmd(SPIx->DMA_RX_Stream, DISABLE); #endif } void SPIx_DeInit(SPI_Driver* SPIx) { GPIO_InitTypeDef GPIO_InitStructure; GPIO_InitStructure.GPIO_Pin = SPIx->SCK_Pin | SPIx->MISO_Pin | SPIx->MOSI_Pin; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(SPIx->Gpio, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = SPIx->CS_Pin; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_Init(SPIx->Gpio, &GPIO_InitStructure); #ifdef SPIx_USE_DMA // Deinitialize DMA Streams DMA_DeInit(SPIx->DMA_TX_Stream); while (DMA_GetCmdStatus(SPIx->DMA_TX_Stream) != DISABLE); DMA_Cmd(SPIx->DMA_TX_Stream, DISABLE); DMA_DeInit(SPIx->DMA_RX_Stream); while (DMA_GetCmdStatus(SPIx->DMA_RX_Stream) != DISABLE); DMA_Cmd(SPIx->DMA_RX_Stream, DISABLE); #endif } uint8_t SPIx_Read_Reg(SPI_Driver* SPIx, uint8_t reg) { uint8_t tmp; reg += 0x80; //reading procedure has to set the most significant bit // Chip Select low Chip_Select(SPIx); // Send Register Address SPIx_SendByte(SPIx, reg); // Read a byte tmp = SPIx_SendByte(SPIx, DUMMY_BYTE); // Chip Select high Chip_DeSelect(SPIx); return tmp; } void SPIx_Write_Reg(SPI_Driver* SPIx, uint8_t regAddr, uint8_t data) { // Chip Select low Chip_Select(SPIx); // Send Register Address SPIx_SendByte(SPIx, regAddr); // Write a byte SPIx_SendByte(SPIx, data); // Chip Select high Chip_DeSelect(SPIx); } void SPIx_Read_Regs(SPI_Driver* SPIx, uint8_t regAddr, uint8_t length, uint8_t* buffer) { uint8_t i = 0; regAddr += 0xc0; //reading procedure has to set the most significant bit // Chip Select low Chip_Select(SPIx); // Send Register Address SPIx_SendByte(SPIx, regAddr); while(i < length){ // Read a byte buffer[i] = SPIx_SendByte(SPIx, DUMMY_BYTE); i++; } // Chip Select high Chip_DeSelect(SPIx); } #ifdef SPIx_USE_DMA void SPIx_DMA_Read_Regs(SPI_Driver* SPIx, uint8_t regAddr, uint8_t length, uint8_t* buffer) { regAddr += 0xc0; //reading procedure has to set the most significant bit // Chip Select low Chip_Select(SPIx); // Send Register Address SPIx_SendByte(SPIx, regAddr); SPIx->DMA_RX_Stream->CR &= 0xFFFFFFFE; while(SPIx->DMA_RX_Stream->CR & 0x00000001); SPIx->DMA_RX->LIFCR |= 0x0F400000; SPIx->DMA_RX_Stream->NDTR = length; SPIx->DMA_RX_Stream->M0AR = (uint32_t)buffer; SPIx->DMA_RX_Stream->CR |= 1; //Dummy TX channel configuration SPIx->DMA_TX_Stream->CR &= 0xFFFFFFFE; while(SPIx->DMA_TX_Stream->CR & 0x00000001); SPIx->DMA_TX->HIFCR |= 0x0000003D; SPIx->DMA_TX_Stream->CR &= 0xFFFFFBFF;//DMA_SxCR_MINC SPIx->DMA_TX_Stream->NDTR = length; SPIx->DMA_TX_Stream->M0AR = (u32)(&DUMMY_BYTE); SPIx->DMA_TX_Stream->CR |= 1; } #endif uint8_t SPIx_SendByte(SPI_Driver* SPIx, uint8_t byte) { // Loop while DR register in not emplty while (SPI_I2S_GetFlagStatus(SPIx->SPI, SPI_I2S_FLAG_TXE) == RESET); // Send byte through the SPI1 peripheral SPI_I2S_SendData(SPIx->SPI, byte); // Wait to receive a byte while (SPI_I2S_GetFlagStatus(SPIx->SPI, SPI_I2S_FLAG_RXNE) == RESET); // Return the byte read from the SPI bus return SPI_I2S_ReceiveData(SPIx->SPI); } uint16_t SPIx_SendWord(SPI_Driver* SPIx, uint16_t word) { // Loop while DR register in not emplty while (SPI_I2S_GetFlagStatus(SPIx->SPI, SPI_I2S_FLAG_TXE) == RESET); // Send byte through the SPI1 peripheral SPI_I2S_SendData(SPIx->SPI, word); // Wait to receive a byte while (SPI_I2S_GetFlagStatus(SPIx->SPI, SPI_I2S_FLAG_RXNE) == RESET); // Return the byte read from the SPI bus return SPI_I2S_ReceiveData(SPIx->SPI); } void SPIx_ReadBytes(SPI_Driver* SPIx,uint8_t length, uint8_t* buffer) { uint8_t i = 0; // Select Mems Sensor: Chip Select low Chip_Select(SPIx); while(i < length){ // Read a byte from the MEMS Sensor buffer[i] = SPIx_SendByte(SPIx, DUMMY_BYTE); i++; } // Deselect Mems Sensor: Chip Select high Chip_DeSelect(SPIx); } void SPIx_SetDivisor(SPI_Driver* SPIx, uint16_t Prescaler) { uint16_t tmp; if(SPIx->SPI_Init.SPI_BaudRatePrescaler == Prescaler){ return; } SPI_Cmd(SPIx->SPI, DISABLE); tmp = SPIx->SPI->CR1; tmp &= SPIx_BR_CLEAR_MASK; tmp |= Prescaler; SPIx->SPI->CR1 = tmp; SPI_Cmd(SPIx->SPI, ENABLE); } ================================================ FILE: Drivers/src/stm32f4_usart.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "stm32f4_usart.h" #include "Memory.h" void USARTx_Init(USART_Driver* USARTx) { USART_InitTypeDef USART_InitStructure; USART_ClockInitTypeDef USART_ClockInitStruct; GPIO_InitTypeDef GPIO_InitStructure; #ifdef USARTx_USE_DMA DMA_InitTypeDef DMA_InitStructure; #endif // USARTx GPIO configuration // Enable GPIO clock USARTx->TX_GPIOClk(USARTx->TX_GPIOFunc, ENABLE); USARTx->RX_GPIOClk(USARTx->RX_GPIOFunc, ENABLE); // Connect USART pins to AF GPIO_PinAFConfig(USARTx->TX_GPIO, USARTx->TX_Src, USARTx->GPIO_AF_USART); GPIO_PinAFConfig(USARTx->RX_GPIO, USARTx->RX_Src, USARTx->GPIO_AF_USART); // Configure USART Tx and Rx as alternate function push-pull GPIO_StructInit(&GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = USARTx->TX_Pin; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; GPIO_Init(USARTx->TX_GPIO, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = USARTx->RX_Pin; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(USARTx->RX_GPIO, &GPIO_InitStructure); // USARTx configuration // Enable the USART OverSampling by 8 //USART_OverSampling8Cmd(USARTx->USART, ENABLE); // Enable USART clock USARTx->USART_CLK(USARTx->USART_Func, ENABLE); USART_StructInit(&USART_InitStructure); USART_InitStructure.USART_BaudRate = USARTx->USART_BaudRate; USART_InitStructure.USART_WordLength = USART_WordLength_8b; USART_InitStructure.USART_StopBits = USART_StopBits_1; // When using Parity the word length must be configured to 9 bits USART_InitStructure.USART_Parity = USART_Parity_No; USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; USART_ClockStructInit(&USART_ClockInitStruct); USART_ClockInit(USARTx->USART, &USART_ClockInitStruct); USART_Init(USARTx->USART, &USART_InitStructure); USART_ITConfig(USARTx->USART, USART_IT_TC, DISABLE); USART_ITConfig(USARTx->USART, USART_IT_IDLE, ENABLE); USART_ITConfig(USARTx->USART, USART_IT_RXNE, DISABLE); USART_ITConfig(USARTx->USART, USART_IT_TXE, DISABLE); NVIC_Init(&USARTx->NVIC_USART); #ifdef USARTx_USE_DMA // Enable the DMA clock USARTx->DMA_CLK(USARTx->DMA_Func, ENABLE); NVIC_Init(&USARTx->NVIC_DMA_TX); //NVIC_Init(&USARTx->NVIC_DMA_RX); // Configure DMA controller to manage USART TX and RX DMA request // Configure DMA Initialization Structure // Configure TX DMA DMA_DeInit(USARTx->DMA_TX_Stream); DMA_InitStructure.DMA_Channel = USARTx->DMA_TX_CH; DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)(&(USARTx->USART->DR)); DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)USARTx->DMA_TX_Buffer; DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; DMA_InitStructure.DMA_BufferSize = USARTx->DMA_TX_Size; DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; DMA_InitStructure.DMA_Priority = DMA_Priority_High; DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable; DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull; DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single ; DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; DMA_Init(USARTx->DMA_TX_Stream, &DMA_InitStructure); DMA_ITConfig(USARTx->DMA_TX_Stream, DMA_IT_TC, ENABLE); // Configure RX DMA DMA_DeInit(USARTx->DMA_RX_Stream); DMA_InitStructure.DMA_BufferSize = USARTx->DMA_RX_Size; DMA_InitStructure.DMA_Channel = USARTx->DMA_RX_CH;; DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory; DMA_InitStructure.DMA_Memory0BaseAddr =(uint32_t)USARTx->DMA_RX_Buffer; DMA_Init(USARTx->DMA_RX_Stream, &DMA_InitStructure); DMA_Cmd(USARTx->DMA_RX_Stream, ENABLE); USART_DMACmd(USARTx->USART, USART_DMAReq_Rx | USART_DMAReq_Tx, ENABLE); #endif // Enable USART USART_Cmd(USARTx->USART, ENABLE); } void USARTx_DeInit(USART_Driver* USARTx) { GPIO_InitTypeDef GPIO_InitStructure; GPIO_InitStructure.GPIO_Pin = USARTx->TX_Pin; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(USARTx->TX_GPIO, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = USARTx->RX_Pin; GPIO_Init(USARTx->RX_GPIO, &GPIO_InitStructure); #ifdef USARTx_USE_DMA // Deinitialize DMA Streams DMA_DeInit(USARTx->DMA_TX_Stream); while (DMA_GetCmdStatus(USARTx->DMA_TX_Stream) != DISABLE); DMA_Cmd(USARTx->DMA_TX_Stream, DISABLE); DMA_DeInit(USARTx->DMA_RX_Stream); while (DMA_GetCmdStatus(USARTx->DMA_RX_Stream) != DISABLE); DMA_Cmd(USARTx->DMA_RX_Stream, DISABLE); #endif } void USARTx_SendByte(USART_Driver* USARTx, uint8_t byte) { USART_SendData(USARTx->USART, byte); // Loop until the end of transmission while (USART_GetFlagStatus(USARTx->USART, USART_FLAG_TXE) == RESET); } void USARTx_SendBytes(USART_Driver* USARTx, uint8_t* buffer, uint8_t length) { uint8_t i = 0; while(i++ < length){ USART_SendData(USARTx->USART, buffer[i]); while (USART_GetFlagStatus(USARTx->USART, USART_FLAG_TXE) == RESET); } } #ifdef USARTx_USE_DMA void USARTx_DMA_SendBytes(USART_Driver* USARTx, uint8_t* buffer, uint8_t length) { FastMemCpy(USARTx->DMA_TX_Buffer, buffer, length); // Enable USARTx DMA TX Channel DMA_SetCurrDataCounter(USARTx->DMA_TX_Stream, length); DMA_Cmd(USARTx->DMA_TX_Stream, ENABLE); //USARTx->DMA_TX_Stream->NDTR = length; //USARTx->DMA_TX_Stream->CR |= DMA_SxCR_EN; } #endif ================================================ FILE: Gps/inc/Map.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _MAP_H #define _MAP_H #include "stm32f4xx.h" #include "Double.h" typedef struct DOUBLEPOINT_T { Double lat; Double lon; }DoublePoint; typedef struct MAP_T { //reference point DoublePoint _dPoint; DoublePoint dPoint; DoublePoint _gsPoint; DoublePoint gsPoint; // //reference position Double X, Y; // //coefficient Double a, b, c, bl; // } Map; ////////////////////////////////////////////////////////////////////////// //must init with local two reference points including lat, lon and the length //betweeb two reference points void Map_Init(Map* pMap, double x1, double y1, double x2, double y2, double x, double y, double length); void Map_GetXY(Map* pMap, double lat, double lon, double *x, double *y); #endif ================================================ FILE: Gps/inc/Nema.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _STM32F4_NEMA_H #define _STM32F4_NEMA_H #include "stm32f4xx.h" #include "Double.h" #define NEMA_MESSAGEID_SIZE (5) #define NMEA_MAXSVS (12) typedef enum{ GPNON = 0x0000, GPGGA = 0x0001, GPGSA = 0x0002, GPRMC = 0x0004, GPVTG = 0x0008 } NEMA_MessageType; //GGA Global positioning system fix data typedef struct _nmeaGPGGA { double time; double lat; char NS; double lon; char EW; int quality; int numSV; double HDOP; double alt; char uAlt; double sep; char uSep; double diffAge; int diffStation; }nmeaGPGGA, *PnmeaGPGGA; //GSA GNSS DOP and Active Satellites typedef struct _nmeaGPGSA { char opMode; int navMode; int sv[NMEA_MAXSVS];//Satellite number double PDOP; double HDOP; double VDOP; int systemId; } nmeaGPGSA, *PnmeaGPGSA; //RMC Recommended Minimum data typedef struct _nmeaGPRMC { double time; char status; double lat; char NS; double lon; char EW; double spd; double cog; int date; double mv; char mvEW; char posMode; char navStatus; } nmeaGPRMC, *PnmeaGPRMC; //VTG Course over ground and Ground speed typedef struct _nmeaGPVTG { double cogt; char T; double cogm; char M; double knots; char N; double kph; char K; char posMode; } nmeaGPVTG, *PnmeaGPVTG; typedef struct _nmeaINFO { double lat; double lon; double alt; double spd; double cog; } nmeaINFO; typedef uint64_t u64; ////////////////////////////////////////////////////////////////////////// //input -2^23 < x < 2^23 __inline float NEMA_Fast_UintToFloat(u32 x) { union { float f; u32 i; } u = { 8388608.0f }; u.i |= x; return u.f - 8388608.0f; } // __inline float NEMA_Fast_FloatInverse(float x) { union { float f; u32 i; } u; u.f = x; u.i = 0x7F000000 - u.i; return u.f; } ////////////////////////////////////////////////////////////////////////// //input -2^52 < x < 2^52 __inline double NEMA_Fast_Uint64ToDouble(u64 x) { union { double d; u64 i; } u = {4503599627370496.0 }; u.i |= x; return u.d - 4503599627370496.0; } __inline double NEMA_Fast_DoubleInverse(double x) { union { double d; u64 i; } u; u.d = x; u.i = (u64)0x7FE0000000000000 - u.i; return u.d; } __inline u8 NEMA_FastCRCtoI(s8 *p, u8 *table){ return table[*p] << 4 | table[*(p + 1)]; } float NEMA_FastAtoF(s8 *p, s32 len); double NEMA_FastAtoD(s8 *p, s32 len); s32 NEMA_FastAtoI(s8 *p, s32 len); u16 NEMA_Parser(s8 *p, u16 len); s16 NEMA_GetMessage(void *data, s32* iType); // double NMEA_Convert2Degrees(double val); double NMEA_Degree2Radian(double val); double NMEA_Radian2Degree(double val); Double NMEA_Degree2RadianD(Double val); #endif ================================================ FILE: Gps/src/Map.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "Map.h" #include "Nema.h" #include "FastMath.h" DoublePoint Map_BLToGauss(Double latitude, Double longitude) { DoublePoint point; int ProjNo = 0, ZoneWide = 6; __int64 X0, Y0; Double lon, lat, _lon; Double e2, ee, NN, T, C, A, M; // float sin, cos; float tan, _2sin, _4sin, _6sin; Double dsin, dcos; Double dtan, _d2sin, _d4sin, _d6sin; //beijing 54 Double a = doubleToDouble(6378245.0); Double f = doubleToDouble(0.00335232986925913509889373114314); //xi'an 80 //Double a = doubleToDouble(6378140.0); //Double f = doubleToDouble(0.00335281317789691440603238146967); ProjNo = (int)DoubleTodouble(DoubleDiv(lon, intToDouble(ZoneWide))); _lon = intToDouble(ProjNo * ZoneWide + ZoneWide / 2); _lon = NMEA_Degree2RadianD(_lon); lon = NMEA_Degree2RadianD(longitude); lat = NMEA_Degree2RadianD(latitude); tan = (float)DoubleTodouble(lat); dtan = floatToDouble(FastTan(tan)); FastSinCos((float)DoubleTodouble(lat), &sin, &cos); dsin = floatToDouble(sin); dcos = floatToDouble(cos); _2sin = (float)DoubleTodouble(DoubleMul(intToDouble(2), lat)); _4sin = (float)DoubleTodouble(DoubleMul(intToDouble(4), lat)); _6sin = (float)DoubleTodouble(DoubleMul(intToDouble(6), lat)); _d2sin = floatToDouble(FastSin(_2sin)); _d4sin = floatToDouble(FastSin(_4sin)); _d6sin = floatToDouble(FastSin(_6sin)); e2 = DoubleSub(DoubleMul(intToDouble(2),f), DoubleMul(f,f)); ee = DoubleMul(e2, DoubleSub(intToDouble(1), e2)); NN = DoubleMul(a, FastSqrtID(DoubleSub(doubleToDouble(1.0), DoubleMul(e2, DoubleMul(dsin, dsin))))); T = DoubleMul(dtan, dtan); C = DoubleMul(ee, DoubleMul(dcos, dcos)); A = DoubleMul(DoubleSub(lon, _lon), dcos); //todo not finish yet! /* M = a * ((1 - e2 / 4 - 3 * e2 * e2 / 64 - 5 * e2 * e2 * e2 / 256) * lat - (3 * e2 / 8 + 3 * e2 * e2 / 32 + 45 * e2 * e2 * e2 / 1024) * _d2sin + (15 * e2 * e2 / 256 + 45 * e2 * e2 * e2 / 1024) * _d4sin - (35 * e2 * e2 * e2 / 3072) * _d6sin); point.lon = NN * (A + (1 - T + C) * A * A * A / 6 + (5 - 18 * T + T * T + 72 * C - 58 * ee) * A * A * A * A * A / 120); point.lat = M + NN * tan * (A * A / 2 + (5 - T + 9 * C + 4 * C * C) * A * A * A * A / 24 + (61 - 58 * T + T * T + 600 * C - 330 * ee) * A * A * A * A * A * A / 720); */ X0 = 1000000L * (ProjNo + 1) + 500000L; Y0 = 0; point.lon = DoubleAdd(point.lon, doubleToDouble(NEMA_Fast_Uint64ToDouble(X0))); point.lat = DoubleAdd(point.lat, doubleToDouble(NEMA_Fast_Uint64ToDouble(Y0))); return point; } ////////////////////////////////////////////////////////////////////////// //must init with local two reference points including lat, lon and the length //betweeb two reference points void Map_Init(Map* pMap, double _lat, double _lon, double lat, double lon, double x, double y, double length) { Double dic; pMap->X = doubleToDouble(x); pMap->Y = doubleToDouble(y); pMap->_dPoint.lat = doubleToDouble(_lat); pMap->_dPoint.lon = doubleToDouble(_lon); pMap->dPoint.lat = doubleToDouble(lat); pMap->_dPoint.lon = doubleToDouble(lon); pMap->_gsPoint = Map_BLToGauss(pMap->_dPoint.lat, pMap->_dPoint.lon); pMap->gsPoint = Map_BLToGauss(pMap->dPoint.lat, pMap->dPoint.lon); pMap->a = DoubleSub(pMap->_gsPoint.lat, pMap->gsPoint.lat); pMap->b = DoubleSub(pMap->_gsPoint.lon, pMap->gsPoint.lon); dic = FastSqrtID(DoubleAdd(DoubleMul(pMap->a, pMap->a), DoubleMul(pMap->b, pMap->b))); pMap->c = DoubleDiv(intToDouble(1), dic); pMap->bl = DoubleMul(doubleToDouble(length), dic); } void Map_GetXY(Map* pMap, double lat, double lon, double *x, double *y) { Double d, e, f, gf, g, h, i; DoublePoint gs = Map_BLToGauss(doubleToDouble(lat), doubleToDouble(lon)); d = DoubleSub(gs.lon, pMap->gsPoint.lon); d = doubleToDouble(FastAbsD(DoubleTodouble(d))); gf = DoubleSub(gs.lat, pMap->gsPoint.lat); gf = doubleToDouble(FastAbsD(DoubleTodouble(gf))); // if (lon > DoubleTodouble(pMap->_dPoint.lon)){ e = DoubleDiv(DoubleMul(d, pMap->c), pMap->b); //e = d * c / b f = DoubleDiv(DoubleMul(pMap->a, e), pMap->c); //f = a * e / c g = DoubleSub(gf, f); h = DoubleDiv(DoubleMul(pMap->a, g), pMap->c); //h = a * g / c i = DoubleDiv(DoubleMul(pMap->a, g), pMap->c); //i = b * g / c //lon mean X, lat mean Y //x = X - i * bl; //y = Y + (h + e) * bl; *x = DoubleTodouble(DoubleSub(pMap->X, DoubleMul(i, pMap->bl))); *y = DoubleTodouble(DoubleAdd(pMap->Y, DoubleMul(DoubleAdd(h, e), pMap->bl))); } else{ e = DoubleDiv(DoubleMul(d, pMap->c), pMap->a); //e = d * c / a; f = DoubleDiv(DoubleMul(e, pMap->b), pMap->c); //f = e * b / c; g = DoubleSub(gf, f); h = DoubleDiv(DoubleMul(pMap->a, g), pMap->c); //h = a * g / c; i = DoubleDiv(DoubleMul(pMap->a, g), pMap->c); //i = b * g / c; //lon mean X, lat mean Y; //x = X - (e + i) * bl; //y = Y + h * bl; *x = DoubleTodouble(DoubleSub(pMap->X, DoubleMul(DoubleAdd(e, i), pMap->bl))); *y = DoubleTodouble(DoubleAdd(pMap->Y, DoubleMul(h, pMap->bl))); } } ================================================ FILE: Gps/src/Nema.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "Memory.h" #include "Nema.h" #include "Queue.h" //gobal queue variable Queue mQueue; Queue *pQueue = &mQueue; // static u8 HexTable[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F }; static const float ReciprocalFloat[] = { 1.0f, 0.1f, 0.01f, 0.001f, 0.0001f, 0.00001f, 0.000001f, 0.0000001f, 0.00000001f, 0.000000001f, 0.0000000001f, 0.00000000001f, 0.000000000001f }; ////////////////////////////////////////////////////////////////////////// float NEMA_FastAtoF(s8 *p, s32 len) { u32 integral, fractional, nReciprocal, sign = 0; s32 i, hasfractional = 0; union { float f; u32 i; } fReciprocal; ////////////////////////////////////////////////////////////////////////// // if (*p++ == '-') { sign = 1; } // ////////////////////////////////////////////////////////////////////////// for (integral = 0, i = 0; *p != '.' && i++ < len; p++) { integral = integral * 10 + (*p - '0'); } // Get digits after decimal point, if any. if (*p++ == '.') { i++; hasfractional = 1; for (fractional = 0; i++ < len; p++) { fractional = fractional * 10 + (*p - '0'); nReciprocal++; } } if (!hasfractional){ return NEMA_Fast_UintToFloat(integral); } else{ fReciprocal.f = ReciprocalFloat[nReciprocal]; if(!sign){ //return NEMA_Fast_UintToFloat(integral) + NEMA_Fast_UintToFloat(fractional) * NEMA_Fast_FloatInverse(NEMA_Fast_UintToFloat(decimal)); return NEMA_Fast_UintToFloat(integral) + NEMA_Fast_UintToFloat(fractional) * fReciprocal.f; } //fReciprocal.f = NEMA_Fast_UintToFloat(integral) + NEMA_Fast_UintToFloat(fractional) * NEMA_Fast_FloatInverse(NEMA_Fast_UintToFloat(decimal)); fReciprocal.f = NEMA_Fast_UintToFloat(integral) + NEMA_Fast_UintToFloat(fractional) * fReciprocal.f; fReciprocal.i |= 0x80000000; return fReciprocal.f; } } static const double ReciprocalDouble[] = { 1.0, 0.1, 0.01, 0.001, 0.0001, 0.00001, 0.000001, 0.0000001, 0.00000001, 0.000000001, 0.0000000001, 0.00000000001, 0.000000000001 }; double NEMA_FastAtoD(s8 *p, s32 len) { u32 integral, fractional, nReciprocal, sign = 0; s32 i, hasfractional = 0; union { double d; u64 i; } dReciprocal; ////////////////////////////////////////////////////////////////////////// // if (*p++ == '-') { sign = 1; } // for (integral = 0, i = 0; *p != '.' && i++ < len; p++) { integral = integral * 10 + (*p - '0'); } // Get digits after decimal point, if any. if (*p++ == '.') { i++; hasfractional = 1; for (fractional = 0; i++ < len; p++) { fractional = fractional * 10 + (*p - '0'); nReciprocal++; } } if (!hasfractional){ return NEMA_Fast_Uint64ToDouble(integral); } else{ dReciprocal.d = ReciprocalDouble[nReciprocal]; if(!sign){ //return NEMA_Fast_Uint64ToDouble(integral) + NEMA_Fast_Uint64ToDouble(fractional) * NEMA_Fast_DoubleInverse(NEMA_Fast_Uint64ToDouble(decimal)); return NEMA_Fast_Uint64ToDouble(integral) + NEMA_Fast_Uint64ToDouble(fractional) * dReciprocal.d; } //dReciprocal.d NEMA_Fast_Uint64ToDouble(integral) + NEMA_Fast_Uint64ToDouble(fractional) * NEMA_Fast_DoubleInverse(NEMA_Fast_Uint64ToDouble(decimal)); dReciprocal.d = NEMA_Fast_Uint64ToDouble(integral) + NEMA_Fast_Uint64ToDouble(fractional) * dReciprocal.d; dReciprocal.i |= (u64)0x8000000000000000; return dReciprocal.d; } } s32 NEMA_FastAtoI(s8 *p, s32 len) { s32 i, integral; u32 sign = 0; ////////////////////////////////////////////////////////////////////////// // if (*p++ == '-') { sign = 1; } // ////////////////////////////////////////////////////////////////////////// for (integral = 0, i = 0;i++ < len; p++) { integral = integral * 10 + (*p - '0'); } if(!sign){ return -integral; } return integral; } static const s8 *NEMA_MessageID[] = { //Number of fields except Message ID, Checksum, Carriage return and line feed "GGA", //17 - 3 = 14 "GSA", //21 - 3 = 18 //"GSV", //8..16 - 3 = 5..13 "RMC", //16 - 3 = 13 "VTG", //12 - 3 = 9 }; s16 NEMA_GetMessage(void *data, s32* iType) { Buff buff; s32 ret; u16 queueSize = Queue_Size(pQueue); u16 useQueueSize = 0, numFields = 0; s16 find = 0, SVs = 0; // NEMA_MessageType messageType = GPNON; *iType = GPNON; if(!queueSize){ return -1; } for(; useQueueSize < queueSize; useQueueSize++){ ret = Queue_Dequeue(pQueue, &buff); if(ret == 0){ ////////////////////////////////////////////////////////////////////////// //find messageID if(find == 0){ if(buff.Len != NEMA_MESSAGEID_SIZE){ continue; } else if(0 == MemCmp((u8*)(buff.Buff + 2), (u8*)NEMA_MessageID[0], 3)){ messageType = GPGGA; numFields = 14; } else if(0 == MemCmp((u8*)(buff.Buff + 2), (u8*)NEMA_MessageID[1], 3)){ messageType = GPGSA; numFields = 18; } else if(0 == MemCmp((u8*)(buff.Buff + 2), (u8*)NEMA_MessageID[2], 3)){ messageType = GPRMC; numFields = 13; } else if(0 == MemCmp((u8*)(buff.Buff + 2), (u8*)NEMA_MessageID[3], 3)){ messageType = GPVTG; numFields = 9; } find = 1; break; } } } if(find && (numFields <= queueSize - useQueueSize)){ switch(numFields){ case 14: //GGA ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPGGA)data)->time = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPGGA)data)->lat = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: North/South indicator always 'N' or 'S' ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPGGA)data)->lon = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: East/West indicator always 'E' or 'W' ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPGGA)data)->quality = NEMA_FastAtoI(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPGGA)data)->numSV = NEMA_FastAtoI(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPGGA)data)->HDOP = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPGGA)data)->alt = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: Altitude units: meters (fixed field) always 'M' ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPGGA)data)->sep = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: Separation units: meters always 'M' ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: Age of differential corrections (blank when DGPS is not used) ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: ID of station providing differential corrections (blank when DGPS is not used) break; case 18: //GSA ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: Operation mode always 'A' ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPGSA)data)->navMode = NEMA_FastAtoI(buff.Buff, buff.Len); for(;SVs < NMEA_MAXSVS; SVs++){ ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPGSA)data)->sv[SVs] = NEMA_FastAtoI(buff.Buff, buff.Len); } ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPGSA)data)->PDOP = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPGSA)data)->HDOP = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPGSA)data)->VDOP = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: GNSS System ID break; case 13: //RMC ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPRMC)data)->time = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: status always 'A' ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPRMC)data)->lat = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: North/South indicator always 'N' or 'S' ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPRMC)data)->lon = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: East/West indicator always 'E' or 'W' ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPRMC)data)->spd = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPRMC)data)->cog = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPRMC)data)->date = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: Magnetic variation value (blank - not supported) ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: Magnetic variation E/W indicator (blank - notsupported) ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: Mode Indicator ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: Navigational status indicator 'V' break; case 9: //VTG ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPVTG)data)->cogt = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: true always 'T' ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPVTG)data)->cogm = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: magnetic always 'M' ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPVTG)data)->knots = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: knots always 'N' ret = Queue_Dequeue(pQueue, &buff); ((PnmeaGPVTG)data)->kph = NEMA_FastAtoD(buff.Buff, buff.Len); ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: kilometers per hour always 'K' ret = Queue_Dequeue(pQueue, &buff); //skip Fixed field: Mode Indicator always 'A' break; } *iType = messageType; } return find; } u16 NEMA_Parser(s8 *p, u16 len) { s8 *dataStart = p; s8 *dataEnd = p + len; u16 size, useSize = 0; u16 startPos, startCRCPos, endCRCPos; s8 null = 0; s8 crc, calCRC = 0; ////////////////////////////////////////////////////////////////////////// u16 findStart = 0, findEnd = 0; s32 error = 0; ////////////////////////////////////////////////////////////////////////// // for(startPos = useSize;((dataStart < dataEnd) && (!findEnd) && (error == 0)); dataStart++, useSize++){ switch(*dataStart) { //find start code '$' case '$': startPos = useSize + 1; findStart = 1; startCRCPos = startPos; break; //find fields case '*': endCRCPos = useSize; case ',': size = useSize - startPos; //A null field if (!size){ error = Queue_Enqueue(pQueue, &null, 1); } else{ error = Queue_Enqueue(pQueue, p + startPos, size); } startPos = useSize + 1; break; //find tail //'*' + [CRC] + '\r' + '\n' case '\n': findEnd = 1; crc = NEMA_FastCRCtoI(p + startPos, HexTable); break; } } if(findStart && findEnd){ for (;startCRCPos < endCRCPos; startCRCPos++){ calCRC ^= p[startCRCPos]; } if (crc != calCRC){ //why will crc be different? //that means something bad happened in serial communication } } if(error < 0){ //why will queue be fully? //error handler } //return len - useSize; return useSize; } double NMEA_Convert2Degrees(double val) { Double onehundred = {100.0f, 0.0f}; Double sixty = {60.0f, 0.0f}; // double degree = ((int)(val / 100)); Double dval = doubleToDouble(val); Double ddegree = DoubleDiv(dval, onehundred); double degree = (s32)DoubleTodouble(ddegree); //val = degree + (val - degree * 100) / 60; ddegree = doubleToDouble(degree); dval = DoubleAdd(ddegree, DoubleDiv(DoubleSub(dval, DoubleMul(ddegree, onehundred)), sixty)); return DoubleTodouble(dval); } double NMEA_Degree2Radian(double val) { Double dret = DoubleMul(doubleToDouble(val), doubleToDouble(0.01745329251994329576923690768489)); return DoubleTodouble(dret); } Double NMEA_Degree2RadianD(Double val) { return DoubleMul(val, doubleToDouble(0.01745329251994329576923690768489)); } double NMEA_Radian2Degree(double val) { Double dret = DoubleMul(doubleToDouble(val), doubleToDouble(57.295779513082320876798154814105)); return DoubleTodouble(dret); } ================================================ FILE: LICENSE ================================================ The MIT License (MIT) Copyright (c) 2015 suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h ================================================ /** ****************************************************************************** * @file stm32f4xx.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F4xx devices. * * The file is the unique include file that the application programmer * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The device used in the target application * - To use or not the peripherals drivers in application code(i.e. * code will be based on direct access to peripherals registers * rather than drivers API), this option is controlled by * "#define USE_STDPERIPH_DRIVER" * - To change few application-specific parameters such as the HSE * crystal frequency * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripherals registers hardware * ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f4xx * @{ */ #ifndef __STM32F4xx_H #define __STM32F4xx_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** @addtogroup Library_configuration_section * @{ */ /* Uncomment the line below according to the target STM32 device used in your application */ #if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) /* #define STM32F40_41xxx */ /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG, STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE, STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ /* #define STM32F427_437xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II, STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */ /* #define STM32F429_439xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI, STM32F439IG and STM32F439II Devices */ /* #define STM32F401xx */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CExx, STM32F401RE, STM32F401VE Devices */ #endif /* Old STM32F40XX definition, maintained for legacy purpose */ #ifdef STM32F40XX #define STM32F40_41xxx #endif /* STM32F40XX */ /* Old STM32F427X definition, maintained for legacy purpose */ #ifdef STM32F427X #define STM32F427_437xx #endif /* STM32F427X */ /* Tip: To avoid modifying this file each time you need to switch between these devices, you can define the device in your toolchain compiler preprocessor. */ #if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" #endif #if !defined (USE_STDPERIPH_DRIVER) /** * @brief Comment the line below if you will not use the peripherals drivers. In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers */ /*#define USE_STDPERIPH_DRIVER */ #endif /* USE_STDPERIPH_DRIVER */ /** * @brief In the following line adjust the value of External High Speed oscillator (HSE) used in your application Tip: To avoid modifying this file each time you need to use different HSE, you can define the HSE value in your toolchain compiler preprocessor. */ #if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)12000000) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ /** * @brief In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ #if !defined (HSE_STARTUP_TIMEOUT) #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) /*!< Time out for HSE start up */ #endif /* HSE_STARTUP_TIMEOUT */ #if !defined (HSI_VALUE) #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** * @brief STM32F4XX Standard Peripherals Library version number V1.3.0 */ #define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ #define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\ |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\ |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\ |(__STM32F4XX_STDPERIPH_VERSION_RC)) /** * @} */ /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ #define __CM4_REV 0x0001 /*!< Core revision r0p1 */ #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1 /*!< FPU present */ /** * @brief STM32F4XX Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum IRQn { /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ /****** STM32 specific Interrupt Numbers **********************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ RCC_IRQn = 5, /*!< RCC global Interrupt */ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ #if defined (STM32F40_41xxx) CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ FSMC_IRQn = 48, /*!< FSMC global Interrupt */ SDIO_IRQn = 49, /*!< SDIO global Interrupt */ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt */ UART5_IRQn = 53, /*!< UART5 global Interrupt */ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ TIM7_IRQn = 55, /*!< TIM7 global interrupt */ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ ETH_IRQn = 61, /*!< Ethernet global Interrupt */ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ USART6_IRQn = 71, /*!< USART6 global interrupt */ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ DCMI_IRQn = 78, /*!< DCMI global interrupt */ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ FPU_IRQn = 81 /*!< FPU global interrupt */ #endif /* STM32F40_41xxx */ #if defined (STM32F427_437xx) CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ FMC_IRQn = 48, /*!< FMC global Interrupt */ SDIO_IRQn = 49, /*!< SDIO global Interrupt */ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt */ UART5_IRQn = 53, /*!< UART5 global Interrupt */ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ TIM7_IRQn = 55, /*!< TIM7 global interrupt */ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ ETH_IRQn = 61, /*!< Ethernet global Interrupt */ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ USART6_IRQn = 71, /*!< USART6 global interrupt */ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ DCMI_IRQn = 78, /*!< DCMI global interrupt */ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ FPU_IRQn = 81, /*!< FPU global interrupt */ UART7_IRQn = 82, /*!< UART7 global interrupt */ UART8_IRQn = 83, /*!< UART8 global interrupt */ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ #endif /* STM32F427_437xx */ #if defined (STM32F429_439xx) CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ FMC_IRQn = 48, /*!< FMC global Interrupt */ SDIO_IRQn = 49, /*!< SDIO global Interrupt */ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt */ UART5_IRQn = 53, /*!< UART5 global Interrupt */ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ TIM7_IRQn = 55, /*!< TIM7 global interrupt */ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ ETH_IRQn = 61, /*!< Ethernet global Interrupt */ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ USART6_IRQn = 71, /*!< USART6 global interrupt */ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ DCMI_IRQn = 78, /*!< DCMI global interrupt */ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ FPU_IRQn = 81, /*!< FPU global interrupt */ UART7_IRQn = 82, /*!< UART7 global interrupt */ UART8_IRQn = 83, /*!< UART8 global interrupt */ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ LTDC_IRQn = 88, /*!< LTDC global Interrupt */ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ #endif /* STM32F429_439xx */ #if defined (STM32F401xx) EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ SDIO_IRQn = 49, /*!< SDIO global Interrupt */ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ USART6_IRQn = 71, /*!< USART6 global interrupt */ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ FPU_IRQn = 81, /*!< FPU global interrupt */ SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ #endif /* STM32F401xx */ } IRQn_Type; /** * @} */ #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ #include "system_stm32f4xx.h" #include /** @addtogroup Exported_types * @{ */ /*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ typedef int32_t s32; typedef int16_t s16; typedef int8_t s8; typedef const int32_t sc32; /*!< Read Only */ typedef const int16_t sc16; /*!< Read Only */ typedef const int8_t sc8; /*!< Read Only */ typedef __IO int32_t vs32; typedef __IO int16_t vs16; typedef __IO int8_t vs8; typedef __I int32_t vsc32; /*!< Read Only */ typedef __I int16_t vsc16; /*!< Read Only */ typedef __I int8_t vsc8; /*!< Read Only */ typedef uint32_t u32; typedef uint16_t u16; typedef uint8_t u8; typedef const uint32_t uc32; /*!< Read Only */ typedef const uint16_t uc16; /*!< Read Only */ typedef const uint8_t uc8; /*!< Read Only */ typedef __IO uint32_t vu32; typedef __IO uint16_t vu16; typedef __IO uint8_t vu8; typedef __I uint32_t vuc32; /*!< Read Only */ typedef __I uint16_t vuc16; /*!< Read Only */ typedef __I uint8_t vuc8; /*!< Read Only */ typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; /** * @} */ /** @addtogroup Peripheral_registers_structures * @{ */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ } ADC_TypeDef; typedef struct { __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual AND triple modes, Address offset: ADC1 base address + 0x308 */ } ADC_Common_TypeDef; /** * @brief Controller Area Network TxMailBox */ typedef struct { __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ __IO uint32_t TDLR; /*!< CAN mailbox data low register */ __IO uint32_t TDHR; /*!< CAN mailbox data high register */ } CAN_TxMailBox_TypeDef; /** * @brief Controller Area Network FIFOMailBox */ typedef struct { __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ } CAN_FIFOMailBox_TypeDef; /** * @brief Controller Area Network FilterRegister */ typedef struct { __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ } CAN_FilterRegister_TypeDef; /** * @brief Controller Area Network */ typedef struct { __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ uint32_t RESERVED2; /*!< Reserved, 0x208 */ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ uint32_t RESERVED3; /*!< Reserved, 0x210 */ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ uint32_t RESERVED4; /*!< Reserved, 0x218 */ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ } CAN_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ uint8_t RESERVED0; /*!< Reserved, 0x05 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ } CRC_TypeDef; /** * @brief Digital to Analog Converter */ typedef struct { __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ } DAC_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ }DBGMCU_TypeDef; /** * @brief DCMI */ typedef struct { __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ } DCMI_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; typedef struct { __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ } DMA_TypeDef; /** * @brief DMA2D Controller */ typedef struct { __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ } DMA2D_TypeDef; /** * @brief Ethernet MAC */ typedef struct { __IO uint32_t MACCR; __IO uint32_t MACFFR; __IO uint32_t MACHTHR; __IO uint32_t MACHTLR; __IO uint32_t MACMIIAR; __IO uint32_t MACMIIDR; __IO uint32_t MACFCR; __IO uint32_t MACVLANTR; /* 8 */ uint32_t RESERVED0[2]; __IO uint32_t MACRWUFFR; /* 11 */ __IO uint32_t MACPMTCSR; uint32_t RESERVED1[2]; __IO uint32_t MACSR; /* 15 */ __IO uint32_t MACIMR; __IO uint32_t MACA0HR; __IO uint32_t MACA0LR; __IO uint32_t MACA1HR; __IO uint32_t MACA1LR; __IO uint32_t MACA2HR; __IO uint32_t MACA2LR; __IO uint32_t MACA3HR; __IO uint32_t MACA3LR; /* 24 */ uint32_t RESERVED2[40]; __IO uint32_t MMCCR; /* 65 */ __IO uint32_t MMCRIR; __IO uint32_t MMCTIR; __IO uint32_t MMCRIMR; __IO uint32_t MMCTIMR; /* 69 */ uint32_t RESERVED3[14]; __IO uint32_t MMCTGFSCCR; /* 84 */ __IO uint32_t MMCTGFMSCCR; uint32_t RESERVED4[5]; __IO uint32_t MMCTGFCR; uint32_t RESERVED5[10]; __IO uint32_t MMCRFCECR; __IO uint32_t MMCRFAECR; uint32_t RESERVED6[10]; __IO uint32_t MMCRGUFCR; uint32_t RESERVED7[334]; __IO uint32_t PTPTSCR; __IO uint32_t PTPSSIR; __IO uint32_t PTPTSHR; __IO uint32_t PTPTSLR; __IO uint32_t PTPTSHUR; __IO uint32_t PTPTSLUR; __IO uint32_t PTPTSAR; __IO uint32_t PTPTTHR; __IO uint32_t PTPTTLR; __IO uint32_t RESERVED8; __IO uint32_t PTPTSSR; uint32_t RESERVED9[565]; __IO uint32_t DMABMR; __IO uint32_t DMATPDR; __IO uint32_t DMARPDR; __IO uint32_t DMARDLAR; __IO uint32_t DMATDLAR; __IO uint32_t DMASR; __IO uint32_t DMAOMR; __IO uint32_t DMAIER; __IO uint32_t DMAMFBOCR; __IO uint32_t DMARSWTR; uint32_t RESERVED10[8]; __IO uint32_t DMACHTDR; __IO uint32_t DMACHRDR; __IO uint32_t DMACHTBAR; __IO uint32_t DMACHRBAR; } ETH_TypeDef; /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ } EXTI_TypeDef; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ } FLASH_TypeDef; #if defined (STM32F40_41xxx) /** * @brief Flexible Static Memory Controller */ typedef struct { __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ } FSMC_Bank1_TypeDef; /** * @brief Flexible Static Memory Controller Bank1E */ typedef struct { __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ } FSMC_Bank1E_TypeDef; /** * @brief Flexible Static Memory Controller Bank2 */ typedef struct { __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ uint32_t RESERVED0; /*!< Reserved, 0x70 */ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ } FSMC_Bank2_TypeDef; /** * @brief Flexible Static Memory Controller Bank3 */ typedef struct { __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ uint32_t RESERVED0; /*!< Reserved, 0x90 */ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ } FSMC_Bank3_TypeDef; /** * @brief Flexible Static Memory Controller Bank4 */ typedef struct { __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ } FSMC_Bank4_TypeDef; #endif /* STM32F40_41xxx */ #if defined (STM32F427_437xx) || defined (STM32F429_439xx) /** * @brief Flexible Memory Controller */ typedef struct { __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ } FMC_Bank1_TypeDef; /** * @brief Flexible Memory Controller Bank1E */ typedef struct { __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ } FMC_Bank1E_TypeDef; /** * @brief Flexible Memory Controller Bank2 */ typedef struct { __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ uint32_t RESERVED0; /*!< Reserved, 0x70 */ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ } FMC_Bank2_TypeDef; /** * @brief Flexible Memory Controller Bank3 */ typedef struct { __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ uint32_t RESERVED0; /*!< Reserved, 0x90 */ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ } FMC_Bank3_TypeDef; /** * @brief Flexible Memory Controller Bank4 */ typedef struct { __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ } FMC_Bank4_TypeDef; /** * @brief Flexible Memory Controller Bank5_6 */ typedef struct { __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ } FMC_Bank5_6_TypeDef; #endif /* STM32F427_437xx || STM32F429_439xx */ /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ } GPIO_TypeDef; /** * @brief System configuration controller */ typedef struct { __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ } SYSCFG_TypeDef; /** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ uint16_t RESERVED0; /*!< Reserved, 0x02 */ __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ uint16_t RESERVED2; /*!< Reserved, 0x0A */ __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ uint16_t RESERVED3; /*!< Reserved, 0x0E */ __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ uint16_t RESERVED4; /*!< Reserved, 0x12 */ __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ uint16_t RESERVED5; /*!< Reserved, 0x16 */ __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ uint16_t RESERVED6; /*!< Reserved, 0x1A */ __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ uint16_t RESERVED7; /*!< Reserved, 0x1E */ __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ uint16_t RESERVED8; /*!< Reserved, 0x22 */ __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ uint16_t RESERVED9; /*!< Reserved, 0x26 */ } I2C_TypeDef; /** * @brief Independent WATCHDOG */ typedef struct { __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ } IWDG_TypeDef; /** * @brief LCD-TFT Display Controller */ typedef struct { uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ } LTDC_TypeDef; /** * @brief LCD-TFT Display layer x Controller */ typedef struct { __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ uint32_t RESERVED0[2]; /*!< Reserved */ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ uint32_t RESERVED1[3]; /*!< Reserved */ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ } LTDC_Layer_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ } PWR_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ uint32_t RESERVED0; /*!< Reserved, 0x1C */ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ uint32_t RESERVED2; /*!< Reserved, 0x3C */ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ uint32_t RESERVED4; /*!< Reserved, 0x5C */ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ } RCC_TypeDef; /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ uint32_t RESERVED7; /*!< Reserved, 0x4C */ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ } RTC_TypeDef; /** * @brief Serial Audio Interface */ typedef struct { __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ } SAI_TypeDef; typedef struct { __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ } SAI_Block_TypeDef; /** * @brief SD host Interface */ typedef struct { __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ } SDIO_TypeDef; /** * @brief Serial Peripheral Interface */ typedef struct { __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ uint16_t RESERVED0; /*!< Reserved, 0x02 */ __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ uint16_t RESERVED2; /*!< Reserved, 0x0A */ __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ uint16_t RESERVED3; /*!< Reserved, 0x0E */ __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ uint16_t RESERVED4; /*!< Reserved, 0x12 */ __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ uint16_t RESERVED5; /*!< Reserved, 0x16 */ __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ uint16_t RESERVED6; /*!< Reserved, 0x1A */ __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ uint16_t RESERVED7; /*!< Reserved, 0x1E */ __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ uint16_t RESERVED8; /*!< Reserved, 0x22 */ } SPI_TypeDef; /** * @brief TIM */ typedef struct { __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ uint16_t RESERVED0; /*!< Reserved, 0x02 */ __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ uint16_t RESERVED2; /*!< Reserved, 0x0A */ __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ uint16_t RESERVED3; /*!< Reserved, 0x0E */ __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ uint16_t RESERVED4; /*!< Reserved, 0x12 */ __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ uint16_t RESERVED5; /*!< Reserved, 0x16 */ __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ uint16_t RESERVED6; /*!< Reserved, 0x1A */ __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ uint16_t RESERVED7; /*!< Reserved, 0x1E */ __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ uint16_t RESERVED8; /*!< Reserved, 0x22 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ uint16_t RESERVED9; /*!< Reserved, 0x2A */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ uint16_t RESERVED10; /*!< Reserved, 0x32 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ uint16_t RESERVED11; /*!< Reserved, 0x46 */ __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ uint16_t RESERVED12; /*!< Reserved, 0x4A */ __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ uint16_t RESERVED13; /*!< Reserved, 0x4E */ __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ uint16_t RESERVED14; /*!< Reserved, 0x52 */ } TIM_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ uint16_t RESERVED0; /*!< Reserved, 0x02 */ __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ uint16_t RESERVED2; /*!< Reserved, 0x0A */ __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ uint16_t RESERVED3; /*!< Reserved, 0x0E */ __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ uint16_t RESERVED4; /*!< Reserved, 0x12 */ __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ uint16_t RESERVED5; /*!< Reserved, 0x16 */ __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ uint16_t RESERVED6; /*!< Reserved, 0x1A */ } USART_TypeDef; /** * @brief Window WATCHDOG */ typedef struct { __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; /** * @brief Crypto Processor */ typedef struct { __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ } CRYP_TypeDef; /** * @brief HASH */ typedef struct { __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ } HASH_TypeDef; /** * @brief HASH_DIGEST */ typedef struct { __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ } HASH_DIGEST_TypeDef; /** * @brief RNG */ typedef struct { __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ } RNG_TypeDef; /** * @} */ /** @addtogroup Peripheral_memory_map * @{ */ #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ #if defined (STM32F40_41xxx) #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ #endif /* STM32F40_41xxx */ #if defined (STM32F427_437xx) || defined (STM32F429_439xx) #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */ #endif /* STM32F427_437xx || STM32F429_439xx */ #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ #define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */ #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE #define SRAM_BB_BASE SRAM1_BB_BASE /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) /*!< APB1 peripherals */ #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) #define TIM12_BASE (APB1PERIPH_BASE + 0x1800) #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) #define TIM14_BASE (APB1PERIPH_BASE + 0x2000) #define RTC_BASE (APB1PERIPH_BASE + 0x2800) #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) #define USART2_BASE (APB1PERIPH_BASE + 0x4400) #define USART3_BASE (APB1PERIPH_BASE + 0x4800) #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) #define UART5_BASE (APB1PERIPH_BASE + 0x5000) #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) #define CAN2_BASE (APB1PERIPH_BASE + 0x6800) #define PWR_BASE (APB1PERIPH_BASE + 0x7000) #define DAC_BASE (APB1PERIPH_BASE + 0x7400) #define UART7_BASE (APB1PERIPH_BASE + 0x7800) #define UART8_BASE (APB1PERIPH_BASE + 0x7C00) /*!< APB2 peripherals */ #define TIM1_BASE (APB2PERIPH_BASE + 0x0000) #define TIM8_BASE (APB2PERIPH_BASE + 0x0400) #define USART1_BASE (APB2PERIPH_BASE + 0x1000) #define USART6_BASE (APB2PERIPH_BASE + 0x1400) #define ADC1_BASE (APB2PERIPH_BASE + 0x2000) #define ADC2_BASE (APB2PERIPH_BASE + 0x2100) #define ADC3_BASE (APB2PERIPH_BASE + 0x2200) #define ADC_BASE (APB2PERIPH_BASE + 0x2300) #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) #define SPI4_BASE (APB2PERIPH_BASE + 0x3400) #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) #define TIM9_BASE (APB2PERIPH_BASE + 0x4000) #define TIM10_BASE (APB2PERIPH_BASE + 0x4400) #define TIM11_BASE (APB2PERIPH_BASE + 0x4800) #define SPI5_BASE (APB2PERIPH_BASE + 0x5000) #define SPI6_BASE (APB2PERIPH_BASE + 0x5400) #define SAI1_BASE (APB2PERIPH_BASE + 0x5800) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) #define LTDC_BASE (APB2PERIPH_BASE + 0x6800) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104) /*!< AHB1 peripherals */ #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400) #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800) #define CRC_BASE (AHB1PERIPH_BASE + 0x3000) #define RCC_BASE (AHB1PERIPH_BASE + 0x3800) #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) #define DMA1_Stream0_BASE (DMA1_BASE + 0x010) #define DMA1_Stream1_BASE (DMA1_BASE + 0x028) #define DMA1_Stream2_BASE (DMA1_BASE + 0x040) #define DMA1_Stream3_BASE (DMA1_BASE + 0x058) #define DMA1_Stream4_BASE (DMA1_BASE + 0x070) #define DMA1_Stream5_BASE (DMA1_BASE + 0x088) #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) #define DMA2_Stream0_BASE (DMA2_BASE + 0x010) #define DMA2_Stream1_BASE (DMA2_BASE + 0x028) #define DMA2_Stream2_BASE (DMA2_BASE + 0x040) #define DMA2_Stream3_BASE (DMA2_BASE + 0x058) #define DMA2_Stream4_BASE (DMA2_BASE + 0x070) #define DMA2_Stream5_BASE (DMA2_BASE + 0x088) #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) #define ETH_BASE (AHB1PERIPH_BASE + 0x8000) #define ETH_MAC_BASE (ETH_BASE) #define ETH_MMC_BASE (ETH_BASE + 0x0100) #define ETH_PTP_BASE (ETH_BASE + 0x0700) #define ETH_DMA_BASE (ETH_BASE + 0x1000) #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000) /*!< AHB2 peripherals */ #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) #define HASH_BASE (AHB2PERIPH_BASE + 0x60400) #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710) #define RNG_BASE (AHB2PERIPH_BASE + 0x60800) #if defined (STM32F40_41xxx) /*!< FSMC Bankx registers base address */ #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) #endif /* STM32F40_41xxx */ #if defined (STM32F427_437xx) || defined (STM32F429_439xx) /*!< FMC Bankx registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) #define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) #endif /* STM32F427_437xx || STM32F429_439xx */ /* Debug MCU registers base address */ #define DBGMCU_BASE ((uint32_t )0xE0042000) /** * @} */ /** @addtogroup Peripheral_declaration * @{ */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) #define TIM5 ((TIM_TypeDef *) TIM5_BASE) #define TIM6 ((TIM_TypeDef *) TIM6_BASE) #define TIM7 ((TIM_TypeDef *) TIM7_BASE) #define TIM12 ((TIM_TypeDef *) TIM12_BASE) #define TIM13 ((TIM_TypeDef *) TIM13_BASE) #define TIM14 ((TIM_TypeDef *) TIM14_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define WWDG ((WWDG_TypeDef *) WWDG_BASE) #define IWDG ((IWDG_TypeDef *) IWDG_BASE) #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) #define SPI2 ((SPI_TypeDef *) SPI2_BASE) #define SPI3 ((SPI_TypeDef *) SPI3_BASE) #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) #define USART3 ((USART_TypeDef *) USART3_BASE) #define UART4 ((USART_TypeDef *) UART4_BASE) #define UART5 ((USART_TypeDef *) UART5_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define CAN2 ((CAN_TypeDef *) CAN2_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define DAC ((DAC_TypeDef *) DAC_BASE) #define UART7 ((USART_TypeDef *) UART7_BASE) #define UART8 ((USART_TypeDef *) UART8_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define TIM8 ((TIM_TypeDef *) TIM8_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define USART6 ((USART_TypeDef *) USART6_BASE) #define ADC ((ADC_Common_TypeDef *) ADC_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC2 ((ADC_TypeDef *) ADC2_BASE) #define ADC3 ((ADC_TypeDef *) ADC3_BASE) #define SDIO ((SDIO_TypeDef *) SDIO_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define SPI4 ((SPI_TypeDef *) SPI4_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define TIM9 ((TIM_TypeDef *) TIM9_BASE) #define TIM10 ((TIM_TypeDef *) TIM10_BASE) #define TIM11 ((TIM_TypeDef *) TIM11_BASE) #define SPI5 ((SPI_TypeDef *) SPI5_BASE) #define SPI6 ((SPI_TypeDef *) SPI6_BASE) #define SAI1 ((SAI_TypeDef *) SAI1_BASE) #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) #define ETH ((ETH_TypeDef *) ETH_BASE) #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) #define DCMI ((DCMI_TypeDef *) DCMI_BASE) #define CRYP ((CRYP_TypeDef *) CRYP_BASE) #define HASH ((HASH_TypeDef *) HASH_BASE) #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) #define RNG ((RNG_TypeDef *) RNG_BASE) #if defined (STM32F40_41xxx) #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) #endif /* STM32F40_41xxx */ #if defined (STM32F427_437xx) || defined (STM32F429_439xx) #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) #define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE) #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) #endif /* STM32F427_437xx || STM32F429_439xx */ #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) /** * @} */ /** @addtogroup Exported_constants * @{ */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ /******************************************************************************/ /* */ /* Analog to Digital Converter */ /* */ /******************************************************************************/ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD ((uint8_t)0x01) /*!
© COPYRIGHT 2013 STMicroelectronics
* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f4xx_system * @{ */ /** * @brief Define to prevent recursive inclusion */ #ifndef __SYSTEM_STM32F4XX_H #define __SYSTEM_STM32F4XX_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup STM32F4xx_System_Includes * @{ */ /** * @} */ /** @addtogroup STM32F4xx_System_Exported_types * @{ */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ /** * @} */ /** @addtogroup STM32F4xx_System_Exported_Constants * @{ */ /** * @} */ /** @addtogroup STM32F4xx_System_Exported_Macros * @{ */ /** * @} */ /** @addtogroup STM32F4xx_System_Exported_Functions * @{ */ extern void SystemInit(void); extern void SystemCoreClockUpdate(void); /** * @} */ #ifdef __cplusplus } #endif #endif /*__SYSTEM_STM32F4XX_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Release_Notes.html ================================================ Release Notes for STM32F4xx CMSIS


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Release Notes for STM32F4xx CMSIS

Copyright 2013 STMicroelectronics

 

Contents

  1. STM32F4xx CMSIS update History
  2. License

STM32F4xx CMSIS update History

V1.3.0 / 08-November-2013

Main Changes

  • Add support of STM32F401xExx devices

  • Update startup files "startup_stm32f401xx.s" for EWARM, MDK-ARM, TrueSTUDIO and Ride toolchains: Add SPI4 interrupt handler entry in the vector table

V1.2.1 / 19-September-2013

Main Changes

  • system_stm32f4xx.c : Update FMC SDRAM configuration (RBURST mode activation)

  • Update startup files "startup_stm32f427_437xx.s" and "startup_stm32f429_439xx.s"  for TrueSTUDIO and Ride toolchains and maintain the old name of startup files for legacy purpose

V1.2.0 / 11-September-2013

Main Changes

  • Add support of STM32F429/439xx and STM32F401xCxx devices

  • Update definition of STM32F427/437xx devices : extension of the features to include system clock up to 180MHz, dual bank Flash, reduced STOP Mode current, SAI, PCROP, SDRAM and DMA2D
  • stm32f4xx.h
    • Add the following device defines :
      • "#define STM32F40_41xxx" for all STM32405/415/407/417xx devices
      • "#define STM32F427_437xx" for all STM32F427/437xx devices
      • "#define STM32F429_439xx" for all STM32F429/439xx devices
      • "#define STM32F401xx" for all STM32F401xx devices
    • Maintain the old device define for legacy purpose
    • Update IRQ handler enumeration structure to support all STM32F4xx Family devices.  
  • Add new startup files "startup_stm32f40_41xxx.s","startup_stm32f427_437xx.s", "startup_stm32f429_439xx.s" and "startup_stm32f401xx.s" for all toolchains and maintain the old name for startup files for legacy purpose
  • system_stm32f4xx.c
    • Update the system configuration to support all STM32F4xx Family devices.  

V1.1.0 / 11-January-2013

Main Changes

  • Official release for STM32F427x/437x devices.
  • stm32f4xx.h
    • Update product define: replace "#define STM32F4XX" by "#define STM32F40XX" for STM32F40x/41x devices
    •  Add new product define: "#define STM32F427X" for STM32F427x/437x devices.
  • Add new startup files "startup_stm32f427x.s" for all toolchains
  • rename startup files "startup_stm32f4xx.s" by "startup_stm32f40xx.s" for all toolchains
  • system_stm32f4xx.c
    • Prefetch Buffer enabled
    • Add reference to STM32F427x/437x devices and STM324x7I_EVAL board
    • SystemInit_ExtMemCtl() function
      • Add configuration of missing FSMC address and data lines
      • Change memory type to SRAM instead of PSRAM (PSRAM is available only on STM324xG-EVAL RevA) and update timing values

V1.0.2 / 05-March-2012

Main Changes

  • All source files: license disclaimer text update and add link to the License file on ST Internet.

V1.0.1 / 28-December-2011

Main Changes

  • All source files: update disclaimer to add reference to the new license agreement
  • stm32f4xx.h
    • Correct bit definition: RCC_AHB2RSTR_HSAHRST changed to RCC_AHB2RSTR_HASHRST

V1.0.0 / 30-September-2011

Main Changes

  • First official release for STM32F40x/41x devices
  • Add startup file for TASKING toolchain
  • system_stm32f4xx.c: driver's comments update

V1.0.0RC2 / 26-September-2011

Main Changes

  • Official version (V1.0.0) Release Candidate2 for STM32F40x/41x devices
  • stm32f4xx.h
    • Add define for Cortex-M4 revision __CM4_REV
    • Correct RCC_CFGR_PPRE2_DIV16 bit (in RCC_CFGR register) value to 0x0000E000
    • Correct some bits definition to be in line with naming used in the Reference Manual (RM0090)
      • GPIO_OTYPER_IDR_x changed to GPIO_IDR_IDR_x
      • GPIO_OTYPER_ODR_x changed to GPIO_ODR_ODR_x
      • SYSCFG_PMC_MII_RMII changed to SYSCFG_PMC_MII_RMII_SEL
      • RCC_APB2RSTR_SPI1 changed to RCC_APB2RSTR_SPI1RST
      • DBGMCU_APB1_FZ_DBG_IWDEG_STOP changed to DBGMCU_APB1_FZ_DBG_IWDG_STOP
      • PWR_CR_PMODE changed to PWR_CR_VOS
      • PWR_CSR_REGRDY changed to PWR_CSR_VOSRDY
      • Add new define RCC_AHB1ENR_CCMDATARAMEN
      • Add new defines SRAM2_BASE, CCMDATARAM_BASE and BKPSRAM_BASE
    • GPIO_TypeDef structure: in the comment change AFR[2] address mapping to 0x20-0x24 instead of 0x24-0x28
  • system_stm32f4xx.c
    • SystemInit(): add code to enable the FPU
    • SetSysClock(): change PWR_CR_PMODE by PWR_CR_VOS
    • SystemInit_ExtMemCtl(): remove commented values
  • startup (for all compilers)
    • Delete code used to enable the FPU (moved to system_stm32f4xx.c file)
    • File’s header updated

V1.0.0RC1 / 25-August-2011

Main Changes

  • Official version (V1.0.0) Release Candidate1 for STM32F4xx devices

License

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

For complete documentation on STM32 Microcontrollers visit www.st.com/STM32

 

================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/TASKING/cstart_thumb2.asm ================================================ ;; NOTE: To allow the use of this file for both ARMv6M and ARMv7M, ;; we will only use 16-bit Thumb intructions. .extern _lc_ub_stack ; usr/sys mode stack pointer .extern _lc_ue_stack ; symbol required by debugger .extern _lc_ub_table ; ROM to RAM copy table .extern main .extern _Exit .extern exit .weak exit .global __get_argcv .weak __get_argcv .extern __argcvbuf .weak __argcvbuf ;;.extern __init_hardware .extern SystemInit .if @defined('__PROF_ENABLE__') .extern __prof_init .endif .if @defined('__POSIX__') .extern posix_main .extern _posix_boot_stack_top .endif .global _START .section .text.cstart .thumb _START: ;; anticipate possible ROM/RAM remapping ;; by loading the 'real' program address ldr r1,=_Next bx r1 _Next: ;; initialize the stack pointer ldr r1,=_lc_ub_stack ; TODO: make this part of the vector table mov sp,r1 ; Call the clock system intitialization function. bl SystemInit ;; copy initialized sections from ROM to RAM ;; and clear uninitialized data sections in RAM ldr r3,=_lc_ub_table movs r0,#0 cploop: ldr r4,[r3,#0] ; load type ldr r5,[r3,#4] ; dst address ldr r6,[r3,#8] ; src address ldr r7,[r3,#12] ; size cmp r4,#1 beq copy cmp r4,#2 beq clear b done copy: subs r7,r7,#1 ldrb r1,[r6,r7] strb r1,[r5,r7] bne copy adds r3,r3,#16 b cploop clear: subs r7,r7,#1 strb r0,[r5,r7] bne clear adds r3,r3,#16 b cploop done: .if @defined('__POSIX__') ;; posix stack buffer for system upbringing ldr r0,=_posix_boot_stack_top ldr r0, [r0] mov sp,r0 .else ;; load r10 with end of USR/SYS stack, which is ;; needed in case stack overflow checking is on ;; NOTE: use 16-bit instructions only, for ARMv6M ldr r0,=_lc_ue_stack mov r10,r0 .endif .if @defined('__PROF_ENABLE__') bl __prof_init .endif .if @defined('__POSIX__') ;; call posix_main with no arguments bl posix_main .else ;; retrieve argc and argv (default argv[0]==NULL & argc==0) bl __get_argcv ldr r1,=__argcvbuf ;; call main bl main .endif ;; call exit using the return value from main() ;; Note. Calling exit will also run all functions ;; that were supplied through atexit(). bl exit __get_argcv: ; weak definition movs r0,#0 bx lr .ltorg .endsec .calls '_START', ' ' .calls '_START','__init_vector_table' .if @defined('__PROF_ENABLE__') .calls '_START','__prof_init' .endif .if @defined('__POSIX__') .calls '_START','posix_main' .else .calls '_START','__get_argcv' .calls '_START','main' .endif .calls '_START','exit' .calls '_START','',0 .end ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/TrueSTUDIO/startup_stm32f401xx.s ================================================ /** ****************************************************************************** * @file startup_stm32f401xx.s * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief STM32F401xx Devices vector table for Atollic TrueSTUDIO toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Configure the clock system * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ .syntax unified .cpu cortex-m4 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ bl main bx lr .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_IRQHandler /* PVD through EXTI Line detection */ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ .word FLASH_IRQHandler /* FLASH */ .word RCC_IRQHandler /* RCC */ .word EXTI0_IRQHandler /* EXTI Line0 */ .word EXTI1_IRQHandler /* EXTI Line1 */ .word EXTI2_IRQHandler /* EXTI Line2 */ .word EXTI3_IRQHandler /* EXTI Line3 */ .word EXTI4_IRQHandler /* EXTI Line4 */ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word EXTI9_5_IRQHandler /* External Line[9:5]s */ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ .word TIM2_IRQHandler /* TIM2 */ .word TIM3_IRQHandler /* TIM3 */ .word TIM4_IRQHandler /* TIM4 */ .word I2C1_EV_IRQHandler /* I2C1 Event */ .word I2C1_ER_IRQHandler /* I2C1 Error */ .word I2C2_EV_IRQHandler /* I2C2 Event */ .word I2C2_ER_IRQHandler /* I2C2 Error */ .word SPI1_IRQHandler /* SPI1 */ .word SPI2_IRQHandler /* SPI2 */ .word USART1_IRQHandler /* USART1 */ .word USART2_IRQHandler /* USART2 */ .word 0 /* Reserved */ .word EXTI15_10_IRQHandler /* External Line[15:10]s */ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ .word 0 /* Reserved */ .word SDIO_IRQHandler /* SDIO */ .word TIM5_IRQHandler /* TIM5 */ .word SPI3_IRQHandler /* SPI3 */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word OTG_FS_IRQHandler /* USB OTG FS */ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ .word USART6_IRQHandler /* USART6 */ .word I2C3_EV_IRQHandler /* I2C3 event */ .word I2C3_ER_IRQHandler /* I2C3 error */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word FPU_IRQHandler /* FPU */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word SPI4_IRQHandler /* SPI4 */ /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM9_IRQHandler .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler .weak TIM1_UP_TIM10_IRQHandler .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM11_IRQHandler .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak SDIO_IRQHandler .thumb_set SDIO_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/TrueSTUDIO/startup_stm32f40_41xxx.s ================================================ /** ****************************************************************************** * @file startup_stm32f40_41xxx.s * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief STM32F40xxx/41xxx Devices vector table for Atollic TrueSTUDIO toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Configure the clock system and the external SRAM mounted on * STM324xG-EVAL board to be used as data memory (optional, * to be enabled by user) * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ .syntax unified .cpu cortex-m3 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ bl main bx lr .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_IRQHandler /* PVD through EXTI Line detection */ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ .word FLASH_IRQHandler /* FLASH */ .word RCC_IRQHandler /* RCC */ .word EXTI0_IRQHandler /* EXTI Line0 */ .word EXTI1_IRQHandler /* EXTI Line1 */ .word EXTI2_IRQHandler /* EXTI Line2 */ .word EXTI3_IRQHandler /* EXTI Line3 */ .word EXTI4_IRQHandler /* EXTI Line4 */ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ .word CAN1_TX_IRQHandler /* CAN1 TX */ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ .word CAN1_SCE_IRQHandler /* CAN1 SCE */ .word EXTI9_5_IRQHandler /* External Line[9:5]s */ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ .word TIM2_IRQHandler /* TIM2 */ .word TIM3_IRQHandler /* TIM3 */ .word TIM4_IRQHandler /* TIM4 */ .word I2C1_EV_IRQHandler /* I2C1 Event */ .word I2C1_ER_IRQHandler /* I2C1 Error */ .word I2C2_EV_IRQHandler /* I2C2 Event */ .word I2C2_ER_IRQHandler /* I2C2 Error */ .word SPI1_IRQHandler /* SPI1 */ .word SPI2_IRQHandler /* SPI2 */ .word USART1_IRQHandler /* USART1 */ .word USART2_IRQHandler /* USART2 */ .word USART3_IRQHandler /* USART3 */ .word EXTI15_10_IRQHandler /* External Line[15:10]s */ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ .word FSMC_IRQHandler /* FSMC */ .word SDIO_IRQHandler /* SDIO */ .word TIM5_IRQHandler /* TIM5 */ .word SPI3_IRQHandler /* SPI3 */ .word UART4_IRQHandler /* UART4 */ .word UART5_IRQHandler /* UART5 */ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ .word TIM7_IRQHandler /* TIM7 */ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ .word ETH_IRQHandler /* Ethernet */ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ .word CAN2_TX_IRQHandler /* CAN2 TX */ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ .word CAN2_SCE_IRQHandler /* CAN2 SCE */ .word OTG_FS_IRQHandler /* USB OTG FS */ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ .word USART6_IRQHandler /* USART6 */ .word I2C3_EV_IRQHandler /* I2C3 event */ .word I2C3_ER_IRQHandler /* I2C3 error */ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ .word OTG_HS_IRQHandler /* USB OTG HS */ .word DCMI_IRQHandler /* DCMI */ .word CRYP_IRQHandler /* CRYP crypto */ .word HASH_RNG_IRQHandler /* Hash and Rng */ .word FPU_IRQHandler /* FPU */ /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak CAN1_TX_IRQHandler .thumb_set CAN1_TX_IRQHandler,Default_Handler .weak CAN1_RX0_IRQHandler .thumb_set CAN1_RX0_IRQHandler,Default_Handler .weak CAN1_RX1_IRQHandler .thumb_set CAN1_RX1_IRQHandler,Default_Handler .weak CAN1_SCE_IRQHandler .thumb_set CAN1_SCE_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM9_IRQHandler .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler .weak TIM1_UP_TIM10_IRQHandler .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM11_IRQHandler .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak TIM8_BRK_TIM12_IRQHandler .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler .weak TIM8_UP_TIM13_IRQHandler .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler .weak TIM8_TRG_COM_TIM14_IRQHandler .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak FSMC_IRQHandler .thumb_set FSMC_IRQHandler,Default_Handler .weak SDIO_IRQHandler .thumb_set SDIO_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak ETH_IRQHandler .thumb_set ETH_IRQHandler,Default_Handler .weak ETH_WKUP_IRQHandler .thumb_set ETH_WKUP_IRQHandler,Default_Handler .weak CAN2_TX_IRQHandler .thumb_set CAN2_TX_IRQHandler,Default_Handler .weak CAN2_RX0_IRQHandler .thumb_set CAN2_RX0_IRQHandler,Default_Handler .weak CAN2_RX1_IRQHandler .thumb_set CAN2_RX1_IRQHandler,Default_Handler .weak CAN2_SCE_IRQHandler .thumb_set CAN2_SCE_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak OTG_HS_EP1_OUT_IRQHandler .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_HS_EP1_IN_IRQHandler .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler .weak OTG_HS_WKUP_IRQHandler .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler .weak OTG_HS_IRQHandler .thumb_set OTG_HS_IRQHandler,Default_Handler .weak DCMI_IRQHandler .thumb_set DCMI_IRQHandler,Default_Handler .weak CRYP_IRQHandler .thumb_set CRYP_IRQHandler,Default_Handler .weak HASH_RNG_IRQHandler .thumb_set HASH_RNG_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/TrueSTUDIO/startup_stm32f40xx.s ================================================ /** ****************************************************************************** * @file startup_stm32f40_41xxx.s * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief STM32F40xxx/41xxx Devices vector table for Atollic TrueSTUDIO toolchain. * Same as startup_stm32f40_41xxx.s and maintained for legacy purpose * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Configure the clock system and the external SRAM mounted on * STM324xG-EVAL board to be used as data memory (optional, * to be enabled by user) * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ .syntax unified .cpu cortex-m3 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ bl main bx lr .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_IRQHandler /* PVD through EXTI Line detection */ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ .word FLASH_IRQHandler /* FLASH */ .word RCC_IRQHandler /* RCC */ .word EXTI0_IRQHandler /* EXTI Line0 */ .word EXTI1_IRQHandler /* EXTI Line1 */ .word EXTI2_IRQHandler /* EXTI Line2 */ .word EXTI3_IRQHandler /* EXTI Line3 */ .word EXTI4_IRQHandler /* EXTI Line4 */ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ .word CAN1_TX_IRQHandler /* CAN1 TX */ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ .word CAN1_SCE_IRQHandler /* CAN1 SCE */ .word EXTI9_5_IRQHandler /* External Line[9:5]s */ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ .word TIM2_IRQHandler /* TIM2 */ .word TIM3_IRQHandler /* TIM3 */ .word TIM4_IRQHandler /* TIM4 */ .word I2C1_EV_IRQHandler /* I2C1 Event */ .word I2C1_ER_IRQHandler /* I2C1 Error */ .word I2C2_EV_IRQHandler /* I2C2 Event */ .word I2C2_ER_IRQHandler /* I2C2 Error */ .word SPI1_IRQHandler /* SPI1 */ .word SPI2_IRQHandler /* SPI2 */ .word USART1_IRQHandler /* USART1 */ .word USART2_IRQHandler /* USART2 */ .word USART3_IRQHandler /* USART3 */ .word EXTI15_10_IRQHandler /* External Line[15:10]s */ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ .word FSMC_IRQHandler /* FSMC */ .word SDIO_IRQHandler /* SDIO */ .word TIM5_IRQHandler /* TIM5 */ .word SPI3_IRQHandler /* SPI3 */ .word UART4_IRQHandler /* UART4 */ .word UART5_IRQHandler /* UART5 */ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ .word TIM7_IRQHandler /* TIM7 */ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ .word ETH_IRQHandler /* Ethernet */ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ .word CAN2_TX_IRQHandler /* CAN2 TX */ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ .word CAN2_SCE_IRQHandler /* CAN2 SCE */ .word OTG_FS_IRQHandler /* USB OTG FS */ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ .word USART6_IRQHandler /* USART6 */ .word I2C3_EV_IRQHandler /* I2C3 event */ .word I2C3_ER_IRQHandler /* I2C3 error */ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ .word OTG_HS_IRQHandler /* USB OTG HS */ .word DCMI_IRQHandler /* DCMI */ .word CRYP_IRQHandler /* CRYP crypto */ .word HASH_RNG_IRQHandler /* Hash and Rng */ .word FPU_IRQHandler /* FPU */ /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak CAN1_TX_IRQHandler .thumb_set CAN1_TX_IRQHandler,Default_Handler .weak CAN1_RX0_IRQHandler .thumb_set CAN1_RX0_IRQHandler,Default_Handler .weak CAN1_RX1_IRQHandler .thumb_set CAN1_RX1_IRQHandler,Default_Handler .weak CAN1_SCE_IRQHandler .thumb_set CAN1_SCE_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM9_IRQHandler .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler .weak TIM1_UP_TIM10_IRQHandler .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM11_IRQHandler .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak TIM8_BRK_TIM12_IRQHandler .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler .weak TIM8_UP_TIM13_IRQHandler .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler .weak TIM8_TRG_COM_TIM14_IRQHandler .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak FSMC_IRQHandler .thumb_set FSMC_IRQHandler,Default_Handler .weak SDIO_IRQHandler .thumb_set SDIO_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak ETH_IRQHandler .thumb_set ETH_IRQHandler,Default_Handler .weak ETH_WKUP_IRQHandler .thumb_set ETH_WKUP_IRQHandler,Default_Handler .weak CAN2_TX_IRQHandler .thumb_set CAN2_TX_IRQHandler,Default_Handler .weak CAN2_RX0_IRQHandler .thumb_set CAN2_RX0_IRQHandler,Default_Handler .weak CAN2_RX1_IRQHandler .thumb_set CAN2_RX1_IRQHandler,Default_Handler .weak CAN2_SCE_IRQHandler .thumb_set CAN2_SCE_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak OTG_HS_EP1_OUT_IRQHandler .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_HS_EP1_IN_IRQHandler .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler .weak OTG_HS_WKUP_IRQHandler .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler .weak OTG_HS_IRQHandler .thumb_set OTG_HS_IRQHandler,Default_Handler .weak DCMI_IRQHandler .thumb_set DCMI_IRQHandler,Default_Handler .weak CRYP_IRQHandler .thumb_set CRYP_IRQHandler,Default_Handler .weak HASH_RNG_IRQHandler .thumb_set HASH_RNG_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/TrueSTUDIO/startup_stm32f427_437xx.s ================================================ /** ****************************************************************************** * @file startup_stm32f427_437xx.s * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief STM32F427xx/437xx Devices vector table for Atollic TrueSTUDIO toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Configure the clock system and the external SRAM mounted on * STM324x7I-EVAL board to be used as data memory * (optional, to be enabled by user) * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ .syntax unified .cpu cortex-m3 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ bl main bx lr .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_IRQHandler /* PVD through EXTI Line detection */ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ .word FLASH_IRQHandler /* FLASH */ .word RCC_IRQHandler /* RCC */ .word EXTI0_IRQHandler /* EXTI Line0 */ .word EXTI1_IRQHandler /* EXTI Line1 */ .word EXTI2_IRQHandler /* EXTI Line2 */ .word EXTI3_IRQHandler /* EXTI Line3 */ .word EXTI4_IRQHandler /* EXTI Line4 */ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ .word CAN1_TX_IRQHandler /* CAN1 TX */ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ .word CAN1_SCE_IRQHandler /* CAN1 SCE */ .word EXTI9_5_IRQHandler /* External Line[9:5]s */ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ .word TIM2_IRQHandler /* TIM2 */ .word TIM3_IRQHandler /* TIM3 */ .word TIM4_IRQHandler /* TIM4 */ .word I2C1_EV_IRQHandler /* I2C1 Event */ .word I2C1_ER_IRQHandler /* I2C1 Error */ .word I2C2_EV_IRQHandler /* I2C2 Event */ .word I2C2_ER_IRQHandler /* I2C2 Error */ .word SPI1_IRQHandler /* SPI1 */ .word SPI2_IRQHandler /* SPI2 */ .word USART1_IRQHandler /* USART1 */ .word USART2_IRQHandler /* USART2 */ .word USART3_IRQHandler /* USART3 */ .word EXTI15_10_IRQHandler /* External Line[15:10]s */ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ .word FSMC_IRQHandler /* FSMC */ .word SDIO_IRQHandler /* SDIO */ .word TIM5_IRQHandler /* TIM5 */ .word SPI3_IRQHandler /* SPI3 */ .word UART4_IRQHandler /* UART4 */ .word UART5_IRQHandler /* UART5 */ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ .word TIM7_IRQHandler /* TIM7 */ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ .word ETH_IRQHandler /* Ethernet */ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ .word CAN2_TX_IRQHandler /* CAN2 TX */ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ .word CAN2_SCE_IRQHandler /* CAN2 SCE */ .word OTG_FS_IRQHandler /* USB OTG FS */ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ .word USART6_IRQHandler /* USART6 */ .word I2C3_EV_IRQHandler /* I2C3 event */ .word I2C3_ER_IRQHandler /* I2C3 error */ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ .word OTG_HS_IRQHandler /* USB OTG HS */ .word DCMI_IRQHandler /* DCMI */ .word CRYP_IRQHandler /* CRYP crypto */ .word HASH_RNG_IRQHandler /* Hash and Rng */ .word FPU_IRQHandler /* FPU */ .word UART7_IRQHandler /* UART7 */ .word UART8_IRQHandler /* UART8 */ .word SPI4_IRQHandler /* SPI4 */ .word SPI5_IRQHandler /* SPI5 */ .word SPI6_IRQHandler /* SPI6 */ .word SAI1_IRQHandler /* SAI1 */ .word LTDC_IRQHandler /* LTDC */ .word LTDC_ER_IRQHandler /* LTDC error */ .word DMA2D_IRQHandler /* DMA2D */ /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak CAN1_TX_IRQHandler .thumb_set CAN1_TX_IRQHandler,Default_Handler .weak CAN1_RX0_IRQHandler .thumb_set CAN1_RX0_IRQHandler,Default_Handler .weak CAN1_RX1_IRQHandler .thumb_set CAN1_RX1_IRQHandler,Default_Handler .weak CAN1_SCE_IRQHandler .thumb_set CAN1_SCE_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM9_IRQHandler .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler .weak TIM1_UP_TIM10_IRQHandler .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM11_IRQHandler .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak TIM8_BRK_TIM12_IRQHandler .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler .weak TIM8_UP_TIM13_IRQHandler .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler .weak TIM8_TRG_COM_TIM14_IRQHandler .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak FSMC_IRQHandler .thumb_set FSMC_IRQHandler,Default_Handler .weak SDIO_IRQHandler .thumb_set SDIO_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak ETH_IRQHandler .thumb_set ETH_IRQHandler,Default_Handler .weak ETH_WKUP_IRQHandler .thumb_set ETH_WKUP_IRQHandler,Default_Handler .weak CAN2_TX_IRQHandler .thumb_set CAN2_TX_IRQHandler,Default_Handler .weak CAN2_RX0_IRQHandler .thumb_set CAN2_RX0_IRQHandler,Default_Handler .weak CAN2_RX1_IRQHandler .thumb_set CAN2_RX1_IRQHandler,Default_Handler .weak CAN2_SCE_IRQHandler .thumb_set CAN2_SCE_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak OTG_HS_EP1_OUT_IRQHandler .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_HS_EP1_IN_IRQHandler .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler .weak OTG_HS_WKUP_IRQHandler .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler .weak OTG_HS_IRQHandler .thumb_set OTG_HS_IRQHandler,Default_Handler .weak DCMI_IRQHandler .thumb_set DCMI_IRQHandler,Default_Handler .weak CRYP_IRQHandler .thumb_set CRYP_IRQHandler,Default_Handler .weak HASH_RNG_IRQHandler .thumb_set HASH_RNG_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler .weak UART7_IRQHandler .thumb_set UART7_IRQHandler,Default_Handler .weak UART8_IRQHandler .thumb_set UART8_IRQHandler,Default_Handler .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler .weak SPI5_IRQHandler .thumb_set SPI5_IRQHandler,Default_Handler .weak SPI6_IRQHandler .thumb_set SPI6_IRQHandler,Default_Handler .weak SAI1_IRQHandler .thumb_set SAI1_IRQHandler,Default_Handler .weak LTDC_IRQHandler .thumb_set LTDC_IRQHandler,Default_Handler .weak LTDC_ER_IRQHandler .thumb_set LTDC_ER_IRQHandler,Default_Handler .weak DMA2D_IRQHandler .thumb_set DMA2D_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/TrueSTUDIO/startup_stm32f427xx.s ================================================ /** ****************************************************************************** * @file startup_stm32f427x.s * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief STM32F42xxx/43xxx Devices vector table for Atollic TrueSTUDIO toolchain. * Same as startup_stm32f42_43xxx.s and maintained for legacy purpose * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Configure the clock system and the external SRAM mounted on * STM324x9I-EVAL/STM324x7I-EVAL boards to be used as data memory * (optional, to be enabled by user) * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ .syntax unified .cpu cortex-m3 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ bl main bx lr .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_IRQHandler /* PVD through EXTI Line detection */ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ .word FLASH_IRQHandler /* FLASH */ .word RCC_IRQHandler /* RCC */ .word EXTI0_IRQHandler /* EXTI Line0 */ .word EXTI1_IRQHandler /* EXTI Line1 */ .word EXTI2_IRQHandler /* EXTI Line2 */ .word EXTI3_IRQHandler /* EXTI Line3 */ .word EXTI4_IRQHandler /* EXTI Line4 */ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ .word CAN1_TX_IRQHandler /* CAN1 TX */ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ .word CAN1_SCE_IRQHandler /* CAN1 SCE */ .word EXTI9_5_IRQHandler /* External Line[9:5]s */ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ .word TIM2_IRQHandler /* TIM2 */ .word TIM3_IRQHandler /* TIM3 */ .word TIM4_IRQHandler /* TIM4 */ .word I2C1_EV_IRQHandler /* I2C1 Event */ .word I2C1_ER_IRQHandler /* I2C1 Error */ .word I2C2_EV_IRQHandler /* I2C2 Event */ .word I2C2_ER_IRQHandler /* I2C2 Error */ .word SPI1_IRQHandler /* SPI1 */ .word SPI2_IRQHandler /* SPI2 */ .word USART1_IRQHandler /* USART1 */ .word USART2_IRQHandler /* USART2 */ .word USART3_IRQHandler /* USART3 */ .word EXTI15_10_IRQHandler /* External Line[15:10]s */ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ .word FSMC_IRQHandler /* FSMC */ .word SDIO_IRQHandler /* SDIO */ .word TIM5_IRQHandler /* TIM5 */ .word SPI3_IRQHandler /* SPI3 */ .word UART4_IRQHandler /* UART4 */ .word UART5_IRQHandler /* UART5 */ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ .word TIM7_IRQHandler /* TIM7 */ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ .word ETH_IRQHandler /* Ethernet */ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ .word CAN2_TX_IRQHandler /* CAN2 TX */ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ .word CAN2_SCE_IRQHandler /* CAN2 SCE */ .word OTG_FS_IRQHandler /* USB OTG FS */ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ .word USART6_IRQHandler /* USART6 */ .word I2C3_EV_IRQHandler /* I2C3 event */ .word I2C3_ER_IRQHandler /* I2C3 error */ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ .word OTG_HS_IRQHandler /* USB OTG HS */ .word DCMI_IRQHandler /* DCMI */ .word CRYP_IRQHandler /* CRYP crypto */ .word HASH_RNG_IRQHandler /* Hash and Rng */ .word FPU_IRQHandler /* FPU */ .word UART7_IRQHandler /* UART7 */ .word UART8_IRQHandler /* UART8 */ .word SPI4_IRQHandler /* SPI4 */ .word SPI5_IRQHandler /* SPI5 */ .word SPI6_IRQHandler /* SPI6 */ .word SAI1_IRQHandler /* SAI1 */ .word LTDC_IRQHandler /* LTDC */ .word LTDC_ER_IRQHandler /* LTDC error */ .word DMA2D_IRQHandler /* DMA2D */ /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak CAN1_TX_IRQHandler .thumb_set CAN1_TX_IRQHandler,Default_Handler .weak CAN1_RX0_IRQHandler .thumb_set CAN1_RX0_IRQHandler,Default_Handler .weak CAN1_RX1_IRQHandler .thumb_set CAN1_RX1_IRQHandler,Default_Handler .weak CAN1_SCE_IRQHandler .thumb_set CAN1_SCE_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM9_IRQHandler .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler .weak TIM1_UP_TIM10_IRQHandler .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM11_IRQHandler .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak TIM8_BRK_TIM12_IRQHandler .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler .weak TIM8_UP_TIM13_IRQHandler .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler .weak TIM8_TRG_COM_TIM14_IRQHandler .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak FSMC_IRQHandler .thumb_set FSMC_IRQHandler,Default_Handler .weak SDIO_IRQHandler .thumb_set SDIO_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak ETH_IRQHandler .thumb_set ETH_IRQHandler,Default_Handler .weak ETH_WKUP_IRQHandler .thumb_set ETH_WKUP_IRQHandler,Default_Handler .weak CAN2_TX_IRQHandler .thumb_set CAN2_TX_IRQHandler,Default_Handler .weak CAN2_RX0_IRQHandler .thumb_set CAN2_RX0_IRQHandler,Default_Handler .weak CAN2_RX1_IRQHandler .thumb_set CAN2_RX1_IRQHandler,Default_Handler .weak CAN2_SCE_IRQHandler .thumb_set CAN2_SCE_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak OTG_HS_EP1_OUT_IRQHandler .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_HS_EP1_IN_IRQHandler .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler .weak OTG_HS_WKUP_IRQHandler .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler .weak OTG_HS_IRQHandler .thumb_set OTG_HS_IRQHandler,Default_Handler .weak DCMI_IRQHandler .thumb_set DCMI_IRQHandler,Default_Handler .weak CRYP_IRQHandler .thumb_set CRYP_IRQHandler,Default_Handler .weak HASH_RNG_IRQHandler .thumb_set HASH_RNG_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler .weak UART7_IRQHandler .thumb_set UART7_IRQHandler,Default_Handler .weak UART8_IRQHandler .thumb_set UART8_IRQHandler,Default_Handler .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler .weak SPI5_IRQHandler .thumb_set SPI5_IRQHandler,Default_Handler .weak SPI6_IRQHandler .thumb_set SPI6_IRQHandler,Default_Handler .weak SAI1_IRQHandler .thumb_set SAI1_IRQHandler,Default_Handler .weak LTDC_IRQHandler .thumb_set LTDC_IRQHandler,Default_Handler .weak LTDC_ER_IRQHandler .thumb_set LTDC_ER_IRQHandler,Default_Handler .weak DMA2D_IRQHandler .thumb_set DMA2D_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/TrueSTUDIO/startup_stm32f429_439xx.s ================================================ /** ****************************************************************************** * @file startup_stm32f429_439xx.s * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief STM32F429xx/439xx Devices vector table for Atollic TrueSTUDIO toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Configure the clock system and the external SRAM mounted on * STM324x9I-EVAL board to be used as data memory * (optional, to be enabled by user) * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ .syntax unified .cpu cortex-m3 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ bl main bx lr .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_IRQHandler /* PVD through EXTI Line detection */ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ .word FLASH_IRQHandler /* FLASH */ .word RCC_IRQHandler /* RCC */ .word EXTI0_IRQHandler /* EXTI Line0 */ .word EXTI1_IRQHandler /* EXTI Line1 */ .word EXTI2_IRQHandler /* EXTI Line2 */ .word EXTI3_IRQHandler /* EXTI Line3 */ .word EXTI4_IRQHandler /* EXTI Line4 */ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ .word CAN1_TX_IRQHandler /* CAN1 TX */ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ .word CAN1_SCE_IRQHandler /* CAN1 SCE */ .word EXTI9_5_IRQHandler /* External Line[9:5]s */ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ .word TIM2_IRQHandler /* TIM2 */ .word TIM3_IRQHandler /* TIM3 */ .word TIM4_IRQHandler /* TIM4 */ .word I2C1_EV_IRQHandler /* I2C1 Event */ .word I2C1_ER_IRQHandler /* I2C1 Error */ .word I2C2_EV_IRQHandler /* I2C2 Event */ .word I2C2_ER_IRQHandler /* I2C2 Error */ .word SPI1_IRQHandler /* SPI1 */ .word SPI2_IRQHandler /* SPI2 */ .word USART1_IRQHandler /* USART1 */ .word USART2_IRQHandler /* USART2 */ .word USART3_IRQHandler /* USART3 */ .word EXTI15_10_IRQHandler /* External Line[15:10]s */ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ .word FSMC_IRQHandler /* FSMC */ .word SDIO_IRQHandler /* SDIO */ .word TIM5_IRQHandler /* TIM5 */ .word SPI3_IRQHandler /* SPI3 */ .word UART4_IRQHandler /* UART4 */ .word UART5_IRQHandler /* UART5 */ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ .word TIM7_IRQHandler /* TIM7 */ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ .word ETH_IRQHandler /* Ethernet */ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ .word CAN2_TX_IRQHandler /* CAN2 TX */ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ .word CAN2_SCE_IRQHandler /* CAN2 SCE */ .word OTG_FS_IRQHandler /* USB OTG FS */ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ .word USART6_IRQHandler /* USART6 */ .word I2C3_EV_IRQHandler /* I2C3 event */ .word I2C3_ER_IRQHandler /* I2C3 error */ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ .word OTG_HS_IRQHandler /* USB OTG HS */ .word DCMI_IRQHandler /* DCMI */ .word CRYP_IRQHandler /* CRYP crypto */ .word HASH_RNG_IRQHandler /* Hash and Rng */ .word FPU_IRQHandler /* FPU */ .word UART7_IRQHandler /* UART7 */ .word UART8_IRQHandler /* UART8 */ .word SPI4_IRQHandler /* SPI4 */ .word SPI5_IRQHandler /* SPI5 */ .word SPI6_IRQHandler /* SPI6 */ .word SAI1_IRQHandler /* SAI1 */ .word LTDC_IRQHandler /* LTDC */ .word LTDC_ER_IRQHandler /* LTDC error */ .word DMA2D_IRQHandler /* DMA2D */ /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak CAN1_TX_IRQHandler .thumb_set CAN1_TX_IRQHandler,Default_Handler .weak CAN1_RX0_IRQHandler .thumb_set CAN1_RX0_IRQHandler,Default_Handler .weak CAN1_RX1_IRQHandler .thumb_set CAN1_RX1_IRQHandler,Default_Handler .weak CAN1_SCE_IRQHandler .thumb_set CAN1_SCE_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM9_IRQHandler .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler .weak TIM1_UP_TIM10_IRQHandler .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM11_IRQHandler .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak TIM8_BRK_TIM12_IRQHandler .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler .weak TIM8_UP_TIM13_IRQHandler .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler .weak TIM8_TRG_COM_TIM14_IRQHandler .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak FSMC_IRQHandler .thumb_set FSMC_IRQHandler,Default_Handler .weak SDIO_IRQHandler .thumb_set SDIO_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak ETH_IRQHandler .thumb_set ETH_IRQHandler,Default_Handler .weak ETH_WKUP_IRQHandler .thumb_set ETH_WKUP_IRQHandler,Default_Handler .weak CAN2_TX_IRQHandler .thumb_set CAN2_TX_IRQHandler,Default_Handler .weak CAN2_RX0_IRQHandler .thumb_set CAN2_RX0_IRQHandler,Default_Handler .weak CAN2_RX1_IRQHandler .thumb_set CAN2_RX1_IRQHandler,Default_Handler .weak CAN2_SCE_IRQHandler .thumb_set CAN2_SCE_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak OTG_HS_EP1_OUT_IRQHandler .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_HS_EP1_IN_IRQHandler .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler .weak OTG_HS_WKUP_IRQHandler .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler .weak OTG_HS_IRQHandler .thumb_set OTG_HS_IRQHandler,Default_Handler .weak DCMI_IRQHandler .thumb_set DCMI_IRQHandler,Default_Handler .weak CRYP_IRQHandler .thumb_set CRYP_IRQHandler,Default_Handler .weak HASH_RNG_IRQHandler .thumb_set HASH_RNG_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler .weak UART7_IRQHandler .thumb_set UART7_IRQHandler,Default_Handler .weak UART8_IRQHandler .thumb_set UART8_IRQHandler,Default_Handler .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler .weak SPI5_IRQHandler .thumb_set SPI5_IRQHandler,Default_Handler .weak SPI6_IRQHandler .thumb_set SPI6_IRQHandler,Default_Handler .weak SAI1_IRQHandler .thumb_set SAI1_IRQHandler,Default_Handler .weak LTDC_IRQHandler .thumb_set LTDC_IRQHandler,Default_Handler .weak LTDC_ER_IRQHandler .thumb_set LTDC_ER_IRQHandler,Default_Handler .weak DMA2D_IRQHandler .thumb_set DMA2D_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f401xx.s ================================================ ;******************** (C) COPYRIGHT 2013 STMicroelectronics ******************** ;* File Name : startup_stm32f401xx.s ;* Author : MCD Application Team ;* Version : V1.3.0 ;* Date : 08-November-2013 ;* Description : STM32F401xx devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address ;* - Configure the system clock ;* - Branches to __main in the C library (which eventually ;* calls main()). ;* After Reset the CortexM4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ; ; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); ; You may not use this file except in compliance with the License. ; You may obtain a copy of the License at: ; ; http://www.st.com/software_license_agreement_liberty_v2 ; ; Unless required by applicable law or agreed to in writing, software ; distributed under the License is distributed on an "AS IS" BASIS, ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; See the License for the specific language governing permissions and ; limitations under the License. ; ;******************************************************************************* ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; Stack Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; Heap Configuration ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap_Size EQU 0x00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog DCD PVD_IRQHandler ; PVD through EXTI Line detection DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line DCD FLASH_IRQHandler ; FLASH DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line0 DCD EXTI1_IRQHandler ; EXTI Line1 DCD EXTI2_IRQHandler ; EXTI Line2 DCD EXTI3_IRQHandler ; EXTI Line3 DCD EXTI4_IRQHandler ; EXTI Line4 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 DCD ADC_IRQHandler ; ADC1 DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD 0 ; Reserved DCD EXTI15_10_IRQHandler ; External Line[15:10]s DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 DCD 0 ; Reserved DCD SDIO_IRQHandler ; SDIO DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD OTG_FS_IRQHandler ; USB OTG FS DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 DCD USART6_IRQHandler ; USART6 DCD I2C3_EV_IRQHandler ; I2C3 event DCD I2C3_ER_IRQHandler ; I2C3 error DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD FPU_IRQHandler ; FPU DCD 0 ; Reserved DCD 0 ; Reserved DCD SPI4_IRQHandler ; SPI4 __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WWDG_IRQHandler [WEAK] EXPORT PVD_IRQHandler [WEAK] EXPORT TAMP_STAMP_IRQHandler [WEAK] EXPORT RTC_WKUP_IRQHandler [WEAK] EXPORT FLASH_IRQHandler [WEAK] EXPORT RCC_IRQHandler [WEAK] EXPORT EXTI0_IRQHandler [WEAK] EXPORT EXTI1_IRQHandler [WEAK] EXPORT EXTI2_IRQHandler [WEAK] EXPORT EXTI3_IRQHandler [WEAK] EXPORT EXTI4_IRQHandler [WEAK] EXPORT DMA1_Stream0_IRQHandler [WEAK] EXPORT DMA1_Stream1_IRQHandler [WEAK] EXPORT DMA1_Stream2_IRQHandler [WEAK] EXPORT DMA1_Stream3_IRQHandler [WEAK] EXPORT DMA1_Stream4_IRQHandler [WEAK] EXPORT DMA1_Stream5_IRQHandler [WEAK] EXPORT DMA1_Stream6_IRQHandler [WEAK] EXPORT ADC_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] EXPORT TIM4_IRQHandler [WEAK] EXPORT I2C1_EV_IRQHandler [WEAK] EXPORT I2C1_ER_IRQHandler [WEAK] EXPORT I2C2_EV_IRQHandler [WEAK] EXPORT I2C2_ER_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK] EXPORT SPI2_IRQHandler [WEAK] EXPORT USART1_IRQHandler [WEAK] EXPORT USART2_IRQHandler [WEAK] EXPORT EXTI15_10_IRQHandler [WEAK] EXPORT RTC_Alarm_IRQHandler [WEAK] EXPORT OTG_FS_WKUP_IRQHandler [WEAK] EXPORT DMA1_Stream7_IRQHandler [WEAK] EXPORT SDIO_IRQHandler [WEAK] EXPORT TIM5_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] EXPORT DMA2_Stream0_IRQHandler [WEAK] EXPORT DMA2_Stream1_IRQHandler [WEAK] EXPORT DMA2_Stream2_IRQHandler [WEAK] EXPORT DMA2_Stream3_IRQHandler [WEAK] EXPORT DMA2_Stream4_IRQHandler [WEAK] EXPORT OTG_FS_IRQHandler [WEAK] EXPORT DMA2_Stream5_IRQHandler [WEAK] EXPORT DMA2_Stream6_IRQHandler [WEAK] EXPORT DMA2_Stream7_IRQHandler [WEAK] EXPORT USART6_IRQHandler [WEAK] EXPORT I2C3_EV_IRQHandler [WEAK] EXPORT I2C3_ER_IRQHandler [WEAK] EXPORT FPU_IRQHandler [WEAK] EXPORT SPI4_IRQHandler [WEAK] WWDG_IRQHandler PVD_IRQHandler TAMP_STAMP_IRQHandler RTC_WKUP_IRQHandler FLASH_IRQHandler RCC_IRQHandler EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler DMA1_Stream0_IRQHandler DMA1_Stream1_IRQHandler DMA1_Stream2_IRQHandler DMA1_Stream3_IRQHandler DMA1_Stream4_IRQHandler DMA1_Stream5_IRQHandler DMA1_Stream6_IRQHandler ADC_IRQHandler EXTI9_5_IRQHandler TIM1_BRK_TIM9_IRQHandler TIM1_UP_TIM10_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler TIM1_CC_IRQHandler TIM2_IRQHandler TIM3_IRQHandler TIM4_IRQHandler I2C1_EV_IRQHandler I2C1_ER_IRQHandler I2C2_EV_IRQHandler I2C2_ER_IRQHandler SPI1_IRQHandler SPI2_IRQHandler USART1_IRQHandler USART2_IRQHandler EXTI15_10_IRQHandler RTC_Alarm_IRQHandler OTG_FS_WKUP_IRQHandler DMA1_Stream7_IRQHandler SDIO_IRQHandler TIM5_IRQHandler SPI3_IRQHandler DMA2_Stream0_IRQHandler DMA2_Stream1_IRQHandler DMA2_Stream2_IRQHandler DMA2_Stream3_IRQHandler DMA2_Stream4_IRQHandler ETH_IRQHandler OTG_FS_IRQHandler DMA2_Stream5_IRQHandler DMA2_Stream6_IRQHandler DMA2_Stream7_IRQHandler USART6_IRQHandler I2C3_EV_IRQHandler I2C3_ER_IRQHandler FPU_IRQHandler SPI4_IRQHandler B . ENDP ALIGN ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ALIGN ENDIF END ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f40_41xxx.s ================================================ ;******************** (C) COPYRIGHT 2013 STMicroelectronics ******************** ;* File Name : startup_stm32f40_41xxx.s ;* Author : MCD Application Team ;* Version : V1.3.0 ;* Date : 08-November-2013 ;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address ;* - Configure the system clock and the external SRAM mounted on ;* STM324xG-EVAL board to be used as data memory (optional, ;* to be enabled by user) ;* - Branches to __main in the C library (which eventually ;* calls main()). ;* After Reset the CortexM4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ; ; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); ; You may not use this file except in compliance with the License. ; You may obtain a copy of the License at: ; ; http://www.st.com/software_license_agreement_liberty_v2 ; ; Unless required by applicable law or agreed to in writing, software ; distributed under the License is distributed on an "AS IS" BASIS, ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; See the License for the specific language governing permissions and ; limitations under the License. ; ;******************************************************************************* ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; Stack Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; ;modified by hetao.su ;Stack_Size EQU 0x00000400 Stack_Size EQU 0x00004000 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; Heap Configuration ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap_Size EQU 0x00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog DCD PVD_IRQHandler ; PVD through EXTI Line detection DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line DCD FLASH_IRQHandler ; FLASH DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line0 DCD EXTI1_IRQHandler ; EXTI Line1 DCD EXTI2_IRQHandler ; EXTI Line2 DCD EXTI3_IRQHandler ; EXTI Line3 DCD EXTI4_IRQHandler ; EXTI Line4 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s DCD CAN1_TX_IRQHandler ; CAN1 TX DCD CAN1_RX0_IRQHandler ; CAN1 RX0 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 DCD CAN1_SCE_IRQHandler ; CAN1 SCE DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; External Line[15:10]s DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 DCD FSMC_IRQHandler ; FSMC DCD SDIO_IRQHandler ; SDIO DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 DCD UART4_IRQHandler ; UART4 DCD UART5_IRQHandler ; UART5 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 DCD ETH_IRQHandler ; Ethernet DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line DCD CAN2_TX_IRQHandler ; CAN2 TX DCD CAN2_RX0_IRQHandler ; CAN2 RX0 DCD CAN2_RX1_IRQHandler ; CAN2 RX1 DCD CAN2_SCE_IRQHandler ; CAN2 SCE DCD OTG_FS_IRQHandler ; USB OTG FS DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 DCD USART6_IRQHandler ; USART6 DCD I2C3_EV_IRQHandler ; I2C3 event DCD I2C3_ER_IRQHandler ; I2C3 error DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_IRQHandler ; DCMI DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WWDG_IRQHandler [WEAK] EXPORT PVD_IRQHandler [WEAK] EXPORT TAMP_STAMP_IRQHandler [WEAK] EXPORT RTC_WKUP_IRQHandler [WEAK] EXPORT FLASH_IRQHandler [WEAK] EXPORT RCC_IRQHandler [WEAK] EXPORT EXTI0_IRQHandler [WEAK] EXPORT EXTI1_IRQHandler [WEAK] EXPORT EXTI2_IRQHandler [WEAK] EXPORT EXTI3_IRQHandler [WEAK] EXPORT EXTI4_IRQHandler [WEAK] EXPORT DMA1_Stream0_IRQHandler [WEAK] EXPORT DMA1_Stream1_IRQHandler [WEAK] EXPORT DMA1_Stream2_IRQHandler [WEAK] EXPORT DMA1_Stream3_IRQHandler [WEAK] EXPORT DMA1_Stream4_IRQHandler [WEAK] EXPORT DMA1_Stream5_IRQHandler [WEAK] EXPORT DMA1_Stream6_IRQHandler [WEAK] EXPORT ADC_IRQHandler [WEAK] EXPORT CAN1_TX_IRQHandler [WEAK] EXPORT CAN1_RX0_IRQHandler [WEAK] EXPORT CAN1_RX1_IRQHandler [WEAK] EXPORT CAN1_SCE_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] EXPORT TIM4_IRQHandler [WEAK] EXPORT I2C1_EV_IRQHandler [WEAK] EXPORT I2C1_ER_IRQHandler [WEAK] EXPORT I2C2_EV_IRQHandler [WEAK] EXPORT I2C2_ER_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK] EXPORT SPI2_IRQHandler [WEAK] EXPORT USART1_IRQHandler [WEAK] EXPORT USART2_IRQHandler [WEAK] EXPORT USART3_IRQHandler [WEAK] EXPORT EXTI15_10_IRQHandler [WEAK] EXPORT RTC_Alarm_IRQHandler [WEAK] EXPORT OTG_FS_WKUP_IRQHandler [WEAK] EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] EXPORT TIM8_CC_IRQHandler [WEAK] EXPORT DMA1_Stream7_IRQHandler [WEAK] EXPORT FSMC_IRQHandler [WEAK] EXPORT SDIO_IRQHandler [WEAK] EXPORT TIM5_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT UART5_IRQHandler [WEAK] EXPORT TIM6_DAC_IRQHandler [WEAK] EXPORT TIM7_IRQHandler [WEAK] EXPORT DMA2_Stream0_IRQHandler [WEAK] EXPORT DMA2_Stream1_IRQHandler [WEAK] EXPORT DMA2_Stream2_IRQHandler [WEAK] EXPORT DMA2_Stream3_IRQHandler [WEAK] EXPORT DMA2_Stream4_IRQHandler [WEAK] EXPORT ETH_IRQHandler [WEAK] EXPORT ETH_WKUP_IRQHandler [WEAK] EXPORT CAN2_TX_IRQHandler [WEAK] EXPORT CAN2_RX0_IRQHandler [WEAK] EXPORT CAN2_RX1_IRQHandler [WEAK] EXPORT CAN2_SCE_IRQHandler [WEAK] EXPORT OTG_FS_IRQHandler [WEAK] EXPORT DMA2_Stream5_IRQHandler [WEAK] EXPORT DMA2_Stream6_IRQHandler [WEAK] EXPORT DMA2_Stream7_IRQHandler [WEAK] EXPORT USART6_IRQHandler [WEAK] EXPORT I2C3_EV_IRQHandler [WEAK] EXPORT I2C3_ER_IRQHandler [WEAK] EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] EXPORT OTG_HS_WKUP_IRQHandler [WEAK] EXPORT OTG_HS_IRQHandler [WEAK] EXPORT DCMI_IRQHandler [WEAK] EXPORT CRYP_IRQHandler [WEAK] EXPORT HASH_RNG_IRQHandler [WEAK] EXPORT FPU_IRQHandler [WEAK] WWDG_IRQHandler PVD_IRQHandler TAMP_STAMP_IRQHandler RTC_WKUP_IRQHandler FLASH_IRQHandler RCC_IRQHandler EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler DMA1_Stream0_IRQHandler DMA1_Stream1_IRQHandler DMA1_Stream2_IRQHandler DMA1_Stream3_IRQHandler DMA1_Stream4_IRQHandler DMA1_Stream5_IRQHandler DMA1_Stream6_IRQHandler ADC_IRQHandler CAN1_TX_IRQHandler CAN1_RX0_IRQHandler CAN1_RX1_IRQHandler CAN1_SCE_IRQHandler EXTI9_5_IRQHandler TIM1_BRK_TIM9_IRQHandler TIM1_UP_TIM10_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler TIM1_CC_IRQHandler TIM2_IRQHandler TIM3_IRQHandler TIM4_IRQHandler I2C1_EV_IRQHandler I2C1_ER_IRQHandler I2C2_EV_IRQHandler I2C2_ER_IRQHandler SPI1_IRQHandler SPI2_IRQHandler USART1_IRQHandler USART2_IRQHandler USART3_IRQHandler EXTI15_10_IRQHandler RTC_Alarm_IRQHandler OTG_FS_WKUP_IRQHandler TIM8_BRK_TIM12_IRQHandler TIM8_UP_TIM13_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler TIM8_CC_IRQHandler DMA1_Stream7_IRQHandler FSMC_IRQHandler SDIO_IRQHandler TIM5_IRQHandler SPI3_IRQHandler UART4_IRQHandler UART5_IRQHandler TIM6_DAC_IRQHandler TIM7_IRQHandler DMA2_Stream0_IRQHandler DMA2_Stream1_IRQHandler DMA2_Stream2_IRQHandler DMA2_Stream3_IRQHandler DMA2_Stream4_IRQHandler ETH_IRQHandler ETH_WKUP_IRQHandler CAN2_TX_IRQHandler CAN2_RX0_IRQHandler CAN2_RX1_IRQHandler CAN2_SCE_IRQHandler OTG_FS_IRQHandler DMA2_Stream5_IRQHandler DMA2_Stream6_IRQHandler DMA2_Stream7_IRQHandler USART6_IRQHandler I2C3_EV_IRQHandler I2C3_ER_IRQHandler OTG_HS_EP1_OUT_IRQHandler OTG_HS_EP1_IN_IRQHandler OTG_HS_WKUP_IRQHandler OTG_HS_IRQHandler DCMI_IRQHandler CRYP_IRQHandler HASH_RNG_IRQHandler FPU_IRQHandler B . ENDP ALIGN ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ALIGN ENDIF END ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f40xx.s ================================================ ;******************** (C) COPYRIGHT 2013 STMicroelectronics ******************** ;* File Name : startup_stm32f40xx.s ;* Author : MCD Application Team ;* Version : V1.3.0 ;* Date : 08-November-2013 ;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain. ;* Same as startup_stm32f40_41xxx.s and maintained for legacy purpose ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address ;* - Configure the system clock and the external SRAM mounted on ;* STM324xG-EVAL board to be used as data memory (optional, ;* to be enabled by user) ;* - Branches to __main in the C library (which eventually ;* calls main()). ;* After Reset the CortexM4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ; ; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); ; You may not use this file except in compliance with the License. ; You may obtain a copy of the License at: ; ; http://www.st.com/software_license_agreement_liberty_v2 ; ; Unless required by applicable law or agreed to in writing, software ; distributed under the License is distributed on an "AS IS" BASIS, ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; See the License for the specific language governing permissions and ; limitations under the License. ; ;******************************************************************************* ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; Stack Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; Heap Configuration ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap_Size EQU 0x00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog DCD PVD_IRQHandler ; PVD through EXTI Line detection DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line DCD FLASH_IRQHandler ; FLASH DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line0 DCD EXTI1_IRQHandler ; EXTI Line1 DCD EXTI2_IRQHandler ; EXTI Line2 DCD EXTI3_IRQHandler ; EXTI Line3 DCD EXTI4_IRQHandler ; EXTI Line4 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s DCD CAN1_TX_IRQHandler ; CAN1 TX DCD CAN1_RX0_IRQHandler ; CAN1 RX0 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 DCD CAN1_SCE_IRQHandler ; CAN1 SCE DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; External Line[15:10]s DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 DCD FSMC_IRQHandler ; FSMC DCD SDIO_IRQHandler ; SDIO DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 DCD UART4_IRQHandler ; UART4 DCD UART5_IRQHandler ; UART5 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 DCD ETH_IRQHandler ; Ethernet DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line DCD CAN2_TX_IRQHandler ; CAN2 TX DCD CAN2_RX0_IRQHandler ; CAN2 RX0 DCD CAN2_RX1_IRQHandler ; CAN2 RX1 DCD CAN2_SCE_IRQHandler ; CAN2 SCE DCD OTG_FS_IRQHandler ; USB OTG FS DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 DCD USART6_IRQHandler ; USART6 DCD I2C3_EV_IRQHandler ; I2C3 event DCD I2C3_ER_IRQHandler ; I2C3 error DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_IRQHandler ; DCMI DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WWDG_IRQHandler [WEAK] EXPORT PVD_IRQHandler [WEAK] EXPORT TAMP_STAMP_IRQHandler [WEAK] EXPORT RTC_WKUP_IRQHandler [WEAK] EXPORT FLASH_IRQHandler [WEAK] EXPORT RCC_IRQHandler [WEAK] EXPORT EXTI0_IRQHandler [WEAK] EXPORT EXTI1_IRQHandler [WEAK] EXPORT EXTI2_IRQHandler [WEAK] EXPORT EXTI3_IRQHandler [WEAK] EXPORT EXTI4_IRQHandler [WEAK] EXPORT DMA1_Stream0_IRQHandler [WEAK] EXPORT DMA1_Stream1_IRQHandler [WEAK] EXPORT DMA1_Stream2_IRQHandler [WEAK] EXPORT DMA1_Stream3_IRQHandler [WEAK] EXPORT DMA1_Stream4_IRQHandler [WEAK] EXPORT DMA1_Stream5_IRQHandler [WEAK] EXPORT DMA1_Stream6_IRQHandler [WEAK] EXPORT ADC_IRQHandler [WEAK] EXPORT CAN1_TX_IRQHandler [WEAK] EXPORT CAN1_RX0_IRQHandler [WEAK] EXPORT CAN1_RX1_IRQHandler [WEAK] EXPORT CAN1_SCE_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] EXPORT TIM4_IRQHandler [WEAK] EXPORT I2C1_EV_IRQHandler [WEAK] EXPORT I2C1_ER_IRQHandler [WEAK] EXPORT I2C2_EV_IRQHandler [WEAK] EXPORT I2C2_ER_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK] EXPORT SPI2_IRQHandler [WEAK] EXPORT USART1_IRQHandler [WEAK] EXPORT USART2_IRQHandler [WEAK] EXPORT USART3_IRQHandler [WEAK] EXPORT EXTI15_10_IRQHandler [WEAK] EXPORT RTC_Alarm_IRQHandler [WEAK] EXPORT OTG_FS_WKUP_IRQHandler [WEAK] EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] EXPORT TIM8_CC_IRQHandler [WEAK] EXPORT DMA1_Stream7_IRQHandler [WEAK] EXPORT FSMC_IRQHandler [WEAK] EXPORT SDIO_IRQHandler [WEAK] EXPORT TIM5_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT UART5_IRQHandler [WEAK] EXPORT TIM6_DAC_IRQHandler [WEAK] EXPORT TIM7_IRQHandler [WEAK] EXPORT DMA2_Stream0_IRQHandler [WEAK] EXPORT DMA2_Stream1_IRQHandler [WEAK] EXPORT DMA2_Stream2_IRQHandler [WEAK] EXPORT DMA2_Stream3_IRQHandler [WEAK] EXPORT DMA2_Stream4_IRQHandler [WEAK] EXPORT ETH_IRQHandler [WEAK] EXPORT ETH_WKUP_IRQHandler [WEAK] EXPORT CAN2_TX_IRQHandler [WEAK] EXPORT CAN2_RX0_IRQHandler [WEAK] EXPORT CAN2_RX1_IRQHandler [WEAK] EXPORT CAN2_SCE_IRQHandler [WEAK] EXPORT OTG_FS_IRQHandler [WEAK] EXPORT DMA2_Stream5_IRQHandler [WEAK] EXPORT DMA2_Stream6_IRQHandler [WEAK] EXPORT DMA2_Stream7_IRQHandler [WEAK] EXPORT USART6_IRQHandler [WEAK] EXPORT I2C3_EV_IRQHandler [WEAK] EXPORT I2C3_ER_IRQHandler [WEAK] EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] EXPORT OTG_HS_WKUP_IRQHandler [WEAK] EXPORT OTG_HS_IRQHandler [WEAK] EXPORT DCMI_IRQHandler [WEAK] EXPORT CRYP_IRQHandler [WEAK] EXPORT HASH_RNG_IRQHandler [WEAK] EXPORT FPU_IRQHandler [WEAK] WWDG_IRQHandler PVD_IRQHandler TAMP_STAMP_IRQHandler RTC_WKUP_IRQHandler FLASH_IRQHandler RCC_IRQHandler EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler DMA1_Stream0_IRQHandler DMA1_Stream1_IRQHandler DMA1_Stream2_IRQHandler DMA1_Stream3_IRQHandler DMA1_Stream4_IRQHandler DMA1_Stream5_IRQHandler DMA1_Stream6_IRQHandler ADC_IRQHandler CAN1_TX_IRQHandler CAN1_RX0_IRQHandler CAN1_RX1_IRQHandler CAN1_SCE_IRQHandler EXTI9_5_IRQHandler TIM1_BRK_TIM9_IRQHandler TIM1_UP_TIM10_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler TIM1_CC_IRQHandler TIM2_IRQHandler TIM3_IRQHandler TIM4_IRQHandler I2C1_EV_IRQHandler I2C1_ER_IRQHandler I2C2_EV_IRQHandler I2C2_ER_IRQHandler SPI1_IRQHandler SPI2_IRQHandler USART1_IRQHandler USART2_IRQHandler USART3_IRQHandler EXTI15_10_IRQHandler RTC_Alarm_IRQHandler OTG_FS_WKUP_IRQHandler TIM8_BRK_TIM12_IRQHandler TIM8_UP_TIM13_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler TIM8_CC_IRQHandler DMA1_Stream7_IRQHandler FSMC_IRQHandler SDIO_IRQHandler TIM5_IRQHandler SPI3_IRQHandler UART4_IRQHandler UART5_IRQHandler TIM6_DAC_IRQHandler TIM7_IRQHandler DMA2_Stream0_IRQHandler DMA2_Stream1_IRQHandler DMA2_Stream2_IRQHandler DMA2_Stream3_IRQHandler DMA2_Stream4_IRQHandler ETH_IRQHandler ETH_WKUP_IRQHandler CAN2_TX_IRQHandler CAN2_RX0_IRQHandler CAN2_RX1_IRQHandler CAN2_SCE_IRQHandler OTG_FS_IRQHandler DMA2_Stream5_IRQHandler DMA2_Stream6_IRQHandler DMA2_Stream7_IRQHandler USART6_IRQHandler I2C3_EV_IRQHandler I2C3_ER_IRQHandler OTG_HS_EP1_OUT_IRQHandler OTG_HS_EP1_IN_IRQHandler OTG_HS_WKUP_IRQHandler OTG_HS_IRQHandler DCMI_IRQHandler CRYP_IRQHandler HASH_RNG_IRQHandler FPU_IRQHandler B . ENDP ALIGN ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ALIGN ENDIF END ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f427_437xx.s ================================================ ;******************** (C) COPYRIGHT 2013 STMicroelectronics ******************** ;* File Name : startup_stm32f427_437xx.s ;* Author : MCD Application Team ;* Version : V1.3.0 ;* Date : 08-November-2013 ;* Description : STM32F427xx/437xx devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address ;* - Configure the system clock and the external SRAM/SDRAM mounted ;* on STM324x7I-EVAL board to be used as data memory ;* (optional, to be enabled by user) ;* - Branches to __main in the C library (which eventually ;* calls main()). ;* After Reset the CortexM4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ; ; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); ; You may not use this file except in compliance with the License. ; You may obtain a copy of the License at: ; ; http://www.st.com/software_license_agreement_liberty_v2 ; ; Unless required by applicable law or agreed to in writing, software ; distributed under the License is distributed on an "AS IS" BASIS, ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; See the License for the specific language governing permissions and ; limitations under the License. ; ;******************************************************************************* ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; Stack Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; Heap Configuration ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap_Size EQU 0x00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog DCD PVD_IRQHandler ; PVD through EXTI Line detection DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line DCD FLASH_IRQHandler ; FLASH DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line0 DCD EXTI1_IRQHandler ; EXTI Line1 DCD EXTI2_IRQHandler ; EXTI Line2 DCD EXTI3_IRQHandler ; EXTI Line3 DCD EXTI4_IRQHandler ; EXTI Line4 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s DCD CAN1_TX_IRQHandler ; CAN1 TX DCD CAN1_RX0_IRQHandler ; CAN1 RX0 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 DCD CAN1_SCE_IRQHandler ; CAN1 SCE DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; External Line[15:10]s DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 DCD FMC_IRQHandler ; FMC DCD SDIO_IRQHandler ; SDIO DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 DCD UART4_IRQHandler ; UART4 DCD UART5_IRQHandler ; UART5 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 DCD ETH_IRQHandler ; Ethernet DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line DCD CAN2_TX_IRQHandler ; CAN2 TX DCD CAN2_RX0_IRQHandler ; CAN2 RX0 DCD CAN2_RX1_IRQHandler ; CAN2 RX1 DCD CAN2_SCE_IRQHandler ; CAN2 SCE DCD OTG_FS_IRQHandler ; USB OTG FS DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 DCD USART6_IRQHandler ; USART6 DCD I2C3_EV_IRQHandler ; I2C3 event DCD I2C3_ER_IRQHandler ; I2C3 error DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_IRQHandler ; DCMI DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 DCD UART8_IRQHandler ; UART8 DCD SPI4_IRQHandler ; SPI4 DCD SPI5_IRQHandler ; SPI5 DCD SPI6_IRQHandler ; SPI6 DCD SAI1_IRQHandler ; SAI1 DCD 0 ; Reserved DCD 0 ; Reserved DCD DMA2D_IRQHandler ; DMA2D __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WWDG_IRQHandler [WEAK] EXPORT PVD_IRQHandler [WEAK] EXPORT TAMP_STAMP_IRQHandler [WEAK] EXPORT RTC_WKUP_IRQHandler [WEAK] EXPORT FLASH_IRQHandler [WEAK] EXPORT RCC_IRQHandler [WEAK] EXPORT EXTI0_IRQHandler [WEAK] EXPORT EXTI1_IRQHandler [WEAK] EXPORT EXTI2_IRQHandler [WEAK] EXPORT EXTI3_IRQHandler [WEAK] EXPORT EXTI4_IRQHandler [WEAK] EXPORT DMA1_Stream0_IRQHandler [WEAK] EXPORT DMA1_Stream1_IRQHandler [WEAK] EXPORT DMA1_Stream2_IRQHandler [WEAK] EXPORT DMA1_Stream3_IRQHandler [WEAK] EXPORT DMA1_Stream4_IRQHandler [WEAK] EXPORT DMA1_Stream5_IRQHandler [WEAK] EXPORT DMA1_Stream6_IRQHandler [WEAK] EXPORT ADC_IRQHandler [WEAK] EXPORT CAN1_TX_IRQHandler [WEAK] EXPORT CAN1_RX0_IRQHandler [WEAK] EXPORT CAN1_RX1_IRQHandler [WEAK] EXPORT CAN1_SCE_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] EXPORT TIM4_IRQHandler [WEAK] EXPORT I2C1_EV_IRQHandler [WEAK] EXPORT I2C1_ER_IRQHandler [WEAK] EXPORT I2C2_EV_IRQHandler [WEAK] EXPORT I2C2_ER_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK] EXPORT SPI2_IRQHandler [WEAK] EXPORT USART1_IRQHandler [WEAK] EXPORT USART2_IRQHandler [WEAK] EXPORT USART3_IRQHandler [WEAK] EXPORT EXTI15_10_IRQHandler [WEAK] EXPORT RTC_Alarm_IRQHandler [WEAK] EXPORT OTG_FS_WKUP_IRQHandler [WEAK] EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] EXPORT TIM8_CC_IRQHandler [WEAK] EXPORT DMA1_Stream7_IRQHandler [WEAK] EXPORT FMC_IRQHandler [WEAK] EXPORT SDIO_IRQHandler [WEAK] EXPORT TIM5_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT UART5_IRQHandler [WEAK] EXPORT TIM6_DAC_IRQHandler [WEAK] EXPORT TIM7_IRQHandler [WEAK] EXPORT DMA2_Stream0_IRQHandler [WEAK] EXPORT DMA2_Stream1_IRQHandler [WEAK] EXPORT DMA2_Stream2_IRQHandler [WEAK] EXPORT DMA2_Stream3_IRQHandler [WEAK] EXPORT DMA2_Stream4_IRQHandler [WEAK] EXPORT ETH_IRQHandler [WEAK] EXPORT ETH_WKUP_IRQHandler [WEAK] EXPORT CAN2_TX_IRQHandler [WEAK] EXPORT CAN2_RX0_IRQHandler [WEAK] EXPORT CAN2_RX1_IRQHandler [WEAK] EXPORT CAN2_SCE_IRQHandler [WEAK] EXPORT OTG_FS_IRQHandler [WEAK] EXPORT DMA2_Stream5_IRQHandler [WEAK] EXPORT DMA2_Stream6_IRQHandler [WEAK] EXPORT DMA2_Stream7_IRQHandler [WEAK] EXPORT USART6_IRQHandler [WEAK] EXPORT I2C3_EV_IRQHandler [WEAK] EXPORT I2C3_ER_IRQHandler [WEAK] EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] EXPORT OTG_HS_WKUP_IRQHandler [WEAK] EXPORT OTG_HS_IRQHandler [WEAK] EXPORT DCMI_IRQHandler [WEAK] EXPORT CRYP_IRQHandler [WEAK] EXPORT HASH_RNG_IRQHandler [WEAK] EXPORT FPU_IRQHandler [WEAK] EXPORT UART7_IRQHandler [WEAK] EXPORT UART8_IRQHandler [WEAK] EXPORT SPI4_IRQHandler [WEAK] EXPORT SPI5_IRQHandler [WEAK] EXPORT SPI6_IRQHandler [WEAK] EXPORT SAI1_IRQHandler [WEAK] EXPORT DMA2D_IRQHandler [WEAK] WWDG_IRQHandler PVD_IRQHandler TAMP_STAMP_IRQHandler RTC_WKUP_IRQHandler FLASH_IRQHandler RCC_IRQHandler EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler DMA1_Stream0_IRQHandler DMA1_Stream1_IRQHandler DMA1_Stream2_IRQHandler DMA1_Stream3_IRQHandler DMA1_Stream4_IRQHandler DMA1_Stream5_IRQHandler DMA1_Stream6_IRQHandler ADC_IRQHandler CAN1_TX_IRQHandler CAN1_RX0_IRQHandler CAN1_RX1_IRQHandler CAN1_SCE_IRQHandler EXTI9_5_IRQHandler TIM1_BRK_TIM9_IRQHandler TIM1_UP_TIM10_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler TIM1_CC_IRQHandler TIM2_IRQHandler TIM3_IRQHandler TIM4_IRQHandler I2C1_EV_IRQHandler I2C1_ER_IRQHandler I2C2_EV_IRQHandler I2C2_ER_IRQHandler SPI1_IRQHandler SPI2_IRQHandler USART1_IRQHandler USART2_IRQHandler USART3_IRQHandler EXTI15_10_IRQHandler RTC_Alarm_IRQHandler OTG_FS_WKUP_IRQHandler TIM8_BRK_TIM12_IRQHandler TIM8_UP_TIM13_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler TIM8_CC_IRQHandler DMA1_Stream7_IRQHandler FMC_IRQHandler SDIO_IRQHandler TIM5_IRQHandler SPI3_IRQHandler UART4_IRQHandler UART5_IRQHandler TIM6_DAC_IRQHandler TIM7_IRQHandler DMA2_Stream0_IRQHandler DMA2_Stream1_IRQHandler DMA2_Stream2_IRQHandler DMA2_Stream3_IRQHandler DMA2_Stream4_IRQHandler ETH_IRQHandler ETH_WKUP_IRQHandler CAN2_TX_IRQHandler CAN2_RX0_IRQHandler CAN2_RX1_IRQHandler CAN2_SCE_IRQHandler OTG_FS_IRQHandler DMA2_Stream5_IRQHandler DMA2_Stream6_IRQHandler DMA2_Stream7_IRQHandler USART6_IRQHandler I2C3_EV_IRQHandler I2C3_ER_IRQHandler OTG_HS_EP1_OUT_IRQHandler OTG_HS_EP1_IN_IRQHandler OTG_HS_WKUP_IRQHandler OTG_HS_IRQHandler DCMI_IRQHandler CRYP_IRQHandler HASH_RNG_IRQHandler FPU_IRQHandler UART7_IRQHandler UART8_IRQHandler SPI4_IRQHandler SPI5_IRQHandler SPI6_IRQHandler SAI1_IRQHandler DMA2D_IRQHandler B . ENDP ALIGN ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ALIGN ENDIF END ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f427x.s ================================================ ;******************** (C) COPYRIGHT 2013 STMicroelectronics ******************** ;* File Name : startup_stm32f427x.s ;* Author : MCD Application Team ;* Version : V1.3.0 ;* Date : 08-November-2013 ;* Description : STM32F427xx/437xx devices vector table for MDK-ARM toolchain. ;* Same as startup_stm32f427_437xx.s and maintained for legacy purpose ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address ;* - Configure the system clock and the external SRAM/SDRAM mounted ;* on STM324x9I-EVAL/STM324x7I-EVALs board to be used as data memory ;* (optional, to be enabled by user) ;* - Branches to __main in the C library (which eventually ;* calls main()). ;* After Reset the CortexM4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ; ; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); ; You may not use this file except in compliance with the License. ; You may obtain a copy of the License at: ; ; http://www.st.com/software_license_agreement_liberty_v2 ; ; Unless required by applicable law or agreed to in writing, software ; distributed under the License is distributed on an "AS IS" BASIS, ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; See the License for the specific language governing permissions and ; limitations under the License. ; ;******************************************************************************* ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; Stack Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; Heap Configuration ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap_Size EQU 0x00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog DCD PVD_IRQHandler ; PVD through EXTI Line detection DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line DCD FLASH_IRQHandler ; FLASH DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line0 DCD EXTI1_IRQHandler ; EXTI Line1 DCD EXTI2_IRQHandler ; EXTI Line2 DCD EXTI3_IRQHandler ; EXTI Line3 DCD EXTI4_IRQHandler ; EXTI Line4 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s DCD CAN1_TX_IRQHandler ; CAN1 TX DCD CAN1_RX0_IRQHandler ; CAN1 RX0 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 DCD CAN1_SCE_IRQHandler ; CAN1 SCE DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; External Line[15:10]s DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 DCD FMC_IRQHandler ; FMC DCD SDIO_IRQHandler ; SDIO DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 DCD UART4_IRQHandler ; UART4 DCD UART5_IRQHandler ; UART5 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 DCD ETH_IRQHandler ; Ethernet DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line DCD CAN2_TX_IRQHandler ; CAN2 TX DCD CAN2_RX0_IRQHandler ; CAN2 RX0 DCD CAN2_RX1_IRQHandler ; CAN2 RX1 DCD CAN2_SCE_IRQHandler ; CAN2 SCE DCD OTG_FS_IRQHandler ; USB OTG FS DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 DCD USART6_IRQHandler ; USART6 DCD I2C3_EV_IRQHandler ; I2C3 event DCD I2C3_ER_IRQHandler ; I2C3 error DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_IRQHandler ; DCMI DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 DCD UART8_IRQHandler ; UART8 DCD SPI4_IRQHandler ; SPI4 DCD SPI5_IRQHandler ; SPI5 DCD SPI6_IRQHandler ; SPI6 DCD SAI1_IRQHandler ; SAI1 DCD 0 ; Reserved DCD 0 ; Reserved DCD DMA2D_IRQHandler ; DMA2D __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WWDG_IRQHandler [WEAK] EXPORT PVD_IRQHandler [WEAK] EXPORT TAMP_STAMP_IRQHandler [WEAK] EXPORT RTC_WKUP_IRQHandler [WEAK] EXPORT FLASH_IRQHandler [WEAK] EXPORT RCC_IRQHandler [WEAK] EXPORT EXTI0_IRQHandler [WEAK] EXPORT EXTI1_IRQHandler [WEAK] EXPORT EXTI2_IRQHandler [WEAK] EXPORT EXTI3_IRQHandler [WEAK] EXPORT EXTI4_IRQHandler [WEAK] EXPORT DMA1_Stream0_IRQHandler [WEAK] EXPORT DMA1_Stream1_IRQHandler [WEAK] EXPORT DMA1_Stream2_IRQHandler [WEAK] EXPORT DMA1_Stream3_IRQHandler [WEAK] EXPORT DMA1_Stream4_IRQHandler [WEAK] EXPORT DMA1_Stream5_IRQHandler [WEAK] EXPORT DMA1_Stream6_IRQHandler [WEAK] EXPORT ADC_IRQHandler [WEAK] EXPORT CAN1_TX_IRQHandler [WEAK] EXPORT CAN1_RX0_IRQHandler [WEAK] EXPORT CAN1_RX1_IRQHandler [WEAK] EXPORT CAN1_SCE_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] EXPORT TIM4_IRQHandler [WEAK] EXPORT I2C1_EV_IRQHandler [WEAK] EXPORT I2C1_ER_IRQHandler [WEAK] EXPORT I2C2_EV_IRQHandler [WEAK] EXPORT I2C2_ER_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK] EXPORT SPI2_IRQHandler [WEAK] EXPORT USART1_IRQHandler [WEAK] EXPORT USART2_IRQHandler [WEAK] EXPORT USART3_IRQHandler [WEAK] EXPORT EXTI15_10_IRQHandler [WEAK] EXPORT RTC_Alarm_IRQHandler [WEAK] EXPORT OTG_FS_WKUP_IRQHandler [WEAK] EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] EXPORT TIM8_CC_IRQHandler [WEAK] EXPORT DMA1_Stream7_IRQHandler [WEAK] EXPORT FMC_IRQHandler [WEAK] EXPORT SDIO_IRQHandler [WEAK] EXPORT TIM5_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT UART5_IRQHandler [WEAK] EXPORT TIM6_DAC_IRQHandler [WEAK] EXPORT TIM7_IRQHandler [WEAK] EXPORT DMA2_Stream0_IRQHandler [WEAK] EXPORT DMA2_Stream1_IRQHandler [WEAK] EXPORT DMA2_Stream2_IRQHandler [WEAK] EXPORT DMA2_Stream3_IRQHandler [WEAK] EXPORT DMA2_Stream4_IRQHandler [WEAK] EXPORT ETH_IRQHandler [WEAK] EXPORT ETH_WKUP_IRQHandler [WEAK] EXPORT CAN2_TX_IRQHandler [WEAK] EXPORT CAN2_RX0_IRQHandler [WEAK] EXPORT CAN2_RX1_IRQHandler [WEAK] EXPORT CAN2_SCE_IRQHandler [WEAK] EXPORT OTG_FS_IRQHandler [WEAK] EXPORT DMA2_Stream5_IRQHandler [WEAK] EXPORT DMA2_Stream6_IRQHandler [WEAK] EXPORT DMA2_Stream7_IRQHandler [WEAK] EXPORT USART6_IRQHandler [WEAK] EXPORT I2C3_EV_IRQHandler [WEAK] EXPORT I2C3_ER_IRQHandler [WEAK] EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] EXPORT OTG_HS_WKUP_IRQHandler [WEAK] EXPORT OTG_HS_IRQHandler [WEAK] EXPORT DCMI_IRQHandler [WEAK] EXPORT CRYP_IRQHandler [WEAK] EXPORT HASH_RNG_IRQHandler [WEAK] EXPORT FPU_IRQHandler [WEAK] EXPORT UART7_IRQHandler [WEAK] EXPORT UART8_IRQHandler [WEAK] EXPORT SPI4_IRQHandler [WEAK] EXPORT SPI5_IRQHandler [WEAK] EXPORT SPI6_IRQHandler [WEAK] EXPORT SAI1_IRQHandler [WEAK] EXPORT DMA2D_IRQHandler [WEAK] WWDG_IRQHandler PVD_IRQHandler TAMP_STAMP_IRQHandler RTC_WKUP_IRQHandler FLASH_IRQHandler RCC_IRQHandler EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler DMA1_Stream0_IRQHandler DMA1_Stream1_IRQHandler DMA1_Stream2_IRQHandler DMA1_Stream3_IRQHandler DMA1_Stream4_IRQHandler DMA1_Stream5_IRQHandler DMA1_Stream6_IRQHandler ADC_IRQHandler CAN1_TX_IRQHandler CAN1_RX0_IRQHandler CAN1_RX1_IRQHandler CAN1_SCE_IRQHandler EXTI9_5_IRQHandler TIM1_BRK_TIM9_IRQHandler TIM1_UP_TIM10_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler TIM1_CC_IRQHandler TIM2_IRQHandler TIM3_IRQHandler TIM4_IRQHandler I2C1_EV_IRQHandler I2C1_ER_IRQHandler I2C2_EV_IRQHandler I2C2_ER_IRQHandler SPI1_IRQHandler SPI2_IRQHandler USART1_IRQHandler USART2_IRQHandler USART3_IRQHandler EXTI15_10_IRQHandler RTC_Alarm_IRQHandler OTG_FS_WKUP_IRQHandler TIM8_BRK_TIM12_IRQHandler TIM8_UP_TIM13_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler TIM8_CC_IRQHandler DMA1_Stream7_IRQHandler FMC_IRQHandler SDIO_IRQHandler TIM5_IRQHandler SPI3_IRQHandler UART4_IRQHandler UART5_IRQHandler TIM6_DAC_IRQHandler TIM7_IRQHandler DMA2_Stream0_IRQHandler DMA2_Stream1_IRQHandler DMA2_Stream2_IRQHandler DMA2_Stream3_IRQHandler DMA2_Stream4_IRQHandler ETH_IRQHandler ETH_WKUP_IRQHandler CAN2_TX_IRQHandler CAN2_RX0_IRQHandler CAN2_RX1_IRQHandler CAN2_SCE_IRQHandler OTG_FS_IRQHandler DMA2_Stream5_IRQHandler DMA2_Stream6_IRQHandler DMA2_Stream7_IRQHandler USART6_IRQHandler I2C3_EV_IRQHandler I2C3_ER_IRQHandler OTG_HS_EP1_OUT_IRQHandler OTG_HS_EP1_IN_IRQHandler OTG_HS_WKUP_IRQHandler OTG_HS_IRQHandler DCMI_IRQHandler CRYP_IRQHandler HASH_RNG_IRQHandler FPU_IRQHandler UART7_IRQHandler UART8_IRQHandler SPI4_IRQHandler SPI5_IRQHandler SPI6_IRQHandler SAI1_IRQHandler DMA2D_IRQHandler B . ENDP ALIGN ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ALIGN ENDIF END ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/arm/startup_stm32f429_439xx.s ================================================ ;******************** (C) COPYRIGHT 2013 STMicroelectronics ******************** ;* File Name : startup_stm32f429_439xx.s ;* Author : MCD Application Team ;* Version : V1.3.0 ;* Date : 08-November-2013 ;* Description : STM32F429xx/439xx devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == Reset_Handler ;* - Set the vector table entries with the exceptions ISR address ;* - Configure the system clock and the external SRAM/SDRAM mounted ;* on STM324x9I-EVAL boards to be used as data memory ;* (optional, to be enabled by user) ;* - Branches to __main in the C library (which eventually ;* calls main()). ;* After Reset the CortexM4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ; ; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); ; You may not use this file except in compliance with the License. ; You may obtain a copy of the License at: ; ; http://www.st.com/software_license_agreement_liberty_v2 ; ; Unless required by applicable law or agreed to in writing, software ; distributed under the License is distributed on an "AS IS" BASIS, ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ; See the License for the specific language governing permissions and ; limitations under the License. ; ;******************************************************************************* ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs ; Stack Configuration ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Stack_Size EQU 0x00000400 AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size __initial_sp ; Heap Configuration ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; Heap_Size EQU 0x00000200 AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base Heap_Mem SPACE Heap_Size __heap_limit PRESERVE8 THUMB ; Vector Table Mapped to Address 0 at Reset AREA RESET, DATA, READONLY EXPORT __Vectors EXPORT __Vectors_End EXPORT __Vectors_Size __Vectors DCD __initial_sp ; Top of Stack DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog DCD PVD_IRQHandler ; PVD through EXTI Line detection DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line DCD FLASH_IRQHandler ; FLASH DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line0 DCD EXTI1_IRQHandler ; EXTI Line1 DCD EXTI2_IRQHandler ; EXTI Line2 DCD EXTI3_IRQHandler ; EXTI Line3 DCD EXTI4_IRQHandler ; EXTI Line4 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s DCD CAN1_TX_IRQHandler ; CAN1 TX DCD CAN1_RX0_IRQHandler ; CAN1 RX0 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 DCD CAN1_SCE_IRQHandler ; CAN1 SCE DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; External Line[15:10]s DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 DCD FMC_IRQHandler ; FMC DCD SDIO_IRQHandler ; SDIO DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 DCD UART4_IRQHandler ; UART4 DCD UART5_IRQHandler ; UART5 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 DCD ETH_IRQHandler ; Ethernet DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line DCD CAN2_TX_IRQHandler ; CAN2 TX DCD CAN2_RX0_IRQHandler ; CAN2 RX0 DCD CAN2_RX1_IRQHandler ; CAN2 RX1 DCD CAN2_SCE_IRQHandler ; CAN2 SCE DCD OTG_FS_IRQHandler ; USB OTG FS DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 DCD USART6_IRQHandler ; USART6 DCD I2C3_EV_IRQHandler ; I2C3 event DCD I2C3_ER_IRQHandler ; I2C3 error DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_IRQHandler ; DCMI DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 DCD UART8_IRQHandler ; UART8 DCD SPI4_IRQHandler ; SPI4 DCD SPI5_IRQHandler ; SPI5 DCD SPI6_IRQHandler ; SPI6 DCD SAI1_IRQHandler ; SAI1 DCD LTDC_IRQHandler ; LTDC DCD LTDC_ER_IRQHandler ; LTDC error DCD DMA2D_IRQHandler ; DMA2D __Vectors_End __Vectors_Size EQU __Vectors_End - __Vectors AREA |.text|, CODE, READONLY ; Reset handler Reset_Handler PROC EXPORT Reset_Handler [WEAK] IMPORT SystemInit IMPORT __main LDR R0, =SystemInit BLX R0 LDR R0, =__main BX R0 ENDP ; Dummy Exception Handlers (infinite loops which can be modified) NMI_Handler PROC EXPORT NMI_Handler [WEAK] B . ENDP HardFault_Handler\ PROC EXPORT HardFault_Handler [WEAK] B . ENDP MemManage_Handler\ PROC EXPORT MemManage_Handler [WEAK] B . ENDP BusFault_Handler\ PROC EXPORT BusFault_Handler [WEAK] B . ENDP UsageFault_Handler\ PROC EXPORT UsageFault_Handler [WEAK] B . ENDP SVC_Handler PROC EXPORT SVC_Handler [WEAK] B . ENDP DebugMon_Handler\ PROC EXPORT DebugMon_Handler [WEAK] B . ENDP PendSV_Handler PROC EXPORT PendSV_Handler [WEAK] B . ENDP SysTick_Handler PROC EXPORT SysTick_Handler [WEAK] B . ENDP Default_Handler PROC EXPORT WWDG_IRQHandler [WEAK] EXPORT PVD_IRQHandler [WEAK] EXPORT TAMP_STAMP_IRQHandler [WEAK] EXPORT RTC_WKUP_IRQHandler [WEAK] EXPORT FLASH_IRQHandler [WEAK] EXPORT RCC_IRQHandler [WEAK] EXPORT EXTI0_IRQHandler [WEAK] EXPORT EXTI1_IRQHandler [WEAK] EXPORT EXTI2_IRQHandler [WEAK] EXPORT EXTI3_IRQHandler [WEAK] EXPORT EXTI4_IRQHandler [WEAK] EXPORT DMA1_Stream0_IRQHandler [WEAK] EXPORT DMA1_Stream1_IRQHandler [WEAK] EXPORT DMA1_Stream2_IRQHandler [WEAK] EXPORT DMA1_Stream3_IRQHandler [WEAK] EXPORT DMA1_Stream4_IRQHandler [WEAK] EXPORT DMA1_Stream5_IRQHandler [WEAK] EXPORT DMA1_Stream6_IRQHandler [WEAK] EXPORT ADC_IRQHandler [WEAK] EXPORT CAN1_TX_IRQHandler [WEAK] EXPORT CAN1_RX0_IRQHandler [WEAK] EXPORT CAN1_RX1_IRQHandler [WEAK] EXPORT CAN1_SCE_IRQHandler [WEAK] EXPORT EXTI9_5_IRQHandler [WEAK] EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] EXPORT TIM1_CC_IRQHandler [WEAK] EXPORT TIM2_IRQHandler [WEAK] EXPORT TIM3_IRQHandler [WEAK] EXPORT TIM4_IRQHandler [WEAK] EXPORT I2C1_EV_IRQHandler [WEAK] EXPORT I2C1_ER_IRQHandler [WEAK] EXPORT I2C2_EV_IRQHandler [WEAK] EXPORT I2C2_ER_IRQHandler [WEAK] EXPORT SPI1_IRQHandler [WEAK] EXPORT SPI2_IRQHandler [WEAK] EXPORT USART1_IRQHandler [WEAK] EXPORT USART2_IRQHandler [WEAK] EXPORT USART3_IRQHandler [WEAK] EXPORT EXTI15_10_IRQHandler [WEAK] EXPORT RTC_Alarm_IRQHandler [WEAK] EXPORT OTG_FS_WKUP_IRQHandler [WEAK] EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] EXPORT TIM8_CC_IRQHandler [WEAK] EXPORT DMA1_Stream7_IRQHandler [WEAK] EXPORT FMC_IRQHandler [WEAK] EXPORT SDIO_IRQHandler [WEAK] EXPORT TIM5_IRQHandler [WEAK] EXPORT SPI3_IRQHandler [WEAK] EXPORT UART4_IRQHandler [WEAK] EXPORT UART5_IRQHandler [WEAK] EXPORT TIM6_DAC_IRQHandler [WEAK] EXPORT TIM7_IRQHandler [WEAK] EXPORT DMA2_Stream0_IRQHandler [WEAK] EXPORT DMA2_Stream1_IRQHandler [WEAK] EXPORT DMA2_Stream2_IRQHandler [WEAK] EXPORT DMA2_Stream3_IRQHandler [WEAK] EXPORT DMA2_Stream4_IRQHandler [WEAK] EXPORT ETH_IRQHandler [WEAK] EXPORT ETH_WKUP_IRQHandler [WEAK] EXPORT CAN2_TX_IRQHandler [WEAK] EXPORT CAN2_RX0_IRQHandler [WEAK] EXPORT CAN2_RX1_IRQHandler [WEAK] EXPORT CAN2_SCE_IRQHandler [WEAK] EXPORT OTG_FS_IRQHandler [WEAK] EXPORT DMA2_Stream5_IRQHandler [WEAK] EXPORT DMA2_Stream6_IRQHandler [WEAK] EXPORT DMA2_Stream7_IRQHandler [WEAK] EXPORT USART6_IRQHandler [WEAK] EXPORT I2C3_EV_IRQHandler [WEAK] EXPORT I2C3_ER_IRQHandler [WEAK] EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] EXPORT OTG_HS_WKUP_IRQHandler [WEAK] EXPORT OTG_HS_IRQHandler [WEAK] EXPORT DCMI_IRQHandler [WEAK] EXPORT CRYP_IRQHandler [WEAK] EXPORT HASH_RNG_IRQHandler [WEAK] EXPORT FPU_IRQHandler [WEAK] EXPORT UART7_IRQHandler [WEAK] EXPORT UART8_IRQHandler [WEAK] EXPORT SPI4_IRQHandler [WEAK] EXPORT SPI5_IRQHandler [WEAK] EXPORT SPI6_IRQHandler [WEAK] EXPORT SAI1_IRQHandler [WEAK] EXPORT LTDC_IRQHandler [WEAK] EXPORT LTDC_ER_IRQHandler [WEAK] EXPORT DMA2D_IRQHandler [WEAK] WWDG_IRQHandler PVD_IRQHandler TAMP_STAMP_IRQHandler RTC_WKUP_IRQHandler FLASH_IRQHandler RCC_IRQHandler EXTI0_IRQHandler EXTI1_IRQHandler EXTI2_IRQHandler EXTI3_IRQHandler EXTI4_IRQHandler DMA1_Stream0_IRQHandler DMA1_Stream1_IRQHandler DMA1_Stream2_IRQHandler DMA1_Stream3_IRQHandler DMA1_Stream4_IRQHandler DMA1_Stream5_IRQHandler DMA1_Stream6_IRQHandler ADC_IRQHandler CAN1_TX_IRQHandler CAN1_RX0_IRQHandler CAN1_RX1_IRQHandler CAN1_SCE_IRQHandler EXTI9_5_IRQHandler TIM1_BRK_TIM9_IRQHandler TIM1_UP_TIM10_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler TIM1_CC_IRQHandler TIM2_IRQHandler TIM3_IRQHandler TIM4_IRQHandler I2C1_EV_IRQHandler I2C1_ER_IRQHandler I2C2_EV_IRQHandler I2C2_ER_IRQHandler SPI1_IRQHandler SPI2_IRQHandler USART1_IRQHandler USART2_IRQHandler USART3_IRQHandler EXTI15_10_IRQHandler RTC_Alarm_IRQHandler OTG_FS_WKUP_IRQHandler TIM8_BRK_TIM12_IRQHandler TIM8_UP_TIM13_IRQHandler TIM8_TRG_COM_TIM14_IRQHandler TIM8_CC_IRQHandler DMA1_Stream7_IRQHandler FMC_IRQHandler SDIO_IRQHandler TIM5_IRQHandler SPI3_IRQHandler UART4_IRQHandler UART5_IRQHandler TIM6_DAC_IRQHandler TIM7_IRQHandler DMA2_Stream0_IRQHandler DMA2_Stream1_IRQHandler DMA2_Stream2_IRQHandler DMA2_Stream3_IRQHandler DMA2_Stream4_IRQHandler ETH_IRQHandler ETH_WKUP_IRQHandler CAN2_TX_IRQHandler CAN2_RX0_IRQHandler CAN2_RX1_IRQHandler CAN2_SCE_IRQHandler OTG_FS_IRQHandler DMA2_Stream5_IRQHandler DMA2_Stream6_IRQHandler DMA2_Stream7_IRQHandler USART6_IRQHandler I2C3_EV_IRQHandler I2C3_ER_IRQHandler OTG_HS_EP1_OUT_IRQHandler OTG_HS_EP1_IN_IRQHandler OTG_HS_WKUP_IRQHandler OTG_HS_IRQHandler DCMI_IRQHandler CRYP_IRQHandler HASH_RNG_IRQHandler FPU_IRQHandler UART7_IRQHandler UART8_IRQHandler SPI4_IRQHandler SPI5_IRQHandler SPI6_IRQHandler SAI1_IRQHandler LTDC_IRQHandler LTDC_ER_IRQHandler DMA2D_IRQHandler B . ENDP ALIGN ;******************************************************************************* ; User Stack and Heap initialization ;******************************************************************************* IF :DEF:__MICROLIB EXPORT __initial_sp EXPORT __heap_base EXPORT __heap_limit ELSE IMPORT __use_two_region_memory EXPORT __user_initial_stackheap __user_initial_stackheap LDR R0, = Heap_Mem LDR R1, =(Stack_Mem + Stack_Size) LDR R2, = (Heap_Mem + Heap_Size) LDR R3, = Stack_Mem BX LR ALIGN ENDIF END ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_stm32f401xx.s ================================================ /** ****************************************************************************** * @file startup_stm32f40xx.s * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief STM32F401xx Devices vector table for RIDE7 toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Configure the clock system * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ .syntax unified .cpu cortex-m3 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call the application's entry point.*/ bl main bx lr .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_IRQHandler /* PVD through EXTI Line detection */ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ .word FLASH_IRQHandler /* FLASH */ .word RCC_IRQHandler /* RCC */ .word EXTI0_IRQHandler /* EXTI Line0 */ .word EXTI1_IRQHandler /* EXTI Line1 */ .word EXTI2_IRQHandler /* EXTI Line2 */ .word EXTI3_IRQHandler /* EXTI Line3 */ .word EXTI4_IRQHandler /* EXTI Line4 */ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word EXTI9_5_IRQHandler /* External Line[9:5]s */ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ .word TIM2_IRQHandler /* TIM2 */ .word TIM3_IRQHandler /* TIM3 */ .word TIM4_IRQHandler /* TIM4 */ .word I2C1_EV_IRQHandler /* I2C1 Event */ .word I2C1_ER_IRQHandler /* I2C1 Error */ .word I2C2_EV_IRQHandler /* I2C2 Event */ .word I2C2_ER_IRQHandler /* I2C2 Error */ .word SPI1_IRQHandler /* SPI1 */ .word SPI2_IRQHandler /* SPI2 */ .word USART1_IRQHandler /* USART1 */ .word USART2_IRQHandler /* USART2 */ .word 0 /* Reserved */ .word EXTI15_10_IRQHandler /* External Line[15:10]s */ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ .word 0 /* Reserved */ .word SDIO_IRQHandler /* SDIO */ .word TIM5_IRQHandler /* TIM5 */ .word SPI3_IRQHandler /* SPI3 */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word OTG_FS_IRQHandler /* USB OTG FS */ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ .word USART6_IRQHandler /* USART6 */ .word I2C3_EV_IRQHandler /* I2C3 event */ .word I2C3_ER_IRQHandler /* I2C3 error */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word FPU_IRQHandler /* FPU */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word SPI4_IRQHandler /* SPI4 */ /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM9_IRQHandler .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler .weak TIM1_UP_TIM10_IRQHandler .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM11_IRQHandler .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak SDIO_IRQHandler .thumb_set SDIO_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_stm32f40_41xxx.s ================================================ /** ****************************************************************************** * @file startup_stm32f40_41xxx.s * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief STM32F40xxx/41xxx Devices vector table for RIDE7 toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Configure the clock system and the external SRAM mounted on * STM324xG-EVAL board to be used as data memory (optional, * to be enabled by user) * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ .syntax unified .cpu cortex-m3 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call the application's entry point.*/ bl main bx lr .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_IRQHandler /* PVD through EXTI Line detection */ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ .word FLASH_IRQHandler /* FLASH */ .word RCC_IRQHandler /* RCC */ .word EXTI0_IRQHandler /* EXTI Line0 */ .word EXTI1_IRQHandler /* EXTI Line1 */ .word EXTI2_IRQHandler /* EXTI Line2 */ .word EXTI3_IRQHandler /* EXTI Line3 */ .word EXTI4_IRQHandler /* EXTI Line4 */ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ .word CAN1_TX_IRQHandler /* CAN1 TX */ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ .word CAN1_SCE_IRQHandler /* CAN1 SCE */ .word EXTI9_5_IRQHandler /* External Line[9:5]s */ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ .word TIM2_IRQHandler /* TIM2 */ .word TIM3_IRQHandler /* TIM3 */ .word TIM4_IRQHandler /* TIM4 */ .word I2C1_EV_IRQHandler /* I2C1 Event */ .word I2C1_ER_IRQHandler /* I2C1 Error */ .word I2C2_EV_IRQHandler /* I2C2 Event */ .word I2C2_ER_IRQHandler /* I2C2 Error */ .word SPI1_IRQHandler /* SPI1 */ .word SPI2_IRQHandler /* SPI2 */ .word USART1_IRQHandler /* USART1 */ .word USART2_IRQHandler /* USART2 */ .word USART3_IRQHandler /* USART3 */ .word EXTI15_10_IRQHandler /* External Line[15:10]s */ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ .word FSMC_IRQHandler /* FSMC */ .word SDIO_IRQHandler /* SDIO */ .word TIM5_IRQHandler /* TIM5 */ .word SPI3_IRQHandler /* SPI3 */ .word UART4_IRQHandler /* UART4 */ .word UART5_IRQHandler /* UART5 */ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ .word TIM7_IRQHandler /* TIM7 */ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ .word ETH_IRQHandler /* Ethernet */ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ .word CAN2_TX_IRQHandler /* CAN2 TX */ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ .word CAN2_SCE_IRQHandler /* CAN2 SCE */ .word OTG_FS_IRQHandler /* USB OTG FS */ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ .word USART6_IRQHandler /* USART6 */ .word I2C3_EV_IRQHandler /* I2C3 event */ .word I2C3_ER_IRQHandler /* I2C3 error */ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ .word OTG_HS_IRQHandler /* USB OTG HS */ .word DCMI_IRQHandler /* DCMI */ .word CRYP_IRQHandler /* CRYP crypto */ .word HASH_RNG_IRQHandler /* Hash and Rng */ .word FPU_IRQHandler /* FPU */ /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak CAN1_TX_IRQHandler .thumb_set CAN1_TX_IRQHandler,Default_Handler .weak CAN1_RX0_IRQHandler .thumb_set CAN1_RX0_IRQHandler,Default_Handler .weak CAN1_RX1_IRQHandler .thumb_set CAN1_RX1_IRQHandler,Default_Handler .weak CAN1_SCE_IRQHandler .thumb_set CAN1_SCE_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM9_IRQHandler .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler .weak TIM1_UP_TIM10_IRQHandler .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM11_IRQHandler .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak TIM8_BRK_TIM12_IRQHandler .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler .weak TIM8_UP_TIM13_IRQHandler .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler .weak TIM8_TRG_COM_TIM14_IRQHandler .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak FSMC_IRQHandler .thumb_set FSMC_IRQHandler,Default_Handler .weak SDIO_IRQHandler .thumb_set SDIO_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak ETH_IRQHandler .thumb_set ETH_IRQHandler,Default_Handler .weak ETH_WKUP_IRQHandler .thumb_set ETH_WKUP_IRQHandler,Default_Handler .weak CAN2_TX_IRQHandler .thumb_set CAN2_TX_IRQHandler,Default_Handler .weak CAN2_RX0_IRQHandler .thumb_set CAN2_RX0_IRQHandler,Default_Handler .weak CAN2_RX1_IRQHandler .thumb_set CAN2_RX1_IRQHandler,Default_Handler .weak CAN2_SCE_IRQHandler .thumb_set CAN2_SCE_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak OTG_HS_EP1_OUT_IRQHandler .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_HS_EP1_IN_IRQHandler .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler .weak OTG_HS_WKUP_IRQHandler .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler .weak OTG_HS_IRQHandler .thumb_set OTG_HS_IRQHandler,Default_Handler .weak DCMI_IRQHandler .thumb_set DCMI_IRQHandler,Default_Handler .weak CRYP_IRQHandler .thumb_set CRYP_IRQHandler,Default_Handler .weak HASH_RNG_IRQHandler .thumb_set HASH_RNG_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_stm32f40xx.s ================================================ /** ****************************************************************************** * @file startup_stm32f40xx.s * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief STM32F40xxx/41xxx Devices vector table for RIDE7 toolchain. * Same as startup_stm32f40xx.s and maintained for legacy purpose * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Configure the clock system and the external SRAM mounted on * STM324xG-EVAL board to be used as data memory (optional, * to be enabled by user) * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ .syntax unified .cpu cortex-m3 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call the application's entry point.*/ bl main bx lr .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_IRQHandler /* PVD through EXTI Line detection */ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ .word FLASH_IRQHandler /* FLASH */ .word RCC_IRQHandler /* RCC */ .word EXTI0_IRQHandler /* EXTI Line0 */ .word EXTI1_IRQHandler /* EXTI Line1 */ .word EXTI2_IRQHandler /* EXTI Line2 */ .word EXTI3_IRQHandler /* EXTI Line3 */ .word EXTI4_IRQHandler /* EXTI Line4 */ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ .word CAN1_TX_IRQHandler /* CAN1 TX */ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ .word CAN1_SCE_IRQHandler /* CAN1 SCE */ .word EXTI9_5_IRQHandler /* External Line[9:5]s */ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ .word TIM2_IRQHandler /* TIM2 */ .word TIM3_IRQHandler /* TIM3 */ .word TIM4_IRQHandler /* TIM4 */ .word I2C1_EV_IRQHandler /* I2C1 Event */ .word I2C1_ER_IRQHandler /* I2C1 Error */ .word I2C2_EV_IRQHandler /* I2C2 Event */ .word I2C2_ER_IRQHandler /* I2C2 Error */ .word SPI1_IRQHandler /* SPI1 */ .word SPI2_IRQHandler /* SPI2 */ .word USART1_IRQHandler /* USART1 */ .word USART2_IRQHandler /* USART2 */ .word USART3_IRQHandler /* USART3 */ .word EXTI15_10_IRQHandler /* External Line[15:10]s */ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ .word FSMC_IRQHandler /* FSMC */ .word SDIO_IRQHandler /* SDIO */ .word TIM5_IRQHandler /* TIM5 */ .word SPI3_IRQHandler /* SPI3 */ .word UART4_IRQHandler /* UART4 */ .word UART5_IRQHandler /* UART5 */ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ .word TIM7_IRQHandler /* TIM7 */ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ .word ETH_IRQHandler /* Ethernet */ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ .word CAN2_TX_IRQHandler /* CAN2 TX */ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ .word CAN2_SCE_IRQHandler /* CAN2 SCE */ .word OTG_FS_IRQHandler /* USB OTG FS */ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ .word USART6_IRQHandler /* USART6 */ .word I2C3_EV_IRQHandler /* I2C3 event */ .word I2C3_ER_IRQHandler /* I2C3 error */ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ .word OTG_HS_IRQHandler /* USB OTG HS */ .word DCMI_IRQHandler /* DCMI */ .word CRYP_IRQHandler /* CRYP crypto */ .word HASH_RNG_IRQHandler /* Hash and Rng */ .word FPU_IRQHandler /* FPU */ /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak CAN1_TX_IRQHandler .thumb_set CAN1_TX_IRQHandler,Default_Handler .weak CAN1_RX0_IRQHandler .thumb_set CAN1_RX0_IRQHandler,Default_Handler .weak CAN1_RX1_IRQHandler .thumb_set CAN1_RX1_IRQHandler,Default_Handler .weak CAN1_SCE_IRQHandler .thumb_set CAN1_SCE_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM9_IRQHandler .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler .weak TIM1_UP_TIM10_IRQHandler .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM11_IRQHandler .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak TIM8_BRK_TIM12_IRQHandler .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler .weak TIM8_UP_TIM13_IRQHandler .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler .weak TIM8_TRG_COM_TIM14_IRQHandler .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak FSMC_IRQHandler .thumb_set FSMC_IRQHandler,Default_Handler .weak SDIO_IRQHandler .thumb_set SDIO_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak ETH_IRQHandler .thumb_set ETH_IRQHandler,Default_Handler .weak ETH_WKUP_IRQHandler .thumb_set ETH_WKUP_IRQHandler,Default_Handler .weak CAN2_TX_IRQHandler .thumb_set CAN2_TX_IRQHandler,Default_Handler .weak CAN2_RX0_IRQHandler .thumb_set CAN2_RX0_IRQHandler,Default_Handler .weak CAN2_RX1_IRQHandler .thumb_set CAN2_RX1_IRQHandler,Default_Handler .weak CAN2_SCE_IRQHandler .thumb_set CAN2_SCE_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak OTG_HS_EP1_OUT_IRQHandler .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_HS_EP1_IN_IRQHandler .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler .weak OTG_HS_WKUP_IRQHandler .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler .weak OTG_HS_IRQHandler .thumb_set OTG_HS_IRQHandler,Default_Handler .weak DCMI_IRQHandler .thumb_set DCMI_IRQHandler,Default_Handler .weak CRYP_IRQHandler .thumb_set CRYP_IRQHandler,Default_Handler .weak HASH_RNG_IRQHandler .thumb_set HASH_RNG_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_stm32f427_437xx.s ================================================ /** ****************************************************************************** * @file startup_stm32f427_437xx.s * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief STM32F427xx/437xx Devices vector table for RIDE7 toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Configure the clock system and the external SRAM mounted on * STM324x7I-EVAL board to be used as data memory (optional, * to be enabled by user) * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ .syntax unified .cpu cortex-m3 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call the application's entry point.*/ bl main bx lr .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_IRQHandler /* PVD through EXTI Line detection */ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ .word FLASH_IRQHandler /* FLASH */ .word RCC_IRQHandler /* RCC */ .word EXTI0_IRQHandler /* EXTI Line0 */ .word EXTI1_IRQHandler /* EXTI Line1 */ .word EXTI2_IRQHandler /* EXTI Line2 */ .word EXTI3_IRQHandler /* EXTI Line3 */ .word EXTI4_IRQHandler /* EXTI Line4 */ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ .word CAN1_TX_IRQHandler /* CAN1 TX */ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ .word CAN1_SCE_IRQHandler /* CAN1 SCE */ .word EXTI9_5_IRQHandler /* External Line[9:5]s */ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ .word TIM2_IRQHandler /* TIM2 */ .word TIM3_IRQHandler /* TIM3 */ .word TIM4_IRQHandler /* TIM4 */ .word I2C1_EV_IRQHandler /* I2C1 Event */ .word I2C1_ER_IRQHandler /* I2C1 Error */ .word I2C2_EV_IRQHandler /* I2C2 Event */ .word I2C2_ER_IRQHandler /* I2C2 Error */ .word SPI1_IRQHandler /* SPI1 */ .word SPI2_IRQHandler /* SPI2 */ .word USART1_IRQHandler /* USART1 */ .word USART2_IRQHandler /* USART2 */ .word USART3_IRQHandler /* USART3 */ .word EXTI15_10_IRQHandler /* External Line[15:10]s */ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ .word FSMC_IRQHandler /* FSMC */ .word SDIO_IRQHandler /* SDIO */ .word TIM5_IRQHandler /* TIM5 */ .word SPI3_IRQHandler /* SPI3 */ .word UART4_IRQHandler /* UART4 */ .word UART5_IRQHandler /* UART5 */ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ .word TIM7_IRQHandler /* TIM7 */ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ .word ETH_IRQHandler /* Ethernet */ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ .word CAN2_TX_IRQHandler /* CAN2 TX */ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ .word CAN2_SCE_IRQHandler /* CAN2 SCE */ .word OTG_FS_IRQHandler /* USB OTG FS */ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ .word USART6_IRQHandler /* USART6 */ .word I2C3_EV_IRQHandler /* I2C3 event */ .word I2C3_ER_IRQHandler /* I2C3 error */ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ .word OTG_HS_IRQHandler /* USB OTG HS */ .word DCMI_IRQHandler /* DCMI */ .word CRYP_IRQHandler /* CRYP crypto */ .word HASH_RNG_IRQHandler /* Hash and Rng */ .word FPU_IRQHandler /* FPU */ .word UART7_IRQHandler /* UART7 */ .word UART8_IRQHandler /* UART8 */ .word SPI4_IRQHandler /* SPI4 */ .word SPI5_IRQHandler /* SPI5 */ .word SPI6_IRQHandler /* SPI6 */ .word SAI1_IRQHandler /* SAI1 */ .word LTDC_IRQHandler /* LTDC */ .word LTDC_ER_IRQHandler /* LTDC error */ .word DMA2D_IRQHandler /* DMA2D */ /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak CAN1_TX_IRQHandler .thumb_set CAN1_TX_IRQHandler,Default_Handler .weak CAN1_RX0_IRQHandler .thumb_set CAN1_RX0_IRQHandler,Default_Handler .weak CAN1_RX1_IRQHandler .thumb_set CAN1_RX1_IRQHandler,Default_Handler .weak CAN1_SCE_IRQHandler .thumb_set CAN1_SCE_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM9_IRQHandler .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler .weak TIM1_UP_TIM10_IRQHandler .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM11_IRQHandler .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak TIM8_BRK_TIM12_IRQHandler .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler .weak TIM8_UP_TIM13_IRQHandler .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler .weak TIM8_TRG_COM_TIM14_IRQHandler .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak FSMC_IRQHandler .thumb_set FSMC_IRQHandler,Default_Handler .weak SDIO_IRQHandler .thumb_set SDIO_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak ETH_IRQHandler .thumb_set ETH_IRQHandler,Default_Handler .weak ETH_WKUP_IRQHandler .thumb_set ETH_WKUP_IRQHandler,Default_Handler .weak CAN2_TX_IRQHandler .thumb_set CAN2_TX_IRQHandler,Default_Handler .weak CAN2_RX0_IRQHandler .thumb_set CAN2_RX0_IRQHandler,Default_Handler .weak CAN2_RX1_IRQHandler .thumb_set CAN2_RX1_IRQHandler,Default_Handler .weak CAN2_SCE_IRQHandler .thumb_set CAN2_SCE_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak OTG_HS_EP1_OUT_IRQHandler .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_HS_EP1_IN_IRQHandler .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler .weak OTG_HS_WKUP_IRQHandler .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler .weak OTG_HS_IRQHandler .thumb_set OTG_HS_IRQHandler,Default_Handler .weak DCMI_IRQHandler .thumb_set DCMI_IRQHandler,Default_Handler .weak CRYP_IRQHandler .thumb_set CRYP_IRQHandler,Default_Handler .weak HASH_RNG_IRQHandler .thumb_set HASH_RNG_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler .weak UART7_IRQHandler .thumb_set UART7_IRQHandler,Default_Handler .weak UART8_IRQHandler .thumb_set UART8_IRQHandler,Default_Handler .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler .weak SPI5_IRQHandler .thumb_set SPI5_IRQHandler,Default_Handler .weak SPI6_IRQHandler .thumb_set SPI6_IRQHandler,Default_Handler .weak SAI1_IRQHandler .thumb_set SAI1_IRQHandler,Default_Handler .weak LTDC_IRQHandler .thumb_set LTDC_IRQHandler,Default_Handler .weak LTDC_ER_IRQHandler .thumb_set LTDC_ER_IRQHandler,Default_Handler .weak DMA2D_IRQHandler .thumb_set DMA2D_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_stm32f427x.s ================================================ /** ****************************************************************************** * @file startup_stm32f427x.s * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief STM32F427xx/437xx Devices vector table for RIDE7 toolchain. * Same as startup_stm32f427_437xx.s and maintained for legacy purpose * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Configure the clock system and the external SRAM mounted on * STM324x7I-EVAL board to be used as data memory * (optional, to be enabled by user) * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ .syntax unified .cpu cortex-m3 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call the application's entry point.*/ bl main bx lr .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_IRQHandler /* PVD through EXTI Line detection */ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ .word FLASH_IRQHandler /* FLASH */ .word RCC_IRQHandler /* RCC */ .word EXTI0_IRQHandler /* EXTI Line0 */ .word EXTI1_IRQHandler /* EXTI Line1 */ .word EXTI2_IRQHandler /* EXTI Line2 */ .word EXTI3_IRQHandler /* EXTI Line3 */ .word EXTI4_IRQHandler /* EXTI Line4 */ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ .word CAN1_TX_IRQHandler /* CAN1 TX */ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ .word CAN1_SCE_IRQHandler /* CAN1 SCE */ .word EXTI9_5_IRQHandler /* External Line[9:5]s */ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ .word TIM2_IRQHandler /* TIM2 */ .word TIM3_IRQHandler /* TIM3 */ .word TIM4_IRQHandler /* TIM4 */ .word I2C1_EV_IRQHandler /* I2C1 Event */ .word I2C1_ER_IRQHandler /* I2C1 Error */ .word I2C2_EV_IRQHandler /* I2C2 Event */ .word I2C2_ER_IRQHandler /* I2C2 Error */ .word SPI1_IRQHandler /* SPI1 */ .word SPI2_IRQHandler /* SPI2 */ .word USART1_IRQHandler /* USART1 */ .word USART2_IRQHandler /* USART2 */ .word USART3_IRQHandler /* USART3 */ .word EXTI15_10_IRQHandler /* External Line[15:10]s */ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ .word FSMC_IRQHandler /* FSMC */ .word SDIO_IRQHandler /* SDIO */ .word TIM5_IRQHandler /* TIM5 */ .word SPI3_IRQHandler /* SPI3 */ .word UART4_IRQHandler /* UART4 */ .word UART5_IRQHandler /* UART5 */ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ .word TIM7_IRQHandler /* TIM7 */ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ .word ETH_IRQHandler /* Ethernet */ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ .word CAN2_TX_IRQHandler /* CAN2 TX */ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ .word CAN2_SCE_IRQHandler /* CAN2 SCE */ .word OTG_FS_IRQHandler /* USB OTG FS */ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ .word USART6_IRQHandler /* USART6 */ .word I2C3_EV_IRQHandler /* I2C3 event */ .word I2C3_ER_IRQHandler /* I2C3 error */ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ .word OTG_HS_IRQHandler /* USB OTG HS */ .word DCMI_IRQHandler /* DCMI */ .word CRYP_IRQHandler /* CRYP crypto */ .word HASH_RNG_IRQHandler /* Hash and Rng */ .word FPU_IRQHandler /* FPU */ .word UART7_IRQHandler /* UART7 */ .word UART8_IRQHandler /* UART8 */ .word SPI4_IRQHandler /* SPI4 */ .word SPI5_IRQHandler /* SPI5 */ .word SPI6_IRQHandler /* SPI6 */ .word SAI1_IRQHandler /* SAI1 */ .word LTDC_IRQHandler /* LTDC */ .word LTDC_ER_IRQHandler /* LTDC error */ .word DMA2D_IRQHandler /* DMA2D */ /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak CAN1_TX_IRQHandler .thumb_set CAN1_TX_IRQHandler,Default_Handler .weak CAN1_RX0_IRQHandler .thumb_set CAN1_RX0_IRQHandler,Default_Handler .weak CAN1_RX1_IRQHandler .thumb_set CAN1_RX1_IRQHandler,Default_Handler .weak CAN1_SCE_IRQHandler .thumb_set CAN1_SCE_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM9_IRQHandler .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler .weak TIM1_UP_TIM10_IRQHandler .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM11_IRQHandler .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak TIM8_BRK_TIM12_IRQHandler .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler .weak TIM8_UP_TIM13_IRQHandler .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler .weak TIM8_TRG_COM_TIM14_IRQHandler .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak FSMC_IRQHandler .thumb_set FSMC_IRQHandler,Default_Handler .weak SDIO_IRQHandler .thumb_set SDIO_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak ETH_IRQHandler .thumb_set ETH_IRQHandler,Default_Handler .weak ETH_WKUP_IRQHandler .thumb_set ETH_WKUP_IRQHandler,Default_Handler .weak CAN2_TX_IRQHandler .thumb_set CAN2_TX_IRQHandler,Default_Handler .weak CAN2_RX0_IRQHandler .thumb_set CAN2_RX0_IRQHandler,Default_Handler .weak CAN2_RX1_IRQHandler .thumb_set CAN2_RX1_IRQHandler,Default_Handler .weak CAN2_SCE_IRQHandler .thumb_set CAN2_SCE_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak OTG_HS_EP1_OUT_IRQHandler .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_HS_EP1_IN_IRQHandler .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler .weak OTG_HS_WKUP_IRQHandler .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler .weak OTG_HS_IRQHandler .thumb_set OTG_HS_IRQHandler,Default_Handler .weak DCMI_IRQHandler .thumb_set DCMI_IRQHandler,Default_Handler .weak CRYP_IRQHandler .thumb_set CRYP_IRQHandler,Default_Handler .weak HASH_RNG_IRQHandler .thumb_set HASH_RNG_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler .weak UART7_IRQHandler .thumb_set UART7_IRQHandler,Default_Handler .weak UART8_IRQHandler .thumb_set UART8_IRQHandler,Default_Handler .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler .weak SPI5_IRQHandler .thumb_set SPI5_IRQHandler,Default_Handler .weak SPI6_IRQHandler .thumb_set SPI6_IRQHandler,Default_Handler .weak SAI1_IRQHandler .thumb_set SAI1_IRQHandler,Default_Handler .weak LTDC_IRQHandler .thumb_set LTDC_IRQHandler,Default_Handler .weak LTDC_ER_IRQHandler .thumb_set LTDC_ER_IRQHandler,Default_Handler .weak DMA2D_IRQHandler .thumb_set DMA2D_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_stm32f429_439xx.s ================================================ /** ****************************************************************************** * @file startup_stm32f429_439xx.s * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief STM32F429xx/439xx Devices vector table for RIDE7 toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Configure the clock system and the external SRAM mounted on * STM324x9I-EVAL board to be used as data memory (optional, * to be enabled by user) * - Branches to main in the C library (which eventually * calls main()). * After Reset the Cortex-M4 processor is in Thread mode, * priority is Privileged, and the Stack is set to Main. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ .syntax unified .cpu cortex-m3 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss b LoopFillZerobss /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit /* Call the application's entry point.*/ bl main bx lr .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * @param None * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_IRQHandler /* PVD through EXTI Line detection */ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ .word FLASH_IRQHandler /* FLASH */ .word RCC_IRQHandler /* RCC */ .word EXTI0_IRQHandler /* EXTI Line0 */ .word EXTI1_IRQHandler /* EXTI Line1 */ .word EXTI2_IRQHandler /* EXTI Line2 */ .word EXTI3_IRQHandler /* EXTI Line3 */ .word EXTI4_IRQHandler /* EXTI Line4 */ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ .word CAN1_TX_IRQHandler /* CAN1 TX */ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ .word CAN1_SCE_IRQHandler /* CAN1 SCE */ .word EXTI9_5_IRQHandler /* External Line[9:5]s */ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ .word TIM2_IRQHandler /* TIM2 */ .word TIM3_IRQHandler /* TIM3 */ .word TIM4_IRQHandler /* TIM4 */ .word I2C1_EV_IRQHandler /* I2C1 Event */ .word I2C1_ER_IRQHandler /* I2C1 Error */ .word I2C2_EV_IRQHandler /* I2C2 Event */ .word I2C2_ER_IRQHandler /* I2C2 Error */ .word SPI1_IRQHandler /* SPI1 */ .word SPI2_IRQHandler /* SPI2 */ .word USART1_IRQHandler /* USART1 */ .word USART2_IRQHandler /* USART2 */ .word USART3_IRQHandler /* USART3 */ .word EXTI15_10_IRQHandler /* External Line[15:10]s */ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ .word FSMC_IRQHandler /* FSMC */ .word SDIO_IRQHandler /* SDIO */ .word TIM5_IRQHandler /* TIM5 */ .word SPI3_IRQHandler /* SPI3 */ .word UART4_IRQHandler /* UART4 */ .word UART5_IRQHandler /* UART5 */ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ .word TIM7_IRQHandler /* TIM7 */ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ .word ETH_IRQHandler /* Ethernet */ .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ .word CAN2_TX_IRQHandler /* CAN2 TX */ .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ .word CAN2_SCE_IRQHandler /* CAN2 SCE */ .word OTG_FS_IRQHandler /* USB OTG FS */ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ .word USART6_IRQHandler /* USART6 */ .word I2C3_EV_IRQHandler /* I2C3 event */ .word I2C3_ER_IRQHandler /* I2C3 error */ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ .word OTG_HS_IRQHandler /* USB OTG HS */ .word DCMI_IRQHandler /* DCMI */ .word CRYP_IRQHandler /* CRYP crypto */ .word HASH_RNG_IRQHandler /* Hash and Rng */ .word FPU_IRQHandler /* FPU */ .word UART7_IRQHandler /* UART7 */ .word UART8_IRQHandler /* UART8 */ .word SPI4_IRQHandler /* SPI4 */ .word SPI5_IRQHandler /* SPI5 */ .word SPI6_IRQHandler /* SPI6 */ .word SAI1_IRQHandler /* SAI1 */ .word LTDC_IRQHandler /* LTDC */ .word LTDC_ER_IRQHandler /* LTDC error */ .word DMA2D_IRQHandler /* DMA2D */ /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG_IRQHandler .thumb_set WWDG_IRQHandler,Default_Handler .weak PVD_IRQHandler .thumb_set PVD_IRQHandler,Default_Handler .weak TAMP_STAMP_IRQHandler .thumb_set TAMP_STAMP_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA1_Stream0_IRQHandler .thumb_set DMA1_Stream0_IRQHandler,Default_Handler .weak DMA1_Stream1_IRQHandler .thumb_set DMA1_Stream1_IRQHandler,Default_Handler .weak DMA1_Stream2_IRQHandler .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler .weak DMA1_Stream5_IRQHandler .thumb_set DMA1_Stream5_IRQHandler,Default_Handler .weak DMA1_Stream6_IRQHandler .thumb_set DMA1_Stream6_IRQHandler,Default_Handler .weak ADC_IRQHandler .thumb_set ADC_IRQHandler,Default_Handler .weak CAN1_TX_IRQHandler .thumb_set CAN1_TX_IRQHandler,Default_Handler .weak CAN1_RX0_IRQHandler .thumb_set CAN1_RX0_IRQHandler,Default_Handler .weak CAN1_RX1_IRQHandler .thumb_set CAN1_RX1_IRQHandler,Default_Handler .weak CAN1_SCE_IRQHandler .thumb_set CAN1_SCE_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_TIM9_IRQHandler .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler .weak TIM1_UP_TIM10_IRQHandler .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler .weak TIM1_TRG_COM_TIM11_IRQHandler .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler .weak TIM1_CC_IRQHandler .thumb_set TIM1_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_Alarm_IRQHandler .thumb_set RTC_Alarm_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak TIM8_BRK_TIM12_IRQHandler .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler .weak TIM8_UP_TIM13_IRQHandler .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler .weak TIM8_TRG_COM_TIM14_IRQHandler .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler .weak FSMC_IRQHandler .thumb_set FSMC_IRQHandler,Default_Handler .weak SDIO_IRQHandler .thumb_set SDIO_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler .weak DMA2_Stream0_IRQHandler .thumb_set DMA2_Stream0_IRQHandler,Default_Handler .weak DMA2_Stream1_IRQHandler .thumb_set DMA2_Stream1_IRQHandler,Default_Handler .weak DMA2_Stream2_IRQHandler .thumb_set DMA2_Stream2_IRQHandler,Default_Handler .weak DMA2_Stream3_IRQHandler .thumb_set DMA2_Stream3_IRQHandler,Default_Handler .weak DMA2_Stream4_IRQHandler .thumb_set DMA2_Stream4_IRQHandler,Default_Handler .weak ETH_IRQHandler .thumb_set ETH_IRQHandler,Default_Handler .weak ETH_WKUP_IRQHandler .thumb_set ETH_WKUP_IRQHandler,Default_Handler .weak CAN2_TX_IRQHandler .thumb_set CAN2_TX_IRQHandler,Default_Handler .weak CAN2_RX0_IRQHandler .thumb_set CAN2_RX0_IRQHandler,Default_Handler .weak CAN2_RX1_IRQHandler .thumb_set CAN2_RX1_IRQHandler,Default_Handler .weak CAN2_SCE_IRQHandler .thumb_set CAN2_SCE_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMA2_Stream5_IRQHandler .thumb_set DMA2_Stream5_IRQHandler,Default_Handler .weak DMA2_Stream6_IRQHandler .thumb_set DMA2_Stream6_IRQHandler,Default_Handler .weak DMA2_Stream7_IRQHandler .thumb_set DMA2_Stream7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak OTG_HS_EP1_OUT_IRQHandler .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_HS_EP1_IN_IRQHandler .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler .weak OTG_HS_WKUP_IRQHandler .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler .weak OTG_HS_IRQHandler .thumb_set OTG_HS_IRQHandler,Default_Handler .weak DCMI_IRQHandler .thumb_set DCMI_IRQHandler,Default_Handler .weak CRYP_IRQHandler .thumb_set CRYP_IRQHandler,Default_Handler .weak HASH_RNG_IRQHandler .thumb_set HASH_RNG_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler .weak UART7_IRQHandler .thumb_set UART7_IRQHandler,Default_Handler .weak UART8_IRQHandler .thumb_set UART8_IRQHandler,Default_Handler .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler .weak SPI5_IRQHandler .thumb_set SPI5_IRQHandler,Default_Handler .weak SPI6_IRQHandler .thumb_set SPI6_IRQHandler,Default_Handler .weak SAI1_IRQHandler .thumb_set SAI1_IRQHandler,Default_Handler .weak LTDC_IRQHandler .thumb_set LTDC_IRQHandler,Default_Handler .weak LTDC_ER_IRQHandler .thumb_set LTDC_ER_IRQHandler,Default_Handler .weak DMA2D_IRQHandler .thumb_set DMA2D_IRQHandler,Default_Handler /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f401xx.s ================================================ ;/******************** (C) COPYRIGHT 2013 STMicroelectronics ******************** ;* File Name : startup_stm32f401x.s ;* Author : MCD Application Team ;* Version : V1.3.0 ;* Date : 08-November-2013 ;* Description : STM32F401xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, ;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Configure the system clock ;* - Branches to main in the C library (which eventually ;* calls main()). ;* After Reset the Cortex-M4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* ;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); ;* You may not use this file except in compliance with the License. ;* You may obtain a copy of the License at: ;* ;* http://www.st.com/software_license_agreement_liberty_v2 ;* ;* Unless required by applicable law or agreed to in writing, software ;* distributed under the License is distributed on an "AS IS" BASIS, ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* See the License for the specific language governing permissions and ;* limitations under the License. ;* ;*******************************************************************************/ ; ; ; The modules in this file are included in the libraries, and may be replaced ; by any user-defined modules that define the PUBLIC symbol _program_start or ; a user defined start symbol. ; To override the cstartup defined in the library, simply add your modified ; version to the workbench project. ; ; The vector table is normally located at address 0. ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. ; The name "__vector_table" has special meaning for C-SPY: ; it is where the SP start value is found, and the NVIC vector ; table register (VTOR) is initialized to this address if != 0. ; ; Cortex-M version ; MODULE ?cstartup ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) EXTERN __iar_program_start EXTERN SystemInit PUBLIC __vector_table DATA __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog DCD PVD_IRQHandler ; PVD through EXTI Line detection DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line DCD FLASH_IRQHandler ; FLASH DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line0 DCD EXTI1_IRQHandler ; EXTI Line1 DCD EXTI2_IRQHandler ; EXTI Line2 DCD EXTI3_IRQHandler ; EXTI Line3 DCD EXTI4_IRQHandler ; EXTI Line4 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 DCD ADC_IRQHandler ; ADC1 DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD 0 ; Reserved DCD EXTI15_10_IRQHandler ; External Line[15:10]s DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 DCD 0 ; Reserved DCD SDIO_IRQHandler ; SDIO DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD OTG_FS_IRQHandler ; USB OTG FS DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 DCD USART6_IRQHandler ; USART6 DCD I2C3_EV_IRQHandler ; I2C3 event DCD I2C3_ER_IRQHandler ; I2C3 error DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD FPU_IRQHandler ; FPU DCD 0 ; Reserved DCD 0 ; Reserved DCD SPI4_IRQHandler ; SPI4 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. ;; THUMB PUBWEAK Reset_Handler SECTION .text:CODE:REORDER(2) Reset_Handler LDR R0, =SystemInit BLX R0 LDR R0, =__iar_program_start BX R0 PUBWEAK NMI_Handler SECTION .text:CODE:REORDER(1) NMI_Handler B NMI_Handler PUBWEAK HardFault_Handler SECTION .text:CODE:REORDER(1) HardFault_Handler B HardFault_Handler PUBWEAK MemManage_Handler SECTION .text:CODE:REORDER(1) MemManage_Handler B MemManage_Handler PUBWEAK BusFault_Handler SECTION .text:CODE:REORDER(1) BusFault_Handler B BusFault_Handler PUBWEAK UsageFault_Handler SECTION .text:CODE:REORDER(1) UsageFault_Handler B UsageFault_Handler PUBWEAK SVC_Handler SECTION .text:CODE:REORDER(1) SVC_Handler B SVC_Handler PUBWEAK DebugMon_Handler SECTION .text:CODE:REORDER(1) DebugMon_Handler B DebugMon_Handler PUBWEAK PendSV_Handler SECTION .text:CODE:REORDER(1) PendSV_Handler B PendSV_Handler PUBWEAK SysTick_Handler SECTION .text:CODE:REORDER(1) SysTick_Handler B SysTick_Handler PUBWEAK WWDG_IRQHandler SECTION .text:CODE:REORDER(1) WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_IRQHandler SECTION .text:CODE:REORDER(1) PVD_IRQHandler B PVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler SECTION .text:CODE:REORDER(1) TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:REORDER(1) FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:REORDER(1) RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:REORDER(1) EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:REORDER(1) EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:REORDER(1) EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler SECTION .text:CODE:REORDER(1) EXTI3_IRQHandler B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler SECTION .text:CODE:REORDER(1) EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:REORDER(1) ADC_IRQHandler B ADC_IRQHandler PUBWEAK EXTI9_5_IRQHandler SECTION .text:CODE:REORDER(1) EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_TIM9_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_BRK_TIM9_IRQHandler B TIM1_BRK_TIM9_IRQHandler PUBWEAK TIM1_UP_TIM10_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_UP_TIM10_IRQHandler B TIM1_UP_TIM10_IRQHandler PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_TRG_COM_TIM11_IRQHandler B TIM1_TRG_COM_TIM11_IRQHandler PUBWEAK TIM1_CC_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:REORDER(1) TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:REORDER(1) TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:REORDER(1) TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler SECTION .text:CODE:REORDER(1) I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler SECTION .text:CODE:REORDER(1) I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler SECTION .text:CODE:REORDER(1) I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler SECTION .text:CODE:REORDER(1) I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:REORDER(1) SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:REORDER(1) SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:REORDER(1) USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:REORDER(1) USART2_IRQHandler B USART2_IRQHandler PUBWEAK EXTI15_10_IRQHandler SECTION .text:CODE:REORDER(1) EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler SECTION .text:CODE:REORDER(1) RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK SDIO_IRQHandler SECTION .text:CODE:REORDER(1) SDIO_IRQHandler B SDIO_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:REORDER(1) TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:REORDER(1) SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK OTG_FS_IRQHandler SECTION .text:CODE:REORDER(1) OTG_FS_IRQHandler B OTG_FS_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:REORDER(1) USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler SECTION .text:CODE:REORDER(1) I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler SECTION .text:CODE:REORDER(1) I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK FPU_IRQHandler SECTION .text:CODE:REORDER(1) FPU_IRQHandler B FPU_IRQHandler PUBWEAK SPI4_IRQHandler SECTION .text:CODE:REORDER(1) SPI4_IRQHandler B SPI4_IRQHandler END /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f40_41xxx.s ================================================ ;/******************** (C) COPYRIGHT 2013 STMicroelectronics ******************** ;* File Name : startup_stm32f40_41xxx.s ;* Author : MCD Application Team ;* Version : V1.3.0 ;* Date : 08-November-2013 ;* Description : STM32F40xxx/41xxx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, ;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Configure the system clock and the external SRAM mounted on ;* STM324xG-EVAL board to be used as data memory (optional, ;* to be enabled by user) ;* - Branches to main in the C library (which eventually ;* calls main()). ;* After Reset the Cortex-M4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* ;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); ;* You may not use this file except in compliance with the License. ;* You may obtain a copy of the License at: ;* ;* http://www.st.com/software_license_agreement_liberty_v2 ;* ;* Unless required by applicable law or agreed to in writing, software ;* distributed under the License is distributed on an "AS IS" BASIS, ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* See the License for the specific language governing permissions and ;* limitations under the License. ;* ;*******************************************************************************/ ; ; ; The modules in this file are included in the libraries, and may be replaced ; by any user-defined modules that define the PUBLIC symbol _program_start or ; a user defined start symbol. ; To override the cstartup defined in the library, simply add your modified ; version to the workbench project. ; ; The vector table is normally located at address 0. ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. ; The name "__vector_table" has special meaning for C-SPY: ; it is where the SP start value is found, and the NVIC vector ; table register (VTOR) is initialized to this address if != 0. ; ; Cortex-M version ; MODULE ?cstartup ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) EXTERN __iar_program_start EXTERN SystemInit PUBLIC __vector_table DATA __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog DCD PVD_IRQHandler ; PVD through EXTI Line detection DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line DCD FLASH_IRQHandler ; FLASH DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line0 DCD EXTI1_IRQHandler ; EXTI Line1 DCD EXTI2_IRQHandler ; EXTI Line2 DCD EXTI3_IRQHandler ; EXTI Line3 DCD EXTI4_IRQHandler ; EXTI Line4 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s DCD CAN1_TX_IRQHandler ; CAN1 TX DCD CAN1_RX0_IRQHandler ; CAN1 RX0 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 DCD CAN1_SCE_IRQHandler ; CAN1 SCE DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; External Line[15:10]s DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 DCD FSMC_IRQHandler ; FSMC DCD SDIO_IRQHandler ; SDIO DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 DCD UART4_IRQHandler ; UART4 DCD UART5_IRQHandler ; UART5 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 DCD ETH_IRQHandler ; Ethernet DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line DCD CAN2_TX_IRQHandler ; CAN2 TX DCD CAN2_RX0_IRQHandler ; CAN2 RX0 DCD CAN2_RX1_IRQHandler ; CAN2 RX1 DCD CAN2_SCE_IRQHandler ; CAN2 SCE DCD OTG_FS_IRQHandler ; USB OTG FS DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 DCD USART6_IRQHandler ; USART6 DCD I2C3_EV_IRQHandler ; I2C3 event DCD I2C3_ER_IRQHandler ; I2C3 error DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_IRQHandler ; DCMI DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. ;; THUMB PUBWEAK Reset_Handler SECTION .text:CODE:REORDER(2) Reset_Handler LDR R0, =SystemInit BLX R0 LDR R0, =__iar_program_start BX R0 PUBWEAK NMI_Handler SECTION .text:CODE:REORDER(1) NMI_Handler B NMI_Handler PUBWEAK HardFault_Handler SECTION .text:CODE:REORDER(1) HardFault_Handler B HardFault_Handler PUBWEAK MemManage_Handler SECTION .text:CODE:REORDER(1) MemManage_Handler B MemManage_Handler PUBWEAK BusFault_Handler SECTION .text:CODE:REORDER(1) BusFault_Handler B BusFault_Handler PUBWEAK UsageFault_Handler SECTION .text:CODE:REORDER(1) UsageFault_Handler B UsageFault_Handler PUBWEAK SVC_Handler SECTION .text:CODE:REORDER(1) SVC_Handler B SVC_Handler PUBWEAK DebugMon_Handler SECTION .text:CODE:REORDER(1) DebugMon_Handler B DebugMon_Handler PUBWEAK PendSV_Handler SECTION .text:CODE:REORDER(1) PendSV_Handler B PendSV_Handler PUBWEAK SysTick_Handler SECTION .text:CODE:REORDER(1) SysTick_Handler B SysTick_Handler PUBWEAK WWDG_IRQHandler SECTION .text:CODE:REORDER(1) WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_IRQHandler SECTION .text:CODE:REORDER(1) PVD_IRQHandler B PVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler SECTION .text:CODE:REORDER(1) TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:REORDER(1) FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:REORDER(1) RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:REORDER(1) EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:REORDER(1) EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:REORDER(1) EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler SECTION .text:CODE:REORDER(1) EXTI3_IRQHandler B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler SECTION .text:CODE:REORDER(1) EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:REORDER(1) ADC_IRQHandler B ADC_IRQHandler PUBWEAK CAN1_TX_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_TX_IRQHandler B CAN1_TX_IRQHandler PUBWEAK CAN1_RX0_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_RX0_IRQHandler B CAN1_RX0_IRQHandler PUBWEAK CAN1_RX1_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_RX1_IRQHandler B CAN1_RX1_IRQHandler PUBWEAK CAN1_SCE_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_SCE_IRQHandler B CAN1_SCE_IRQHandler PUBWEAK EXTI9_5_IRQHandler SECTION .text:CODE:REORDER(1) EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_TIM9_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_BRK_TIM9_IRQHandler B TIM1_BRK_TIM9_IRQHandler PUBWEAK TIM1_UP_TIM10_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_UP_TIM10_IRQHandler B TIM1_UP_TIM10_IRQHandler PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_TRG_COM_TIM11_IRQHandler B TIM1_TRG_COM_TIM11_IRQHandler PUBWEAK TIM1_CC_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:REORDER(1) TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:REORDER(1) TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:REORDER(1) TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler SECTION .text:CODE:REORDER(1) I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler SECTION .text:CODE:REORDER(1) I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler SECTION .text:CODE:REORDER(1) I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler SECTION .text:CODE:REORDER(1) I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:REORDER(1) SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:REORDER(1) SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:REORDER(1) USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:REORDER(1) USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:REORDER(1) USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler SECTION .text:CODE:REORDER(1) EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler SECTION .text:CODE:REORDER(1) RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler PUBWEAK TIM8_BRK_TIM12_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FSMC_IRQHandler SECTION .text:CODE:REORDER(1) FSMC_IRQHandler B FSMC_IRQHandler PUBWEAK SDIO_IRQHandler SECTION .text:CODE:REORDER(1) SDIO_IRQHandler B SDIO_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:REORDER(1) TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:REORDER(1) SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:REORDER(1) UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:REORDER(1) UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler SECTION .text:CODE:REORDER(1) TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler SECTION .text:CODE:REORDER(1) TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:REORDER(1) ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK CAN2_TX_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_TX_IRQHandler B CAN2_TX_IRQHandler PUBWEAK CAN2_RX0_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_RX0_IRQHandler B CAN2_RX0_IRQHandler PUBWEAK CAN2_RX1_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_RX1_IRQHandler B CAN2_RX1_IRQHandler PUBWEAK CAN2_SCE_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_SCE_IRQHandler B CAN2_SCE_IRQHandler PUBWEAK OTG_FS_IRQHandler SECTION .text:CODE:REORDER(1) OTG_FS_IRQHandler B OTG_FS_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:REORDER(1) USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler SECTION .text:CODE:REORDER(1) I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler SECTION .text:CODE:REORDER(1) I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_IRQHandler B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:REORDER(1) DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK CRYP_IRQHandler SECTION .text:CODE:REORDER(1) CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler SECTION .text:CODE:REORDER(1) HASH_RNG_IRQHandler B HASH_RNG_IRQHandler PUBWEAK FPU_IRQHandler SECTION .text:CODE:REORDER(1) FPU_IRQHandler B FPU_IRQHandler END /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f40xx.s ================================================ ;/******************** (C) COPYRIGHT 2013 STMicroelectronics ******************** ;* File Name : startup_stm32f40xx.s ;* Author : MCD Application Team ;* Version : V1.3.0 ;* Date : 08-November-2013 ;* Description : STM32F40xxx/41xxx devices vector table for EWARM toolchain. ;* Same as startup_stm32f40_41xxx.s and maintained for legacy purpose ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, ;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Configure the system clock and the external SRAM mounted on ;* STM324xG-EVAL board to be used as data memory (optional, ;* to be enabled by user) ;* - Branches to main in the C library (which eventually ;* calls main()). ;* After Reset the Cortex-M4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* ;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); ;* You may not use this file except in compliance with the License. ;* You may obtain a copy of the License at: ;* ;* http://www.st.com/software_license_agreement_liberty_v2 ;* ;* Unless required by applicable law or agreed to in writing, software ;* distributed under the License is distributed on an "AS IS" BASIS, ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* See the License for the specific language governing permissions and ;* limitations under the License. ;* ;*******************************************************************************/ ; ; ; The modules in this file are included in the libraries, and may be replaced ; by any user-defined modules that define the PUBLIC symbol _program_start or ; a user defined start symbol. ; To override the cstartup defined in the library, simply add your modified ; version to the workbench project. ; ; The vector table is normally located at address 0. ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. ; The name "__vector_table" has special meaning for C-SPY: ; it is where the SP start value is found, and the NVIC vector ; table register (VTOR) is initialized to this address if != 0. ; ; Cortex-M version ; MODULE ?cstartup ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) EXTERN __iar_program_start EXTERN SystemInit PUBLIC __vector_table DATA __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog DCD PVD_IRQHandler ; PVD through EXTI Line detection DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line DCD FLASH_IRQHandler ; FLASH DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line0 DCD EXTI1_IRQHandler ; EXTI Line1 DCD EXTI2_IRQHandler ; EXTI Line2 DCD EXTI3_IRQHandler ; EXTI Line3 DCD EXTI4_IRQHandler ; EXTI Line4 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s DCD CAN1_TX_IRQHandler ; CAN1 TX DCD CAN1_RX0_IRQHandler ; CAN1 RX0 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 DCD CAN1_SCE_IRQHandler ; CAN1 SCE DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; External Line[15:10]s DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 DCD FSMC_IRQHandler ; FSMC DCD SDIO_IRQHandler ; SDIO DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 DCD UART4_IRQHandler ; UART4 DCD UART5_IRQHandler ; UART5 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 DCD ETH_IRQHandler ; Ethernet DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line DCD CAN2_TX_IRQHandler ; CAN2 TX DCD CAN2_RX0_IRQHandler ; CAN2 RX0 DCD CAN2_RX1_IRQHandler ; CAN2 RX1 DCD CAN2_SCE_IRQHandler ; CAN2 SCE DCD OTG_FS_IRQHandler ; USB OTG FS DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 DCD USART6_IRQHandler ; USART6 DCD I2C3_EV_IRQHandler ; I2C3 event DCD I2C3_ER_IRQHandler ; I2C3 error DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_IRQHandler ; DCMI DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. ;; THUMB PUBWEAK Reset_Handler SECTION .text:CODE:REORDER(2) Reset_Handler LDR R0, =SystemInit BLX R0 LDR R0, =__iar_program_start BX R0 PUBWEAK NMI_Handler SECTION .text:CODE:REORDER(1) NMI_Handler B NMI_Handler PUBWEAK HardFault_Handler SECTION .text:CODE:REORDER(1) HardFault_Handler B HardFault_Handler PUBWEAK MemManage_Handler SECTION .text:CODE:REORDER(1) MemManage_Handler B MemManage_Handler PUBWEAK BusFault_Handler SECTION .text:CODE:REORDER(1) BusFault_Handler B BusFault_Handler PUBWEAK UsageFault_Handler SECTION .text:CODE:REORDER(1) UsageFault_Handler B UsageFault_Handler PUBWEAK SVC_Handler SECTION .text:CODE:REORDER(1) SVC_Handler B SVC_Handler PUBWEAK DebugMon_Handler SECTION .text:CODE:REORDER(1) DebugMon_Handler B DebugMon_Handler PUBWEAK PendSV_Handler SECTION .text:CODE:REORDER(1) PendSV_Handler B PendSV_Handler PUBWEAK SysTick_Handler SECTION .text:CODE:REORDER(1) SysTick_Handler B SysTick_Handler PUBWEAK WWDG_IRQHandler SECTION .text:CODE:REORDER(1) WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_IRQHandler SECTION .text:CODE:REORDER(1) PVD_IRQHandler B PVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler SECTION .text:CODE:REORDER(1) TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:REORDER(1) FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:REORDER(1) RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:REORDER(1) EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:REORDER(1) EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:REORDER(1) EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler SECTION .text:CODE:REORDER(1) EXTI3_IRQHandler B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler SECTION .text:CODE:REORDER(1) EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:REORDER(1) ADC_IRQHandler B ADC_IRQHandler PUBWEAK CAN1_TX_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_TX_IRQHandler B CAN1_TX_IRQHandler PUBWEAK CAN1_RX0_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_RX0_IRQHandler B CAN1_RX0_IRQHandler PUBWEAK CAN1_RX1_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_RX1_IRQHandler B CAN1_RX1_IRQHandler PUBWEAK CAN1_SCE_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_SCE_IRQHandler B CAN1_SCE_IRQHandler PUBWEAK EXTI9_5_IRQHandler SECTION .text:CODE:REORDER(1) EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_TIM9_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_BRK_TIM9_IRQHandler B TIM1_BRK_TIM9_IRQHandler PUBWEAK TIM1_UP_TIM10_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_UP_TIM10_IRQHandler B TIM1_UP_TIM10_IRQHandler PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_TRG_COM_TIM11_IRQHandler B TIM1_TRG_COM_TIM11_IRQHandler PUBWEAK TIM1_CC_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:REORDER(1) TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:REORDER(1) TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:REORDER(1) TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler SECTION .text:CODE:REORDER(1) I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler SECTION .text:CODE:REORDER(1) I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler SECTION .text:CODE:REORDER(1) I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler SECTION .text:CODE:REORDER(1) I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:REORDER(1) SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:REORDER(1) SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:REORDER(1) USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:REORDER(1) USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:REORDER(1) USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler SECTION .text:CODE:REORDER(1) EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler SECTION .text:CODE:REORDER(1) RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler PUBWEAK TIM8_BRK_TIM12_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FSMC_IRQHandler SECTION .text:CODE:REORDER(1) FSMC_IRQHandler B FSMC_IRQHandler PUBWEAK SDIO_IRQHandler SECTION .text:CODE:REORDER(1) SDIO_IRQHandler B SDIO_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:REORDER(1) TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:REORDER(1) SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:REORDER(1) UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:REORDER(1) UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler SECTION .text:CODE:REORDER(1) TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler SECTION .text:CODE:REORDER(1) TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:REORDER(1) ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK CAN2_TX_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_TX_IRQHandler B CAN2_TX_IRQHandler PUBWEAK CAN2_RX0_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_RX0_IRQHandler B CAN2_RX0_IRQHandler PUBWEAK CAN2_RX1_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_RX1_IRQHandler B CAN2_RX1_IRQHandler PUBWEAK CAN2_SCE_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_SCE_IRQHandler B CAN2_SCE_IRQHandler PUBWEAK OTG_FS_IRQHandler SECTION .text:CODE:REORDER(1) OTG_FS_IRQHandler B OTG_FS_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:REORDER(1) USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler SECTION .text:CODE:REORDER(1) I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler SECTION .text:CODE:REORDER(1) I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_IRQHandler B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:REORDER(1) DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK CRYP_IRQHandler SECTION .text:CODE:REORDER(1) CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler SECTION .text:CODE:REORDER(1) HASH_RNG_IRQHandler B HASH_RNG_IRQHandler PUBWEAK FPU_IRQHandler SECTION .text:CODE:REORDER(1) FPU_IRQHandler B FPU_IRQHandler END /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f427_437xx.s ================================================ ;/******************** (C) COPYRIGHT 2013 STMicroelectronics ******************** ;* File Name : startup_stm32f427_437xx.s ;* Author : MCD Application Team ;* Version : V1.3.0 ;* Date : 08-November-2013 ;* Description : STM32F427xx/437xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, ;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Configure the system clock and the external SRAM/SDRAM mounted ;* on STM324x7I-EVAL board to be used as data memory (optional, ;* to be enabled by user) ;* - Branches to main in the C library (which eventually ;* calls main()). ;* After Reset the Cortex-M4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* ;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); ;* You may not use this file except in compliance with the License. ;* You may obtain a copy of the License at: ;* ;* http://www.st.com/software_license_agreement_liberty_v2 ;* ;* Unless required by applicable law or agreed to in writing, software ;* distributed under the License is distributed on an "AS IS" BASIS, ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* See the License for the specific language governing permissions and ;* limitations under the License. ;* ;*******************************************************************************/ ; ; ; The modules in this file are included in the libraries, and may be replaced ; by any user-defined modules that define the PUBLIC symbol _program_start or ; a user defined start symbol. ; To override the cstartup defined in the library, simply add your modified ; version to the workbench project. ; ; The vector table is normally located at address 0. ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. ; The name "__vector_table" has special meaning for C-SPY: ; it is where the SP start value is found, and the NVIC vector ; table register (VTOR) is initialized to this address if != 0. ; ; Cortex-M version ; MODULE ?cstartup ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) EXTERN __iar_program_start EXTERN SystemInit PUBLIC __vector_table DATA __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog DCD PVD_IRQHandler ; PVD through EXTI Line detection DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line DCD FLASH_IRQHandler ; FLASH DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line0 DCD EXTI1_IRQHandler ; EXTI Line1 DCD EXTI2_IRQHandler ; EXTI Line2 DCD EXTI3_IRQHandler ; EXTI Line3 DCD EXTI4_IRQHandler ; EXTI Line4 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s DCD CAN1_TX_IRQHandler ; CAN1 TX DCD CAN1_RX0_IRQHandler ; CAN1 RX0 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 DCD CAN1_SCE_IRQHandler ; CAN1 SCE DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; External Line[15:10]s DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 DCD FMC_IRQHandler ; FMC DCD SDIO_IRQHandler ; SDIO DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 DCD UART4_IRQHandler ; UART4 DCD UART5_IRQHandler ; UART5 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 DCD ETH_IRQHandler ; Ethernet DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line DCD CAN2_TX_IRQHandler ; CAN2 TX DCD CAN2_RX0_IRQHandler ; CAN2 RX0 DCD CAN2_RX1_IRQHandler ; CAN2 RX1 DCD CAN2_SCE_IRQHandler ; CAN2 SCE DCD OTG_FS_IRQHandler ; USB OTG FS DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 DCD USART6_IRQHandler ; USART6 DCD I2C3_EV_IRQHandler ; I2C3 event DCD I2C3_ER_IRQHandler ; I2C3 error DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_IRQHandler ; DCMI DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 DCD UART8_IRQHandler ; UART8 DCD SPI4_IRQHandler ; SPI4 DCD SPI5_IRQHandler ; SPI5 DCD SPI6_IRQHandler ; SPI6 DCD SAI1_IRQHandler ; SAI1 DCD 0 ; Reserved DCD 0 ; Reserved DCD DMA2D_IRQHandler ; DMA2D ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. ;; THUMB PUBWEAK Reset_Handler SECTION .text:CODE:REORDER(2) Reset_Handler LDR R0, =SystemInit BLX R0 LDR R0, =__iar_program_start BX R0 PUBWEAK NMI_Handler SECTION .text:CODE:REORDER(1) NMI_Handler B NMI_Handler PUBWEAK HardFault_Handler SECTION .text:CODE:REORDER(1) HardFault_Handler B HardFault_Handler PUBWEAK MemManage_Handler SECTION .text:CODE:REORDER(1) MemManage_Handler B MemManage_Handler PUBWEAK BusFault_Handler SECTION .text:CODE:REORDER(1) BusFault_Handler B BusFault_Handler PUBWEAK UsageFault_Handler SECTION .text:CODE:REORDER(1) UsageFault_Handler B UsageFault_Handler PUBWEAK SVC_Handler SECTION .text:CODE:REORDER(1) SVC_Handler B SVC_Handler PUBWEAK DebugMon_Handler SECTION .text:CODE:REORDER(1) DebugMon_Handler B DebugMon_Handler PUBWEAK PendSV_Handler SECTION .text:CODE:REORDER(1) PendSV_Handler B PendSV_Handler PUBWEAK SysTick_Handler SECTION .text:CODE:REORDER(1) SysTick_Handler B SysTick_Handler PUBWEAK WWDG_IRQHandler SECTION .text:CODE:REORDER(1) WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_IRQHandler SECTION .text:CODE:REORDER(1) PVD_IRQHandler B PVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler SECTION .text:CODE:REORDER(1) TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:REORDER(1) FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:REORDER(1) RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:REORDER(1) EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:REORDER(1) EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:REORDER(1) EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler SECTION .text:CODE:REORDER(1) EXTI3_IRQHandler B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler SECTION .text:CODE:REORDER(1) EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:REORDER(1) ADC_IRQHandler B ADC_IRQHandler PUBWEAK CAN1_TX_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_TX_IRQHandler B CAN1_TX_IRQHandler PUBWEAK CAN1_RX0_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_RX0_IRQHandler B CAN1_RX0_IRQHandler PUBWEAK CAN1_RX1_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_RX1_IRQHandler B CAN1_RX1_IRQHandler PUBWEAK CAN1_SCE_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_SCE_IRQHandler B CAN1_SCE_IRQHandler PUBWEAK EXTI9_5_IRQHandler SECTION .text:CODE:REORDER(1) EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_TIM9_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_BRK_TIM9_IRQHandler B TIM1_BRK_TIM9_IRQHandler PUBWEAK TIM1_UP_TIM10_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_UP_TIM10_IRQHandler B TIM1_UP_TIM10_IRQHandler PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_TRG_COM_TIM11_IRQHandler B TIM1_TRG_COM_TIM11_IRQHandler PUBWEAK TIM1_CC_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:REORDER(1) TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:REORDER(1) TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:REORDER(1) TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler SECTION .text:CODE:REORDER(1) I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler SECTION .text:CODE:REORDER(1) I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler SECTION .text:CODE:REORDER(1) I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler SECTION .text:CODE:REORDER(1) I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:REORDER(1) SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:REORDER(1) SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:REORDER(1) USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:REORDER(1) USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:REORDER(1) USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler SECTION .text:CODE:REORDER(1) EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler SECTION .text:CODE:REORDER(1) RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler PUBWEAK TIM8_BRK_TIM12_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:REORDER(1) FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDIO_IRQHandler SECTION .text:CODE:REORDER(1) SDIO_IRQHandler B SDIO_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:REORDER(1) TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:REORDER(1) SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:REORDER(1) UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:REORDER(1) UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler SECTION .text:CODE:REORDER(1) TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler SECTION .text:CODE:REORDER(1) TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:REORDER(1) ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK CAN2_TX_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_TX_IRQHandler B CAN2_TX_IRQHandler PUBWEAK CAN2_RX0_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_RX0_IRQHandler B CAN2_RX0_IRQHandler PUBWEAK CAN2_RX1_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_RX1_IRQHandler B CAN2_RX1_IRQHandler PUBWEAK CAN2_SCE_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_SCE_IRQHandler B CAN2_SCE_IRQHandler PUBWEAK OTG_FS_IRQHandler SECTION .text:CODE:REORDER(1) OTG_FS_IRQHandler B OTG_FS_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:REORDER(1) USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler SECTION .text:CODE:REORDER(1) I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler SECTION .text:CODE:REORDER(1) I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_IRQHandler B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:REORDER(1) DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK CRYP_IRQHandler SECTION .text:CODE:REORDER(1) CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler SECTION .text:CODE:REORDER(1) HASH_RNG_IRQHandler B HASH_RNG_IRQHandler PUBWEAK FPU_IRQHandler SECTION .text:CODE:REORDER(1) FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler SECTION .text:CODE:REORDER(1) UART7_IRQHandler B UART7_IRQHandler PUBWEAK UART8_IRQHandler SECTION .text:CODE:REORDER(1) UART8_IRQHandler B UART8_IRQHandler PUBWEAK SPI4_IRQHandler SECTION .text:CODE:REORDER(1) SPI4_IRQHandler B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler SECTION .text:CODE:REORDER(1) SPI5_IRQHandler B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler SECTION .text:CODE:REORDER(1) SPI6_IRQHandler B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler SECTION .text:CODE:REORDER(1) SAI1_IRQHandler B SAI1_IRQHandler PUBWEAK DMA2D_IRQHandler SECTION .text:CODE:REORDER(1) DMA2D_IRQHandler B DMA2D_IRQHandler END /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f427x.s ================================================ ;/******************** (C) COPYRIGHT 2013 STMicroelectronics ******************** ;* File Name : startup_stm32f427x.s ;* Author : MCD Application Team ;* Version : V1.3.0 ;* Date : 08-November-2013 ;* Description : STM32F427xx/437xx devices vector table for EWARM toolchain. ;* Same as startup_stm32f42_43xxx.s and maintained for legacy purpose ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, ;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Configure the system clock and the external SRAM/SDRAM mounted ;* on STM324x7I-EVAL boards to be used as data memory ;* (optional, to be enabled by user) ;* - Branches to main in the C library (which eventually ;* calls main()). ;* After Reset the Cortex-M4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* ;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); ;* You may not use this file except in compliance with the License. ;* You may obtain a copy of the License at: ;* ;* http://www.st.com/software_license_agreement_liberty_v2 ;* ;* Unless required by applicable law or agreed to in writing, software ;* distributed under the License is distributed on an "AS IS" BASIS, ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* See the License for the specific language governing permissions and ;* limitations under the License. ;* ;*******************************************************************************/ ; ; ; The modules in this file are included in the libraries, and may be replaced ; by any user-defined modules that define the PUBLIC symbol _program_start or ; a user defined start symbol. ; To override the cstartup defined in the library, simply add your modified ; version to the workbench project. ; ; The vector table is normally located at address 0. ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. ; The name "__vector_table" has special meaning for C-SPY: ; it is where the SP start value is found, and the NVIC vector ; table register (VTOR) is initialized to this address if != 0. ; ; Cortex-M version ; MODULE ?cstartup ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) EXTERN __iar_program_start EXTERN SystemInit PUBLIC __vector_table DATA __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog DCD PVD_IRQHandler ; PVD through EXTI Line detection DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line DCD FLASH_IRQHandler ; FLASH DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line0 DCD EXTI1_IRQHandler ; EXTI Line1 DCD EXTI2_IRQHandler ; EXTI Line2 DCD EXTI3_IRQHandler ; EXTI Line3 DCD EXTI4_IRQHandler ; EXTI Line4 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s DCD CAN1_TX_IRQHandler ; CAN1 TX DCD CAN1_RX0_IRQHandler ; CAN1 RX0 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 DCD CAN1_SCE_IRQHandler ; CAN1 SCE DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; External Line[15:10]s DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 DCD FMC_IRQHandler ; FMC DCD SDIO_IRQHandler ; SDIO DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 DCD UART4_IRQHandler ; UART4 DCD UART5_IRQHandler ; UART5 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 DCD ETH_IRQHandler ; Ethernet DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line DCD CAN2_TX_IRQHandler ; CAN2 TX DCD CAN2_RX0_IRQHandler ; CAN2 RX0 DCD CAN2_RX1_IRQHandler ; CAN2 RX1 DCD CAN2_SCE_IRQHandler ; CAN2 SCE DCD OTG_FS_IRQHandler ; USB OTG FS DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 DCD USART6_IRQHandler ; USART6 DCD I2C3_EV_IRQHandler ; I2C3 event DCD I2C3_ER_IRQHandler ; I2C3 error DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_IRQHandler ; DCMI DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 DCD UART8_IRQHandler ; UART8 DCD SPI4_IRQHandler ; SPI4 DCD SPI5_IRQHandler ; SPI5 DCD SPI6_IRQHandler ; SPI6 DCD SAI1_IRQHandler ; SAI1 DCD 0 ; Reserved DCD 0 ; Reserved DCD DMA2D_IRQHandler ; DMA2D ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. ;; THUMB PUBWEAK Reset_Handler SECTION .text:CODE:REORDER(2) Reset_Handler LDR R0, =SystemInit BLX R0 LDR R0, =__iar_program_start BX R0 PUBWEAK NMI_Handler SECTION .text:CODE:REORDER(1) NMI_Handler B NMI_Handler PUBWEAK HardFault_Handler SECTION .text:CODE:REORDER(1) HardFault_Handler B HardFault_Handler PUBWEAK MemManage_Handler SECTION .text:CODE:REORDER(1) MemManage_Handler B MemManage_Handler PUBWEAK BusFault_Handler SECTION .text:CODE:REORDER(1) BusFault_Handler B BusFault_Handler PUBWEAK UsageFault_Handler SECTION .text:CODE:REORDER(1) UsageFault_Handler B UsageFault_Handler PUBWEAK SVC_Handler SECTION .text:CODE:REORDER(1) SVC_Handler B SVC_Handler PUBWEAK DebugMon_Handler SECTION .text:CODE:REORDER(1) DebugMon_Handler B DebugMon_Handler PUBWEAK PendSV_Handler SECTION .text:CODE:REORDER(1) PendSV_Handler B PendSV_Handler PUBWEAK SysTick_Handler SECTION .text:CODE:REORDER(1) SysTick_Handler B SysTick_Handler PUBWEAK WWDG_IRQHandler SECTION .text:CODE:REORDER(1) WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_IRQHandler SECTION .text:CODE:REORDER(1) PVD_IRQHandler B PVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler SECTION .text:CODE:REORDER(1) TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:REORDER(1) FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:REORDER(1) RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:REORDER(1) EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:REORDER(1) EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:REORDER(1) EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler SECTION .text:CODE:REORDER(1) EXTI3_IRQHandler B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler SECTION .text:CODE:REORDER(1) EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:REORDER(1) ADC_IRQHandler B ADC_IRQHandler PUBWEAK CAN1_TX_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_TX_IRQHandler B CAN1_TX_IRQHandler PUBWEAK CAN1_RX0_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_RX0_IRQHandler B CAN1_RX0_IRQHandler PUBWEAK CAN1_RX1_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_RX1_IRQHandler B CAN1_RX1_IRQHandler PUBWEAK CAN1_SCE_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_SCE_IRQHandler B CAN1_SCE_IRQHandler PUBWEAK EXTI9_5_IRQHandler SECTION .text:CODE:REORDER(1) EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_TIM9_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_BRK_TIM9_IRQHandler B TIM1_BRK_TIM9_IRQHandler PUBWEAK TIM1_UP_TIM10_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_UP_TIM10_IRQHandler B TIM1_UP_TIM10_IRQHandler PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_TRG_COM_TIM11_IRQHandler B TIM1_TRG_COM_TIM11_IRQHandler PUBWEAK TIM1_CC_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:REORDER(1) TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:REORDER(1) TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:REORDER(1) TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler SECTION .text:CODE:REORDER(1) I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler SECTION .text:CODE:REORDER(1) I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler SECTION .text:CODE:REORDER(1) I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler SECTION .text:CODE:REORDER(1) I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:REORDER(1) SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:REORDER(1) SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:REORDER(1) USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:REORDER(1) USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:REORDER(1) USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler SECTION .text:CODE:REORDER(1) EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler SECTION .text:CODE:REORDER(1) RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler PUBWEAK TIM8_BRK_TIM12_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:REORDER(1) FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDIO_IRQHandler SECTION .text:CODE:REORDER(1) SDIO_IRQHandler B SDIO_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:REORDER(1) TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:REORDER(1) SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:REORDER(1) UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:REORDER(1) UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler SECTION .text:CODE:REORDER(1) TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler SECTION .text:CODE:REORDER(1) TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:REORDER(1) ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK CAN2_TX_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_TX_IRQHandler B CAN2_TX_IRQHandler PUBWEAK CAN2_RX0_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_RX0_IRQHandler B CAN2_RX0_IRQHandler PUBWEAK CAN2_RX1_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_RX1_IRQHandler B CAN2_RX1_IRQHandler PUBWEAK CAN2_SCE_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_SCE_IRQHandler B CAN2_SCE_IRQHandler PUBWEAK OTG_FS_IRQHandler SECTION .text:CODE:REORDER(1) OTG_FS_IRQHandler B OTG_FS_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:REORDER(1) USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler SECTION .text:CODE:REORDER(1) I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler SECTION .text:CODE:REORDER(1) I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_IRQHandler B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:REORDER(1) DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK CRYP_IRQHandler SECTION .text:CODE:REORDER(1) CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler SECTION .text:CODE:REORDER(1) HASH_RNG_IRQHandler B HASH_RNG_IRQHandler PUBWEAK FPU_IRQHandler SECTION .text:CODE:REORDER(1) FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler SECTION .text:CODE:REORDER(1) UART7_IRQHandler B UART7_IRQHandler PUBWEAK UART8_IRQHandler SECTION .text:CODE:REORDER(1) UART8_IRQHandler B UART8_IRQHandler PUBWEAK SPI4_IRQHandler SECTION .text:CODE:REORDER(1) SPI4_IRQHandler B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler SECTION .text:CODE:REORDER(1) SPI5_IRQHandler B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler SECTION .text:CODE:REORDER(1) SPI6_IRQHandler B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler SECTION .text:CODE:REORDER(1) SAI1_IRQHandler B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler SECTION .text:CODE:REORDER(1) LTDC_IRQHandler B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler SECTION .text:CODE:REORDER(1) LTDC_ER_IRQHandler B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler SECTION .text:CODE:REORDER(1) DMA2D_IRQHandler B DMA2D_IRQHandler END /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f429_439xx.s ================================================ ;/******************** (C) COPYRIGHT 2013 STMicroelectronics ******************** ;* File Name : startup_stm32f429_439xx.s ;* Author : MCD Application Team ;* Version : V1.3.0 ;* Date : 08-November-2013 ;* Description : STM32F429xx/439xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP ;* - Set the initial PC == _iar_program_start, ;* - Set the vector table entries with the exceptions ISR ;* address. ;* - Configure the system clock and the external SRAM/SDRAM mounted ;* on STM324x9I-EVAL board to be used as data memory (optional, ;* to be enabled by user) ;* - Branches to main in the C library (which eventually ;* calls main()). ;* After Reset the Cortex-M4 processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. ;******************************************************************************** ;* ;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); ;* You may not use this file except in compliance with the License. ;* You may obtain a copy of the License at: ;* ;* http://www.st.com/software_license_agreement_liberty_v2 ;* ;* Unless required by applicable law or agreed to in writing, software ;* distributed under the License is distributed on an "AS IS" BASIS, ;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. ;* See the License for the specific language governing permissions and ;* limitations under the License. ;* ;*******************************************************************************/ ; ; ; The modules in this file are included in the libraries, and may be replaced ; by any user-defined modules that define the PUBLIC symbol _program_start or ; a user defined start symbol. ; To override the cstartup defined in the library, simply add your modified ; version to the workbench project. ; ; The vector table is normally located at address 0. ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. ; The name "__vector_table" has special meaning for C-SPY: ; it is where the SP start value is found, and the NVIC vector ; table register (VTOR) is initialized to this address if != 0. ; ; Cortex-M version ; MODULE ?cstartup ;; Forward declaration of sections. SECTION CSTACK:DATA:NOROOT(3) SECTION .intvec:CODE:NOROOT(2) EXTERN __iar_program_start EXTERN SystemInit PUBLIC __vector_table DATA __vector_table DCD sfe(CSTACK) DCD Reset_Handler ; Reset Handler DCD NMI_Handler ; NMI Handler DCD HardFault_Handler ; Hard Fault Handler DCD MemManage_Handler ; MPU Fault Handler DCD BusFault_Handler ; Bus Fault Handler DCD UsageFault_Handler ; Usage Fault Handler DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD 0 ; Reserved DCD SVC_Handler ; SVCall Handler DCD DebugMon_Handler ; Debug Monitor Handler DCD 0 ; Reserved DCD PendSV_Handler ; PendSV Handler DCD SysTick_Handler ; SysTick Handler ; External Interrupts DCD WWDG_IRQHandler ; Window WatchDog DCD PVD_IRQHandler ; PVD through EXTI Line detection DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line DCD FLASH_IRQHandler ; FLASH DCD RCC_IRQHandler ; RCC DCD EXTI0_IRQHandler ; EXTI Line0 DCD EXTI1_IRQHandler ; EXTI Line1 DCD EXTI2_IRQHandler ; EXTI Line2 DCD EXTI3_IRQHandler ; EXTI Line3 DCD EXTI4_IRQHandler ; EXTI Line4 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s DCD CAN1_TX_IRQHandler ; CAN1 TX DCD CAN1_RX0_IRQHandler ; CAN1 RX0 DCD CAN1_RX1_IRQHandler ; CAN1 RX1 DCD CAN1_SCE_IRQHandler ; CAN1 SCE DCD EXTI9_5_IRQHandler ; External Line[9:5]s DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare DCD TIM2_IRQHandler ; TIM2 DCD TIM3_IRQHandler ; TIM3 DCD TIM4_IRQHandler ; TIM4 DCD I2C1_EV_IRQHandler ; I2C1 Event DCD I2C1_ER_IRQHandler ; I2C1 Error DCD I2C2_EV_IRQHandler ; I2C2 Event DCD I2C2_ER_IRQHandler ; I2C2 Error DCD SPI1_IRQHandler ; SPI1 DCD SPI2_IRQHandler ; SPI2 DCD USART1_IRQHandler ; USART1 DCD USART2_IRQHandler ; USART2 DCD USART3_IRQHandler ; USART3 DCD EXTI15_10_IRQHandler ; External Line[15:10]s DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 DCD FMC_IRQHandler ; FMC DCD SDIO_IRQHandler ; SDIO DCD TIM5_IRQHandler ; TIM5 DCD SPI3_IRQHandler ; SPI3 DCD UART4_IRQHandler ; UART4 DCD UART5_IRQHandler ; UART5 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors DCD TIM7_IRQHandler ; TIM7 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 DCD ETH_IRQHandler ; Ethernet DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line DCD CAN2_TX_IRQHandler ; CAN2 TX DCD CAN2_RX0_IRQHandler ; CAN2 RX0 DCD CAN2_RX1_IRQHandler ; CAN2 RX1 DCD CAN2_SCE_IRQHandler ; CAN2 SCE DCD OTG_FS_IRQHandler ; USB OTG FS DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 DCD USART6_IRQHandler ; USART6 DCD I2C3_EV_IRQHandler ; I2C3 event DCD I2C3_ER_IRQHandler ; I2C3 error DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI DCD OTG_HS_IRQHandler ; USB OTG HS DCD DCMI_IRQHandler ; DCMI DCD CRYP_IRQHandler ; CRYP crypto DCD HASH_RNG_IRQHandler ; Hash and Rng DCD FPU_IRQHandler ; FPU DCD UART7_IRQHandler ; UART7 DCD UART8_IRQHandler ; UART8 DCD SPI4_IRQHandler ; SPI4 DCD SPI5_IRQHandler ; SPI5 DCD SPI6_IRQHandler ; SPI6 DCD SAI1_IRQHandler ; SAI1 DCD LTDC_IRQHandler ; LTDC DCD LTDC_ER_IRQHandler ; LTDC error DCD DMA2D_IRQHandler ; DMA2D ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Default interrupt handlers. ;; THUMB PUBWEAK Reset_Handler SECTION .text:CODE:REORDER(2) Reset_Handler LDR R0, =SystemInit BLX R0 LDR R0, =__iar_program_start BX R0 PUBWEAK NMI_Handler SECTION .text:CODE:REORDER(1) NMI_Handler B NMI_Handler PUBWEAK HardFault_Handler SECTION .text:CODE:REORDER(1) HardFault_Handler B HardFault_Handler PUBWEAK MemManage_Handler SECTION .text:CODE:REORDER(1) MemManage_Handler B MemManage_Handler PUBWEAK BusFault_Handler SECTION .text:CODE:REORDER(1) BusFault_Handler B BusFault_Handler PUBWEAK UsageFault_Handler SECTION .text:CODE:REORDER(1) UsageFault_Handler B UsageFault_Handler PUBWEAK SVC_Handler SECTION .text:CODE:REORDER(1) SVC_Handler B SVC_Handler PUBWEAK DebugMon_Handler SECTION .text:CODE:REORDER(1) DebugMon_Handler B DebugMon_Handler PUBWEAK PendSV_Handler SECTION .text:CODE:REORDER(1) PendSV_Handler B PendSV_Handler PUBWEAK SysTick_Handler SECTION .text:CODE:REORDER(1) SysTick_Handler B SysTick_Handler PUBWEAK WWDG_IRQHandler SECTION .text:CODE:REORDER(1) WWDG_IRQHandler B WWDG_IRQHandler PUBWEAK PVD_IRQHandler SECTION .text:CODE:REORDER(1) PVD_IRQHandler B PVD_IRQHandler PUBWEAK TAMP_STAMP_IRQHandler SECTION .text:CODE:REORDER(1) TAMP_STAMP_IRQHandler B TAMP_STAMP_IRQHandler PUBWEAK RTC_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) RTC_WKUP_IRQHandler B RTC_WKUP_IRQHandler PUBWEAK FLASH_IRQHandler SECTION .text:CODE:REORDER(1) FLASH_IRQHandler B FLASH_IRQHandler PUBWEAK RCC_IRQHandler SECTION .text:CODE:REORDER(1) RCC_IRQHandler B RCC_IRQHandler PUBWEAK EXTI0_IRQHandler SECTION .text:CODE:REORDER(1) EXTI0_IRQHandler B EXTI0_IRQHandler PUBWEAK EXTI1_IRQHandler SECTION .text:CODE:REORDER(1) EXTI1_IRQHandler B EXTI1_IRQHandler PUBWEAK EXTI2_IRQHandler SECTION .text:CODE:REORDER(1) EXTI2_IRQHandler B EXTI2_IRQHandler PUBWEAK EXTI3_IRQHandler SECTION .text:CODE:REORDER(1) EXTI3_IRQHandler B EXTI3_IRQHandler PUBWEAK EXTI4_IRQHandler SECTION .text:CODE:REORDER(1) EXTI4_IRQHandler B EXTI4_IRQHandler PUBWEAK DMA1_Stream0_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream0_IRQHandler B DMA1_Stream0_IRQHandler PUBWEAK DMA1_Stream1_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream1_IRQHandler B DMA1_Stream1_IRQHandler PUBWEAK DMA1_Stream2_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream2_IRQHandler B DMA1_Stream2_IRQHandler PUBWEAK DMA1_Stream3_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream3_IRQHandler B DMA1_Stream3_IRQHandler PUBWEAK DMA1_Stream4_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream4_IRQHandler B DMA1_Stream4_IRQHandler PUBWEAK DMA1_Stream5_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream5_IRQHandler B DMA1_Stream5_IRQHandler PUBWEAK DMA1_Stream6_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream6_IRQHandler B DMA1_Stream6_IRQHandler PUBWEAK ADC_IRQHandler SECTION .text:CODE:REORDER(1) ADC_IRQHandler B ADC_IRQHandler PUBWEAK CAN1_TX_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_TX_IRQHandler B CAN1_TX_IRQHandler PUBWEAK CAN1_RX0_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_RX0_IRQHandler B CAN1_RX0_IRQHandler PUBWEAK CAN1_RX1_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_RX1_IRQHandler B CAN1_RX1_IRQHandler PUBWEAK CAN1_SCE_IRQHandler SECTION .text:CODE:REORDER(1) CAN1_SCE_IRQHandler B CAN1_SCE_IRQHandler PUBWEAK EXTI9_5_IRQHandler SECTION .text:CODE:REORDER(1) EXTI9_5_IRQHandler B EXTI9_5_IRQHandler PUBWEAK TIM1_BRK_TIM9_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_BRK_TIM9_IRQHandler B TIM1_BRK_TIM9_IRQHandler PUBWEAK TIM1_UP_TIM10_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_UP_TIM10_IRQHandler B TIM1_UP_TIM10_IRQHandler PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_TRG_COM_TIM11_IRQHandler B TIM1_TRG_COM_TIM11_IRQHandler PUBWEAK TIM1_CC_IRQHandler SECTION .text:CODE:REORDER(1) TIM1_CC_IRQHandler B TIM1_CC_IRQHandler PUBWEAK TIM2_IRQHandler SECTION .text:CODE:REORDER(1) TIM2_IRQHandler B TIM2_IRQHandler PUBWEAK TIM3_IRQHandler SECTION .text:CODE:REORDER(1) TIM3_IRQHandler B TIM3_IRQHandler PUBWEAK TIM4_IRQHandler SECTION .text:CODE:REORDER(1) TIM4_IRQHandler B TIM4_IRQHandler PUBWEAK I2C1_EV_IRQHandler SECTION .text:CODE:REORDER(1) I2C1_EV_IRQHandler B I2C1_EV_IRQHandler PUBWEAK I2C1_ER_IRQHandler SECTION .text:CODE:REORDER(1) I2C1_ER_IRQHandler B I2C1_ER_IRQHandler PUBWEAK I2C2_EV_IRQHandler SECTION .text:CODE:REORDER(1) I2C2_EV_IRQHandler B I2C2_EV_IRQHandler PUBWEAK I2C2_ER_IRQHandler SECTION .text:CODE:REORDER(1) I2C2_ER_IRQHandler B I2C2_ER_IRQHandler PUBWEAK SPI1_IRQHandler SECTION .text:CODE:REORDER(1) SPI1_IRQHandler B SPI1_IRQHandler PUBWEAK SPI2_IRQHandler SECTION .text:CODE:REORDER(1) SPI2_IRQHandler B SPI2_IRQHandler PUBWEAK USART1_IRQHandler SECTION .text:CODE:REORDER(1) USART1_IRQHandler B USART1_IRQHandler PUBWEAK USART2_IRQHandler SECTION .text:CODE:REORDER(1) USART2_IRQHandler B USART2_IRQHandler PUBWEAK USART3_IRQHandler SECTION .text:CODE:REORDER(1) USART3_IRQHandler B USART3_IRQHandler PUBWEAK EXTI15_10_IRQHandler SECTION .text:CODE:REORDER(1) EXTI15_10_IRQHandler B EXTI15_10_IRQHandler PUBWEAK RTC_Alarm_IRQHandler SECTION .text:CODE:REORDER(1) RTC_Alarm_IRQHandler B RTC_Alarm_IRQHandler PUBWEAK OTG_FS_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) OTG_FS_WKUP_IRQHandler B OTG_FS_WKUP_IRQHandler PUBWEAK TIM8_BRK_TIM12_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_BRK_TIM12_IRQHandler B TIM8_BRK_TIM12_IRQHandler PUBWEAK TIM8_UP_TIM13_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_UP_TIM13_IRQHandler B TIM8_UP_TIM13_IRQHandler PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_TRG_COM_TIM14_IRQHandler B TIM8_TRG_COM_TIM14_IRQHandler PUBWEAK TIM8_CC_IRQHandler SECTION .text:CODE:REORDER(1) TIM8_CC_IRQHandler B TIM8_CC_IRQHandler PUBWEAK DMA1_Stream7_IRQHandler SECTION .text:CODE:REORDER(1) DMA1_Stream7_IRQHandler B DMA1_Stream7_IRQHandler PUBWEAK FMC_IRQHandler SECTION .text:CODE:REORDER(1) FMC_IRQHandler B FMC_IRQHandler PUBWEAK SDIO_IRQHandler SECTION .text:CODE:REORDER(1) SDIO_IRQHandler B SDIO_IRQHandler PUBWEAK TIM5_IRQHandler SECTION .text:CODE:REORDER(1) TIM5_IRQHandler B TIM5_IRQHandler PUBWEAK SPI3_IRQHandler SECTION .text:CODE:REORDER(1) SPI3_IRQHandler B SPI3_IRQHandler PUBWEAK UART4_IRQHandler SECTION .text:CODE:REORDER(1) UART4_IRQHandler B UART4_IRQHandler PUBWEAK UART5_IRQHandler SECTION .text:CODE:REORDER(1) UART5_IRQHandler B UART5_IRQHandler PUBWEAK TIM6_DAC_IRQHandler SECTION .text:CODE:REORDER(1) TIM6_DAC_IRQHandler B TIM6_DAC_IRQHandler PUBWEAK TIM7_IRQHandler SECTION .text:CODE:REORDER(1) TIM7_IRQHandler B TIM7_IRQHandler PUBWEAK DMA2_Stream0_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream0_IRQHandler B DMA2_Stream0_IRQHandler PUBWEAK DMA2_Stream1_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream1_IRQHandler B DMA2_Stream1_IRQHandler PUBWEAK DMA2_Stream2_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream2_IRQHandler B DMA2_Stream2_IRQHandler PUBWEAK DMA2_Stream3_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream3_IRQHandler B DMA2_Stream3_IRQHandler PUBWEAK DMA2_Stream4_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream4_IRQHandler B DMA2_Stream4_IRQHandler PUBWEAK ETH_IRQHandler SECTION .text:CODE:REORDER(1) ETH_IRQHandler B ETH_IRQHandler PUBWEAK ETH_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) ETH_WKUP_IRQHandler B ETH_WKUP_IRQHandler PUBWEAK CAN2_TX_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_TX_IRQHandler B CAN2_TX_IRQHandler PUBWEAK CAN2_RX0_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_RX0_IRQHandler B CAN2_RX0_IRQHandler PUBWEAK CAN2_RX1_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_RX1_IRQHandler B CAN2_RX1_IRQHandler PUBWEAK CAN2_SCE_IRQHandler SECTION .text:CODE:REORDER(1) CAN2_SCE_IRQHandler B CAN2_SCE_IRQHandler PUBWEAK OTG_FS_IRQHandler SECTION .text:CODE:REORDER(1) OTG_FS_IRQHandler B OTG_FS_IRQHandler PUBWEAK DMA2_Stream5_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream5_IRQHandler B DMA2_Stream5_IRQHandler PUBWEAK DMA2_Stream6_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream6_IRQHandler B DMA2_Stream6_IRQHandler PUBWEAK DMA2_Stream7_IRQHandler SECTION .text:CODE:REORDER(1) DMA2_Stream7_IRQHandler B DMA2_Stream7_IRQHandler PUBWEAK USART6_IRQHandler SECTION .text:CODE:REORDER(1) USART6_IRQHandler B USART6_IRQHandler PUBWEAK I2C3_EV_IRQHandler SECTION .text:CODE:REORDER(1) I2C3_EV_IRQHandler B I2C3_EV_IRQHandler PUBWEAK I2C3_ER_IRQHandler SECTION .text:CODE:REORDER(1) I2C3_ER_IRQHandler B I2C3_ER_IRQHandler PUBWEAK OTG_HS_EP1_OUT_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_EP1_OUT_IRQHandler B OTG_HS_EP1_OUT_IRQHandler PUBWEAK OTG_HS_EP1_IN_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_EP1_IN_IRQHandler B OTG_HS_EP1_IN_IRQHandler PUBWEAK OTG_HS_WKUP_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_WKUP_IRQHandler B OTG_HS_WKUP_IRQHandler PUBWEAK OTG_HS_IRQHandler SECTION .text:CODE:REORDER(1) OTG_HS_IRQHandler B OTG_HS_IRQHandler PUBWEAK DCMI_IRQHandler SECTION .text:CODE:REORDER(1) DCMI_IRQHandler B DCMI_IRQHandler PUBWEAK CRYP_IRQHandler SECTION .text:CODE:REORDER(1) CRYP_IRQHandler B CRYP_IRQHandler PUBWEAK HASH_RNG_IRQHandler SECTION .text:CODE:REORDER(1) HASH_RNG_IRQHandler B HASH_RNG_IRQHandler PUBWEAK FPU_IRQHandler SECTION .text:CODE:REORDER(1) FPU_IRQHandler B FPU_IRQHandler PUBWEAK UART7_IRQHandler SECTION .text:CODE:REORDER(1) UART7_IRQHandler B UART7_IRQHandler PUBWEAK UART8_IRQHandler SECTION .text:CODE:REORDER(1) UART8_IRQHandler B UART8_IRQHandler PUBWEAK SPI4_IRQHandler SECTION .text:CODE:REORDER(1) SPI4_IRQHandler B SPI4_IRQHandler PUBWEAK SPI5_IRQHandler SECTION .text:CODE:REORDER(1) SPI5_IRQHandler B SPI5_IRQHandler PUBWEAK SPI6_IRQHandler SECTION .text:CODE:REORDER(1) SPI6_IRQHandler B SPI6_IRQHandler PUBWEAK SAI1_IRQHandler SECTION .text:CODE:REORDER(1) SAI1_IRQHandler B SAI1_IRQHandler PUBWEAK LTDC_IRQHandler SECTION .text:CODE:REORDER(1) LTDC_IRQHandler B LTDC_IRQHandler PUBWEAK LTDC_ER_IRQHandler SECTION .text:CODE:REORDER(1) LTDC_ER_IRQHandler B LTDC_ER_IRQHandler PUBWEAK DMA2D_IRQHandler SECTION .text:CODE:REORDER(1) DMA2D_IRQHandler B DMA2D_IRQHandler END /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c ================================================ /** ****************************************************************************** * @file system_stm32f4xx.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * This file contains the system clock configuration for STM32F4xx devices. * * 1. This file provides two functions and one global variable to be called from * user application: * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier * and Divider factors, AHB/APBx prescalers and Flash settings), * depending on the configuration made in the clock xls tool. * This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32f4xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used * by the user application to setup the SysTick * timer or configure other parameters. * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. * * 2. After each device reset the HSI (16 MHz) is used as system clock source. * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to * configure the system clock before to branch to main program. * * 3. If the system clock source selected by user fails to startup, the SystemInit() * function will do nothing and HSI still used as system clock source. User can * add some code to deal with this issue inside the SetSysClock() function. * * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or * through PLL, and you are using different crystal you have to adapt the HSE * value to your own configuration. * * 5. This file configures the system clock as follows: *============================================================================= *============================================================================= * Supported STM32F40xxx/41xxx devices *----------------------------------------------------------------------------- * System Clock source | PLL (HSE) *----------------------------------------------------------------------------- * SYSCLK(Hz) | 168000000 *----------------------------------------------------------------------------- * HCLK(Hz) | 168000000 *----------------------------------------------------------------------------- * AHB Prescaler | 1 *----------------------------------------------------------------------------- * APB1 Prescaler | 4 *----------------------------------------------------------------------------- * APB2 Prescaler | 2 *----------------------------------------------------------------------------- * HSE Frequency(Hz) | 25000000 *----------------------------------------------------------------------------- * PLL_M | 25 *----------------------------------------------------------------------------- * PLL_N | 336 *----------------------------------------------------------------------------- * PLL_P | 2 *----------------------------------------------------------------------------- * PLL_Q | 7 *----------------------------------------------------------------------------- * PLLI2S_N | NA *----------------------------------------------------------------------------- * PLLI2S_R | NA *----------------------------------------------------------------------------- * I2S input clock | NA *----------------------------------------------------------------------------- * VDD(V) | 3.3 *----------------------------------------------------------------------------- * Main regulator output voltage | Scale1 mode *----------------------------------------------------------------------------- * Flash Latency(WS) | 5 *----------------------------------------------------------------------------- * Prefetch Buffer | ON *----------------------------------------------------------------------------- * Instruction cache | ON *----------------------------------------------------------------------------- * Data cache | ON *----------------------------------------------------------------------------- * Require 48MHz for USB OTG FS, | Disabled * SDIO and RNG clock | *----------------------------------------------------------------------------- *============================================================================= *============================================================================= * Supported STM32F42xxx/43xxx devices *----------------------------------------------------------------------------- * System Clock source | PLL (HSE) *----------------------------------------------------------------------------- * SYSCLK(Hz) | 180000000 *----------------------------------------------------------------------------- * HCLK(Hz) | 180000000 *----------------------------------------------------------------------------- * AHB Prescaler | 1 *----------------------------------------------------------------------------- * APB1 Prescaler | 4 *----------------------------------------------------------------------------- * APB2 Prescaler | 2 *----------------------------------------------------------------------------- * HSE Frequency(Hz) | 25000000 *----------------------------------------------------------------------------- * PLL_M | 25 *----------------------------------------------------------------------------- * PLL_N | 360 *----------------------------------------------------------------------------- * PLL_P | 2 *----------------------------------------------------------------------------- * PLL_Q | 7 *----------------------------------------------------------------------------- * PLLI2S_N | NA *----------------------------------------------------------------------------- * PLLI2S_R | NA *----------------------------------------------------------------------------- * I2S input clock | NA *----------------------------------------------------------------------------- * VDD(V) | 3.3 *----------------------------------------------------------------------------- * Main regulator output voltage | Scale1 mode *----------------------------------------------------------------------------- * Flash Latency(WS) | 5 *----------------------------------------------------------------------------- * Prefetch Buffer | ON *----------------------------------------------------------------------------- * Instruction cache | ON *----------------------------------------------------------------------------- * Data cache | ON *----------------------------------------------------------------------------- * Require 48MHz for USB OTG FS, | Disabled * SDIO and RNG clock | *----------------------------------------------------------------------------- *============================================================================= *============================================================================= * Supported STM32F401xx devices *----------------------------------------------------------------------------- * System Clock source | PLL (HSE) *----------------------------------------------------------------------------- * SYSCLK(Hz) | 84000000 *----------------------------------------------------------------------------- * HCLK(Hz) | 84000000 *----------------------------------------------------------------------------- * AHB Prescaler | 1 *----------------------------------------------------------------------------- * APB1 Prescaler | 2 *----------------------------------------------------------------------------- * APB2 Prescaler | 1 *----------------------------------------------------------------------------- * HSE Frequency(Hz) | 25000000 *----------------------------------------------------------------------------- * PLL_M | 25 *----------------------------------------------------------------------------- * PLL_N | 336 *----------------------------------------------------------------------------- * PLL_P | 4 *----------------------------------------------------------------------------- * PLL_Q | 7 *----------------------------------------------------------------------------- * PLLI2S_N | NA *----------------------------------------------------------------------------- * PLLI2S_R | NA *----------------------------------------------------------------------------- * I2S input clock | NA *----------------------------------------------------------------------------- * VDD(V) | 3.3 *----------------------------------------------------------------------------- * Main regulator output voltage | Scale1 mode *----------------------------------------------------------------------------- * Flash Latency(WS) | 2 *----------------------------------------------------------------------------- * Prefetch Buffer | ON *----------------------------------------------------------------------------- * Instruction cache | ON *----------------------------------------------------------------------------- * Data cache | ON *----------------------------------------------------------------------------- * Require 48MHz for USB OTG FS, | Disabled * SDIO and RNG clock | *----------------------------------------------------------------------------- *============================================================================= ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f4xx_system * @{ */ /** @addtogroup STM32F4xx_System_Private_Includes * @{ */ #include "stm32f4xx.h" /** * @} */ /** @addtogroup STM32F4xx_System_Private_TypesDefinitions * @{ */ /** * @} */ /** @addtogroup STM32F4xx_System_Private_Defines * @{ */ /************************* Miscellaneous Configuration ************************/ /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted on STM324xG_EVAL/STM324x7I_EVAL/STM324x9I_EVAL boards as data memory */ #if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) /* #define DATA_IN_ExtSRAM */ #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx */ #if defined (STM32F427_437xx) || defined (STM32F429_439xx) /* #define DATA_IN_ExtSDRAM */ #endif /* STM32F427_437x || STM32F429_439xx */ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ /******************************************************************************/ /************************* PLL Parameters *************************************/ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ #define PLL_M 25 /* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ #define PLL_Q 7 #if defined (STM32F40_41xxx) #define PLL_N 336 /* SYSCLK = PLL_VCO / PLL_P */ #define PLL_P 2 #endif /* STM32F40_41xxx */ #if defined (STM32F427_437xx) || defined (STM32F429_439xx) #define PLL_N 360 /* SYSCLK = PLL_VCO / PLL_P */ #define PLL_P 2 #endif /* STM32F427_437x || STM32F429_439xx */ #if defined (STM32F401xx) #define PLL_N 336 /* SYSCLK = PLL_VCO / PLL_P */ #define PLL_P 4 #endif /* STM32F401xx */ /******************************************************************************/ /** * @} */ /** @addtogroup STM32F4xx_System_Private_Macros * @{ */ /** * @} */ /** @addtogroup STM32F4xx_System_Private_Variables * @{ */ #if defined (STM32F40_41xxx) uint32_t SystemCoreClock = 168000000; #endif /* STM32F40_41xxx */ #if defined (STM32F427_437xx) || defined (STM32F429_439xx) uint32_t SystemCoreClock = 180000000; #endif /* STM32F427_437x || STM32F429_439xx */ #if defined (STM32F401xx) uint32_t SystemCoreClock = 84000000; #endif /* STM32F401xx */ __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; /** * @} */ /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes * @{ */ static void SetSysClock(void); #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) static void SystemInit_ExtMemCtl(void); #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ /** * @} */ /** @addtogroup STM32F4xx_System_Private_Functions * @{ */ /** * @brief Setup the microcontroller system * Initialize the Embedded Flash Interface, the PLL and update the * SystemFrequency variable. * @param None * @retval None */ void SystemInit(void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; /* Reset CFGR register */ RCC->CFGR = 0x00000000; /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFFF; /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x24003010; /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; /* Disable all interrupts */ RCC->CIR = 0x00000000; #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) SystemInit_ExtMemCtl(); #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ /* Configure the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings ----------------------------------*/ SetSysClock(); /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ #endif } /** * @brief Update SystemCoreClock variable according to Clock Register Values. * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration * based on this variable will be incorrect. * * @note - The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) * * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. * * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value * 16 MHz) but the real value may vary depending on the variations * in voltage and temperature. * * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value * 25 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. * * - The result of this function could be not correct when using fractional * value for HSE crystal. * * @param None * @retval None */ void SystemCoreClockUpdate(void) { uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { case 0x00: /* HSI used as system clock source */ SystemCoreClock = HSI_VALUE; break; case 0x04: /* HSE used as system clock source */ SystemCoreClock = HSE_VALUE; break; case 0x08: /* PLL used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N SYSCLK = PLL_VCO / PLL_P */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; if (pllsource != 0) { /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } else { /* HSI used as PLL clock source */ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; SystemCoreClock = pllvco/pllp; break; default: SystemCoreClock = HSI_VALUE; break; } /* Compute HCLK frequency --------------------------------------------------*/ /* Get HCLK prescaler */ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; /* HCLK frequency */ SystemCoreClock >>= tmp; } /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings * @Note This function should be called only once the RCC clock configuration * is reset to the default reset state (done in SystemInit() function). * @param None * @retval None */ static void SetSysClock(void) { /******************************************************************************/ /* PLL (clocked by HSE) used as System clock source */ /******************************************************************************/ __IO uint32_t StartUpCounter = 0, HSEStatus = 0; /* Enable HSE */ RCC->CR |= ((uint32_t)RCC_CR_HSEON); /* Wait till HSE is ready and if Time out is reached exit */ do { HSEStatus = RCC->CR & RCC_CR_HSERDY; StartUpCounter++; } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); if ((RCC->CR & RCC_CR_HSERDY) != RESET) { HSEStatus = (uint32_t)0x01; } else { HSEStatus = (uint32_t)0x00; } if (HSEStatus == (uint32_t)0x01) { /* Select regulator voltage output Scale 1 mode */ RCC->APB1ENR |= RCC_APB1ENR_PWREN; PWR->CR |= PWR_CR_VOS; /* HCLK = SYSCLK / 1*/ RCC->CFGR |= RCC_CFGR_HPRE_DIV1; #if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) /* PCLK2 = HCLK / 2*/ RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; /* PCLK1 = HCLK / 4*/ RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx */ #if defined (STM32F401xx) /* PCLK2 = HCLK / 2*/ RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; /* PCLK1 = HCLK / 4*/ RCC->CFGR |= RCC_CFGR_PPRE1_DIV2; #endif /* STM32F401xx */ /* Configure the main PLL */ RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); /* Enable the main PLL */ RCC->CR |= RCC_CR_PLLON; /* Wait till the main PLL is ready */ while((RCC->CR & RCC_CR_PLLRDY) == 0) { } #if defined (STM32F427_437xx) || defined (STM32F429_439xx) /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ PWR->CR |= PWR_CR_ODEN; while((PWR->CSR & PWR_CSR_ODRDY) == 0) { } PWR->CR |= PWR_CR_ODSWEN; while((PWR->CSR & PWR_CSR_ODSWRDY) == 0) { } /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; #endif /* STM32F427_437x || STM32F429_439xx */ #if defined (STM32F40_41xxx) /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; #endif /* STM32F40_41xxx */ #if defined (STM32F401xx) /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS; #endif /* STM32F401xx */ /* Select the main PLL as system clock source */ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= RCC_CFGR_SW_PLL; /* Wait till the main PLL is used as system clock source */ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ } } /** * @brief Setup the external memory controller. Called in startup_stm32f4xx.s * before jump to __main * @param None * @retval None */ #ifdef DATA_IN_ExtSRAM /** * @brief Setup the external memory controller. * Called in startup_stm32f4xx.s before jump to main. * This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I boards * This SRAM will be used as program data memory (including heap and stack). * @param None * @retval None */ void SystemInit_ExtMemCtl(void) { /*-- GPIOs Configuration -----------------------------------------------------*/ /* +-------------------+--------------------+------------------+--------------+ + SRAM pins assignment + +-------------------+--------------------+------------------+--------------+ | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 | | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 | | PD4 <-> FMC_NOE | PE3 <-> FMC_A19 | PF2 <-> FMC_A2 | PG2 <-> FMC_A12 | | PD5 <-> FMC_NWE | PE4 <-> FMC_A20 | PF3 <-> FMC_A3 | PG3 <-> FMC_A13 | | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF4 <-> FMC_A4 | PG4 <-> FMC_A14 | | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF5 <-> FMC_A5 | PG5 <-> FMC_A15 | | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 | | PD11 <-> FMC_A16 | PE10 <-> FMC_D7 | PF13 <-> FMC_A7 |-----------------+ | PD12 <-> FMC_A17 | PE11 <-> FMC_D8 | PF14 <-> FMC_A8 | | PD13 <-> FMC_A18 | PE12 <-> FMC_D9 | PF15 <-> FMC_A9 | | PD14 <-> FMC_D0 | PE13 <-> FMC_D10 |-----------------+ | PD15 <-> FMC_D1 | PE14 <-> FMC_D11 | | | PE15 <-> FMC_D12 | +------------------+------------------+ */ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ RCC->AHB1ENR |= 0x00000078; /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x00cc00cc; GPIOD->AFR[1] = 0xcccccccc; /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xaaaa0a0a; /* Configure PDx pins speed to 100 MHz */ GPIOD->OSPEEDR = 0xffff0f0f; /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xcccccccc; GPIOE->AFR[1] = 0xcccccccc; /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xaaaaaaaa; /* Configure PEx pins speed to 100 MHz */ GPIOE->OSPEEDR = 0xffffffff; /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0x00cccccc; GPIOF->AFR[1] = 0xcccc0000; /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xaa000aaa; /* Configure PFx pins speed to 100 MHz */ GPIOF->OSPEEDR = 0xff000fff; /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0x00cccccc; GPIOG->AFR[1] = 0x000000c0; /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0x00080aaa; /* Configure PGx pins speed to 100 MHz */ GPIOG->OSPEEDR = 0x000c0fff; /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; /*-- FMC Configuration ------------------------------------------------------*/ /* Enable the FMC/FSMC interface clock */ RCC->AHB3ENR |= 0x00000001; #if defined (STM32F427_437xx) || defined (STM32F429_439xx) /* Configure and enable Bank1_SRAM2 */ FMC_Bank1->BTCR[2] = 0x00001011; FMC_Bank1->BTCR[3] = 0x00000201; FMC_Bank1E->BWTR[2] = 0x0fffffff; #endif /* STM32F427_437xx || STM32F429_439xx */ #if defined (STM32F40_41xxx) /* Configure and enable Bank1_SRAM2 */ FSMC_Bank1->BTCR[2] = 0x00001011; FSMC_Bank1->BTCR[3] = 0x00000201; FSMC_Bank1E->BWTR[2] = 0x0fffffff; #endif /* STM32F40_41xxx */ /* Bank1_SRAM2 is configured as follow: In case of FSMC configuration NORSRAMTimingStructure.FSMC_AddressSetupTime = 1; NORSRAMTimingStructure.FSMC_AddressHoldTime = 0; NORSRAMTimingStructure.FSMC_DataSetupTime = 2; NORSRAMTimingStructure.FSMC_BusTurnAroundDuration = 0; NORSRAMTimingStructure.FSMC_CLKDivision = 0; NORSRAMTimingStructure.FSMC_DataLatency = 0; NORSRAMTimingStructure.FSMC_AccessMode = FMC_AccessMode_A; FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &NORSRAMTimingStructure; FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &NORSRAMTimingStructure; In case of FMC configuration NORSRAMTimingStructure.FMC_AddressSetupTime = 1; NORSRAMTimingStructure.FMC_AddressHoldTime = 0; NORSRAMTimingStructure.FMC_DataSetupTime = 2; NORSRAMTimingStructure.FMC_BusTurnAroundDuration = 0; NORSRAMTimingStructure.FMC_CLKDivision = 0; NORSRAMTimingStructure.FMC_DataLatency = 0; NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A; FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2; FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable; FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM; FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b; FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable; FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable; FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low; FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable; FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState; FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable; FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable; FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable; FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable; FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly; FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure; FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure; */ } #endif /* DATA_IN_ExtSRAM */ #ifdef DATA_IN_ExtSDRAM /** * @brief Setup the external memory controller. * Called in startup_stm32f4xx.s before jump to main. * This function configures the external SDRAM mounted on STM324x9I_EVAL board * This SDRAM will be used as program data memory (including heap and stack). * @param None * @retval None */ void SystemInit_ExtMemCtl(void) { register uint32_t tmpreg = 0, timeout = 0xFFFF; register uint32_t index; /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ RCC->AHB1ENR |= 0x000001FC; /* Connect PCx pins to FMC Alternate function */ GPIOC->AFR[0] = 0x0000000c; GPIOC->AFR[1] = 0x00007700; /* Configure PCx pins in Alternate function mode */ GPIOC->MODER = 0x00a00002; /* Configure PCx pins speed to 50 MHz */ GPIOC->OSPEEDR = 0x00a00002; /* Configure PCx pins Output type to push-pull */ GPIOC->OTYPER = 0x00000000; /* No pull-up, pull-down for PCx pins */ GPIOC->PUPDR = 0x00500000; /* Connect PDx pins to FMC Alternate function */ GPIOD->AFR[0] = 0x000000CC; GPIOD->AFR[1] = 0xCC000CCC; /* Configure PDx pins in Alternate function mode */ GPIOD->MODER = 0xA02A000A; /* Configure PDx pins speed to 50 MHz */ GPIOD->OSPEEDR = 0xA02A000A; /* Configure PDx pins Output type to push-pull */ GPIOD->OTYPER = 0x00000000; /* No pull-up, pull-down for PDx pins */ GPIOD->PUPDR = 0x00000000; /* Connect PEx pins to FMC Alternate function */ GPIOE->AFR[0] = 0xC00000CC; GPIOE->AFR[1] = 0xCCCCCCCC; /* Configure PEx pins in Alternate function mode */ GPIOE->MODER = 0xAAAA800A; /* Configure PEx pins speed to 50 MHz */ GPIOE->OSPEEDR = 0xAAAA800A; /* Configure PEx pins Output type to push-pull */ GPIOE->OTYPER = 0x00000000; /* No pull-up, pull-down for PEx pins */ GPIOE->PUPDR = 0x00000000; /* Connect PFx pins to FMC Alternate function */ GPIOF->AFR[0] = 0xcccccccc; GPIOF->AFR[1] = 0xcccccccc; /* Configure PFx pins in Alternate function mode */ GPIOF->MODER = 0xAA800AAA; /* Configure PFx pins speed to 50 MHz */ GPIOF->OSPEEDR = 0xAA800AAA; /* Configure PFx pins Output type to push-pull */ GPIOF->OTYPER = 0x00000000; /* No pull-up, pull-down for PFx pins */ GPIOF->PUPDR = 0x00000000; /* Connect PGx pins to FMC Alternate function */ GPIOG->AFR[0] = 0xcccccccc; GPIOG->AFR[1] = 0xcccccccc; /* Configure PGx pins in Alternate function mode */ GPIOG->MODER = 0xaaaaaaaa; /* Configure PGx pins speed to 50 MHz */ GPIOG->OSPEEDR = 0xaaaaaaaa; /* Configure PGx pins Output type to push-pull */ GPIOG->OTYPER = 0x00000000; /* No pull-up, pull-down for PGx pins */ GPIOG->PUPDR = 0x00000000; /* Connect PHx pins to FMC Alternate function */ GPIOH->AFR[0] = 0x00C0CC00; GPIOH->AFR[1] = 0xCCCCCCCC; /* Configure PHx pins in Alternate function mode */ GPIOH->MODER = 0xAAAA08A0; /* Configure PHx pins speed to 50 MHz */ GPIOH->OSPEEDR = 0xAAAA08A0; /* Configure PHx pins Output type to push-pull */ GPIOH->OTYPER = 0x00000000; /* No pull-up, pull-down for PHx pins */ GPIOH->PUPDR = 0x00000000; /* Connect PIx pins to FMC Alternate function */ GPIOI->AFR[0] = 0xCCCCCCCC; GPIOI->AFR[1] = 0x00000CC0; /* Configure PIx pins in Alternate function mode */ GPIOI->MODER = 0x0028AAAA; /* Configure PIx pins speed to 50 MHz */ GPIOI->OSPEEDR = 0x0028AAAA; /* Configure PIx pins Output type to push-pull */ GPIOI->OTYPER = 0x00000000; /* No pull-up, pull-down for PIx pins */ GPIOI->PUPDR = 0x00000000; /*-- FMC Configuration ------------------------------------------------------*/ /* Enable the FMC interface clock */ RCC->AHB3ENR |= 0x00000001; /* Configure and enable SDRAM bank1 */ FMC_Bank5_6->SDCR[0] = 0x000039D0; FMC_Bank5_6->SDTR[0] = 0x01115351; /* SDRAM initialization sequence */ /* Clock enable command */ FMC_Bank5_6->SDCMR = 0x00000011; tmpreg = FMC_Bank5_6->SDSR & 0x00000020; while((tmpreg != 0) & (timeout-- > 0)) { tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* Delay */ for (index = 0; index<1000; index++); /* PALL command */ FMC_Bank5_6->SDCMR = 0x00000012; timeout = 0xFFFF; while((tmpreg != 0) & (timeout-- > 0)) { tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* Auto refresh command */ FMC_Bank5_6->SDCMR = 0x00000073; timeout = 0xFFFF; while((tmpreg != 0) & (timeout-- > 0)) { tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* MRD register program */ FMC_Bank5_6->SDCMR = 0x00046014; timeout = 0xFFFF; while((tmpreg != 0) & (timeout-- > 0)) { tmpreg = FMC_Bank5_6->SDSR & 0x00000020; } /* Set refresh count */ tmpreg = FMC_Bank5_6->SDRTR; FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); /* Disable write protection */ tmpreg = FMC_Bank5_6->SDCR[0]; FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); /* Bank1_SDRAM is configured as follow: FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2; FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6; FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4; FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6; FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2; FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2; FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2; FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK; FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b; FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b; FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4; FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3; FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable; FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2; FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable; FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1; FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure; */ } #endif /* DATA_IN_ExtSDRAM */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/CMSIS/Include/arm_common_tables.h ================================================ /* ---------------------------------------------------------------------- * Copyright (C) 2010-2013 ARM Limited. All rights reserved. * * $Date: 17. January 2013 * $Revision: V1.4.1 * * Project: CMSIS DSP Library * Title: arm_common_tables.h * * Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions * * Target Processor: Cortex-M4/Cortex-M3 * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * - Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * - Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * - Neither the name of ARM LIMITED nor the names of its contributors * may be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * -------------------------------------------------------------------- */ #ifndef _ARM_COMMON_TABLES_H #define _ARM_COMMON_TABLES_H #include "arm_math.h" extern const uint16_t armBitRevTable[1024]; extern const q15_t armRecipTableQ15[64]; extern const q31_t armRecipTableQ31[64]; extern const q31_t realCoefAQ31[1024]; extern const q31_t realCoefBQ31[1024]; extern const float32_t twiddleCoef_16[32]; extern const float32_t twiddleCoef_32[64]; extern const float32_t twiddleCoef_64[128]; extern const float32_t twiddleCoef_128[256]; extern const float32_t twiddleCoef_256[512]; extern const float32_t twiddleCoef_512[1024]; extern const float32_t twiddleCoef_1024[2048]; extern const float32_t twiddleCoef_2048[4096]; extern const float32_t twiddleCoef_4096[8192]; #define twiddleCoef twiddleCoef_4096 extern const q31_t twiddleCoefQ31[6144]; extern const q15_t twiddleCoefQ15[6144]; extern const float32_t twiddleCoef_rfft_32[32]; extern const float32_t twiddleCoef_rfft_64[64]; extern const float32_t twiddleCoef_rfft_128[128]; extern const float32_t twiddleCoef_rfft_256[256]; extern const float32_t twiddleCoef_rfft_512[512]; extern const float32_t twiddleCoef_rfft_1024[1024]; extern const float32_t twiddleCoef_rfft_2048[2048]; extern const float32_t twiddleCoef_rfft_4096[4096]; #define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) #define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) #define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) #define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) #define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) #define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; #endif /* ARM_COMMON_TABLES_H */ ================================================ FILE: Libraries/CMSIS/Include/arm_const_structs.h ================================================ /* ---------------------------------------------------------------------- * Copyright (C) 2010-2013 ARM Limited. All rights reserved. * * $Date: 17. January 2013 * $Revision: V1.4.1 * * Project: CMSIS DSP Library * Title: arm_const_structs.h * * Description: This file has constant structs that are initialized for * user convenience. For example, some can be given as * arguments to the arm_cfft_f32() function. * * Target Processor: Cortex-M4/Cortex-M3 * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * - Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * - Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * - Neither the name of ARM LIMITED nor the names of its contributors * may be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * -------------------------------------------------------------------- */ #ifndef _ARM_CONST_STRUCTS_H #define _ARM_CONST_STRUCTS_H #include "arm_math.h" #include "arm_common_tables.h" const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = { 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH }; const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = { 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH }; const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = { 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH }; const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = { 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH }; const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = { 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH }; const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = { 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH }; const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = { 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH }; const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = { 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH }; const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = { 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH }; #endif ================================================ FILE: Libraries/CMSIS/Include/arm_math.h ================================================ /* ---------------------------------------------------------------------- * Copyright (C) 2010-2013 ARM Limited. All rights reserved. * * $Date: 17. January 2013 * $Revision: V1.4.1 * * Project: CMSIS DSP Library * Title: arm_math.h * * Description: Public header file for CMSIS DSP Library * * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * - Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * - Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * - Neither the name of ARM LIMITED nor the names of its contributors * may be used to endorse or promote products derived from this * software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * -------------------------------------------------------------------- */ /** \mainpage CMSIS DSP Software Library * * Introduction * * This user manual describes the CMSIS DSP software library, * a suite of common signal processing functions for use on Cortex-M processor based devices. * * The library is divided into a number of functions each covering a specific category: * - Basic math functions * - Fast math functions * - Complex math functions * - Filters * - Matrix functions * - Transforms * - Motor control functions * - Statistical functions * - Support functions * - Interpolation functions * * The library has separate functions for operating on 8-bit integers, 16-bit integers, * 32-bit integer and 32-bit floating-point values. * * Using the Library * * The library installer contains prebuilt versions of the libraries in the Lib folder. * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) * * The library functions are declared in the public file arm_math.h which is placed in the Include folder. * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. * * Examples * * The library ships with a number of examples which demonstrate how to use the library functions. * * Toolchain Support * * The library has been developed and tested with MDK-ARM version 4.60. * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. * * Building the Library * * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. * - arm_cortexM0b_math.uvproj * - arm_cortexM0l_math.uvproj * - arm_cortexM3b_math.uvproj * - arm_cortexM3l_math.uvproj * - arm_cortexM4b_math.uvproj * - arm_cortexM4l_math.uvproj * - arm_cortexM4bf_math.uvproj * - arm_cortexM4lf_math.uvproj * * * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above. * * Pre-processor Macros * * Each library project have differant pre-processor macros. * * - UNALIGNED_SUPPORT_DISABLE: * * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access * * - ARM_MATH_BIG_ENDIAN: * * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. * * - ARM_MATH_MATRIX_CHECK: * * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices * * - ARM_MATH_ROUNDING: * * Define macro ARM_MATH_ROUNDING for rounding on support functions * * - ARM_MATH_CMx: * * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. * * - __FPU_PRESENT: * * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries * * Copyright Notice * * Copyright (C) 2010-2013 ARM Limited. All rights reserved. */ /** * @defgroup groupMath Basic Math Functions */ /** * @defgroup groupFastMath Fast Math Functions * This set of functions provides a fast approximation to sine, cosine, and square root. * As compared to most of the other functions in the CMSIS math library, the fast math functions * operate on individual values and not arrays. * There are separate functions for Q15, Q31, and floating-point data. * */ /** * @defgroup groupCmplxMath Complex Math Functions * This set of functions operates on complex data vectors. * The data in the complex arrays is stored in an interleaved fashion * (real, imag, real, imag, ...). * In the API functions, the number of samples in a complex array refers * to the number of complex values; the array contains twice this number of * real values. */ /** * @defgroup groupFilters Filtering Functions */ /** * @defgroup groupMatrix Matrix Functions * * This set of functions provides basic matrix math operations. * The functions operate on matrix data structures. For example, * the type * definition for the floating-point matrix structure is shown * below: * 
 *     typedef struct
 *     {
 *       uint16_t numRows;     // number of rows of the matrix.
 *       uint16_t numCols;     // number of columns of the matrix.
 *       float32_t *pData;     // points to the data of the matrix.
 *     } arm_matrix_instance_f32;
 *
* There are similar definitions for Q15 and Q31 data types. * * The structure specifies the size of the matrix and then points to * an array of data. The array is of size numRows X numCols * and the values are arranged in row order. That is, the * matrix element (i, j) is stored at: * 
 *     pData[i*numCols + j]
 *
* * \par Init Functions * There is an associated initialization function for each type of matrix * data structure. * The initialization function sets the values of the internal structure fields. * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. * * \par * Use of the initialization function is optional. However, if initialization function is used * then the instance structure cannot be placed into a const data section. * To place the instance structure in a const data * section, manually initialize the data structure. For example: * 
 * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
 * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
 * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
 *
* where nRows specifies the number of rows, nColumns * specifies the number of columns, and pData points to the * data array. * * \par Size Checking * By default all of the matrix functions perform size checking on the input and * output matrices. For example, the matrix addition function verifies that the * two input matrices and the output matrix all have the same number of rows and * columns. If the size check fails the functions return: * 
 *     ARM_MATH_SIZE_MISMATCH
 *
* Otherwise the functions return * 
 *     ARM_MATH_SUCCESS
 *
* There is some overhead associated with this matrix size checking. * The matrix size checking is enabled via the \#define * 
 *     ARM_MATH_MATRIX_CHECK
 *
* within the library project settings. By default this macro is defined * and size checking is enabled. By changing the project settings and * undefining this macro size checking is eliminated and the functions * run a bit faster. With size checking disabled the functions always * return ARM_MATH_SUCCESS. */ /** * @defgroup groupTransforms Transform Functions */ /** * @defgroup groupController Controller Functions */ /** * @defgroup groupStats Statistics Functions */ /** * @defgroup groupSupport Support Functions */ /** * @defgroup groupInterpolation Interpolation Functions * These functions perform 1- and 2-dimensional interpolation of data. * Linear interpolation is used for 1-dimensional data and * bilinear interpolation is used for 2-dimensional data. */ /** * @defgroup groupExamples Examples */ #ifndef _ARM_MATH_H #define _ARM_MATH_H #define __CMSIS_GENERIC /* disable NVIC and Systick functions */ #if defined (ARM_MATH_CM4) #include "core_cm4.h" #elif defined (ARM_MATH_CM3) #include "core_cm3.h" #elif defined (ARM_MATH_CM0) #include "core_cm0.h" #define ARM_MATH_CM0_FAMILY #elif defined (ARM_MATH_CM0PLUS) #include "core_cm0plus.h" #define ARM_MATH_CM0_FAMILY #else #include "ARMCM4.h" #warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." #endif #undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ #include "string.h" #include "math.h" #ifdef __cplusplus extern "C" { #endif /** * @brief Macros required for reciprocal calculation in Normalized LMS */ #define DELTA_Q31 (0x100) #define DELTA_Q15 0x5 #define INDEX_MASK 0x0000003F #ifndef PI #define PI 3.14159265358979f #endif /** * @brief Macros required for SINE and COSINE Fast math approximations */ #define TABLE_SIZE 256 #define TABLE_SPACING_Q31 0x800000 #define TABLE_SPACING_Q15 0x80 /** * @brief Macros required for SINE and COSINE Controller functions */ /* 1.31(q31) Fixed value of 2/360 */ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ #define INPUT_SPACING 0xB60B61 /** * @brief Macro for Unaligned Support */ #ifndef UNALIGNED_SUPPORT_DISABLE #define ALIGN4 #else #if defined (__GNUC__) #define ALIGN4 __attribute__((aligned(4))) #else #define ALIGN4 __align(4) #endif #endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ /** * @brief Error status returned by some functions in the library. */ typedef enum { ARM_MATH_SUCCESS = 0, /**< No error */ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ } arm_status; /** * @brief 8-bit fractional data type in 1.7 format. */ typedef int8_t q7_t; /** * @brief 16-bit fractional data type in 1.15 format. */ typedef int16_t q15_t; /** * @brief 32-bit fractional data type in 1.31 format. */ typedef int32_t q31_t; /** * @brief 64-bit fractional data type in 1.63 format. */ typedef int64_t q63_t; /** * @brief 32-bit floating-point type definition. */ typedef float float32_t; /** * @brief 64-bit floating-point type definition. */ typedef double float64_t; /** * @brief definition to read/write two 16 bit values. */ #if defined __CC_ARM #define __SIMD32_TYPE int32_t __packed #define CMSIS_UNUSED __attribute__((unused)) #elif defined __ICCARM__ #define CMSIS_UNUSED #define __SIMD32_TYPE int32_t __packed #elif defined __GNUC__ #define __SIMD32_TYPE int32_t #define CMSIS_UNUSED __attribute__((unused)) #else #error Unknown compiler #endif #define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) #define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) #define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) #define __SIMD64(addr) (*(int64_t **) & (addr)) #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) /** * @brief definition to pack two 16 bit values. */ #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) #endif /** * @brief definition to pack four 8 bit values. */ #ifndef ARM_MATH_BIG_ENDIAN #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) #else #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) #endif /** * @brief Clips Q63 to Q31 values. */ static __INLINE q31_t clip_q63_to_q31( q63_t x) { return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; } /** * @brief Clips Q63 to Q15 values. */ static __INLINE q15_t clip_q63_to_q15( q63_t x) { return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); } /** * @brief Clips Q31 to Q7 values. */ static __INLINE q7_t clip_q31_to_q7( q31_t x) { return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; } /** * @brief Clips Q31 to Q15 values. */ static __INLINE q15_t clip_q31_to_q15( q31_t x) { return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; } /** * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. */ static __INLINE q63_t mult32x64( q63_t x, q31_t y) { return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + (((q63_t) (x >> 32) * y))); } #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) #define __CLZ __clz #endif #if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) static __INLINE uint32_t __CLZ( q31_t data); static __INLINE uint32_t __CLZ( q31_t data) { uint32_t count = 0; uint32_t mask = 0x80000000; while((data & mask) == 0) { count += 1u; mask = mask >> 1u; } return (count); } #endif /** * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. */ static __INLINE uint32_t arm_recip_q31( q31_t in, q31_t * dst, q31_t * pRecipTable) { uint32_t out, tempVal; uint32_t index, i; uint32_t signBits; if(in > 0) { signBits = __CLZ(in) - 1; } else { signBits = __CLZ(-in) - 1; } /* Convert input sample to 1.31 format */ in = in << signBits; /* calculation of index for initial approximated Val */ index = (uint32_t) (in >> 24u); index = (index & INDEX_MASK); /* 1.31 with exp 1 */ out = pRecipTable[index]; /* calculation of reciprocal value */ /* running approximation for two iterations */ for (i = 0u; i < 2u; i++) { tempVal = (q31_t) (((q63_t) in * out) >> 31u); tempVal = 0x7FFFFFFF - tempVal; /* 1.31 with exp 1 */ //out = (q31_t) (((q63_t) out * tempVal) >> 30u); out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); } /* write output */ *dst = out; /* return num of signbits of out = 1/in value */ return (signBits + 1u); } /** * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. */ static __INLINE uint32_t arm_recip_q15( q15_t in, q15_t * dst, q15_t * pRecipTable) { uint32_t out = 0, tempVal = 0; uint32_t index = 0, i = 0; uint32_t signBits = 0; if(in > 0) { signBits = __CLZ(in) - 17; } else { signBits = __CLZ(-in) - 17; } /* Convert input sample to 1.15 format */ in = in << signBits; /* calculation of index for initial approximated Val */ index = in >> 8; index = (index & INDEX_MASK); /* 1.15 with exp 1 */ out = pRecipTable[index]; /* calculation of reciprocal value */ /* running approximation for two iterations */ for (i = 0; i < 2; i++) { tempVal = (q15_t) (((q31_t) in * out) >> 15); tempVal = 0x7FFF - tempVal; /* 1.15 with exp 1 */ out = (q15_t) (((q31_t) out * tempVal) >> 14); } /* write output */ *dst = out; /* return num of signbits of out = 1/in value */ return (signBits + 1); } /* * @brief C custom defined intrinisic function for only M0 processors */ #if defined(ARM_MATH_CM0_FAMILY) static __INLINE q31_t __SSAT( q31_t x, uint32_t y) { int32_t posMax, negMin; uint32_t i; posMax = 1; for (i = 0; i < (y - 1); i++) { posMax = posMax * 2; } if(x > 0) { posMax = (posMax - 1); if(x > posMax) { x = posMax; } } else { negMin = -posMax; if(x < negMin) { x = negMin; } } return (x); } #endif /* end of ARM_MATH_CM0_FAMILY */ /* * @brief C custom defined intrinsic function for M3 and M0 processors */ #if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) /* * @brief C custom defined QADD8 for M3 and M0 processors */ static __INLINE q31_t __QADD8( q31_t x, q31_t y) { q31_t sum; q7_t r, s, t, u; r = (q7_t) x; s = (q7_t) y; r = __SSAT((q31_t) (r + s), 8); s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); return sum; } /* * @brief C custom defined QSUB8 for M3 and M0 processors */ static __INLINE q31_t __QSUB8( q31_t x, q31_t y) { q31_t sum; q31_t r, s, t, u; r = (q7_t) x; s = (q7_t) y; r = __SSAT((r - s), 8); s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; sum = (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF); return sum; } /* * @brief C custom defined QADD16 for M3 and M0 processors */ /* * @brief C custom defined QADD16 for M3 and M0 processors */ static __INLINE q31_t __QADD16( q31_t x, q31_t y) { q31_t sum; q31_t r, s; r = (short) x; s = (short) y; r = __SSAT(r + s, 16); s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); return sum; } /* * @brief C custom defined SHADD16 for M3 and M0 processors */ static __INLINE q31_t __SHADD16( q31_t x, q31_t y) { q31_t sum; q31_t r, s; r = (short) x; s = (short) y; r = ((r >> 1) + (s >> 1)); s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); return sum; } /* * @brief C custom defined QSUB16 for M3 and M0 processors */ static __INLINE q31_t __QSUB16( q31_t x, q31_t y) { q31_t sum; q31_t r, s; r = (short) x; s = (short) y; r = __SSAT(r - s, 16); s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); return sum; } /* * @brief C custom defined SHSUB16 for M3 and M0 processors */ static __INLINE q31_t __SHSUB16( q31_t x, q31_t y) { q31_t diff; q31_t r, s; r = (short) x; s = (short) y; r = ((r >> 1) - (s >> 1)); s = (((x >> 17) - (y >> 17)) << 16); diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); return diff; } /* * @brief C custom defined QASX for M3 and M0 processors */ static __INLINE q31_t __QASX( q31_t x, q31_t y) { q31_t sum = 0; sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); return sum; } /* * @brief C custom defined SHASX for M3 and M0 processors */ static __INLINE q31_t __SHASX( q31_t x, q31_t y) { q31_t sum; q31_t r, s; r = (short) x; s = (short) y; r = ((r >> 1) - (y >> 17)); s = (((x >> 17) + (s >> 1)) << 16); sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); return sum; } /* * @brief C custom defined QSAX for M3 and M0 processors */ static __INLINE q31_t __QSAX( q31_t x, q31_t y) { q31_t sum = 0; sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); return sum; } /* * @brief C custom defined SHSAX for M3 and M0 processors */ static __INLINE q31_t __SHSAX( q31_t x, q31_t y) { q31_t sum; q31_t r, s; r = (short) x; s = (short) y; r = ((r >> 1) + (y >> 17)); s = (((x >> 17) - (s >> 1)) << 16); sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); return sum; } /* * @brief C custom defined SMUSDX for M3 and M0 processors */ static __INLINE q31_t __SMUSDX( q31_t x, q31_t y) { return ((q31_t) (((short) x * (short) (y >> 16)) - ((short) (x >> 16) * (short) y))); } /* * @brief C custom defined SMUADX for M3 and M0 processors */ static __INLINE q31_t __SMUADX( q31_t x, q31_t y) { return ((q31_t) (((short) x * (short) (y >> 16)) + ((short) (x >> 16) * (short) y))); } /* * @brief C custom defined QADD for M3 and M0 processors */ static __INLINE q31_t __QADD( q31_t x, q31_t y) { return clip_q63_to_q31((q63_t) x + y); } /* * @brief C custom defined QSUB for M3 and M0 processors */ static __INLINE q31_t __QSUB( q31_t x, q31_t y) { return clip_q63_to_q31((q63_t) x - y); } /* * @brief C custom defined SMLAD for M3 and M0 processors */ static __INLINE q31_t __SMLAD( q31_t x, q31_t y, q31_t sum) { return (sum + ((short) (x >> 16) * (short) (y >> 16)) + ((short) x * (short) y)); } /* * @brief C custom defined SMLADX for M3 and M0 processors */ static __INLINE q31_t __SMLADX( q31_t x, q31_t y, q31_t sum) { return (sum + ((short) (x >> 16) * (short) (y)) + ((short) x * (short) (y >> 16))); } /* * @brief C custom defined SMLSDX for M3 and M0 processors */ static __INLINE q31_t __SMLSDX( q31_t x, q31_t y, q31_t sum) { return (sum - ((short) (x >> 16) * (short) (y)) + ((short) x * (short) (y >> 16))); } /* * @brief C custom defined SMLALD for M3 and M0 processors */ static __INLINE q63_t __SMLALD( q31_t x, q31_t y, q63_t sum) { return (sum + ((short) (x >> 16) * (short) (y >> 16)) + ((short) x * (short) y)); } /* * @brief C custom defined SMLALDX for M3 and M0 processors */ static __INLINE q63_t __SMLALDX( q31_t x, q31_t y, q63_t sum) { return (sum + ((short) (x >> 16) * (short) y)) + ((short) x * (short) (y >> 16)); } /* * @brief C custom defined SMUAD for M3 and M0 processors */ static __INLINE q31_t __SMUAD( q31_t x, q31_t y) { return (((x >> 16) * (y >> 16)) + (((x << 16) >> 16) * ((y << 16) >> 16))); } /* * @brief C custom defined SMUSD for M3 and M0 processors */ static __INLINE q31_t __SMUSD( q31_t x, q31_t y) { return (-((x >> 16) * (y >> 16)) + (((x << 16) >> 16) * ((y << 16) >> 16))); } /* * @brief C custom defined SXTB16 for M3 and M0 processors */ static __INLINE q31_t __SXTB16( q31_t x) { return ((((x << 24) >> 24) & 0x0000FFFF) | (((x << 8) >> 8) & 0xFFFF0000)); } #endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ /** * @brief Instance structure for the Q7 FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ } arm_fir_instance_q7; /** * @brief Instance structure for the Q15 FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ } arm_fir_instance_q15; /** * @brief Instance structure for the Q31 FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ } arm_fir_instance_q31; /** * @brief Instance structure for the floating-point FIR filter. */ typedef struct { uint16_t numTaps; /**< number of filter coefficients in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ } arm_fir_instance_f32; /** * @brief Processing function for the Q7 FIR filter. * @param[in] *S points to an instance of the Q7 FIR filter structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_fir_q7( const arm_fir_instance_q7 * S, q7_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q7 FIR filter. * @param[in,out] *S points to an instance of the Q7 FIR structure. * @param[in] numTaps Number of filter coefficients in the filter. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of samples that are processed. * @return none */ void arm_fir_init_q7( arm_fir_instance_q7 * S, uint16_t numTaps, q7_t * pCoeffs, q7_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q15 FIR filter. * @param[in] *S points to an instance of the Q15 FIR structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_fir_q15( const arm_fir_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q15 FIR filter structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_fir_fast_q15( const arm_fir_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 FIR filter. * @param[in,out] *S points to an instance of the Q15 FIR filter structure. * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if * numTaps is not a supported value. */ arm_status arm_fir_init_q15( arm_fir_instance_q15 * S, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR filter. * @param[in] *S points to an instance of the Q31 FIR filter structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_fir_q31( const arm_fir_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q31 FIR structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_fir_fast_q31( const arm_fir_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR filter. * @param[in,out] *S points to an instance of the Q31 FIR structure. * @param[in] numTaps Number of filter coefficients in the filter. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. * @return none. */ void arm_fir_init_q31( arm_fir_instance_q31 * S, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, uint32_t blockSize); /** * @brief Processing function for the floating-point FIR filter. * @param[in] *S points to an instance of the floating-point FIR structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_fir_f32( const arm_fir_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR filter. * @param[in,out] *S points to an instance of the floating-point FIR filter structure. * @param[in] numTaps Number of filter coefficients in the filter. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of samples that are processed at a time. * @return none. */ void arm_fir_init_f32( arm_fir_instance_f32 * S, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, uint32_t blockSize); /** * @brief Instance structure for the Q15 Biquad cascade filter. */ typedef struct { int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ } arm_biquad_casd_df1_inst_q15; /** * @brief Instance structure for the Q31 Biquad cascade filter. */ typedef struct { uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ } arm_biquad_casd_df1_inst_q31; /** * @brief Instance structure for the floating-point Biquad cascade filter. */ typedef struct { uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_casd_df1_inst_f32; /** * @brief Processing function for the Q15 Biquad cascade filter. * @param[in] *S points to an instance of the Q15 Biquad cascade structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_biquad_cascade_df1_q15( const arm_biquad_casd_df1_inst_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 Biquad cascade filter. * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format * @return none */ void arm_biquad_cascade_df1_init_q15( arm_biquad_casd_df1_inst_q15 * S, uint8_t numStages, q15_t * pCoeffs, q15_t * pState, int8_t postShift); /** * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q15 Biquad cascade structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_biquad_cascade_df1_fast_q15( const arm_biquad_casd_df1_inst_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Processing function for the Q31 Biquad cascade filter * @param[in] *S points to an instance of the Q31 Biquad cascade structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_biquad_cascade_df1_q31( const arm_biquad_casd_df1_inst_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q31 Biquad cascade structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_biquad_cascade_df1_fast_q31( const arm_biquad_casd_df1_inst_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 Biquad cascade filter. * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format * @return none */ void arm_biquad_cascade_df1_init_q31( arm_biquad_casd_df1_inst_q31 * S, uint8_t numStages, q31_t * pCoeffs, q31_t * pState, int8_t postShift); /** * @brief Processing function for the floating-point Biquad cascade filter. * @param[in] *S points to an instance of the floating-point Biquad cascade structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_biquad_cascade_df1_f32( const arm_biquad_casd_df1_inst_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point Biquad cascade filter. * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @return none */ void arm_biquad_cascade_df1_init_f32( arm_biquad_casd_df1_inst_f32 * S, uint8_t numStages, float32_t * pCoeffs, float32_t * pState); /** * @brief Instance structure for the floating-point matrix structure. */ typedef struct { uint16_t numRows; /**< number of rows of the matrix. */ uint16_t numCols; /**< number of columns of the matrix. */ float32_t *pData; /**< points to the data of the matrix. */ } arm_matrix_instance_f32; /** * @brief Instance structure for the Q15 matrix structure. */ typedef struct { uint16_t numRows; /**< number of rows of the matrix. */ uint16_t numCols; /**< number of columns of the matrix. */ q15_t *pData; /**< points to the data of the matrix. */ } arm_matrix_instance_q15; /** * @brief Instance structure for the Q31 matrix structure. */ typedef struct { uint16_t numRows; /**< number of rows of the matrix. */ uint16_t numCols; /**< number of columns of the matrix. */ q31_t *pData; /**< points to the data of the matrix. */ } arm_matrix_instance_q31; /** * @brief Floating-point matrix addition. * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_add_f32( const arm_matrix_instance_f32 * pSrcA, const arm_matrix_instance_f32 * pSrcB, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix addition. * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_add_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix addition. * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_add_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix transpose. * @param[in] *pSrc points to the input matrix * @param[out] *pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_trans_f32( const arm_matrix_instance_f32 * pSrc, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix transpose. * @param[in] *pSrc points to the input matrix * @param[out] *pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_trans_q15( const arm_matrix_instance_q15 * pSrc, arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix transpose. * @param[in] *pSrc points to the input matrix * @param[out] *pDst points to the output matrix * @return The function returns either ARM_MATH_SIZE_MISMATCH * or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_trans_q31( const arm_matrix_instance_q31 * pSrc, arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix multiplication * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_f32( const arm_matrix_instance_f32 * pSrcA, const arm_matrix_instance_f32 * pSrcB, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix multiplication * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @param[in] *pState points to the array for storing intermediate results * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, arm_matrix_instance_q15 * pDst, q15_t * pState); /** * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @param[in] *pState points to the array for storing intermediate results * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_fast_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, arm_matrix_instance_q15 * pDst, q15_t * pState); /** * @brief Q31 matrix multiplication * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, arm_matrix_instance_q31 * pDst); /** * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_mult_fast_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix subtraction * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_sub_f32( const arm_matrix_instance_f32 * pSrcA, const arm_matrix_instance_f32 * pSrcB, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix subtraction * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_sub_q15( const arm_matrix_instance_q15 * pSrcA, const arm_matrix_instance_q15 * pSrcB, arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix subtraction * @param[in] *pSrcA points to the first input matrix structure * @param[in] *pSrcB points to the second input matrix structure * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_sub_q31( const arm_matrix_instance_q31 * pSrcA, const arm_matrix_instance_q31 * pSrcB, arm_matrix_instance_q31 * pDst); /** * @brief Floating-point matrix scaling. * @param[in] *pSrc points to the input matrix * @param[in] scale scale factor * @param[out] *pDst points to the output matrix * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_scale_f32( const arm_matrix_instance_f32 * pSrc, float32_t scale, arm_matrix_instance_f32 * pDst); /** * @brief Q15 matrix scaling. * @param[in] *pSrc points to input matrix * @param[in] scaleFract fractional portion of the scale factor * @param[in] shift number of bits to shift the result by * @param[out] *pDst points to output matrix * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_scale_q15( const arm_matrix_instance_q15 * pSrc, q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 * pDst); /** * @brief Q31 matrix scaling. * @param[in] *pSrc points to input matrix * @param[in] scaleFract fractional portion of the scale factor * @param[in] shift number of bits to shift the result by * @param[out] *pDst points to output matrix structure * @return The function returns either * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. */ arm_status arm_mat_scale_q31( const arm_matrix_instance_q31 * pSrc, q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 * pDst); /** * @brief Q31 matrix initialization. * @param[in,out] *S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] *pData points to the matrix data array. * @return none */ void arm_mat_init_q31( arm_matrix_instance_q31 * S, uint16_t nRows, uint16_t nColumns, q31_t * pData); /** * @brief Q15 matrix initialization. * @param[in,out] *S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] *pData points to the matrix data array. * @return none */ void arm_mat_init_q15( arm_matrix_instance_q15 * S, uint16_t nRows, uint16_t nColumns, q15_t * pData); /** * @brief Floating-point matrix initialization. * @param[in,out] *S points to an instance of the floating-point matrix structure. * @param[in] nRows number of rows in the matrix. * @param[in] nColumns number of columns in the matrix. * @param[in] *pData points to the matrix data array. * @return none */ void arm_mat_init_f32( arm_matrix_instance_f32 * S, uint16_t nRows, uint16_t nColumns, float32_t * pData); /** * @brief Instance structure for the Q15 PID Control. */ typedef struct { q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ #ifdef ARM_MATH_CM0_FAMILY q15_t A1; q15_t A2; #else q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ #endif q15_t state[3]; /**< The state array of length 3. */ q15_t Kp; /**< The proportional gain. */ q15_t Ki; /**< The integral gain. */ q15_t Kd; /**< The derivative gain. */ } arm_pid_instance_q15; /** * @brief Instance structure for the Q31 PID Control. */ typedef struct { q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ q31_t A2; /**< The derived gain, A2 = Kd . */ q31_t state[3]; /**< The state array of length 3. */ q31_t Kp; /**< The proportional gain. */ q31_t Ki; /**< The integral gain. */ q31_t Kd; /**< The derivative gain. */ } arm_pid_instance_q31; /** * @brief Instance structure for the floating-point PID Control. */ typedef struct { float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ float32_t A2; /**< The derived gain, A2 = Kd . */ float32_t state[3]; /**< The state array of length 3. */ float32_t Kp; /**< The proportional gain. */ float32_t Ki; /**< The integral gain. */ float32_t Kd; /**< The derivative gain. */ } arm_pid_instance_f32; /** * @brief Initialization function for the floating-point PID Control. * @param[in,out] *S points to an instance of the PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. * @return none. */ void arm_pid_init_f32( arm_pid_instance_f32 * S, int32_t resetStateFlag); /** * @brief Reset function for the floating-point PID Control. * @param[in,out] *S is an instance of the floating-point PID Control structure * @return none */ void arm_pid_reset_f32( arm_pid_instance_f32 * S); /** * @brief Initialization function for the Q31 PID Control. * @param[in,out] *S points to an instance of the Q15 PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. * @return none. */ void arm_pid_init_q31( arm_pid_instance_q31 * S, int32_t resetStateFlag); /** * @brief Reset function for the Q31 PID Control. * @param[in,out] *S points to an instance of the Q31 PID Control structure * @return none */ void arm_pid_reset_q31( arm_pid_instance_q31 * S); /** * @brief Initialization function for the Q15 PID Control. * @param[in,out] *S points to an instance of the Q15 PID structure. * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. * @return none. */ void arm_pid_init_q15( arm_pid_instance_q15 * S, int32_t resetStateFlag); /** * @brief Reset function for the Q15 PID Control. * @param[in,out] *S points to an instance of the q15 PID Control structure * @return none */ void arm_pid_reset_q15( arm_pid_instance_q15 * S); /** * @brief Instance structure for the floating-point Linear Interpolate function. */ typedef struct { uint32_t nValues; /**< nValues */ float32_t x1; /**< x1 */ float32_t xSpacing; /**< xSpacing */ float32_t *pYData; /**< pointer to the table of Y values */ } arm_linear_interp_instance_f32; /** * @brief Instance structure for the floating-point bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ float32_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_f32; /** * @brief Instance structure for the Q31 bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ q31_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_q31; /** * @brief Instance structure for the Q15 bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ q15_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_q15; /** * @brief Instance structure for the Q15 bilinear interpolation function. */ typedef struct { uint16_t numRows; /**< number of rows in the data table. */ uint16_t numCols; /**< number of columns in the data table. */ q7_t *pData; /**< points to the data table. */ } arm_bilinear_interp_instance_q7; /** * @brief Q7 vector multiplication. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_mult_q7( q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, uint32_t blockSize); /** * @brief Q15 vector multiplication. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_mult_q15( q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, uint32_t blockSize); /** * @brief Q31 vector multiplication. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_mult_q31( q31_t * pSrcA, q31_t * pSrcB, q31_t * pDst, uint32_t blockSize); /** * @brief Floating-point vector multiplication. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_mult_f32( float32_t * pSrcA, float32_t * pSrcB, float32_t * pDst, uint32_t blockSize); /** * @brief Instance structure for the Q15 CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix2_instance_q15; arm_status arm_cfft_radix2_init_q15( arm_cfft_radix2_instance_q15 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); void arm_cfft_radix2_q15( const arm_cfft_radix2_instance_q15 * S, q15_t * pSrc); /** * @brief Instance structure for the Q15 CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ q15_t *pTwiddle; /**< points to the twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix4_instance_q15; arm_status arm_cfft_radix4_init_q15( arm_cfft_radix4_instance_q15 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); void arm_cfft_radix4_q15( const arm_cfft_radix4_instance_q15 * S, q15_t * pSrc); /** * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ q31_t *pTwiddle; /**< points to the Twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix2_instance_q31; arm_status arm_cfft_radix2_init_q31( arm_cfft_radix2_instance_q31 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); void arm_cfft_radix2_q31( const arm_cfft_radix2_instance_q31 * S, q31_t * pSrc); /** * @brief Instance structure for the Q31 CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ q31_t *pTwiddle; /**< points to the twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ } arm_cfft_radix4_instance_q31; void arm_cfft_radix4_q31( const arm_cfft_radix4_instance_q31 * S, q31_t * pSrc); arm_status arm_cfft_radix4_init_q31( arm_cfft_radix4_instance_q31 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ float32_t *pTwiddle; /**< points to the Twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ float32_t onebyfftLen; /**< value of 1/fftLen. */ } arm_cfft_radix2_instance_f32; /* Deprecated */ arm_status arm_cfft_radix2_init_f32( arm_cfft_radix2_instance_f32 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix2_f32( const arm_cfft_radix2_instance_f32 * S, float32_t * pSrc); /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ float32_t *pTwiddle; /**< points to the Twiddle factor table. */ uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ float32_t onebyfftLen; /**< value of 1/fftLen. */ } arm_cfft_radix4_instance_f32; /* Deprecated */ arm_status arm_cfft_radix4_init_f32( arm_cfft_radix4_instance_f32 * S, uint16_t fftLen, uint8_t ifftFlag, uint8_t bitReverseFlag); /* Deprecated */ void arm_cfft_radix4_f32( const arm_cfft_radix4_instance_f32 * S, float32_t * pSrc); /** * @brief Instance structure for the floating-point CFFT/CIFFT function. */ typedef struct { uint16_t fftLen; /**< length of the FFT. */ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ uint16_t bitRevLength; /**< bit reversal table length. */ } arm_cfft_instance_f32; void arm_cfft_f32( const arm_cfft_instance_f32 * S, float32_t * p1, uint8_t ifftFlag, uint8_t bitReverseFlag); /** * @brief Instance structure for the Q15 RFFT/RIFFT function. */ typedef struct { uint32_t fftLenReal; /**< length of the real FFT. */ uint32_t fftLenBy2; /**< length of the complex FFT. */ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ } arm_rfft_instance_q15; arm_status arm_rfft_init_q15( arm_rfft_instance_q15 * S, arm_cfft_radix4_instance_q15 * S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); void arm_rfft_q15( const arm_rfft_instance_q15 * S, q15_t * pSrc, q15_t * pDst); /** * @brief Instance structure for the Q31 RFFT/RIFFT function. */ typedef struct { uint32_t fftLenReal; /**< length of the real FFT. */ uint32_t fftLenBy2; /**< length of the complex FFT. */ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ } arm_rfft_instance_q31; arm_status arm_rfft_init_q31( arm_rfft_instance_q31 * S, arm_cfft_radix4_instance_q31 * S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); void arm_rfft_q31( const arm_rfft_instance_q31 * S, q31_t * pSrc, q31_t * pDst); /** * @brief Instance structure for the floating-point RFFT/RIFFT function. */ typedef struct { uint32_t fftLenReal; /**< length of the real FFT. */ uint16_t fftLenBy2; /**< length of the complex FFT. */ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ } arm_rfft_instance_f32; arm_status arm_rfft_init_f32( arm_rfft_instance_f32 * S, arm_cfft_radix4_instance_f32 * S_CFFT, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); void arm_rfft_f32( const arm_rfft_instance_f32 * S, float32_t * pSrc, float32_t * pDst); /** * @brief Instance structure for the floating-point RFFT/RIFFT function. */ typedef struct { arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ uint16_t fftLenRFFT; /**< length of the real sequence */ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ } arm_rfft_fast_instance_f32 ; arm_status arm_rfft_fast_init_f32 ( arm_rfft_fast_instance_f32 * S, uint16_t fftLen); void arm_rfft_fast_f32( arm_rfft_fast_instance_f32 * S, float32_t * p, float32_t * pOut, uint8_t ifftFlag); /** * @brief Instance structure for the floating-point DCT4/IDCT4 function. */ typedef struct { uint16_t N; /**< length of the DCT4. */ uint16_t Nby2; /**< half of the length of the DCT4. */ float32_t normalize; /**< normalizing factor. */ float32_t *pTwiddle; /**< points to the twiddle factor table. */ float32_t *pCosFactor; /**< points to the cosFactor table. */ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ } arm_dct4_instance_f32; /** * @brief Initialization function for the floating-point DCT4/IDCT4. * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. */ arm_status arm_dct4_init_f32( arm_dct4_instance_f32 * S, arm_rfft_instance_f32 * S_RFFT, arm_cfft_radix4_instance_f32 * S_CFFT, uint16_t N, uint16_t Nby2, float32_t normalize); /** * @brief Processing function for the floating-point DCT4/IDCT4. * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. * @param[in] *pState points to state buffer. * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. * @return none. */ void arm_dct4_f32( const arm_dct4_instance_f32 * S, float32_t * pState, float32_t * pInlineBuffer); /** * @brief Instance structure for the Q31 DCT4/IDCT4 function. */ typedef struct { uint16_t N; /**< length of the DCT4. */ uint16_t Nby2; /**< half of the length of the DCT4. */ q31_t normalize; /**< normalizing factor. */ q31_t *pTwiddle; /**< points to the twiddle factor table. */ q31_t *pCosFactor; /**< points to the cosFactor table. */ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ } arm_dct4_instance_q31; /** * @brief Initialization function for the Q31 DCT4/IDCT4. * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. */ arm_status arm_dct4_init_q31( arm_dct4_instance_q31 * S, arm_rfft_instance_q31 * S_RFFT, arm_cfft_radix4_instance_q31 * S_CFFT, uint16_t N, uint16_t Nby2, q31_t normalize); /** * @brief Processing function for the Q31 DCT4/IDCT4. * @param[in] *S points to an instance of the Q31 DCT4 structure. * @param[in] *pState points to state buffer. * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. * @return none. */ void arm_dct4_q31( const arm_dct4_instance_q31 * S, q31_t * pState, q31_t * pInlineBuffer); /** * @brief Instance structure for the Q15 DCT4/IDCT4 function. */ typedef struct { uint16_t N; /**< length of the DCT4. */ uint16_t Nby2; /**< half of the length of the DCT4. */ q15_t normalize; /**< normalizing factor. */ q15_t *pTwiddle; /**< points to the twiddle factor table. */ q15_t *pCosFactor; /**< points to the cosFactor table. */ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ } arm_dct4_instance_q15; /** * @brief Initialization function for the Q15 DCT4/IDCT4. * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. * @param[in] N length of the DCT4. * @param[in] Nby2 half of the length of the DCT4. * @param[in] normalize normalizing factor. * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. */ arm_status arm_dct4_init_q15( arm_dct4_instance_q15 * S, arm_rfft_instance_q15 * S_RFFT, arm_cfft_radix4_instance_q15 * S_CFFT, uint16_t N, uint16_t Nby2, q15_t normalize); /** * @brief Processing function for the Q15 DCT4/IDCT4. * @param[in] *S points to an instance of the Q15 DCT4 structure. * @param[in] *pState points to state buffer. * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. * @return none. */ void arm_dct4_q15( const arm_dct4_instance_q15 * S, q15_t * pState, q15_t * pInlineBuffer); /** * @brief Floating-point vector addition. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_add_f32( float32_t * pSrcA, float32_t * pSrcB, float32_t * pDst, uint32_t blockSize); /** * @brief Q7 vector addition. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_add_q7( q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, uint32_t blockSize); /** * @brief Q15 vector addition. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_add_q15( q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, uint32_t blockSize); /** * @brief Q31 vector addition. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_add_q31( q31_t * pSrcA, q31_t * pSrcB, q31_t * pDst, uint32_t blockSize); /** * @brief Floating-point vector subtraction. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_sub_f32( float32_t * pSrcA, float32_t * pSrcB, float32_t * pDst, uint32_t blockSize); /** * @brief Q7 vector subtraction. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_sub_q7( q7_t * pSrcA, q7_t * pSrcB, q7_t * pDst, uint32_t blockSize); /** * @brief Q15 vector subtraction. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_sub_q15( q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, uint32_t blockSize); /** * @brief Q31 vector subtraction. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in each vector * @return none. */ void arm_sub_q31( q31_t * pSrcA, q31_t * pSrcB, q31_t * pDst, uint32_t blockSize); /** * @brief Multiplies a floating-point vector by a scalar. * @param[in] *pSrc points to the input vector * @param[in] scale scale factor to be applied * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_scale_f32( float32_t * pSrc, float32_t scale, float32_t * pDst, uint32_t blockSize); /** * @brief Multiplies a Q7 vector by a scalar. * @param[in] *pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value * @param[in] shift number of bits to shift the result by * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_scale_q7( q7_t * pSrc, q7_t scaleFract, int8_t shift, q7_t * pDst, uint32_t blockSize); /** * @brief Multiplies a Q15 vector by a scalar. * @param[in] *pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value * @param[in] shift number of bits to shift the result by * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_scale_q15( q15_t * pSrc, q15_t scaleFract, int8_t shift, q15_t * pDst, uint32_t blockSize); /** * @brief Multiplies a Q31 vector by a scalar. * @param[in] *pSrc points to the input vector * @param[in] scaleFract fractional portion of the scale value * @param[in] shift number of bits to shift the result by * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_scale_q31( q31_t * pSrc, q31_t scaleFract, int8_t shift, q31_t * pDst, uint32_t blockSize); /** * @brief Q7 vector absolute value. * @param[in] *pSrc points to the input buffer * @param[out] *pDst points to the output buffer * @param[in] blockSize number of samples in each vector * @return none. */ void arm_abs_q7( q7_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Floating-point vector absolute value. * @param[in] *pSrc points to the input buffer * @param[out] *pDst points to the output buffer * @param[in] blockSize number of samples in each vector * @return none. */ void arm_abs_f32( float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Q15 vector absolute value. * @param[in] *pSrc points to the input buffer * @param[out] *pDst points to the output buffer * @param[in] blockSize number of samples in each vector * @return none. */ void arm_abs_q15( q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Q31 vector absolute value. * @param[in] *pSrc points to the input buffer * @param[out] *pDst points to the output buffer * @param[in] blockSize number of samples in each vector * @return none. */ void arm_abs_q31( q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Dot product of floating-point vectors. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] *result output result returned here * @return none. */ void arm_dot_prod_f32( float32_t * pSrcA, float32_t * pSrcB, uint32_t blockSize, float32_t * result); /** * @brief Dot product of Q7 vectors. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] *result output result returned here * @return none. */ void arm_dot_prod_q7( q7_t * pSrcA, q7_t * pSrcB, uint32_t blockSize, q31_t * result); /** * @brief Dot product of Q15 vectors. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] *result output result returned here * @return none. */ void arm_dot_prod_q15( q15_t * pSrcA, q15_t * pSrcB, uint32_t blockSize, q63_t * result); /** * @brief Dot product of Q31 vectors. * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[in] blockSize number of samples in each vector * @param[out] *result output result returned here * @return none. */ void arm_dot_prod_q31( q31_t * pSrcA, q31_t * pSrcB, uint32_t blockSize, q63_t * result); /** * @brief Shifts the elements of a Q7 vector a specified number of bits. * @param[in] *pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_shift_q7( q7_t * pSrc, int8_t shiftBits, q7_t * pDst, uint32_t blockSize); /** * @brief Shifts the elements of a Q15 vector a specified number of bits. * @param[in] *pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_shift_q15( q15_t * pSrc, int8_t shiftBits, q15_t * pDst, uint32_t blockSize); /** * @brief Shifts the elements of a Q31 vector a specified number of bits. * @param[in] *pSrc points to the input vector * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_shift_q31( q31_t * pSrc, int8_t shiftBits, q31_t * pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a floating-point vector. * @param[in] *pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_offset_f32( float32_t * pSrc, float32_t offset, float32_t * pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a Q7 vector. * @param[in] *pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_offset_q7( q7_t * pSrc, q7_t offset, q7_t * pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a Q15 vector. * @param[in] *pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_offset_q15( q15_t * pSrc, q15_t offset, q15_t * pDst, uint32_t blockSize); /** * @brief Adds a constant offset to a Q31 vector. * @param[in] *pSrc points to the input vector * @param[in] offset is the offset to be added * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_offset_q31( q31_t * pSrc, q31_t offset, q31_t * pDst, uint32_t blockSize); /** * @brief Negates the elements of a floating-point vector. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_negate_f32( float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Negates the elements of a Q7 vector. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_negate_q7( q7_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Negates the elements of a Q15 vector. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_negate_q15( q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Negates the elements of a Q31 vector. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector * @param[in] blockSize number of samples in the vector * @return none. */ void arm_negate_q31( q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Copies the elements of a floating-point vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_copy_f32( float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Copies the elements of a Q7 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_copy_q7( q7_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Copies the elements of a Q15 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_copy_q15( q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Copies the elements of a Q31 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_copy_q31( q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Fills a constant value into a floating-point vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_fill_f32( float32_t value, float32_t * pDst, uint32_t blockSize); /** * @brief Fills a constant value into a Q7 vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_fill_q7( q7_t value, q7_t * pDst, uint32_t blockSize); /** * @brief Fills a constant value into a Q15 vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_fill_q15( q15_t value, q15_t * pDst, uint32_t blockSize); /** * @brief Fills a constant value into a Q31 vector. * @param[in] value input value to be filled * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_fill_q31( q31_t value, q31_t * pDst, uint32_t blockSize); /** * @brief Convolution of floating-point sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. * @return none. */ void arm_conv_f32( float32_t * pSrcA, uint32_t srcALen, float32_t * pSrcB, uint32_t srcBLen, float32_t * pDst); /** * @brief Convolution of Q15 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). * @return none. */ void arm_conv_opt_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Convolution of Q15 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. * @return none. */ void arm_conv_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst); /** * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. * @return none. */ void arm_conv_fast_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst); /** * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). * @return none. */ void arm_conv_fast_opt_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Convolution of Q31 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. * @return none. */ void arm_conv_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst); /** * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. * @return none. */ void arm_conv_fast_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst); /** * @brief Convolution of Q7 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). * @return none. */ void arm_conv_opt_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Convolution of Q7 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. * @return none. */ void arm_conv_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst); /** * @brief Partial convolution of floating-point sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_f32( float32_t * pSrcA, uint32_t srcALen, float32_t * pSrcB, uint32_t srcBLen, float32_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q15 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_opt_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, uint32_t firstIndex, uint32_t numPoints, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Partial convolution of Q15 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_fast_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_fast_opt_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, uint32_t firstIndex, uint32_t numPoints, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Partial convolution of Q31 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_fast_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Partial convolution of Q7 sequences * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_opt_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst, uint32_t firstIndex, uint32_t numPoints, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Partial convolution of Q7 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data * @param[in] firstIndex is the first output sample to start with. * @param[in] numPoints is the number of output points to be computed. * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. */ arm_status arm_conv_partial_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst, uint32_t firstIndex, uint32_t numPoints); /** * @brief Instance structure for the Q15 FIR decimator. */ typedef struct { uint8_t M; /**< decimation factor. */ uint16_t numTaps; /**< number of coefficients in the filter. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ } arm_fir_decimate_instance_q15; /** * @brief Instance structure for the Q31 FIR decimator. */ typedef struct { uint8_t M; /**< decimation factor. */ uint16_t numTaps; /**< number of coefficients in the filter. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ } arm_fir_decimate_instance_q31; /** * @brief Instance structure for the floating-point FIR decimator. */ typedef struct { uint8_t M; /**< decimation factor. */ uint16_t numTaps; /**< number of coefficients in the filter. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ } arm_fir_decimate_instance_f32; /** * @brief Processing function for the floating-point FIR decimator. * @param[in] *S points to an instance of the floating-point FIR decimator structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. * @return none */ void arm_fir_decimate_f32( const arm_fir_decimate_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR decimator. * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. * @param[in] M decimation factor. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * blockSize is not a multiple of M. */ arm_status arm_fir_decimate_init_f32( arm_fir_decimate_instance_f32 * S, uint16_t numTaps, uint8_t M, float32_t * pCoeffs, float32_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q15 FIR decimator. * @param[in] *S points to an instance of the Q15 FIR decimator structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. * @return none */ void arm_fir_decimate_q15( const arm_fir_decimate_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q15 FIR decimator structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. * @return none */ void arm_fir_decimate_fast_q15( const arm_fir_decimate_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 FIR decimator. * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. * @param[in] M decimation factor. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * blockSize is not a multiple of M. */ arm_status arm_fir_decimate_init_q15( arm_fir_decimate_instance_q15 * S, uint16_t numTaps, uint8_t M, q15_t * pCoeffs, q15_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR decimator. * @param[in] *S points to an instance of the Q31 FIR decimator structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. * @return none */ void arm_fir_decimate_q31( const arm_fir_decimate_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. * @param[in] *S points to an instance of the Q31 FIR decimator structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] blockSize number of input samples to process per call. * @return none */ void arm_fir_decimate_fast_q31( arm_fir_decimate_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR decimator. * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. * @param[in] numTaps number of coefficients in the filter. * @param[in] M decimation factor. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * blockSize is not a multiple of M. */ arm_status arm_fir_decimate_init_q31( arm_fir_decimate_instance_q31 * S, uint16_t numTaps, uint8_t M, q31_t * pCoeffs, q31_t * pState, uint32_t blockSize); /** * @brief Instance structure for the Q15 FIR interpolator. */ typedef struct { uint8_t L; /**< upsample factor. */ uint16_t phaseLength; /**< length of each polyphase filter component. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ } arm_fir_interpolate_instance_q15; /** * @brief Instance structure for the Q31 FIR interpolator. */ typedef struct { uint8_t L; /**< upsample factor. */ uint16_t phaseLength; /**< length of each polyphase filter component. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ } arm_fir_interpolate_instance_q31; /** * @brief Instance structure for the floating-point FIR interpolator. */ typedef struct { uint8_t L; /**< upsample factor. */ uint16_t phaseLength; /**< length of each polyphase filter component. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ } arm_fir_interpolate_instance_f32; /** * @brief Processing function for the Q15 FIR interpolator. * @param[in] *S points to an instance of the Q15 FIR interpolator structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of input samples to process per call. * @return none. */ void arm_fir_interpolate_q15( const arm_fir_interpolate_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 FIR interpolator. * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. * @param[in] L upsample factor. * @param[in] numTaps number of filter coefficients in the filter. * @param[in] *pCoeffs points to the filter coefficient buffer. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * the filter length numTaps is not a multiple of the interpolation factor L. */ arm_status arm_fir_interpolate_init_q15( arm_fir_interpolate_instance_q15 * S, uint8_t L, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q31 FIR interpolator. * @param[in] *S points to an instance of the Q15 FIR interpolator structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of input samples to process per call. * @return none. */ void arm_fir_interpolate_q31( const arm_fir_interpolate_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR interpolator. * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. * @param[in] L upsample factor. * @param[in] numTaps number of filter coefficients in the filter. * @param[in] *pCoeffs points to the filter coefficient buffer. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * the filter length numTaps is not a multiple of the interpolation factor L. */ arm_status arm_fir_interpolate_init_q31( arm_fir_interpolate_instance_q31 * S, uint8_t L, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, uint32_t blockSize); /** * @brief Processing function for the floating-point FIR interpolator. * @param[in] *S points to an instance of the floating-point FIR interpolator structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of input samples to process per call. * @return none. */ void arm_fir_interpolate_f32( const arm_fir_interpolate_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR interpolator. * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. * @param[in] L upsample factor. * @param[in] numTaps number of filter coefficients in the filter. * @param[in] *pCoeffs points to the filter coefficient buffer. * @param[in] *pState points to the state buffer. * @param[in] blockSize number of input samples to process per call. * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if * the filter length numTaps is not a multiple of the interpolation factor L. */ arm_status arm_fir_interpolate_init_f32( arm_fir_interpolate_instance_f32 * S, uint8_t L, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, uint32_t blockSize); /** * @brief Instance structure for the high precision Q31 Biquad cascade filter. */ typedef struct { uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ } arm_biquad_cas_df1_32x64_ins_q31; /** * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] blockSize number of samples to process. * @return none. */ void arm_biquad_cas_df1_32x64_q31( const arm_biquad_cas_df1_32x64_ins_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format * @return none */ void arm_biquad_cas_df1_32x64_init_q31( arm_biquad_cas_df1_32x64_ins_q31 * S, uint8_t numStages, q31_t * pCoeffs, q63_t * pState, uint8_t postShift); /** * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. */ typedef struct { uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ } arm_biquad_cascade_df2T_instance_f32; /** * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. * @param[in] *S points to an instance of the filter data structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] blockSize number of samples to process. * @return none. */ void arm_biquad_cascade_df2T_f32( const arm_biquad_cascade_df2T_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. * @param[in,out] *S points to an instance of the filter data structure. * @param[in] numStages number of 2nd order stages in the filter. * @param[in] *pCoeffs points to the filter coefficients. * @param[in] *pState points to the state buffer. * @return none */ void arm_biquad_cascade_df2T_init_f32( arm_biquad_cascade_df2T_instance_f32 * S, uint8_t numStages, float32_t * pCoeffs, float32_t * pState); /** * @brief Instance structure for the Q15 FIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of filter stages. */ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ } arm_fir_lattice_instance_q15; /** * @brief Instance structure for the Q31 FIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of filter stages. */ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ } arm_fir_lattice_instance_q31; /** * @brief Instance structure for the floating-point FIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of filter stages. */ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ } arm_fir_lattice_instance_f32; /** * @brief Initialization function for the Q15 FIR lattice filter. * @param[in] *S points to an instance of the Q15 FIR lattice structure. * @param[in] numStages number of filter stages. * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. * @param[in] *pState points to the state buffer. The array is of length numStages. * @return none. */ void arm_fir_lattice_init_q15( arm_fir_lattice_instance_q15 * S, uint16_t numStages, q15_t * pCoeffs, q15_t * pState); /** * @brief Processing function for the Q15 FIR lattice filter. * @param[in] *S points to an instance of the Q15 FIR lattice structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_fir_lattice_q15( const arm_fir_lattice_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 FIR lattice filter. * @param[in] *S points to an instance of the Q31 FIR lattice structure. * @param[in] numStages number of filter stages. * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. * @param[in] *pState points to the state buffer. The array is of length numStages. * @return none. */ void arm_fir_lattice_init_q31( arm_fir_lattice_instance_q31 * S, uint16_t numStages, q31_t * pCoeffs, q31_t * pState); /** * @brief Processing function for the Q31 FIR lattice filter. * @param[in] *S points to an instance of the Q31 FIR lattice structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] blockSize number of samples to process. * @return none. */ void arm_fir_lattice_q31( const arm_fir_lattice_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point FIR lattice filter. * @param[in] *S points to an instance of the floating-point FIR lattice structure. * @param[in] numStages number of filter stages. * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. * @param[in] *pState points to the state buffer. The array is of length numStages. * @return none. */ void arm_fir_lattice_init_f32( arm_fir_lattice_instance_f32 * S, uint16_t numStages, float32_t * pCoeffs, float32_t * pState); /** * @brief Processing function for the floating-point FIR lattice filter. * @param[in] *S points to an instance of the floating-point FIR lattice structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] blockSize number of samples to process. * @return none. */ void arm_fir_lattice_f32( const arm_fir_lattice_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Instance structure for the Q15 IIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of stages in the filter. */ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ } arm_iir_lattice_instance_q15; /** * @brief Instance structure for the Q31 IIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of stages in the filter. */ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ } arm_iir_lattice_instance_q31; /** * @brief Instance structure for the floating-point IIR lattice filter. */ typedef struct { uint16_t numStages; /**< number of stages in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ } arm_iir_lattice_instance_f32; /** * @brief Processing function for the floating-point IIR lattice filter. * @param[in] *S points to an instance of the floating-point IIR lattice structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_iir_lattice_f32( const arm_iir_lattice_instance_f32 * S, float32_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the floating-point IIR lattice filter. * @param[in] *S points to an instance of the floating-point IIR lattice structure. * @param[in] numStages number of stages in the filter. * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. * @param[in] blockSize number of samples to process. * @return none. */ void arm_iir_lattice_init_f32( arm_iir_lattice_instance_f32 * S, uint16_t numStages, float32_t * pkCoeffs, float32_t * pvCoeffs, float32_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q31 IIR lattice filter. * @param[in] *S points to an instance of the Q31 IIR lattice structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_iir_lattice_q31( const arm_iir_lattice_instance_q31 * S, q31_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q31 IIR lattice filter. * @param[in] *S points to an instance of the Q31 IIR lattice structure. * @param[in] numStages number of stages in the filter. * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. * @param[in] blockSize number of samples to process. * @return none. */ void arm_iir_lattice_init_q31( arm_iir_lattice_instance_q31 * S, uint16_t numStages, q31_t * pkCoeffs, q31_t * pvCoeffs, q31_t * pState, uint32_t blockSize); /** * @brief Processing function for the Q15 IIR lattice filter. * @param[in] *S points to an instance of the Q15 IIR lattice structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_iir_lattice_q15( const arm_iir_lattice_instance_q15 * S, q15_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Initialization function for the Q15 IIR lattice filter. * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. * @param[in] numStages number of stages in the filter. * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. * @param[in] blockSize number of samples to process per call. * @return none. */ void arm_iir_lattice_init_q15( arm_iir_lattice_instance_q15 * S, uint16_t numStages, q15_t * pkCoeffs, q15_t * pvCoeffs, q15_t * pState, uint32_t blockSize); /** * @brief Instance structure for the floating-point LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ float32_t mu; /**< step size that controls filter coefficient updates. */ } arm_lms_instance_f32; /** * @brief Processing function for floating-point LMS filter. * @param[in] *S points to an instance of the floating-point LMS filter structure. * @param[in] *pSrc points to the block of input data. * @param[in] *pRef points to the block of reference data. * @param[out] *pOut points to the block of output data. * @param[out] *pErr points to the block of error data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_lms_f32( const arm_lms_instance_f32 * S, float32_t * pSrc, float32_t * pRef, float32_t * pOut, float32_t * pErr, uint32_t blockSize); /** * @brief Initialization function for floating-point LMS filter. * @param[in] *S points to an instance of the floating-point LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] *pCoeffs points to the coefficient buffer. * @param[in] *pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @return none. */ void arm_lms_init_f32( arm_lms_instance_f32 * S, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, float32_t mu, uint32_t blockSize); /** * @brief Instance structure for the Q15 LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q15_t mu; /**< step size that controls filter coefficient updates. */ uint32_t postShift; /**< bit shift applied to coefficients. */ } arm_lms_instance_q15; /** * @brief Initialization function for the Q15 LMS filter. * @param[in] *S points to an instance of the Q15 LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] *pCoeffs points to the coefficient buffer. * @param[in] *pState points to the state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. * @return none. */ void arm_lms_init_q15( arm_lms_instance_q15 * S, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, q15_t mu, uint32_t blockSize, uint32_t postShift); /** * @brief Processing function for Q15 LMS filter. * @param[in] *S points to an instance of the Q15 LMS filter structure. * @param[in] *pSrc points to the block of input data. * @param[in] *pRef points to the block of reference data. * @param[out] *pOut points to the block of output data. * @param[out] *pErr points to the block of error data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_lms_q15( const arm_lms_instance_q15 * S, q15_t * pSrc, q15_t * pRef, q15_t * pOut, q15_t * pErr, uint32_t blockSize); /** * @brief Instance structure for the Q31 LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q31_t mu; /**< step size that controls filter coefficient updates. */ uint32_t postShift; /**< bit shift applied to coefficients. */ } arm_lms_instance_q31; /** * @brief Processing function for Q31 LMS filter. * @param[in] *S points to an instance of the Q15 LMS filter structure. * @param[in] *pSrc points to the block of input data. * @param[in] *pRef points to the block of reference data. * @param[out] *pOut points to the block of output data. * @param[out] *pErr points to the block of error data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_lms_q31( const arm_lms_instance_q31 * S, q31_t * pSrc, q31_t * pRef, q31_t * pOut, q31_t * pErr, uint32_t blockSize); /** * @brief Initialization function for Q31 LMS filter. * @param[in] *S points to an instance of the Q31 LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] *pCoeffs points to coefficient buffer. * @param[in] *pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. * @return none. */ void arm_lms_init_q31( arm_lms_instance_q31 * S, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, q31_t mu, uint32_t blockSize, uint32_t postShift); /** * @brief Instance structure for the floating-point normalized LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ float32_t mu; /**< step size that control filter coefficient updates. */ float32_t energy; /**< saves previous frame energy. */ float32_t x0; /**< saves previous input sample. */ } arm_lms_norm_instance_f32; /** * @brief Processing function for floating-point normalized LMS filter. * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. * @param[in] *pSrc points to the block of input data. * @param[in] *pRef points to the block of reference data. * @param[out] *pOut points to the block of output data. * @param[out] *pErr points to the block of error data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_lms_norm_f32( arm_lms_norm_instance_f32 * S, float32_t * pSrc, float32_t * pRef, float32_t * pOut, float32_t * pErr, uint32_t blockSize); /** * @brief Initialization function for floating-point normalized LMS filter. * @param[in] *S points to an instance of the floating-point LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] *pCoeffs points to coefficient buffer. * @param[in] *pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @return none. */ void arm_lms_norm_init_f32( arm_lms_norm_instance_f32 * S, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, float32_t mu, uint32_t blockSize); /** * @brief Instance structure for the Q31 normalized LMS filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q31_t mu; /**< step size that controls filter coefficient updates. */ uint8_t postShift; /**< bit shift applied to coefficients. */ q31_t *recipTable; /**< points to the reciprocal initial value table. */ q31_t energy; /**< saves previous frame energy. */ q31_t x0; /**< saves previous input sample. */ } arm_lms_norm_instance_q31; /** * @brief Processing function for Q31 normalized LMS filter. * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. * @param[in] *pSrc points to the block of input data. * @param[in] *pRef points to the block of reference data. * @param[out] *pOut points to the block of output data. * @param[out] *pErr points to the block of error data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_lms_norm_q31( arm_lms_norm_instance_q31 * S, q31_t * pSrc, q31_t * pRef, q31_t * pOut, q31_t * pErr, uint32_t blockSize); /** * @brief Initialization function for Q31 normalized LMS filter. * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] *pCoeffs points to coefficient buffer. * @param[in] *pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. * @return none. */ void arm_lms_norm_init_q31( arm_lms_norm_instance_q31 * S, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, q31_t mu, uint32_t blockSize, uint8_t postShift); /** * @brief Instance structure for the Q15 normalized LMS filter. */ typedef struct { uint16_t numTaps; /**< Number of coefficients in the filter. */ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ q15_t mu; /**< step size that controls filter coefficient updates. */ uint8_t postShift; /**< bit shift applied to coefficients. */ q15_t *recipTable; /**< Points to the reciprocal initial value table. */ q15_t energy; /**< saves previous frame energy. */ q15_t x0; /**< saves previous input sample. */ } arm_lms_norm_instance_q15; /** * @brief Processing function for Q15 normalized LMS filter. * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. * @param[in] *pSrc points to the block of input data. * @param[in] *pRef points to the block of reference data. * @param[out] *pOut points to the block of output data. * @param[out] *pErr points to the block of error data. * @param[in] blockSize number of samples to process. * @return none. */ void arm_lms_norm_q15( arm_lms_norm_instance_q15 * S, q15_t * pSrc, q15_t * pRef, q15_t * pOut, q15_t * pErr, uint32_t blockSize); /** * @brief Initialization function for Q15 normalized LMS filter. * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. * @param[in] numTaps number of filter coefficients. * @param[in] *pCoeffs points to coefficient buffer. * @param[in] *pState points to state buffer. * @param[in] mu step size that controls filter coefficient updates. * @param[in] blockSize number of samples to process. * @param[in] postShift bit shift applied to coefficients. * @return none. */ void arm_lms_norm_init_q15( arm_lms_norm_instance_q15 * S, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, q15_t mu, uint32_t blockSize, uint8_t postShift); /** * @brief Correlation of floating-point sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @return none. */ void arm_correlate_f32( float32_t * pSrcA, uint32_t srcALen, float32_t * pSrcB, uint32_t srcBLen, float32_t * pDst); /** * @brief Correlation of Q15 sequences * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @return none. */ void arm_correlate_opt_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, q15_t * pScratch); /** * @brief Correlation of Q15 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @return none. */ void arm_correlate_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst); /** * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @return none. */ void arm_correlate_fast_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst); /** * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @return none. */ void arm_correlate_fast_opt_q15( q15_t * pSrcA, uint32_t srcALen, q15_t * pSrcB, uint32_t srcBLen, q15_t * pDst, q15_t * pScratch); /** * @brief Correlation of Q31 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @return none. */ void arm_correlate_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst); /** * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @return none. */ void arm_correlate_fast_q31( q31_t * pSrcA, uint32_t srcALen, q31_t * pSrcB, uint32_t srcBLen, q31_t * pDst); /** * @brief Correlation of Q7 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). * @return none. */ void arm_correlate_opt_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst, q15_t * pScratch1, q15_t * pScratch2); /** * @brief Correlation of Q7 sequences. * @param[in] *pSrcA points to the first input sequence. * @param[in] srcALen length of the first input sequence. * @param[in] *pSrcB points to the second input sequence. * @param[in] srcBLen length of the second input sequence. * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. * @return none. */ void arm_correlate_q7( q7_t * pSrcA, uint32_t srcALen, q7_t * pSrcB, uint32_t srcBLen, q7_t * pDst); /** * @brief Instance structure for the floating-point sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_f32; /** * @brief Instance structure for the Q31 sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_q31; /** * @brief Instance structure for the Q15 sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_q15; /** * @brief Instance structure for the Q7 sparse FIR filter. */ typedef struct { uint16_t numTaps; /**< number of coefficients in the filter. */ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ } arm_fir_sparse_instance_q7; /** * @brief Processing function for the floating-point sparse FIR filter. * @param[in] *S points to an instance of the floating-point sparse FIR structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] *pScratchIn points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. * @return none. */ void arm_fir_sparse_f32( arm_fir_sparse_instance_f32 * S, float32_t * pSrc, float32_t * pDst, float32_t * pScratchIn, uint32_t blockSize); /** * @brief Initialization function for the floating-point sparse FIR filter. * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] *pCoeffs points to the array of filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] *pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. * @return none */ void arm_fir_sparse_init_f32( arm_fir_sparse_instance_f32 * S, uint16_t numTaps, float32_t * pCoeffs, float32_t * pState, int32_t * pTapDelay, uint16_t maxDelay, uint32_t blockSize); /** * @brief Processing function for the Q31 sparse FIR filter. * @param[in] *S points to an instance of the Q31 sparse FIR structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] *pScratchIn points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. * @return none. */ void arm_fir_sparse_q31( arm_fir_sparse_instance_q31 * S, q31_t * pSrc, q31_t * pDst, q31_t * pScratchIn, uint32_t blockSize); /** * @brief Initialization function for the Q31 sparse FIR filter. * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] *pCoeffs points to the array of filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] *pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. * @return none */ void arm_fir_sparse_init_q31( arm_fir_sparse_instance_q31 * S, uint16_t numTaps, q31_t * pCoeffs, q31_t * pState, int32_t * pTapDelay, uint16_t maxDelay, uint32_t blockSize); /** * @brief Processing function for the Q15 sparse FIR filter. * @param[in] *S points to an instance of the Q15 sparse FIR structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] *pScratchIn points to a temporary buffer of size blockSize. * @param[in] *pScratchOut points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. * @return none. */ void arm_fir_sparse_q15( arm_fir_sparse_instance_q15 * S, q15_t * pSrc, q15_t * pDst, q15_t * pScratchIn, q31_t * pScratchOut, uint32_t blockSize); /** * @brief Initialization function for the Q15 sparse FIR filter. * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] *pCoeffs points to the array of filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] *pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. * @return none */ void arm_fir_sparse_init_q15( arm_fir_sparse_instance_q15 * S, uint16_t numTaps, q15_t * pCoeffs, q15_t * pState, int32_t * pTapDelay, uint16_t maxDelay, uint32_t blockSize); /** * @brief Processing function for the Q7 sparse FIR filter. * @param[in] *S points to an instance of the Q7 sparse FIR structure. * @param[in] *pSrc points to the block of input data. * @param[out] *pDst points to the block of output data * @param[in] *pScratchIn points to a temporary buffer of size blockSize. * @param[in] *pScratchOut points to a temporary buffer of size blockSize. * @param[in] blockSize number of input samples to process per call. * @return none. */ void arm_fir_sparse_q7( arm_fir_sparse_instance_q7 * S, q7_t * pSrc, q7_t * pDst, q7_t * pScratchIn, q31_t * pScratchOut, uint32_t blockSize); /** * @brief Initialization function for the Q7 sparse FIR filter. * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. * @param[in] numTaps number of nonzero coefficients in the filter. * @param[in] *pCoeffs points to the array of filter coefficients. * @param[in] *pState points to the state buffer. * @param[in] *pTapDelay points to the array of offset times. * @param[in] maxDelay maximum offset time supported. * @param[in] blockSize number of samples that will be processed per block. * @return none */ void arm_fir_sparse_init_q7( arm_fir_sparse_instance_q7 * S, uint16_t numTaps, q7_t * pCoeffs, q7_t * pState, int32_t * pTapDelay, uint16_t maxDelay, uint32_t blockSize); /* * @brief Floating-point sin_cos function. * @param[in] theta input value in degrees * @param[out] *pSinVal points to the processed sine output. * @param[out] *pCosVal points to the processed cos output. * @return none. */ void arm_sin_cos_f32( float32_t theta, float32_t * pSinVal, float32_t * pCcosVal); /* * @brief Q31 sin_cos function. * @param[in] theta scaled input value in degrees * @param[out] *pSinVal points to the processed sine output. * @param[out] *pCosVal points to the processed cosine output. * @return none. */ void arm_sin_cos_q31( q31_t theta, q31_t * pSinVal, q31_t * pCosVal); /** * @brief Floating-point complex conjugate. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector * @param[in] numSamples number of complex samples in each vector * @return none. */ void arm_cmplx_conj_f32( float32_t * pSrc, float32_t * pDst, uint32_t numSamples); /** * @brief Q31 complex conjugate. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector * @param[in] numSamples number of complex samples in each vector * @return none. */ void arm_cmplx_conj_q31( q31_t * pSrc, q31_t * pDst, uint32_t numSamples); /** * @brief Q15 complex conjugate. * @param[in] *pSrc points to the input vector * @param[out] *pDst points to the output vector * @param[in] numSamples number of complex samples in each vector * @return none. */ void arm_cmplx_conj_q15( q15_t * pSrc, q15_t * pDst, uint32_t numSamples); /** * @brief Floating-point complex magnitude squared * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector * @return none. */ void arm_cmplx_mag_squared_f32( float32_t * pSrc, float32_t * pDst, uint32_t numSamples); /** * @brief Q31 complex magnitude squared * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector * @return none. */ void arm_cmplx_mag_squared_q31( q31_t * pSrc, q31_t * pDst, uint32_t numSamples); /** * @brief Q15 complex magnitude squared * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector * @return none. */ void arm_cmplx_mag_squared_q15( q15_t * pSrc, q15_t * pDst, uint32_t numSamples); /** * @ingroup groupController */ /** * @defgroup PID PID Motor Control * * A Proportional Integral Derivative (PID) controller is a generic feedback control * loop mechanism widely used in industrial control systems. * A PID controller is the most commonly used type of feedback controller. * * This set of functions implements (PID) controllers * for Q15, Q31, and floating-point data types. The functions operate on a single sample * of data and each call to the function returns a single processed value. * S points to an instance of the PID control data structure. in * is the input sample value. The functions return the output value. * * \par Algorithm: * 
   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
   *    A0 = Kp + Ki + Kd
   *    A1 = (-Kp ) - (2 * Kd )
   *    A2 = Kd
* * \par * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant * * \par * \image html PID.gif "Proportional Integral Derivative Controller" * * \par * The PID controller calculates an "error" value as the difference between * the measured output and the reference input. * The controller attempts to minimize the error by adjusting the process control inputs. * The proportional value determines the reaction to the current error, * the integral value determines the reaction based on the sum of recent errors, * and the derivative value determines the reaction based on the rate at which the error has been changing. * * \par Instance Structure * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. * A separate instance structure must be defined for each PID Controller. * There are separate instance structure declarations for each of the 3 supported data types. * * \par Reset Functions * There is also an associated reset function for each data type which clears the state array. * * \par Initialization Functions * There is also an associated initialization function for each data type. * The initialization function performs the following operations: * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. * - Zeros out the values in the state buffer. * * \par * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. * * \par Fixed-Point Behavior * Care must be taken when using the fixed-point versions of the PID Controller functions. * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup PID * @{ */ /** * @brief Process function for the floating-point PID Control. * @param[in,out] *S is an instance of the floating-point PID Control structure * @param[in] in input sample to process * @return out processed output sample. */ static __INLINE float32_t arm_pid_f32( arm_pid_instance_f32 * S, float32_t in) { float32_t out; /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ out = (S->A0 * in) + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); /* Update state */ S->state[1] = S->state[0]; S->state[0] = in; S->state[2] = out; /* return to application */ return (out); } /** * @brief Process function for the Q31 PID Control. * @param[in,out] *S points to an instance of the Q31 PID Control structure * @param[in] in input sample to process * @return out processed output sample. * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 64-bit accumulator. * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. * Thus, if the accumulator result overflows it wraps around rather than clip. * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. */ static __INLINE q31_t arm_pid_q31( arm_pid_instance_q31 * S, q31_t in) { q63_t acc; q31_t out; /* acc = A0 * x[n] */ acc = (q63_t) S->A0 * in; /* acc += A1 * x[n-1] */ acc += (q63_t) S->A1 * S->state[0]; /* acc += A2 * x[n-2] */ acc += (q63_t) S->A2 * S->state[1]; /* convert output to 1.31 format to add y[n-1] */ out = (q31_t) (acc >> 31u); /* out += y[n-1] */ out += S->state[2]; /* Update state */ S->state[1] = S->state[0]; S->state[0] = in; S->state[2] = out; /* return to application */ return (out); } /** * @brief Process function for the Q15 PID Control. * @param[in,out] *S points to an instance of the Q15 PID Control structure * @param[in] in input sample to process * @return out processed output sample. * * Scaling and Overflow Behavior: * \par * The function is implemented using a 64-bit internal accumulator. * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. * Lastly, the accumulator is saturated to yield a result in 1.15 format. */ static __INLINE q15_t arm_pid_q15( arm_pid_instance_q15 * S, q15_t in) { q63_t acc; q15_t out; #ifndef ARM_MATH_CM0_FAMILY __SIMD32_TYPE *vstate; /* Implementation of PID controller */ /* acc = A0 * x[n] */ acc = (q31_t) __SMUAD(S->A0, in); /* acc += A1 * x[n-1] + A2 * x[n-2] */ vstate = __SIMD32_CONST(S->state); acc = __SMLALD(S->A1, (q31_t) *vstate, acc); #else /* acc = A0 * x[n] */ acc = ((q31_t) S->A0) * in; /* acc += A1 * x[n-1] + A2 * x[n-2] */ acc += (q31_t) S->A1 * S->state[0]; acc += (q31_t) S->A2 * S->state[1]; #endif /* acc += y[n-1] */ acc += (q31_t) S->state[2] << 15; /* saturate the output */ out = (q15_t) (__SSAT((acc >> 15), 16)); /* Update state */ S->state[1] = S->state[0]; S->state[0] = in; S->state[2] = out; /* return to application */ return (out); } /** * @} end of PID group */ /** * @brief Floating-point matrix inverse. * @param[in] *src points to the instance of the input floating-point matrix structure. * @param[out] *dst points to the instance of the output floating-point matrix structure. * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. */ arm_status arm_mat_inverse_f32( const arm_matrix_instance_f32 * src, arm_matrix_instance_f32 * dst); /** * @ingroup groupController */ /** * @defgroup clarke Vector Clarke Transform * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents * in the two-phase orthogonal stator axis Ialpha and Ibeta. * When Ialpha is superposed with Ia as shown in the figure below * \image html clarke.gif Stator current space vector and its components in (a,b). * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta * can be calculated using only Ia and Ib. * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html clarkeFormula.gif * where Ia and Ib are the instantaneous stator phases and * pIalpha and pIbeta are the two coordinates of time invariant vector. * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Clarke transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup clarke * @{ */ /** * * @brief Floating-point Clarke transform * @param[in] Ia input three-phase coordinate a * @param[in] Ib input three-phase coordinate b * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta * @return none. */ static __INLINE void arm_clarke_f32( float32_t Ia, float32_t Ib, float32_t * pIalpha, float32_t * pIbeta) { /* Calculate pIalpha using the equation, pIalpha = Ia */ *pIalpha = Ia; /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); } /** * @brief Clarke transform for Q31 version * @param[in] Ia input three-phase coordinate a * @param[in] Ib input three-phase coordinate b * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta * @return none. * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the addition, hence there is no risk of overflow. */ static __INLINE void arm_clarke_q31( q31_t Ia, q31_t Ib, q31_t * pIalpha, q31_t * pIbeta) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ /* Calculating pIalpha from Ia by equation pIalpha = Ia */ *pIalpha = Ia; /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); /* pIbeta is calculated by adding the intermediate products */ *pIbeta = __QADD(product1, product2); } /** * @} end of clarke group */ /** * @brief Converts the elements of the Q7 vector to Q31 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_q7_to_q31( q7_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @ingroup groupController */ /** * @defgroup inv_clarke Vector Inverse Clarke Transform * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html clarkeInvFormula.gif * where pIa and pIb are the instantaneous stator phases and * Ialpha and Ibeta are the two coordinates of time invariant vector. * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Clarke transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup inv_clarke * @{ */ /** * @brief Floating-point Inverse Clarke transform * @param[in] Ialpha input two-phase orthogonal vector axis alpha * @param[in] Ibeta input two-phase orthogonal vector axis beta * @param[out] *pIa points to output three-phase coordinate a * @param[out] *pIb points to output three-phase coordinate b * @return none. */ static __INLINE void arm_inv_clarke_f32( float32_t Ialpha, float32_t Ibeta, float32_t * pIa, float32_t * pIb) { /* Calculating pIa from Ialpha by equation pIa = Ialpha */ *pIa = Ialpha; /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; } /** * @brief Inverse Clarke transform for Q31 version * @param[in] Ialpha input two-phase orthogonal vector axis alpha * @param[in] Ibeta input two-phase orthogonal vector axis beta * @param[out] *pIa points to output three-phase coordinate a * @param[out] *pIb points to output three-phase coordinate b * @return none. * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the subtraction, hence there is no risk of overflow. */ static __INLINE void arm_inv_clarke_q31( q31_t Ialpha, q31_t Ibeta, q31_t * pIa, q31_t * pIb) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ /* Calculating pIa from Ialpha by equation pIa = Ialpha */ *pIa = Ialpha; /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); /* pIb is calculated by subtracting the products */ *pIb = __QSUB(product2, product1); } /** * @} end of inv_clarke group */ /** * @brief Converts the elements of the Q7 vector to Q15 vector. * @param[in] *pSrc input pointer * @param[out] *pDst output pointer * @param[in] blockSize number of samples to process * @return none. */ void arm_q7_to_q15( q7_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @ingroup groupController */ /** * @defgroup park Vector Park Transform * * Forward Park transform converts the input two-coordinate vector to flux and torque components. * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents * from the stationary to the moving reference frame and control the spatial relationship between * the stator vector current and rotor flux vector. * If we consider the d axis aligned with the rotor flux, the diagram below shows the * current vector and the relationship from the two reference frames: * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html parkFormula.gif * where Ialpha and Ibeta are the stator vector components, * pId and pIq are rotor vector components and cosVal and sinVal are the * cosine and sine values of theta (rotor flux position). * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Park transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup park * @{ */ /** * @brief Floating-point Park transform * @param[in] Ialpha input two-phase vector coordinate alpha * @param[in] Ibeta input two-phase vector coordinate beta * @param[out] *pId points to output rotor reference frame d * @param[out] *pIq points to output rotor reference frame q * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * @return none. * * The function implements the forward Park transform. * */ static __INLINE void arm_park_f32( float32_t Ialpha, float32_t Ibeta, float32_t * pId, float32_t * pIq, float32_t sinVal, float32_t cosVal) { /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ *pId = Ialpha * cosVal + Ibeta * sinVal; /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ *pIq = -Ialpha * sinVal + Ibeta * cosVal; } /** * @brief Park transform for Q31 version * @param[in] Ialpha input two-phase vector coordinate alpha * @param[in] Ibeta input two-phase vector coordinate beta * @param[out] *pId points to output rotor reference frame d * @param[out] *pIq points to output rotor reference frame q * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * @return none. * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the addition and subtraction, hence there is no risk of overflow. */ static __INLINE void arm_park_q31( q31_t Ialpha, q31_t Ibeta, q31_t * pId, q31_t * pIq, q31_t sinVal, q31_t cosVal) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ q31_t product3, product4; /* Temporary variables used to store intermediate results */ /* Intermediate product is calculated by (Ialpha * cosVal) */ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); /* Intermediate product is calculated by (Ibeta * sinVal) */ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); /* Intermediate product is calculated by (Ialpha * sinVal) */ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); /* Intermediate product is calculated by (Ibeta * cosVal) */ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); /* Calculate pId by adding the two intermediate products 1 and 2 */ *pId = __QADD(product1, product2); /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ *pIq = __QSUB(product4, product3); } /** * @} end of park group */ /** * @brief Converts the elements of the Q7 vector to floating-point vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ void arm_q7_to_float( q7_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @ingroup groupController */ /** * @defgroup inv_park Vector Inverse Park transform * Inverse Park transform converts the input flux and torque components to two-coordinate vector. * * The function operates on a single sample of data and each call to the function returns the processed output. * The library provides separate functions for Q31 and floating-point data types. * \par Algorithm * \image html parkInvFormula.gif * where pIalpha and pIbeta are the stator vector components, * Id and Iq are rotor vector components and cosVal and sinVal are the * cosine and sine values of theta (rotor flux position). * \par Fixed-Point Behavior * Care must be taken when using the Q31 version of the Park transform. * In particular, the overflow and saturation behavior of the accumulator used must be considered. * Refer to the function specific documentation below for usage guidelines. */ /** * @addtogroup inv_park * @{ */ /** * @brief Floating-point Inverse Park transform * @param[in] Id input coordinate of rotor reference frame d * @param[in] Iq input coordinate of rotor reference frame q * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * @return none. */ static __INLINE void arm_inv_park_f32( float32_t Id, float32_t Iq, float32_t * pIalpha, float32_t * pIbeta, float32_t sinVal, float32_t cosVal) { /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ *pIalpha = Id * cosVal - Iq * sinVal; /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ *pIbeta = Id * sinVal + Iq * cosVal; } /** * @brief Inverse Park transform for Q31 version * @param[in] Id input coordinate of rotor reference frame d * @param[in] Iq input coordinate of rotor reference frame q * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta * @param[in] sinVal sine value of rotation angle theta * @param[in] cosVal cosine value of rotation angle theta * @return none. * * Scaling and Overflow Behavior: * \par * The function is implemented using an internal 32-bit accumulator. * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. * There is saturation on the addition, hence there is no risk of overflow. */ static __INLINE void arm_inv_park_q31( q31_t Id, q31_t Iq, q31_t * pIalpha, q31_t * pIbeta, q31_t sinVal, q31_t cosVal) { q31_t product1, product2; /* Temporary variables used to store intermediate results */ q31_t product3, product4; /* Temporary variables used to store intermediate results */ /* Intermediate product is calculated by (Id * cosVal) */ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); /* Intermediate product is calculated by (Iq * sinVal) */ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); /* Intermediate product is calculated by (Id * sinVal) */ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); /* Intermediate product is calculated by (Iq * cosVal) */ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); /* Calculate pIalpha by using the two intermediate products 1 and 2 */ *pIalpha = __QSUB(product1, product2); /* Calculate pIbeta by using the two intermediate products 3 and 4 */ *pIbeta = __QADD(product4, product3); } /** * @} end of Inverse park group */ /** * @brief Converts the elements of the Q31 vector to floating-point vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ void arm_q31_to_float( q31_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @ingroup groupInterpolation */ /** * @defgroup LinearInterpolate Linear Interpolation * * Linear interpolation is a method of curve fitting using linear polynomials. * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line * * \par * \image html LinearInterp.gif "Linear interpolation" * * \par * A Linear Interpolate function calculates an output value(y), for the input(x) * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) * * \par Algorithm: * 
   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
   *       where x0, x1 are nearest values of input x
   *             y0, y1 are nearest values to output y
   *
* * \par * This set of functions implements Linear interpolation process * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single * sample of data and each call to the function returns a single processed value. * S points to an instance of the Linear Interpolate function data structure. * x is the input sample value. The functions returns the output value. * * \par * if x is outside of the table boundary, Linear interpolation returns first value of the table * if x is below input range and returns last value of table if x is above range. */ /** * @addtogroup LinearInterpolate * @{ */ /** * @brief Process function for the floating-point Linear Interpolation Function. * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure * @param[in] x input sample to process * @return y processed output sample. * */ static __INLINE float32_t arm_linear_interp_f32( arm_linear_interp_instance_f32 * S, float32_t x) { float32_t y; float32_t x0, x1; /* Nearest input values */ float32_t y0, y1; /* Nearest output values */ float32_t xSpacing = S->xSpacing; /* spacing between input values */ int32_t i; /* Index variable */ float32_t *pYData = S->pYData; /* pointer to output table */ /* Calculation of index */ i = (int32_t) ((x - S->x1) / xSpacing); if(i < 0) { /* Iniatilize output for below specified range as least output value of table */ y = pYData[0]; } else if((uint32_t)i >= S->nValues) { /* Iniatilize output for above specified range as last output value of table */ y = pYData[S->nValues - 1]; } else { /* Calculation of nearest input values */ x0 = S->x1 + i * xSpacing; x1 = S->x1 + (i + 1) * xSpacing; /* Read of nearest output values */ y0 = pYData[i]; y1 = pYData[i + 1]; /* Calculation of output */ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); } /* returns output value */ return (y); } /** * * @brief Process function for the Q31 Linear Interpolation Function. * @param[in] *pYData pointer to Q31 Linear Interpolation table * @param[in] x input sample to process * @param[in] nValues number of table values * @return y processed output sample. * * \par * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. * This function can support maximum of table size 2^12. * */ static __INLINE q31_t arm_linear_interp_q31( q31_t * pYData, q31_t x, uint32_t nValues) { q31_t y; /* output */ q31_t y0, y1; /* Nearest output values */ q31_t fract; /* fractional part */ int32_t index; /* Index to read nearest output values */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ index = ((x & 0xFFF00000) >> 20); if(index >= (int32_t)(nValues - 1)) { return (pYData[nValues - 1]); } else if(index < 0) { return (pYData[0]); } else { /* 20 bits for the fractional part */ /* shift left by 11 to keep fract in 1.31 format */ fract = (x & 0x000FFFFF) << 11; /* Read two nearest output values from the index in 1.31(q31) format */ y0 = pYData[index]; y1 = pYData[index + 1u]; /* Calculation of y0 * (1-fract) and y is in 2.30 format */ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ y += ((q31_t) (((q63_t) y1 * fract) >> 32)); /* Convert y to 1.31 format */ return (y << 1u); } } /** * * @brief Process function for the Q15 Linear Interpolation Function. * @param[in] *pYData pointer to Q15 Linear Interpolation table * @param[in] x input sample to process * @param[in] nValues number of table values * @return y processed output sample. * * \par * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. * This function can support maximum of table size 2^12. * */ static __INLINE q15_t arm_linear_interp_q15( q15_t * pYData, q31_t x, uint32_t nValues) { q63_t y; /* output */ q15_t y0, y1; /* Nearest output values */ q31_t fract; /* fractional part */ int32_t index; /* Index to read nearest output values */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ index = ((x & 0xFFF00000) >> 20u); if(index >= (int32_t)(nValues - 1)) { return (pYData[nValues - 1]); } else if(index < 0) { return (pYData[0]); } else { /* 20 bits for the fractional part */ /* fract is in 12.20 format */ fract = (x & 0x000FFFFF); /* Read two nearest output values from the index */ y0 = pYData[index]; y1 = pYData[index + 1u]; /* Calculation of y0 * (1-fract) and y is in 13.35 format */ y = ((q63_t) y0 * (0xFFFFF - fract)); /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ y += ((q63_t) y1 * (fract)); /* convert y to 1.15 format */ return (y >> 20); } } /** * * @brief Process function for the Q7 Linear Interpolation Function. * @param[in] *pYData pointer to Q7 Linear Interpolation table * @param[in] x input sample to process * @param[in] nValues number of table values * @return y processed output sample. * * \par * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. * This function can support maximum of table size 2^12. */ static __INLINE q7_t arm_linear_interp_q7( q7_t * pYData, q31_t x, uint32_t nValues) { q31_t y; /* output */ q7_t y0, y1; /* Nearest output values */ q31_t fract; /* fractional part */ uint32_t index; /* Index to read nearest output values */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ if (x < 0) { return (pYData[0]); } index = (x >> 20) & 0xfff; if(index >= (nValues - 1)) { return (pYData[nValues - 1]); } else { /* 20 bits for the fractional part */ /* fract is in 12.20 format */ fract = (x & 0x000FFFFF); /* Read two nearest output values from the index and are in 1.7(q7) format */ y0 = pYData[index]; y1 = pYData[index + 1u]; /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ y = ((y0 * (0xFFFFF - fract))); /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ y += (y1 * fract); /* convert y to 1.7(q7) format */ return (y >> 20u); } } /** * @} end of LinearInterpolate group */ /** * @brief Fast approximation to the trigonometric sine function for floating-point data. * @param[in] x input value in radians. * @return sin(x). */ float32_t arm_sin_f32( float32_t x); /** * @brief Fast approximation to the trigonometric sine function for Q31 data. * @param[in] x Scaled input value in radians. * @return sin(x). */ q31_t arm_sin_q31( q31_t x); /** * @brief Fast approximation to the trigonometric sine function for Q15 data. * @param[in] x Scaled input value in radians. * @return sin(x). */ q15_t arm_sin_q15( q15_t x); /** * @brief Fast approximation to the trigonometric cosine function for floating-point data. * @param[in] x input value in radians. * @return cos(x). */ float32_t arm_cos_f32( float32_t x); /** * @brief Fast approximation to the trigonometric cosine function for Q31 data. * @param[in] x Scaled input value in radians. * @return cos(x). */ q31_t arm_cos_q31( q31_t x); /** * @brief Fast approximation to the trigonometric cosine function for Q15 data. * @param[in] x Scaled input value in radians. * @return cos(x). */ q15_t arm_cos_q15( q15_t x); /** * @ingroup groupFastMath */ /** * @defgroup SQRT Square Root * * Computes the square root of a number. * There are separate functions for Q15, Q31, and floating-point data types. * The square root function is computed using the Newton-Raphson algorithm. * This is an iterative algorithm of the form: * 
   *      x1 = x0 - f(x0)/f'(x0)
   *
* where x1 is the current estimate, * x0 is the previous estimate, and * f'(x0) is the derivative of f() evaluated at x0. * For the square root function, the algorithm reduces to: * 
   *     x0 = in/2                         [initial guess]
   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
   *
*/ /** * @addtogroup SQRT * @{ */ /** * @brief Floating-point square root function. * @param[in] in input value. * @param[out] *pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * in is negative value and returns zero output for negative values. */ static __INLINE arm_status arm_sqrt_f32( float32_t in, float32_t * pOut) { if(in > 0) { // #if __FPU_USED #if (__FPU_USED == 1) && defined ( __CC_ARM ) *pOut = __sqrtf(in); #else *pOut = sqrtf(in); #endif return (ARM_MATH_SUCCESS); } else { *pOut = 0.0f; return (ARM_MATH_ARGUMENT_ERROR); } } /** * @brief Q31 square root function. * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. * @param[out] *pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * in is negative value and returns zero output for negative values. */ arm_status arm_sqrt_q31( q31_t in, q31_t * pOut); /** * @brief Q15 square root function. * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. * @param[out] *pOut square root of input value. * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * in is negative value and returns zero output for negative values. */ arm_status arm_sqrt_q15( q15_t in, q15_t * pOut); /** * @} end of SQRT group */ /** * @brief floating-point Circular write function. */ static __INLINE void arm_circularWrite_f32( int32_t * circBuffer, int32_t L, uint16_t * writeOffset, int32_t bufferInc, const int32_t * src, int32_t srcInc, uint32_t blockSize) { uint32_t i = 0u; int32_t wOffset; /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ wOffset = *writeOffset; /* Loop over the blockSize */ i = blockSize; while(i > 0u) { /* copy the input sample to the circular buffer */ circBuffer[wOffset] = *src; /* Update the input pointer */ src += srcInc; /* Circularly update wOffset. Watch out for positive and negative value */ wOffset += bufferInc; if(wOffset >= L) wOffset -= L; /* Decrement the loop counter */ i--; } /* Update the index pointer */ *writeOffset = wOffset; } /** * @brief floating-point Circular Read function. */ static __INLINE void arm_circularRead_f32( int32_t * circBuffer, int32_t L, int32_t * readOffset, int32_t bufferInc, int32_t * dst, int32_t * dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize) { uint32_t i = 0u; int32_t rOffset, dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ rOffset = *readOffset; dst_end = (int32_t) (dst_base + dst_length); /* Loop over the blockSize */ i = blockSize; while(i > 0u) { /* copy the sample from the circular buffer to the destination buffer */ *dst = circBuffer[rOffset]; /* Update the input pointer */ dst += dstInc; if(dst == (int32_t *) dst_end) { dst = dst_base; } /* Circularly update rOffset. Watch out for positive and negative value */ rOffset += bufferInc; if(rOffset >= L) { rOffset -= L; } /* Decrement the loop counter */ i--; } /* Update the index pointer */ *readOffset = rOffset; } /** * @brief Q15 Circular write function. */ static __INLINE void arm_circularWrite_q15( q15_t * circBuffer, int32_t L, uint16_t * writeOffset, int32_t bufferInc, const q15_t * src, int32_t srcInc, uint32_t blockSize) { uint32_t i = 0u; int32_t wOffset; /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ wOffset = *writeOffset; /* Loop over the blockSize */ i = blockSize; while(i > 0u) { /* copy the input sample to the circular buffer */ circBuffer[wOffset] = *src; /* Update the input pointer */ src += srcInc; /* Circularly update wOffset. Watch out for positive and negative value */ wOffset += bufferInc; if(wOffset >= L) wOffset -= L; /* Decrement the loop counter */ i--; } /* Update the index pointer */ *writeOffset = wOffset; } /** * @brief Q15 Circular Read function. */ static __INLINE void arm_circularRead_q15( q15_t * circBuffer, int32_t L, int32_t * readOffset, int32_t bufferInc, q15_t * dst, q15_t * dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize) { uint32_t i = 0; int32_t rOffset, dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ rOffset = *readOffset; dst_end = (int32_t) (dst_base + dst_length); /* Loop over the blockSize */ i = blockSize; while(i > 0u) { /* copy the sample from the circular buffer to the destination buffer */ *dst = circBuffer[rOffset]; /* Update the input pointer */ dst += dstInc; if(dst == (q15_t *) dst_end) { dst = dst_base; } /* Circularly update wOffset. Watch out for positive and negative value */ rOffset += bufferInc; if(rOffset >= L) { rOffset -= L; } /* Decrement the loop counter */ i--; } /* Update the index pointer */ *readOffset = rOffset; } /** * @brief Q7 Circular write function. */ static __INLINE void arm_circularWrite_q7( q7_t * circBuffer, int32_t L, uint16_t * writeOffset, int32_t bufferInc, const q7_t * src, int32_t srcInc, uint32_t blockSize) { uint32_t i = 0u; int32_t wOffset; /* Copy the value of Index pointer that points * to the current location where the input samples to be copied */ wOffset = *writeOffset; /* Loop over the blockSize */ i = blockSize; while(i > 0u) { /* copy the input sample to the circular buffer */ circBuffer[wOffset] = *src; /* Update the input pointer */ src += srcInc; /* Circularly update wOffset. Watch out for positive and negative value */ wOffset += bufferInc; if(wOffset >= L) wOffset -= L; /* Decrement the loop counter */ i--; } /* Update the index pointer */ *writeOffset = wOffset; } /** * @brief Q7 Circular Read function. */ static __INLINE void arm_circularRead_q7( q7_t * circBuffer, int32_t L, int32_t * readOffset, int32_t bufferInc, q7_t * dst, q7_t * dst_base, int32_t dst_length, int32_t dstInc, uint32_t blockSize) { uint32_t i = 0; int32_t rOffset, dst_end; /* Copy the value of Index pointer that points * to the current location from where the input samples to be read */ rOffset = *readOffset; dst_end = (int32_t) (dst_base + dst_length); /* Loop over the blockSize */ i = blockSize; while(i > 0u) { /* copy the sample from the circular buffer to the destination buffer */ *dst = circBuffer[rOffset]; /* Update the input pointer */ dst += dstInc; if(dst == (q7_t *) dst_end) { dst = dst_base; } /* Circularly update rOffset. Watch out for positive and negative value */ rOffset += bufferInc; if(rOffset >= L) { rOffset -= L; } /* Decrement the loop counter */ i--; } /* Update the index pointer */ *readOffset = rOffset; } /** * @brief Sum of the squares of the elements of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_power_q31( q31_t * pSrc, uint32_t blockSize, q63_t * pResult); /** * @brief Sum of the squares of the elements of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_power_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Sum of the squares of the elements of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_power_q15( q15_t * pSrc, uint32_t blockSize, q63_t * pResult); /** * @brief Sum of the squares of the elements of a Q7 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_power_q7( q7_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Mean value of a Q7 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_mean_q7( q7_t * pSrc, uint32_t blockSize, q7_t * pResult); /** * @brief Mean value of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_mean_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult); /** * @brief Mean value of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_mean_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Mean value of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_mean_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Variance of the elements of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_var_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Variance of the elements of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_var_q31( q31_t * pSrc, uint32_t blockSize, q63_t * pResult); /** * @brief Variance of the elements of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_var_q15( q15_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Root Mean Square of the elements of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_rms_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Root Mean Square of the elements of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_rms_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Root Mean Square of the elements of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_rms_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult); /** * @brief Standard deviation of the elements of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_std_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult); /** * @brief Standard deviation of the elements of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_std_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult); /** * @brief Standard deviation of the elements of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output value. * @return none. */ void arm_std_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult); /** * @brief Floating-point complex magnitude * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector * @return none. */ void arm_cmplx_mag_f32( float32_t * pSrc, float32_t * pDst, uint32_t numSamples); /** * @brief Q31 complex magnitude * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector * @return none. */ void arm_cmplx_mag_q31( q31_t * pSrc, q31_t * pDst, uint32_t numSamples); /** * @brief Q15 complex magnitude * @param[in] *pSrc points to the complex input vector * @param[out] *pDst points to the real output vector * @param[in] numSamples number of complex samples in the input vector * @return none. */ void arm_cmplx_mag_q15( q15_t * pSrc, q15_t * pDst, uint32_t numSamples); /** * @brief Q15 complex dot product * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[in] numSamples number of complex samples in each vector * @param[out] *realResult real part of the result returned here * @param[out] *imagResult imaginary part of the result returned here * @return none. */ void arm_cmplx_dot_prod_q15( q15_t * pSrcA, q15_t * pSrcB, uint32_t numSamples, q31_t * realResult, q31_t * imagResult); /** * @brief Q31 complex dot product * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[in] numSamples number of complex samples in each vector * @param[out] *realResult real part of the result returned here * @param[out] *imagResult imaginary part of the result returned here * @return none. */ void arm_cmplx_dot_prod_q31( q31_t * pSrcA, q31_t * pSrcB, uint32_t numSamples, q63_t * realResult, q63_t * imagResult); /** * @brief Floating-point complex dot product * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[in] numSamples number of complex samples in each vector * @param[out] *realResult real part of the result returned here * @param[out] *imagResult imaginary part of the result returned here * @return none. */ void arm_cmplx_dot_prod_f32( float32_t * pSrcA, float32_t * pSrcB, uint32_t numSamples, float32_t * realResult, float32_t * imagResult); /** * @brief Q15 complex-by-real multiplication * @param[in] *pSrcCmplx points to the complex input vector * @param[in] *pSrcReal points to the real input vector * @param[out] *pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector * @return none. */ void arm_cmplx_mult_real_q15( q15_t * pSrcCmplx, q15_t * pSrcReal, q15_t * pCmplxDst, uint32_t numSamples); /** * @brief Q31 complex-by-real multiplication * @param[in] *pSrcCmplx points to the complex input vector * @param[in] *pSrcReal points to the real input vector * @param[out] *pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector * @return none. */ void arm_cmplx_mult_real_q31( q31_t * pSrcCmplx, q31_t * pSrcReal, q31_t * pCmplxDst, uint32_t numSamples); /** * @brief Floating-point complex-by-real multiplication * @param[in] *pSrcCmplx points to the complex input vector * @param[in] *pSrcReal points to the real input vector * @param[out] *pCmplxDst points to the complex output vector * @param[in] numSamples number of samples in each vector * @return none. */ void arm_cmplx_mult_real_f32( float32_t * pSrcCmplx, float32_t * pSrcReal, float32_t * pCmplxDst, uint32_t numSamples); /** * @brief Minimum value of a Q7 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *result is output pointer * @param[in] index is the array index of the minimum value in the input buffer. * @return none. */ void arm_min_q7( q7_t * pSrc, uint32_t blockSize, q7_t * result, uint32_t * index); /** * @brief Minimum value of a Q15 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output pointer * @param[in] *pIndex is the array index of the minimum value in the input buffer. * @return none. */ void arm_min_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult, uint32_t * pIndex); /** * @brief Minimum value of a Q31 vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output pointer * @param[out] *pIndex is the array index of the minimum value in the input buffer. * @return none. */ void arm_min_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult, uint32_t * pIndex); /** * @brief Minimum value of a floating-point vector. * @param[in] *pSrc is input pointer * @param[in] blockSize is the number of samples to process * @param[out] *pResult is output pointer * @param[out] *pIndex is the array index of the minimum value in the input buffer. * @return none. */ void arm_min_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult, uint32_t * pIndex); /** * @brief Maximum value of a Q7 vector. * @param[in] *pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] *pResult maximum value returned here * @param[out] *pIndex index of maximum value returned here * @return none. */ void arm_max_q7( q7_t * pSrc, uint32_t blockSize, q7_t * pResult, uint32_t * pIndex); /** * @brief Maximum value of a Q15 vector. * @param[in] *pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] *pResult maximum value returned here * @param[out] *pIndex index of maximum value returned here * @return none. */ void arm_max_q15( q15_t * pSrc, uint32_t blockSize, q15_t * pResult, uint32_t * pIndex); /** * @brief Maximum value of a Q31 vector. * @param[in] *pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] *pResult maximum value returned here * @param[out] *pIndex index of maximum value returned here * @return none. */ void arm_max_q31( q31_t * pSrc, uint32_t blockSize, q31_t * pResult, uint32_t * pIndex); /** * @brief Maximum value of a floating-point vector. * @param[in] *pSrc points to the input buffer * @param[in] blockSize length of the input vector * @param[out] *pResult maximum value returned here * @param[out] *pIndex index of maximum value returned here * @return none. */ void arm_max_f32( float32_t * pSrc, uint32_t blockSize, float32_t * pResult, uint32_t * pIndex); /** * @brief Q15 complex-by-complex multiplication * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] numSamples number of complex samples in each vector * @return none. */ void arm_cmplx_mult_cmplx_q15( q15_t * pSrcA, q15_t * pSrcB, q15_t * pDst, uint32_t numSamples); /** * @brief Q31 complex-by-complex multiplication * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] numSamples number of complex samples in each vector * @return none. */ void arm_cmplx_mult_cmplx_q31( q31_t * pSrcA, q31_t * pSrcB, q31_t * pDst, uint32_t numSamples); /** * @brief Floating-point complex-by-complex multiplication * @param[in] *pSrcA points to the first input vector * @param[in] *pSrcB points to the second input vector * @param[out] *pDst points to the output vector * @param[in] numSamples number of complex samples in each vector * @return none. */ void arm_cmplx_mult_cmplx_f32( float32_t * pSrcA, float32_t * pSrcB, float32_t * pDst, uint32_t numSamples); /** * @brief Converts the elements of the floating-point vector to Q31 vector. * @param[in] *pSrc points to the floating-point input vector * @param[out] *pDst points to the Q31 output vector * @param[in] blockSize length of the input vector * @return none. */ void arm_float_to_q31( float32_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the floating-point vector to Q15 vector. * @param[in] *pSrc points to the floating-point input vector * @param[out] *pDst points to the Q15 output vector * @param[in] blockSize length of the input vector * @return none */ void arm_float_to_q15( float32_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the floating-point vector to Q7 vector. * @param[in] *pSrc points to the floating-point input vector * @param[out] *pDst points to the Q7 output vector * @param[in] blockSize length of the input vector * @return none */ void arm_float_to_q7( float32_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q31 vector to Q15 vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ void arm_q31_to_q15( q31_t * pSrc, q15_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q31 vector to Q7 vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ void arm_q31_to_q7( q31_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q15 vector to floating-point vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ void arm_q15_to_float( q15_t * pSrc, float32_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q15 vector to Q31 vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ void arm_q15_to_q31( q15_t * pSrc, q31_t * pDst, uint32_t blockSize); /** * @brief Converts the elements of the Q15 vector to Q7 vector. * @param[in] *pSrc is input pointer * @param[out] *pDst is output pointer * @param[in] blockSize is the number of samples to process * @return none. */ void arm_q15_to_q7( q15_t * pSrc, q7_t * pDst, uint32_t blockSize); /** * @ingroup groupInterpolation */ /** * @defgroup BilinearInterpolate Bilinear Interpolation * * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. * The underlying function f(x, y) is sampled on a regular grid and the interpolation process * determines values between the grid points. * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. * Bilinear interpolation is often used in image processing to rescale images. * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. * * Algorithm * \par * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. * For floating-point, the instance structure is defined as: * 
   *   typedef struct
   *   {
   *     uint16_t numRows;
   *     uint16_t numCols;
   *     float32_t *pData;
   * } arm_bilinear_interp_instance_f32;
   *
* * \par * where numRows specifies the number of rows in the table; * numCols specifies the number of columns in the table; * and pData points to an array of size numRows*numCols values. * The data table pTable is organized in row order and the supplied data values fall on integer indexes. * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. * * \par * Let (x, y) specify the desired interpolation point. Then define: * 
   *     XF = floor(x)
   *     YF = floor(y)
   *
* \par * The interpolated output point is computed as: * 
   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
   *
* Note that the coordinates (x, y) contain integer and fractional components. * The integer components specify which portion of the table to use while the * fractional components control the interpolation processor. * * \par * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. */ /** * @addtogroup BilinearInterpolate * @{ */ /** * * @brief Floating-point bilinear interpolation. * @param[in,out] *S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate. * @param[in] Y interpolation coordinate. * @return out interpolated value. */ static __INLINE float32_t arm_bilinear_interp_f32( const arm_bilinear_interp_instance_f32 * S, float32_t X, float32_t Y) { float32_t out; float32_t f00, f01, f10, f11; float32_t *pData = S->pData; int32_t xIndex, yIndex, index; float32_t xdiff, ydiff; float32_t b1, b2, b3, b4; xIndex = (int32_t) X; yIndex = (int32_t) Y; /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) { return (0); } /* Calculation of index for two nearest points in X-direction */ index = (xIndex - 1) + (yIndex - 1) * S->numCols; /* Read two nearest points in X-direction */ f00 = pData[index]; f01 = pData[index + 1]; /* Calculation of index for two nearest points in Y-direction */ index = (xIndex - 1) + (yIndex) * S->numCols; /* Read two nearest points in Y-direction */ f10 = pData[index]; f11 = pData[index + 1]; /* Calculation of intermediate values */ b1 = f00; b2 = f01 - f00; b3 = f10 - f00; b4 = f00 - f01 - f10 + f11; /* Calculation of fractional part in X */ xdiff = X - xIndex; /* Calculation of fractional part in Y */ ydiff = Y - yIndex; /* Calculation of bi-linear interpolated output */ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; /* return to application */ return (out); } /** * * @brief Q31 bilinear interpolation. * @param[in,out] *S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ static __INLINE q31_t arm_bilinear_interp_q31( arm_bilinear_interp_instance_q31 * S, q31_t X, q31_t Y) { q31_t out; /* Temporary output */ q31_t acc = 0; /* output */ q31_t xfract, yfract; /* X, Y fractional parts */ q31_t x1, x2, y1, y2; /* Nearest output values */ int32_t rI, cI; /* Row and column indices */ q31_t *pYData = S->pData; /* pointer to output table values */ uint32_t nCols = S->numCols; /* num of rows */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ rI = ((X & 0xFFF00000) >> 20u); /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ cI = ((Y & 0xFFF00000) >> 20u); /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { return (0); } /* 20 bits for the fractional part */ /* shift left xfract by 11 to keep 1.31 format */ xfract = (X & 0x000FFFFF) << 11u; /* Read two nearest output values from the index */ x1 = pYData[(rI) + nCols * (cI)]; x2 = pYData[(rI) + nCols * (cI) + 1u]; /* 20 bits for the fractional part */ /* shift left yfract by 11 to keep 1.31 format */ yfract = (Y & 0x000FFFFF) << 11u; /* Read two nearest output values from the index */ y1 = pYData[(rI) + nCols * (cI + 1)]; y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); /* Convert acc to 1.31(q31) format */ return (acc << 2u); } /** * @brief Q15 bilinear interpolation. * @param[in,out] *S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ static __INLINE q15_t arm_bilinear_interp_q15( arm_bilinear_interp_instance_q15 * S, q31_t X, q31_t Y) { q63_t acc = 0; /* output */ q31_t out; /* Temporary output */ q15_t x1, x2, y1, y2; /* Nearest output values */ q31_t xfract, yfract; /* X, Y fractional parts */ int32_t rI, cI; /* Row and column indices */ q15_t *pYData = S->pData; /* pointer to output table values */ uint32_t nCols = S->numCols; /* num of rows */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ rI = ((X & 0xFFF00000) >> 20); /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ cI = ((Y & 0xFFF00000) >> 20); /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { return (0); } /* 20 bits for the fractional part */ /* xfract should be in 12.20 format */ xfract = (X & 0x000FFFFF); /* Read two nearest output values from the index */ x1 = pYData[(rI) + nCols * (cI)]; x2 = pYData[(rI) + nCols * (cI) + 1u]; /* 20 bits for the fractional part */ /* yfract should be in 12.20 format */ yfract = (Y & 0x000FFFFF); /* Read two nearest output values from the index */ y1 = pYData[(rI) + nCols * (cI + 1)]; y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); acc = ((q63_t) out * (0xFFFFF - yfract)); /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); acc += ((q63_t) out * (xfract)); /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); acc += ((q63_t) out * (yfract)); /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); acc += ((q63_t) out * (yfract)); /* acc is in 13.51 format and down shift acc by 36 times */ /* Convert out to 1.15 format */ return (acc >> 36); } /** * @brief Q7 bilinear interpolation. * @param[in,out] *S points to an instance of the interpolation structure. * @param[in] X interpolation coordinate in 12.20 format. * @param[in] Y interpolation coordinate in 12.20 format. * @return out interpolated value. */ static __INLINE q7_t arm_bilinear_interp_q7( arm_bilinear_interp_instance_q7 * S, q31_t X, q31_t Y) { q63_t acc = 0; /* output */ q31_t out; /* Temporary output */ q31_t xfract, yfract; /* X, Y fractional parts */ q7_t x1, x2, y1, y2; /* Nearest output values */ int32_t rI, cI; /* Row and column indices */ q7_t *pYData = S->pData; /* pointer to output table values */ uint32_t nCols = S->numCols; /* num of rows */ /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ rI = ((X & 0xFFF00000) >> 20); /* Input is in 12.20 format */ /* 12 bits for the table index */ /* Index value calculation */ cI = ((Y & 0xFFF00000) >> 20); /* Care taken for table outside boundary */ /* Returns zero output when values are outside table boundary */ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { return (0); } /* 20 bits for the fractional part */ /* xfract should be in 12.20 format */ xfract = (X & 0x000FFFFF); /* Read two nearest output values from the index */ x1 = pYData[(rI) + nCols * (cI)]; x2 = pYData[(rI) + nCols * (cI) + 1u]; /* 20 bits for the fractional part */ /* yfract should be in 12.20 format */ yfract = (Y & 0x000FFFFF); /* Read two nearest output values from the index */ y1 = pYData[(rI) + nCols * (cI + 1)]; y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ out = ((x1 * (0xFFFFF - xfract))); acc = (((q63_t) out * (0xFFFFF - yfract))); /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ out = ((x2 * (0xFFFFF - yfract))); acc += (((q63_t) out * (xfract))); /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ out = ((y1 * (0xFFFFF - xfract))); acc += (((q63_t) out * (yfract))); /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ out = ((y2 * (yfract))); acc += (((q63_t) out * (xfract))); /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ return (acc >> 40); } /** * @} end of BilinearInterpolate group */ #if defined ( __CC_ARM ) //Keil //SMMLAR #define multAcc_32x32_keep32_R(a, x, y) \ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) //SMMLSR #define multSub_32x32_keep32_R(a, x, y) \ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) //SMMULR #define mult_32x32_keep32_R(a, x, y) \ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) //Enter low optimization region - place directly above function definition #define LOW_OPTIMIZATION_ENTER \ _Pragma ("push") \ _Pragma ("O1") //Exit low optimization region - place directly after end of function definition #define LOW_OPTIMIZATION_EXIT \ _Pragma ("pop") //Enter low optimization region - place directly above function definition #define IAR_ONLY_LOW_OPTIMIZATION_ENTER //Exit low optimization region - place directly after end of function definition #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined(__ICCARM__) //IAR //SMMLA #define multAcc_32x32_keep32_R(a, x, y) \ a += (q31_t) (((q63_t) x * y) >> 32) //SMMLS #define multSub_32x32_keep32_R(a, x, y) \ a -= (q31_t) (((q63_t) x * y) >> 32) //SMMUL #define mult_32x32_keep32_R(a, x, y) \ a = (q31_t) (((q63_t) x * y ) >> 32) //Enter low optimization region - place directly above function definition #define LOW_OPTIMIZATION_ENTER \ _Pragma ("optimize=low") //Exit low optimization region - place directly after end of function definition #define LOW_OPTIMIZATION_EXIT //Enter low optimization region - place directly above function definition #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ _Pragma ("optimize=low") //Exit low optimization region - place directly after end of function definition #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #elif defined(__GNUC__) //SMMLA #define multAcc_32x32_keep32_R(a, x, y) \ a += (q31_t) (((q63_t) x * y) >> 32) //SMMLS #define multSub_32x32_keep32_R(a, x, y) \ a -= (q31_t) (((q63_t) x * y) >> 32) //SMMUL #define mult_32x32_keep32_R(a, x, y) \ a = (q31_t) (((q63_t) x * y ) >> 32) #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) #define LOW_OPTIMIZATION_EXIT #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #define IAR_ONLY_LOW_OPTIMIZATION_EXIT #endif #ifdef __cplusplus } #endif #endif /* _ARM_MATH_H */ /** * * End of file. */ ================================================ FILE: Libraries/CMSIS/Include/core_cm0.h ================================================ /**************************************************************************//** * @file core_cm0.h * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File * @version V3.20 * @date 25. February 2013 * * @note * ******************************************************************************/ /* Copyright (c) 2009 - 2013 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #endif #ifdef __cplusplus extern "C" { #endif #ifndef __CORE_CM0_H_GENERIC #define __CORE_CM0_H_GENERIC /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M0 @{ */ /* CMSIS CM0 definitions */ #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ #define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ #define __CORTEX_M (0x00) /*!< Cortex-M Core */ #if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined ( __ICCARM__ ) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __STATIC_INLINE static inline #elif defined ( __GNUC__ ) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __STATIC_INLINE static inline #elif defined ( __TASKING__ ) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline #endif /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0 #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include /* standard types definitions */ #include /* Core Instruction Access */ #include /* Core Function Access */ #endif /* __CORE_CM0_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM0_H_DEPENDANT #define __CORE_CM0_H_DEPENDANT /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0_REV #define __CM0_REV 0x0000 #warning "__CM0_REV not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /*@} end of group Cortex_M0 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { #if (__CORTEX_M != 0x04) uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ #else uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ #endif uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ #if (__CORTEX_M != 0x04) uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ #else uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ #endif uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31]; __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31]; __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31]; __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31]; uint32_t RESERVED4[64]; __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ uint32_t RESERVED0; __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Cortex-M0 Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) /** \brief Enable External Interrupt The function enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); } /** \brief Disable External Interrupt The function disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); } /** \brief Get Pending Interrupt The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); } /** \brief Set Pending Interrupt The function sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); } /** \brief Clear Pending Interrupt The function clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ } /** \brief Set Interrupt Priority The function sets the priority of an interrupt. \note The priority cannot be set for every core interrupt. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if(IRQn < 0) { SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } else { NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } } /** \brief Get Interrupt Priority The function reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { if(IRQn < 0) { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ else { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ } /** \brief System Reset The function initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ while(1); /* wait until reset */ } /*@} end of CMSIS_Core_NVICFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if (__Vendor_SysTickConfig == 0) /** \brief System Tick Configuration The function initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ SysTick->LOAD = ticks - 1; /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ SysTick->VAL = 0; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #endif /* __CORE_CM0_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ #ifdef __cplusplus } #endif ================================================ FILE: Libraries/CMSIS/Include/core_cm0plus.h ================================================ /**************************************************************************//** * @file core_cm0plus.h * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File * @version V3.20 * @date 25. February 2013 * * @note * ******************************************************************************/ /* Copyright (c) 2009 - 2013 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #endif #ifdef __cplusplus extern "C" { #endif #ifndef __CORE_CM0PLUS_H_GENERIC #define __CORE_CM0PLUS_H_GENERIC /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex-M0+ @{ */ /* CMSIS CM0P definitions */ #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ #define __CORTEX_M (0x00) /*!< Cortex-M Core */ #if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined ( __ICCARM__ ) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __STATIC_INLINE static inline #elif defined ( __GNUC__ ) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __STATIC_INLINE static inline #elif defined ( __TASKING__ ) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline #endif /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0 #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include /* standard types definitions */ #include /* Core Instruction Access */ #include /* Core Function Access */ #endif /* __CORE_CM0PLUS_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM0PLUS_H_DEPENDANT #define __CORE_CM0PLUS_H_DEPENDANT /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM0PLUS_REV #define __CM0PLUS_REV 0x0000 #warning "__CM0PLUS_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0 #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __VTOR_PRESENT #define __VTOR_PRESENT 0 #warning "__VTOR_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /*@} end of group Cortex-M0+ */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { #if (__CORTEX_M != 0x04) uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ #else uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ #endif uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ #if (__CORTEX_M != 0x04) uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ #else uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ #endif uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31]; __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31]; __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31]; __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31]; uint32_t RESERVED4[64]; __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ #if (__VTOR_PRESENT == 1) __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ #else uint32_t RESERVED0; #endif __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED1; __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ #if (__VTOR_PRESENT == 1) /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ #if (__MPU_PRESENT == 1) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register */ #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Cortex-M0+ Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #if (__MPU_PRESENT == 1) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) /** \brief Enable External Interrupt The function enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); } /** \brief Disable External Interrupt The function disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); } /** \brief Get Pending Interrupt The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); } /** \brief Set Pending Interrupt The function sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); } /** \brief Clear Pending Interrupt The function clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ } /** \brief Set Interrupt Priority The function sets the priority of an interrupt. \note The priority cannot be set for every core interrupt. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if(IRQn < 0) { SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } else { NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } } /** \brief Get Interrupt Priority The function reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { if(IRQn < 0) { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ else { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ } /** \brief System Reset The function initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ while(1); /* wait until reset */ } /*@} end of CMSIS_Core_NVICFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if (__Vendor_SysTickConfig == 0) /** \brief System Tick Configuration The function initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ SysTick->LOAD = ticks - 1; /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ SysTick->VAL = 0; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #endif /* __CORE_CM0PLUS_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ #ifdef __cplusplus } #endif ================================================ FILE: Libraries/CMSIS/Include/core_cm3.h ================================================ /**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File * @version V3.20 * @date 25. February 2013 * * @note * ******************************************************************************/ /* Copyright (c) 2009 - 2013 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #endif #ifdef __cplusplus extern "C" { #endif #ifndef __CORE_CM3_H_GENERIC #define __CORE_CM3_H_GENERIC /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M3 @{ */ /* CMSIS CM3 definitions */ #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ #define __CORTEX_M (0x03) /*!< Cortex-M Core */ #if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined ( __ICCARM__ ) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __STATIC_INLINE static inline #elif defined ( __TMS470__ ) #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __STATIC_INLINE static inline #elif defined ( __GNUC__ ) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __STATIC_INLINE static inline #elif defined ( __TASKING__ ) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline #endif /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0 #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TMS470__ ) #if defined __TI__VFP_SUPPORT____ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include /* standard types definitions */ #include /* Core Instruction Access */ #include /* Core Function Access */ #endif /* __CORE_CM3_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM3_H_DEPENDANT #define __CORE_CM3_H_DEPENDANT /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM3_REV #define __CM3_REV 0x0200 #warning "__CM3_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0 #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 4 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /*@} end of group Cortex_M3 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { #if (__CORTEX_M != 0x04) uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ #else uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ #endif uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ #if (__CORTEX_M != 0x04) uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ #else uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ #endif uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24]; __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24]; __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24]; __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24]; __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56]; __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644]; __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5]; __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #if (__CM3_REV < 0x0201) /* core r2p1 */ #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #else #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ #endif /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Registers Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Registers Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1]; __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ #else uint32_t RESERVED1[1]; #endif } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __O union { __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864]; __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15]; __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15]; __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29]; __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43]; __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6]; __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1]; __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1]; __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1]; __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2]; __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55]; __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131]; __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759]; __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1]; __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39]; __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8]; __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if (__MPU_PRESENT == 1) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register */ #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register */ #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register */ #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Cortex-M3 Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if (__MPU_PRESENT == 1) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ /** \brief Set Priority Grouping The function sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping The function reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ } /** \brief Enable External Interrupt The function enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ } /** \brief Disable External Interrupt The function disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ } /** \brief Get Pending Interrupt The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ } /** \brief Set Pending Interrupt The function sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ } /** \brief Clear Pending Interrupt The function clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ } /** \brief Get Active Interrupt The function reads the active register in NVIC and returns the active bit. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. */ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ } /** \brief Set Interrupt Priority The function sets the priority of an interrupt. \note The priority cannot be set for every core interrupt. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if(IRQn < 0) { SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ else { NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ } /** \brief Get Interrupt Priority The function reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { if(IRQn < 0) { return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ else { return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ } /** \brief Encode Priority The function encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; return ( ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | ((SubPriority & ((1 << (SubPriorityBits )) - 1))) ); } /** \brief Decode Priority The function decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); } /** \brief System Reset The function initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ while(1); /* wait until reset */ } /*@} end of CMSIS_Core_NVICFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if (__Vendor_SysTickConfig == 0) /** \brief System Tick Configuration The function initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ SysTick->LOAD = ticks - 1; /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ SysTick->VAL = 0; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character The function transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0].u32 == 0); ITM->PORT[0].u8 = (uint8_t) ch; } return (ch); } /** \brief ITM Receive Character The function inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #endif /* __CORE_CM3_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ #ifdef __cplusplus } #endif ================================================ FILE: Libraries/CMSIS/Include/core_cm4.h ================================================ /**************************************************************************//** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File * @version V3.20 * @date 25. February 2013 * * @note * ******************************************************************************/ /* Copyright (c) 2009 - 2013 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #endif #ifdef __cplusplus extern "C" { #endif #ifndef __CORE_CM4_H_GENERIC #define __CORE_CM4_H_GENERIC /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup Cortex_M4 @{ */ /* CMSIS CM4 definitions */ #define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ #define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ #define __CORTEX_M (0x04) /*!< Cortex-M Core */ #if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined ( __ICCARM__ ) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __STATIC_INLINE static inline #elif defined ( __TMS470__ ) #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ #define __STATIC_INLINE static inline #elif defined ( __GNUC__ ) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __STATIC_INLINE static inline #elif defined ( __TASKING__ ) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline #endif /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. */ #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #if (__FPU_PRESENT == 1) #define __FPU_USED 1 #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0 #endif #else #define __FPU_USED 0 #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #if (__FPU_PRESENT == 1) #define __FPU_USED 1 #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0 #endif #else #define __FPU_USED 0 #endif #elif defined ( __TMS470__ ) #if defined __TI_VFP_SUPPORT__ #if (__FPU_PRESENT == 1) #define __FPU_USED 1 #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0 #endif #else #define __FPU_USED 0 #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #if (__FPU_PRESENT == 1) #define __FPU_USED 1 #else #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0 #endif #else #define __FPU_USED 0 #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #if (__FPU_PRESENT == 1) #define __FPU_USED 1 #else #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #define __FPU_USED 0 #endif #else #define __FPU_USED 0 #endif #endif #include /* standard types definitions */ #include /* Core Instruction Access */ #include /* Core Function Access */ #include /* Compiler specific SIMD Intrinsics */ #endif /* __CORE_CM4_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_CM4_H_DEPENDANT #define __CORE_CM4_H_DEPENDANT /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __CM4_REV #define __CM4_REV 0x0000 #warning "__CM4_REV not defined in device header file; using default!" #endif #ifndef __FPU_PRESENT #define __FPU_PRESENT 0 #warning "__FPU_PRESENT not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0 #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 4 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /*@} end of group Cortex_M4 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register - Core FPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { #if (__CORTEX_M != 0x04) uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ #else uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ #endif uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ #if (__CORTEX_M != 0x04) uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ #else uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ #endif uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24]; __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24]; __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24]; __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24]; __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56]; __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644]; __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5]; __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Registers Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Registers Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1]; __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __O union { __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864]; __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15]; __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15]; __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29]; __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43]; __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6]; __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1]; __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1]; __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1]; __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2]; __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55]; __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131]; __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759]; __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1]; __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39]; __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8]; __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if (__MPU_PRESENT == 1) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register */ #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif #if (__FPU_PRESENT == 1) /** \ingroup CMSIS_core_register \defgroup CMSIS_FPU Floating Point Unit (FPU) \brief Type definitions for the Floating Point Unit (FPU) @{ */ /** \brief Structure type to access the Floating Point Unit (FPU). */ typedef struct { uint32_t RESERVED0[1]; __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ } FPU_Type; /* Floating-Point Context Control Register */ #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register */ #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ /* Floating-Point Default Status Control Register */ #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ /* Media and FP Feature Register 0 */ #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 */ #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register */ #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register */ #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Cortex-M4 Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if (__MPU_PRESENT == 1) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif #if (__FPU_PRESENT == 1) #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ /** \brief Set Priority Grouping The function sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping The function reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ } /** \brief Enable External Interrupt The function enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ } /** \brief Disable External Interrupt The function disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ } /** \brief Get Pending Interrupt The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ } /** \brief Set Pending Interrupt The function sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ } /** \brief Clear Pending Interrupt The function clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ } /** \brief Get Active Interrupt The function reads the active register in NVIC and returns the active bit. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. */ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ } /** \brief Set Interrupt Priority The function sets the priority of an interrupt. \note The priority cannot be set for every core interrupt. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if(IRQn < 0) { SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ else { NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ } /** \brief Get Interrupt Priority The function reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { if(IRQn < 0) { return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ else { return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ } /** \brief Encode Priority The function encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; return ( ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | ((SubPriority & ((1 << (SubPriorityBits )) - 1))) ); } /** \brief Decode Priority The function decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); } /** \brief System Reset The function initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ while(1); /* wait until reset */ } /*@} end of CMSIS_Core_NVICFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if (__Vendor_SysTickConfig == 0) /** \brief System Tick Configuration The function initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ SysTick->LOAD = ticks - 1; /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ SysTick->VAL = 0; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character The function transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0].u32 == 0); ITM->PORT[0].u8 = (uint8_t) ch; } return (ch); } /** \brief ITM Receive Character The function inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #endif /* __CORE_CM4_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ #ifdef __cplusplus } #endif ================================================ FILE: Libraries/CMSIS/Include/core_cm4_simd.h ================================================ /**************************************************************************//** * @file core_cm4_simd.h * @brief CMSIS Cortex-M4 SIMD Header File * @version V3.20 * @date 25. February 2013 * * @note * ******************************************************************************/ /* Copyright (c) 2009 - 2013 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #ifdef __cplusplus extern "C" { #endif #ifndef __CORE_CM4_SIMD_H #define __CORE_CM4_SIMD_H /******************************************************************************* * Hardware Abstraction Layer ******************************************************************************/ /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @{ */ #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ #define __SADD8 __sadd8 #define __QADD8 __qadd8 #define __SHADD8 __shadd8 #define __UADD8 __uadd8 #define __UQADD8 __uqadd8 #define __UHADD8 __uhadd8 #define __SSUB8 __ssub8 #define __QSUB8 __qsub8 #define __SHSUB8 __shsub8 #define __USUB8 __usub8 #define __UQSUB8 __uqsub8 #define __UHSUB8 __uhsub8 #define __SADD16 __sadd16 #define __QADD16 __qadd16 #define __SHADD16 __shadd16 #define __UADD16 __uadd16 #define __UQADD16 __uqadd16 #define __UHADD16 __uhadd16 #define __SSUB16 __ssub16 #define __QSUB16 __qsub16 #define __SHSUB16 __shsub16 #define __USUB16 __usub16 #define __UQSUB16 __uqsub16 #define __UHSUB16 __uhsub16 #define __SASX __sasx #define __QASX __qasx #define __SHASX __shasx #define __UASX __uasx #define __UQASX __uqasx #define __UHASX __uhasx #define __SSAX __ssax #define __QSAX __qsax #define __SHSAX __shsax #define __USAX __usax #define __UQSAX __uqsax #define __UHSAX __uhsax #define __USAD8 __usad8 #define __USADA8 __usada8 #define __SSAT16 __ssat16 #define __USAT16 __usat16 #define __UXTB16 __uxtb16 #define __UXTAB16 __uxtab16 #define __SXTB16 __sxtb16 #define __SXTAB16 __sxtab16 #define __SMUAD __smuad #define __SMUADX __smuadx #define __SMLAD __smlad #define __SMLADX __smladx #define __SMLALD __smlald #define __SMLALDX __smlaldx #define __SMUSD __smusd #define __SMUSDX __smusdx #define __SMLSD __smlsd #define __SMLSDX __smlsdx #define __SMLSLD __smlsld #define __SMLSLDX __smlsldx #define __SEL __sel #define __QADD __qadd #define __QSUB __qsub #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ ((int64_t)(ARG3) << 32) ) >> 32)) /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ #include /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ /* TI CCS specific functions */ /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ #include /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } #define __SSAT16(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) #define __USAT16(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } #define __SMLALD(ARG1,ARG2,ARG3) \ ({ \ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ }) #define __SMLALDX(ARG1,ARG2,ARG3) \ ({ \ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ }) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } #define __SMLSLD(ARG1,ARG2,ARG3) \ ({ \ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ }) #define __SMLSLDX(ARG1,ARG2,ARG3) \ ({ \ uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ }) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) { uint32_t result; __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } #define __PKHBT(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) #define __PKHTB(ARG1,ARG2,ARG3) \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ if (ARG3 == 0) \ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ else \ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ /*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ /* not yet supported */ /*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ #endif /*@} end of group CMSIS_SIMD_intrinsics */ #endif /* __CORE_CM4_SIMD_H */ #ifdef __cplusplus } #endif ================================================ FILE: Libraries/CMSIS/Include/core_cmFunc.h ================================================ /**************************************************************************//** * @file core_cmFunc.h * @brief CMSIS Cortex-M Core Function Access Header File * @version V3.20 * @date 25. February 2013 * * @note * ******************************************************************************/ /* Copyright (c) 2009 - 2013 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #ifndef __CORE_CMFUNC_H #define __CORE_CMFUNC_H /* ########################### Core Function Access ########################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions @{ */ #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ #if (__ARMCC_VERSION < 400677) #error "Please use ARM Compiler Toolchain V4.0.677 or later!" #endif /* intrinsic void __enable_irq(); */ /* intrinsic void __disable_irq(); */ /** \brief Get Control Register This function returns the content of the Control Register. \return Control Register value */ __STATIC_INLINE uint32_t __get_CONTROL(void) { register uint32_t __regControl __ASM("control"); return(__regControl); } /** \brief Set Control Register This function writes the given value to the Control Register. \param [in] control Control Register value to set */ __STATIC_INLINE void __set_CONTROL(uint32_t control) { register uint32_t __regControl __ASM("control"); __regControl = control; } /** \brief Get IPSR Register This function returns the content of the IPSR Register. \return IPSR Register value */ __STATIC_INLINE uint32_t __get_IPSR(void) { register uint32_t __regIPSR __ASM("ipsr"); return(__regIPSR); } /** \brief Get APSR Register This function returns the content of the APSR Register. \return APSR Register value */ __STATIC_INLINE uint32_t __get_APSR(void) { register uint32_t __regAPSR __ASM("apsr"); return(__regAPSR); } /** \brief Get xPSR Register This function returns the content of the xPSR Register. \return xPSR Register value */ __STATIC_INLINE uint32_t __get_xPSR(void) { register uint32_t __regXPSR __ASM("xpsr"); return(__regXPSR); } /** \brief Get Process Stack Pointer This function returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __STATIC_INLINE uint32_t __get_PSP(void) { register uint32_t __regProcessStackPointer __ASM("psp"); return(__regProcessStackPointer); } /** \brief Set Process Stack Pointer This function assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { register uint32_t __regProcessStackPointer __ASM("psp"); __regProcessStackPointer = topOfProcStack; } /** \brief Get Main Stack Pointer This function returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __STATIC_INLINE uint32_t __get_MSP(void) { register uint32_t __regMainStackPointer __ASM("msp"); return(__regMainStackPointer); } /** \brief Set Main Stack Pointer This function assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { register uint32_t __regMainStackPointer __ASM("msp"); __regMainStackPointer = topOfMainStack; } /** \brief Get Priority Mask This function returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __STATIC_INLINE uint32_t __get_PRIMASK(void) { register uint32_t __regPriMask __ASM("primask"); return(__regPriMask); } /** \brief Set Priority Mask This function assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { register uint32_t __regPriMask __ASM("primask"); __regPriMask = (priMask); } #if (__CORTEX_M >= 0x03) /** \brief Enable FIQ This function enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __enable_fault_irq __enable_fiq /** \brief Disable FIQ This function disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ #define __disable_fault_irq __disable_fiq /** \brief Get Base Priority This function returns the current value of the Base Priority register. \return Base Priority register value */ __STATIC_INLINE uint32_t __get_BASEPRI(void) { register uint32_t __regBasePri __ASM("basepri"); return(__regBasePri); } /** \brief Set Base Priority This function assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) { register uint32_t __regBasePri __ASM("basepri"); __regBasePri = (basePri & 0xff); } /** \brief Get Fault Mask This function returns the current value of the Fault Mask register. \return Fault Mask register value */ __STATIC_INLINE uint32_t __get_FAULTMASK(void) { register uint32_t __regFaultMask __ASM("faultmask"); return(__regFaultMask); } /** \brief Set Fault Mask This function assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { register uint32_t __regFaultMask __ASM("faultmask"); __regFaultMask = (faultMask & (uint32_t)1); } #endif /* (__CORTEX_M >= 0x03) */ #if (__CORTEX_M == 0x04) /** \brief Get FPSCR This function returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ __STATIC_INLINE uint32_t __get_FPSCR(void) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) register uint32_t __regfpscr __ASM("fpscr"); return(__regfpscr); #else return(0); #endif } /** \brief Set FPSCR This function assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) register uint32_t __regfpscr __ASM("fpscr"); __regfpscr = (fpscr); #endif } #endif /* (__CORTEX_M == 0x04) */ #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ #include #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ /* TI CCS specific functions */ #include #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ /** \brief Enable IRQ Interrupts This function enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) { __ASM volatile ("cpsie i" : : : "memory"); } /** \brief Disable IRQ Interrupts This function disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); } /** \brief Get Control Register This function returns the content of the Control Register. \return Control Register value */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) { uint32_t result; __ASM volatile ("MRS %0, control" : "=r" (result) ); return(result); } /** \brief Set Control Register This function writes the given value to the Control Register. \param [in] control Control Register value to set */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) { __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); } /** \brief Get IPSR Register This function returns the content of the IPSR Register. \return IPSR Register value */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) { uint32_t result; __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); return(result); } /** \brief Get APSR Register This function returns the content of the APSR Register. \return APSR Register value */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) { uint32_t result; __ASM volatile ("MRS %0, apsr" : "=r" (result) ); return(result); } /** \brief Get xPSR Register This function returns the content of the xPSR Register. \return xPSR Register value */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) { uint32_t result; __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); return(result); } /** \brief Get Process Stack Pointer This function returns the current value of the Process Stack Pointer (PSP). \return PSP Register value */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) { register uint32_t result; __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); return(result); } /** \brief Set Process Stack Pointer This function assigns the given value to the Process Stack Pointer (PSP). \param [in] topOfProcStack Process Stack Pointer value to set */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) { __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); } /** \brief Get Main Stack Pointer This function returns the current value of the Main Stack Pointer (MSP). \return MSP Register value */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) { register uint32_t result; __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); return(result); } /** \brief Set Main Stack Pointer This function assigns the given value to the Main Stack Pointer (MSP). \param [in] topOfMainStack Main Stack Pointer value to set */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) { __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); } /** \brief Get Priority Mask This function returns the current state of the priority mask bit from the Priority Mask Register. \return Priority Mask value */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); return(result); } /** \brief Set Priority Mask This function assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); } #if (__CORTEX_M >= 0x03) /** \brief Enable FIQ This function enables FIQ interrupts by clearing the F-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) { __ASM volatile ("cpsie f" : : : "memory"); } /** \brief Disable FIQ This function disables FIQ interrupts by setting the F-bit in the CPSR. Can only be executed in Privileged modes. */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) { __ASM volatile ("cpsid f" : : : "memory"); } /** \brief Get Base Priority This function returns the current value of the Base Priority register. \return Base Priority register value */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) { uint32_t result; __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); return(result); } /** \brief Set Base Priority This function assigns the given value to the Base Priority register. \param [in] basePri Base Priority value to set */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) { __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); } /** \brief Get Fault Mask This function returns the current value of the Fault Mask register. \return Fault Mask register value */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) { uint32_t result; __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); return(result); } /** \brief Set Fault Mask This function assigns the given value to the Fault Mask register. \param [in] faultMask Fault Mask value to set */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) { __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); } #endif /* (__CORTEX_M >= 0x03) */ #if (__CORTEX_M == 0x04) /** \brief Get FPSCR This function returns the current value of the Floating Point Status/Control register. \return Floating Point Status/Control register value */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) uint32_t result; /* Empty asm statement works as a scheduling barrier */ __ASM volatile (""); __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); __ASM volatile (""); return(result); #else return(0); #endif } /** \brief Set FPSCR This function assigns the given value to the Floating Point Status/Control register. \param [in] fpscr Floating Point Status/Control value to set */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) { #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) /* Empty asm statement works as a scheduling barrier */ __ASM volatile (""); __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); __ASM volatile (""); #endif } #endif /* (__CORTEX_M == 0x04) */ #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all instrinsics, * Including the CMSIS ones. */ #endif /*@} end of CMSIS_Core_RegAccFunctions */ #endif /* __CORE_CMFUNC_H */ ================================================ FILE: Libraries/CMSIS/Include/core_cmInstr.h ================================================ /**************************************************************************//** * @file core_cmInstr.h * @brief CMSIS Cortex-M Core Instruction Access Header File * @version V3.20 * @date 05. March 2013 * * @note * ******************************************************************************/ /* Copyright (c) 2009 - 2013 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #ifndef __CORE_CMINSTR_H #define __CORE_CMINSTR_H /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ #if (__ARMCC_VERSION < 400677) #error "Please use ARM Compiler Toolchain V4.0.677 or later!" #endif /** \brief No Operation No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __nop /** \brief Wait For Interrupt Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __wfi /** \brief Wait For Event Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __wfe /** \brief Send Event Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __sev /** \brief Instruction Synchronization Barrier Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() __isb(0xF) /** \brief Data Synchronization Barrier This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() __dsb(0xF) /** \brief Data Memory Barrier This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() __dmb(0xF) /** \brief Reverse byte order (32 bit) This function reverses the byte order in integer value. \param [in] value Value to reverse \return Reversed value */ #define __REV __rev /** \brief Reverse byte order (16 bit) This function reverses the byte order in two unsigned short values. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr } #endif /** \brief Reverse byte order in signed short value This function reverses the byte order in a signed short value with sign extension to integer. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) { revsh r0, r0 bx lr } #endif /** \brief Rotate Right in unsigned value (32 bit) This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] value Value to rotate \param [in] value Number of Bits to rotate \return Rotated value */ #define __ROR __ror /** \brief Breakpoint This function causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __breakpoint(value) #if (__CORTEX_M >= 0x03) /** \brief Reverse bit order of value This function reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #define __RBIT __rbit /** \brief LDR Exclusive (8 bit) This function performs a exclusive LDR command for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) /** \brief LDR Exclusive (16 bit) This function performs a exclusive LDR command for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) /** \brief LDR Exclusive (32 bit) This function performs a exclusive LDR command for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) /** \brief STR Exclusive (8 bit) This function performs a exclusive STR command for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXB(value, ptr) __strex(value, ptr) /** \brief STR Exclusive (16 bit) This function performs a exclusive STR command for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXH(value, ptr) __strex(value, ptr) /** \brief STR Exclusive (32 bit) This function performs a exclusive STR command for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXW(value, ptr) __strex(value, ptr) /** \brief Remove the exclusive lock This function removes the exclusive lock which is created by LDREX. */ #define __CLREX __clrex /** \brief Signed Saturate This function saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __ssat /** \brief Unsigned Saturate This function saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __usat /** \brief Count leading zeros This function counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ __clz #endif /* (__CORTEX_M >= 0x03) */ #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ #include #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ /* TI CCS specific functions */ #include #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constrant "l" * Otherwise, use general registers, specified by constrant "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** \brief No Operation No Operation does nothing. This instruction can be used for code alignment purposes. */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) { __ASM volatile ("nop"); } /** \brief Wait For Interrupt Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) { __ASM volatile ("wfi"); } /** \brief Wait For Event Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) { __ASM volatile ("wfe"); } /** \brief Send Event Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) { __ASM volatile ("sev"); } /** \brief Instruction Synchronization Barrier Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) { __ASM volatile ("isb"); } /** \brief Data Synchronization Barrier This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) { __ASM volatile ("dsb"); } /** \brief Data Memory Barrier This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) { __ASM volatile ("dmb"); } /** \brief Reverse byte order (32 bit) This function reverses the byte order in integer value. \param [in] value Value to reverse \return Reversed value */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) return __builtin_bswap32(value); #else uint32_t result; __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); #endif } /** \brief Reverse byte order (16 bit) This function reverses the byte order in two unsigned short values. \param [in] value Value to reverse \return Reversed value */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) { uint32_t result; __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief Reverse byte order in signed short value This function reverses the byte order in a signed short value with sign extension to integer. \param [in] value Value to reverse \return Reversed value */ __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) return (short)__builtin_bswap16(value); #else uint32_t result; __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); #endif } /** \brief Rotate Right in unsigned value (32 bit) This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] value Value to rotate \param [in] value Number of Bits to rotate \return Rotated value */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { return (op1 >> op2) | (op1 << (32 - op2)); } /** \brief Breakpoint This function causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) #if (__CORTEX_M >= 0x03) /** \brief Reverse bit order of value This function reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); return(result); } /** \brief LDR Exclusive (8 bit) This function performs a exclusive LDR command for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return(result); } /** \brief LDR Exclusive (16 bit) This function performs a exclusive LDR command for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return(result); } /** \brief LDR Exclusive (32 bit) This function performs a exclusive LDR command for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); return(result); } /** \brief STR Exclusive (8 bit) This function performs a exclusive STR command for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { uint32_t result; __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); return(result); } /** \brief STR Exclusive (16 bit) This function performs a exclusive STR command for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { uint32_t result; __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); return(result); } /** \brief STR Exclusive (32 bit) This function performs a exclusive STR command for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); return(result); } /** \brief Remove the exclusive lock This function removes the exclusive lock which is created by LDREX. */ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) { __ASM volatile ("clrex" ::: "memory"); } /** \brief Signed Saturate This function saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) /** \brief Unsigned Saturate This function saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) /** \brief Count leading zeros This function counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) { uint32_t result; __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); return(result); } #endif /* (__CORTEX_M >= 0x03) */ #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all intrinsics, * Including the CMSIS ones. */ #endif /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ #endif /* __CORE_CMINSTR_H */ ================================================ FILE: Libraries/CMSIS/Include/core_sc000.h ================================================ /**************************************************************************//** * @file core_sc000.h * @brief CMSIS SC000 Core Peripheral Access Layer Header File * @version V3.20 * @date 25. February 2013 * * @note * ******************************************************************************/ /* Copyright (c) 2009 - 2013 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #endif #ifdef __cplusplus extern "C" { #endif #ifndef __CORE_SC000_H_GENERIC #define __CORE_SC000_H_GENERIC /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup SC000 @{ */ /* CMSIS SC000 definitions */ #define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ #define __SC000_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ #define __CORTEX_SC (0) /*!< Cortex secure core */ #if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined ( __ICCARM__ ) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __STATIC_INLINE static inline #elif defined ( __GNUC__ ) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __STATIC_INLINE static inline #elif defined ( __TASKING__ ) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline #endif /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0 #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include /* standard types definitions */ #include /* Core Instruction Access */ #include /* Core Function Access */ #endif /* __CORE_SC000_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_SC000_H_DEPENDANT #define __CORE_SC000_H_DEPENDANT /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __SC000_REV #define __SC000_REV 0x0000 #warning "__SC000_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0 #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 2 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /*@} end of group SC000 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { #if (__CORTEX_M != 0x04) uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ #else uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ #endif uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ #if (__CORTEX_M != 0x04) uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ #else uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ #endif uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[31]; __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[31]; __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[31]; __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[31]; uint32_t RESERVED4[64]; __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ } NVIC_Type; /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ uint32_t RESERVED0[1]; __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ uint32_t RESERVED1[154]; __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ /* SCB Security Features Register Definitions */ #define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ #define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ #define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ #define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[2]; __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ } SCnSCB_Type; /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ #if (__MPU_PRESENT == 1) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register */ #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. Therefore they are not covered by the Cortex-M0 header file. @{ */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of SC000 Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #if (__MPU_PRESENT == 1) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) /** \brief Enable External Interrupt The function enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); } /** \brief Disable External Interrupt The function disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); } /** \brief Get Pending Interrupt The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); } /** \brief Set Pending Interrupt The function sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); } /** \brief Clear Pending Interrupt The function clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ } /** \brief Set Interrupt Priority The function sets the priority of an interrupt. \note The priority cannot be set for every core interrupt. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if(IRQn < 0) { SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } else { NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } } /** \brief Get Interrupt Priority The function reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { if(IRQn < 0) { return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ else { return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ } /** \brief System Reset The function initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ while(1); /* wait until reset */ } /*@} end of CMSIS_Core_NVICFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if (__Vendor_SysTickConfig == 0) /** \brief System Tick Configuration The function initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ SysTick->LOAD = ticks - 1; /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ SysTick->VAL = 0; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ #endif /* __CORE_SC000_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ #ifdef __cplusplus } #endif ================================================ FILE: Libraries/CMSIS/Include/core_sc300.h ================================================ /**************************************************************************//** * @file core_sc300.h * @brief CMSIS SC300 Core Peripheral Access Layer Header File * @version V3.20 * @date 25. February 2013 * * @note * ******************************************************************************/ /* Copyright (c) 2009 - 2013 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #endif #ifdef __cplusplus extern "C" { #endif #ifndef __CORE_SC300_H_GENERIC #define __CORE_SC300_H_GENERIC /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions CMSIS violates the following MISRA-C:2004 rules: \li Required Rule 8.5, object/function definition in header file.
Function definitions in header files are used to allow 'inlining'. \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
Unions are used for effective representation of core registers. \li Advisory Rule 19.7, Function-like macro defined.
Function-like macros are used to allow more efficient code. */ /******************************************************************************* * CMSIS definitions ******************************************************************************/ /** \ingroup SC3000 @{ */ /* CMSIS SC300 definitions */ #define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ #define __SC300_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ #define __CORTEX_SC (300) /*!< Cortex secure core */ #if defined ( __CC_ARM ) #define __ASM __asm /*!< asm keyword for ARM Compiler */ #define __INLINE __inline /*!< inline keyword for ARM Compiler */ #define __STATIC_INLINE static __inline #elif defined ( __ICCARM__ ) #define __ASM __asm /*!< asm keyword for IAR Compiler */ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ #define __STATIC_INLINE static inline #elif defined ( __GNUC__ ) #define __ASM __asm /*!< asm keyword for GNU Compiler */ #define __INLINE inline /*!< inline keyword for GNU Compiler */ #define __STATIC_INLINE static inline #elif defined ( __TASKING__ ) #define __ASM __asm /*!< asm keyword for TASKING Compiler */ #define __INLINE inline /*!< inline keyword for TASKING Compiler */ #define __STATIC_INLINE static inline #endif /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all */ #define __FPU_USED 0 #if defined ( __CC_ARM ) #if defined __TARGET_FPU_VFP #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __ICCARM__ ) #if defined __ARMVFP__ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __GNUC__ ) #if defined (__VFP_FP__) && !defined(__SOFTFP__) #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #elif defined ( __TASKING__ ) #if defined __FPU_VFP__ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" #endif #endif #include /* standard types definitions */ #include /* Core Instruction Access */ #include /* Core Function Access */ #endif /* __CORE_SC300_H_GENERIC */ #ifndef __CMSIS_GENERIC #ifndef __CORE_SC300_H_DEPENDANT #define __CORE_SC300_H_DEPENDANT /* check device defines and use defaults */ #if defined __CHECK_DEVICE_DEFINES #ifndef __SC300_REV #define __SC300_REV 0x0000 #warning "__SC300_REV not defined in device header file; using default!" #endif #ifndef __MPU_PRESENT #define __MPU_PRESENT 0 #warning "__MPU_PRESENT not defined in device header file; using default!" #endif #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 4 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" #endif #ifndef __Vendor_SysTickConfig #define __Vendor_SysTickConfig 0 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" #endif #endif /* IO definitions (access restrictions to peripheral registers) */ /** \defgroup CMSIS_glob_defs CMSIS Global Defines IO Type Qualifiers are used \li to specify the access to peripheral variables. \li for automatic generation of peripheral register debug information. */ #ifdef __cplusplus #define __I volatile /*!< Defines 'read only' permissions */ #else #define __I volatile const /*!< Defines 'read only' permissions */ #endif #define __O volatile /*!< Defines 'write only' permissions */ #define __IO volatile /*!< Defines 'read / write' permissions */ /*@} end of group SC300 */ /******************************************************************************* * Register Abstraction Core Register contain: - Core Register - Core NVIC Register - Core SCB Register - Core SysTick Register - Core Debug Register - Core MPU Register ******************************************************************************/ /** \defgroup CMSIS_core_register Defines and Type Definitions \brief Type definitions and defines for Cortex-M processor based devices. */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CORE Status and Control Registers \brief Core Register type definitions. @{ */ /** \brief Union type to access the Application Program Status Register (APSR). */ typedef union { struct { #if (__CORTEX_M != 0x04) uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ #else uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ #endif uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } APSR_Type; /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } IPSR_Type; /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ typedef union { struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ #if (__CORTEX_M != 0x04) uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ #else uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ #endif uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ uint32_t N:1; /*!< bit: 31 Negative condition code flag */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } xPSR_Type; /** \brief Union type to access the Control Registers (CONTROL). */ typedef union { struct { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; /*@} end of group CMSIS_CORE */ /** \ingroup CMSIS_core_register \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) \brief Type definitions for the NVIC Registers @{ */ /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). */ typedef struct { __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ uint32_t RESERVED0[24]; __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ uint32_t RSERVED1[24]; __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ uint32_t RESERVED2[24]; __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ uint32_t RESERVED3[24]; __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ uint32_t RESERVED4[56]; __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ uint32_t RESERVED5[644]; __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ } NVIC_Type; /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCB System Control Block (SCB) \brief Type definitions for the System Control Block Registers @{ */ /** \brief Structure type to access the System Control Block (SCB). */ typedef struct { __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5]; __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ /* SCB Configuration Control Register Definitions */ #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Registers Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Registers Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ /* SCB Debug Fault Status Register Definitions */ #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) \brief Type definitions for the System Control and ID Register not in the SCB @{ */ /** \brief Structure type to access the System Control and ID Register not in the SCB. */ typedef struct { uint32_t RESERVED0[1]; __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ uint32_t RESERVED1[1]; } SCnSCB_Type; /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ /** \ingroup CMSIS_core_register \defgroup CMSIS_SysTick System Tick Timer (SysTick) \brief Type definitions for the System Timer Registers. @{ */ /** \brief Structure type to access the System Timer (SysTick). */ typedef struct { __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ } SysTick_Type; /* SysTick Control / Status Register Definitions */ #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ /** \ingroup CMSIS_core_register \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) \brief Type definitions for the Instrumentation Trace Macrocell (ITM) @{ */ /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). */ typedef struct { __O union { __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ uint32_t RESERVED0[864]; __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ uint32_t RESERVED1[15]; __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15]; __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ uint32_t RESERVED3[29]; __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ uint32_t RESERVED4[43]; __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ uint32_t RESERVED5[6]; __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ } ITM_Type; /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ /** \ingroup CMSIS_core_register \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) \brief Type definitions for the Data Watchpoint and Trace (DWT) @{ */ /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). */ typedef struct { __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ uint32_t RESERVED0[1]; __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ uint32_t RESERVED1[1]; __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ uint32_t RESERVED2[1]; __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ } DWT_Type; /* DWT Control Register Definitions */ #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ /** \ingroup CMSIS_core_register \defgroup CMSIS_TPI Trace Port Interface (TPI) \brief Type definitions for the Trace Port Interface (TPI) @{ */ /** \brief Structure type to access the Trace Port Interface Register (TPI). */ typedef struct { __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2]; __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ uint32_t RESERVED1[55]; __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ uint32_t RESERVED2[131]; __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ uint32_t RESERVED3[759]; __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ uint32_t RESERVED4[1]; __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39]; __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8]; __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ /*@}*/ /* end of group CMSIS_TPI */ #if (__MPU_PRESENT == 1) /** \ingroup CMSIS_core_register \defgroup CMSIS_MPU Memory Protection Unit (MPU) \brief Type definitions for the Memory Protection Unit (MPU) @{ */ /** \brief Structure type to access the Memory Protection Unit (MPU). */ typedef struct { __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ } MPU_Type; /* MPU Type Register */ #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) \brief Type definitions for the Core Debug Registers @{ */ /** \brief Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register */ #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register */ #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ /** \ingroup CMSIS_core_register \defgroup CMSIS_core_base Core Definitions \brief Definitions for base addresses, unions, and structures. @{ */ /* Memory mapping of Cortex-M3 Hardware */ #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ #if (__MPU_PRESENT == 1) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ #endif /*@} */ /******************************************************************************* * Hardware Abstraction Layer Core Function Interface contains: - Core NVIC Functions - Core SysTick Functions - Core Debug Functions - Core Register Access Functions ******************************************************************************/ /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference */ /* ########################## NVIC functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_NVICFunctions NVIC Functions \brief Functions that manage interrupts and exceptions via the NVIC. @{ */ /** \brief Set Priority Grouping The function sets the priority grouping field using the required unlock sequence. The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } /** \brief Get Priority Grouping The function reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ } /** \brief Enable External Interrupt The function enables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ } /** \brief Disable External Interrupt The function disables a device-specific interrupt in the NVIC interrupt controller. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ } /** \brief Get Pending Interrupt The function reads the pending register in the NVIC and returns the pending bit for the specified interrupt. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not pending. \return 1 Interrupt status is pending. */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ } /** \brief Set Pending Interrupt The function sets the pending bit of an external interrupt. \param [in] IRQn Interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ } /** \brief Clear Pending Interrupt The function clears the pending bit of an external interrupt. \param [in] IRQn External interrupt number. Value cannot be negative. */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ } /** \brief Get Active Interrupt The function reads the active register in NVIC and returns the active bit. \param [in] IRQn Interrupt number. \return 0 Interrupt status is not active. \return 1 Interrupt status is active. */ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ } /** \brief Set Interrupt Priority The function sets the priority of an interrupt. \note The priority cannot be set for every core interrupt. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { if(IRQn < 0) { SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ else { NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ } /** \brief Get Interrupt Priority The function reads the priority of an interrupt. The interrupt number can be positive to specify an external (device specific) interrupt, or negative to specify an internal (core) interrupt. \param [in] IRQn Interrupt number. \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. */ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { if(IRQn < 0) { return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ else { return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ } /** \brief Encode Priority The function encodes the priority for an interrupt with the given priority group, preemptive priority value, and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. \param [in] PriorityGroup Used priority group. \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; return ( ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | ((SubPriority & ((1 << (SubPriorityBits )) - 1))) ); } /** \brief Decode Priority The function decodes an interrupt priority value with a given priority group to preemptive priority value and subpriority value. In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). \param [in] PriorityGroup Used priority group. \param [out] pPreemptPriority Preemptive priority value (starting from 0). \param [out] pSubPriority Subpriority value (starting from 0). */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) { uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); } /** \brief System Reset The function initiates a system reset request to reset the MCU. */ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ __DSB(); /* Ensure completion of memory access */ while(1); /* wait until reset */ } /*@} end of CMSIS_Core_NVICFunctions */ /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_SysTickFunctions SysTick Functions \brief Functions that configure the System. @{ */ #if (__Vendor_SysTickConfig == 0) /** \brief System Tick Configuration The function initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts. \param [in] ticks Number of ticks between two interrupts. \return 0 Function succeeded. \return 1 Function failed. \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ SysTick->LOAD = ticks - 1; /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ SysTick->VAL = 0; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0); /* Function successful */ } #endif /*@} end of CMSIS_Core_SysTickFunctions */ /* ##################################### Debug In/Output function ########################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_core_DebugFunctions ITM Functions \brief Functions that access the ITM debug interface. @{ */ extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ /** \brief ITM Send Character The function transmits a character via the ITM channel 0, and \li Just returns when no debugger is connected that has booked the output. \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. \param [in] ch Character to transmit. \returns Character to transmit. */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ { while (ITM->PORT[0].u32 == 0); ITM->PORT[0].u8 = (uint8_t) ch; } return (ch); } /** \brief ITM Receive Character The function inputs a character via the external variable \ref ITM_RxBuffer. \return Received character. \return -1 No character pending. */ __STATIC_INLINE int32_t ITM_ReceiveChar (void) { int32_t ch = -1; /* no character available */ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { ch = ITM_RxBuffer; ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ } return (ch); } /** \brief ITM Check Character The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. \return 0 No character available. \return 1 Character available. */ __STATIC_INLINE int32_t ITM_CheckChar (void) { if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { return (0); /* no character available */ } else { return (1); /* character available */ } } /*@} end of CMSIS_core_DebugFunctions */ #endif /* __CORE_SC300_H_DEPENDANT */ #endif /* __CMSIS_GENERIC */ #ifdef __cplusplus } #endif ================================================ FILE: Libraries/CMSIS/README.txt ================================================ * ------------------------------------------------------------------- * Copyright (C) 2011-2013 ARM Limited. All rights reserved. * * Date: 18 March 2013 * Revision: V3.20 * * Project: Cortex Microcontroller Software Interface Standard (CMSIS) * Title: Release Note for CMSIS * * ------------------------------------------------------------------- NOTE - Open the index.html file to access CMSIS documentation The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects and reduces time-to-market for new embedded applications. CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf"). Any user of the software package is bound to the terms and conditions of the end user license agreement. You will find the following sub-directories: Documentation - Contains CMSIS documentation. DSP_Lib - MDK project files, Examples and source files etc.. to build the CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors. Include - CMSIS Core Support and CMSIS DSP Include Files. Lib - CMSIS DSP Libraries. RTOS - CMSIS RTOS API template header file. SVD - CMSIS SVD Schema files and Conversion Utility. ================================================ FILE: Libraries/CMSIS/index.html ================================================  Redirect to the CMSIS main page after 0 seconds If the automatic redirection is failing, click open CMSIS Documentation. ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/Release_Notes.html ================================================ Release Notes for STM32F4xx Standard Peripherals Library Drivers

 

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Release Notes for STM32F4xx Standard Peripherals  Drivers

Copyright 2013 STMicroelectronics

 

Contents

  1. STM32F4xx Standard Peripherals Library Drivers update History
  2. License

STM32F4xx Standard Peripherals Library Drivers  update History


V1.3.0 / 08-November-2013

Main Changes

  • Add support of STM32F401xExx devices
  • stm32f4xx_gpio.c/h
    • Update GPIOSpeed_TypeDef structures fields name to be in line with GPIO out speed definition in the product Reference Manual
    • Add a legacy defines to keep compatibility with previous version
  • stm32f4xx_flash.c/h
    • Files header comments: update description of the maximum AHB frequency vs. voltage scaling configuration

V1.2.1 / 19-September-2013

Main Changes

  • stm32f4xx_pwr.c/.h 

    • Add new function to configure the Under-Drive STOP Mode : PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) only used in case of STM32F427/437/429/439xx devices.

V1.2.0 / 11-September-2013

Main Changes

  • Add support of STM32F429/439xx and STM32F401xCxx devices

  • Update definition of STM32F427/437xx devices : extension of the features to include system clock up to 180MHz, dual bank Flash, reduced STOP Mode current, SAI, PCROP, SDRAM and DMA2D
  • Add drivers for new peripherals of STM32F4xx STM32F427/437xx and STM32F429/439xx devices:
    • stm32f4xx_dma2d.h/.c
    • stm32f4xx_fmc.h/.c
    • stm32f4xx_ltdc.h/.c
    • stm32f4xx_sai.h/.c

  • stm32f4xx_adc.c/.h 

    • Update the Temperature sensor channel for STM32F427/STM32F437x/STM32F429x/STM32F439x devices from Channel 16 to Channel 18

    • Add a note in ADC_VBATCmd() header function to inform that the Voltage measured is VBAT/2 in case of STM3240xxx/41xxx and VBAT/4 in case of STM32F42xxx/43xxx.

    • In ADC_GetSoftwareStartConvStatus() function, replace "ADC_CR2_JSWSTART" by "ADC_CR2_SWSTART"

  • stm32f4xx_flash.c/.h
    • Update the header file descriptioon, add the table of number of wait states according to system frequency selected for all STM32F4xx family devices
    • Update FLASH_EraseAllSectors() function to support the erase for all sectors within Bank1 and Bank2 in case of STM32F42/43xxx devices
    • Add new FLASH Latency values: FLASH_Latency_8, FLASH_Latency_9, FLASH_Latency_10, FLASH_Latency_11, FLASH_Latency_12, FLASH_Latency_13, FLASH_Latency_14, FLASH_Latency_15.
    • Add new flag error in FLASH_Status structure: " FLASH_ERROR_RD"
    • Add new functions: 
      • FLASH_EraseAllBank1Sectors(): mass erase in bank 1 (Half mass erase)
      • FLASH_EraseAllBank2Sectors(): mass erase in Bank 2 (Half mass erase)
      • FLASH_OB_BootConfig(): configure Dual bank boot mode
      • FLASH_OB_PCROPSelectionConfig(): select PCROP feature
      • FLASH_OB_WRP1Config(): configure write protection from Sector 12 to sector 23
      • FLASH_OB_PCROPConfig(): configure PC read/write protection from Sector 0 to sector 11
      • FLASH_OB_PCROP1Config(): configure PC read/write protection from Sector12 to sector23
      • FLASH_OB_GetWRP1(): Read the write protected sectors from 12 to 23
      • FLASH_OB_GetPCROP(): Read the PC read/write protected sectors from 0 to 11
      • FLASH_OB_GetPCROP1(): Read the PC read/write protected sectors from 12 to 23
  • stm32f4xx_gpio.c/.h
    • Update GPIO_DeInit() function : Add GPIOJ, GPIOK clock reset/enable
    • Add a new alternate function for I2C2 and I2C3 :
      • #define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping */
      • #define GPIO_AF9_I2C3          ((uint8_t)0x09)  /* I2C3 Alternate Function mapping */
    • Update all functions header comments.
  • stm32f4xx_rcc.c/.h
    • Add new definitions for new peripherals: SAI1, LTDC, FMC
    • Add a new parameter in RCC_PLLI2SConfig() function : PLLI2SQ to specifies the division factor for SAI1 clock
    • Add new functions: 
      • RCC_PLLSAIConfig(), RCC_PLLSAICmd(): PLL SAI Clock configuration
      • Add new function RCC_SAICLKConfig(): SAI clock division factors configuration
      • RCC_LCDCLKConfig(): LCD clock division factors configuration
  • stm32l1xx_syscfg.c/.h
    • Add new SYSCFG port sources configurations : EXTI_PortSourceGPIOJ, EXTI_PortSourceGPIOK
    • Add new function SYSCFG_MemorySwappingBank(): swap between bank 1 and Bank 2

  • stm32f4xx_pwr.c/.h  

    • Add more details and update comments in functions and groups description

    • Add the following functions to configure the Over-drive and Under-drive Modes :

      • PWR_OverDriveCmd()

      • PWR_OverDriveSWCmd()

      • PWR_UnderDriveCmd()

V1.1.0 / 11-Janury-2013

Main Changes

  • Official release for STM32F427x/437x devices.
  • stm32f4xx_cryp.c/.h
    • Update CRYP_Init() function : add the support for new algorithms (GCM/CCM).
    • Add new function : CRYP_PhaseConfig() used for new AES-GCM and AES-CCM algorithms.
    • CRYP_InitTypeDef structure : update all structure fields from uint16_t to uint32_t and update all driver functions  parameters and the correpondant define to be declared with uint32_t type.
    • Replace the "CRYP_ContextSave->CR_bits9to2" by "CRYP_ContextSave->CurrentConfig".
  • stm32f4xx_flash.c/.h
    • Update FLASH sectors numbers "FLASH_Sector_x" with x = 0..23.
    • Update FLASH_EraseAllSectors() function to support mass erase for STM32F427x/437x devices.
  • stm32f4xx_gpio.c/.h
    • Add Alternate functions for new peripherals: SPI4, SPI5, SPI6, UART7, UART8.
    • Update all functions header comment.
  • stm32f4xx_hash.c/.h
    • Update HASH_GetDigest() function : add the HASH_DIGEST structure.
    • Add new function HASH_AutoStartDigest().
    • Update HASH_MsgDigest structure: to support SHA-224 and SHA-256 modes.
    •  Update HASH_Context structure.
    • Update some define using bit definitions already declared in stm32f4xx.h.
  • stm32f4xx_i2c.c/.h
    • Add new functions:
      • I2C_AnalogFilterCmd(): enable/disable the analog I2C filters.
      • I2C_DigitalFilterConfig(): configure the digital I2C filters.
  • stm32f4xx_pwr.c/.h
    • Add new argument "PWR_Regulator_Voltage_Scale3"  to PWR_MainRegulatorModeConfig() function to be in line with Reference Manual description.
  • stm32f4xx_rcc.c/.h
    • Add new definitions for new peripherals: SPI4, SPI5, SPI6, SAI1, UART7, UART8.
    • Add a new parameter in RCC_PLLI2SConfig() function : PLLI2SQ to specifies the division factor for SAI1 clock.
    • Add RCC_TIMCLKPresConfig() function : TIMER Prescaler selection. 
  • stm32l1xx_spi.c/.h
    • Update to support SPI4, SPI5, SPI6.
    • Update all functions header comment.
  • stm32l1xx_usart.c/.h
    • Update to support UART7 and UART8.
    • Update all functions header comment.

V1.0.2 / 05-March-2012

Main Changes

  • All source files: license disclaimer text update and add link to the License file on ST Internet.
  • stm32f4xx_dcmi.c
    • DCMI_GetFlagStatus() function: fix test condition on RISR register, use if (dcmireg == 0x00) instead of if (dcmireg == 0x01)
  • stm32f4xx_pwr.c
    • PWR_PVDLevelConfig() function: remove value of the voltage threshold corresponding to each PVD detection level, user should refer to the electrical characteristics of the STM32 device datasheet to have the correct value

V1.0.1 / 28-December-2011

Main Changes

  • All source files: update disclaimer to add reference to the new license agreement
  • stm32f4xx_rtc.c: 
    • In RTC_FLAGS_MASK define: add RTC_FLAG_RECALPF and RTC_FLAG_SHPF
    • RTC_DeInit() function: add reset of the following registers: SHIFTR, CALR, ALRMASSR and ALRMBSSR
    • RTC_SetTime() and RTC_SetDate() functions: add test condition on BYPSHAD flag before to test RSF flag (when Bypass mode is enabled, the RSF bit is never set).

V1.0.0 / 30-September-2011

Main Changes

  • First official release for STM32F40x/41x devices
  • stm32f4xx_rtc.c: remove useless code from RTC_GetDate() function
  • stm32f4xx_rcc.c, stm32f4xx_spi.c, stm32f4xx_wwdg.c and stm32f4xx_syscfg.c: driver's comments update

V1.0.0RC2 / 26-September-2011

Main Changes

  • Official version (V1.0.0) Release Candidate1 for STM32F40x/STM32F41x devices
  • stm32f4xx_usart.h/.c
    • Update procedure to check on overrun error interrupt pending bit, defines for the following flag are added:
      • USART_IT_ORE_RX: this flag is set if overrun error interrupt occurs and RXNEIE bit is set
      • USART_IT_ORE_ER: this flag is set if overrun error interrupt occurs and EIE bit is set
  • stm32f4xx_tim.c
    • TIM_UpdateRequestConfig(): correct function header's comment 
    • TIM_ICInit(): add assert macros to test if the passed TIM parameter has channel 2, 3 or 4
  • stm32f4xx_pwr.h/.c
    • Rename PWR_FLAG_REGRDY constant to PWR_CSR_REGRDY
    • Rename PWR_FLAG_VOSRDY constant to PWR_CSR_VOSRDY
    • Rename PWR_HighPerformanceModeCmd(FunctionalState NewState) function to PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage)
  • stm32f4xx_rcc.h/.c
    • RCC_AHB1PeriphClockCmd(): add new constant RCC_AHB1Periph_CCMDATARAMEN as value for RCC_AHB1Periph parameter
  • stm32f4xx_spi.h
    • IS_I2S_EXT_PERIPH(): add check on I2S3ext peripheral

V1.0.0RC1 / 25-August-2011

Main Changes

  • Official version (V1.0.0) Release Candidate1 for STM32F4xx devices

License

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at:


Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

For complete documentation on STM32 Microcontrollers visit www.st.com/STM32

 

================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h ================================================ /** ****************************************************************************** * @file misc.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the miscellaneous * firmware library functions (add-on to CMSIS functions). ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __MISC_H #define __MISC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup MISC * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief NVIC Init Structure definition */ typedef struct { uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. This parameter can be an enumerator of @ref IRQn_Type enumeration (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file) */ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel specified in NVIC_IRQChannel. This parameter can be a value between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table A lower priority value indicates a higher priority */ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified in NVIC_IRQChannel. This parameter can be a value between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table A lower priority value indicates a higher priority */ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel will be enabled or disabled. This parameter can be set either to ENABLE or DISABLE */ } NVIC_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup MISC_Exported_Constants * @{ */ /** @defgroup MISC_Vector_Table_Base * @{ */ #define NVIC_VectTab_RAM ((uint32_t)0x20000000) #define NVIC_VectTab_FLASH ((uint32_t)0x08000000) #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ ((VECTTAB) == NVIC_VectTab_FLASH)) /** * @} */ /** @defgroup MISC_System_Low_Power * @{ */ #define NVIC_LP_SEVONPEND ((uint8_t)0x10) #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ ((LP) == NVIC_LP_SLEEPDEEP) || \ ((LP) == NVIC_LP_SLEEPONEXIT)) /** * @} */ /** @defgroup MISC_Preemption_Priority_Group * @{ */ #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */ #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */ #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */ #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */ #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */ #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ ((GROUP) == NVIC_PriorityGroup_1) || \ ((GROUP) == NVIC_PriorityGroup_2) || \ ((GROUP) == NVIC_PriorityGroup_3) || \ ((GROUP) == NVIC_PriorityGroup_4)) #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) /** * @} */ /** @defgroup MISC_SysTick_clock_source * @{ */ #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); #ifdef __cplusplus } #endif #endif /* __MISC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h ================================================ /** ****************************************************************************** * @file stm32f4xx_adc.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the ADC firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_ADC_H #define __STM32F4xx_ADC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup ADC * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief ADC Init structure definition */ typedef struct { uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode. This parameter can be a value of @ref ADC_resolution */ FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in Scan (multichannels) or Single (one channel) mode. This parameter can be set to ENABLE or DISABLE */ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode. This parameter can be set to ENABLE or DISABLE. */ uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger of a regular group. This parameter can be a value of @ref ADC_external_trigger_edge_for_regular_channels_conversion */ uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion of a regular group. This parameter can be a value of @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. This parameter can be a value of @ref ADC_data_align */ uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for regular channel group. This parameter must range from 1 to 16. */ }ADC_InitTypeDef; /** * @brief ADC Common Init structure definition */ typedef struct { uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or multi mode. This parameter can be a value of @ref ADC_Common_mode */ uint32_t ADC_Prescaler; /*!< Select the frequency of the clock to the ADC. The clock is common for all the ADCs. This parameter can be a value of @ref ADC_Prescaler */ uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode. This parameter can be a value of @ref ADC_Direct_memory_access_mode_for_multi_mode */ uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */ }ADC_CommonInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup ADC_Exported_Constants * @{ */ #define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ ((PERIPH) == ADC2) || \ ((PERIPH) == ADC3)) /** @defgroup ADC_Common_mode * @{ */ #define ADC_Mode_Independent ((uint32_t)0x00000000) #define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001) #define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002) #define ADC_DualMode_InjecSimult ((uint32_t)0x00000005) #define ADC_DualMode_RegSimult ((uint32_t)0x00000006) #define ADC_DualMode_Interl ((uint32_t)0x00000007) #define ADC_DualMode_AlterTrig ((uint32_t)0x00000009) #define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011) #define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012) #define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015) #define ADC_TripleMode_RegSimult ((uint32_t)0x00000016) #define ADC_TripleMode_Interl ((uint32_t)0x00000017) #define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019) #define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \ ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \ ((MODE) == ADC_DualMode_InjecSimult) || \ ((MODE) == ADC_DualMode_RegSimult) || \ ((MODE) == ADC_DualMode_Interl) || \ ((MODE) == ADC_DualMode_AlterTrig) || \ ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \ ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \ ((MODE) == ADC_TripleMode_InjecSimult) || \ ((MODE) == ADC_TripleMode_RegSimult) || \ ((MODE) == ADC_TripleMode_Interl) || \ ((MODE) == ADC_TripleMode_AlterTrig)) /** * @} */ /** @defgroup ADC_Prescaler * @{ */ #define ADC_Prescaler_Div2 ((uint32_t)0x00000000) #define ADC_Prescaler_Div4 ((uint32_t)0x00010000) #define ADC_Prescaler_Div6 ((uint32_t)0x00020000) #define ADC_Prescaler_Div8 ((uint32_t)0x00030000) #define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \ ((PRESCALER) == ADC_Prescaler_Div4) || \ ((PRESCALER) == ADC_Prescaler_Div6) || \ ((PRESCALER) == ADC_Prescaler_Div8)) /** * @} */ /** @defgroup ADC_Direct_memory_access_mode_for_multi_mode * @{ */ #define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */ #define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ #define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ #define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ #define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \ ((MODE) == ADC_DMAAccessMode_1) || \ ((MODE) == ADC_DMAAccessMode_2) || \ ((MODE) == ADC_DMAAccessMode_3)) /** * @} */ /** @defgroup ADC_delay_between_2_sampling_phases * @{ */ #define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000) #define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100) #define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200) #define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300) #define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400) #define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500) #define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600) #define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700) #define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800) #define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900) #define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00) #define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00) #define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00) #define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00) #define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00) #define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00) #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \ ((DELAY) == ADC_TwoSamplingDelay_20Cycles)) /** * @} */ /** @defgroup ADC_resolution * @{ */ #define ADC_Resolution_12b ((uint32_t)0x00000000) #define ADC_Resolution_10b ((uint32_t)0x01000000) #define ADC_Resolution_8b ((uint32_t)0x02000000) #define ADC_Resolution_6b ((uint32_t)0x03000000) #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ ((RESOLUTION) == ADC_Resolution_10b) || \ ((RESOLUTION) == ADC_Resolution_8b) || \ ((RESOLUTION) == ADC_Resolution_6b)) /** * @} */ /** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion * @{ */ #define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) #define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000) #define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000) #define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000) #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) /** * @} */ /** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion * @{ */ #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000) #define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000) #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000) #define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000) #define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000) #define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000) #define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000) #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000) #define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000) #define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000) #define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000) #define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000) #define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000) #define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000) #define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000) #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \ ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \ ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)) /** * @} */ /** @defgroup ADC_data_align * @{ */ #define ADC_DataAlign_Right ((uint32_t)0x00000000) #define ADC_DataAlign_Left ((uint32_t)0x00000800) #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ ((ALIGN) == ADC_DataAlign_Left)) /** * @} */ /** @defgroup ADC_channels * @{ */ #define ADC_Channel_0 ((uint8_t)0x00) #define ADC_Channel_1 ((uint8_t)0x01) #define ADC_Channel_2 ((uint8_t)0x02) #define ADC_Channel_3 ((uint8_t)0x03) #define ADC_Channel_4 ((uint8_t)0x04) #define ADC_Channel_5 ((uint8_t)0x05) #define ADC_Channel_6 ((uint8_t)0x06) #define ADC_Channel_7 ((uint8_t)0x07) #define ADC_Channel_8 ((uint8_t)0x08) #define ADC_Channel_9 ((uint8_t)0x09) #define ADC_Channel_10 ((uint8_t)0x0A) #define ADC_Channel_11 ((uint8_t)0x0B) #define ADC_Channel_12 ((uint8_t)0x0C) #define ADC_Channel_13 ((uint8_t)0x0D) #define ADC_Channel_14 ((uint8_t)0x0E) #define ADC_Channel_15 ((uint8_t)0x0F) #define ADC_Channel_16 ((uint8_t)0x10) #define ADC_Channel_17 ((uint8_t)0x11) #define ADC_Channel_18 ((uint8_t)0x12) #if defined (STM32F40_41xxx) #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) #endif /* STM32F40_41xxx */ #if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18) #endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx */ #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) #define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18) #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \ ((CHANNEL) == ADC_Channel_1) || \ ((CHANNEL) == ADC_Channel_2) || \ ((CHANNEL) == ADC_Channel_3) || \ ((CHANNEL) == ADC_Channel_4) || \ ((CHANNEL) == ADC_Channel_5) || \ ((CHANNEL) == ADC_Channel_6) || \ ((CHANNEL) == ADC_Channel_7) || \ ((CHANNEL) == ADC_Channel_8) || \ ((CHANNEL) == ADC_Channel_9) || \ ((CHANNEL) == ADC_Channel_10) || \ ((CHANNEL) == ADC_Channel_11) || \ ((CHANNEL) == ADC_Channel_12) || \ ((CHANNEL) == ADC_Channel_13) || \ ((CHANNEL) == ADC_Channel_14) || \ ((CHANNEL) == ADC_Channel_15) || \ ((CHANNEL) == ADC_Channel_16) || \ ((CHANNEL) == ADC_Channel_17) || \ ((CHANNEL) == ADC_Channel_18)) /** * @} */ /** @defgroup ADC_sampling_times * @{ */ #define ADC_SampleTime_3Cycles ((uint8_t)0x00) #define ADC_SampleTime_15Cycles ((uint8_t)0x01) #define ADC_SampleTime_28Cycles ((uint8_t)0x02) #define ADC_SampleTime_56Cycles ((uint8_t)0x03) #define ADC_SampleTime_84Cycles ((uint8_t)0x04) #define ADC_SampleTime_112Cycles ((uint8_t)0x05) #define ADC_SampleTime_144Cycles ((uint8_t)0x06) #define ADC_SampleTime_480Cycles ((uint8_t)0x07) #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \ ((TIME) == ADC_SampleTime_15Cycles) || \ ((TIME) == ADC_SampleTime_28Cycles) || \ ((TIME) == ADC_SampleTime_56Cycles) || \ ((TIME) == ADC_SampleTime_84Cycles) || \ ((TIME) == ADC_SampleTime_112Cycles) || \ ((TIME) == ADC_SampleTime_144Cycles) || \ ((TIME) == ADC_SampleTime_480Cycles)) /** * @} */ /** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion * @{ */ #define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000) #define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000) #define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000) #define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000) #define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \ ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \ ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling)) /** * @} */ /** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion * @{ */ #define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000) #define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000) #define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000) #define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000) #define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000) #define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000) #define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000) #define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000) #define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000) #define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000) #define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000) #define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000) #define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000) #define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000) #define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000) #define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000) #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)) /** * @} */ /** @defgroup ADC_injected_channel_selection * @{ */ #define ADC_InjectedChannel_1 ((uint8_t)0x14) #define ADC_InjectedChannel_2 ((uint8_t)0x18) #define ADC_InjectedChannel_3 ((uint8_t)0x1C) #define ADC_InjectedChannel_4 ((uint8_t)0x20) #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ ((CHANNEL) == ADC_InjectedChannel_2) || \ ((CHANNEL) == ADC_InjectedChannel_3) || \ ((CHANNEL) == ADC_InjectedChannel_4)) /** * @} */ /** @defgroup ADC_analog_watchdog_selection * @{ */ #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ ((WATCHDOG) == ADC_AnalogWatchdog_None)) /** * @} */ /** @defgroup ADC_interrupts_definition * @{ */ #define ADC_IT_EOC ((uint16_t)0x0205) #define ADC_IT_AWD ((uint16_t)0x0106) #define ADC_IT_JEOC ((uint16_t)0x0407) #define ADC_IT_OVR ((uint16_t)0x201A) #define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) /** * @} */ /** @defgroup ADC_flags_definition * @{ */ #define ADC_FLAG_AWD ((uint8_t)0x01) #define ADC_FLAG_EOC ((uint8_t)0x02) #define ADC_FLAG_JEOC ((uint8_t)0x04) #define ADC_FLAG_JSTRT ((uint8_t)0x08) #define ADC_FLAG_STRT ((uint8_t)0x10) #define ADC_FLAG_OVR ((uint8_t)0x20) #define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00)) #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \ ((FLAG) == ADC_FLAG_EOC) || \ ((FLAG) == ADC_FLAG_JEOC) || \ ((FLAG)== ADC_FLAG_JSTRT) || \ ((FLAG) == ADC_FLAG_STRT) || \ ((FLAG)== ADC_FLAG_OVR)) /** * @} */ /** @defgroup ADC_thresholds * @{ */ #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) /** * @} */ /** @defgroup ADC_injected_offset * @{ */ #define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) /** * @} */ /** @defgroup ADC_injected_length * @{ */ #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) /** * @} */ /** @defgroup ADC_injected_rank * @{ */ #define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) /** * @} */ /** @defgroup ADC_regular_length * @{ */ #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) /** * @} */ /** @defgroup ADC_regular_rank * @{ */ #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) /** * @} */ /** @defgroup ADC_regular_discontinuous_mode_number * @{ */ #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the ADC configuration to the default reset state *****/ void ADC_DeInit(void); /* Initialization and Configuration functions *********************************/ void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); /* Analog Watchdog configuration functions ************************************/ void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); /* Temperature Sensor, Vrefint and VBAT management functions ******************/ void ADC_TempSensorVrefintCmd(FunctionalState NewState); void ADC_VBATCmd(FunctionalState NewState); /* Regular Channels Configuration functions ***********************************/ void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); void ADC_SoftwareStartConv(ADC_TypeDef* ADCx); FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); uint32_t ADC_GetMultiModeConversionValue(void); /* Regular Channels DMA Configuration functions *******************************/ void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState); /* Injected channels Configuration functions **********************************/ void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge); void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx); FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); /* Interrupts and flags management functions **********************************/ void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_ADC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h ================================================ /** ****************************************************************************** * @file stm32f4xx_can.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the CAN firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_CAN_H #define __STM32F4xx_CAN_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup CAN * @{ */ /* Exported types ------------------------------------------------------------*/ #define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ ((PERIPH) == CAN2)) /** * @brief CAN init structure definition */ typedef struct { uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */ uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. This parameter can be a value of @ref CAN_operating_mode */ uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform resynchronization. This parameter can be a value of @ref CAN_synchronisation_jump_width */ uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1. This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. This parameter can be set either to ENABLE or DISABLE. */ FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. This parameter can be set either to ENABLE or DISABLE. */ } CAN_InitTypeDef; /** * @brief CAN filter init structure definition */ typedef struct { uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). This parameter can be a value between 0x0000 and 0xFFFF */ uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. This parameter can be a value of @ref CAN_filter_mode */ uint8_t CAN_FilterScale; /*!< Specifies the filter scale. This parameter can be a value of @ref CAN_filter_scale */ FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. This parameter can be set either to ENABLE or DISABLE. */ } CAN_FilterInitTypeDef; /** * @brief CAN Tx message structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF. */ uint32_t ExtId; /*!< Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF. */ uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. This parameter can be a value of @ref CAN_identifier_type */ uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. This parameter can be a value of @ref CAN_remote_transmission_request */ uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted. This parameter can be a value between 0 to 8 */ uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */ } CanTxMsg; /** * @brief CAN Rx message structure definition */ typedef struct { uint32_t StdId; /*!< Specifies the standard identifier. This parameter can be a value between 0 to 0x7FF. */ uint32_t ExtId; /*!< Specifies the extended identifier. This parameter can be a value between 0 to 0x1FFFFFFF. */ uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received. This parameter can be a value of @ref CAN_identifier_type */ uint8_t RTR; /*!< Specifies the type of frame for the received message. This parameter can be a value of @ref CAN_remote_transmission_request */ uint8_t DLC; /*!< Specifies the length of the frame that will be received. This parameter can be a value between 0 to 8 */ uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */ uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. This parameter can be a value between 0 to 0xFF */ } CanRxMsg; /* Exported constants --------------------------------------------------------*/ /** @defgroup CAN_Exported_Constants * @{ */ /** @defgroup CAN_InitStatus * @{ */ #define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ #define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ /* Legacy defines */ #define CANINITFAILED CAN_InitStatus_Failed #define CANINITOK CAN_InitStatus_Success /** * @} */ /** @defgroup CAN_operating_mode * @{ */ #define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ #define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ #define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ #define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ #define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ ((MODE) == CAN_Mode_LoopBack)|| \ ((MODE) == CAN_Mode_Silent) || \ ((MODE) == CAN_Mode_Silent_LoopBack)) /** * @} */ /** * @defgroup CAN_operating_mode * @{ */ #define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ #define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ #define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ #define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ ((MODE) == CAN_OperatingMode_Normal)|| \ ((MODE) == CAN_OperatingMode_Sleep)) /** * @} */ /** * @defgroup CAN_operating_mode_status * @{ */ #define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ #define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ /** * @} */ /** @defgroup CAN_synchronisation_jump_width * @{ */ #define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ #define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ #define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ #define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) /** * @} */ /** @defgroup CAN_time_quantum_in_bit_segment_1 * @{ */ #define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ #define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ #define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ #define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ #define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ #define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ #define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ #define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ #define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ #define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ #define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ #define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ #define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ #define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ #define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ #define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) /** * @} */ /** @defgroup CAN_time_quantum_in_bit_segment_2 * @{ */ #define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ #define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ #define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ #define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ #define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ #define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ #define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ #define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) /** * @} */ /** @defgroup CAN_clock_prescaler * @{ */ #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) /** * @} */ /** @defgroup CAN_filter_number * @{ */ #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) /** * @} */ /** @defgroup CAN_filter_mode * @{ */ #define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ #define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ ((MODE) == CAN_FilterMode_IdList)) /** * @} */ /** @defgroup CAN_filter_scale * @{ */ #define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ #define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ ((SCALE) == CAN_FilterScale_32bit)) /** * @} */ /** @defgroup CAN_filter_FIFO * @{ */ #define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ #define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ ((FIFO) == CAN_FilterFIFO1)) /* Legacy defines */ #define CAN_FilterFIFO0 CAN_Filter_FIFO0 #define CAN_FilterFIFO1 CAN_Filter_FIFO1 /** * @} */ /** @defgroup CAN_Start_bank_filter_for_slave_CAN * @{ */ #define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) /** * @} */ /** @defgroup CAN_Tx * @{ */ #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) #define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) #define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) /** * @} */ /** @defgroup CAN_identifier_type * @{ */ #define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ #define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ ((IDTYPE) == CAN_Id_Extended)) /* Legacy defines */ #define CAN_ID_STD CAN_Id_Standard #define CAN_ID_EXT CAN_Id_Extended /** * @} */ /** @defgroup CAN_remote_transmission_request * @{ */ #define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ #define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) /* Legacy defines */ #define CAN_RTR_DATA CAN_RTR_Data #define CAN_RTR_REMOTE CAN_RTR_Remote /** * @} */ /** @defgroup CAN_transmit_constants * @{ */ #define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ #define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ #define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ #define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ /* Legacy defines */ #define CANTXFAILED CAN_TxStatus_Failed #define CANTXOK CAN_TxStatus_Ok #define CANTXPENDING CAN_TxStatus_Pending #define CAN_NO_MB CAN_TxStatus_NoMailBox /** * @} */ /** @defgroup CAN_receive_FIFO_number_constants * @{ */ #define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ #define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) /** * @} */ /** @defgroup CAN_sleep_constants * @{ */ #define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ #define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ /* Legacy defines */ #define CANSLEEPFAILED CAN_Sleep_Failed #define CANSLEEPOK CAN_Sleep_Ok /** * @} */ /** @defgroup CAN_wake_up_constants * @{ */ #define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ #define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ /* Legacy defines */ #define CANWAKEUPFAILED CAN_WakeUp_Failed #define CANWAKEUPOK CAN_WakeUp_Ok /** * @} */ /** * @defgroup CAN_Error_Code_constants * @{ */ #define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ #define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ #define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ #define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ #define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ #define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ #define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ #define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ /** * @} */ /** @defgroup CAN_flags * @{ */ /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() and CAN_ClearFlag() functions. */ /* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */ /* Transmit Flags */ #define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ #define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ #define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ /* Receive Flags */ #define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ #define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ #define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ #define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ #define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ #define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ /* Operating Mode Flags */ #define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ #define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. In this case the SLAK bit can be polled.*/ /* Error Flags */ #define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ #define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ #define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ #define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ #define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ ((FLAG) == CAN_FLAG_SLAK )) #define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) /** * @} */ /** @defgroup CAN_interrupts * @{ */ #define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ /* Receive Interrupts */ #define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ #define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ #define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ #define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ #define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ #define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ /* Operating Mode Interrupts */ #define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ #define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ /* Error Interrupts */ #define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ #define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ #define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ #define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ #define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ /* Flags named as Interrupts : kept only for FW compatibility */ #define CAN_IT_RQCP0 CAN_IT_TME #define CAN_IT_RQCP1 CAN_IT_TME #define CAN_IT_RQCP2 CAN_IT_TME #define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) #define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the CAN configuration to the default reset state *****/ void CAN_DeInit(CAN_TypeDef* CANx); /* Initialization and Configuration functions *********************************/ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); void CAN_SlaveStartBank(uint8_t CAN_BankNumber); void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); /* CAN Frames Transmission functions ******************************************/ uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); /* CAN Frames Reception functions *********************************************/ void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); /* Operation modes functions **************************************************/ uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); uint8_t CAN_Sleep(CAN_TypeDef* CANx); uint8_t CAN_WakeUp(CAN_TypeDef* CANx); /* CAN Bus Error management functions *****************************************/ uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); /* Interrupts and flags management functions **********************************/ void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_CAN_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h ================================================ /** ****************************************************************************** * @file stm32f4xx_crc.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the CRC firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_CRC_H #define __STM32F4xx_CRC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup CRC * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup CRC_Exported_Constants * @{ */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ void CRC_ResetDR(void); uint32_t CRC_CalcCRC(uint32_t Data); uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); uint32_t CRC_GetCRC(void); void CRC_SetIDRegister(uint8_t IDValue); uint8_t CRC_GetIDRegister(void); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_CRC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h ================================================ /** ****************************************************************************** * @file stm32f4xx_cryp.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the Cryptographic * processor(CRYP) firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_CRYP_H #define __STM32F4xx_CRYP_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup CRYP * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief CRYP Init structure definition */ typedef struct { uint32_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a value of @ref CRYP_Algorithm_Direction */ uint32_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, AES-CBC, AES-CTR, AES-Key, AES-GCM and AES-CCM. This parameter can be a value of @ref CRYP_Algorithm_Mode */ uint32_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit string. This parameter can be a value of @ref CRYP_Data_Type */ uint32_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit key length. This parameter can be a value of @ref CRYP_Key_Size_for_AES_only */ }CRYP_InitTypeDef; /** * @brief CRYP Key(s) structure definition */ typedef struct { uint32_t CRYP_Key0Left; /*!< Key 0 Left */ uint32_t CRYP_Key0Right; /*!< Key 0 Right */ uint32_t CRYP_Key1Left; /*!< Key 1 left */ uint32_t CRYP_Key1Right; /*!< Key 1 Right */ uint32_t CRYP_Key2Left; /*!< Key 2 left */ uint32_t CRYP_Key2Right; /*!< Key 2 Right */ uint32_t CRYP_Key3Left; /*!< Key 3 left */ uint32_t CRYP_Key3Right; /*!< Key 3 Right */ }CRYP_KeyInitTypeDef; /** * @brief CRYP Initialization Vectors (IV) structure definition */ typedef struct { uint32_t CRYP_IV0Left; /*!< Init Vector 0 Left */ uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */ uint32_t CRYP_IV1Left; /*!< Init Vector 1 left */ uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */ }CRYP_IVInitTypeDef; /** * @brief CRYP context swapping structure definition */ typedef struct { /*!< Current Configuration */ uint32_t CR_CurrentConfig; /*!< IV */ uint32_t CRYP_IV0LR; uint32_t CRYP_IV0RR; uint32_t CRYP_IV1LR; uint32_t CRYP_IV1RR; /*!< KEY */ uint32_t CRYP_K0LR; uint32_t CRYP_K0RR; uint32_t CRYP_K1LR; uint32_t CRYP_K1RR; uint32_t CRYP_K2LR; uint32_t CRYP_K2RR; uint32_t CRYP_K3LR; uint32_t CRYP_K3RR; uint32_t CRYP_CSGCMCCMR[8]; uint32_t CRYP_CSGCMR[8]; }CRYP_Context; /* Exported constants --------------------------------------------------------*/ /** @defgroup CRYP_Exported_Constants * @{ */ /** @defgroup CRYP_Algorithm_Direction * @{ */ #define CRYP_AlgoDir_Encrypt ((uint16_t)0x0000) #define CRYP_AlgoDir_Decrypt ((uint16_t)0x0004) #define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \ ((ALGODIR) == CRYP_AlgoDir_Decrypt)) /** * @} */ /** @defgroup CRYP_Algorithm_Mode * @{ */ /*!< TDES Modes */ #define CRYP_AlgoMode_TDES_ECB ((uint32_t)0x00000000) #define CRYP_AlgoMode_TDES_CBC ((uint32_t)0x00000008) /*!< DES Modes */ #define CRYP_AlgoMode_DES_ECB ((uint32_t)0x00000010) #define CRYP_AlgoMode_DES_CBC ((uint32_t)0x00000018) /*!< AES Modes */ #define CRYP_AlgoMode_AES_ECB ((uint32_t)0x00000020) #define CRYP_AlgoMode_AES_CBC ((uint32_t)0x00000028) #define CRYP_AlgoMode_AES_CTR ((uint32_t)0x00000030) #define CRYP_AlgoMode_AES_Key ((uint32_t)0x00000038) #define CRYP_AlgoMode_AES_GCM ((uint32_t)0x00080000) #define CRYP_AlgoMode_AES_CCM ((uint32_t)0x00080008) #define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \ ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \ ((ALGOMODE) == CRYP_AlgoMode_DES_ECB) || \ ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \ ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \ ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \ ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \ ((ALGOMODE) == CRYP_AlgoMode_AES_Key) || \ ((ALGOMODE) == CRYP_AlgoMode_AES_GCM) || \ ((ALGOMODE) == CRYP_AlgoMode_AES_CCM)) /** * @} */ /** @defgroup CRYP_Phase * @{ */ /*!< The phases are valid only for AES-GCM and AES-CCM modes */ #define CRYP_Phase_Init ((uint32_t)0x00000000) #define CRYP_Phase_Header CRYP_CR_GCM_CCMPH_0 #define CRYP_Phase_Payload CRYP_CR_GCM_CCMPH_1 #define CRYP_Phase_Final CRYP_CR_GCM_CCMPH #define IS_CRYP_PHASE(PHASE) (((PHASE) == CRYP_Phase_Init) || \ ((PHASE) == CRYP_Phase_Header) || \ ((PHASE) == CRYP_Phase_Payload) || \ ((PHASE) == CRYP_Phase_Final)) /** * @} */ /** @defgroup CRYP_Data_Type * @{ */ #define CRYP_DataType_32b ((uint16_t)0x0000) #define CRYP_DataType_16b ((uint16_t)0x0040) #define CRYP_DataType_8b ((uint16_t)0x0080) #define CRYP_DataType_1b ((uint16_t)0x00C0) #define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \ ((DATATYPE) == CRYP_DataType_16b)|| \ ((DATATYPE) == CRYP_DataType_8b)|| \ ((DATATYPE) == CRYP_DataType_1b)) /** * @} */ /** @defgroup CRYP_Key_Size_for_AES_only * @{ */ #define CRYP_KeySize_128b ((uint16_t)0x0000) #define CRYP_KeySize_192b ((uint16_t)0x0100) #define CRYP_KeySize_256b ((uint16_t)0x0200) #define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \ ((KEYSIZE) == CRYP_KeySize_192b)|| \ ((KEYSIZE) == CRYP_KeySize_256b)) /** * @} */ /** @defgroup CRYP_flags_definition * @{ */ #define CRYP_FLAG_BUSY ((uint8_t)0x10) /*!< The CRYP core is currently processing a block of data or a key preparation (for AES decryption). */ #define CRYP_FLAG_IFEM ((uint8_t)0x01) /*!< Input Fifo Empty */ #define CRYP_FLAG_IFNF ((uint8_t)0x02) /*!< Input Fifo is Not Full */ #define CRYP_FLAG_INRIS ((uint8_t)0x22) /*!< Raw interrupt pending */ #define CRYP_FLAG_OFNE ((uint8_t)0x04) /*!< Input Fifo service raw interrupt status */ #define CRYP_FLAG_OFFU ((uint8_t)0x08) /*!< Output Fifo is Full */ #define CRYP_FLAG_OUTRIS ((uint8_t)0x21) /*!< Output Fifo service raw interrupt status */ #define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM) || \ ((FLAG) == CRYP_FLAG_IFNF) || \ ((FLAG) == CRYP_FLAG_OFNE) || \ ((FLAG) == CRYP_FLAG_OFFU) || \ ((FLAG) == CRYP_FLAG_BUSY) || \ ((FLAG) == CRYP_FLAG_OUTRIS)|| \ ((FLAG) == CRYP_FLAG_INRIS)) /** * @} */ /** @defgroup CRYP_interrupts_definition * @{ */ #define CRYP_IT_INI ((uint8_t)0x01) /*!< IN Fifo Interrupt */ #define CRYP_IT_OUTI ((uint8_t)0x02) /*!< OUT Fifo Interrupt */ #define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00)) #define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI)) /** * @} */ /** @defgroup CRYP_Encryption_Decryption_modes_definition * @{ */ #define MODE_ENCRYPT ((uint8_t)0x01) #define MODE_DECRYPT ((uint8_t)0x00) /** * @} */ /** @defgroup CRYP_DMA_transfer_requests * @{ */ #define CRYP_DMAReq_DataIN ((uint8_t)0x01) #define CRYP_DMAReq_DataOUT ((uint8_t)0x02) #define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the CRYP configuration to the default reset state ****/ void CRYP_DeInit(void); /* CRYP Initialization and Configuration functions ****************************/ void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct); void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct); void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); void CRYP_Cmd(FunctionalState NewState); void CRYP_PhaseConfig(uint32_t CRYP_Phase); void CRYP_FIFOFlush(void); /* CRYP Data processing functions *********************************************/ void CRYP_DataIn(uint32_t Data); uint32_t CRYP_DataOut(void); /* CRYP Context swapping functions ********************************************/ ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore); /* CRYP DMA interface function ************************************************/ void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState); ITStatus CRYP_GetITStatus(uint8_t CRYP_IT); FunctionalState CRYP_GetCmdStatus(void); FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG); /* High Level AES functions **************************************************/ ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output); ErrorStatus CRYP_AES_CBC(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output); ErrorStatus CRYP_AES_CTR(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t Ilength, uint8_t *Output); ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t ILength, uint8_t *Header, uint32_t HLength, uint8_t *Output, uint8_t *AuthTAG); ErrorStatus CRYP_AES_CCM(uint8_t Mode, uint8_t* Nonce, uint32_t NonceSize, uint8_t* Key, uint16_t Keysize, uint8_t* Input, uint32_t ILength, uint8_t* Header, uint32_t HLength, uint8_t *HBuffer, uint8_t* Output, uint8_t* AuthTAG, uint32_t TAGSize); /* High Level TDES functions **************************************************/ ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input, uint32_t Ilength, uint8_t *Output); ErrorStatus CRYP_TDES_CBC(uint8_t Mode, uint8_t Key[24], uint8_t InitVectors[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output); /* High Level DES functions **************************************************/ ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output); ErrorStatus CRYP_DES_CBC(uint8_t Mode, uint8_t Key[8], uint8_t InitVectors[8], uint8_t *Input,uint32_t Ilength, uint8_t *Output); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_CRYP_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h ================================================ /** ****************************************************************************** * @file stm32f4xx_dac.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the DAC firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_DAC_H #define __STM32F4xx_DAC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup DAC * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief DAC Init structure definition */ typedef struct { uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. This parameter can be a value of @ref DAC_trigger_selection */ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves are generated, or whether no wave is generated. This parameter can be a value of @ref DAC_wave_generation */ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or the maximum amplitude triangle generation for the DAC channel. This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of @ref DAC_output_buffer */ }DAC_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup DAC_Exported_Constants * @{ */ /** @defgroup DAC_trigger_selection * @{ */ #define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ #define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ #define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ ((TRIGGER) == DAC_Trigger_Software)) /** * @} */ /** @defgroup DAC_wave_generation * @{ */ #define DAC_WaveGeneration_None ((uint32_t)0x00000000) #define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) #define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) #define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ ((WAVE) == DAC_WaveGeneration_Noise) || \ ((WAVE) == DAC_WaveGeneration_Triangle)) /** * @} */ /** @defgroup DAC_lfsrunmask_triangleamplitude * @{ */ #define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ #define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ #define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ #define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ #define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ #define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ #define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ #define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ #define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ #define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ #define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ #define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ #define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ #define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ #define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ ((VALUE) == DAC_TriangleAmplitude_1) || \ ((VALUE) == DAC_TriangleAmplitude_3) || \ ((VALUE) == DAC_TriangleAmplitude_7) || \ ((VALUE) == DAC_TriangleAmplitude_15) || \ ((VALUE) == DAC_TriangleAmplitude_31) || \ ((VALUE) == DAC_TriangleAmplitude_63) || \ ((VALUE) == DAC_TriangleAmplitude_127) || \ ((VALUE) == DAC_TriangleAmplitude_255) || \ ((VALUE) == DAC_TriangleAmplitude_511) || \ ((VALUE) == DAC_TriangleAmplitude_1023) || \ ((VALUE) == DAC_TriangleAmplitude_2047) || \ ((VALUE) == DAC_TriangleAmplitude_4095)) /** * @} */ /** @defgroup DAC_output_buffer * @{ */ #define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) #define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ ((STATE) == DAC_OutputBuffer_Disable)) /** * @} */ /** @defgroup DAC_Channel_selection * @{ */ #define DAC_Channel_1 ((uint32_t)0x00000000) #define DAC_Channel_2 ((uint32_t)0x00000010) #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ ((CHANNEL) == DAC_Channel_2)) /** * @} */ /** @defgroup DAC_data_alignement * @{ */ #define DAC_Align_12b_R ((uint32_t)0x00000000) #define DAC_Align_12b_L ((uint32_t)0x00000004) #define DAC_Align_8b_R ((uint32_t)0x00000008) #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ ((ALIGN) == DAC_Align_12b_L) || \ ((ALIGN) == DAC_Align_8b_R)) /** * @} */ /** @defgroup DAC_wave_generation * @{ */ #define DAC_Wave_Noise ((uint32_t)0x00000040) #define DAC_Wave_Triangle ((uint32_t)0x00000080) #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ ((WAVE) == DAC_Wave_Triangle)) /** * @} */ /** @defgroup DAC_data * @{ */ #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) /** * @} */ /** @defgroup DAC_interrupts_definition * @{ */ #define DAC_IT_DMAUDR ((uint32_t)0x00002000) #define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) /** * @} */ /** @defgroup DAC_flags_definition * @{ */ #define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) #define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the DAC configuration to the default reset state *****/ void DAC_DeInit(void); /* DAC channels configuration: trigger, output buffer, data format functions */ void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); /* DMA management functions ***************************************************/ void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_DAC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h ================================================ /** ****************************************************************************** * @file stm32f4xx_dbgmcu.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the DBGMCU firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_DBGMCU_H #define __STM32F4xx_DBGMCU_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup DBGMCU * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup DBGMCU_Exported_Constants * @{ */ #define DBGMCU_SLEEP ((uint32_t)0x00000001) #define DBGMCU_STOP ((uint32_t)0x00000002) #define DBGMCU_STANDBY ((uint32_t)0x00000004) #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00)) #define DBGMCU_TIM2_STOP ((uint32_t)0x00000001) #define DBGMCU_TIM3_STOP ((uint32_t)0x00000002) #define DBGMCU_TIM4_STOP ((uint32_t)0x00000004) #define DBGMCU_TIM5_STOP ((uint32_t)0x00000008) #define DBGMCU_TIM6_STOP ((uint32_t)0x00000010) #define DBGMCU_TIM7_STOP ((uint32_t)0x00000020) #define DBGMCU_TIM12_STOP ((uint32_t)0x00000040) #define DBGMCU_TIM13_STOP ((uint32_t)0x00000080) #define DBGMCU_TIM14_STOP ((uint32_t)0x00000100) #define DBGMCU_RTC_STOP ((uint32_t)0x00000400) #define DBGMCU_WWDG_STOP ((uint32_t)0x00000800) #define DBGMCU_IWDG_STOP ((uint32_t)0x00001000) #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) #define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) #define DBGMCU_CAN1_STOP ((uint32_t)0x02000000) #define DBGMCU_CAN2_STOP ((uint32_t)0x04000000) #define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00)) #define DBGMCU_TIM1_STOP ((uint32_t)0x00000001) #define DBGMCU_TIM8_STOP ((uint32_t)0x00000002) #define DBGMCU_TIM9_STOP ((uint32_t)0x00010000) #define DBGMCU_TIM10_STOP ((uint32_t)0x00020000) #define DBGMCU_TIM11_STOP ((uint32_t)0x00040000) #define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ uint32_t DBGMCU_GetREVID(void); uint32_t DBGMCU_GetDEVID(void); void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_DBGMCU_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h ================================================ /** ****************************************************************************** * @file stm32f4xx_dcmi.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the DCMI firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_DCMI_H #define __STM32F4xx_DCMI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup DCMI * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief DCMI Init structure definition */ typedef struct { uint16_t DCMI_CaptureMode; /*!< Specifies the Capture Mode: Continuous or Snapshot. This parameter can be a value of @ref DCMI_Capture_Mode */ uint16_t DCMI_SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. This parameter can be a value of @ref DCMI_Synchronization_Mode */ uint16_t DCMI_PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. This parameter can be a value of @ref DCMI_PIXCK_Polarity */ uint16_t DCMI_VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. This parameter can be a value of @ref DCMI_VSYNC_Polarity */ uint16_t DCMI_HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. This parameter can be a value of @ref DCMI_HSYNC_Polarity */ uint16_t DCMI_CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4. This parameter can be a value of @ref DCMI_Capture_Rate */ uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. This parameter can be a value of @ref DCMI_Extended_Data_Mode */ } DCMI_InitTypeDef; /** * @brief DCMI CROP Init structure definition */ typedef struct { uint16_t DCMI_VerticalStartLine; /*!< Specifies the Vertical start line count from which the image capture will start. This parameter can be a value between 0x00 and 0x1FFF */ uint16_t DCMI_HorizontalOffsetCount; /*!< Specifies the number of pixel clocks to count before starting a capture. This parameter can be a value between 0x00 and 0x3FFF */ uint16_t DCMI_VerticalLineCount; /*!< Specifies the number of lines to be captured from the starting point. This parameter can be a value between 0x00 and 0x3FFF */ uint16_t DCMI_CaptureCount; /*!< Specifies the number of pixel clocks to be captured from the starting point on the same line. This parameter can be a value between 0x00 and 0x3FFF */ } DCMI_CROPInitTypeDef; /** * @brief DCMI Embedded Synchronisation CODE Init structure definition */ typedef struct { uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ uint8_t DCMI_LineStartCode; /*!< Specifies the code of the line start delimiter. */ uint8_t DCMI_LineEndCode; /*!< Specifies the code of the line end delimiter. */ uint8_t DCMI_FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ } DCMI_CodesInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup DCMI_Exported_Constants * @{ */ /** @defgroup DCMI_Capture_Mode * @{ */ #define DCMI_CaptureMode_Continuous ((uint16_t)0x0000) /*!< The received data are transferred continuously into the destination memory through the DMA */ #define DCMI_CaptureMode_SnapShot ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA */ #define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \ ((MODE) == DCMI_CaptureMode_SnapShot)) /** * @} */ /** @defgroup DCMI_Synchronization_Mode * @{ */ #define DCMI_SynchroMode_Hardware ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop) is synchronized with the HSYNC/VSYNC signals */ #define DCMI_SynchroMode_Embedded ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow */ #define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \ ((MODE) == DCMI_SynchroMode_Embedded)) /** * @} */ /** @defgroup DCMI_PIXCK_Polarity * @{ */ #define DCMI_PCKPolarity_Falling ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */ #define DCMI_PCKPolarity_Rising ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */ #define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \ ((POLARITY) == DCMI_PCKPolarity_Rising)) /** * @} */ /** @defgroup DCMI_VSYNC_Polarity * @{ */ #define DCMI_VSPolarity_Low ((uint16_t)0x0000) /*!< Vertical synchronization active Low */ #define DCMI_VSPolarity_High ((uint16_t)0x0080) /*!< Vertical synchronization active High */ #define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \ ((POLARITY) == DCMI_VSPolarity_High)) /** * @} */ /** @defgroup DCMI_HSYNC_Polarity * @{ */ #define DCMI_HSPolarity_Low ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */ #define DCMI_HSPolarity_High ((uint16_t)0x0040) /*!< Horizontal synchronization active High */ #define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \ ((POLARITY) == DCMI_HSPolarity_High)) /** * @} */ /** @defgroup DCMI_Capture_Rate * @{ */ #define DCMI_CaptureRate_All_Frame ((uint16_t)0x0000) /*!< All frames are captured */ #define DCMI_CaptureRate_1of2_Frame ((uint16_t)0x0100) /*!< Every alternate frame captured */ #define DCMI_CaptureRate_1of4_Frame ((uint16_t)0x0200) /*!< One frame in 4 frames captured */ #define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \ ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\ ((RATE) == DCMI_CaptureRate_1of4_Frame)) /** * @} */ /** @defgroup DCMI_Extended_Data_Mode * @{ */ #define DCMI_ExtendedDataMode_8b ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */ #define DCMI_ExtendedDataMode_10b ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */ #define DCMI_ExtendedDataMode_12b ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */ #define DCMI_ExtendedDataMode_14b ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */ #define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \ ((DATA) == DCMI_ExtendedDataMode_10b) ||\ ((DATA) == DCMI_ExtendedDataMode_12b) ||\ ((DATA) == DCMI_ExtendedDataMode_14b)) /** * @} */ /** @defgroup DCMI_interrupt_sources * @{ */ #define DCMI_IT_FRAME ((uint16_t)0x0001) #define DCMI_IT_OVF ((uint16_t)0x0002) #define DCMI_IT_ERR ((uint16_t)0x0004) #define DCMI_IT_VSYNC ((uint16_t)0x0008) #define DCMI_IT_LINE ((uint16_t)0x0010) #define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000)) #define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \ ((IT) == DCMI_IT_OVF) || \ ((IT) == DCMI_IT_ERR) || \ ((IT) == DCMI_IT_VSYNC) || \ ((IT) == DCMI_IT_LINE)) /** * @} */ /** @defgroup DCMI_Flags * @{ */ /** * @brief DCMI SR register */ #define DCMI_FLAG_HSYNC ((uint16_t)0x2001) #define DCMI_FLAG_VSYNC ((uint16_t)0x2002) #define DCMI_FLAG_FNE ((uint16_t)0x2004) /** * @brief DCMI RISR register */ #define DCMI_FLAG_FRAMERI ((uint16_t)0x0001) #define DCMI_FLAG_OVFRI ((uint16_t)0x0002) #define DCMI_FLAG_ERRRI ((uint16_t)0x0004) #define DCMI_FLAG_VSYNCRI ((uint16_t)0x0008) #define DCMI_FLAG_LINERI ((uint16_t)0x0010) /** * @brief DCMI MISR register */ #define DCMI_FLAG_FRAMEMI ((uint16_t)0x1001) #define DCMI_FLAG_OVFMI ((uint16_t)0x1002) #define DCMI_FLAG_ERRMI ((uint16_t)0x1004) #define DCMI_FLAG_VSYNCMI ((uint16_t)0x1008) #define DCMI_FLAG_LINEMI ((uint16_t)0x1010) #define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \ ((FLAG) == DCMI_FLAG_VSYNC) || \ ((FLAG) == DCMI_FLAG_FNE) || \ ((FLAG) == DCMI_FLAG_FRAMERI) || \ ((FLAG) == DCMI_FLAG_OVFRI) || \ ((FLAG) == DCMI_FLAG_ERRRI) || \ ((FLAG) == DCMI_FLAG_VSYNCRI) || \ ((FLAG) == DCMI_FLAG_LINERI) || \ ((FLAG) == DCMI_FLAG_FRAMEMI) || \ ((FLAG) == DCMI_FLAG_OVFMI) || \ ((FLAG) == DCMI_FLAG_ERRMI) || \ ((FLAG) == DCMI_FLAG_VSYNCMI) || \ ((FLAG) == DCMI_FLAG_LINEMI)) #define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the DCMI configuration to the default reset state ****/ void DCMI_DeInit(void); /* Initialization and Configuration functions *********************************/ void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct); void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct); void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct); void DCMI_CROPCmd(FunctionalState NewState); void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct); void DCMI_JPEGCmd(FunctionalState NewState); /* Image capture functions ****************************************************/ void DCMI_Cmd(FunctionalState NewState); void DCMI_CaptureCmd(FunctionalState NewState); uint32_t DCMI_ReadData(void); /* Interrupts and flags management functions **********************************/ void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState); FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG); void DCMI_ClearFlag(uint16_t DCMI_FLAG); ITStatus DCMI_GetITStatus(uint16_t DCMI_IT); void DCMI_ClearITPendingBit(uint16_t DCMI_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_DCMI_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h ================================================ /** ****************************************************************************** * @file stm32f4xx_dma.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the DMA firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_DMA_H #define __STM32F4xx_DMA_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup DMA * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief DMA Init structure definition */ typedef struct { uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream. This parameter can be a value of @ref DMA_channel */ uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */ uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx. This memory is the default memory used when double buffer mode is not enabled. */ uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral, from memory to memory or from peripheral to memory. This parameter can be a value of @ref DMA_data_transfer_direction */ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream. The data unit is equal to the configuration set in DMA_PeripheralDataSize or DMA_MemoryDataSize members depending in the transfer direction. */ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not. This parameter can be a value of @ref DMA_peripheral_incremented_mode */ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not. This parameter can be a value of @ref DMA_memory_incremented_mode */ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. This parameter can be a value of @ref DMA_peripheral_data_size */ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. This parameter can be a value of @ref DMA_memory_data_size */ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx. This parameter can be a value of @ref DMA_circular_normal_mode @note The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Stream */ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx. This parameter can be a value of @ref DMA_priority_level */ uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream. This parameter can be a value of @ref DMA_fifo_direct_mode @note The Direct mode (FIFO mode disabled) cannot be used if the memory-to-memory data transfer is configured on the selected Stream */ uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level. This parameter can be a value of @ref DMA_fifo_threshold_level */ uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. It specifies the amount of data to be transferred in a single non interruptable transaction. This parameter can be a value of @ref DMA_memory_burst @note The burst mode is possible only if the address Increment mode is enabled. */ uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. It specifies the amount of data to be transferred in a single non interruptable transaction. This parameter can be a value of @ref DMA_peripheral_burst @note The burst mode is possible only if the address Increment mode is enabled. */ }DMA_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup DMA_Exported_Constants * @{ */ #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \ ((PERIPH) == DMA1_Stream1) || \ ((PERIPH) == DMA1_Stream2) || \ ((PERIPH) == DMA1_Stream3) || \ ((PERIPH) == DMA1_Stream4) || \ ((PERIPH) == DMA1_Stream5) || \ ((PERIPH) == DMA1_Stream6) || \ ((PERIPH) == DMA1_Stream7) || \ ((PERIPH) == DMA2_Stream0) || \ ((PERIPH) == DMA2_Stream1) || \ ((PERIPH) == DMA2_Stream2) || \ ((PERIPH) == DMA2_Stream3) || \ ((PERIPH) == DMA2_Stream4) || \ ((PERIPH) == DMA2_Stream5) || \ ((PERIPH) == DMA2_Stream6) || \ ((PERIPH) == DMA2_Stream7)) #define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \ ((CONTROLLER) == DMA2)) /** @defgroup DMA_channel * @{ */ #define DMA_Channel_0 ((uint32_t)0x00000000) #define DMA_Channel_1 ((uint32_t)0x02000000) #define DMA_Channel_2 ((uint32_t)0x04000000) #define DMA_Channel_3 ((uint32_t)0x06000000) #define DMA_Channel_4 ((uint32_t)0x08000000) #define DMA_Channel_5 ((uint32_t)0x0A000000) #define DMA_Channel_6 ((uint32_t)0x0C000000) #define DMA_Channel_7 ((uint32_t)0x0E000000) #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \ ((CHANNEL) == DMA_Channel_1) || \ ((CHANNEL) == DMA_Channel_2) || \ ((CHANNEL) == DMA_Channel_3) || \ ((CHANNEL) == DMA_Channel_4) || \ ((CHANNEL) == DMA_Channel_5) || \ ((CHANNEL) == DMA_Channel_6) || \ ((CHANNEL) == DMA_Channel_7)) /** * @} */ /** @defgroup DMA_data_transfer_direction * @{ */ #define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000) #define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040) #define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080) #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \ ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \ ((DIRECTION) == DMA_DIR_MemoryToMemory)) /** * @} */ /** @defgroup DMA_data_buffer_size * @{ */ #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) /** * @} */ /** @defgroup DMA_peripheral_incremented_mode * @{ */ #define DMA_PeripheralInc_Enable ((uint32_t)0x00000200) #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ ((STATE) == DMA_PeripheralInc_Disable)) /** * @} */ /** @defgroup DMA_memory_incremented_mode * @{ */ #define DMA_MemoryInc_Enable ((uint32_t)0x00000400) #define DMA_MemoryInc_Disable ((uint32_t)0x00000000) #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ ((STATE) == DMA_MemoryInc_Disable)) /** * @} */ /** @defgroup DMA_peripheral_data_size * @{ */ #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800) #define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000) #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ ((SIZE) == DMA_PeripheralDataSize_Word)) /** * @} */ /** @defgroup DMA_memory_data_size * @{ */ #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000) #define DMA_MemoryDataSize_Word ((uint32_t)0x00004000) #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ ((SIZE) == DMA_MemoryDataSize_Word )) /** * @} */ /** @defgroup DMA_circular_normal_mode * @{ */ #define DMA_Mode_Normal ((uint32_t)0x00000000) #define DMA_Mode_Circular ((uint32_t)0x00000100) #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \ ((MODE) == DMA_Mode_Circular)) /** * @} */ /** @defgroup DMA_priority_level * @{ */ #define DMA_Priority_Low ((uint32_t)0x00000000) #define DMA_Priority_Medium ((uint32_t)0x00010000) #define DMA_Priority_High ((uint32_t)0x00020000) #define DMA_Priority_VeryHigh ((uint32_t)0x00030000) #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \ ((PRIORITY) == DMA_Priority_Medium) || \ ((PRIORITY) == DMA_Priority_High) || \ ((PRIORITY) == DMA_Priority_VeryHigh)) /** * @} */ /** @defgroup DMA_fifo_direct_mode * @{ */ #define DMA_FIFOMode_Disable ((uint32_t)0x00000000) #define DMA_FIFOMode_Enable ((uint32_t)0x00000004) #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \ ((STATE) == DMA_FIFOMode_Enable)) /** * @} */ /** @defgroup DMA_fifo_threshold_level * @{ */ #define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000) #define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001) #define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002) #define DMA_FIFOThreshold_Full ((uint32_t)0x00000003) #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \ ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \ ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \ ((THRESHOLD) == DMA_FIFOThreshold_Full)) /** * @} */ /** @defgroup DMA_memory_burst * @{ */ #define DMA_MemoryBurst_Single ((uint32_t)0x00000000) #define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000) #define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000) #define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000) #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \ ((BURST) == DMA_MemoryBurst_INC4) || \ ((BURST) == DMA_MemoryBurst_INC8) || \ ((BURST) == DMA_MemoryBurst_INC16)) /** * @} */ /** @defgroup DMA_peripheral_burst * @{ */ #define DMA_PeripheralBurst_Single ((uint32_t)0x00000000) #define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000) #define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000) #define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000) #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \ ((BURST) == DMA_PeripheralBurst_INC4) || \ ((BURST) == DMA_PeripheralBurst_INC8) || \ ((BURST) == DMA_PeripheralBurst_INC16)) /** * @} */ /** @defgroup DMA_fifo_status_level * @{ */ #define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3) #define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3) #define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3) #define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3) #define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3) #define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3) #define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \ ((STATUS) == DMA_FIFOStatus_HalfFull) || \ ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \ ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \ ((STATUS) == DMA_FIFOStatus_Full) || \ ((STATUS) == DMA_FIFOStatus_Empty)) /** * @} */ /** @defgroup DMA_flags_definition * @{ */ #define DMA_FLAG_FEIF0 ((uint32_t)0x10800001) #define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004) #define DMA_FLAG_TEIF0 ((uint32_t)0x10000008) #define DMA_FLAG_HTIF0 ((uint32_t)0x10000010) #define DMA_FLAG_TCIF0 ((uint32_t)0x10000020) #define DMA_FLAG_FEIF1 ((uint32_t)0x10000040) #define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100) #define DMA_FLAG_TEIF1 ((uint32_t)0x10000200) #define DMA_FLAG_HTIF1 ((uint32_t)0x10000400) #define DMA_FLAG_TCIF1 ((uint32_t)0x10000800) #define DMA_FLAG_FEIF2 ((uint32_t)0x10010000) #define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000) #define DMA_FLAG_TEIF2 ((uint32_t)0x10080000) #define DMA_FLAG_HTIF2 ((uint32_t)0x10100000) #define DMA_FLAG_TCIF2 ((uint32_t)0x10200000) #define DMA_FLAG_FEIF3 ((uint32_t)0x10400000) #define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000) #define DMA_FLAG_TEIF3 ((uint32_t)0x12000000) #define DMA_FLAG_HTIF3 ((uint32_t)0x14000000) #define DMA_FLAG_TCIF3 ((uint32_t)0x18000000) #define DMA_FLAG_FEIF4 ((uint32_t)0x20000001) #define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004) #define DMA_FLAG_TEIF4 ((uint32_t)0x20000008) #define DMA_FLAG_HTIF4 ((uint32_t)0x20000010) #define DMA_FLAG_TCIF4 ((uint32_t)0x20000020) #define DMA_FLAG_FEIF5 ((uint32_t)0x20000040) #define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100) #define DMA_FLAG_TEIF5 ((uint32_t)0x20000200) #define DMA_FLAG_HTIF5 ((uint32_t)0x20000400) #define DMA_FLAG_TCIF5 ((uint32_t)0x20000800) #define DMA_FLAG_FEIF6 ((uint32_t)0x20010000) #define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000) #define DMA_FLAG_TEIF6 ((uint32_t)0x20080000) #define DMA_FLAG_HTIF6 ((uint32_t)0x20100000) #define DMA_FLAG_TCIF6 ((uint32_t)0x20200000) #define DMA_FLAG_FEIF7 ((uint32_t)0x20400000) #define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000) #define DMA_FLAG_TEIF7 ((uint32_t)0x22000000) #define DMA_FLAG_HTIF7 ((uint32_t)0x24000000) #define DMA_FLAG_TCIF7 ((uint32_t)0x28000000) #define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \ (((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00)) #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \ ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \ ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \ ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \ ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \ ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \ ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \ ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \ ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \ ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \ ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \ ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \ ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \ ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \ ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \ ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \ ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \ ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \ ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \ ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7)) /** * @} */ /** @defgroup DMA_interrupt_enable_definitions * @{ */ #define DMA_IT_TC ((uint32_t)0x00000010) #define DMA_IT_HT ((uint32_t)0x00000008) #define DMA_IT_TE ((uint32_t)0x00000004) #define DMA_IT_DME ((uint32_t)0x00000002) #define DMA_IT_FE ((uint32_t)0x00000080) #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00)) /** * @} */ /** @defgroup DMA_interrupts_definitions * @{ */ #define DMA_IT_FEIF0 ((uint32_t)0x90000001) #define DMA_IT_DMEIF0 ((uint32_t)0x10001004) #define DMA_IT_TEIF0 ((uint32_t)0x10002008) #define DMA_IT_HTIF0 ((uint32_t)0x10004010) #define DMA_IT_TCIF0 ((uint32_t)0x10008020) #define DMA_IT_FEIF1 ((uint32_t)0x90000040) #define DMA_IT_DMEIF1 ((uint32_t)0x10001100) #define DMA_IT_TEIF1 ((uint32_t)0x10002200) #define DMA_IT_HTIF1 ((uint32_t)0x10004400) #define DMA_IT_TCIF1 ((uint32_t)0x10008800) #define DMA_IT_FEIF2 ((uint32_t)0x90010000) #define DMA_IT_DMEIF2 ((uint32_t)0x10041000) #define DMA_IT_TEIF2 ((uint32_t)0x10082000) #define DMA_IT_HTIF2 ((uint32_t)0x10104000) #define DMA_IT_TCIF2 ((uint32_t)0x10208000) #define DMA_IT_FEIF3 ((uint32_t)0x90400000) #define DMA_IT_DMEIF3 ((uint32_t)0x11001000) #define DMA_IT_TEIF3 ((uint32_t)0x12002000) #define DMA_IT_HTIF3 ((uint32_t)0x14004000) #define DMA_IT_TCIF3 ((uint32_t)0x18008000) #define DMA_IT_FEIF4 ((uint32_t)0xA0000001) #define DMA_IT_DMEIF4 ((uint32_t)0x20001004) #define DMA_IT_TEIF4 ((uint32_t)0x20002008) #define DMA_IT_HTIF4 ((uint32_t)0x20004010) #define DMA_IT_TCIF4 ((uint32_t)0x20008020) #define DMA_IT_FEIF5 ((uint32_t)0xA0000040) #define DMA_IT_DMEIF5 ((uint32_t)0x20001100) #define DMA_IT_TEIF5 ((uint32_t)0x20002200) #define DMA_IT_HTIF5 ((uint32_t)0x20004400) #define DMA_IT_TCIF5 ((uint32_t)0x20008800) #define DMA_IT_FEIF6 ((uint32_t)0xA0010000) #define DMA_IT_DMEIF6 ((uint32_t)0x20041000) #define DMA_IT_TEIF6 ((uint32_t)0x20082000) #define DMA_IT_HTIF6 ((uint32_t)0x20104000) #define DMA_IT_TCIF6 ((uint32_t)0x20208000) #define DMA_IT_FEIF7 ((uint32_t)0xA0400000) #define DMA_IT_DMEIF7 ((uint32_t)0x21001000) #define DMA_IT_TEIF7 ((uint32_t)0x22002000) #define DMA_IT_HTIF7 ((uint32_t)0x24004000) #define DMA_IT_TCIF7 ((uint32_t)0x28008000) #define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \ (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \ (((IT) & 0x40820082) == 0x00)) #define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \ ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \ ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \ ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \ ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \ ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \ ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \ ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \ ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \ ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \ ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \ ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \ ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \ ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \ ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \ ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \ ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \ ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \ ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \ ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7)) /** * @} */ /** @defgroup DMA_peripheral_increment_offset * @{ */ #define DMA_PINCOS_Psize ((uint32_t)0x00000000) #define DMA_PINCOS_WordAligned ((uint32_t)0x00008000) #define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \ ((SIZE) == DMA_PINCOS_WordAligned)) /** * @} */ /** @defgroup DMA_flow_controller_definitions * @{ */ #define DMA_FlowCtrl_Memory ((uint32_t)0x00000000) #define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020) #define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \ ((CTRL) == DMA_FlowCtrl_Peripheral)) /** * @} */ /** @defgroup DMA_memory_targets_definitions * @{ */ #define DMA_Memory_0 ((uint32_t)0x00000000) #define DMA_Memory_1 ((uint32_t)0x00080000) #define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the DMA configuration to the default reset state *****/ void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx); /* Initialization and Configuration functions *********************************/ void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct); void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); /* Optional Configuration functions *******************************************/ void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos); void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl); /* Data Counter functions *****************************************************/ void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); /* Double Buffer mode functions ***********************************************/ void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory); void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget); uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); /* Interrupts and flags management functions **********************************/ FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_DMA_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h ================================================ /** ****************************************************************************** * @file stm32f4xx_dma2d.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the DMA2D firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * *

© COPYRIGHT 2013 STMicroelectronics

****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_DMA2D_H #define __STM32F4xx_DMA2D_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup DMA2D * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief DMA2D Init structure definition */ typedef struct { uint32_t DMA2D_Mode; /*!< configures the DMA2D transfer mode. This parameter can be one value of @ref DMA2D_MODE */ uint32_t DMA2D_CMode; /*!< configures the color format of the output image. This parameter can be one value of @ref DMA2D_CMODE */ uint32_t DMA2D_OutputBlue; /*!< configures the blue value of the output image. This parameter must range: - from 0x00 to 0xFF if ARGB8888 color mode is slected - from 0x00 to 0xFF if RGB888 color mode is slected - from 0x00 to 0x1F if RGB565 color mode is slected - from 0x00 to 0x1F if ARGB1555 color mode is slected - from 0x00 to 0x0F if ARGB4444 color mode is slected */ uint32_t DMA2D_OutputGreen; /*!< configures the green value of the output image. This parameter must range: - from 0x00 to 0xFF if ARGB8888 color mode is slected - from 0x00 to 0xFF if RGB888 color mode is slected - from 0x00 to 0x2F if RGB565 color mode is slected - from 0x00 to 0x1F if ARGB1555 color mode is slected - from 0x00 to 0x0F if ARGB4444 color mode is slected */ uint32_t DMA2D_OutputRed; /*!< configures the red value of the output image. This parameter must range: - from 0x00 to 0xFF if ARGB8888 color mode is slected - from 0x00 to 0xFF if RGB888 color mode is slected - from 0x00 to 0x1F if RGB565 color mode is slected - from 0x00 to 0x1F if ARGB1555 color mode is slected - from 0x00 to 0x0F if ARGB4444 color mode is slected */ uint32_t DMA2D_OutputAlpha; /*!< configures the alpha channel of the output color. This parameter must range: - from 0x00 to 0xFF if ARGB8888 color mode is slected - from 0x00 to 0x01 if ARGB1555 color mode is slected - from 0x00 to 0x0F if ARGB4444 color mode is slected */ uint32_t DMA2D_OutputMemoryAdd; /*!< Specifies the memory address. This parameter must be range from 0x00000000 to 0xFFFFFFFF. */ uint32_t DMA2D_OutputOffset; /*!< Specifies the Offset value. This parameter must be range from 0x0000 to 0x3FFF. */ uint32_t DMA2D_NumberOfLine; /*!< Configures the number of line of the area to be transfered. This parameter must range from 0x0000 to 0xFFFF */ uint32_t DMA2D_PixelPerLine; /*!< Configures the number pixel per line of the area to be transfered. This parameter must range from 0x0000 to 0x3FFF */ } DMA2D_InitTypeDef; typedef struct { uint32_t DMA2D_FGMA; /*!< configures the DMA2D foreground memory address. This parameter must be range from 0x00000000 to 0xFFFFFFFF. */ uint32_t DMA2D_FGO; /*!< configures the DMA2D foreground offset. This parameter must be range from 0x0000 to 0x3FFF. */ uint32_t DMA2D_FGCM; /*!< configures the DMA2D foreground color mode . This parameter can be one value of @ref DMA2D_FGCM */ uint32_t DMA2D_FG_CLUT_CM; /*!< configures the DMA2D foreground CLUT color mode. This parameter can be one value of @ref DMA2D_FG_CLUT_CM */ uint32_t DMA2D_FG_CLUT_SIZE; /*!< configures the DMA2D foreground CLUT size. This parameter must range from 0x00 to 0xFF. */ uint32_t DMA2D_FGPFC_ALPHA_MODE; /*!< configures the DMA2D foreground alpha mode. This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */ uint32_t DMA2D_FGPFC_ALPHA_VALUE; /*!< Specifies the DMA2D foreground alpha value must be range from 0x00 to 0xFF. */ uint32_t DMA2D_FGC_BLUE; /*!< Specifies the DMA2D foreground blue value must be range from 0x00 to 0xFF. */ uint32_t DMA2D_FGC_GREEN; /*!< Specifies the DMA2D foreground green value must be range from 0x00 to 0xFF. */ uint32_t DMA2D_FGC_RED; /*!< Specifies the DMA2D foreground red value must be range from 0x00 to 0xFF. */ uint32_t DMA2D_FGCMAR; /*!< Configures the DMA2D foreground CLUT memory address. This parameter must range from 0x00000000 to 0xFFFFFFFF. */ } DMA2D_FG_InitTypeDef; typedef struct { uint32_t DMA2D_BGMA; /*!< configures the DMA2D background memory address. This parameter must be range from 0x00000000 to 0xFFFFFFFF. */ uint32_t DMA2D_BGO; /*!< configures the DMA2D background offset. This parameter must be range from 0x0000 to 0x3FFF. */ uint32_t DMA2D_BGCM; /*!< configures the DMA2D background color mode . This parameter can be one value of @ref DMA2D_FGCM */ uint32_t DMA2D_BG_CLUT_CM; /*!< configures the DMA2D background CLUT color mode. This parameter can be one value of @ref DMA2D_FG_CLUT_CM */ uint32_t DMA2D_BG_CLUT_SIZE; /*!< configures the DMA2D background CLUT size. This parameter must range from 0x00 to 0xFF. */ uint32_t DMA2D_BGPFC_ALPHA_MODE; /*!< configures the DMA2D background alpha mode. This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */ uint32_t DMA2D_BGPFC_ALPHA_VALUE; /*!< Specifies the DMA2D background alpha value must be range from 0x00 to 0xFF. */ uint32_t DMA2D_BGC_BLUE; /*!< Specifies the DMA2D background blue value must be range from 0x00 to 0xFF. */ uint32_t DMA2D_BGC_GREEN; /*!< Specifies the DMA2D background green value must be range from 0x00 to 0xFF. */ uint32_t DMA2D_BGC_RED; /*!< Specifies the DMA2D background red value must be range from 0x00 to 0xFF. */ uint32_t DMA2D_BGCMAR; /*!< Configures the DMA2D background CLUT memory address. This parameter must range from 0x00000000 to 0xFFFFFFFF. */ } DMA2D_BG_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup DMA2D_Exported_Constants * @{ */ /** @defgroup DMA2D_MODE * @{ */ #define DMA2D_M2M ((uint32_t)0x00000000) #define DMA2D_M2M_PFC ((uint32_t)0x00010000) #define DMA2D_M2M_BLEND ((uint32_t)0x00020000) #define DMA2D_R2M ((uint32_t)0x00030000) #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) /** * @} */ /** @defgroup DMA2D_CMODE * @{ */ #define DMA2D_ARGB8888 ((uint32_t)0x00000000) #define DMA2D_RGB888 ((uint32_t)0x00000001) #define DMA2D_RGB565 ((uint32_t)0x00000002) #define DMA2D_ARGB1555 ((uint32_t)0x00000003) #define DMA2D_ARGB4444 ((uint32_t)0x00000004) #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \ ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \ ((MODE_ARGB) == DMA2D_ARGB4444)) /** * @} */ /** @defgroup DMA2D_OUTPUT_COLOR * @{ */ #define DMA2D_Output_Color ((uint32_t)0x000000FF) #define IS_DMA2D_OGREEN(OGREEN) ((OGREEN) <= DMA2D_Output_Color) #define IS_DMA2D_ORED(ORED) ((ORED) <= DMA2D_Output_Color) #define IS_DMA2D_OBLUE(OBLUE) ((OBLUE) <= DMA2D_Output_Color) #define IS_DMA2D_OALPHA(OALPHA) ((OALPHA) <= DMA2D_Output_Color) /** * @} */ /** @defgroup DMA2D_OUTPUT_OFFSET * @{ */ #define DMA2D_OUTPUT_OFFSET ((uint32_t)0x00003FFF) #define IS_DMA2D_OUTPUT_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OUTPUT_OFFSET) /** * @} */ /** @defgroup DMA2D_SIZE * @{ */ #define DMA2D_pixel ((uint32_t)0x00003FFF) #define DMA2D_Line ((uint32_t)0x0000FFFF) #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_Line) #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_pixel) /** * @} */ /** @defgroup DMA2D_OFFSET * @{ */ #define OFFSET ((uint32_t)0x00003FFF) #define IS_DMA2D_FGO(FGO) ((FGO) <= OFFSET) #define IS_DMA2D_BGO(BGO) ((BGO) <= OFFSET) /** * @} */ /** @defgroup DMA2D_FGCM * @{ */ #define CM_ARGB8888 ((uint32_t)0x00000000) #define CM_RGB888 ((uint32_t)0x00000001) #define CM_RGB565 ((uint32_t)0x00000002) #define CM_ARGB1555 ((uint32_t)0x00000003) #define CM_ARGB4444 ((uint32_t)0x00000004) #define CM_L8 ((uint32_t)0x00000005) #define CM_AL44 ((uint32_t)0x00000006) #define CM_AL88 ((uint32_t)0x00000007) #define CM_L4 ((uint32_t)0x00000008) #define CM_A8 ((uint32_t)0x00000009) #define CM_A4 ((uint32_t)0x0000000A) #define IS_DMA2D_FGCM(FGCM) (((FGCM) == CM_ARGB8888) || ((FGCM) == CM_RGB888) || \ ((FGCM) == CM_RGB565) || ((FGCM) == CM_ARGB1555) || \ ((FGCM) == CM_ARGB4444) || ((FGCM) == CM_L8) || \ ((FGCM) == CM_AL44) || ((FGCM) == CM_AL88) || \ ((FGCM) == CM_L4) || ((FGCM) == CM_A8) || \ ((FGCM) == CM_A4)) #define IS_DMA2D_BGCM(BGCM) (((BGCM) == CM_ARGB8888) || ((BGCM) == CM_RGB888) || \ ((BGCM) == CM_RGB565) || ((BGCM) == CM_ARGB1555) || \ ((BGCM) == CM_ARGB4444) || ((BGCM) == CM_L8) || \ ((BGCM) == CM_AL44) || ((BGCM) == CM_AL88) || \ ((BGCM) == CM_L4) || ((BGCM) == CM_A8) || \ ((BGCM) == CM_A4)) /** * @} */ /** @defgroup DMA2D_FG_CLUT_CM * @{ */ #define CLUT_CM_ARGB8888 ((uint32_t)0x00000000) #define CLUT_CM_RGB888 ((uint32_t)0x00000001) #define IS_DMA2D_FG_CLUT_CM(FG_CLUT_CM) (((FG_CLUT_CM) == CLUT_CM_ARGB8888) || ((FG_CLUT_CM) == CLUT_CM_RGB888)) #define IS_DMA2D_BG_CLUT_CM(BG_CLUT_CM) (((BG_CLUT_CM) == CLUT_CM_ARGB8888) || ((BG_CLUT_CM) == CLUT_CM_RGB888)) /** * @} */ /** @defgroup DMA2D_FG_COLOR_VALUE * @{ */ #define COLOR_VALUE ((uint32_t)0x000000FF) #define IS_DMA2D_FG_CLUT_SIZE(FG_CLUT_SIZE) ((FG_CLUT_SIZE) <= COLOR_VALUE) #define IS_DMA2D_FG_ALPHA_VALUE(FG_ALPHA_VALUE) ((FG_ALPHA_VALUE) <= COLOR_VALUE) #define IS_DMA2D_FGC_BLUE(FGC_BLUE) ((FGC_BLUE) <= COLOR_VALUE) #define IS_DMA2D_FGC_GREEN(FGC_GREEN) ((FGC_GREEN) <= COLOR_VALUE) #define IS_DMA2D_FGC_RED(FGC_RED) ((FGC_RED) <= COLOR_VALUE) #define IS_DMA2D_BG_CLUT_SIZE(BG_CLUT_SIZE) ((BG_CLUT_SIZE) <= COLOR_VALUE) #define IS_DMA2D_BG_ALPHA_VALUE(BG_ALPHA_VALUE) ((BG_ALPHA_VALUE) <= COLOR_VALUE) #define IS_DMA2D_BGC_BLUE(BGC_BLUE) ((BGC_BLUE) <= COLOR_VALUE) #define IS_DMA2D_BGC_GREEN(BGC_GREEN) ((BGC_GREEN) <= COLOR_VALUE) #define IS_DMA2D_BGC_RED(BGC_RED) ((BGC_RED) <= COLOR_VALUE) /** * @} */ /** DMA2D_FGPFC_ALPHA_MODE * @{ */ #define NO_MODIF_ALPHA_VALUE ((uint32_t)0x00000000) #define REPLACE_ALPHA_VALUE ((uint32_t)0x00000001) #define COMBINE_ALPHA_VALUE ((uint32_t)0x00000002) #define IS_DMA2D_FG_ALPHA_MODE(FG_ALPHA_MODE) (((FG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \ ((FG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \ ((FG_ALPHA_MODE) == COMBINE_ALPHA_VALUE)) #define IS_DMA2D_BG_ALPHA_MODE(BG_ALPHA_MODE) (((BG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \ ((BG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \ ((BG_ALPHA_MODE) == COMBINE_ALPHA_VALUE)) /** * @} */ /** @defgroup DMA2D_Interrupts * @{ */ #define DMA2D_IT_CE DMA2D_CR_CEIE #define DMA2D_IT_CTC DMA2D_CR_CTCIE #define DMA2D_IT_CAE DMA2D_CR_CAEIE #define DMA2D_IT_TW DMA2D_CR_TWIE #define DMA2D_IT_TC DMA2D_CR_TCIE #define DMA2D_IT_TE DMA2D_CR_TEIE #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) /** * @} */ /** @defgroup DMA2D_Flag * @{ */ #define DMA2D_FLAG_CE DMA2D_ISR_CEIF #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF #define DMA2D_FLAG_TW DMA2D_ISR_TWIF #define DMA2D_FLAG_TC DMA2D_ISR_TCIF #define DMA2D_FLAG_TE DMA2D_ISR_TEIF #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) /** * @} */ /** @defgroup DMA2D_DeadTime * @{ */ #define DEADTIME ((uint32_t)0x000000FF) #define IS_DMA2D_DEAD_TIME(DEAD_TIME) ((DEAD_TIME) <= DEADTIME) #define LINE_WATERMARK DMA2D_LWR_LW #define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the DMA2D configuration to the default reset state *****/ void DMA2D_DeInit(void); /* Initialization and Configuration functions *********************************/ void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct); void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct); void DMA2D_StartTransfer(void); void DMA2D_AbortTransfer(void); void DMA2D_Suspend(FunctionalState NewState); void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct); void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct); void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct); void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct); void DMA2D_FGStart(FunctionalState NewState); void DMA2D_BGStart(FunctionalState NewState); void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState); void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig); /* Interrupts and flags management functions **********************************/ void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState); FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG); void DMA2D_ClearFlag(uint32_t DMA2D_FLAG); ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT); void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_DMA2D_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h ================================================ /** ****************************************************************************** * @file stm32f4xx_exti.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the EXTI firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_EXTI_H #define __STM32F4xx_EXTI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup EXTI * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief EXTI mode enumeration */ typedef enum { EXTI_Mode_Interrupt = 0x00, EXTI_Mode_Event = 0x04 }EXTIMode_TypeDef; #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) /** * @brief EXTI Trigger enumeration */ typedef enum { EXTI_Trigger_Rising = 0x08, EXTI_Trigger_Falling = 0x0C, EXTI_Trigger_Rising_Falling = 0x10 }EXTITrigger_TypeDef; #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ ((TRIGGER) == EXTI_Trigger_Falling) || \ ((TRIGGER) == EXTI_Trigger_Rising_Falling)) /** * @brief EXTI Init Structure definition */ typedef struct { uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. This parameter can be any combination value of @ref EXTI_Lines */ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. This parameter can be a value of @ref EXTIMode_TypeDef */ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. This parameter can be a value of @ref EXTITrigger_TypeDef */ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. This parameter can be set either to ENABLE or DISABLE */ }EXTI_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup EXTI_Exported_Constants * @{ */ /** @defgroup EXTI_Lines * @{ */ #define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ #define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ #define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ #define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ #define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ #define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ #define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ #define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ #define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ #define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ #define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ #define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ #define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ #define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ #define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ #define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ #define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ #define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ #define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ #define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ #define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ #define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ #define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00)) #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\ ((LINE) == EXTI_Line22)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the EXTI configuration to the default reset state *****/ void EXTI_DeInit(void); /* Initialization and Configuration functions *********************************/ void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); /* Interrupts and flags management functions **********************************/ FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); void EXTI_ClearFlag(uint32_t EXTI_Line); ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); void EXTI_ClearITPendingBit(uint32_t EXTI_Line); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_EXTI_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h ================================================ /** ****************************************************************************** * @file stm32f4xx_flash.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the FLASH * firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_FLASH_H #define __STM32F4xx_FLASH_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup FLASH * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief FLASH Status */ typedef enum { FLASH_BUSY = 1, FLASH_ERROR_RD, FLASH_ERROR_PGS, FLASH_ERROR_PGP, FLASH_ERROR_PGA, FLASH_ERROR_WRP, FLASH_ERROR_PROGRAM, FLASH_ERROR_OPERATION, FLASH_COMPLETE }FLASH_Status; /* Exported constants --------------------------------------------------------*/ /** @defgroup FLASH_Exported_Constants * @{ */ /** @defgroup Flash_Latency * @{ */ #define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */ #define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */ #define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */ #define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */ #define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */ #define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */ #define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */ #define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */ #define FLASH_Latency_8 ((uint8_t)0x0008) /*!< FLASH Eight Latency cycles */ #define FLASH_Latency_9 ((uint8_t)0x0009) /*!< FLASH Nine Latency cycles */ #define FLASH_Latency_10 ((uint8_t)0x000A) /*!< FLASH Ten Latency cycles */ #define FLASH_Latency_11 ((uint8_t)0x000B) /*!< FLASH Eleven Latency cycles */ #define FLASH_Latency_12 ((uint8_t)0x000C) /*!< FLASH Twelve Latency cycles */ #define FLASH_Latency_13 ((uint8_t)0x000D) /*!< FLASH Thirteen Latency cycles */ #define FLASH_Latency_14 ((uint8_t)0x000E) /*!< FLASH Fourteen Latency cycles */ #define FLASH_Latency_15 ((uint8_t)0x000F) /*!< FLASH Fifteen Latency cycles */ #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ ((LATENCY) == FLASH_Latency_1) || \ ((LATENCY) == FLASH_Latency_2) || \ ((LATENCY) == FLASH_Latency_3) || \ ((LATENCY) == FLASH_Latency_4) || \ ((LATENCY) == FLASH_Latency_5) || \ ((LATENCY) == FLASH_Latency_6) || \ ((LATENCY) == FLASH_Latency_7) || \ ((LATENCY) == FLASH_Latency_8) || \ ((LATENCY) == FLASH_Latency_9) || \ ((LATENCY) == FLASH_Latency_10) || \ ((LATENCY) == FLASH_Latency_11) || \ ((LATENCY) == FLASH_Latency_12) || \ ((LATENCY) == FLASH_Latency_13) || \ ((LATENCY) == FLASH_Latency_14) || \ ((LATENCY) == FLASH_Latency_15)) /** * @} */ /** @defgroup FLASH_Voltage_Range * @{ */ #define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */ #define VoltageRange_2 ((uint8_t)0x01) /*!= 0x08000000) && ((ADDRESS) < 0x081FFFFF)) ||\ (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) #endif /* STM32F427_437xx || STM32F429_439xx */ #if defined (STM32F40_41xxx) #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\ (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) #endif /* STM32F40_41xxx */ #if defined (STM32F401xx) #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0803FFFF)) ||\ (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) #endif /* STM32F401xx */ /** * @} */ /** @defgroup Option_Bytes_Write_Protection * @{ */ #define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ #define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ #define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ #define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ #define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ #define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ #define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ #define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ #define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ #define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ #define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ #define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ #define OB_WRP_Sector_12 ((uint32_t)0x00000001) /*!< Write protection of Sector12 */ #define OB_WRP_Sector_13 ((uint32_t)0x00000002) /*!< Write protection of Sector13 */ #define OB_WRP_Sector_14 ((uint32_t)0x00000004) /*!< Write protection of Sector14 */ #define OB_WRP_Sector_15 ((uint32_t)0x00000008) /*!< Write protection of Sector15 */ #define OB_WRP_Sector_16 ((uint32_t)0x00000010) /*!< Write protection of Sector16 */ #define OB_WRP_Sector_17 ((uint32_t)0x00000020) /*!< Write protection of Sector17 */ #define OB_WRP_Sector_18 ((uint32_t)0x00000040) /*!< Write protection of Sector18 */ #define OB_WRP_Sector_19 ((uint32_t)0x00000080) /*!< Write protection of Sector19 */ #define OB_WRP_Sector_20 ((uint32_t)0x00000100) /*!< Write protection of Sector20 */ #define OB_WRP_Sector_21 ((uint32_t)0x00000200) /*!< Write protection of Sector21 */ #define OB_WRP_Sector_22 ((uint32_t)0x00000400) /*!< Write protection of Sector22 */ #define OB_WRP_Sector_23 ((uint32_t)0x00000800) /*!< Write protection of Sector23 */ #define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ #define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) /** * @} */ /** @defgroup Selection_Protection_Mode * @{ */ #define OB_PcROP_Disable ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */ #define OB_PcROP_Enable ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */ #define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PcROP_Disable) || ((PCROP) == OB_PcROP_Enable)) /** * @} */ /** @defgroup Option_Bytes_PC_ReadWrite_Protection * @{ */ #define OB_PCROP_Sector_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */ #define OB_PCROP_Sector_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */ #define OB_PCROP_Sector_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */ #define OB_PCROP_Sector_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */ #define OB_PCROP_Sector_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */ #define OB_PCROP_Sector_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */ #define OB_PCROP_Sector_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */ #define OB_PCROP_Sector_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */ #define OB_PCROP_Sector_8 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8 */ #define OB_PCROP_Sector_9 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9 */ #define OB_PCROP_Sector_10 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10 */ #define OB_PCROP_Sector_11 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11 */ #define OB_PCROP_Sector_12 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12 */ #define OB_PCROP_Sector_13 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13 */ #define OB_PCROP_Sector_14 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14 */ #define OB_PCROP_Sector_15 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15 */ #define OB_PCROP_Sector_16 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16 */ #define OB_PCROP_Sector_17 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17 */ #define OB_PCROP_Sector_18 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18 */ #define OB_PCROP_Sector_19 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19 */ #define OB_PCROP_Sector_20 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20 */ #define OB_PCROP_Sector_21 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21 */ #define OB_PCROP_Sector_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */ #define OB_PCROP_Sector_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */ #define OB_PCROP_Sector_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */ #define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) /** * @} */ /** @defgroup FLASH_Option_Bytes_Read_Protection * @{ */ #define OB_RDP_Level_0 ((uint8_t)0xAA) #define OB_RDP_Level_1 ((uint8_t)0x55) /*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 it's no more possible to go back to level 1 or 0 */ #define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ ((LEVEL) == OB_RDP_Level_1))/*||\ ((LEVEL) == OB_RDP_Level_2))*/ /** * @} */ /** @defgroup FLASH_Option_Bytes_IWatchdog * @{ */ #define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ #define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) /** * @} */ /** @defgroup FLASH_Option_Bytes_nRST_STOP * @{ */ #define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ #define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) /** * @} */ /** @defgroup FLASH_Option_Bytes_nRST_STDBY * @{ */ #define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ #define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) /** * @} */ /** @defgroup FLASH_BOR_Reset_Level * @{ */ #define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ #define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ #define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ #define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ #define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) /** * @} */ /** @defgroup FLASH_Dual_Boot * @{ */ #define OB_Dual_BootEnabled ((uint8_t)0x10) /*!< Dual Bank Boot Enable */ #define OB_Dual_BootDisabled ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */ #define IS_OB_BOOT(BOOT) (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled)) /** * @} */ /** @defgroup FLASH_Interrupts * @{ */ #define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */ #define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */ #define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000)) /** * @} */ /** @defgroup FLASH_Flags * @{ */ #define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */ #define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */ #define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ #define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */ #define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */ #define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */ #define FLASH_FLAG_RDERR ((uint32_t)0x00000100) /*!< Read Protection error flag (PCROP) */ #define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ #define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000)) #define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \ ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \ ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \ ((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_RDERR)) /** * @} */ /** @defgroup FLASH_Program_Parallelism * @{ */ #define FLASH_PSIZE_BYTE ((uint32_t)0x00000000) #define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100) #define FLASH_PSIZE_WORD ((uint32_t)0x00000200) #define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300) #define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF) /** * @} */ /** @defgroup FLASH_Keys * @{ */ #define RDP_KEY ((uint16_t)0x00A5) #define FLASH_KEY1 ((uint32_t)0x45670123) #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) #define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B) #define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F) /** * @} */ /** * @brief ACR register byte 0 (Bits[7:0]) base address */ #define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) /** * @brief OPTCR register byte 0 (Bits[7:0]) base address */ #define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14) /** * @brief OPTCR register byte 1 (Bits[15:8]) base address */ #define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) /** * @brief OPTCR register byte 2 (Bits[23:16]) base address */ #define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16) /** * @brief OPTCR register byte 3 (Bits[31:24]) base address */ #define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17) /** * @brief OPTCR1 register byte 0 (Bits[7:0]) base address */ #define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A) /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* FLASH Interface configuration functions ************************************/ void FLASH_SetLatency(uint32_t FLASH_Latency); void FLASH_PrefetchBufferCmd(FunctionalState NewState); void FLASH_InstructionCacheCmd(FunctionalState NewState); void FLASH_DataCacheCmd(FunctionalState NewState); void FLASH_InstructionCacheReset(void); void FLASH_DataCacheReset(void); /* FLASH Memory Programming functions *****************************************/ void FLASH_Unlock(void); void FLASH_Lock(void); FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange); FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange); FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange); FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange); FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data); FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data); /* Option Bytes Programming functions *****************************************/ void FLASH_OB_Unlock(void); void FLASH_OB_Lock(void); void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState); void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP); void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState); void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState); void FLASH_OB_RDPConfig(uint8_t OB_RDP); void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); void FLASH_OB_BORConfig(uint8_t OB_BOR); void FLASH_OB_BootConfig(uint8_t OB_BOOT); FLASH_Status FLASH_OB_Launch(void); uint8_t FLASH_OB_GetUser(void); uint16_t FLASH_OB_GetWRP(void); uint16_t FLASH_OB_GetWRP1(void); uint16_t FLASH_OB_GetPCROP(void); uint16_t FLASH_OB_GetPCROP1(void); FlagStatus FLASH_OB_GetRDP(void); uint8_t FLASH_OB_GetBOR(void); /* Interrupts and flags management functions **********************************/ void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); void FLASH_ClearFlag(uint32_t FLASH_FLAG); FLASH_Status FLASH_GetStatus(void); FLASH_Status FLASH_WaitForLastOperation(void); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_FLASH_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h ================================================ /** ****************************************************************************** * @file stm32f4xx_fmc.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the FMC firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * *

© COPYRIGHT 2011 STMicroelectronics

****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_FMC_H #define __STM32F4xx_FMC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup FMC * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief Timing parameters For NOR/SRAM Banks */ typedef struct { uint32_t FMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the address setup time. This parameter can be a value between 0 and 15. @note This parameter is not used with synchronous NOR Flash memories. */ uint32_t FMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the address hold time. This parameter can be a value between 1 and 15. @note This parameter is not used with synchronous NOR Flash memories.*/ uint32_t FMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between 1 and 255. @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ uint32_t FMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between 0 and 15. @note This parameter is only used for multiplexed NOR Flash memories. */ uint32_t FMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. This parameter can be a value between 1 and 15. @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ uint32_t FMC_DataLatency; /*!< Defines the number of memory clock cycles to issue to the memory before getting the first data. The parameter value depends on the memory type as shown below: - It must be set to 0 in case of a CRAM - It is don't care in asynchronous NOR, SRAM or ROM accesses - It may assume a value between 0 and 15 in NOR Flash memories with synchronous burst mode enable */ uint32_t FMC_AccessMode; /*!< Specifies the asynchronous access mode. This parameter can be a value of @ref FMC_Access_Mode */ }FMC_NORSRAMTimingInitTypeDef; /** * @brief FMC NOR/SRAM Init structure definition */ typedef struct { uint32_t FMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. This parameter can be a value of @ref FMC_NORSRAM_Bank */ uint32_t FMC_DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the databus or not. This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ uint32_t FMC_MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory bank. This parameter can be a value of @ref FMC_Memory_Type */ uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width. This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ uint32_t FMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. This parameter can be a value of @ref FMC_Burst_Access_Mode */ uint32_t FMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ uint32_t FMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash memory, valid only when accessing Flash memories in burst mode. This parameter can be a value of @ref FMC_Wrap_Mode */ uint32_t FMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. This parameter can be a value of @ref FMC_Wait_Timing */ uint32_t FMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FMC. This parameter can be a value of @ref FMC_Write_Operation */ uint32_t FMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. This parameter can be a value of @ref FMC_Wait_Signal */ uint32_t FMC_ExtendedMode; /*!< Enables or disables the extended mode. This parameter can be a value of @ref FMC_Extended_Mode */ uint32_t FMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. This parameter can be a value of @ref FMC_AsynchronousWait */ uint32_t FMC_WriteBurst; /*!< Enables or disables the write burst operation. This parameter can be a value of @ref FMC_Write_Burst */ uint32_t FMC_ContinousClock; /*!< Enables or disables the FMC clock output to external memory devices. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. This parameter can be a value of @ref FMC_Continous_Clock */ FMC_NORSRAMTimingInitTypeDef* FMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/ FMC_NORSRAMTimingInitTypeDef* FMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/ }FMC_NORSRAMInitTypeDef; /** * @brief Timing parameters For FMC NAND and PCCARD Banks */ typedef struct { uint32_t FMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before the command assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a value between 0 and 255.*/ uint32_t FMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the command for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0 and 255 */ uint32_t FMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address (and data for write access) after the command de-assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0 and 255 */ uint32_t FMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the start of a NAND-Flash write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0 and 255 */ }FMC_NAND_PCCARDTimingInitTypeDef; /** * @brief FMC NAND Init structure definition */ typedef struct { uint32_t FMC_Bank; /*!< Specifies the NAND memory bank that will be used. This parameter can be a value of @ref FMC_NAND_Bank */ uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. This parameter can be any value of @ref FMC_Wait_feature */ uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width. This parameter can be any value of @ref FMC_NAND_Data_Width */ uint32_t FMC_ECC; /*!< Enables or disables the ECC computation. This parameter can be any value of @ref FMC_ECC */ uint32_t FMC_ECCPageSize; /*!< Defines the page size for the extended ECC. This parameter can be any value of @ref FMC_ECC_Page_Size */ uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between 0 and 255. */ uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between 0 and 255 */ FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */ FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */ }FMC_NANDInitTypeDef; /** * @brief FMC PCCARD Init structure definition */ typedef struct { uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. This parameter can be any value of @ref FMC_Wait_feature */ uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between 0 and 255. */ uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between 0 and 255 */ FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */ FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */ FMC_NAND_PCCARDTimingInitTypeDef* FMC_IOSpaceTimingStruct; /*!< FMC IO Space Timing */ }FMC_PCCARDInitTypeDef; /** * @brief Timing parameters for FMC SDRAM Banks */ typedef struct { uint32_t FMC_LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and an active or Refresh command in number of memory clock cycles. This parameter can be a value between 1 and 16. */ uint32_t FMC_ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to issuing the Activate command in number of memory clock cycles. This parameter can be a value between 1 and 16. */ uint32_t FMC_SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock cycles. This parameter can be a value between 1 and 16. */ uint32_t FMC_RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command and the delay between two consecutive Refresh commands in number of memory clock cycles. This parameter can be a value between 1 and 16. */ uint32_t FMC_WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. This parameter can be a value between 1 and 16. */ uint32_t FMC_RPDelay; /*!< Defines the delay between a Precharge Command and an other command in number of memory clock cycles. This parameter can be a value between 1 and 16. */ uint32_t FMC_RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write command in number of memory clock cycles. This parameter can be a value between 1 and 16. */ }FMC_SDRAMTimingInitTypeDef; /** * @brief Command parameters for FMC SDRAM Banks */ typedef struct { uint32_t FMC_CommandMode; /*!< Defines the command issued to the SDRAM device. This parameter can be a value of @ref FMC_Command_Mode. */ uint32_t FMC_CommandTarget; /*!< Defines which bank (1 or 2) the command will be issued to. This parameter can be a value of @ref FMC_Command_Target. */ uint32_t FMC_AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued in auto refresh mode. This parameter can be a value between 1 and 16. */ uint32_t FMC_ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ }FMC_SDRAMCommandTypeDef; /** * @brief FMC SDRAM Init structure definition */ typedef struct { uint32_t FMC_Bank; /*!< Specifies the SDRAM memory bank that will be used. This parameter can be a value of @ref FMC_SDRAM_Bank */ uint32_t FMC_ColumnBitsNumber; /*!< Defines the number of bits of column address. This parameter can be a value of @ref FMC_ColumnBits_Number. */ uint32_t FMC_RowBitsNumber; /*!< Defines the number of bits of column address.. This parameter can be a value of @ref FMC_RowBits_Number. */ uint32_t FMC_SDMemoryDataWidth; /*!< Defines the memory device width. This parameter can be a value of @ref FMC_SDMemory_Data_Width. */ uint32_t FMC_InternalBankNumber; /*!< Defines the number of bits of column address. This parameter can be of @ref FMC_InternalBank_Number. */ uint32_t FMC_CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. This parameter can be a value of @ref FMC_CAS_Latency. */ uint32_t FMC_WriteProtection; /*!< Enables the SDRAM bank to be accessed in write mode. This parameter can be a value of @ref FMC_Write_Protection. */ uint32_t FMC_SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM Banks and they allow to disable the clock before changing frequency. This parameter can be a value of @ref FMC_SDClock_Period. */ uint32_t FMC_ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read commands during the CAS latency and stores data in the Read FIFO. This parameter can be a value of @ref FMC_Read_Burst. */ uint32_t FMC_ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. This parameter can be a value of @ref FMC_ReadPipe_Delay. */ FMC_SDRAMTimingInitTypeDef* FMC_SDRAMTimingStruct; /*!< Timing Parameters for write and read access*/ }FMC_SDRAMInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup FMC_Exported_Constants * @{ */ /** @defgroup FMC_NORSRAM_Bank * @{ */ #define FMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) #define FMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) #define FMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) #define FMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_Bank1_NORSRAM1) || \ ((BANK) == FMC_Bank1_NORSRAM2) || \ ((BANK) == FMC_Bank1_NORSRAM3) || \ ((BANK) == FMC_Bank1_NORSRAM4)) /** * @} */ /** @defgroup FMC_NAND_Bank * @{ */ #define FMC_Bank2_NAND ((uint32_t)0x00000010) #define FMC_Bank3_NAND ((uint32_t)0x00000100) #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \ ((BANK) == FMC_Bank3_NAND)) /** * @} */ /** @defgroup FMC_PCCARD_Bank * @{ */ #define FMC_Bank4_PCCARD ((uint32_t)0x00001000) /** * @} */ /** @defgroup FMC_SDRAM_Bank * @{ */ #define FMC_Bank1_SDRAM ((uint32_t)0x00000000) #define FMC_Bank2_SDRAM ((uint32_t)0x00000001) #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_Bank1_SDRAM) || \ ((BANK) == FMC_Bank2_SDRAM)) /** * @} */ /** @defgroup FMC_NOR_SRAM_Controller * @{ */ /** @defgroup FMC_Data_Address_Bus_Multiplexing * @{ */ #define FMC_DataAddressMux_Disable ((uint32_t)0x00000000) #define FMC_DataAddressMux_Enable ((uint32_t)0x00000002) #define IS_FMC_MUX(MUX) (((MUX) == FMC_DataAddressMux_Disable) || \ ((MUX) == FMC_DataAddressMux_Enable)) /** * @} */ /** @defgroup FMC_Memory_Type * @{ */ #define FMC_MemoryType_SRAM ((uint32_t)0x00000000) #define FMC_MemoryType_PSRAM ((uint32_t)0x00000004) #define FMC_MemoryType_NOR ((uint32_t)0x00000008) #define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MemoryType_SRAM) || \ ((MEMORY) == FMC_MemoryType_PSRAM)|| \ ((MEMORY) == FMC_MemoryType_NOR)) /** * @} */ /** @defgroup FMC_NORSRAM_Data_Width * @{ */ #define FMC_NORSRAM_MemoryDataWidth_8b ((uint32_t)0x00000000) #define FMC_NORSRAM_MemoryDataWidth_16b ((uint32_t)0x00000010) #define FMC_NORSRAM_MemoryDataWidth_32b ((uint32_t)0x00000020) #define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MemoryDataWidth_8b) || \ ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_16b) || \ ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_32b)) /** * @} */ /** @defgroup FMC_Burst_Access_Mode * @{ */ #define FMC_BurstAccessMode_Disable ((uint32_t)0x00000000) #define FMC_BurstAccessMode_Enable ((uint32_t)0x00000100) #define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BurstAccessMode_Disable) || \ ((STATE) == FMC_BurstAccessMode_Enable)) /** * @} */ /** @defgroup FMC_AsynchronousWait * @{ */ #define FMC_AsynchronousWait_Disable ((uint32_t)0x00000000) #define FMC_AsynchronousWait_Enable ((uint32_t)0x00008000) #define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_AsynchronousWait_Disable) || \ ((STATE) == FMC_AsynchronousWait_Enable)) /** * @} */ /** @defgroup FMC_Wait_Signal_Polarity * @{ */ #define FMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) #define FMC_WaitSignalPolarity_High ((uint32_t)0x00000200) #define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WaitSignalPolarity_Low) || \ ((POLARITY) == FMC_WaitSignalPolarity_High)) /** * @} */ /** @defgroup FMC_Wrap_Mode * @{ */ #define FMC_WrapMode_Disable ((uint32_t)0x00000000) #define FMC_WrapMode_Enable ((uint32_t)0x00000400) #define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WrapMode_Disable) || \ ((MODE) == FMC_WrapMode_Enable)) /** * @} */ /** @defgroup FMC_Wait_Timing * @{ */ #define FMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) #define FMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) #define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WaitSignalActive_BeforeWaitState) || \ ((ACTIVE) == FMC_WaitSignalActive_DuringWaitState)) /** * @} */ /** @defgroup FMC_Write_Operation * @{ */ #define FMC_WriteOperation_Disable ((uint32_t)0x00000000) #define FMC_WriteOperation_Enable ((uint32_t)0x00001000) #define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WriteOperation_Disable) || \ ((OPERATION) == FMC_WriteOperation_Enable)) /** * @} */ /** @defgroup FMC_Wait_Signal * @{ */ #define FMC_WaitSignal_Disable ((uint32_t)0x00000000) #define FMC_WaitSignal_Enable ((uint32_t)0x00002000) #define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WaitSignal_Disable) || \ ((SIGNAL) == FMC_WaitSignal_Enable)) /** * @} */ /** @defgroup FMC_Extended_Mode * @{ */ #define FMC_ExtendedMode_Disable ((uint32_t)0x00000000) #define FMC_ExtendedMode_Enable ((uint32_t)0x00004000) #define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_ExtendedMode_Disable) || \ ((MODE) == FMC_ExtendedMode_Enable)) /** * @} */ /** @defgroup FMC_Write_Burst * @{ */ #define FMC_WriteBurst_Disable ((uint32_t)0x00000000) #define FMC_WriteBurst_Enable ((uint32_t)0x00080000) #define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WriteBurst_Disable) || \ ((BURST) == FMC_WriteBurst_Enable)) /** * @} */ /** @defgroup FMC_Continous_Clock * @{ */ #define FMC_CClock_SyncOnly ((uint32_t)0x00000000) #define FMC_CClock_SyncAsync ((uint32_t)0x00100000) #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CClock_SyncOnly) || \ ((CCLOCK) == FMC_CClock_SyncAsync)) /** * @} */ /** @defgroup FMC_Address_Setup_Time * @{ */ #define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15) /** * @} */ /** @defgroup FMC_Address_Hold_Time * @{ */ #define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15)) /** * @} */ /** @defgroup FMC_Data_Setup_Time * @{ */ #define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255)) /** * @} */ /** @defgroup FMC_Bus_Turn_around_Duration * @{ */ #define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15) /** * @} */ /** @defgroup FMC_CLK_Division * @{ */ #define IS_FMC_CLK_DIV(DIV) (((DIV) > 0) && ((DIV) <= 15)) /** * @} */ /** @defgroup FMC_Data_Latency * @{ */ #define IS_FMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 15) /** * @} */ /** @defgroup FMC_Access_Mode * @{ */ #define FMC_AccessMode_A ((uint32_t)0x00000000) #define FMC_AccessMode_B ((uint32_t)0x10000000) #define FMC_AccessMode_C ((uint32_t)0x20000000) #define FMC_AccessMode_D ((uint32_t)0x30000000) #define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_AccessMode_A) || \ ((MODE) == FMC_AccessMode_B) || \ ((MODE) == FMC_AccessMode_C) || \ ((MODE) == FMC_AccessMode_D)) /** * @} */ /** * @} */ /** @defgroup FMC_NAND_PCCARD_Controller * @{ */ /** @defgroup FMC_Wait_feature * @{ */ #define FMC_Waitfeature_Disable ((uint32_t)0x00000000) #define FMC_Waitfeature_Enable ((uint32_t)0x00000002) #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_Waitfeature_Disable) || \ ((FEATURE) == FMC_Waitfeature_Enable)) /** * @} */ /** @defgroup FMC_NAND_Data_Width * @{ */ #define FMC_NAND_MemoryDataWidth_8b ((uint32_t)0x00000000) #define FMC_NAND_MemoryDataWidth_16b ((uint32_t)0x00000010) #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MemoryDataWidth_8b) || \ ((WIDTH) == FMC_NAND_MemoryDataWidth_16b)) /** * @} */ /** @defgroup FMC_ECC * @{ */ #define FMC_ECC_Disable ((uint32_t)0x00000000) #define FMC_ECC_Enable ((uint32_t)0x00000040) #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_ECC_Disable) || \ ((STATE) == FMC_ECC_Enable)) /** * @} */ /** @defgroup FMC_ECC_Page_Size * @{ */ #define FMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) #define FMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) #define FMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) #define FMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) #define FMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) #define FMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_ECCPageSize_256Bytes) || \ ((SIZE) == FMC_ECCPageSize_512Bytes) || \ ((SIZE) == FMC_ECCPageSize_1024Bytes) || \ ((SIZE) == FMC_ECCPageSize_2048Bytes) || \ ((SIZE) == FMC_ECCPageSize_4096Bytes) || \ ((SIZE) == FMC_ECCPageSize_8192Bytes)) /** * @} */ /** @defgroup FMC_TCLR_Setup_Time * @{ */ #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255) /** * @} */ /** @defgroup FMC_TAR_Setup_Time * @{ */ #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255) /** * @} */ /** @defgroup FMC_Setup_Time * @{ */ #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255) /** * @} */ /** @defgroup FMC_Wait_Setup_Time * @{ */ #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255) /** * @} */ /** @defgroup FMC_Hold_Setup_Time * @{ */ #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255) /** * @} */ /** @defgroup FMC_HiZ_Setup_Time * @{ */ #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255) /** * @} */ /** * @} */ /** @defgroup FMC_NOR_SRAM_Controller * @{ */ /** @defgroup FMC_ColumnBits_Number * @{ */ #define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000) #define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001) #define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002) #define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003) #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_ColumnBits_Number_8b) || \ ((COLUMN) == FMC_ColumnBits_Number_9b) || \ ((COLUMN) == FMC_ColumnBits_Number_10b) || \ ((COLUMN) == FMC_ColumnBits_Number_11b)) /** * @} */ /** @defgroup FMC_RowBits_Number * @{ */ #define FMC_RowBits_Number_11b ((uint32_t)0x00000000) #define FMC_RowBits_Number_12b ((uint32_t)0x00000004) #define FMC_RowBits_Number_13b ((uint32_t)0x00000008) #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_RowBits_Number_11b) || \ ((ROW) == FMC_RowBits_Number_12b) || \ ((ROW) == FMC_RowBits_Number_13b)) /** * @} */ /** @defgroup FMC_SDMemory_Data_Width * @{ */ #define FMC_SDMemory_Width_8b ((uint32_t)0x00000000) #define FMC_SDMemory_Width_16b ((uint32_t)0x00000010) #define FMC_SDMemory_Width_32b ((uint32_t)0x00000020) #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDMemory_Width_8b) || \ ((WIDTH) == FMC_SDMemory_Width_16b) || \ ((WIDTH) == FMC_SDMemory_Width_32b)) /** * @} */ /** @defgroup FMC_InternalBank_Number * @{ */ #define FMC_InternalBank_Number_2 ((uint32_t)0x00000000) #define FMC_InternalBank_Number_4 ((uint32_t)0x00000040) #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_InternalBank_Number_2) || \ ((NUMBER) == FMC_InternalBank_Number_4)) /** * @} */ /** @defgroup FMC_CAS_Latency * @{ */ #define FMC_CAS_Latency_1 ((uint32_t)0x00000080) #define FMC_CAS_Latency_2 ((uint32_t)0x00000100) #define FMC_CAS_Latency_3 ((uint32_t)0x00000180) #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_CAS_Latency_1) || \ ((LATENCY) == FMC_CAS_Latency_2) || \ ((LATENCY) == FMC_CAS_Latency_3)) /** * @} */ /** @defgroup FMC_Write_Protection * @{ */ #define FMC_Write_Protection_Disable ((uint32_t)0x00000000) #define FMC_Write_Protection_Enable ((uint32_t)0x00000200) #define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_Write_Protection_Disable) || \ ((WRITE) == FMC_Write_Protection_Enable)) /** * @} */ /** @defgroup FMC_SDClock_Period * @{ */ #define FMC_SDClock_Disable ((uint32_t)0x00000000) #define FMC_SDClock_Period_2 ((uint32_t)0x00000800) #define FMC_SDClock_Period_3 ((uint32_t)0x00000C00) #define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDClock_Disable) || \ ((PERIOD) == FMC_SDClock_Period_2) || \ ((PERIOD) == FMC_SDClock_Period_3)) /** * @} */ /** @defgroup FMC_Read_Burst * @{ */ #define FMC_Read_Burst_Disable ((uint32_t)0x00000000) #define FMC_Read_Burst_Enable ((uint32_t)0x00001000) #define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_Read_Burst_Disable) || \ ((RBURST) == FMC_Read_Burst_Enable)) /** * @} */ /** @defgroup FMC_ReadPipe_Delay * @{ */ #define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000) #define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000) #define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000) #define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_ReadPipe_Delay_0) || \ ((DELAY) == FMC_ReadPipe_Delay_1) || \ ((DELAY) == FMC_ReadPipe_Delay_2)) /** * @} */ /** @defgroup FMC_LoadToActive_Delay * @{ */ #define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) /** * @} */ /** @defgroup FMC_ExitSelfRefresh_Delay * @{ */ #define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) /** * @} */ /** @defgroup FMC_SelfRefresh_Time * @{ */ #define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16)) /** * @} */ /** @defgroup FMC_RowCycle_Delay * @{ */ #define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) /** * @} */ /** @defgroup FMC_Write_Recovery_Time * @{ */ #define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16)) /** * @} */ /** @defgroup FMC_RP_Delay * @{ */ #define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) /** * @} */ /** @defgroup FMC_RCD_Delay * @{ */ #define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) /** * @} */ /** @defgroup FMC_Command_Mode * @{ */ #define FMC_Command_Mode_normal ((uint32_t)0x00000000) #define FMC_Command_Mode_CLK_Enabled ((uint32_t)0x00000001) #define FMC_Command_Mode_PALL ((uint32_t)0x00000002) #define FMC_Command_Mode_AutoRefresh ((uint32_t)0x00000003) #define FMC_Command_Mode_LoadMode ((uint32_t)0x00000004) #define FMC_Command_Mode_Selfrefresh ((uint32_t)0x00000005) #define FMC_Command_Mode_PowerDown ((uint32_t)0x00000006) #define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_Command_Mode_normal) || \ ((COMMAND) == FMC_Command_Mode_CLK_Enabled) || \ ((COMMAND) == FMC_Command_Mode_PALL) || \ ((COMMAND) == FMC_Command_Mode_AutoRefresh) || \ ((COMMAND) == FMC_Command_Mode_LoadMode) || \ ((COMMAND) == FMC_Command_Mode_Selfrefresh) || \ ((COMMAND) == FMC_Command_Mode_PowerDown)) /** * @} */ /** @defgroup FMC_Command_Target * @{ */ #define FMC_Command_Target_bank2 ((uint32_t)0x00000008) #define FMC_Command_Target_bank1 ((uint32_t)0x00000010) #define FMC_Command_Target_bank1_2 ((uint32_t)0x00000018) #define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_Command_Target_bank1) || \ ((TARGET) == FMC_Command_Target_bank2) || \ ((TARGET) == FMC_Command_Target_bank1_2)) /** * @} */ /** @defgroup FMC_AutoRefresh_Number * @{ */ #define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16)) /** * @} */ /** @defgroup FMC_ModeRegister_Definition * @{ */ #define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191) /** * @} */ /** @defgroup FMC_Mode_Status * @{ */ #define FMC_NormalMode_Status ((uint32_t)0x00000000) #define FMC_SelfRefreshMode_Status FMC_SDSR_MODES1_0 #define FMC_PowerDownMode_Status FMC_SDSR_MODES1_1 #define IS_FMC_MODE_STATUS(STATUS) (((STATUS) == FMC_NormalMode_Status) || \ ((STATUS) == FMC_SelfRefreshMode_Status) || \ ((STATUS) == FMC_PowerDownMode_Status)) /** * @} */ /** * @} */ /** @defgroup FMC_Interrupt_sources * @{ */ #define FMC_IT_RisingEdge ((uint32_t)0x00000008) #define FMC_IT_Level ((uint32_t)0x00000010) #define FMC_IT_FallingEdge ((uint32_t)0x00000020) #define FMC_IT_Refresh ((uint32_t)0x00004000) #define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000)) #define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RisingEdge) || \ ((IT) == FMC_IT_Level) || \ ((IT) == FMC_IT_FallingEdge) || \ ((IT) == FMC_IT_Refresh)) #define IS_FMC_IT_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \ ((BANK) == FMC_Bank3_NAND) || \ ((BANK) == FMC_Bank4_PCCARD) || \ ((BANK) == FMC_Bank1_SDRAM) || \ ((BANK) == FMC_Bank2_SDRAM)) /** * @} */ /** @defgroup FMC_Flags * @{ */ #define FMC_FLAG_RisingEdge ((uint32_t)0x00000001) #define FMC_FLAG_Level ((uint32_t)0x00000002) #define FMC_FLAG_FallingEdge ((uint32_t)0x00000004) #define FMC_FLAG_FEMPT ((uint32_t)0x00000040) #define FMC_FLAG_Refresh FMC_SDSR_RE #define FMC_FLAG_Busy FMC_SDSR_BUSY #define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RisingEdge) || \ ((FLAG) == FMC_FLAG_Level) || \ ((FLAG) == FMC_FLAG_FallingEdge) || \ ((FLAG) == FMC_FLAG_FEMPT) || \ ((FLAG) == FMC_FLAG_Refresh) || \ ((FLAG) == FMC_SDSR_BUSY)) #define IS_FMC_GETFLAG_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \ ((BANK) == FMC_Bank3_NAND) || \ ((BANK) == FMC_Bank4_PCCARD) || \ ((BANK) == FMC_Bank1_SDRAM) || \ ((BANK) == FMC_Bank2_SDRAM) || \ ((BANK) == (FMC_Bank1_SDRAM | FMC_Bank2_SDRAM))) #define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) /** * @} */ /** @defgroup FMC_Refresh_count * @{ */ #define IS_FMC_REFRESH_COUNT(COUNT) ((COUNT) <= 8191) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* NOR/SRAM Controller functions **********************************************/ void FMC_NORSRAMDeInit(uint32_t FMC_Bank); void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct); void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct); void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState); /* NAND Controller functions **************************************************/ void FMC_NANDDeInit(uint32_t FMC_Bank); void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct); void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct); void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState); void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState); uint32_t FMC_GetECC(uint32_t FMC_Bank); /* PCCARD Controller functions ************************************************/ void FMC_PCCARDDeInit(void); void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct); void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct); void FMC_PCCARDCmd(FunctionalState NewState); /* SDRAM Controller functions ************************************************/ void FMC_SDRAMDeInit(uint32_t FMC_Bank); void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct); void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct); void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct); uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank); void FMC_SetRefreshCount(uint32_t FMC_Count); void FMC_SetAutoRefresh_Number(uint32_t FMC_Number); void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState); FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG); void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG); ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT); void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_FMC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h ================================================ /** ****************************************************************************** * @file stm32f4xx_fsmc.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the FSMC firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_FSMC_H #define __STM32F4xx_FSMC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup FSMC * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief Timing parameters For NOR/SRAM Banks */ typedef struct { uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the address setup time. This parameter can be a value between 0 and 0xF. @note This parameter is not used with synchronous NOR Flash memories. */ uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the address hold time. This parameter can be a value between 0 and 0xF. @note This parameter is not used with synchronous NOR Flash memories.*/ uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between 0 and 0xFF. @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between 0 and 0xF. @note This parameter is only used for multiplexed NOR Flash memories. */ uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. This parameter can be a value between 1 and 0xF. @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue to the memory before getting the first data. The parameter value depends on the memory type as shown below: - It must be set to 0 in case of a CRAM - It is don't care in asynchronous NOR, SRAM or ROM accesses - It may assume a value between 0 and 0xF in NOR Flash memories with synchronous burst mode enable */ uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. This parameter can be a value of @ref FSMC_Access_Mode */ }FSMC_NORSRAMTimingInitTypeDef; /** * @brief FSMC NOR/SRAM Init structure definition */ typedef struct { uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. This parameter can be a value of @ref FSMC_NORSRAM_Bank */ uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory bank. This parameter can be a value of @ref FSMC_Memory_Type */ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. This parameter can be a value of @ref FSMC_Data_Width */ uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. This parameter can be a value of @ref FSMC_Burst_Access_Mode */ uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. This parameter can be a value of @ref FSMC_AsynchronousWait */ uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash memory, valid only when accessing Flash memories in burst mode. This parameter can be a value of @ref FSMC_Wrap_Mode */ uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. This parameter can be a value of @ref FSMC_Wait_Timing */ uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. This parameter can be a value of @ref FSMC_Write_Operation */ uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. This parameter can be a value of @ref FSMC_Wait_Signal */ uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. This parameter can be a value of @ref FSMC_Extended_Mode */ uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. This parameter can be a value of @ref FSMC_Write_Burst */ FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/ FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/ }FSMC_NORSRAMInitTypeDef; /** * @brief Timing parameters For FSMC NAND and PCCARD Banks */ typedef struct { uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before the command assertion for NAND Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a value between 0 and 0xFF.*/ uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the command for NAND Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0x00 and 0xFF */ uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address (and data for write access) after the command de-assertion for NAND Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0x00 and 0xFF */ uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the data bus is kept in HiZ after the start of a NAND Flash write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between 0x00 and 0xFF */ }FSMC_NAND_PCCARDTimingInitTypeDef; /** * @brief FSMC NAND Init structure definition */ typedef struct { uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. This parameter can be a value of @ref FSMC_NAND_Bank */ uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. This parameter can be any value of @ref FSMC_Wait_feature */ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. This parameter can be any value of @ref FSMC_Data_Width */ uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. This parameter can be any value of @ref FSMC_ECC */ uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. This parameter can be any value of @ref FSMC_ECC_Page_Size */ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between 0 and 0xFF. */ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between 0x0 and 0xFF */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ }FSMC_NANDInitTypeDef; /** * @brief FSMC PCCARD Init structure definition */ typedef struct { uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. This parameter can be any value of @ref FSMC_Wait_feature */ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. This parameter can be a value between 0 and 0xFF. */ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between 0x0 and 0xFF */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ }FSMC_PCCARDInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup FSMC_Exported_Constants * @{ */ /** @defgroup FSMC_NORSRAM_Bank * @{ */ #define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) #define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) #define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) #define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) /** * @} */ /** @defgroup FSMC_NAND_Bank * @{ */ #define FSMC_Bank2_NAND ((uint32_t)0x00000010) #define FSMC_Bank3_NAND ((uint32_t)0x00000100) /** * @} */ /** @defgroup FSMC_PCCARD_Bank * @{ */ #define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) /** * @} */ #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ ((BANK) == FSMC_Bank1_NORSRAM2) || \ ((BANK) == FSMC_Bank1_NORSRAM3) || \ ((BANK) == FSMC_Bank1_NORSRAM4)) #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ ((BANK) == FSMC_Bank3_NAND)) #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ ((BANK) == FSMC_Bank3_NAND) || \ ((BANK) == FSMC_Bank4_PCCARD)) #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ ((BANK) == FSMC_Bank3_NAND) || \ ((BANK) == FSMC_Bank4_PCCARD)) /** @defgroup FSMC_NOR_SRAM_Controller * @{ */ /** @defgroup FSMC_Data_Address_Bus_Multiplexing * @{ */ #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ ((MUX) == FSMC_DataAddressMux_Enable)) /** * @} */ /** @defgroup FSMC_Memory_Type * @{ */ #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) #define FSMC_MemoryType_NOR ((uint32_t)0x00000008) #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ ((MEMORY) == FSMC_MemoryType_NOR)) /** * @} */ /** @defgroup FSMC_Data_Width * @{ */ #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ ((WIDTH) == FSMC_MemoryDataWidth_16b)) /** * @} */ /** @defgroup FSMC_Burst_Access_Mode * @{ */ #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ ((STATE) == FSMC_BurstAccessMode_Enable)) /** * @} */ /** @defgroup FSMC_AsynchronousWait * @{ */ #define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) #define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ ((STATE) == FSMC_AsynchronousWait_Enable)) /** * @} */ /** @defgroup FSMC_Wait_Signal_Polarity * @{ */ #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ ((POLARITY) == FSMC_WaitSignalPolarity_High)) /** * @} */ /** @defgroup FSMC_Wrap_Mode * @{ */ #define FSMC_WrapMode_Disable ((uint32_t)0x00000000) #define FSMC_WrapMode_Enable ((uint32_t)0x00000400) #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ ((MODE) == FSMC_WrapMode_Enable)) /** * @} */ /** @defgroup FSMC_Wait_Timing * @{ */ #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) /** * @} */ /** @defgroup FSMC_Write_Operation * @{ */ #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ ((OPERATION) == FSMC_WriteOperation_Enable)) /** * @} */ /** @defgroup FSMC_Wait_Signal * @{ */ #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ ((SIGNAL) == FSMC_WaitSignal_Enable)) /** * @} */ /** @defgroup FSMC_Extended_Mode * @{ */ #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ ((MODE) == FSMC_ExtendedMode_Enable)) /** * @} */ /** @defgroup FSMC_Write_Burst * @{ */ #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ ((BURST) == FSMC_WriteBurst_Enable)) /** * @} */ /** @defgroup FSMC_Address_Setup_Time * @{ */ #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) /** * @} */ /** @defgroup FSMC_Address_Hold_Time * @{ */ #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) /** * @} */ /** @defgroup FSMC_Data_Setup_Time * @{ */ #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) /** * @} */ /** @defgroup FSMC_Bus_Turn_around_Duration * @{ */ #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) /** * @} */ /** @defgroup FSMC_CLK_Division * @{ */ #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) /** * @} */ /** @defgroup FSMC_Data_Latency * @{ */ #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) /** * @} */ /** @defgroup FSMC_Access_Mode * @{ */ #define FSMC_AccessMode_A ((uint32_t)0x00000000) #define FSMC_AccessMode_B ((uint32_t)0x10000000) #define FSMC_AccessMode_C ((uint32_t)0x20000000) #define FSMC_AccessMode_D ((uint32_t)0x30000000) #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ ((MODE) == FSMC_AccessMode_B) || \ ((MODE) == FSMC_AccessMode_C) || \ ((MODE) == FSMC_AccessMode_D)) /** * @} */ /** * @} */ /** @defgroup FSMC_NAND_PCCARD_Controller * @{ */ /** @defgroup FSMC_Wait_feature * @{ */ #define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) #define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ ((FEATURE) == FSMC_Waitfeature_Enable)) /** * @} */ /** @defgroup FSMC_ECC * @{ */ #define FSMC_ECC_Disable ((uint32_t)0x00000000) #define FSMC_ECC_Enable ((uint32_t)0x00000040) #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ ((STATE) == FSMC_ECC_Enable)) /** * @} */ /** @defgroup FSMC_ECC_Page_Size * @{ */ #define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) #define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) #define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) #define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) #define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) #define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ ((SIZE) == FSMC_ECCPageSize_8192Bytes)) /** * @} */ /** @defgroup FSMC_TCLR_Setup_Time * @{ */ #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_TAR_Setup_Time * @{ */ #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_Setup_Time * @{ */ #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_Wait_Setup_Time * @{ */ #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_Hold_Setup_Time * @{ */ #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_HiZ_Setup_Time * @{ */ #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) /** * @} */ /** @defgroup FSMC_Interrupt_sources * @{ */ #define FSMC_IT_RisingEdge ((uint32_t)0x00000008) #define FSMC_IT_Level ((uint32_t)0x00000010) #define FSMC_IT_FallingEdge ((uint32_t)0x00000020) #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ ((IT) == FSMC_IT_Level) || \ ((IT) == FSMC_IT_FallingEdge)) /** * @} */ /** @defgroup FSMC_Flags * @{ */ #define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) #define FSMC_FLAG_Level ((uint32_t)0x00000002) #define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ ((FLAG) == FSMC_FLAG_Level) || \ ((FLAG) == FSMC_FLAG_FallingEdge) || \ ((FLAG) == FSMC_FLAG_FEMPT)) #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) /** * @} */ /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* NOR/SRAM Controller functions **********************************************/ void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); /* NAND Controller functions **************************************************/ void FSMC_NANDDeInit(uint32_t FSMC_Bank); void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); uint32_t FSMC_GetECC(uint32_t FSMC_Bank); /* PCCARD Controller functions ************************************************/ void FSMC_PCCARDDeInit(void); void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); void FSMC_PCCARDCmd(FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_FSMC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h ================================================ /** ****************************************************************************** * @file stm32f4xx_gpio.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the GPIO firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_GPIO_H #define __STM32F4xx_GPIO_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup GPIO * @{ */ /* Exported types ------------------------------------------------------------*/ #define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ ((PERIPH) == GPIOB) || \ ((PERIPH) == GPIOC) || \ ((PERIPH) == GPIOD) || \ ((PERIPH) == GPIOE) || \ ((PERIPH) == GPIOF) || \ ((PERIPH) == GPIOG) || \ ((PERIPH) == GPIOH) || \ ((PERIPH) == GPIOI) || \ ((PERIPH) == GPIOJ) || \ ((PERIPH) == GPIOK)) /** * @brief GPIO Configuration Mode enumeration */ typedef enum { GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */ }GPIOMode_TypeDef; #define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \ ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) /** * @brief GPIO Output type enumeration */ typedef enum { GPIO_OType_PP = 0x00, GPIO_OType_OD = 0x01 }GPIOOType_TypeDef; #define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) /** * @brief GPIO Output Maximum frequency enumeration */ typedef enum { GPIO_Low_Speed = 0x00, /*!< Low speed */ GPIO_Medium_Speed = 0x01, /*!< Medium speed */ GPIO_Fast_Speed = 0x02, /*!< Fast speed */ GPIO_High_Speed = 0x03 /*!< High speed */ }GPIOSpeed_TypeDef; /* Add legacy definition */ #define GPIO_Speed_2MHz GPIO_Low_Speed #define GPIO_Speed_25MHz GPIO_Medium_Speed #define GPIO_Speed_50MHz GPIO_Fast_Speed #define GPIO_Speed_100MHz GPIO_High_Speed #define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \ ((SPEED) == GPIO_Fast_Speed)|| ((SPEED) == GPIO_High_Speed)) /** * @brief GPIO Configuration PullUp PullDown enumeration */ typedef enum { GPIO_PuPd_NOPULL = 0x00, GPIO_PuPd_UP = 0x01, GPIO_PuPd_DOWN = 0x02 }GPIOPuPd_TypeDef; #define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ ((PUPD) == GPIO_PuPd_DOWN)) /** * @brief GPIO Bit SET and Bit RESET enumeration */ typedef enum { Bit_RESET = 0, Bit_SET }BitAction; #define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) /** * @brief GPIO Init structure definition */ typedef struct { uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. This parameter can be any value of @ref GPIO_pins_define */ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. This parameter can be a value of @ref GPIOMode_TypeDef */ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. This parameter can be a value of @ref GPIOSpeed_TypeDef */ GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. This parameter can be a value of @ref GPIOOType_TypeDef */ GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. This parameter can be a value of @ref GPIOPuPd_TypeDef */ }GPIO_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup GPIO_Exported_Constants * @{ */ /** @defgroup GPIO_pins_define * @{ */ #define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ #define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ #define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ #define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ #define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ #define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ #define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ #define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ #define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ #define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ #define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ #define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ #define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ #define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ #define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ #define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ #define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ #define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) #define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ ((PIN) == GPIO_Pin_1) || \ ((PIN) == GPIO_Pin_2) || \ ((PIN) == GPIO_Pin_3) || \ ((PIN) == GPIO_Pin_4) || \ ((PIN) == GPIO_Pin_5) || \ ((PIN) == GPIO_Pin_6) || \ ((PIN) == GPIO_Pin_7) || \ ((PIN) == GPIO_Pin_8) || \ ((PIN) == GPIO_Pin_9) || \ ((PIN) == GPIO_Pin_10) || \ ((PIN) == GPIO_Pin_11) || \ ((PIN) == GPIO_Pin_12) || \ ((PIN) == GPIO_Pin_13) || \ ((PIN) == GPIO_Pin_14) || \ ((PIN) == GPIO_Pin_15)) /** * @} */ /** @defgroup GPIO_Pin_sources * @{ */ #define GPIO_PinSource0 ((uint8_t)0x00) #define GPIO_PinSource1 ((uint8_t)0x01) #define GPIO_PinSource2 ((uint8_t)0x02) #define GPIO_PinSource3 ((uint8_t)0x03) #define GPIO_PinSource4 ((uint8_t)0x04) #define GPIO_PinSource5 ((uint8_t)0x05) #define GPIO_PinSource6 ((uint8_t)0x06) #define GPIO_PinSource7 ((uint8_t)0x07) #define GPIO_PinSource8 ((uint8_t)0x08) #define GPIO_PinSource9 ((uint8_t)0x09) #define GPIO_PinSource10 ((uint8_t)0x0A) #define GPIO_PinSource11 ((uint8_t)0x0B) #define GPIO_PinSource12 ((uint8_t)0x0C) #define GPIO_PinSource13 ((uint8_t)0x0D) #define GPIO_PinSource14 ((uint8_t)0x0E) #define GPIO_PinSource15 ((uint8_t)0x0F) #define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ ((PINSOURCE) == GPIO_PinSource1) || \ ((PINSOURCE) == GPIO_PinSource2) || \ ((PINSOURCE) == GPIO_PinSource3) || \ ((PINSOURCE) == GPIO_PinSource4) || \ ((PINSOURCE) == GPIO_PinSource5) || \ ((PINSOURCE) == GPIO_PinSource6) || \ ((PINSOURCE) == GPIO_PinSource7) || \ ((PINSOURCE) == GPIO_PinSource8) || \ ((PINSOURCE) == GPIO_PinSource9) || \ ((PINSOURCE) == GPIO_PinSource10) || \ ((PINSOURCE) == GPIO_PinSource11) || \ ((PINSOURCE) == GPIO_PinSource12) || \ ((PINSOURCE) == GPIO_PinSource13) || \ ((PINSOURCE) == GPIO_PinSource14) || \ ((PINSOURCE) == GPIO_PinSource15)) /** * @} */ /** @defgroup GPIO_Alternat_function_selection_define * @{ */ /** * @brief AF 0 selection */ #define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ #define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ #define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ #define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ #define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ /** * @brief AF 1 selection */ #define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ #define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ /** * @brief AF 2 selection */ #define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ #define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ #define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ /** * @brief AF 3 selection */ #define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ #define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ #define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ #define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ /** * @brief AF 4 selection */ #define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ #define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ #define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ /** * @brief AF 5 selection */ #define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ #define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ #define GPIO_AF_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ #define GPIO_AF_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ #define GPIO_AF_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ /** * @brief AF 6 selection */ #define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ #define GPIO_AF_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ /** * @brief AF 7 selection */ #define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ #define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ #define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ #define GPIO_AF_I2S3ext ((uint8_t)0x07) /* I2S3ext Alternate Function mapping */ /** * @brief AF 8 selection */ #define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ #define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ #define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ #define GPIO_AF_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ #define GPIO_AF_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ /** * @brief AF 9 selection */ #define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ #define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ #define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ #define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ #define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ #define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx Devices) */ #define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx Devices) */ /** * @brief AF 10 selection */ #define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */ #define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */ /** * @brief AF 11 selection */ #define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ /** * @brief AF 12 selection */ #if defined (STM32F40_41xxx) #define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */ #endif /* STM32F40_41xxx */ #if defined (STM32F427_437xx) || defined (STM32F429_439xx) #define GPIO_AF_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */ #endif /* STM32F427_437xx || STM32F429_439xx */ #define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ #define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ /** * @brief AF 13 selection */ #define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ /** * @brief AF 14 selection */ #define GPIO_AF_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ /** * @brief AF 15 selection */ #define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ #if defined (STM32F40_41xxx) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \ ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \ ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_FSMC)) #endif /* STM32F40_41xxx */ #if defined (STM32F401xx) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_USART6) || \ ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4)) #endif /* STM32F401xx */ #if defined (STM32F427_437xx) || defined (STM32F429_439xx) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \ ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \ ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4) || \ ((AF) == GPIO_AF_SPI5) || ((AF) == GPIO_AF_SPI6) || \ ((AF) == GPIO_AF_UART7) || ((AF) == GPIO_AF_UART8) || \ ((AF) == GPIO_AF_FMC) || ((AF) == GPIO_AF_SAI1) || \ ((AF) == GPIO_AF_LTDC)) #endif /* STM32F427_437xx || STM32F429_439xx */ /** * @} */ /** @defgroup GPIO_Legacy * @{ */ #define GPIO_Mode_AIN GPIO_Mode_AN #define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS #define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS #define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the GPIO configuration to the default reset state ****/ void GPIO_DeInit(GPIO_TypeDef* GPIOx); /* Initialization and Configuration functions *********************************/ void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); /* GPIO Read and Write functions **********************************************/ uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); /* GPIO Alternate functions configuration function ****************************/ void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_GPIO_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h ================================================ /** ****************************************************************************** * @file stm32f4xx_hash.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the HASH * firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_HASH_H #define __STM32F4xx_HASH_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup HASH * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief HASH Init structure definition */ typedef struct { uint32_t HASH_AlgoSelection; /*!< SHA-1, SHA-224, SHA-256 or MD5. This parameter can be a value of @ref HASH_Algo_Selection */ uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value of @ref HASH_processor_Algorithm_Mode */ uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or bit string. This parameter can be a value of @ref HASH_Data_Type */ uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */ }HASH_InitTypeDef; /** * @brief HASH message digest result structure definition */ typedef struct { uint32_t Data[8]; /*!< Message digest result : 8x 32bit wors for SHA-256, 7x 32bit wors for SHA-224, 5x 32bit words for SHA-1 or 4x 32bit words for MD5 */ } HASH_MsgDigest; /** * @brief HASH context swapping structure definition */ typedef struct { uint32_t HASH_IMR; uint32_t HASH_STR; uint32_t HASH_CR; uint32_t HASH_CSR[54]; }HASH_Context; /* Exported constants --------------------------------------------------------*/ /** @defgroup HASH_Exported_Constants * @{ */ /** @defgroup HASH_Algo_Selection * @{ */ #define HASH_AlgoSelection_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */ #define HASH_AlgoSelection_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */ #define HASH_AlgoSelection_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */ #define HASH_AlgoSelection_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */ #define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \ ((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \ ((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \ ((ALGOSELECTION) == HASH_AlgoSelection_MD5)) /** * @} */ /** @defgroup HASH_processor_Algorithm_Mode * @{ */ #define HASH_AlgoMode_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */ #define HASH_AlgoMode_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */ #define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \ ((ALGOMODE) == HASH_AlgoMode_HMAC)) /** * @} */ /** @defgroup HASH_Data_Type * @{ */ #define HASH_DataType_32b ((uint32_t)0x0000) /*!< 32-bit data. No swapping */ #define HASH_DataType_16b HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */ #define HASH_DataType_8b HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */ #define HASH_DataType_1b HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */ #define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \ ((DATATYPE) == HASH_DataType_16b)|| \ ((DATATYPE) == HASH_DataType_8b) || \ ((DATATYPE) == HASH_DataType_1b)) /** * @} */ /** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode * @{ */ #define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */ #define HASH_HMACKeyType_LongKey HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */ #define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \ ((KEYTYPE) == HASH_HMACKeyType_LongKey)) /** * @} */ /** @defgroup Number_of_valid_bits_in_last_word_of_the_message * @{ */ #define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F) /** * @} */ /** @defgroup HASH_interrupts_definition * @{ */ #define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */ #define HASH_IT_DCI HASH_IMR_DCIM /*!< Digest calculation complete */ #define IS_HASH_IT(IT) ((((IT) & (uint32_t)0xFFFFFFFC) == 0x00000000) && ((IT) != 0x00000000)) #define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI)) /** * @} */ /** @defgroup HASH_flags_definition * @{ */ #define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */ #define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */ #define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ #define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */ #define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */ #define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \ ((FLAG) == HASH_FLAG_DCIS) || \ ((FLAG) == HASH_FLAG_DMAS) || \ ((FLAG) == HASH_FLAG_BUSY) || \ ((FLAG) == HASH_FLAG_DINNE)) #define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \ ((FLAG) == HASH_FLAG_DCIS)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the HASH configuration to the default reset state ****/ void HASH_DeInit(void); /* HASH Configuration function ************************************************/ void HASH_Init(HASH_InitTypeDef* HASH_InitStruct); void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct); void HASH_Reset(void); /* HASH Message Digest generation functions ***********************************/ void HASH_DataIn(uint32_t Data); uint8_t HASH_GetInFIFOWordsNbr(void); void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber); void HASH_StartDigest(void); void HASH_AutoStartDigest(FunctionalState NewState); void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest); /* HASH Context swapping functions ********************************************/ void HASH_SaveContext(HASH_Context* HASH_ContextSave); void HASH_RestoreContext(HASH_Context* HASH_ContextRestore); /* HASH DMA interface function ************************************************/ void HASH_DMACmd(FunctionalState NewState); /* HASH Interrupts and flags management functions *****************************/ void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState); FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG); void HASH_ClearFlag(uint32_t HASH_FLAG); ITStatus HASH_GetITStatus(uint32_t HASH_IT); void HASH_ClearITPendingBit(uint32_t HASH_IT); /* High Level SHA1 functions **************************************************/ ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]); ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, uint8_t *Input, uint32_t Ilen, uint8_t Output[20]); /* High Level MD5 functions ***************************************************/ ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]); ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, uint8_t *Input, uint32_t Ilen, uint8_t Output[16]); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_HASH_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h ================================================ /** ****************************************************************************** * @file stm32f4xx_i2c.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the I2C firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_I2C_H #define __STM32F4xx_I2C_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup I2C * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief I2C Init structure definition */ typedef struct { uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. This parameter must be set to a value lower than 400kHz */ uint16_t I2C_Mode; /*!< Specifies the I2C mode. This parameter can be a value of @ref I2C_mode */ uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. This parameter can be a 7-bit or 10-bit address. */ uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. This parameter can be a value of @ref I2C_acknowledgement */ uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. This parameter can be a value of @ref I2C_acknowledged_address */ }I2C_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup I2C_Exported_Constants * @{ */ #define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ ((PERIPH) == I2C2) || \ ((PERIPH) == I2C3)) /** @defgroup I2C_Digital_Filter * @{ */ #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) /** * @} */ /** @defgroup I2C_mode * @{ */ #define I2C_Mode_I2C ((uint16_t)0x0000) #define I2C_Mode_SMBusDevice ((uint16_t)0x0002) #define I2C_Mode_SMBusHost ((uint16_t)0x000A) #define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ ((MODE) == I2C_Mode_SMBusDevice) || \ ((MODE) == I2C_Mode_SMBusHost)) /** * @} */ /** @defgroup I2C_duty_cycle_in_fast_mode * @{ */ #define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ #define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ ((CYCLE) == I2C_DutyCycle_2)) /** * @} */ /** @defgroup I2C_acknowledgement * @{ */ #define I2C_Ack_Enable ((uint16_t)0x0400) #define I2C_Ack_Disable ((uint16_t)0x0000) #define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ ((STATE) == I2C_Ack_Disable)) /** * @} */ /** @defgroup I2C_transfer_direction * @{ */ #define I2C_Direction_Transmitter ((uint8_t)0x00) #define I2C_Direction_Receiver ((uint8_t)0x01) #define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ ((DIRECTION) == I2C_Direction_Receiver)) /** * @} */ /** @defgroup I2C_acknowledged_address * @{ */ #define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) #define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) #define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) /** * @} */ /** @defgroup I2C_registers * @{ */ #define I2C_Register_CR1 ((uint8_t)0x00) #define I2C_Register_CR2 ((uint8_t)0x04) #define I2C_Register_OAR1 ((uint8_t)0x08) #define I2C_Register_OAR2 ((uint8_t)0x0C) #define I2C_Register_DR ((uint8_t)0x10) #define I2C_Register_SR1 ((uint8_t)0x14) #define I2C_Register_SR2 ((uint8_t)0x18) #define I2C_Register_CCR ((uint8_t)0x1C) #define I2C_Register_TRISE ((uint8_t)0x20) #define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ ((REGISTER) == I2C_Register_CR2) || \ ((REGISTER) == I2C_Register_OAR1) || \ ((REGISTER) == I2C_Register_OAR2) || \ ((REGISTER) == I2C_Register_DR) || \ ((REGISTER) == I2C_Register_SR1) || \ ((REGISTER) == I2C_Register_SR2) || \ ((REGISTER) == I2C_Register_CCR) || \ ((REGISTER) == I2C_Register_TRISE)) /** * @} */ /** @defgroup I2C_NACK_position * @{ */ #define I2C_NACKPosition_Next ((uint16_t)0x0800) #define I2C_NACKPosition_Current ((uint16_t)0xF7FF) #define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ ((POSITION) == I2C_NACKPosition_Current)) /** * @} */ /** @defgroup I2C_SMBus_alert_pin_level * @{ */ #define I2C_SMBusAlert_Low ((uint16_t)0x2000) #define I2C_SMBusAlert_High ((uint16_t)0xDFFF) #define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ ((ALERT) == I2C_SMBusAlert_High)) /** * @} */ /** @defgroup I2C_PEC_position * @{ */ #define I2C_PECPosition_Next ((uint16_t)0x0800) #define I2C_PECPosition_Current ((uint16_t)0xF7FF) #define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ ((POSITION) == I2C_PECPosition_Current)) /** * @} */ /** @defgroup I2C_interrupts_definition * @{ */ #define I2C_IT_BUF ((uint16_t)0x0400) #define I2C_IT_EVT ((uint16_t)0x0200) #define I2C_IT_ERR ((uint16_t)0x0100) #define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) /** * @} */ /** @defgroup I2C_interrupts_definition * @{ */ #define I2C_IT_SMBALERT ((uint32_t)0x01008000) #define I2C_IT_TIMEOUT ((uint32_t)0x01004000) #define I2C_IT_PECERR ((uint32_t)0x01001000) #define I2C_IT_OVR ((uint32_t)0x01000800) #define I2C_IT_AF ((uint32_t)0x01000400) #define I2C_IT_ARLO ((uint32_t)0x01000200) #define I2C_IT_BERR ((uint32_t)0x01000100) #define I2C_IT_TXE ((uint32_t)0x06000080) #define I2C_IT_RXNE ((uint32_t)0x06000040) #define I2C_IT_STOPF ((uint32_t)0x02000010) #define I2C_IT_ADD10 ((uint32_t)0x02000008) #define I2C_IT_BTF ((uint32_t)0x02000004) #define I2C_IT_ADDR ((uint32_t)0x02000002) #define I2C_IT_SB ((uint32_t)0x02000001) #define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) #define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) /** * @} */ /** @defgroup I2C_flags_definition * @{ */ /** * @brief SR2 register flags */ #define I2C_FLAG_DUALF ((uint32_t)0x00800000) #define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) #define I2C_FLAG_GENCALL ((uint32_t)0x00100000) #define I2C_FLAG_TRA ((uint32_t)0x00040000) #define I2C_FLAG_BUSY ((uint32_t)0x00020000) #define I2C_FLAG_MSL ((uint32_t)0x00010000) /** * @brief SR1 register flags */ #define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) #define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) #define I2C_FLAG_PECERR ((uint32_t)0x10001000) #define I2C_FLAG_OVR ((uint32_t)0x10000800) #define I2C_FLAG_AF ((uint32_t)0x10000400) #define I2C_FLAG_ARLO ((uint32_t)0x10000200) #define I2C_FLAG_BERR ((uint32_t)0x10000100) #define I2C_FLAG_TXE ((uint32_t)0x10000080) #define I2C_FLAG_RXNE ((uint32_t)0x10000040) #define I2C_FLAG_STOPF ((uint32_t)0x10000010) #define I2C_FLAG_ADD10 ((uint32_t)0x10000008) #define I2C_FLAG_BTF ((uint32_t)0x10000004) #define I2C_FLAG_ADDR ((uint32_t)0x10000002) #define I2C_FLAG_SB ((uint32_t)0x10000001) #define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) #define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ ((FLAG) == I2C_FLAG_SB)) /** * @} */ /** @defgroup I2C_Events * @{ */ /** =============================================================================== I2C Master Events (Events grouped in order of communication) =============================================================================== */ /** * @brief Communication start * * After sending the START condition (I2C_GenerateSTART() function) the master * has to wait for this event. It means that the Start condition has been correctly * released on the I2C bus (the bus is free, no other devices is communicating). * */ /* --EV5 */ #define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ /** * @brief Address Acknowledge * * After checking on EV5 (start condition correctly released on the bus), the * master sends the address of the slave(s) with which it will communicate * (I2C_Send7bitAddress() function, it also determines the direction of the communication: * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges * his address. If an acknowledge is sent on the bus, one of the following events will * be set: * * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED * event is set. * * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED * is set * * 3) In case of 10-Bit addressing mode, the master (just after generating the START * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() * function). Then master should wait on EV9. It means that the 10-bit addressing * header has been correctly sent on the bus. Then master should send the second part of * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master * should wait for event EV6. * */ /* --EV6 */ #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ /* --EV9 */ #define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ /** * @brief Communication events * * If a communication is established (START condition generated and slave address * acknowledged) then the master has to check on one of the following events for * communication procedures: * * 1) Master Receiver mode: The master has to wait on the event EV7 then to read * the data received from the slave (I2C_ReceiveData() function). * * 2) Master Transmitter mode: The master has to send data (I2C_SendData() * function) then to wait on event EV8 or EV8_2. * These two events are similar: * - EV8 means that the data has been written in the data register and is * being shifted out. * - EV8_2 means that the data has been physically shifted out and output * on the bus. * In most cases, using EV8 is sufficient for the application. * Using EV8_2 leads to a slower communication but ensure more reliable test. * EV8_2 is also more suitable than EV8 for testing on the last data transmission * (before Stop condition generation). * * @note In case the user software does not guarantee that this event EV7 is * managed before the current byte end of transfer, then user may check on EV7 * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). * In this case the communication may be slower. * */ /* Master RECEIVER mode -----------------------------*/ /* --EV7 */ #define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ /* Master TRANSMITTER mode --------------------------*/ /* --EV8 */ #define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ /* --EV8_2 */ #define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ /** =============================================================================== I2C Slave Events (Events grouped in order of communication) =============================================================================== */ /** * @brief Communication start events * * Wait on one of these events at the start of the communication. It means that * the I2C peripheral detected a Start condition on the bus (generated by master * device) followed by the peripheral address. The peripheral generates an ACK * condition on the bus (if the acknowledge feature is enabled through function * I2C_AcknowledgeConfig()) and the events listed above are set : * * 1) In normal case (only one address managed by the slave), when the address * sent by the master matches the own address of the peripheral (configured by * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set * (where XXX could be TRANSMITTER or RECEIVER). * * 2) In case the address sent by the master matches the second address of the * peripheral (configured by the function I2C_OwnAddress2Config() and enabled * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED * (where XXX could be TRANSMITTER or RECEIVER) are set. * * 3) In case the address sent by the master is General Call (address 0x00) and * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. * */ /* --EV1 (all the events below are variants of EV1) */ /* 1) Case of One Single Address managed by the slave */ #define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ #define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ /* 2) Case of Dual address managed by the slave */ #define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ #define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ /* 3) Case of General Call enabled for the slave */ #define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ /** * @brief Communication events * * Wait on one of these events when EV1 has already been checked and: * * - Slave RECEIVER mode: * - EV2: When the application is expecting a data byte to be received. * - EV4: When the application is expecting the end of the communication: master * sends a stop condition and data transmission is stopped. * * - Slave Transmitter mode: * - EV3: When a byte has been transmitted by the slave and the application is expecting * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be * used when the user software doesn't guarantee the EV3 is managed before the * current byte end of transfer. * - EV3_2: When the master sends a NACK in order to tell slave that data transmission * shall end (before sending the STOP condition). In this case slave has to stop sending * data bytes and expect a Stop condition on the bus. * * @note In case the user software does not guarantee that the event EV2 is * managed before the current byte end of transfer, then user may check on EV2 * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). * In this case the communication may be slower. * */ /* Slave RECEIVER mode --------------------------*/ /* --EV2 */ #define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ /* --EV4 */ #define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ /* Slave TRANSMITTER mode -----------------------*/ /* --EV3 */ #define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ #define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ /* --EV3_2 */ #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ /* =============================================================================== End of Events Description =============================================================================== */ #define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) /** * @} */ /** @defgroup I2C_own_address1 * @{ */ #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) /** * @} */ /** @defgroup I2C_clock_speed * @{ */ #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the I2C configuration to the default reset state *****/ void I2C_DeInit(I2C_TypeDef* I2Cx); /* Initialization and Configuration functions *********************************/ void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter); void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); /* Data transfers functions ***************************************************/ void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); /* PEC management functions ***************************************************/ void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); /* DMA transfers management functions *****************************************/ void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); /* Interrupts, events and flags management functions **************************/ uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); /* =============================================================================== I2C State Monitoring Functions =============================================================================== This I2C driver provides three different ways for I2C state monitoring depending on the application requirements and constraints: 1. Basic state monitoring (Using I2C_CheckEvent() function) ----------------------------------------------------------- It compares the status registers (SR1 and SR2) content to a given event (can be the combination of one or more flags). It returns SUCCESS if the current status includes the given flags and returns ERROR if one or more flags are missing in the current status. - When to use - This function is suitable for most applications as well as for startup activity since the events are fully described in the product reference manual (RM0090). - It is also suitable for users who need to define their own events. - Limitations - If an error occurs (ie. error flags are set besides to the monitored flags), the I2C_CheckEvent() function may return SUCCESS despite the communication hold or corrupted real state. In this case, it is advised to use error interrupts to monitor the error events and handle them in the interrupt IRQ handler. Note For error management, it is advised to use the following functions: - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. Where x is the peripheral instance (I2C1, I2C2 ...) - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the I2Cx_ER_IRQHandler() function in order to determine which error occurred. - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() and/or I2C_GenerateStop() in order to clear the error flag and source and return to correct communication status. 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) -------------------------------------------------------------------- Using the function I2C_GetLastEvent() which returns the image of both status registers in a single word (uint32_t) (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). - When to use - This function is suitable for the same applications above but it allows to overcome the mentioned limitation of I2C_GetFlagStatus() function. - The returned value could be compared to events already defined in this file or to custom values defined by user. This function is suitable when multiple flags are monitored at the same time. - At the opposite of I2C_CheckEvent() function, this function allows user to choose when an event is accepted (when all events flags are set and no other flags are set or just when the needed flags are set like I2C_CheckEvent() function. - Limitations - User may need to define his own events. - Same remark concerning the error management is applicable for this function if user decides to check only regular communication flags (and ignores error flags). 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) ----------------------------------------------------------------------- Using the function I2C_GetFlagStatus() which simply returns the status of one single flag (ie. I2C_FLAG_RXNE ...). - When to use - This function could be used for specific applications or in debug phase. - It is suitable when only one flag checking is needed (most I2C events are monitored through multiple flags). - Limitations: - When calling this function, the Status register is accessed. Some flags are cleared when the status register is accessed. So checking the status of one Flag, may clear other ones. - Function may need to be called twice or more in order to monitor one single event. */ /* =============================================================================== 1. Basic state monitoring =============================================================================== */ ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); /* =============================================================================== 2. Advanced state monitoring =============================================================================== */ uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); /* =============================================================================== 3. Flag-based state monitoring =============================================================================== */ FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_I2C_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h ================================================ /** ****************************************************************************** * @file stm32f4xx_iwdg.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the IWDG * firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_IWDG_H #define __STM32F4xx_IWDG_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup IWDG * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup IWDG_Exported_Constants * @{ */ /** @defgroup IWDG_WriteAccess * @{ */ #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ ((ACCESS) == IWDG_WriteAccess_Disable)) /** * @} */ /** @defgroup IWDG_prescaler * @{ */ #define IWDG_Prescaler_4 ((uint8_t)0x00) #define IWDG_Prescaler_8 ((uint8_t)0x01) #define IWDG_Prescaler_16 ((uint8_t)0x02) #define IWDG_Prescaler_32 ((uint8_t)0x03) #define IWDG_Prescaler_64 ((uint8_t)0x04) #define IWDG_Prescaler_128 ((uint8_t)0x05) #define IWDG_Prescaler_256 ((uint8_t)0x06) #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ ((PRESCALER) == IWDG_Prescaler_8) || \ ((PRESCALER) == IWDG_Prescaler_16) || \ ((PRESCALER) == IWDG_Prescaler_32) || \ ((PRESCALER) == IWDG_Prescaler_64) || \ ((PRESCALER) == IWDG_Prescaler_128)|| \ ((PRESCALER) == IWDG_Prescaler_256)) /** * @} */ /** @defgroup IWDG_Flag * @{ */ #define IWDG_FLAG_PVU ((uint16_t)0x0001) #define IWDG_FLAG_RVU ((uint16_t)0x0002) #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Prescaler and Counter configuration functions ******************************/ void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); void IWDG_SetReload(uint16_t Reload); void IWDG_ReloadCounter(void); /* IWDG activation function ***************************************************/ void IWDG_Enable(void); /* Flag management function ***************************************************/ FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_IWDG_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h ================================================ /** ****************************************************************************** * @file stm32f4xx_ltdc.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the LTDC firmware * library. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * *

© COPYRIGHT 2013 STMicroelectronics

****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_LTDC_H #define __STM32F4xx_LTDC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup LTDC * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief LTDC Init structure definition */ typedef struct { uint32_t LTDC_HSPolarity; /*!< configures the horizontal synchronization polarity. This parameter can be one value of @ref LTDC_HSPolarity */ uint32_t LTDC_VSPolarity; /*!< configures the vertical synchronization polarity. This parameter can be one value of @ref LTDC_VSPolarity */ uint32_t LTDC_DEPolarity; /*!< configures the data enable polarity. This parameter can be one of value of @ref LTDC_DEPolarity */ uint32_t LTDC_PCPolarity; /*!< configures the pixel clock polarity. This parameter can be one of value of @ref LTDC_PCPolarity */ uint32_t LTDC_HorizontalSync; /*!< configures the number of Horizontal synchronization width. This parameter must range from 0x000 to 0xFFF. */ uint32_t LTDC_VerticalSync; /*!< configures the number of Vertical synchronization heigh. This parameter must range from 0x000 to 0x7FF. */ uint32_t LTDC_AccumulatedHBP; /*!< configures the accumulated horizontal back porch width. This parameter must range from LTDC_HorizontalSync to 0xFFF. */ uint32_t LTDC_AccumulatedVBP; /*!< configures the accumulated vertical back porch heigh. This parameter must range from LTDC_VerticalSync to 0x7FF. */ uint32_t LTDC_AccumulatedActiveW; /*!< configures the accumulated active width. This parameter must range from LTDC_AccumulatedHBP to 0xFFF. */ uint32_t LTDC_AccumulatedActiveH; /*!< configures the accumulated active heigh. This parameter must range from LTDC_AccumulatedVBP to 0x7FF. */ uint32_t LTDC_TotalWidth; /*!< configures the total width. This parameter must range from LTDC_AccumulatedActiveW to 0xFFF. */ uint32_t LTDC_TotalHeigh; /*!< configures the total heigh. This parameter must range from LTDC_AccumulatedActiveH to 0x7FF. */ uint32_t LTDC_BackgroundRedValue; /*!< configures the background red value. This parameter must range from 0x00 to 0xFF. */ uint32_t LTDC_BackgroundGreenValue; /*!< configures the background green value. This parameter must range from 0x00 to 0xFF. */ uint32_t LTDC_BackgroundBlueValue; /*!< configures the background blue value. This parameter must range from 0x00 to 0xFF. */ } LTDC_InitTypeDef; /** * @brief LTDC Layer structure definition */ typedef struct { uint32_t LTDC_HorizontalStart; /*!< Configures the Window Horizontal Start Position. This parameter must range from 0x000 to 0xFFF. */ uint32_t LTDC_HorizontalStop; /*!< Configures the Window Horizontal Stop Position. This parameter must range from 0x0000 to 0xFFFF. */ uint32_t LTDC_VerticalStart; /*!< Configures the Window vertical Start Position. This parameter must range from 0x000 to 0xFFF. */ uint32_t LTDC_VerticalStop; /*!< Configures the Window vaertical Stop Position. This parameter must range from 0x0000 to 0xFFFF. */ uint32_t LTDC_PixelFormat; /*!< Specifies the pixel format. This parameter can be one of value of @ref LTDC_Pixelformat */ uint32_t LTDC_ConstantAlpha; /*!< Specifies the constant alpha used for blending. This parameter must range from 0x00 to 0xFF. */ uint32_t LTDC_DefaultColorBlue; /*!< Configures the default blue value. This parameter must range from 0x00 to 0xFF. */ uint32_t LTDC_DefaultColorGreen; /*!< Configures the default green value. This parameter must range from 0x00 to 0xFF. */ uint32_t LTDC_DefaultColorRed; /*!< Configures the default red value. This parameter must range from 0x00 to 0xFF. */ uint32_t LTDC_DefaultColorAlpha; /*!< Configures the default alpha value. This parameter must range from 0x00 to 0xFF. */ uint32_t LTDC_BlendingFactor_1; /*!< Select the blending factor 1. This parameter can be one of value of @ref LTDC_BlendingFactor1 */ uint32_t LTDC_BlendingFactor_2; /*!< Select the blending factor 2. This parameter can be one of value of @ref LTDC_BlendingFactor2 */ uint32_t LTDC_CFBStartAdress; /*!< Configures the color frame buffer address */ uint32_t LTDC_CFBLineLength; /*!< Configures the color frame buffer line length. This parameter must range from 0x0000 to 0x1FFF. */ uint32_t LTDC_CFBPitch; /*!< Configures the color frame buffer pitch in bytes. This parameter must range from 0x0000 to 0x1FFF. */ uint32_t LTDC_CFBLineNumber; /*!< Specifies the number of line in frame buffer. This parameter must range from 0x000 to 0x7FF. */ } LTDC_Layer_InitTypeDef; /** * @brief LTDC Position structure definition */ typedef struct { uint32_t LTDC_POSX; /*!< Current X Position */ uint32_t LTDC_POSY; /*!< Current Y Position */ } LTDC_PosTypeDef; typedef struct { uint32_t LTDC_BlueWidth; /*!< Blue width */ uint32_t LTDC_GreenWidth; /*!< Green width */ uint32_t LTDC_RedWidth; /*!< Red width */ } LTDC_RGBTypeDef; typedef struct { uint32_t LTDC_ColorKeyBlue; /*!< Configures the color key blue value. This parameter must range from 0x00 to 0xFF. */ uint32_t LTDC_ColorKeyGreen; /*!< Configures the color key green value. This parameter must range from 0x00 to 0xFF. */ uint32_t LTDC_ColorKeyRed; /*!< Configures the color key red value. This parameter must range from 0x00 to 0xFF. */ } LTDC_ColorKeying_InitTypeDef; typedef struct { uint32_t LTDC_CLUTAdress; /*!< Configures the CLUT address. This parameter must range from 0x00 to 0xFF. */ uint32_t LTDC_BlueValue; /*!< Configures the blue value. This parameter must range from 0x00 to 0xFF. */ uint32_t LTDC_GreenValue; /*!< Configures the green value. This parameter must range from 0x00 to 0xFF. */ uint32_t LTDC_RedValue; /*!< Configures the red value. This parameter must range from 0x00 to 0xFF. */ } LTDC_CLUT_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup LTDC_Exported_Constants * @} */ /** @defgroup LTDC_SYNC * @{ */ #define LTDC_HorizontalSYNC ((uint32_t)0x00000FFF) #define LTDC_VerticalSYNC ((uint32_t)0x000007FF) #define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HorizontalSYNC) #define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VerticalSYNC) #define IS_LTDC_AHBP(AHBP) ((AHBP) <= LTDC_HorizontalSYNC) #define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VerticalSYNC) #define IS_LTDC_AAW(AAW) ((AAW) <= LTDC_HorizontalSYNC) #define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VerticalSYNC) #define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HorizontalSYNC) #define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VerticalSYNC) /** * @} */ /** @defgroup LTDC_HSPolarity * @{ */ #define LTDC_HSPolarity_AL ((uint32_t)0x00000000) /*!< Horizontal Synchronization is active low. */ #define LTDC_HSPolarity_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */ #define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPolarity_AL) || \ ((HSPOL) == LTDC_HSPolarity_AH)) /** * @} */ /** @defgroup LTDC_VSPolarity * @{ */ #define LTDC_VSPolarity_AL ((uint32_t)0x00000000) /*!< Vertical Synchronization is active low. */ #define LTDC_VSPolarity_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */ #define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPolarity_AL) || \ ((VSPOL) == LTDC_VSPolarity_AH)) /** * @} */ /** @defgroup LTDC_DEPolarity * @{ */ #define LTDC_DEPolarity_AL ((uint32_t)0x00000000) /*!< Data Enable, is active low. */ #define LTDC_DEPolarity_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */ #define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_VSPolarity_AL) || \ ((DEPOL) == LTDC_DEPolarity_AH)) /** * @} */ /** @defgroup LTDC_PCPolarity * @{ */ #define LTDC_PCPolarity_IPC ((uint32_t)0x00000000) /*!< input pixel clock. */ #define LTDC_PCPolarity_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */ #define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPolarity_IPC) || \ ((PCPOL) == LTDC_PCPolarity_IIPC)) /** * @} */ /** @defgroup LTDC_Reload * @{ */ #define LTDC_IMReload LTDC_SRCR_IMR /*!< Immediately Reload. */ #define LTDC_VBReload LTDC_SRCR_VBR /*!< Vertical Blanking Reload. */ #define IS_LTDC_RELOAD(RELOAD) (((RELOAD) == LTDC_IMReload) || \ ((RELOAD) == LTDC_VBReload)) /** * @} */ /** @defgroup LTDC_Back_Color * @{ */ #define LTDC_Back_Color ((uint32_t)0x000000FF) #define IS_LTDC_BackBlueValue(BBLUE) ((BBLUE) <= LTDC_Back_Color) #define IS_LTDC_BackGreenValue(BGREEN) ((BGREEN) <= LTDC_Back_Color) #define IS_LTDC_BackRedValue(BRED) ((BRED) <= LTDC_Back_Color) /** * @} */ /** @defgroup LTDC_Position * @{ */ #define LTDC_POS_CY LTDC_CPSR_CYPOS #define LTDC_POS_CX LTDC_CPSR_CXPOS #define IS_LTDC_GET_POS(POS) (((POS) <= LTDC_POS_CY)) /** * @} */ /** @defgroup LTDC_LIPosition * @{ */ #define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF) /** * @} */ /** @defgroup LTDC_CurrentStatus * @{ */ #define LTDC_CD_VDES LTDC_CDSR_VDES #define LTDC_CD_HDES LTDC_CDSR_HDES #define LTDC_CD_VSYNC LTDC_CDSR_VSYNCS #define LTDC_CD_HSYNC LTDC_CDSR_HSYNCS #define IS_LTDC_GET_CD(CD) (((CD) == LTDC_CD_VDES) || ((CD) == LTDC_CD_HDES) || \ ((CD) == LTDC_CD_VSYNC) || ((CD) == LTDC_CD_HSYNC)) /** * @} */ /** @defgroup LTDC_Interrupts * @{ */ #define LTDC_IT_LI LTDC_IER_LIE #define LTDC_IT_FU LTDC_IER_FUIE #define LTDC_IT_TERR LTDC_IER_TERRIE #define LTDC_IT_RR LTDC_IER_RRIE #define IS_LTDC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF0) == 0x00) && ((IT) != 0x00)) /** * @} */ /** @defgroup LTDC_Flag * @{ */ #define LTDC_FLAG_LI LTDC_ISR_LIF #define LTDC_FLAG_FU LTDC_ISR_FUIF #define LTDC_FLAG_TERR LTDC_ISR_TERRIF #define LTDC_FLAG_RR LTDC_ISR_RRIF #define IS_LTDC_FLAG(FLAG) (((FLAG) == LTDC_FLAG_LI) || ((FLAG) == LTDC_FLAG_FU) || \ ((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR)) /** * @} */ /** @defgroup LTDC_Pixelformat * @{ */ #define LTDC_Pixelformat_ARGB8888 ((uint32_t)0x00000000) #define LTDC_Pixelformat_RGB888 ((uint32_t)0x00000001) #define LTDC_Pixelformat_RGB565 ((uint32_t)0x00000002) #define LTDC_Pixelformat_ARGB1555 ((uint32_t)0x00000003) #define LTDC_Pixelformat_ARGB4444 ((uint32_t)0x00000004) #define LTDC_Pixelformat_L8 ((uint32_t)0x00000005) #define LTDC_Pixelformat_AL44 ((uint32_t)0x00000006) #define LTDC_Pixelformat_AL88 ((uint32_t)0x00000007) #define IS_LTDC_Pixelformat(Pixelformat) (((Pixelformat) == LTDC_Pixelformat_ARGB8888) || ((Pixelformat) == LTDC_Pixelformat_RGB888) || \ ((Pixelformat) == LTDC_Pixelformat_RGB565) || ((Pixelformat) == LTDC_Pixelformat_ARGB1555) || \ ((Pixelformat) == LTDC_Pixelformat_ARGB4444) || ((Pixelformat) == LTDC_Pixelformat_L8) || \ ((Pixelformat) == LTDC_Pixelformat_AL44) || ((Pixelformat) == LTDC_Pixelformat_AL88)) /** * @} */ /** @defgroup LTDC_BlendingFactor1 * @{ */ #define LTDC_BlendingFactor1_CA ((uint32_t)0x00000400) #define LTDC_BlendingFactor1_PAxCA ((uint32_t)0x00000600) #define IS_LTDC_BlendingFactor1(BlendingFactor1) (((BlendingFactor1) == LTDC_BlendingFactor1_CA) || ((BlendingFactor1) == LTDC_BlendingFactor1_PAxCA)) /** * @} */ /** @defgroup LTDC_BlendingFactor2 * @{ */ #define LTDC_BlendingFactor2_CA ((uint32_t)0x00000005) #define LTDC_BlendingFactor2_PAxCA ((uint32_t)0x00000007) #define IS_LTDC_BlendingFactor2(BlendingFactor2) (((BlendingFactor2) == LTDC_BlendingFactor2_CA) || ((BlendingFactor2) == LTDC_BlendingFactor2_PAxCA)) /** * @} */ /** @defgroup LTDC_LAYER_Config * @{ */ #define LTDC_STOPPosition ((uint32_t)0x0000FFFF) #define LTDC_STARTPosition ((uint32_t)0x00000FFF) #define LTDC_DefaultColorConfig ((uint32_t)0x000000FF) #define LTDC_ColorFrameBuffer ((uint32_t)0x00001FFF) #define LTDC_LineNumber ((uint32_t)0x000007FF) #define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPosition) #define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPosition) #define IS_LTDC_VCONFIGST(VCONFIGST) ((VCONFIGST) <= LTDC_STARTPosition) #define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPosition) #define IS_LTDC_DEFAULTCOLOR(DEFAULTCOLOR) ((DEFAULTCOLOR) <= LTDC_DefaultColorConfig) #define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_ColorFrameBuffer) #define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_ColorFrameBuffer) #define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LineNumber) /** * @} */ /** @defgroup LTDC_colorkeying_Config * @{ */ #define LTDC_colorkeyingConfig ((uint32_t)0x000000FF) #define IS_LTDC_CKEYING(CKEYING) ((CKEYING) <= LTDC_colorkeyingConfig) /** * @} */ /** @defgroup LTDC_CLUT_Config * @{ */ #define LTDC_CLUTWR ((uint32_t)0x000000FF) #define IS_LTDC_CLUTWR(CLUTWR) ((CLUTWR) <= LTDC_CLUTWR) /* Exported macro ------------------------------------------------------------*/ /* Exported functions ------------------------------------------------------- */ /* Function used to set the LTDC configuration to the default reset state *****/ void LTDC_DeInit(void); /* Initialization and Configuration functions *********************************/ void LTDC_Init(LTDC_InitTypeDef* LTDC_InitStruct); void LTDC_StructInit(LTDC_InitTypeDef* LTDC_InitStruct); void LTDC_Cmd(FunctionalState NewState); void LTDC_DitherCmd(FunctionalState NewState); LTDC_RGBTypeDef LTDC_GetRGBWidth(void); void LTDC_RGBStructInit(LTDC_RGBTypeDef* LTDC_RGB_InitStruct); void LTDC_LIPConfig(uint32_t LTDC_LIPositionConfig); void LTDC_ReloadConfig(uint32_t LTDC_Reload); void LTDC_LayerInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_Layer_InitTypeDef* LTDC_Layer_InitStruct); void LTDC_LayerStructInit(LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct); void LTDC_LayerCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState); LTDC_PosTypeDef LTDC_GetPosStatus(void); void LTDC_PosStructInit(LTDC_PosTypeDef* LTDC_Pos_InitStruct); FlagStatus LTDC_GetCDStatus(uint32_t LTDC_CD); void LTDC_ColorKeyingConfig(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct, FunctionalState NewState); void LTDC_ColorKeyingStructInit(LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct); void LTDC_CLUTCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState); void LTDC_CLUTInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct); void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct); void LTDC_LayerPosition(LTDC_Layer_TypeDef* LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY); void LTDC_LayerAlpha(LTDC_Layer_TypeDef* LTDC_Layerx, uint8_t ConstantAlpha); void LTDC_LayerAddress(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Address); void LTDC_LayerSize(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Width, uint32_t Height); void LTDC_LayerPixelFormat(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t PixelFormat); /* Interrupts and flags management functions **********************************/ void LTDC_ITConfig(uint32_t LTDC_IT, FunctionalState NewState); FlagStatus LTDC_GetFlagStatus(uint32_t LTDC_FLAG); void LTDC_ClearFlag(uint32_t LTDC_FLAG); ITStatus LTDC_GetITStatus(uint32_t LTDC_IT); void LTDC_ClearITPendingBit(uint32_t LTDC_IT); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_LTDC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h ================================================ /** ****************************************************************************** * @file stm32f4xx_pwr.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the PWR firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_PWR_H #define __STM32F4xx_PWR_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup PWR * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup PWR_Exported_Constants * @{ */ /** @defgroup PWR_PVD_detection_level * @{ */ #define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 #define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 #define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 #define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 #define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 #define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 #define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 #define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) /** * @} */ /** @defgroup PWR_Regulator_state_in_STOP_mode * @{ */ #define PWR_MainRegulator_ON ((uint32_t)0x00000000) #define PWR_LowPowerRegulator_ON PWR_CR_LPDS /* --- PWR_Legacy ---*/ #define PWR_Regulator_ON PWR_MainRegulator_ON #define PWR_Regulator_LowPower PWR_LowPowerRegulator_ON #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) || \ ((REGULATOR) == PWR_LowPowerRegulator_ON)) /** * @} */ /** @defgroup PWR_Regulator_state_in_UnderDrive_mode * @{ */ #define PWR_MainRegulator_UnderDrive_ON PWR_CR_MRUDS #define PWR_LowPowerRegulator_UnderDrive_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS)) #define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || \ ((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON)) /** * @} */ /** @defgroup PWR_STOP_mode_entry * @{ */ #define PWR_STOPEntry_WFI ((uint8_t)0x01) #define PWR_STOPEntry_WFE ((uint8_t)0x02) #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) /** * @} */ /** @defgroup PWR_Regulator_Voltage_Scale * @{ */ #define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x0000C000) #define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00008000) #define PWR_Regulator_Voltage_Scale3 ((uint32_t)0x00004000) #define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || \ ((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || \ ((VOLTAGE) == PWR_Regulator_Voltage_Scale3)) /** * @} */ /** @defgroup PWR_Flag * @{ */ #define PWR_FLAG_WU PWR_CSR_WUF #define PWR_FLAG_SB PWR_CSR_SBF #define PWR_FLAG_PVDO PWR_CSR_PVDO #define PWR_FLAG_BRR PWR_CSR_BRR #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY #define PWR_FLAG_ODRDY PWR_CSR_ODRDY #define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY #define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY /* --- FLAG Legacy ---*/ #define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \ ((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || \ ((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY)) #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ ((FLAG) == PWR_FLAG_UDRDY)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the PWR configuration to the default reset state ******/ void PWR_DeInit(void); /* Backup Domain Access function **********************************************/ void PWR_BackupAccessCmd(FunctionalState NewState); /* PVD configuration functions ************************************************/ void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); void PWR_PVDCmd(FunctionalState NewState); /* WakeUp pins configuration functions ****************************************/ void PWR_WakeUpPinCmd(FunctionalState NewState); /* Main and Backup Regulators configuration functions *************************/ void PWR_BackupRegulatorCmd(FunctionalState NewState); void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage); void PWR_OverDriveCmd(FunctionalState NewState); void PWR_OverDriveSWCmd(FunctionalState NewState); void PWR_UnderDriveCmd(FunctionalState NewState); /* FLASH Power Down configuration functions ***********************************/ void PWR_FlashPowerDownCmd(FunctionalState NewState); /* Low Power modes configuration functions ************************************/ void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); void PWR_EnterSTANDBYMode(void); /* Flags management functions *************************************************/ FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); void PWR_ClearFlag(uint32_t PWR_FLAG); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_PWR_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h ================================================ /** ****************************************************************************** * @file stm32f4xx_rcc.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the RCC firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_RCC_H #define __STM32F4xx_RCC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup RCC * @{ */ /* Exported types ------------------------------------------------------------*/ typedef struct { uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ }RCC_ClocksTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup RCC_Exported_Constants * @{ */ /** @defgroup RCC_HSE_configuration * @{ */ #define RCC_HSE_OFF ((uint8_t)0x00) #define RCC_HSE_ON ((uint8_t)0x01) #define RCC_HSE_Bypass ((uint8_t)0x05) #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ ((HSE) == RCC_HSE_Bypass)) /** * @} */ /** @defgroup RCC_PLL_Clock_Source * @{ */ #define RCC_PLLSource_HSI ((uint32_t)0x00000000) #define RCC_PLLSource_HSE ((uint32_t)0x00400000) #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ ((SOURCE) == RCC_PLLSource_HSE)) #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) #define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) #define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000) #define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000) #define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000) #define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000) #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\ ((VALUE) == RCC_PLLSAIDivR_Div4) ||\ ((VALUE) == RCC_PLLSAIDivR_Div8) ||\ ((VALUE) == RCC_PLLSAIDivR_Div16)) /** * @} */ /** @defgroup RCC_System_Clock_Source * @{ */ #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ ((SOURCE) == RCC_SYSCLKSource_HSE) || \ ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) /** * @} */ /** @defgroup RCC_AHB_Clock_Source * @{ */ #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ ((HCLK) == RCC_SYSCLK_Div512)) /** * @} */ /** @defgroup RCC_APB1_APB2_Clock_Source * @{ */ #define RCC_HCLK_Div1 ((uint32_t)0x00000000) #define RCC_HCLK_Div2 ((uint32_t)0x00001000) #define RCC_HCLK_Div4 ((uint32_t)0x00001400) #define RCC_HCLK_Div8 ((uint32_t)0x00001800) #define RCC_HCLK_Div16 ((uint32_t)0x00001C00) #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ ((PCLK) == RCC_HCLK_Div16)) /** * @} */ /** @defgroup RCC_Interrupt_Source * @{ */ #define RCC_IT_LSIRDY ((uint8_t)0x01) #define RCC_IT_LSERDY ((uint8_t)0x02) #define RCC_IT_HSIRDY ((uint8_t)0x04) #define RCC_IT_HSERDY ((uint8_t)0x08) #define RCC_IT_PLLRDY ((uint8_t)0x10) #define RCC_IT_PLLI2SRDY ((uint8_t)0x20) #define RCC_IT_PLLSAIRDY ((uint8_t)0x40) #define RCC_IT_CSS ((uint8_t)0x80) #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY)) #define IS_RCC_CLEAR_IT(IT)((IT) != 0x00) /** * @} */ /** @defgroup RCC_LSE_Configuration * @{ */ #define RCC_LSE_OFF ((uint8_t)0x00) #define RCC_LSE_ON ((uint8_t)0x01) #define RCC_LSE_Bypass ((uint8_t)0x04) #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ ((LSE) == RCC_LSE_Bypass)) /** * @} */ /** @defgroup RCC_RTC_Clock_Source * @{ */ #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) #define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) #define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) #define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) #define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) #define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) #define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) #define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) #define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) #define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) #define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) #define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) #define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) #define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) #define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) #define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) #define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) #define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) #define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) #define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ ((SOURCE) == RCC_RTCCLKSource_LSI) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) /** * @} */ /** @defgroup RCC_I2S_Clock_Source * @{ */ #define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) /** * @} */ /** @defgroup RCC_SAI_BlockA_Clock_Source * @{ */ #define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000) #define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000) #define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000) #define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\ ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\ ((SOURCE) == RCC_SAIACLKSource_Ext)) /** * @} */ /** @defgroup RCC_SAI_BlockB_Clock_Source * @{ */ #define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000) #define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000) #define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000) #define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\ ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\ ((SOURCE) == RCC_SAIBCLKSource_Ext)) /** * @} */ /** @defgroup RCC_TIM_PRescaler_Selection * @{ */ #define RCC_TIMPrescDesactivated ((uint8_t)0x00) #define RCC_TIMPrescActivated ((uint8_t)0x01) #define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated)) /** * @} */ /** @defgroup RCC_AHB1_Peripherals * @{ */ #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) #define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200) #define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400) #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) #define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000) #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000) #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) #define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000) #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x810BE800) == 0x00) && ((PERIPH) != 0x00)) #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD1FE800) == 0x00) && ((PERIPH) != 0x00)) #define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81106800) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup RCC_AHB2_Peripherals * @{ */ #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) #define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) #define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) #define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) #define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) #define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup RCC_AHB3_Peripherals * @{ */ #if defined (STM32F40_41xxx) #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) #endif /* STM32F40_41xxx */ #if defined (STM32F427_437xx) || defined (STM32F429_439xx) #define RCC_AHB3Periph_FMC ((uint32_t)0x00000001) #endif /* STM32F427_437xx || STM32F429_439xx */ #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup RCC_APB1_Peripherals * @{ */ #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) #define RCC_APB1Periph_UART7 ((uint32_t)0x40000000) #define RCC_APB1Periph_UART8 ((uint32_t)0x80000000) #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x09013600) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup RCC_APB2_Peripherals * @{ */ #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) #define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) #define RCC_APB2Periph_ADC ((uint32_t)0x00000100) #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) #define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000) #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) #define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000) #define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000) #define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000) #define RCC_APB2Periph_LTDC ((uint32_t)0x04000000) #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFB8880CC) == 0x00) && ((PERIPH) != 0x00)) #define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFB8886CC) == 0x00) && ((PERIPH) != 0x00)) /** * @} */ /** @defgroup RCC_MCO1_Clock_Source_Prescaler * @{ */ #define RCC_MCO1Source_HSI ((uint32_t)0x00000000) #define RCC_MCO1Source_LSE ((uint32_t)0x00200000) #define RCC_MCO1Source_HSE ((uint32_t)0x00400000) #define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) #define RCC_MCO1Div_1 ((uint32_t)0x00000000) #define RCC_MCO1Div_2 ((uint32_t)0x04000000) #define RCC_MCO1Div_3 ((uint32_t)0x05000000) #define RCC_MCO1Div_4 ((uint32_t)0x06000000) #define RCC_MCO1Div_5 ((uint32_t)0x07000000) #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ ((DIV) == RCC_MCO1Div_5)) /** * @} */ /** @defgroup RCC_MCO2_Clock_Source_Prescaler * @{ */ #define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) #define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) #define RCC_MCO2Source_HSE ((uint32_t)0x80000000) #define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) #define RCC_MCO2Div_1 ((uint32_t)0x00000000) #define RCC_MCO2Div_2 ((uint32_t)0x20000000) #define RCC_MCO2Div_3 ((uint32_t)0x28000000) #define RCC_MCO2Div_4 ((uint32_t)0x30000000) #define RCC_MCO2Div_5 ((uint32_t)0x38000000) #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ ((DIV) == RCC_MCO2Div_5)) /** * @} */ /** @defgroup RCC_Flag * @{ */ #define RCC_FLAG_HSIRDY ((uint8_t)0x21) #define RCC_FLAG_HSERDY ((uint8_t)0x31) #define RCC_FLAG_PLLRDY ((uint8_t)0x39) #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D) #define RCC_FLAG_LSERDY ((uint8_t)0x41) #define RCC_FLAG_LSIRDY ((uint8_t)0x61) #define RCC_FLAG_BORRST ((uint8_t)0x79) #define RCC_FLAG_PINRST ((uint8_t)0x7A) #define RCC_FLAG_PORRST ((uint8_t)0x7B) #define RCC_FLAG_SFTRST ((uint8_t)0x7C) #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \ ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY)) #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the RCC clock configuration to the default reset state */ void RCC_DeInit(void); /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ void RCC_HSEConfig(uint8_t RCC_HSE); ErrorStatus RCC_WaitForHSEStartUp(void); void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); void RCC_HSICmd(FunctionalState NewState); void RCC_LSEConfig(uint8_t RCC_LSE); void RCC_LSICmd(FunctionalState NewState); void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); void RCC_PLLCmd(FunctionalState NewState); #if defined (STM32F40_41xxx) || defined (STM32F401xx) void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); #endif /* STM32F40_41xxx || STM32F401xx */ #if defined (STM32F427_437xx) || defined (STM32F429_439xx) void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR); #endif /* STM32F41_43xxx */ void RCC_PLLI2SCmd(FunctionalState NewState); void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR); void RCC_PLLSAICmd(FunctionalState NewState); void RCC_ClockSecuritySystemCmd(FunctionalState NewState); void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); /* System, AHB and APB busses clocks configuration functions ******************/ void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); uint8_t RCC_GetSYSCLKSource(void); void RCC_HCLKConfig(uint32_t RCC_SYSCLK); void RCC_PCLK1Config(uint32_t RCC_HCLK); void RCC_PCLK2Config(uint32_t RCC_HCLK); void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); /* Peripheral clocks configuration functions **********************************/ void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); void RCC_RTCCLKCmd(FunctionalState NewState); void RCC_BackupResetCmd(FunctionalState NewState); void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ); void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ); void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource); void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource); void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR); void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler); void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); void RCC_ClearFlag(void); ITStatus RCC_GetITStatus(uint8_t RCC_IT); void RCC_ClearITPendingBit(uint8_t RCC_IT); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_RCC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h ================================================ /** ****************************************************************************** * @file stm32f4xx_rng.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the Random * Number Generator(RNG) firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_RNG_H #define __STM32F4xx_RNG_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup RNG * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup RNG_Exported_Constants * @{ */ /** @defgroup RNG_flags_definition * @{ */ #define RNG_FLAG_DRDY ((uint8_t)0x0001) /*!< Data ready */ #define RNG_FLAG_CECS ((uint8_t)0x0002) /*!< Clock error current status */ #define RNG_FLAG_SECS ((uint8_t)0x0004) /*!< Seed error current status */ #define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \ ((RNG_FLAG) == RNG_FLAG_CECS) || \ ((RNG_FLAG) == RNG_FLAG_SECS)) #define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \ ((RNG_FLAG) == RNG_FLAG_SECS)) /** * @} */ /** @defgroup RNG_interrupts_definition * @{ */ #define RNG_IT_CEI ((uint8_t)0x20) /*!< Clock error interrupt */ #define RNG_IT_SEI ((uint8_t)0x40) /*!< Seed error interrupt */ #define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00)) #define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the RNG configuration to the default reset state *****/ void RNG_DeInit(void); /* Configuration function *****************************************************/ void RNG_Cmd(FunctionalState NewState); /* Get 32 bit Random number function ******************************************/ uint32_t RNG_GetRandomNumber(void); /* Interrupts and flags management functions **********************************/ void RNG_ITConfig(FunctionalState NewState); FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG); void RNG_ClearFlag(uint8_t RNG_FLAG); ITStatus RNG_GetITStatus(uint8_t RNG_IT); void RNG_ClearITPendingBit(uint8_t RNG_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_RNG_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h ================================================ /** ****************************************************************************** * @file stm32f4xx_rtc.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the RTC firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_RTC_H #define __STM32F4xx_RTC_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup RTC * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief RTC Init structures definition */ typedef struct { uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. This parameter can be a value of @ref RTC_Hour_Formats */ uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. This parameter must be set to a value lower than 0x7F */ uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. This parameter must be set to a value lower than 0x7FFF */ }RTC_InitTypeDef; /** * @brief RTC Time structure definition */ typedef struct { uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. This parameter must be set to a value in the 0-12 range if the RTC_HourFormat_12 is selected or 0-23 range if the RTC_HourFormat_24 is selected. */ uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. This parameter must be set to a value in the 0-59 range. */ uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. This parameter must be set to a value in the 0-59 range. */ uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. This parameter can be a value of @ref RTC_AM_PM_Definitions */ }RTC_TimeTypeDef; /** * @brief RTC Date structure definition */ typedef struct { uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. This parameter can be a value of @ref RTC_WeekDay_Definitions */ uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format). This parameter can be a value of @ref RTC_Month_Date_Definitions */ uint8_t RTC_Date; /*!< Specifies the RTC Date. This parameter must be set to a value in the 1-31 range. */ uint8_t RTC_Year; /*!< Specifies the RTC Date Year. This parameter must be set to a value in the 0-99 range. */ }RTC_DateTypeDef; /** * @brief RTC Alarm structure definition */ typedef struct { RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. This parameter can be a value of @ref RTC_AlarmMask_Definitions */ uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */ }RTC_AlarmTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup RTC_Exported_Constants * @{ */ /** @defgroup RTC_Hour_Formats * @{ */ #define RTC_HourFormat_24 ((uint32_t)0x00000000) #define RTC_HourFormat_12 ((uint32_t)0x00000040) #define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ ((FORMAT) == RTC_HourFormat_24)) /** * @} */ /** @defgroup RTC_Asynchronous_Predivider * @{ */ #define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) /** * @} */ /** @defgroup RTC_Synchronous_Predivider * @{ */ #define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF) /** * @} */ /** @defgroup RTC_Time_Definitions * @{ */ #define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) #define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) #define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) #define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) /** * @} */ /** @defgroup RTC_AM_PM_Definitions * @{ */ #define RTC_H12_AM ((uint8_t)0x00) #define RTC_H12_PM ((uint8_t)0x40) #define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) /** * @} */ /** @defgroup RTC_Year_Date_Definitions * @{ */ #define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) /** * @} */ /** @defgroup RTC_Month_Date_Definitions * @{ */ /* Coded in BCD format */ #define RTC_Month_January ((uint8_t)0x01) #define RTC_Month_February ((uint8_t)0x02) #define RTC_Month_March ((uint8_t)0x03) #define RTC_Month_April ((uint8_t)0x04) #define RTC_Month_May ((uint8_t)0x05) #define RTC_Month_June ((uint8_t)0x06) #define RTC_Month_July ((uint8_t)0x07) #define RTC_Month_August ((uint8_t)0x08) #define RTC_Month_September ((uint8_t)0x09) #define RTC_Month_October ((uint8_t)0x10) #define RTC_Month_November ((uint8_t)0x11) #define RTC_Month_December ((uint8_t)0x12) #define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) #define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) /** * @} */ /** @defgroup RTC_WeekDay_Definitions * @{ */ #define RTC_Weekday_Monday ((uint8_t)0x01) #define RTC_Weekday_Tuesday ((uint8_t)0x02) #define RTC_Weekday_Wednesday ((uint8_t)0x03) #define RTC_Weekday_Thursday ((uint8_t)0x04) #define RTC_Weekday_Friday ((uint8_t)0x05) #define RTC_Weekday_Saturday ((uint8_t)0x06) #define RTC_Weekday_Sunday ((uint8_t)0x07) #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ ((WEEKDAY) == RTC_Weekday_Tuesday) || \ ((WEEKDAY) == RTC_Weekday_Wednesday) || \ ((WEEKDAY) == RTC_Weekday_Thursday) || \ ((WEEKDAY) == RTC_Weekday_Friday) || \ ((WEEKDAY) == RTC_Weekday_Saturday) || \ ((WEEKDAY) == RTC_Weekday_Sunday)) /** * @} */ /** @defgroup RTC_Alarm_Definitions * @{ */ #define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ ((WEEKDAY) == RTC_Weekday_Tuesday) || \ ((WEEKDAY) == RTC_Weekday_Wednesday) || \ ((WEEKDAY) == RTC_Weekday_Thursday) || \ ((WEEKDAY) == RTC_Weekday_Friday) || \ ((WEEKDAY) == RTC_Weekday_Saturday) || \ ((WEEKDAY) == RTC_Weekday_Sunday)) /** * @} */ /** @defgroup RTC_AlarmDateWeekDay_Definitions * @{ */ #define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) #define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) /** * @} */ /** @defgroup RTC_AlarmMask_Definitions * @{ */ #define RTC_AlarmMask_None ((uint32_t)0x00000000) #define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) #define RTC_AlarmMask_Hours ((uint32_t)0x00800000) #define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) #define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) #define RTC_AlarmMask_All ((uint32_t)0x80808080) #define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) /** * @} */ /** @defgroup RTC_Alarms_Definitions * @{ */ #define RTC_Alarm_A ((uint32_t)0x00000100) #define RTC_Alarm_B ((uint32_t)0x00000200) #define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) #define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) /** * @} */ /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions * @{ */ #define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ #define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared. */ #define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm comparison.Only SS[11:0] are compared */ #define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared */ #define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm comparison.Only SS[13:0] are compared */ #define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match to activate alarm. */ #define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \ ((MASK) == RTC_AlarmSubSecondMask_SS14) || \ ((MASK) == RTC_AlarmSubSecondMask_None)) /** * @} */ /** @defgroup RTC_Alarm_Sub_Seconds_Value * @{ */ #define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) /** * @} */ /** @defgroup RTC_Wakeup_Timer_Definitions * @{ */ #define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000) #define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001) #define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002) #define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003) #define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004) #define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006) #define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \ ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \ ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits)) #define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) /** * @} */ /** @defgroup RTC_Time_Stamp_Edges_definitions * @{ */ #define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) #define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) #define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ ((EDGE) == RTC_TimeStampEdge_Falling)) /** * @} */ /** @defgroup RTC_Output_selection_Definitions * @{ */ #define RTC_Output_Disable ((uint32_t)0x00000000) #define RTC_Output_AlarmA ((uint32_t)0x00200000) #define RTC_Output_AlarmB ((uint32_t)0x00400000) #define RTC_Output_WakeUp ((uint32_t)0x00600000) #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ ((OUTPUT) == RTC_Output_AlarmA) || \ ((OUTPUT) == RTC_Output_AlarmB) || \ ((OUTPUT) == RTC_Output_WakeUp)) /** * @} */ /** @defgroup RTC_Output_Polarity_Definitions * @{ */ #define RTC_OutputPolarity_High ((uint32_t)0x00000000) #define RTC_OutputPolarity_Low ((uint32_t)0x00100000) #define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ ((POL) == RTC_OutputPolarity_Low)) /** * @} */ /** @defgroup RTC_Digital_Calibration_Definitions * @{ */ #define RTC_CalibSign_Positive ((uint32_t)0x00000000) #define RTC_CalibSign_Negative ((uint32_t)0x00000080) #define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \ ((SIGN) == RTC_CalibSign_Negative)) #define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) /** * @} */ /** @defgroup RTC_Calib_Output_selection_Definitions * @{ */ #define RTC_CalibOutput_512Hz ((uint32_t)0x00000000) #define RTC_CalibOutput_1Hz ((uint32_t)0x00080000) #define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \ ((OUTPUT) == RTC_CalibOutput_1Hz)) /** * @} */ /** @defgroup RTC_Smooth_calib_period_Definitions * @{ */ #define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation period is 32s, else 2exp20 RTCCLK seconds */ #define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation period is 16s, else 2exp19 RTCCLK seconds */ #define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation period is 8s, else 2exp18 RTCCLK seconds */ #define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \ ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \ ((PERIOD) == RTC_SmoothCalibPeriod_8sec)) /** * @} */ /** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions * @{ */ #define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0]. with Y = 512, 256, 128 when X = 32, 16, 8 */ #define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0]. */ #define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \ ((PLUS) == RTC_SmoothCalibPlusPulses_Reset)) /** * @} */ /** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions * @{ */ #define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) /** * @} */ /** @defgroup RTC_DayLightSaving_Definitions * @{ */ #define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) #define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \ ((SAVE) == RTC_DayLightSaving_ADD1H)) #define RTC_StoreOperation_Reset ((uint32_t)0x00000000) #define RTC_StoreOperation_Set ((uint32_t)0x00040000) #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ ((OPERATION) == RTC_StoreOperation_Set)) /** * @} */ /** @defgroup RTC_Tamper_Trigger_Definitions * @{ */ #define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) #define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) #define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000) #define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001) #define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \ ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \ ((TRIGGER) == RTC_TamperTrigger_HighLevel)) /** * @} */ /** @defgroup RTC_Tamper_Filter_Definitions * @{ */ #define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ #define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 consecutive samples at the active level */ #define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 consecutive samples at the active level */ #define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 consecutive samples at the active leve. */ #define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \ ((FILTER) == RTC_TamperFilter_2Sample) || \ ((FILTER) == RTC_TamperFilter_4Sample) || \ ((FILTER) == RTC_TamperFilter_8Sample)) /** * @} */ /** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions * @{ */ #define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ #define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ #define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ #define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ #define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ #define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ #define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ #define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ #define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \ ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256)) /** * @} */ /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions * @{ */ #define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ #define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ #define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ #define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ #define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \ ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \ ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \ ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK)) /** * @} */ /** @defgroup RTC_Tamper_Pins_Definitions * @{ */ #define RTC_Tamper_1 RTC_TAFCR_TAMP1E #define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1)) /** * @} */ /** @defgroup RTC_Tamper_Pin_Selection * @{ */ #define RTC_TamperPin_PC13 ((uint32_t)0x00000000) #define RTC_TamperPin_PI8 ((uint32_t)0x00010000) #define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \ ((PIN) == RTC_TamperPin_PI8)) /** * @} */ /** @defgroup RTC_TimeStamp_Pin_Selection * @{ */ #define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000) #define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000) #define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \ ((PIN) == RTC_TimeStampPin_PI8)) /** * @} */ /** @defgroup RTC_Output_Type_ALARM_OUT * @{ */ #define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) #define RTC_OutputType_PushPull ((uint32_t)0x00040000) #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ ((TYPE) == RTC_OutputType_PushPull)) /** * @} */ /** @defgroup RTC_Add_1_Second_Parameter_Definitions * @{ */ #define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000) #define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000) #define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \ ((SEL) == RTC_ShiftAdd1S_Set)) /** * @} */ /** @defgroup RTC_Substract_Fraction_Of_Second_Value * @{ */ #define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) /** * @} */ /** @defgroup RTC_Backup_Registers_Definitions * @{ */ #define RTC_BKP_DR0 ((uint32_t)0x00000000) #define RTC_BKP_DR1 ((uint32_t)0x00000001) #define RTC_BKP_DR2 ((uint32_t)0x00000002) #define RTC_BKP_DR3 ((uint32_t)0x00000003) #define RTC_BKP_DR4 ((uint32_t)0x00000004) #define RTC_BKP_DR5 ((uint32_t)0x00000005) #define RTC_BKP_DR6 ((uint32_t)0x00000006) #define RTC_BKP_DR7 ((uint32_t)0x00000007) #define RTC_BKP_DR8 ((uint32_t)0x00000008) #define RTC_BKP_DR9 ((uint32_t)0x00000009) #define RTC_BKP_DR10 ((uint32_t)0x0000000A) #define RTC_BKP_DR11 ((uint32_t)0x0000000B) #define RTC_BKP_DR12 ((uint32_t)0x0000000C) #define RTC_BKP_DR13 ((uint32_t)0x0000000D) #define RTC_BKP_DR14 ((uint32_t)0x0000000E) #define RTC_BKP_DR15 ((uint32_t)0x0000000F) #define RTC_BKP_DR16 ((uint32_t)0x00000010) #define RTC_BKP_DR17 ((uint32_t)0x00000011) #define RTC_BKP_DR18 ((uint32_t)0x00000012) #define RTC_BKP_DR19 ((uint32_t)0x00000013) #define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ ((BKP) == RTC_BKP_DR1) || \ ((BKP) == RTC_BKP_DR2) || \ ((BKP) == RTC_BKP_DR3) || \ ((BKP) == RTC_BKP_DR4) || \ ((BKP) == RTC_BKP_DR5) || \ ((BKP) == RTC_BKP_DR6) || \ ((BKP) == RTC_BKP_DR7) || \ ((BKP) == RTC_BKP_DR8) || \ ((BKP) == RTC_BKP_DR9) || \ ((BKP) == RTC_BKP_DR10) || \ ((BKP) == RTC_BKP_DR11) || \ ((BKP) == RTC_BKP_DR12) || \ ((BKP) == RTC_BKP_DR13) || \ ((BKP) == RTC_BKP_DR14) || \ ((BKP) == RTC_BKP_DR15) || \ ((BKP) == RTC_BKP_DR16) || \ ((BKP) == RTC_BKP_DR17) || \ ((BKP) == RTC_BKP_DR18) || \ ((BKP) == RTC_BKP_DR19)) /** * @} */ /** @defgroup RTC_Input_parameter_format_definitions * @{ */ #define RTC_Format_BIN ((uint32_t)0x000000000) #define RTC_Format_BCD ((uint32_t)0x000000001) #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) /** * @} */ /** @defgroup RTC_Flags_Definitions * @{ */ #define RTC_FLAG_RECALPF ((uint32_t)0x00010000) #define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) #define RTC_FLAG_TSOVF ((uint32_t)0x00001000) #define RTC_FLAG_TSF ((uint32_t)0x00000800) #define RTC_FLAG_WUTF ((uint32_t)0x00000400) #define RTC_FLAG_ALRBF ((uint32_t)0x00000200) #define RTC_FLAG_ALRAF ((uint32_t)0x00000100) #define RTC_FLAG_INITF ((uint32_t)0x00000040) #define RTC_FLAG_RSF ((uint32_t)0x00000020) #define RTC_FLAG_INITS ((uint32_t)0x00000010) #define RTC_FLAG_SHPF ((uint32_t)0x00000008) #define RTC_FLAG_WUTWF ((uint32_t)0x00000004) #define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) #define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) #define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \ ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \ ((FLAG) == RTC_FLAG_SHPF)) #define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET)) /** * @} */ /** @defgroup RTC_Interrupts_Definitions * @{ */ #define RTC_IT_TS ((uint32_t)0x00008000) #define RTC_IT_WUT ((uint32_t)0x00004000) #define RTC_IT_ALRB ((uint32_t)0x00002000) #define RTC_IT_ALRA ((uint32_t)0x00001000) #define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ #define RTC_IT_TAMP1 ((uint32_t)0x00020000) #define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET)) #define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \ ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \ ((IT) == RTC_IT_TAMP1)) #define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET)) /** * @} */ /** @defgroup RTC_Legacy * @{ */ #define RTC_DigitalCalibConfig RTC_CoarseCalibConfig #define RTC_DigitalCalibCmd RTC_CoarseCalibCmd /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the RTC configuration to the default reset state *****/ ErrorStatus RTC_DeInit(void); /* Initialization and Configuration functions *********************************/ ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); void RTC_WriteProtectionCmd(FunctionalState NewState); ErrorStatus RTC_EnterInitMode(void); void RTC_ExitInitMode(void); ErrorStatus RTC_WaitForSynchro(void); ErrorStatus RTC_RefClockCmd(FunctionalState NewState); void RTC_BypassShadowCmd(FunctionalState NewState); /* Time and Date configuration functions **************************************/ ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); uint32_t RTC_GetSubSecond(void); ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); /* Alarms (Alarm A and Alarm B) configuration functions **********************/ void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask); uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); /* WakeUp Timer configuration functions ***************************************/ void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); uint32_t RTC_GetWakeUpCounter(void); ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); /* Daylight Saving configuration functions ************************************/ void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); uint32_t RTC_GetStoreOperation(void); /* Output pin Configuration function ******************************************/ void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); /* Digital Calibration configuration functions *********************************/ ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value); ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState); void RTC_CalibOutputCmd(FunctionalState NewState); void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput); ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, uint32_t RTC_SmoothCalibPlusPulses, uint32_t RTC_SmouthCalibMinusPulsesValue); /* TimeStamp configuration functions ******************************************/ void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, RTC_DateTypeDef* RTC_StampDateStruct); uint32_t RTC_GetTimeStampSubSecond(void); /* Tampers configuration functions ********************************************/ void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter); void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq); void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration); void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState); void RTC_TamperPullUpCmd(FunctionalState NewState); /* Backup Data Registers configuration functions ******************************/ void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); /* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions ******************************************************************/ void RTC_TamperPinSelection(uint32_t RTC_TamperPin); void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin); void RTC_OutputTypeConfig(uint32_t RTC_OutputType); /* RTC_Shift_control_synchonisation_functions *********************************/ ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS); /* Interrupts and flags management functions **********************************/ void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); void RTC_ClearFlag(uint32_t RTC_FLAG); ITStatus RTC_GetITStatus(uint32_t RTC_IT); void RTC_ClearITPendingBit(uint32_t RTC_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_RTC_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h ================================================ /** ****************************************************************************** * @file stm32f4xx_sai.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the SAI * firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_SAI_H #define __STM32F4xx_SAI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup SAI * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief SAI Block Init structure definition */ typedef struct { uint32_t SAI_AudioMode; /*!< Specifies the SAI Block Audio Mode. This parameter can be a value of @ref SAI_Block_Mode */ uint32_t SAI_Protocol; /*!< Specifies the SAI Block Protocol. This parameter can be a value of @ref SAI_Block_Protocol */ uint32_t SAI_DataSize; /*!< Specifies the SAI Block data size. This parameter can be a value of @ref SAI_Block_Data_Size @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ uint32_t SAI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission @note this value has no meaning when AC'97 or SPDIF protocols are selected.*/ uint32_t SAI_ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity. This parameter can be a value of @ref SAI_Block_Clock_Strobing */ uint32_t SAI_Synchro; /*!< Specifies SAI Block synchronization This parameter can be a value of @ref SAI_Block_Synchronization */ uint32_t SAI_OUTDRIV; /*!< Specifies when SAI Block outputs are driven. This parameter can be a value of @ref SAI_Block_Output_Drive @note this value has to be set before enabling the audio block but after the audio block configuration. */ uint32_t SAI_NoDivider; /*!< Specifies whether Master Clock will be divided or not. This parameter can be a value of @ref SAI_Block_NoDivider */ uint32_t SAI_MasterDivider; /*!< Specifies SAI Block Master Clock Divider. @note the Master Clock Frequency is calculated accordingly to the following formula : MCLK_x = SAI_CK_x/(MCKDIV[3:0]*2)*/ uint32_t SAI_FIFOThreshold; /*!< Specifies SAI Block FIFO Threshold. This parameter can be a value of @ref SAI_Block_Fifo_Threshold */ }SAI_InitTypeDef; /** * @brief SAI Block Frame Init structure definition */ typedef struct { uint32_t SAI_FrameLength; /*!< Specifies the Frame Length, the number of SCK clocks for each audio frame. This parameter must be a number between 8 and 256. @note If master Clock MCLK_x pin is declared as an output, the frame length should be Aligned to a number equal to power of 2 in order to keep in an audio frame, an integer number of MCLK pulses by bit Clock. @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ uint32_t SAI_ActiveFrameLength; /*!< Specifies the Frame synchronization active level length. This Parameter specifies the length in number of bit clock (SCK + 1) of the active level of FS signal in audio frame. This parameter must be a number between 1 and 128. @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ uint32_t SAI_FSDefinition; /*!< Specifies the Frame Synchronization definition. This parameter can be a value of @ref SAI_Block_FS_Definition @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ uint32_t SAI_FSPolarity; /*!< Specifies the Frame Synchronization Polarity. This parameter can be a value of @ref SAI_Block_FS_Polarity @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ uint32_t SAI_FSOffset; /*!< Specifies the Frame Synchronization Offset. This parameter can be a value of @ref SAI_Block_FS_Offset @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ }SAI_FrameInitTypeDef; /** * @brief SAI Block Slot Init Structure definition */ typedef struct { uint32_t SAI_FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot. This parameter must be a number between 0 and 24. @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ uint32_t SAI_SlotSize; /*!< Specifies the Slot Size. This parameter can be a value of @ref SAI_Block_Slot_Size @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ uint32_t SAI_SlotNumber; /*!< Specifies the number of slot in the audio frame. This parameter must be a number between 1 and 16. @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ uint32_t SAI_SlotActive; /*!< Specifies the slots in audio frame that will be activated. This parameter can be a value of @ ref SAI_Block_Slot_Active @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ }SAI_SlotInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup SAI_Exported_Constants * @{ */ #define IS_SAI_PERIPH(PERIPH) ((PERIPH) == SAI1) #define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \ ((PERIPH) == SAI1_Block_B)) /** @defgroup SAI_Block_Mode * @{ */ #define SAI_Mode_MasterTx ((uint32_t)0x00000000) #define SAI_Mode_MasterRx ((uint32_t)0x00000001) #define SAI_Mode_SlaveTx ((uint32_t)0x00000002) #define SAI_Mode_SlaveRx ((uint32_t)0x00000003) #define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_Mode_MasterTx) || \ ((MODE) == SAI_Mode_MasterRx) || \ ((MODE) == SAI_Mode_SlaveTx) || \ ((MODE) == SAI_Mode_SlaveRx)) /** * @} */ /** @defgroup SAI_Block_Protocol * @{ */ #define SAI_Free_Protocol ((uint32_t)0x00000000) #define SAI_SPDIF_Protocol ((uint32_t)SAI_xCR1_PRTCFG_0) #define SAI_AC97_Protocol ((uint32_t)SAI_xCR1_PRTCFG_1) #define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_Free_Protocol) || \ ((PROTOCOL) == SAI_SPDIF_Protocol) || \ ((PROTOCOL) == SAI_AC97_Protocol)) /** * @} */ /** @defgroup SAI_Block_Data_Size * @{ */ #define SAI_DataSize_8b ((uint32_t)0x00000040) #define SAI_DataSize_10b ((uint32_t)0x00000060) #define SAI_DataSize_16b ((uint32_t)0x00000080) #define SAI_DataSize_20b ((uint32_t)0x000000A0) #define SAI_DataSize_24b ((uint32_t)0x000000C0) #define SAI_DataSize_32b ((uint32_t)0x000000E0) #define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DataSize_8b) || \ ((DATASIZE) == SAI_DataSize_10b) || \ ((DATASIZE) == SAI_DataSize_16b) || \ ((DATASIZE) == SAI_DataSize_20b) || \ ((DATASIZE) == SAI_DataSize_24b) || \ ((DATASIZE) == SAI_DataSize_32b)) /** * @} */ /** @defgroup SAI_Block_MSB_LSB_transmission * @{ */ #define SAI_FirstBit_MSB ((uint32_t)0x00000000) #define SAI_FirstBit_LSB ((uint32_t)SAI_xCR1_LSBFIRST) #define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FirstBit_MSB) || \ ((BIT) == SAI_FirstBit_LSB)) /** * @} */ /** @defgroup SAI_Block_Clock_Strobing * @{ */ #define SAI_ClockStrobing_FallingEdge ((uint32_t)0x00000000) #define SAI_ClockStrobing_RisingEdge ((uint32_t)SAI_xCR1_CKSTR) #define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_ClockStrobing_FallingEdge) || \ ((CLOCK) == SAI_ClockStrobing_RisingEdge)) /** * @} */ /** @defgroup SAI_Block_Synchronization * @{ */ #define SAI_Asynchronous ((uint32_t)0x00000000) #define SAI_Synchronous ((uint32_t)SAI_xCR1_SYNCEN_0) #define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_Synchronous) || \ ((SYNCHRO) == SAI_Asynchronous)) /** * @} */ /** @defgroup SAI_Block_Output_Drive * @{ */ #define SAI_OutputDrive_Disabled ((uint32_t)0x00000000) #define SAI_OutputDrive_Enabled ((uint32_t)SAI_xCR1_OUTDRIV) #define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OutputDrive_Disabled) || \ ((DRIVE) == SAI_OutputDrive_Enabled)) /** * @} */ /** @defgroup SAI_Block_NoDivider * @{ */ #define SAI_MasterDivider_Enabled ((uint32_t)0x00000000) #define SAI_MasterDivider_Disabled ((uint32_t)SAI_xCR1_NODIV) #define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MasterDivider_Enabled) || \ ((NODIVIDER) == SAI_MasterDivider_Disabled)) /** * @} */ /** @defgroup SAI_Block_Master_Divider * @{ */ #define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15) /** * @} */ /** @defgroup SAI_Block_Frame_Length * @{ */ #define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256)) /** * @} */ /** @defgroup SAI_Block_Active_FrameLength * @{ */ #define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128)) /** * @} */ /** @defgroup SAI_Block_FS_Definition * @{ */ #define SAI_FS_StartFrame ((uint32_t)0x00000000) #define I2S_FS_ChannelIdentification ((uint32_t)SAI_xFRCR_FSDEF) #define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_StartFrame) || \ ((DEFINITION) == I2S_FS_ChannelIdentification)) /** * @} */ /** @defgroup SAI_Block_FS_Polarity * @{ */ #define SAI_FS_ActiveLow ((uint32_t)0x00000000) #define SAI_FS_ActiveHigh ((uint32_t)SAI_xFRCR_FSPO) #define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ActiveLow) || \ ((POLARITY) == SAI_FS_ActiveHigh)) /** * @} */ /** @defgroup SAI_Block_FS_Offset * @{ */ #define SAI_FS_FirstBit ((uint32_t)0x00000000) #define SAI_FS_BeforeFirstBit ((uint32_t)SAI_xFRCR_FSOFF) #define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FirstBit) || \ ((OFFSET) == SAI_FS_BeforeFirstBit)) /** * @} */ /** @defgroup SAI_Block_Slot_FirstBit_Offset * @{ */ #define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24) /** * @} */ /** @defgroup SAI_Block_Slot_Size * @{ */ #define SAI_SlotSize_DataSize ((uint32_t)0x00000000) #define SAI_SlotSize_16b ((uint32_t)SAI_xSLOTR_SLOTSZ_0) #define SAI_SlotSize_32b ((uint32_t)SAI_xSLOTR_SLOTSZ_1) #define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SlotSize_DataSize) || \ ((SIZE) == SAI_SlotSize_16b) || \ ((SIZE) == SAI_SlotSize_32b)) /** * @} */ /** @defgroup SAI_Block_Slot_Number * @{ */ #define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16)) /** * @} */ /** @defgroup SAI_Block_Slot_Active * @{ */ #define SAI_Slot_NotActive ((uint32_t)0x00000000) #define SAI_SlotActive_0 ((uint32_t)0x00010000) #define SAI_SlotActive_1 ((uint32_t)0x00020000) #define SAI_SlotActive_2 ((uint32_t)0x00040000) #define SAI_SlotActive_3 ((uint32_t)0x00080000) #define SAI_SlotActive_4 ((uint32_t)0x00100000) #define SAI_SlotActive_5 ((uint32_t)0x00200000) #define SAI_SlotActive_6 ((uint32_t)0x00400000) #define SAI_SlotActive_7 ((uint32_t)0x00800000) #define SAI_SlotActive_8 ((uint32_t)0x01000000) #define SAI_SlotActive_9 ((uint32_t)0x02000000) #define SAI_SlotActive_10 ((uint32_t)0x04000000) #define SAI_SlotActive_11 ((uint32_t)0x08000000) #define SAI_SlotActive_12 ((uint32_t)0x10000000) #define SAI_SlotActive_13 ((uint32_t)0x20000000) #define SAI_SlotActive_14 ((uint32_t)0x40000000) #define SAI_SlotActive_15 ((uint32_t)0x80000000) #define SAI_SlotActive_ALL ((uint32_t)0xFFFF0000) #define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) != 0) /** * @} */ /** @defgroup SAI_Mono_Streo_Mode * @{ */ #define SAI_MonoMode ((uint32_t)SAI_xCR1_MONO) #define SAI_StreoMode ((uint32_t)0x00000000) #define IS_SAI_BLOCK_MONO_STREO_MODE(MODE) (((MODE) == SAI_MonoMode) ||\ ((MODE) == SAI_StreoMode)) /** * @} */ /** @defgroup SAI_TRIState_Management * @{ */ #define SAI_Output_NotReleased ((uint32_t)0x00000000) #define SAI_Output_Released ((uint32_t)SAI_xCR2_TRIS) #define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_Output_NotReleased) ||\ ((STATE) == SAI_Output_Released)) /** * @} */ /** @defgroup SAI_Block_Fifo_Threshold * @{ */ #define SAI_Threshold_FIFOEmpty ((uint32_t)0x00000000) #define SAI_FIFOThreshold_1QuarterFull ((uint32_t)0x00000001) #define SAI_FIFOThreshold_HalfFull ((uint32_t)0x00000002) #define SAI_FIFOThreshold_3QuartersFull ((uint32_t)0x00000003) #define SAI_FIFOThreshold_Full ((uint32_t)0x00000004) #define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_Threshold_FIFOEmpty) || \ ((THRESHOLD) == SAI_FIFOThreshold_1QuarterFull) || \ ((THRESHOLD) == SAI_FIFOThreshold_HalfFull) || \ ((THRESHOLD) == SAI_FIFOThreshold_3QuartersFull) || \ ((THRESHOLD) == SAI_FIFOThreshold_Full)) /** * @} */ /** @defgroup SAI_Block_Companding_Mode * @{ */ #define SAI_NoCompanding ((uint32_t)0x00000000) #define SAI_ULaw_1CPL_Companding ((uint32_t)0x00008000) #define SAI_ALaw_1CPL_Companding ((uint32_t)0x0000C000) #define SAI_ULaw_2CPL_Companding ((uint32_t)0x0000A000) #define SAI_ALaw_2CPL_Companding ((uint32_t)0x0000E000) #define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NoCompanding) || \ ((MODE) == SAI_ULaw_1CPL_Companding) || \ ((MODE) == SAI_ALaw_1CPL_Companding) || \ ((MODE) == SAI_ULaw_2CPL_Companding) || \ ((MODE) == SAI_ALaw_2CPL_Companding)) /** * @} */ /** @defgroup SAI_Block_Mute_Value * @{ */ #define SAI_ZeroValue ((uint32_t)0x00000000) #define SAI_LastSentValue ((uint32_t)SAI_xCR2_MUTEVAL) #define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZeroValue) || \ ((VALUE) == SAI_LastSentValue)) /** * @} */ /** @defgroup SAI_Block_Mute_Frame_Counter * @{ */ #define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63) /** * @} */ /** @defgroup SAI_Block_Interrupts_Definition * @{ */ #define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE) #define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE) #define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE) #define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE) #define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE) #define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE) #define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE) #define IS_SAI_BLOCK_CONFIG_IT(IT) (((IT) == SAI_IT_OVRUDR) || \ ((IT) == SAI_IT_MUTEDET) || \ ((IT) == SAI_IT_WCKCFG) || \ ((IT) == SAI_IT_FREQ) || \ ((IT) == SAI_IT_CNRDY) || \ ((IT) == SAI_IT_AFSDET) || \ ((IT) == SAI_IT_LFSDET)) /** * @} */ /** @defgroup SAI_Block_Flags_Definition * @{ */ #define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR) #define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET) #define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG) #define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ) #define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY) #define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET) #define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET) #define IS_SAI_BLOCK_GET_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \ ((FLAG) == SAI_FLAG_MUTEDET) || \ ((FLAG) == SAI_FLAG_WCKCFG) || \ ((FLAG) == SAI_FLAG_FREQ) || \ ((FLAG) == SAI_FLAG_CNRDY) || \ ((FLAG) == SAI_FLAG_AFSDET) || \ ((FLAG) == SAI_FLAG_LFSDET)) #define IS_SAI_BLOCK_CLEAR_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \ ((FLAG) == SAI_FLAG_MUTEDET) || \ ((FLAG) == SAI_FLAG_WCKCFG) || \ ((FLAG) == SAI_FLAG_FREQ) || \ ((FLAG) == SAI_FLAG_CNRDY) || \ ((FLAG) == SAI_FLAG_AFSDET) || \ ((FLAG) == SAI_FLAG_LFSDET)) /** * @} */ /** @defgroup SAI_Block_Fifo_Status_Level * @{ */ #define SAI_FIFOStatus_Empty ((uint32_t)0x00000000) #define SAI_FIFOStatus_Less1QuarterFull ((uint32_t)0x00010000) #define SAI_FIFOStatus_1QuarterFull ((uint32_t)0x00020000) #define SAI_FIFOStatus_HalfFull ((uint32_t)0x00030000) #define SAI_FIFOStatus_3QuartersFull ((uint32_t)0x00040000) #define SAI_FIFOStatus_Full ((uint32_t)0x00050000) #define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOStatus_Less1QuarterFull ) || \ ((STATUS) == SAI_FIFOStatus_HalfFull) || \ ((STATUS) == SAI_FIFOStatus_1QuarterFull) || \ ((STATUS) == SAI_FIFOStatus_3QuartersFull) || \ ((STATUS) == SAI_FIFOStatus_Full) || \ ((STATUS) == SAI_FIFOStatus_Empty)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the SAI configuration to the default reset state *****/ void SAI_DeInit(SAI_TypeDef* SAIx); /* Initialization and Configuration functions *********************************/ void SAI_Init(SAI_Block_TypeDef* SAI_Block_x, SAI_InitTypeDef* SAI_InitStruct); void SAI_FrameInit(SAI_Block_TypeDef* SAI_Block_x, SAI_FrameInitTypeDef* SAI_FrameInitStruct); void SAI_SlotInit(SAI_Block_TypeDef* SAI_Block_x, SAI_SlotInitTypeDef* SAI_SlotInitStruct); void SAI_StructInit(SAI_InitTypeDef* SAI_InitStruct); void SAI_FrameStructInit(SAI_FrameInitTypeDef* SAI_FrameInitStruct); void SAI_SlotStructInit(SAI_SlotInitTypeDef* SAI_SlotInitStruct); void SAI_Cmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); void SAI_MonoModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_Mono_StreoMode); void SAI_TRIStateConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_TRIState); void SAI_CompandingModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_CompandingMode); void SAI_MuteModeCmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); void SAI_MuteValueConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteValue); void SAI_MuteFrameCounterConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteCounter); void SAI_FlushFIFO(SAI_Block_TypeDef* SAI_Block_x); /* Data transfers functions ***************************************************/ void SAI_SendData(SAI_Block_TypeDef* SAI_Block_x, uint32_t Data); uint32_t SAI_ReceiveData(SAI_Block_TypeDef* SAI_Block_x); /* DMA transfers management functions *****************************************/ void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState); FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x); uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_SAI_H */ /** * @} */ /** * @} */ /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h ================================================ /** ****************************************************************************** * @file stm32f4xx_sdio.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the SDIO firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_SDIO_H #define __STM32F4xx_SDIO_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup SDIO * @{ */ /* Exported types ------------------------------------------------------------*/ typedef struct { uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. This parameter can be a value of @ref SDIO_Clock_Edge */ uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is enabled or disabled. This parameter can be a value of @ref SDIO_Clock_Bypass */ uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or disabled when the bus is idle. This parameter can be a value of @ref SDIO_Clock_Power_Save */ uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. This parameter can be a value of @ref SDIO_Bus_Wide */ uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. This parameter can be a value between 0x00 and 0xFF. */ } SDIO_InitTypeDef; typedef struct { uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing the command to the command register */ uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ uint32_t SDIO_Response; /*!< Specifies the SDIO response type. This parameter can be a value of @ref SDIO_Response_Type */ uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait for interrupt request is enabled or disabled. This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) is enabled or disabled. This parameter can be a value of @ref SDIO_CPSM_State */ } SDIO_CmdInitTypeDef; typedef struct { uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. This parameter can be a value of @ref SDIO_Data_Block_Size */ uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer is a read or write. This parameter can be a value of @ref SDIO_Transfer_Direction */ uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. This parameter can be a value of @ref SDIO_Transfer_Type */ uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) is enabled or disabled. This parameter can be a value of @ref SDIO_DPSM_State */ } SDIO_DataInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup SDIO_Exported_Constants * @{ */ /** @defgroup SDIO_Clock_Edge * @{ */ #define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) #define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ ((EDGE) == SDIO_ClockEdge_Falling)) /** * @} */ /** @defgroup SDIO_Clock_Bypass * @{ */ #define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) #define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ ((BYPASS) == SDIO_ClockBypass_Enable)) /** * @} */ /** @defgroup SDIO_Clock_Power_Save * @{ */ #define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) #define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ ((SAVE) == SDIO_ClockPowerSave_Enable)) /** * @} */ /** @defgroup SDIO_Bus_Wide * @{ */ #define SDIO_BusWide_1b ((uint32_t)0x00000000) #define SDIO_BusWide_4b ((uint32_t)0x00000800) #define SDIO_BusWide_8b ((uint32_t)0x00001000) #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ ((WIDE) == SDIO_BusWide_8b)) /** * @} */ /** @defgroup SDIO_Hardware_Flow_Control * @{ */ #define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) #define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ ((CONTROL) == SDIO_HardwareFlowControl_Enable)) /** * @} */ /** @defgroup SDIO_Power_State * @{ */ #define SDIO_PowerState_OFF ((uint32_t)0x00000000) #define SDIO_PowerState_ON ((uint32_t)0x00000003) #define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) /** * @} */ /** @defgroup SDIO_Interrupt_sources * @{ */ #define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) #define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) #define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) #define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) #define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) #define SDIO_IT_RXOVERR ((uint32_t)0x00000020) #define SDIO_IT_CMDREND ((uint32_t)0x00000040) #define SDIO_IT_CMDSENT ((uint32_t)0x00000080) #define SDIO_IT_DATAEND ((uint32_t)0x00000100) #define SDIO_IT_STBITERR ((uint32_t)0x00000200) #define SDIO_IT_DBCKEND ((uint32_t)0x00000400) #define SDIO_IT_CMDACT ((uint32_t)0x00000800) #define SDIO_IT_TXACT ((uint32_t)0x00001000) #define SDIO_IT_RXACT ((uint32_t)0x00002000) #define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) #define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) #define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) #define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) #define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) #define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) #define SDIO_IT_TXDAVL ((uint32_t)0x00100000) #define SDIO_IT_RXDAVL ((uint32_t)0x00200000) #define SDIO_IT_SDIOIT ((uint32_t)0x00400000) #define SDIO_IT_CEATAEND ((uint32_t)0x00800000) #define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) /** * @} */ /** @defgroup SDIO_Command_Index * @{ */ #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) /** * @} */ /** @defgroup SDIO_Response_Type * @{ */ #define SDIO_Response_No ((uint32_t)0x00000000) #define SDIO_Response_Short ((uint32_t)0x00000040) #define SDIO_Response_Long ((uint32_t)0x000000C0) #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ ((RESPONSE) == SDIO_Response_Short) || \ ((RESPONSE) == SDIO_Response_Long)) /** * @} */ /** @defgroup SDIO_Wait_Interrupt_State * @{ */ #define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ #define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ #define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ ((WAIT) == SDIO_Wait_Pend)) /** * @} */ /** @defgroup SDIO_CPSM_State * @{ */ #define SDIO_CPSM_Disable ((uint32_t)0x00000000) #define SDIO_CPSM_Enable ((uint32_t)0x00000400) #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) /** * @} */ /** @defgroup SDIO_Response_Registers * @{ */ #define SDIO_RESP1 ((uint32_t)0x00000000) #define SDIO_RESP2 ((uint32_t)0x00000004) #define SDIO_RESP3 ((uint32_t)0x00000008) #define SDIO_RESP4 ((uint32_t)0x0000000C) #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) /** * @} */ /** @defgroup SDIO_Data_Length * @{ */ #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) /** * @} */ /** @defgroup SDIO_Data_Block_Size * @{ */ #define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) #define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) #define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) #define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) #define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) #define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) #define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) #define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) #define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) #define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) #define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) #define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) #define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) #define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) #define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ ((SIZE) == SDIO_DataBlockSize_2b) || \ ((SIZE) == SDIO_DataBlockSize_4b) || \ ((SIZE) == SDIO_DataBlockSize_8b) || \ ((SIZE) == SDIO_DataBlockSize_16b) || \ ((SIZE) == SDIO_DataBlockSize_32b) || \ ((SIZE) == SDIO_DataBlockSize_64b) || \ ((SIZE) == SDIO_DataBlockSize_128b) || \ ((SIZE) == SDIO_DataBlockSize_256b) || \ ((SIZE) == SDIO_DataBlockSize_512b) || \ ((SIZE) == SDIO_DataBlockSize_1024b) || \ ((SIZE) == SDIO_DataBlockSize_2048b) || \ ((SIZE) == SDIO_DataBlockSize_4096b) || \ ((SIZE) == SDIO_DataBlockSize_8192b) || \ ((SIZE) == SDIO_DataBlockSize_16384b)) /** * @} */ /** @defgroup SDIO_Transfer_Direction * @{ */ #define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) #define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ ((DIR) == SDIO_TransferDir_ToSDIO)) /** * @} */ /** @defgroup SDIO_Transfer_Type * @{ */ #define SDIO_TransferMode_Block ((uint32_t)0x00000000) #define SDIO_TransferMode_Stream ((uint32_t)0x00000004) #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ ((MODE) == SDIO_TransferMode_Block)) /** * @} */ /** @defgroup SDIO_DPSM_State * @{ */ #define SDIO_DPSM_Disable ((uint32_t)0x00000000) #define SDIO_DPSM_Enable ((uint32_t)0x00000001) #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) /** * @} */ /** @defgroup SDIO_Flags * @{ */ #define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) #define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) #define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) #define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) #define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) #define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) #define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) #define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) #define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) #define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) #define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) #define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) #define SDIO_FLAG_TXACT ((uint32_t)0x00001000) #define SDIO_FLAG_RXACT ((uint32_t)0x00002000) #define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) #define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) #define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) #define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) #define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) #define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) #define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) #define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) #define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) #define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) #define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ ((FLAG) == SDIO_FLAG_TXUNDERR) || \ ((FLAG) == SDIO_FLAG_RXOVERR) || \ ((FLAG) == SDIO_FLAG_CMDREND) || \ ((FLAG) == SDIO_FLAG_CMDSENT) || \ ((FLAG) == SDIO_FLAG_DATAEND) || \ ((FLAG) == SDIO_FLAG_STBITERR) || \ ((FLAG) == SDIO_FLAG_DBCKEND) || \ ((FLAG) == SDIO_FLAG_CMDACT) || \ ((FLAG) == SDIO_FLAG_TXACT) || \ ((FLAG) == SDIO_FLAG_RXACT) || \ ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ ((FLAG) == SDIO_FLAG_TXFIFOF) || \ ((FLAG) == SDIO_FLAG_RXFIFOF) || \ ((FLAG) == SDIO_FLAG_TXFIFOE) || \ ((FLAG) == SDIO_FLAG_RXFIFOE) || \ ((FLAG) == SDIO_FLAG_TXDAVL) || \ ((FLAG) == SDIO_FLAG_RXDAVL) || \ ((FLAG) == SDIO_FLAG_SDIOIT) || \ ((FLAG) == SDIO_FLAG_CEATAEND)) #define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) #define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ ((IT) == SDIO_IT_DCRCFAIL) || \ ((IT) == SDIO_IT_CTIMEOUT) || \ ((IT) == SDIO_IT_DTIMEOUT) || \ ((IT) == SDIO_IT_TXUNDERR) || \ ((IT) == SDIO_IT_RXOVERR) || \ ((IT) == SDIO_IT_CMDREND) || \ ((IT) == SDIO_IT_CMDSENT) || \ ((IT) == SDIO_IT_DATAEND) || \ ((IT) == SDIO_IT_STBITERR) || \ ((IT) == SDIO_IT_DBCKEND) || \ ((IT) == SDIO_IT_CMDACT) || \ ((IT) == SDIO_IT_TXACT) || \ ((IT) == SDIO_IT_RXACT) || \ ((IT) == SDIO_IT_TXFIFOHE) || \ ((IT) == SDIO_IT_RXFIFOHF) || \ ((IT) == SDIO_IT_TXFIFOF) || \ ((IT) == SDIO_IT_RXFIFOF) || \ ((IT) == SDIO_IT_TXFIFOE) || \ ((IT) == SDIO_IT_RXFIFOE) || \ ((IT) == SDIO_IT_TXDAVL) || \ ((IT) == SDIO_IT_RXDAVL) || \ ((IT) == SDIO_IT_SDIOIT) || \ ((IT) == SDIO_IT_CEATAEND)) #define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) /** * @} */ /** @defgroup SDIO_Read_Wait_Mode * @{ */ #define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) #define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ ((MODE) == SDIO_ReadWaitMode_DATA2)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the SDIO configuration to the default reset state ****/ void SDIO_DeInit(void); /* Initialization and Configuration functions *********************************/ void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); void SDIO_ClockCmd(FunctionalState NewState); void SDIO_SetPowerState(uint32_t SDIO_PowerState); uint32_t SDIO_GetPowerState(void); /* Command path state machine (CPSM) management functions *********************/ void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); uint8_t SDIO_GetCommandResponse(void); uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); /* Data path state machine (DPSM) management functions ************************/ void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); uint32_t SDIO_GetDataCounter(void); uint32_t SDIO_ReadData(void); void SDIO_WriteData(uint32_t Data); uint32_t SDIO_GetFIFOCount(void); /* SDIO IO Cards mode management functions ************************************/ void SDIO_StartSDIOReadWait(FunctionalState NewState); void SDIO_StopSDIOReadWait(FunctionalState NewState); void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); void SDIO_SetSDIOOperation(FunctionalState NewState); void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); /* CE-ATA mode management functions *******************************************/ void SDIO_CommandCompletionCmd(FunctionalState NewState); void SDIO_CEATAITCmd(FunctionalState NewState); void SDIO_SendCEATACmd(FunctionalState NewState); /* DMA transfers management functions *****************************************/ void SDIO_DMACmd(FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); void SDIO_ClearFlag(uint32_t SDIO_FLAG); ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); void SDIO_ClearITPendingBit(uint32_t SDIO_IT); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_SDIO_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h ================================================ /** ****************************************************************************** * @file stm32f4xx_spi.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the SPI * firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_SPI_H #define __STM32F4xx_SPI_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup SPI * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief SPI Init structure definition */ typedef struct { uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of @ref SPI_data_direction */ uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. This parameter can be a value of @ref SPI_mode */ uint16_t SPI_DataSize; /*!< Specifies the SPI data size. This parameter can be a value of @ref SPI_data_size */ uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_Clock_Polarity */ uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_Clock_Phase */ uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. This parameter can be a value of @ref SPI_Slave_Select_management */ uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be used to configure the transmit and receive SCK clock. This parameter can be a value of @ref SPI_BaudRate_Prescaler @note The communication clock is derived from the master clock. The slave clock does not need to be set. */ uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_MSB_LSB_transmission */ uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ }SPI_InitTypeDef; /** * @brief I2S Init structure definition */ typedef struct { uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. This parameter can be a value of @ref I2S_Mode */ uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. This parameter can be a value of @ref I2S_Standard */ uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. This parameter can be a value of @ref I2S_Data_Format */ uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. This parameter can be a value of @ref I2S_MCLK_Output */ uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. This parameter can be a value of @ref I2S_Audio_Frequency */ uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. This parameter can be a value of @ref I2S_Clock_Polarity */ }I2S_InitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup SPI_Exported_Constants * @{ */ #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ ((PERIPH) == SPI2) || \ ((PERIPH) == SPI3) || \ ((PERIPH) == SPI4) || \ ((PERIPH) == SPI5) || \ ((PERIPH) == SPI6)) #define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \ ((PERIPH) == SPI2) || \ ((PERIPH) == SPI3) || \ ((PERIPH) == SPI4) || \ ((PERIPH) == SPI5) || \ ((PERIPH) == SPI6) || \ ((PERIPH) == I2S2ext) || \ ((PERIPH) == I2S3ext)) #define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ ((PERIPH) == SPI3)) #define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \ ((PERIPH) == SPI3) || \ ((PERIPH) == I2S2ext) || \ ((PERIPH) == I2S3ext)) #define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \ ((PERIPH) == I2S3ext)) /** @defgroup SPI_data_direction * @{ */ #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) #define SPI_Direction_1Line_Rx ((uint16_t)0x8000) #define SPI_Direction_1Line_Tx ((uint16_t)0xC000) #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ ((MODE) == SPI_Direction_2Lines_RxOnly) || \ ((MODE) == SPI_Direction_1Line_Rx) || \ ((MODE) == SPI_Direction_1Line_Tx)) /** * @} */ /** @defgroup SPI_mode * @{ */ #define SPI_Mode_Master ((uint16_t)0x0104) #define SPI_Mode_Slave ((uint16_t)0x0000) #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ ((MODE) == SPI_Mode_Slave)) /** * @} */ /** @defgroup SPI_data_size * @{ */ #define SPI_DataSize_16b ((uint16_t)0x0800) #define SPI_DataSize_8b ((uint16_t)0x0000) #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ ((DATASIZE) == SPI_DataSize_8b)) /** * @} */ /** @defgroup SPI_Clock_Polarity * @{ */ #define SPI_CPOL_Low ((uint16_t)0x0000) #define SPI_CPOL_High ((uint16_t)0x0002) #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ ((CPOL) == SPI_CPOL_High)) /** * @} */ /** @defgroup SPI_Clock_Phase * @{ */ #define SPI_CPHA_1Edge ((uint16_t)0x0000) #define SPI_CPHA_2Edge ((uint16_t)0x0001) #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ ((CPHA) == SPI_CPHA_2Edge)) /** * @} */ /** @defgroup SPI_Slave_Select_management * @{ */ #define SPI_NSS_Soft ((uint16_t)0x0200) #define SPI_NSS_Hard ((uint16_t)0x0000) #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ ((NSS) == SPI_NSS_Hard)) /** * @} */ /** @defgroup SPI_BaudRate_Prescaler * @{ */ #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ ((PRESCALER) == SPI_BaudRatePrescaler_256)) /** * @} */ /** @defgroup SPI_MSB_LSB_transmission * @{ */ #define SPI_FirstBit_MSB ((uint16_t)0x0000) #define SPI_FirstBit_LSB ((uint16_t)0x0080) #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ ((BIT) == SPI_FirstBit_LSB)) /** * @} */ /** @defgroup SPI_I2S_Mode * @{ */ #define I2S_Mode_SlaveTx ((uint16_t)0x0000) #define I2S_Mode_SlaveRx ((uint16_t)0x0100) #define I2S_Mode_MasterTx ((uint16_t)0x0200) #define I2S_Mode_MasterRx ((uint16_t)0x0300) #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ ((MODE) == I2S_Mode_SlaveRx) || \ ((MODE) == I2S_Mode_MasterTx)|| \ ((MODE) == I2S_Mode_MasterRx)) /** * @} */ /** @defgroup SPI_I2S_Standard * @{ */ #define I2S_Standard_Phillips ((uint16_t)0x0000) #define I2S_Standard_MSB ((uint16_t)0x0010) #define I2S_Standard_LSB ((uint16_t)0x0020) #define I2S_Standard_PCMShort ((uint16_t)0x0030) #define I2S_Standard_PCMLong ((uint16_t)0x00B0) #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ ((STANDARD) == I2S_Standard_MSB) || \ ((STANDARD) == I2S_Standard_LSB) || \ ((STANDARD) == I2S_Standard_PCMShort) || \ ((STANDARD) == I2S_Standard_PCMLong)) /** * @} */ /** @defgroup SPI_I2S_Data_Format * @{ */ #define I2S_DataFormat_16b ((uint16_t)0x0000) #define I2S_DataFormat_16bextended ((uint16_t)0x0001) #define I2S_DataFormat_24b ((uint16_t)0x0003) #define I2S_DataFormat_32b ((uint16_t)0x0005) #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ ((FORMAT) == I2S_DataFormat_16bextended) || \ ((FORMAT) == I2S_DataFormat_24b) || \ ((FORMAT) == I2S_DataFormat_32b)) /** * @} */ /** @defgroup SPI_I2S_MCLK_Output * @{ */ #define I2S_MCLKOutput_Enable ((uint16_t)0x0200) #define I2S_MCLKOutput_Disable ((uint16_t)0x0000) #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ ((OUTPUT) == I2S_MCLKOutput_Disable)) /** * @} */ /** @defgroup SPI_I2S_Audio_Frequency * @{ */ #define I2S_AudioFreq_192k ((uint32_t)192000) #define I2S_AudioFreq_96k ((uint32_t)96000) #define I2S_AudioFreq_48k ((uint32_t)48000) #define I2S_AudioFreq_44k ((uint32_t)44100) #define I2S_AudioFreq_32k ((uint32_t)32000) #define I2S_AudioFreq_22k ((uint32_t)22050) #define I2S_AudioFreq_16k ((uint32_t)16000) #define I2S_AudioFreq_11k ((uint32_t)11025) #define I2S_AudioFreq_8k ((uint32_t)8000) #define I2S_AudioFreq_Default ((uint32_t)2) #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ ((FREQ) <= I2S_AudioFreq_192k)) || \ ((FREQ) == I2S_AudioFreq_Default)) /** * @} */ /** @defgroup SPI_I2S_Clock_Polarity * @{ */ #define I2S_CPOL_Low ((uint16_t)0x0000) #define I2S_CPOL_High ((uint16_t)0x0008) #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ ((CPOL) == I2S_CPOL_High)) /** * @} */ /** @defgroup SPI_I2S_DMA_transfer_requests * @{ */ #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) #define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) /** * @} */ /** @defgroup SPI_NSS_internal_software_management * @{ */ #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ ((INTERNAL) == SPI_NSSInternalSoft_Reset)) /** * @} */ /** @defgroup SPI_CRC_Transmit_Receive * @{ */ #define SPI_CRC_Tx ((uint8_t)0x00) #define SPI_CRC_Rx ((uint8_t)0x01) #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) /** * @} */ /** @defgroup SPI_direction_transmit_receive * @{ */ #define SPI_Direction_Rx ((uint16_t)0xBFFF) #define SPI_Direction_Tx ((uint16_t)0x4000) #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ ((DIRECTION) == SPI_Direction_Tx)) /** * @} */ /** @defgroup SPI_I2S_interrupts_definition * @{ */ #define SPI_I2S_IT_TXE ((uint8_t)0x71) #define SPI_I2S_IT_RXNE ((uint8_t)0x60) #define SPI_I2S_IT_ERR ((uint8_t)0x50) #define I2S_IT_UDR ((uint8_t)0x53) #define SPI_I2S_IT_TIFRFE ((uint8_t)0x58) #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ ((IT) == SPI_I2S_IT_RXNE) || \ ((IT) == SPI_I2S_IT_ERR)) #define SPI_I2S_IT_OVR ((uint8_t)0x56) #define SPI_IT_MODF ((uint8_t)0x55) #define SPI_IT_CRCERR ((uint8_t)0x54) #define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \ ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \ ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\ ((IT) == SPI_I2S_IT_TIFRFE)) /** * @} */ /** @defgroup SPI_I2S_flags_definition * @{ */ #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) #define I2S_FLAG_CHSIDE ((uint16_t)0x0004) #define I2S_FLAG_UDR ((uint16_t)0x0008) #define SPI_FLAG_CRCERR ((uint16_t)0x0010) #define SPI_FLAG_MODF ((uint16_t)0x0020) #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) #define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100) #define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ ((FLAG) == SPI_I2S_FLAG_TIFRFE)) /** * @} */ /** @defgroup SPI_CRC_polynomial * @{ */ #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) /** * @} */ /** @defgroup SPI_I2S_Legacy * @{ */ #define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx #define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx #define SPI_IT_TXE SPI_I2S_IT_TXE #define SPI_IT_RXNE SPI_I2S_IT_RXNE #define SPI_IT_ERR SPI_I2S_IT_ERR #define SPI_IT_OVR SPI_I2S_IT_OVR #define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE #define SPI_FLAG_TXE SPI_I2S_FLAG_TXE #define SPI_FLAG_OVR SPI_I2S_FLAG_OVR #define SPI_FLAG_BSY SPI_I2S_FLAG_BSY #define SPI_DeInit SPI_I2S_DeInit #define SPI_ITConfig SPI_I2S_ITConfig #define SPI_DMACmd SPI_I2S_DMACmd #define SPI_SendData SPI_I2S_SendData #define SPI_ReceiveData SPI_I2S_ReceiveData #define SPI_GetFlagStatus SPI_I2S_GetFlagStatus #define SPI_ClearFlag SPI_I2S_ClearFlag #define SPI_GetITStatus SPI_I2S_GetITStatus #define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the SPI configuration to the default reset state *****/ void SPI_I2S_DeInit(SPI_TypeDef* SPIx); /* Initialization and Configuration functions *********************************/ void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct); /* Data transfers functions ***************************************************/ void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); /* Hardware CRC Calculation functions *****************************************/ void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); void SPI_TransmitCRC(SPI_TypeDef* SPIx); uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); /* DMA transfers management functions *****************************************/ void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_SPI_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h ================================================ /** ****************************************************************************** * @file stm32f4xx_syscfg.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the SYSCFG firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_SYSCFG_H #define __STM32F4xx_SYSCFG_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup SYSCFG * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup SYSCFG_Exported_Constants * @{ */ /** @defgroup SYSCFG_EXTI_Port_Sources * @{ */ #define EXTI_PortSourceGPIOA ((uint8_t)0x00) #define EXTI_PortSourceGPIOB ((uint8_t)0x01) #define EXTI_PortSourceGPIOC ((uint8_t)0x02) #define EXTI_PortSourceGPIOD ((uint8_t)0x03) #define EXTI_PortSourceGPIOE ((uint8_t)0x04) #define EXTI_PortSourceGPIOF ((uint8_t)0x05) #define EXTI_PortSourceGPIOG ((uint8_t)0x06) #define EXTI_PortSourceGPIOH ((uint8_t)0x07) #define EXTI_PortSourceGPIOI ((uint8_t)0x08) #define EXTI_PortSourceGPIOJ ((uint8_t)0x09) #define EXTI_PortSourceGPIOK ((uint8_t)0x0A) #define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOI) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOJ) || \ ((PORTSOURCE) == EXTI_PortSourceGPIOK)) /** * @} */ /** @defgroup SYSCFG_EXTI_Pin_Sources * @{ */ #define EXTI_PinSource0 ((uint8_t)0x00) #define EXTI_PinSource1 ((uint8_t)0x01) #define EXTI_PinSource2 ((uint8_t)0x02) #define EXTI_PinSource3 ((uint8_t)0x03) #define EXTI_PinSource4 ((uint8_t)0x04) #define EXTI_PinSource5 ((uint8_t)0x05) #define EXTI_PinSource6 ((uint8_t)0x06) #define EXTI_PinSource7 ((uint8_t)0x07) #define EXTI_PinSource8 ((uint8_t)0x08) #define EXTI_PinSource9 ((uint8_t)0x09) #define EXTI_PinSource10 ((uint8_t)0x0A) #define EXTI_PinSource11 ((uint8_t)0x0B) #define EXTI_PinSource12 ((uint8_t)0x0C) #define EXTI_PinSource13 ((uint8_t)0x0D) #define EXTI_PinSource14 ((uint8_t)0x0E) #define EXTI_PinSource15 ((uint8_t)0x0F) #define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ ((PINSOURCE) == EXTI_PinSource1) || \ ((PINSOURCE) == EXTI_PinSource2) || \ ((PINSOURCE) == EXTI_PinSource3) || \ ((PINSOURCE) == EXTI_PinSource4) || \ ((PINSOURCE) == EXTI_PinSource5) || \ ((PINSOURCE) == EXTI_PinSource6) || \ ((PINSOURCE) == EXTI_PinSource7) || \ ((PINSOURCE) == EXTI_PinSource8) || \ ((PINSOURCE) == EXTI_PinSource9) || \ ((PINSOURCE) == EXTI_PinSource10) || \ ((PINSOURCE) == EXTI_PinSource11) || \ ((PINSOURCE) == EXTI_PinSource12) || \ ((PINSOURCE) == EXTI_PinSource13) || \ ((PINSOURCE) == EXTI_PinSource14) || \ ((PINSOURCE) == EXTI_PinSource15)) /** * @} */ /** @defgroup SYSCFG_Memory_Remap_Config * @{ */ #define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) #define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01) #define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) #define SYSCFG_MemoryRemap_SDRAM ((uint8_t)0x04) #if defined (STM32F40_41xxx) #define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02) #endif /* STM32F40_41xxx */ #if defined (STM32F427_437xx) || defined (STM32F429_439xx) #define SYSCFG_MemoryRemap_FMC ((uint8_t)0x02) #endif /* STM32F427_437xx || STM32F429_439xx */ #if defined (STM32F40_41xxx) #define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ ((REMAP) == SYSCFG_MemoryRemap_FSMC)) #endif /* STM32F40_41xxx */ #if defined (STM32F401xx) #define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ ((REMAP) == SYSCFG_MemoryRemap_SRAM)) #endif /* STM32F401xx */ #if defined (STM32F427_437xx) || defined (STM32F429_439xx) #define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ ((REMAP) == SYSCFG_MemoryRemap_SDRAM) || \ ((REMAP) == SYSCFG_MemoryRemap_FMC)) #endif /* STM32F427_437xx || STM32F429_439xx */ /** * @} */ /** @defgroup SYSCFG_ETHERNET_Media_Interface * @{ */ #define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000) #define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001) #define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \ ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ void SYSCFG_DeInit(void); void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap); void SYSCFG_MemorySwappingBank(FunctionalState NewState); void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); void SYSCFG_CompensationCellCmd(FunctionalState NewState); FlagStatus SYSCFG_GetCompensationCellStatus(void); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_SYSCFG_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h ================================================ /** ****************************************************************************** * @file stm32f4xx_tim.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the TIM firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_TIM_H #define __STM32F4xx_TIM_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup TIM * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief TIM Time Base Init structure definition * @note This structure is used with all TIMx except for TIM6 and TIM7. */ typedef struct { uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between 0x0000 and 0xFFFF */ uint16_t TIM_CounterMode; /*!< Specifies the counter mode. This parameter can be a value of @ref TIM_Counter_Mode */ uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between 0x0000 and 0xFFFF. */ uint16_t TIM_ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_Clock_Division_CKD */ uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts from the RCR value (N). This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode This parameter must be a number between 0x00 and 0xFF. @note This parameter is valid only for TIM1 and TIM8. */ } TIM_TimeBaseInitTypeDef; /** * @brief TIM Output Compare Init structure definition */ typedef struct { uint16_t TIM_OCMode; /*!< Specifies the TIM mode. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. This parameter can be a value of @ref TIM_Output_Compare_State */ uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. This parameter can be a value of @ref TIM_Output_Compare_N_State @note This parameter is valid only for TIM1 and TIM8. */ uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. This parameter can be a number between 0x0000 and 0xFFFF */ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_Output_Compare_Polarity */ uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_Output_Compare_N_Polarity @note This parameter is valid only for TIM1 and TIM8. */ uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_Idle_State @note This parameter is valid only for TIM1 and TIM8. */ uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State @note This parameter is valid only for TIM1 and TIM8. */ } TIM_OCInitTypeDef; /** * @brief TIM Input Capture Init structure definition */ typedef struct { uint16_t TIM_Channel; /*!< Specifies the TIM channel. This parameter can be a value of @ref TIM_Channel */ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_Input_Capture_Polarity */ uint16_t TIM_ICSelection; /*!< Specifies the input. This parameter can be a value of @ref TIM_Input_Capture_Selection */ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. This parameter can be a number between 0x0 and 0xF */ } TIM_ICInitTypeDef; /** * @brief BDTR structure definition * @note This structure is used only with TIM1 and TIM8. */ typedef struct { uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. This parameter can be a value of @ref TIM_Lock_level */ uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the switching-on of the outputs. This parameter can be a number between 0x00 and 0xFF */ uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. This parameter can be a value of @ref TIM_Break_Input_enable_disable */ uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. This parameter can be a value of @ref TIM_Break_Polarity */ uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ } TIM_BDTRInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup TIM_Exported_constants * @{ */ #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ ((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM4) || \ ((PERIPH) == TIM5) || \ ((PERIPH) == TIM6) || \ ((PERIPH) == TIM7) || \ ((PERIPH) == TIM8) || \ ((PERIPH) == TIM9) || \ ((PERIPH) == TIM10) || \ ((PERIPH) == TIM11) || \ ((PERIPH) == TIM12) || \ (((PERIPH) == TIM13) || \ ((PERIPH) == TIM14))) /* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */ #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ ((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM4) || \ ((PERIPH) == TIM5) || \ ((PERIPH) == TIM8) || \ ((PERIPH) == TIM9) || \ ((PERIPH) == TIM10) || \ ((PERIPH) == TIM11) || \ ((PERIPH) == TIM12) || \ ((PERIPH) == TIM13) || \ ((PERIPH) == TIM14)) /* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */ #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ ((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM4) || \ ((PERIPH) == TIM5) || \ ((PERIPH) == TIM8) || \ ((PERIPH) == TIM9) || \ ((PERIPH) == TIM12)) /* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */ #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ ((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM4) || \ ((PERIPH) == TIM5) || \ ((PERIPH) == TIM8)) /* LIST4: TIM1 and TIM8 */ #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ ((PERIPH) == TIM8)) /* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */ #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ ((PERIPH) == TIM2) || \ ((PERIPH) == TIM3) || \ ((PERIPH) == TIM4) || \ ((PERIPH) == TIM5) || \ ((PERIPH) == TIM6) || \ ((PERIPH) == TIM7) || \ ((PERIPH) == TIM8)) /* LIST6: TIM2, TIM5 and TIM11 */ #define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \ ((TIMx) == TIM5) || \ ((TIMx) == TIM11)) /** @defgroup TIM_Output_Compare_and_PWM_modes * @{ */ #define TIM_OCMode_Timing ((uint16_t)0x0000) #define TIM_OCMode_Active ((uint16_t)0x0010) #define TIM_OCMode_Inactive ((uint16_t)0x0020) #define TIM_OCMode_Toggle ((uint16_t)0x0030) #define TIM_OCMode_PWM1 ((uint16_t)0x0060) #define TIM_OCMode_PWM2 ((uint16_t)0x0070) #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ ((MODE) == TIM_OCMode_Active) || \ ((MODE) == TIM_OCMode_Inactive) || \ ((MODE) == TIM_OCMode_Toggle)|| \ ((MODE) == TIM_OCMode_PWM1) || \ ((MODE) == TIM_OCMode_PWM2)) #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ ((MODE) == TIM_OCMode_Active) || \ ((MODE) == TIM_OCMode_Inactive) || \ ((MODE) == TIM_OCMode_Toggle)|| \ ((MODE) == TIM_OCMode_PWM1) || \ ((MODE) == TIM_OCMode_PWM2) || \ ((MODE) == TIM_ForcedAction_Active) || \ ((MODE) == TIM_ForcedAction_InActive)) /** * @} */ /** @defgroup TIM_One_Pulse_Mode * @{ */ #define TIM_OPMode_Single ((uint16_t)0x0008) #define TIM_OPMode_Repetitive ((uint16_t)0x0000) #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ ((MODE) == TIM_OPMode_Repetitive)) /** * @} */ /** @defgroup TIM_Channel * @{ */ #define TIM_Channel_1 ((uint16_t)0x0000) #define TIM_Channel_2 ((uint16_t)0x0004) #define TIM_Channel_3 ((uint16_t)0x0008) #define TIM_Channel_4 ((uint16_t)0x000C) #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ ((CHANNEL) == TIM_Channel_2) || \ ((CHANNEL) == TIM_Channel_3) || \ ((CHANNEL) == TIM_Channel_4)) #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ ((CHANNEL) == TIM_Channel_2)) #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ ((CHANNEL) == TIM_Channel_2) || \ ((CHANNEL) == TIM_Channel_3)) /** * @} */ /** @defgroup TIM_Clock_Division_CKD * @{ */ #define TIM_CKD_DIV1 ((uint16_t)0x0000) #define TIM_CKD_DIV2 ((uint16_t)0x0100) #define TIM_CKD_DIV4 ((uint16_t)0x0200) #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ ((DIV) == TIM_CKD_DIV2) || \ ((DIV) == TIM_CKD_DIV4)) /** * @} */ /** @defgroup TIM_Counter_Mode * @{ */ #define TIM_CounterMode_Up ((uint16_t)0x0000) #define TIM_CounterMode_Down ((uint16_t)0x0010) #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ ((MODE) == TIM_CounterMode_Down) || \ ((MODE) == TIM_CounterMode_CenterAligned1) || \ ((MODE) == TIM_CounterMode_CenterAligned2) || \ ((MODE) == TIM_CounterMode_CenterAligned3)) /** * @} */ /** @defgroup TIM_Output_Compare_Polarity * @{ */ #define TIM_OCPolarity_High ((uint16_t)0x0000) #define TIM_OCPolarity_Low ((uint16_t)0x0002) #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ ((POLARITY) == TIM_OCPolarity_Low)) /** * @} */ /** @defgroup TIM_Output_Compare_N_Polarity * @{ */ #define TIM_OCNPolarity_High ((uint16_t)0x0000) #define TIM_OCNPolarity_Low ((uint16_t)0x0008) #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ ((POLARITY) == TIM_OCNPolarity_Low)) /** * @} */ /** @defgroup TIM_Output_Compare_State * @{ */ #define TIM_OutputState_Disable ((uint16_t)0x0000) #define TIM_OutputState_Enable ((uint16_t)0x0001) #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ ((STATE) == TIM_OutputState_Enable)) /** * @} */ /** @defgroup TIM_Output_Compare_N_State * @{ */ #define TIM_OutputNState_Disable ((uint16_t)0x0000) #define TIM_OutputNState_Enable ((uint16_t)0x0004) #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ ((STATE) == TIM_OutputNState_Enable)) /** * @} */ /** @defgroup TIM_Capture_Compare_State * @{ */ #define TIM_CCx_Enable ((uint16_t)0x0001) #define TIM_CCx_Disable ((uint16_t)0x0000) #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ ((CCX) == TIM_CCx_Disable)) /** * @} */ /** @defgroup TIM_Capture_Compare_N_State * @{ */ #define TIM_CCxN_Enable ((uint16_t)0x0004) #define TIM_CCxN_Disable ((uint16_t)0x0000) #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ ((CCXN) == TIM_CCxN_Disable)) /** * @} */ /** @defgroup TIM_Break_Input_enable_disable * @{ */ #define TIM_Break_Enable ((uint16_t)0x1000) #define TIM_Break_Disable ((uint16_t)0x0000) #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ ((STATE) == TIM_Break_Disable)) /** * @} */ /** @defgroup TIM_Break_Polarity * @{ */ #define TIM_BreakPolarity_Low ((uint16_t)0x0000) #define TIM_BreakPolarity_High ((uint16_t)0x2000) #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ ((POLARITY) == TIM_BreakPolarity_High)) /** * @} */ /** @defgroup TIM_AOE_Bit_Set_Reset * @{ */ #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ ((STATE) == TIM_AutomaticOutput_Disable)) /** * @} */ /** @defgroup TIM_Lock_level * @{ */ #define TIM_LOCKLevel_OFF ((uint16_t)0x0000) #define TIM_LOCKLevel_1 ((uint16_t)0x0100) #define TIM_LOCKLevel_2 ((uint16_t)0x0200) #define TIM_LOCKLevel_3 ((uint16_t)0x0300) #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ ((LEVEL) == TIM_LOCKLevel_1) || \ ((LEVEL) == TIM_LOCKLevel_2) || \ ((LEVEL) == TIM_LOCKLevel_3)) /** * @} */ /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state * @{ */ #define TIM_OSSIState_Enable ((uint16_t)0x0400) #define TIM_OSSIState_Disable ((uint16_t)0x0000) #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ ((STATE) == TIM_OSSIState_Disable)) /** * @} */ /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state * @{ */ #define TIM_OSSRState_Enable ((uint16_t)0x0800) #define TIM_OSSRState_Disable ((uint16_t)0x0000) #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ ((STATE) == TIM_OSSRState_Disable)) /** * @} */ /** @defgroup TIM_Output_Compare_Idle_State * @{ */ #define TIM_OCIdleState_Set ((uint16_t)0x0100) #define TIM_OCIdleState_Reset ((uint16_t)0x0000) #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ ((STATE) == TIM_OCIdleState_Reset)) /** * @} */ /** @defgroup TIM_Output_Compare_N_Idle_State * @{ */ #define TIM_OCNIdleState_Set ((uint16_t)0x0200) #define TIM_OCNIdleState_Reset ((uint16_t)0x0000) #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ ((STATE) == TIM_OCNIdleState_Reset)) /** * @} */ /** @defgroup TIM_Input_Capture_Polarity * @{ */ #define TIM_ICPolarity_Rising ((uint16_t)0x0000) #define TIM_ICPolarity_Falling ((uint16_t)0x0002) #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ ((POLARITY) == TIM_ICPolarity_Falling)|| \ ((POLARITY) == TIM_ICPolarity_BothEdge)) /** * @} */ /** @defgroup TIM_Input_Capture_Selection * @{ */ #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively. */ #define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ ((SELECTION) == TIM_ICSelection_IndirectTI) || \ ((SELECTION) == TIM_ICSelection_TRC)) /** * @} */ /** @defgroup TIM_Input_Capture_Prescaler * @{ */ #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ ((PRESCALER) == TIM_ICPSC_DIV2) || \ ((PRESCALER) == TIM_ICPSC_DIV4) || \ ((PRESCALER) == TIM_ICPSC_DIV8)) /** * @} */ /** @defgroup TIM_interrupt_sources * @{ */ #define TIM_IT_Update ((uint16_t)0x0001) #define TIM_IT_CC1 ((uint16_t)0x0002) #define TIM_IT_CC2 ((uint16_t)0x0004) #define TIM_IT_CC3 ((uint16_t)0x0008) #define TIM_IT_CC4 ((uint16_t)0x0010) #define TIM_IT_COM ((uint16_t)0x0020) #define TIM_IT_Trigger ((uint16_t)0x0040) #define TIM_IT_Break ((uint16_t)0x0080) #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ ((IT) == TIM_IT_CC1) || \ ((IT) == TIM_IT_CC2) || \ ((IT) == TIM_IT_CC3) || \ ((IT) == TIM_IT_CC4) || \ ((IT) == TIM_IT_COM) || \ ((IT) == TIM_IT_Trigger) || \ ((IT) == TIM_IT_Break)) /** * @} */ /** @defgroup TIM_DMA_Base_address * @{ */ #define TIM_DMABase_CR1 ((uint16_t)0x0000) #define TIM_DMABase_CR2 ((uint16_t)0x0001) #define TIM_DMABase_SMCR ((uint16_t)0x0002) #define TIM_DMABase_DIER ((uint16_t)0x0003) #define TIM_DMABase_SR ((uint16_t)0x0004) #define TIM_DMABase_EGR ((uint16_t)0x0005) #define TIM_DMABase_CCMR1 ((uint16_t)0x0006) #define TIM_DMABase_CCMR2 ((uint16_t)0x0007) #define TIM_DMABase_CCER ((uint16_t)0x0008) #define TIM_DMABase_CNT ((uint16_t)0x0009) #define TIM_DMABase_PSC ((uint16_t)0x000A) #define TIM_DMABase_ARR ((uint16_t)0x000B) #define TIM_DMABase_RCR ((uint16_t)0x000C) #define TIM_DMABase_CCR1 ((uint16_t)0x000D) #define TIM_DMABase_CCR2 ((uint16_t)0x000E) #define TIM_DMABase_CCR3 ((uint16_t)0x000F) #define TIM_DMABase_CCR4 ((uint16_t)0x0010) #define TIM_DMABase_BDTR ((uint16_t)0x0011) #define TIM_DMABase_DCR ((uint16_t)0x0012) #define TIM_DMABase_OR ((uint16_t)0x0013) #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ ((BASE) == TIM_DMABase_CR2) || \ ((BASE) == TIM_DMABase_SMCR) || \ ((BASE) == TIM_DMABase_DIER) || \ ((BASE) == TIM_DMABase_SR) || \ ((BASE) == TIM_DMABase_EGR) || \ ((BASE) == TIM_DMABase_CCMR1) || \ ((BASE) == TIM_DMABase_CCMR2) || \ ((BASE) == TIM_DMABase_CCER) || \ ((BASE) == TIM_DMABase_CNT) || \ ((BASE) == TIM_DMABase_PSC) || \ ((BASE) == TIM_DMABase_ARR) || \ ((BASE) == TIM_DMABase_RCR) || \ ((BASE) == TIM_DMABase_CCR1) || \ ((BASE) == TIM_DMABase_CCR2) || \ ((BASE) == TIM_DMABase_CCR3) || \ ((BASE) == TIM_DMABase_CCR4) || \ ((BASE) == TIM_DMABase_BDTR) || \ ((BASE) == TIM_DMABase_DCR) || \ ((BASE) == TIM_DMABase_OR)) /** * @} */ /** @defgroup TIM_DMA_Burst_Length * @{ */ #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ ((LENGTH) == TIM_DMABurstLength_18Transfers)) /** * @} */ /** @defgroup TIM_DMA_sources * @{ */ #define TIM_DMA_Update ((uint16_t)0x0100) #define TIM_DMA_CC1 ((uint16_t)0x0200) #define TIM_DMA_CC2 ((uint16_t)0x0400) #define TIM_DMA_CC3 ((uint16_t)0x0800) #define TIM_DMA_CC4 ((uint16_t)0x1000) #define TIM_DMA_COM ((uint16_t)0x2000) #define TIM_DMA_Trigger ((uint16_t)0x4000) #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) /** * @} */ /** @defgroup TIM_External_Trigger_Prescaler * @{ */ #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) /** * @} */ /** @defgroup TIM_Internal_Trigger_Selection * @{ */ #define TIM_TS_ITR0 ((uint16_t)0x0000) #define TIM_TS_ITR1 ((uint16_t)0x0010) #define TIM_TS_ITR2 ((uint16_t)0x0020) #define TIM_TS_ITR3 ((uint16_t)0x0030) #define TIM_TS_TI1F_ED ((uint16_t)0x0040) #define TIM_TS_TI1FP1 ((uint16_t)0x0050) #define TIM_TS_TI2FP2 ((uint16_t)0x0060) #define TIM_TS_ETRF ((uint16_t)0x0070) #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ ((SELECTION) == TIM_TS_ITR1) || \ ((SELECTION) == TIM_TS_ITR2) || \ ((SELECTION) == TIM_TS_ITR3) || \ ((SELECTION) == TIM_TS_TI1F_ED) || \ ((SELECTION) == TIM_TS_TI1FP1) || \ ((SELECTION) == TIM_TS_TI2FP2) || \ ((SELECTION) == TIM_TS_ETRF)) #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ ((SELECTION) == TIM_TS_ITR1) || \ ((SELECTION) == TIM_TS_ITR2) || \ ((SELECTION) == TIM_TS_ITR3)) /** * @} */ /** @defgroup TIM_TIx_External_Clock_Source * @{ */ #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) /** * @} */ /** @defgroup TIM_External_Trigger_Polarity * @{ */ #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) /** * @} */ /** @defgroup TIM_Prescaler_Reload_Mode * @{ */ #define TIM_PSCReloadMode_Update ((uint16_t)0x0000) #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ ((RELOAD) == TIM_PSCReloadMode_Immediate)) /** * @} */ /** @defgroup TIM_Forced_Action * @{ */ #define TIM_ForcedAction_Active ((uint16_t)0x0050) #define TIM_ForcedAction_InActive ((uint16_t)0x0040) #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ ((ACTION) == TIM_ForcedAction_InActive)) /** * @} */ /** @defgroup TIM_Encoder_Mode * @{ */ #define TIM_EncoderMode_TI1 ((uint16_t)0x0001) #define TIM_EncoderMode_TI2 ((uint16_t)0x0002) #define TIM_EncoderMode_TI12 ((uint16_t)0x0003) #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ ((MODE) == TIM_EncoderMode_TI2) || \ ((MODE) == TIM_EncoderMode_TI12)) /** * @} */ /** @defgroup TIM_Event_Source * @{ */ #define TIM_EventSource_Update ((uint16_t)0x0001) #define TIM_EventSource_CC1 ((uint16_t)0x0002) #define TIM_EventSource_CC2 ((uint16_t)0x0004) #define TIM_EventSource_CC3 ((uint16_t)0x0008) #define TIM_EventSource_CC4 ((uint16_t)0x0010) #define TIM_EventSource_COM ((uint16_t)0x0020) #define TIM_EventSource_Trigger ((uint16_t)0x0040) #define TIM_EventSource_Break ((uint16_t)0x0080) #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) /** * @} */ /** @defgroup TIM_Update_Source * @{ */ #define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow or the setting of UG bit, or an update generation through the slave mode controller. */ #define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ ((SOURCE) == TIM_UpdateSource_Regular)) /** * @} */ /** @defgroup TIM_Output_Compare_Preload_State * @{ */ #define TIM_OCPreload_Enable ((uint16_t)0x0008) #define TIM_OCPreload_Disable ((uint16_t)0x0000) #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ ((STATE) == TIM_OCPreload_Disable)) /** * @} */ /** @defgroup TIM_Output_Compare_Fast_State * @{ */ #define TIM_OCFast_Enable ((uint16_t)0x0004) #define TIM_OCFast_Disable ((uint16_t)0x0000) #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ ((STATE) == TIM_OCFast_Disable)) /** * @} */ /** @defgroup TIM_Output_Compare_Clear_State * @{ */ #define TIM_OCClear_Enable ((uint16_t)0x0080) #define TIM_OCClear_Disable ((uint16_t)0x0000) #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ ((STATE) == TIM_OCClear_Disable)) /** * @} */ /** @defgroup TIM_Trigger_Output_Source * @{ */ #define TIM_TRGOSource_Reset ((uint16_t)0x0000) #define TIM_TRGOSource_Enable ((uint16_t)0x0010) #define TIM_TRGOSource_Update ((uint16_t)0x0020) #define TIM_TRGOSource_OC1 ((uint16_t)0x0030) #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ ((SOURCE) == TIM_TRGOSource_Enable) || \ ((SOURCE) == TIM_TRGOSource_Update) || \ ((SOURCE) == TIM_TRGOSource_OC1) || \ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ ((SOURCE) == TIM_TRGOSource_OC4Ref)) /** * @} */ /** @defgroup TIM_Slave_Mode * @{ */ #define TIM_SlaveMode_Reset ((uint16_t)0x0004) #define TIM_SlaveMode_Gated ((uint16_t)0x0005) #define TIM_SlaveMode_Trigger ((uint16_t)0x0006) #define TIM_SlaveMode_External1 ((uint16_t)0x0007) #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ ((MODE) == TIM_SlaveMode_Gated) || \ ((MODE) == TIM_SlaveMode_Trigger) || \ ((MODE) == TIM_SlaveMode_External1)) /** * @} */ /** @defgroup TIM_Master_Slave_Mode * @{ */ #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ ((STATE) == TIM_MasterSlaveMode_Disable)) /** * @} */ /** @defgroup TIM_Remap * @{ */ #define TIM2_TIM8_TRGO ((uint16_t)0x0000) #define TIM2_ETH_PTP ((uint16_t)0x0400) #define TIM2_USBFS_SOF ((uint16_t)0x0800) #define TIM2_USBHS_SOF ((uint16_t)0x0C00) #define TIM5_GPIO ((uint16_t)0x0000) #define TIM5_LSI ((uint16_t)0x0040) #define TIM5_LSE ((uint16_t)0x0080) #define TIM5_RTC ((uint16_t)0x00C0) #define TIM11_GPIO ((uint16_t)0x0000) #define TIM11_HSE ((uint16_t)0x0002) #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\ ((TIM_REMAP) == TIM2_ETH_PTP)||\ ((TIM_REMAP) == TIM2_USBFS_SOF)||\ ((TIM_REMAP) == TIM2_USBHS_SOF)||\ ((TIM_REMAP) == TIM5_GPIO)||\ ((TIM_REMAP) == TIM5_LSI)||\ ((TIM_REMAP) == TIM5_LSE)||\ ((TIM_REMAP) == TIM5_RTC)||\ ((TIM_REMAP) == TIM11_GPIO)||\ ((TIM_REMAP) == TIM11_HSE)) /** * @} */ /** @defgroup TIM_Flags * @{ */ #define TIM_FLAG_Update ((uint16_t)0x0001) #define TIM_FLAG_CC1 ((uint16_t)0x0002) #define TIM_FLAG_CC2 ((uint16_t)0x0004) #define TIM_FLAG_CC3 ((uint16_t)0x0008) #define TIM_FLAG_CC4 ((uint16_t)0x0010) #define TIM_FLAG_COM ((uint16_t)0x0020) #define TIM_FLAG_Trigger ((uint16_t)0x0040) #define TIM_FLAG_Break ((uint16_t)0x0080) #define TIM_FLAG_CC1OF ((uint16_t)0x0200) #define TIM_FLAG_CC2OF ((uint16_t)0x0400) #define TIM_FLAG_CC3OF ((uint16_t)0x0800) #define TIM_FLAG_CC4OF ((uint16_t)0x1000) #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ ((FLAG) == TIM_FLAG_CC1) || \ ((FLAG) == TIM_FLAG_CC2) || \ ((FLAG) == TIM_FLAG_CC3) || \ ((FLAG) == TIM_FLAG_CC4) || \ ((FLAG) == TIM_FLAG_COM) || \ ((FLAG) == TIM_FLAG_Trigger) || \ ((FLAG) == TIM_FLAG_Break) || \ ((FLAG) == TIM_FLAG_CC1OF) || \ ((FLAG) == TIM_FLAG_CC2OF) || \ ((FLAG) == TIM_FLAG_CC3OF) || \ ((FLAG) == TIM_FLAG_CC4OF)) /** * @} */ /** @defgroup TIM_Input_Capture_Filer_Value * @{ */ #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) /** * @} */ /** @defgroup TIM_External_Trigger_Filter * @{ */ #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) /** * @} */ /** @defgroup TIM_Legacy * @{ */ #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* TimeBase management ********************************************************/ void TIM_DeInit(TIM_TypeDef* TIMx); void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); /* Output Compare management **************************************************/ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); /* Input Capture management ***************************************************/ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); /* Advanced-control timers (TIM1 and TIM8) specific features ******************/ void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); /* Interrupts, DMA and flags management ***************************************/ void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); /* Clocks management **********************************************************/ void TIM_InternalClockConfig(TIM_TypeDef* TIMx); void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter); void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); /* Synchronization management *************************************************/ void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); /* Specific interface management **********************************************/ void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); /* Specific remapping management **********************************************/ void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); #ifdef __cplusplus } #endif #endif /*__STM32F4xx_TIM_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h ================================================ /** ****************************************************************************** * @file stm32f4xx_usart.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the USART * firmware library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_USART_H #define __STM32F4xx_USART_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup USART * @{ */ /* Exported types ------------------------------------------------------------*/ /** * @brief USART Init Structure definition */ typedef struct { uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. The baud rate is computed using the following formula: - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate))) - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref USART_Word_Length */ uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. This parameter can be a value of @ref USART_Stop_Bits */ uint16_t USART_Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref USART_Parity @note When parity is enabled, the computed parity is inserted at the MSB position of the transmitted data (9th bit when the word length is set to 9 data bits; 8th bit when the word length is set to 8 data bits). */ uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. This parameter can be a value of @ref USART_Mode */ uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled or disabled. This parameter can be a value of @ref USART_Hardware_Flow_Control */ } USART_InitTypeDef; /** * @brief USART Clock Init Structure definition */ typedef struct { uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. This parameter can be a value of @ref USART_Clock */ uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock. This parameter can be a value of @ref USART_Clock_Polarity */ uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. This parameter can be a value of @ref USART_Clock_Phase */ uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref USART_Last_Bit */ } USART_ClockInitTypeDef; /* Exported constants --------------------------------------------------------*/ /** @defgroup USART_Exported_Constants * @{ */ #define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ ((PERIPH) == USART2) || \ ((PERIPH) == USART3) || \ ((PERIPH) == UART4) || \ ((PERIPH) == UART5) || \ ((PERIPH) == USART6) || \ ((PERIPH) == UART7) || \ ((PERIPH) == UART8)) #define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \ ((PERIPH) == USART2) || \ ((PERIPH) == USART3) || \ ((PERIPH) == USART6)) /** @defgroup USART_Word_Length * @{ */ #define USART_WordLength_8b ((uint16_t)0x0000) #define USART_WordLength_9b ((uint16_t)0x1000) #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ ((LENGTH) == USART_WordLength_9b)) /** * @} */ /** @defgroup USART_Stop_Bits * @{ */ #define USART_StopBits_1 ((uint16_t)0x0000) #define USART_StopBits_0_5 ((uint16_t)0x1000) #define USART_StopBits_2 ((uint16_t)0x2000) #define USART_StopBits_1_5 ((uint16_t)0x3000) #define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ ((STOPBITS) == USART_StopBits_0_5) || \ ((STOPBITS) == USART_StopBits_2) || \ ((STOPBITS) == USART_StopBits_1_5)) /** * @} */ /** @defgroup USART_Parity * @{ */ #define USART_Parity_No ((uint16_t)0x0000) #define USART_Parity_Even ((uint16_t)0x0400) #define USART_Parity_Odd ((uint16_t)0x0600) #define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ ((PARITY) == USART_Parity_Even) || \ ((PARITY) == USART_Parity_Odd)) /** * @} */ /** @defgroup USART_Mode * @{ */ #define USART_Mode_Rx ((uint16_t)0x0004) #define USART_Mode_Tx ((uint16_t)0x0008) #define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) /** * @} */ /** @defgroup USART_Hardware_Flow_Control * @{ */ #define USART_HardwareFlowControl_None ((uint16_t)0x0000) #define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) #define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) #define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) #define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ (((CONTROL) == USART_HardwareFlowControl_None) || \ ((CONTROL) == USART_HardwareFlowControl_RTS) || \ ((CONTROL) == USART_HardwareFlowControl_CTS) || \ ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) /** * @} */ /** @defgroup USART_Clock * @{ */ #define USART_Clock_Disable ((uint16_t)0x0000) #define USART_Clock_Enable ((uint16_t)0x0800) #define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ ((CLOCK) == USART_Clock_Enable)) /** * @} */ /** @defgroup USART_Clock_Polarity * @{ */ #define USART_CPOL_Low ((uint16_t)0x0000) #define USART_CPOL_High ((uint16_t)0x0400) #define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) /** * @} */ /** @defgroup USART_Clock_Phase * @{ */ #define USART_CPHA_1Edge ((uint16_t)0x0000) #define USART_CPHA_2Edge ((uint16_t)0x0200) #define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) /** * @} */ /** @defgroup USART_Last_Bit * @{ */ #define USART_LastBit_Disable ((uint16_t)0x0000) #define USART_LastBit_Enable ((uint16_t)0x0100) #define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ ((LASTBIT) == USART_LastBit_Enable)) /** * @} */ /** @defgroup USART_Interrupt_definition * @{ */ #define USART_IT_PE ((uint16_t)0x0028) #define USART_IT_TXE ((uint16_t)0x0727) #define USART_IT_TC ((uint16_t)0x0626) #define USART_IT_RXNE ((uint16_t)0x0525) #define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */ #define USART_IT_IDLE ((uint16_t)0x0424) #define USART_IT_LBD ((uint16_t)0x0846) #define USART_IT_CTS ((uint16_t)0x096A) #define USART_IT_ERR ((uint16_t)0x0060) #define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */ #define USART_IT_NE ((uint16_t)0x0260) #define USART_IT_FE ((uint16_t)0x0160) /** @defgroup USART_Legacy * @{ */ #define USART_IT_ORE USART_IT_ORE_ER /** * @} */ #define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) #define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \ ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) #define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) /** * @} */ /** @defgroup USART_DMA_Requests * @{ */ #define USART_DMAReq_Tx ((uint16_t)0x0080) #define USART_DMAReq_Rx ((uint16_t)0x0040) #define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) /** * @} */ /** @defgroup USART_WakeUp_methods * @{ */ #define USART_WakeUp_IdleLine ((uint16_t)0x0000) #define USART_WakeUp_AddressMark ((uint16_t)0x0800) #define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ ((WAKEUP) == USART_WakeUp_AddressMark)) /** * @} */ /** @defgroup USART_LIN_Break_Detection_Length * @{ */ #define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) #define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) #define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ (((LENGTH) == USART_LINBreakDetectLength_10b) || \ ((LENGTH) == USART_LINBreakDetectLength_11b)) /** * @} */ /** @defgroup USART_IrDA_Low_Power * @{ */ #define USART_IrDAMode_LowPower ((uint16_t)0x0004) #define USART_IrDAMode_Normal ((uint16_t)0x0000) #define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ ((MODE) == USART_IrDAMode_Normal)) /** * @} */ /** @defgroup USART_Flags * @{ */ #define USART_FLAG_CTS ((uint16_t)0x0200) #define USART_FLAG_LBD ((uint16_t)0x0100) #define USART_FLAG_TXE ((uint16_t)0x0080) #define USART_FLAG_TC ((uint16_t)0x0040) #define USART_FLAG_RXNE ((uint16_t)0x0020) #define USART_FLAG_IDLE ((uint16_t)0x0010) #define USART_FLAG_ORE ((uint16_t)0x0008) #define USART_FLAG_NE ((uint16_t)0x0004) #define USART_FLAG_FE ((uint16_t)0x0002) #define USART_FLAG_PE ((uint16_t)0x0001) #define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) #define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) #define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001)) #define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) #define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the USART configuration to the default reset state ***/ void USART_DeInit(USART_TypeDef* USARTx); /* Initialization and Configuration functions *********************************/ void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); void USART_StructInit(USART_InitTypeDef* USART_InitStruct); void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Data transfers functions ***************************************************/ void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); uint16_t USART_ReceiveData(USART_TypeDef* USARTx); /* Multi-Processor Communication functions ************************************/ void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* LIN mode functions *********************************************************/ void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); void USART_SendBreak(USART_TypeDef* USARTx); /* Half-duplex mode function **************************************************/ void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Smartcard mode functions ***************************************************/ void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); /* IrDA mode functions ********************************************************/ void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); /* DMA transfers management functions *****************************************/ void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); /* Interrupts and flags management functions **********************************/ void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_USART_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h ================================================ /** ****************************************************************************** * @file stm32f4xx_wwdg.h * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file contains all the functions prototypes for the WWDG firmware * library. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32F4xx_WWDG_H #define __STM32F4xx_WWDG_H #ifdef __cplusplus extern "C" { #endif /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @addtogroup WWDG * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup WWDG_Exported_Constants * @{ */ /** @defgroup WWDG_Prescaler * @{ */ #define WWDG_Prescaler_1 ((uint32_t)0x00000000) #define WWDG_Prescaler_2 ((uint32_t)0x00000080) #define WWDG_Prescaler_4 ((uint32_t)0x00000100) #define WWDG_Prescaler_8 ((uint32_t)0x00000180) #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ ((PRESCALER) == WWDG_Prescaler_2) || \ ((PRESCALER) == WWDG_Prescaler_4) || \ ((PRESCALER) == WWDG_Prescaler_8)) #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) /** * @} */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Function used to set the WWDG configuration to the default reset state ****/ void WWDG_DeInit(void); /* Prescaler, Refresh window and Counter configuration functions **************/ void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); void WWDG_SetWindowValue(uint8_t WindowValue); void WWDG_EnableIT(void); void WWDG_SetCounter(uint8_t Counter); /* WWDG activation function ***************************************************/ void WWDG_Enable(uint8_t Counter); /* Interrupts and flags management functions **********************************/ FlagStatus WWDG_GetFlagStatus(void); void WWDG_ClearFlag(void); #ifdef __cplusplus } #endif #endif /* __STM32F4xx_WWDG_H */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c ================================================ /** ****************************************************************************** * @file misc.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides all the miscellaneous firmware functions (add-on * to CMSIS functions). * * @verbatim * * =================================================================== * How to configure Interrupts using driver * =================================================================== * * This section provide functions allowing to configure the NVIC interrupts (IRQ). * The Cortex-M4 exceptions are managed by CMSIS functions. * * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() * function according to the following table. * The table below gives the allowed values of the pre-emption priority and subpriority according * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function * ========================================================================================================================== * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description * ========================================================================================================================== * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority * | | | 4 bits for subpriority * -------------------------------------------------------------------------------------------------------------------------- * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority * | | | 3 bits for subpriority * -------------------------------------------------------------------------------------------------------------------------- * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority * | | | 2 bits for subpriority * -------------------------------------------------------------------------------------------------------------------------- * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority * | | | 1 bits for subpriority * -------------------------------------------------------------------------------------------------------------------------- * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority * | | | 0 bits for subpriority * ========================================================================================================================== * * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init() * * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * * @note IRQ priority order (sorted by highest to lowest priority): * - Lowest pre-emption priority * - Lowest subpriority * - Lowest hardware priority (IRQ number) * * @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "misc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup MISC * @brief MISC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup MISC_Private_Functions * @{ */ /** * @brief Configures the priority grouping: pre-emption priority and subpriority. * @param NVIC_PriorityGroup: specifies the priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority * 4 bits for subpriority * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority * 3 bits for subpriority * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority * 2 bits for subpriority * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority * 1 bits for subpriority * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority * 0 bits for subpriority * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) { /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; } /** * @brief Initializes the NVIC peripheral according to the specified * parameters in the NVIC_InitStruct. * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() * function should be called before. * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains * the configuration information for the specified NVIC peripheral. * @retval None */ void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) { uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) { /* Compute the Corresponding IRQ Priority --------------------------------*/ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; tmppre = (0x4 - tmppriority); tmpsub = tmpsub >> tmppriority; tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub); tmppriority = tmppriority << 0x04; NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; /* Enable the Selected IRQ Channels --------------------------------------*/ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); } else { /* Disable the Selected IRQ Channels -------------------------------------*/ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); } } /** * @brief Sets the vector table location and Offset. * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. * This parameter can be one of the following values: * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM. * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH. * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. * @retval None */ void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) { /* Check the parameters */ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); assert_param(IS_NVIC_OFFSET(Offset)); SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); } /** * @brief Selects the condition for the system to enter low power mode. * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. * This parameter can be one of the following values: * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. * @retval None */ void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_NVIC_LP(LowPowerMode)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { SCB->SCR |= LowPowerMode; } else { SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); } } /** * @brief Configures the SysTick clock source. * @param SysTick_CLKSource: specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. * @retval None */ void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) { /* Check the parameters */ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); if (SysTick_CLKSource == SysTick_CLKSource_HCLK) { SysTick->CTRL |= SysTick_CLKSource_HCLK; } else { SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; } } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c ================================================ /** ****************************************************************************** * @file stm32f4xx_adc.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) peripheral: * + Initialization and Configuration (in addition to ADC multi mode * selection) * + Analog Watchdog configuration * + Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT * management * + Regular Channels Configuration * + Regular Channels DMA Configuration * + Injected channels Configuration * + Interrupts and flags management * @verbatim =============================================================================== ##### How to use this driver ##### =============================================================================== [..] (#) Enable the ADC interface clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE); (#) ADC pins configuration (++) Enable the clock for the ADC GPIOs using the following function: RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); (++) Configure these ADC pins in analog mode using GPIO_Init(); (#) Configure the ADC Prescaler, conversion resolution and data alignment using the ADC_Init() function. (#) Activate the ADC peripheral using ADC_Cmd() function. *** Regular channels group configuration *** ============================================ [..] (+) To configure the ADC regular channels group features, use ADC_Init() and ADC_RegularChannelConfig() functions. (+) To activate the continuous mode, use the ADC_continuousModeCmd() function. (+) To configurate and activate the Discontinuous mode, use the ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. (+) To read the ADC converted values, use the ADC_GetConversionValue() function. *** Multi mode ADCs Regular channels configuration *** ====================================================== [..] (+) Refer to "Regular channels group configuration" description to configure the ADC1, ADC2 and ADC3 regular channels. (+) Select the Multi mode ADC regular channels features (dual or triple mode) using ADC_CommonInit() function and configure the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd() functions. (+) Read the ADCs converted values using the ADC_GetMultiModeConversionValue() function. *** DMA for Regular channels group features configuration *** ============================================================= [..] (+) To enable the DMA mode for regular channels group, use the ADC_DMACmd() function. (+) To enable the generation of DMA requests continuously at the end of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() function. *** Injected channels group configuration *** ============================================= [..] (+) To configure the ADC Injected channels group features, use ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig() functions. (+) To activate the continuous mode, use the ADC_continuousModeCmd() function. (+) To activate the Injected Discontinuous mode, use the ADC_InjectedDiscModeCmd() function. (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() function. (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue() function. @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_adc.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup ADC * @brief ADC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* ADC DISCNUM mask */ #define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF) /* ADC AWDCH mask */ #define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) /* ADC Analog watchdog enable mode mask */ #define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF) /* CR1 register Mask */ #define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) /* ADC EXTEN mask */ #define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF) /* ADC JEXTEN mask */ #define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF) /* ADC JEXTSEL mask */ #define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF) /* CR2 register Mask */ #define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD) /* ADC SQx mask */ #define SQR3_SQ_SET ((uint32_t)0x0000001F) #define SQR2_SQ_SET ((uint32_t)0x0000001F) #define SQR1_SQ_SET ((uint32_t)0x0000001F) /* ADC L Mask */ #define SQR1_L_RESET ((uint32_t)0xFF0FFFFF) /* ADC JSQx mask */ #define JSQR_JSQ_SET ((uint32_t)0x0000001F) /* ADC JL mask */ #define JSQR_JL_SET ((uint32_t)0x00300000) #define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) /* ADC SMPx mask */ #define SMPR1_SMP_SET ((uint32_t)0x00000007) #define SMPR2_SMP_SET ((uint32_t)0x00000007) /* ADC JDRx registers offset */ #define JDR_OFFSET ((uint8_t)0x28) /* ADC CDR register base address */ #define CDR_ADDRESS ((uint32_t)0x40012308) /* ADC CCR register Mask */ #define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup ADC_Private_Functions * @{ */ /** @defgroup ADC_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the ADC Prescaler (+) ADC Conversion Resolution (12bit..6bit) (+) Scan Conversion Mode (multichannel or one channel) for regular group (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for regular group (+) External trigger Edge and source of regular group, (+) Converted data alignment (left or right) (+) The number of ADC conversions that will be done using the sequencer for regular channel group (+) Multi ADC mode selection (+) Direct memory access mode selection for multi ADC mode (+) Delay between 2 sampling phases (used in dual or triple interleaved modes) (+) Enable or disable the ADC peripheral @endverbatim * @{ */ /** * @brief Deinitializes all ADCs peripherals registers to their default reset * values. * @param None * @retval None */ void ADC_DeInit(void) { /* Enable all ADCs reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE); /* Release all ADCs from reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE); } /** * @brief Initializes the ADCx peripheral according to the specified parameters * in the ADC_InitStruct. * @note This function is used to configure the global features of the ADC ( * Resolution and Data Alignment), however, the rest of the configuration * parameters are specific to the regular channels group (scan mode * activation, continuous mode activation, External trigger source and * edge, number of conversion in the regular channels group sequencer). * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains * the configuration information for the specified ADC peripheral. * @retval None */ void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) { uint32_t tmpreg1 = 0; uint8_t tmpreg2 = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion)); /*---------------------------- ADCx CR1 Configuration -----------------*/ /* Get the ADCx CR1 value */ tmpreg1 = ADCx->CR1; /* Clear RES and SCAN bits */ tmpreg1 &= CR1_CLEAR_MASK; /* Configure ADCx: scan conversion mode and resolution */ /* Set SCAN bit according to ADC_ScanConvMode value */ /* Set RES bit according to ADC_Resolution value */ tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \ ADC_InitStruct->ADC_Resolution); /* Write to ADCx CR1 */ ADCx->CR1 = tmpreg1; /*---------------------------- ADCx CR2 Configuration -----------------*/ /* Get the ADCx CR2 value */ tmpreg1 = ADCx->CR2; /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */ tmpreg1 &= CR2_CLEAR_MASK; /* Configure ADCx: external trigger event and edge, data alignment and continuous conversion mode */ /* Set ALIGN bit according to ADC_DataAlign value */ /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ /* Set CONT bit according to ADC_ContinuousConvMode value */ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \ ADC_InitStruct->ADC_ExternalTrigConv | ADC_InitStruct->ADC_ExternalTrigConvEdge | \ ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); /* Write to ADCx CR2 */ ADCx->CR2 = tmpreg1; /*---------------------------- ADCx SQR1 Configuration -----------------*/ /* Get the ADCx SQR1 value */ tmpreg1 = ADCx->SQR1; /* Clear L bits */ tmpreg1 &= SQR1_L_RESET; /* Configure ADCx: regular channel sequence length */ /* Set L bits according to ADC_NbrOfConversion value */ tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1); tmpreg1 |= ((uint32_t)tmpreg2 << 20); /* Write to ADCx SQR1 */ ADCx->SQR1 = tmpreg1; } /** * @brief Fills each ADC_InitStruct member with its default value. * @note This function is used to initialize the global features of the ADC ( * Resolution and Data Alignment), however, the rest of the configuration * parameters are specific to the regular channels group (scan mode * activation, continuous mode activation, External trigger source and * edge, number of conversion in the regular channels group sequencer). * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will * be initialized. * @retval None */ void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) { /* Initialize the ADC_Mode member */ ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; /* initialize the ADC_ScanConvMode member */ ADC_InitStruct->ADC_ScanConvMode = DISABLE; /* Initialize the ADC_ContinuousConvMode member */ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; /* Initialize the ADC_ExternalTrigConvEdge member */ ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; /* Initialize the ADC_ExternalTrigConv member */ ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; /* Initialize the ADC_DataAlign member */ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; /* Initialize the ADC_NbrOfConversion member */ ADC_InitStruct->ADC_NbrOfConversion = 1; } /** * @brief Initializes the ADCs peripherals according to the specified parameters * in the ADC_CommonInitStruct. * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure * that contains the configuration information for All ADCs peripherals. * @retval None */ void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) { uint32_t tmpreg1 = 0; /* Check the parameters */ assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode)); assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler)); assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode)); assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay)); /*---------------------------- ADC CCR Configuration -----------------*/ /* Get the ADC CCR value */ tmpreg1 = ADC->CCR; /* Clear MULTI, DELAY, DMA and ADCPRE bits */ tmpreg1 &= CR_CLEAR_MASK; /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler, and DMA access mode for multimode */ /* Set MULTI bits according to ADC_Mode value */ /* Set ADCPRE bits according to ADC_Prescaler value */ /* Set DMA bits according to ADC_DMAAccessMode value */ /* Set DELAY bits according to ADC_TwoSamplingDelay value */ tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode | ADC_CommonInitStruct->ADC_Prescaler | ADC_CommonInitStruct->ADC_DMAAccessMode | ADC_CommonInitStruct->ADC_TwoSamplingDelay); /* Write to ADC CCR */ ADC->CCR = tmpreg1; } /** * @brief Fills each ADC_CommonInitStruct member with its default value. * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure * which will be initialized. * @retval None */ void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) { /* Initialize the ADC_Mode member */ ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent; /* initialize the ADC_Prescaler member */ ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2; /* Initialize the ADC_DMAAccessMode member */ ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; /* Initialize the ADC_TwoSamplingDelay member */ ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; } /** * @brief Enables or disables the specified ADC peripheral. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the ADCx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set the ADON bit to wake up the ADC from power down mode */ ADCx->CR2 |= (uint32_t)ADC_CR2_ADON; } else { /* Disable the selected ADC peripheral */ ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON); } } /** * @} */ /** @defgroup ADC_Group2 Analog Watchdog configuration functions * @brief Analog Watchdog configuration functions * @verbatim =============================================================================== ##### Analog Watchdog configuration functions ##### =============================================================================== [..] This section provides functions allowing to configure the Analog Watchdog (AWD) feature in the ADC. [..] A typical configuration Analog Watchdog is done following these steps : (#) the ADC guarded channel(s) is (are) selected using the ADC_AnalogWatchdogSingleChannelConfig() function. (#) The Analog watchdog lower and higher threshold are configured using the ADC_AnalogWatchdogThresholdsConfig() function. (#) The Analog watchdog is enabled and configured to enable the check, on one or more channels, using the ADC_AnalogWatchdogCmd() function. @endverbatim * @{ */ /** * @brief Enables or disables the analog watchdog on single/all regular or * injected channels * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. * This parameter can be one of the following values: * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog * @retval None */ void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); /* Get the old register value */ tmpreg = ADCx->CR1; /* Clear AWDEN, JAWDEN and AWDSGL bits */ tmpreg &= CR1_AWDMode_RESET; /* Set the analog watchdog enable mode */ tmpreg |= ADC_AnalogWatchdog; /* Store the new register value */ ADCx->CR1 = tmpreg; } /** * @brief Configures the high and low thresholds of the analog watchdog. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param HighThreshold: the ADC analog watchdog High threshold value. * This parameter must be a 12-bit value. * @param LowThreshold: the ADC analog watchdog Low threshold value. * This parameter must be a 12-bit value. * @retval None */ void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_THRESHOLD(HighThreshold)); assert_param(IS_ADC_THRESHOLD(LowThreshold)); /* Set the ADCx high threshold */ ADCx->HTR = HighThreshold; /* Set the ADCx low threshold */ ADCx->LTR = LowThreshold; } /** * @brief Configures the analog watchdog guarded single channel * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_Channel: the ADC channel to configure for the analog watchdog. * This parameter can be one of the following values: * @arg ADC_Channel_0: ADC Channel0 selected * @arg ADC_Channel_1: ADC Channel1 selected * @arg ADC_Channel_2: ADC Channel2 selected * @arg ADC_Channel_3: ADC Channel3 selected * @arg ADC_Channel_4: ADC Channel4 selected * @arg ADC_Channel_5: ADC Channel5 selected * @arg ADC_Channel_6: ADC Channel6 selected * @arg ADC_Channel_7: ADC Channel7 selected * @arg ADC_Channel_8: ADC Channel8 selected * @arg ADC_Channel_9: ADC Channel9 selected * @arg ADC_Channel_10: ADC Channel10 selected * @arg ADC_Channel_11: ADC Channel11 selected * @arg ADC_Channel_12: ADC Channel12 selected * @arg ADC_Channel_13: ADC Channel13 selected * @arg ADC_Channel_14: ADC Channel14 selected * @arg ADC_Channel_15: ADC Channel15 selected * @arg ADC_Channel_16: ADC Channel16 selected * @arg ADC_Channel_17: ADC Channel17 selected * @arg ADC_Channel_18: ADC Channel18 selected * @retval None */ void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_CHANNEL(ADC_Channel)); /* Get the old register value */ tmpreg = ADCx->CR1; /* Clear the Analog watchdog channel select bits */ tmpreg &= CR1_AWDCH_RESET; /* Set the Analog watchdog channel */ tmpreg |= ADC_Channel; /* Store the new register value */ ADCx->CR1 = tmpreg; } /** * @} */ /** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal) * and VBAT (Voltage BATtery) management functions * @brief Temperature Sensor, Vrefint and VBAT management functions * @verbatim =============================================================================== ##### Temperature Sensor, Vrefint and VBAT management functions ##### =============================================================================== [..] This section provides functions allowing to enable/ disable the internal connections between the ADC and the Temperature Sensor, the Vrefint and the Vbat sources. [..] A typical configuration to get the Temperature sensor and Vrefint channels voltages is done following these steps : (#) Enable the internal connection of Temperature sensor and Vrefint sources with the ADC channels using ADC_TempSensorVrefintCmd() function. (#) Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions (#) Get the voltage values, using ADC_GetConversionValue() or ADC_GetInjectedConversionValue(). [..] A typical configuration to get the VBAT channel voltage is done following these steps : (#) Enable the internal connection of VBAT source with the ADC channel using ADC_VBATCmd() function. (#) Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions (#) Get the voltage value, using ADC_GetConversionValue() or ADC_GetInjectedConversionValue(). @endverbatim * @{ */ /** * @brief Enables or disables the temperature sensor and Vrefint channels. * @param NewState: new state of the temperature sensor and Vrefint channels. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_TempSensorVrefintCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the temperature sensor and Vrefint channel*/ ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE; } else { /* Disable the temperature sensor and Vrefint channel*/ ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE); } } /** * @brief Enables or disables the VBAT (Voltage Battery) channel. * * @note the Battery voltage measured is equal to VBAT/2 on STM32F40xx and * STM32F41xx devices and equal to VBAT/4 on STM32F42xx and STM32F43xx devices * * @param NewState: new state of the VBAT channel. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_VBATCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the VBAT channel*/ ADC->CCR |= (uint32_t)ADC_CCR_VBATE; } else { /* Disable the VBAT channel*/ ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE); } } /** * @} */ /** @defgroup ADC_Group4 Regular Channels Configuration functions * @brief Regular Channels Configuration functions * @verbatim =============================================================================== ##### Regular Channels Configuration functions ##### =============================================================================== [..] This section provides functions allowing to manage the ADC's regular channels, it is composed of 2 sub sections : (#) Configuration and management functions for regular channels: This subsection provides functions allowing to configure the ADC regular channels : (++) Configure the rank in the regular group sequencer for each channel (++) Configure the sampling time for each channel (++) select the conversion Trigger for regular channels (++) select the desired EOC event behavior configuration (++) Activate the continuous Mode (*) (++) Activate the Discontinuous Mode -@@- Please Note that the following features for regular channels are configurated using the ADC_Init() function : (+@@) scan mode activation (+@@) continuous mode activation (**) (+@@) External trigger source (+@@) External trigger edge (+@@) number of conversion in the regular channels group sequencer. -@@- (*) and (**) are performing the same configuration (#) Get the conversion data: This subsection provides an important function in the ADC peripheral since it returns the converted data of the current regular channel. When the Conversion value is read, the EOC Flag is automatically cleared. -@- For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions results data (in the selected multi mode) can be returned in the same time using ADC_GetMultiModeConversionValue() function. @endverbatim * @{ */ /** * @brief Configures for the selected ADC regular channel its corresponding * rank in the sequencer and its sample time. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_Channel: the ADC channel to configure. * This parameter can be one of the following values: * @arg ADC_Channel_0: ADC Channel0 selected * @arg ADC_Channel_1: ADC Channel1 selected * @arg ADC_Channel_2: ADC Channel2 selected * @arg ADC_Channel_3: ADC Channel3 selected * @arg ADC_Channel_4: ADC Channel4 selected * @arg ADC_Channel_5: ADC Channel5 selected * @arg ADC_Channel_6: ADC Channel6 selected * @arg ADC_Channel_7: ADC Channel7 selected * @arg ADC_Channel_8: ADC Channel8 selected * @arg ADC_Channel_9: ADC Channel9 selected * @arg ADC_Channel_10: ADC Channel10 selected * @arg ADC_Channel_11: ADC Channel11 selected * @arg ADC_Channel_12: ADC Channel12 selected * @arg ADC_Channel_13: ADC Channel13 selected * @arg ADC_Channel_14: ADC Channel14 selected * @arg ADC_Channel_15: ADC Channel15 selected * @arg ADC_Channel_16: ADC Channel16 selected * @arg ADC_Channel_17: ADC Channel17 selected * @arg ADC_Channel_18: ADC Channel18 selected * @param Rank: The rank in the regular group sequencer. * This parameter must be between 1 to 16. * @param ADC_SampleTime: The sample time value to be set for the selected channel. * This parameter can be one of the following values: * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles * @retval None */ void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) { uint32_t tmpreg1 = 0, tmpreg2 = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_CHANNEL(ADC_Channel)); assert_param(IS_ADC_REGULAR_RANK(Rank)); assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ if (ADC_Channel > ADC_Channel_9) { /* Get the old register value */ tmpreg1 = ADCx->SMPR1; /* Calculate the mask to clear */ tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10)); /* Clear the old sample time */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); /* Set the new sample time */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SMPR1 = tmpreg1; } else /* ADC_Channel include in ADC_Channel_[0..9] */ { /* Get the old register value */ tmpreg1 = ADCx->SMPR2; /* Calculate the mask to clear */ tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); /* Clear the old sample time */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); /* Set the new sample time */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SMPR2 = tmpreg1; } /* For Rank 1 to 6 */ if (Rank < 7) { /* Get the old register value */ tmpreg1 = ADCx->SQR3; /* Calculate the mask to clear */ tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1)); /* Clear the old SQx bits for the selected rank */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); /* Set the SQx bits for the selected rank */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SQR3 = tmpreg1; } /* For Rank 7 to 12 */ else if (Rank < 13) { /* Get the old register value */ tmpreg1 = ADCx->SQR2; /* Calculate the mask to clear */ tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7)); /* Clear the old SQx bits for the selected rank */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); /* Set the SQx bits for the selected rank */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SQR2 = tmpreg1; } /* For Rank 13 to 16 */ else { /* Get the old register value */ tmpreg1 = ADCx->SQR1; /* Calculate the mask to clear */ tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13)); /* Clear the old SQx bits for the selected rank */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); /* Set the SQx bits for the selected rank */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SQR1 = tmpreg1; } } /** * @brief Enables the selected ADC software start conversion of the regular channels. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @retval None */ void ADC_SoftwareStartConv(ADC_TypeDef* ADCx) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Enable the selected ADC conversion for regular group */ ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART; } /** * @brief Gets the selected ADC Software start regular conversion Status. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @retval The new state of ADC software start conversion (SET or RESET). */ FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Check the status of SWSTART bit */ if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET) { /* SWSTART bit is set */ bitstatus = SET; } else { /* SWSTART bit is reset */ bitstatus = RESET; } /* Return the SWSTART bit status */ return bitstatus; } /** * @brief Enables or disables the EOC on each regular channel conversion * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC EOC flag rising * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC EOC rising on each regular channel conversion */ ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS; } else { /* Disable the selected ADC EOC rising on each regular channel conversion */ ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS); } } /** * @brief Enables or disables the ADC continuous conversion mode * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC continuous conversion mode * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC continuous conversion mode */ ADCx->CR2 |= (uint32_t)ADC_CR2_CONT; } else { /* Disable the selected ADC continuous conversion mode */ ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT); } } /** * @brief Configures the discontinuous mode for the selected ADC regular group * channel. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param Number: specifies the discontinuous mode regular channel count value. * This number must be between 1 and 8. * @retval None */ void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) { uint32_t tmpreg1 = 0; uint32_t tmpreg2 = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); /* Get the old register value */ tmpreg1 = ADCx->CR1; /* Clear the old discontinuous mode channel count */ tmpreg1 &= CR1_DISCNUM_RESET; /* Set the discontinuous mode channel count */ tmpreg2 = Number - 1; tmpreg1 |= tmpreg2 << 13; /* Store the new register value */ ADCx->CR1 = tmpreg1; } /** * @brief Enables or disables the discontinuous mode on regular group channel * for the specified ADC * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC discontinuous mode on * regular group channel. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC regular discontinuous mode */ ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN; } else { /* Disable the selected ADC regular discontinuous mode */ ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN); } } /** * @brief Returns the last ADCx conversion result data for regular channel. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @retval The Data conversion value. */ uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Return the selected ADC conversion value */ return (uint16_t) ADCx->DR; } /** * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results * data in the selected multi mode. * @param None * @retval The Data conversion value. * @note In dual mode, the value returned by this function is as following * Data[15:0] : these bits contain the regular data of ADC1. * Data[31:16]: these bits contain the regular data of ADC2. * @note In triple mode, the value returned by this function is as following * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2. * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3. */ uint32_t ADC_GetMultiModeConversionValue(void) { /* Return the multi mode conversion value */ return (*(__IO uint32_t *) CDR_ADDRESS); } /** * @} */ /** @defgroup ADC_Group5 Regular Channels DMA Configuration functions * @brief Regular Channels DMA Configuration functions * @verbatim =============================================================================== ##### Regular Channels DMA Configuration functions ##### =============================================================================== [..] This section provides functions allowing to configure the DMA for ADC regular channels. Since converted regular channel values are stored into a unique data register, it is useful to use DMA for conversion of more than one regular channel. This avoids the loss of the data already stored in the ADC Data register. When the DMA mode is enabled (using the ADC_DMACmd() function), after each conversion of a regular channel, a DMA request is generated. [..] Depending on the "DMA disable selection for Independent ADC mode" configuration (using the ADC_DMARequestAfterLastTransferCmd() function), at the end of the last DMA transfer, two possibilities are allowed: (+) No new DMA request is issued to the DMA controller (feature DISABLED) (+) Requests can continue to be generated (feature ENABLED). [..] Depending on the "DMA disable selection for multi ADC mode" configuration (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), at the end of the last DMA transfer, two possibilities are allowed: (+) No new DMA request is issued to the DMA controller (feature DISABLED) (+) Requests can continue to be generated (feature ENABLED). @endverbatim * @{ */ /** * @brief Enables or disables the specified ADC DMA request. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC DMA transfer. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC DMA request */ ADCx->CR2 |= (uint32_t)ADC_CR2_DMA; } else { /* Disable the selected ADC DMA request */ ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA); } } /** * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC DMA request after last transfer. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC DMA request after last transfer */ ADCx->CR2 |= (uint32_t)ADC_CR2_DDS; } else { /* Disable the selected ADC DMA request after last transfer */ ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS); } } /** * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode * @param NewState: new state of the selected ADC DMA request after last transfer. * This parameter can be: ENABLE or DISABLE. * @note if Enabled, DMA requests are issued as long as data are converted and * DMA mode for multi ADC mode (selected using ADC_CommonInit() function * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3. * @retval None */ void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC DMA request after last transfer */ ADC->CCR |= (uint32_t)ADC_CCR_DDS; } else { /* Disable the selected ADC DMA request after last transfer */ ADC->CCR &= (uint32_t)(~ADC_CCR_DDS); } } /** * @} */ /** @defgroup ADC_Group6 Injected channels Configuration functions * @brief Injected channels Configuration functions * @verbatim =============================================================================== ##### Injected channels Configuration functions ##### =============================================================================== [..] This section provide functions allowing to configure the ADC Injected channels, it is composed of 2 sub sections : (#) Configuration functions for Injected channels: This subsection provides functions allowing to configure the ADC injected channels : (++) Configure the rank in the injected group sequencer for each channel (++) Configure the sampling time for each channel (++) Activate the Auto injected Mode (++) Activate the Discontinuous Mode (++) scan mode activation (++) External/software trigger source (++) External trigger edge (++) injected channels sequencer. (#) Get the Specified Injected channel conversion data: This subsection provides an important function in the ADC peripheral since it returns the converted data of the specific injected channel. @endverbatim * @{ */ /** * @brief Configures for the selected ADC injected channel its corresponding * rank in the sequencer and its sample time. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_Channel: the ADC channel to configure. * This parameter can be one of the following values: * @arg ADC_Channel_0: ADC Channel0 selected * @arg ADC_Channel_1: ADC Channel1 selected * @arg ADC_Channel_2: ADC Channel2 selected * @arg ADC_Channel_3: ADC Channel3 selected * @arg ADC_Channel_4: ADC Channel4 selected * @arg ADC_Channel_5: ADC Channel5 selected * @arg ADC_Channel_6: ADC Channel6 selected * @arg ADC_Channel_7: ADC Channel7 selected * @arg ADC_Channel_8: ADC Channel8 selected * @arg ADC_Channel_9: ADC Channel9 selected * @arg ADC_Channel_10: ADC Channel10 selected * @arg ADC_Channel_11: ADC Channel11 selected * @arg ADC_Channel_12: ADC Channel12 selected * @arg ADC_Channel_13: ADC Channel13 selected * @arg ADC_Channel_14: ADC Channel14 selected * @arg ADC_Channel_15: ADC Channel15 selected * @arg ADC_Channel_16: ADC Channel16 selected * @arg ADC_Channel_17: ADC Channel17 selected * @arg ADC_Channel_18: ADC Channel18 selected * @param Rank: The rank in the injected group sequencer. * This parameter must be between 1 to 4. * @param ADC_SampleTime: The sample time value to be set for the selected channel. * This parameter can be one of the following values: * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles * @retval None */ void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) { uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_CHANNEL(ADC_Channel)); assert_param(IS_ADC_INJECTED_RANK(Rank)); assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ if (ADC_Channel > ADC_Channel_9) { /* Get the old register value */ tmpreg1 = ADCx->SMPR1; /* Calculate the mask to clear */ tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10)); /* Clear the old sample time */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); /* Set the new sample time */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SMPR1 = tmpreg1; } else /* ADC_Channel include in ADC_Channel_[0..9] */ { /* Get the old register value */ tmpreg1 = ADCx->SMPR2; /* Calculate the mask to clear */ tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); /* Clear the old sample time */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set */ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); /* Set the new sample time */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->SMPR2 = tmpreg1; } /* Rank configuration */ /* Get the old register value */ tmpreg1 = ADCx->JSQR; /* Get JL value: Number = JL+1 */ tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20; /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); /* Clear the old JSQx bits for the selected rank */ tmpreg1 &= ~tmpreg2; /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); /* Set the JSQx bits for the selected rank */ tmpreg1 |= tmpreg2; /* Store the new register value */ ADCx->JSQR = tmpreg1; } /** * @brief Configures the sequencer length for injected channels * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param Length: The sequencer length. * This parameter must be a number between 1 to 4. * @retval None */ void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) { uint32_t tmpreg1 = 0; uint32_t tmpreg2 = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_INJECTED_LENGTH(Length)); /* Get the old register value */ tmpreg1 = ADCx->JSQR; /* Clear the old injected sequence length JL bits */ tmpreg1 &= JSQR_JL_RESET; /* Set the injected sequence length JL bits */ tmpreg2 = Length - 1; tmpreg1 |= tmpreg2 << 20; /* Store the new register value */ ADCx->JSQR = tmpreg1; } /** * @brief Set the injected channels conversion value offset * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_InjectedChannel: the ADC injected channel to set its offset. * This parameter can be one of the following values: * @arg ADC_InjectedChannel_1: Injected Channel1 selected * @arg ADC_InjectedChannel_2: Injected Channel2 selected * @arg ADC_InjectedChannel_3: Injected Channel3 selected * @arg ADC_InjectedChannel_4: Injected Channel4 selected * @param Offset: the offset value for the selected ADC injected channel * This parameter must be a 12bit value. * @retval None */ void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); assert_param(IS_ADC_OFFSET(Offset)); tmp = (uint32_t)ADCx; tmp += ADC_InjectedChannel; /* Set the selected injected channel data offset */ *(__IO uint32_t *) tmp = (uint32_t)Offset; } /** * @brief Configures the ADCx external trigger for injected channels conversion. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. * This parameter can be one of the following values: * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected * @retval None */ void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); /* Get the old register value */ tmpreg = ADCx->CR2; /* Clear the old external event selection for injected group */ tmpreg &= CR2_JEXTSEL_RESET; /* Set the external event selection for injected group */ tmpreg |= ADC_ExternalTrigInjecConv; /* Store the new register value */ ADCx->CR2 = tmpreg; } /** * @brief Configures the ADCx external trigger edge for injected channels conversion. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge * to start injected conversion. * This parameter can be one of the following values: * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for * injected conversion * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising * and falling edge * @retval None */ void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge)); /* Get the old register value */ tmpreg = ADCx->CR2; /* Clear the old external trigger edge for injected group */ tmpreg &= CR2_JEXTEN_RESET; /* Set the new external trigger edge for injected group */ tmpreg |= ADC_ExternalTrigInjecConvEdge; /* Store the new register value */ ADCx->CR2 = tmpreg; } /** * @brief Enables the selected ADC software start conversion of the injected channels. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @retval None */ void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Enable the selected ADC conversion for injected group */ ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART; } /** * @brief Gets the selected ADC Software start injected conversion Status. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @retval The new state of ADC software start injected conversion (SET or RESET). */ FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); /* Check the status of JSWSTART bit */ if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) { /* JSWSTART bit is set */ bitstatus = SET; } else { /* JSWSTART bit is reset */ bitstatus = RESET; } /* Return the JSWSTART bit status */ return bitstatus; } /** * @brief Enables or disables the selected ADC automatic injected group * conversion after regular one. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC auto injected conversion * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC automatic injected group conversion */ ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO; } else { /* Disable the selected ADC automatic injected group conversion */ ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO); } } /** * @brief Enables or disables the discontinuous mode for injected group * channel for the specified ADC * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param NewState: new state of the selected ADC discontinuous mode on injected * group channel. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected ADC injected discontinuous mode */ ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN; } else { /* Disable the selected ADC injected discontinuous mode */ ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN); } } /** * @brief Returns the ADC injected channel conversion result * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_InjectedChannel: the converted ADC injected channel. * This parameter can be one of the following values: * @arg ADC_InjectedChannel_1: Injected Channel1 selected * @arg ADC_InjectedChannel_2: Injected Channel2 selected * @arg ADC_InjectedChannel_3: Injected Channel3 selected * @arg ADC_InjectedChannel_4: Injected Channel4 selected * @retval The Data conversion value. */ uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); tmp = (uint32_t)ADCx; tmp += ADC_InjectedChannel + JDR_OFFSET; /* Returns the selected injected channel conversion data value */ return (uint16_t) (*(__IO uint32_t*) tmp); } /** * @} */ /** @defgroup ADC_Group7 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== [..] This section provides functions allowing to configure the ADC Interrupts and to get the status and clear flags and Interrupts pending bits. [..] Each ADC provides 4 Interrupts sources and 6 Flags which can be divided into 3 groups: *** Flags and Interrupts for ADC regular channels *** ===================================================== [..] (+) Flags : (##) ADC_FLAG_OVR : Overrun detection when regular converted data are lost (##) ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of: (+++) a regular CHANNEL conversion (+++) sequence of regular GROUP conversions . (##) ADC_FLAG_STRT: Regular channel start ==> to indicate when regular CHANNEL conversion starts. [..] (+) Interrupts : (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection event. (##) ADC_IT_EOC : specifies the interrupt source for Regular channel end of conversion event. *** Flags and Interrupts for ADC Injected channels *** ====================================================== [..] (+) Flags : (##) ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate at the end of injected GROUP conversion (##) ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when injected GROUP conversion starts. [..] (+) Interrupts : (##) ADC_IT_JEOC : specifies the interrupt source for Injected channel end of conversion event. *** General Flags and Interrupts for the ADC *** ================================================ [..] (+)Flags : (##) ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage crosses the programmed thresholds values. [..] (+) Interrupts : (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. [..] The user should identify which mode will be used in his application to manage the ADC controller events: Polling mode or Interrupt mode. [..] In the Polling Mode it is advised to use the following functions: (+) ADC_GetFlagStatus() : to check if flags events occur. (+) ADC_ClearFlag() : to clear the flags events. [..] In the Interrupt Mode it is advised to use the following functions: (+) ADC_ITConfig() : to enable or disable the interrupt source. (+) ADC_GetITStatus() : to check if Interrupt occurs. (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag). @endverbatim * @{ */ /** * @brief Enables or disables the specified ADC interrupts. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg ADC_IT_EOC: End of conversion interrupt mask * @arg ADC_IT_AWD: Analog watchdog interrupt mask * @arg ADC_IT_JEOC: End of injected conversion interrupt mask * @arg ADC_IT_OVR: Overrun interrupt enable * @param NewState: new state of the specified ADC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) { uint32_t itmask = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_ADC_IT(ADC_IT)); /* Get the ADC IT index */ itmask = (uint8_t)ADC_IT; itmask = (uint32_t)0x01 << itmask; if (NewState != DISABLE) { /* Enable the selected ADC interrupts */ ADCx->CR1 |= itmask; } else { /* Disable the selected ADC interrupts */ ADCx->CR1 &= (~(uint32_t)itmask); } } /** * @brief Checks whether the specified ADC flag is set or not. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg ADC_FLAG_AWD: Analog watchdog flag * @arg ADC_FLAG_EOC: End of conversion flag * @arg ADC_FLAG_JEOC: End of injected group conversion flag * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag * @arg ADC_FLAG_STRT: Start of regular group conversion flag * @arg ADC_FLAG_OVR: Overrun flag * @retval The new state of ADC_FLAG (SET or RESET). */ FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); /* Check the status of the specified ADC flag */ if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) { /* ADC_FLAG is set */ bitstatus = SET; } else { /* ADC_FLAG is reset */ bitstatus = RESET; } /* Return the ADC_FLAG status */ return bitstatus; } /** * @brief Clears the ADCx's pending flags. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg ADC_FLAG_AWD: Analog watchdog flag * @arg ADC_FLAG_EOC: End of conversion flag * @arg ADC_FLAG_JEOC: End of injected group conversion flag * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag * @arg ADC_FLAG_STRT: Start of regular group conversion flag * @arg ADC_FLAG_OVR: Overrun flag * @retval None */ void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) { /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); /* Clear the selected ADC flags */ ADCx->SR = ~(uint32_t)ADC_FLAG; } /** * @brief Checks whether the specified ADC interrupt has occurred or not. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_IT: specifies the ADC interrupt source to check. * This parameter can be one of the following values: * @arg ADC_IT_EOC: End of conversion interrupt mask * @arg ADC_IT_AWD: Analog watchdog interrupt mask * @arg ADC_IT_JEOC: End of injected conversion interrupt mask * @arg ADC_IT_OVR: Overrun interrupt mask * @retval The new state of ADC_IT (SET or RESET). */ ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) { ITStatus bitstatus = RESET; uint32_t itmask = 0, enablestatus = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_IT(ADC_IT)); /* Get the ADC IT index */ itmask = ADC_IT >> 8; /* Get the ADC_IT enable bit status */ enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ; /* Check the status of the specified ADC interrupt */ if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) { /* ADC_IT is set */ bitstatus = SET; } else { /* ADC_IT is reset */ bitstatus = RESET; } /* Return the ADC_IT status */ return bitstatus; } /** * @brief Clears the ADCx's interrupt pending bits. * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. * @param ADC_IT: specifies the ADC interrupt pending bit to clear. * This parameter can be one of the following values: * @arg ADC_IT_EOC: End of conversion interrupt mask * @arg ADC_IT_AWD: Analog watchdog interrupt mask * @arg ADC_IT_JEOC: End of injected conversion interrupt mask * @arg ADC_IT_OVR: Overrun interrupt mask * @retval None */ void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) { uint8_t itmask = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_PERIPH(ADCx)); assert_param(IS_ADC_IT(ADC_IT)); /* Get the ADC IT index */ itmask = (uint8_t)(ADC_IT >> 8); /* Clear the selected ADC interrupt pending bits */ ADCx->SR = ~(uint32_t)itmask; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c ================================================ /** ****************************************************************************** * @file stm32f4xx_can.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Controller area network (CAN) peripheral: * + Initialization and Configuration * + CAN Frames Transmission * + CAN Frames Reception * + Operation modes switch * + Error management * + Interrupts and flags * @verbatim =============================================================================== ##### How to use this driver ##### =============================================================================== [..] (#) Enable the CAN controller interface clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1 and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2 -@- In case you are using CAN2 only, you have to enable the CAN1 clock. (#) CAN pins configuration (++) Enable the clock for the CAN GPIOs using the following function: RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); (++) Connect the involved CAN pins to AF9 using the following function GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); (++) Configure these CAN pins in alternate function mode by calling the function GPIO_Init(); (#) Initialise and configure the CAN using CAN_Init() and CAN_FilterInit() functions. (#) Transmit the desired CAN frame using CAN_Transmit() function. (#) Check the transmission of a CAN frame using CAN_TransmitStatus() function. (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit() function. (#) Receive a CAN frame using CAN_Recieve() function. (#) Release the receive FIFOs using CAN_FIFORelease() function. (#) Return the number of pending received frames using CAN_MessagePending() function. (#) To control CAN events you can use one of the following two methods: (++) Check on CAN flags using the CAN_GetFlagStatus() function. (++) Use CAN interrupts through the function CAN_ITConfig() at initialization phase and CAN_GetITStatus() function into interrupt routines to check if the event has occurred or not. After checking on a flag you should clear it using CAN_ClearFlag() function. And after checking on an interrupt event you should clear it using CAN_ClearITPendingBit() function. @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_can.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup CAN * @brief CAN driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* CAN Master Control Register bits */ #define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ /* CAN Mailbox Transmit Request */ #define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ /* CAN Filter Master Register bits */ #define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ /* Time out for INAK bit */ #define INAK_TIMEOUT ((uint32_t)0x0000FFFF) /* Time out for SLAK bit */ #define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) /* Flags in TSR register */ #define CAN_FLAGS_TSR ((uint32_t)0x08000000) /* Flags in RF1R register */ #define CAN_FLAGS_RF1R ((uint32_t)0x04000000) /* Flags in RF0R register */ #define CAN_FLAGS_RF0R ((uint32_t)0x02000000) /* Flags in MSR register */ #define CAN_FLAGS_MSR ((uint32_t)0x01000000) /* Flags in ESR register */ #define CAN_FLAGS_ESR ((uint32_t)0x00F00000) /* Mailboxes definition */ #define CAN_TXMAILBOX_0 ((uint8_t)0x00) #define CAN_TXMAILBOX_1 ((uint8_t)0x01) #define CAN_TXMAILBOX_2 ((uint8_t)0x02) #define CAN_MODE_MASK ((uint32_t) 0x00000003) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); /** @defgroup CAN_Private_Functions * @{ */ /** @defgroup CAN_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This section provides functions allowing to (+) Initialize the CAN peripherals : Prescaler, operating mode, the maximum number of time quanta to perform resynchronization, the number of time quanta in Bit Segment 1 and 2 and many other modes. Refer to @ref CAN_InitTypeDef for more details. (+) Configures the CAN reception filter. (+) Select the start bank filter for slave CAN. (+) Enables or disables the Debug Freeze mode for CAN (+)Enables or disables the CAN Time Trigger Operation communication mode @endverbatim * @{ */ /** * @brief Deinitializes the CAN peripheral registers to their default reset values. * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @retval None. */ void CAN_DeInit(CAN_TypeDef* CANx) { /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); if (CANx == CAN1) { /* Enable CAN1 reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); /* Release CAN1 from reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); } else { /* Enable CAN2 reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); /* Release CAN2 from reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); } } /** * @brief Initializes the CAN peripheral according to the specified * parameters in the CAN_InitStruct. * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains * the configuration information for the CAN peripheral. * @retval Constant indicates initialization succeed which will be * CAN_InitStatus_Failed or CAN_InitStatus_Success. */ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) { uint8_t InitStatus = CAN_InitStatus_Failed; uint32_t wait_ack = 0x00000000; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); /* Exit from sleep mode */ CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); /* Request initialisation */ CANx->MCR |= CAN_MCR_INRQ ; /* Wait the acknowledge */ while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) { wait_ack++; } /* Check acknowledge */ if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) { InitStatus = CAN_InitStatus_Failed; } else { /* Set the time triggered communication mode */ if (CAN_InitStruct->CAN_TTCM == ENABLE) { CANx->MCR |= CAN_MCR_TTCM; } else { CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; } /* Set the automatic bus-off management */ if (CAN_InitStruct->CAN_ABOM == ENABLE) { CANx->MCR |= CAN_MCR_ABOM; } else { CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; } /* Set the automatic wake-up mode */ if (CAN_InitStruct->CAN_AWUM == ENABLE) { CANx->MCR |= CAN_MCR_AWUM; } else { CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; } /* Set the no automatic retransmission */ if (CAN_InitStruct->CAN_NART == ENABLE) { CANx->MCR |= CAN_MCR_NART; } else { CANx->MCR &= ~(uint32_t)CAN_MCR_NART; } /* Set the receive FIFO locked mode */ if (CAN_InitStruct->CAN_RFLM == ENABLE) { CANx->MCR |= CAN_MCR_RFLM; } else { CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; } /* Set the transmit FIFO priority */ if (CAN_InitStruct->CAN_TXFP == ENABLE) { CANx->MCR |= CAN_MCR_TXFP; } else { CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; } /* Set the bit timing register */ CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); /* Request leave initialisation */ CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; /* Wait the acknowledge */ wait_ack = 0; while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) { wait_ack++; } /* ...and check acknowledged */ if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) { InitStatus = CAN_InitStatus_Failed; } else { InitStatus = CAN_InitStatus_Success ; } } /* At this step, return the status of initialization */ return InitStatus; } /** * @brief Configures the CAN reception filter according to the specified * parameters in the CAN_FilterInitStruct. * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that * contains the configuration information. * @retval None */ void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) { uint32_t filter_number_bit_pos = 0; /* Check the parameters */ assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; /* Initialisation mode for the filter */ CAN1->FMR |= FMR_FINIT; /* Filter Deactivation */ CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; /* Filter Scale */ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) { /* 16-bit scale for the filter */ CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); } if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) { /* 32-bit scale for the filter */ CAN1->FS1R |= filter_number_bit_pos; /* 32-bit identifier or First 32-bit identifier */ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); /* 32-bit mask or Second 32-bit identifier */ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); } /* Filter Mode */ if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) { /*Id/Mask mode for the filter*/ CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /*Identifier list mode for the filter*/ CAN1->FM1R |= (uint32_t)filter_number_bit_pos; } /* Filter FIFO assignment */ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) { /* FIFO 0 assignation for the filter */ CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; } if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) { /* FIFO 1 assignation for the filter */ CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; } /* Filter activation */ if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) { CAN1->FA1R |= filter_number_bit_pos; } /* Leave the initialisation mode for the filter */ CAN1->FMR &= ~FMR_FINIT; } /** * @brief Fills each CAN_InitStruct member with its default value. * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized. * @retval None */ void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) { /* Reset CAN init structure parameters values */ /* Initialize the time triggered communication mode */ CAN_InitStruct->CAN_TTCM = DISABLE; /* Initialize the automatic bus-off management */ CAN_InitStruct->CAN_ABOM = DISABLE; /* Initialize the automatic wake-up mode */ CAN_InitStruct->CAN_AWUM = DISABLE; /* Initialize the no automatic retransmission */ CAN_InitStruct->CAN_NART = DISABLE; /* Initialize the receive FIFO locked mode */ CAN_InitStruct->CAN_RFLM = DISABLE; /* Initialize the transmit FIFO priority */ CAN_InitStruct->CAN_TXFP = DISABLE; /* Initialize the CAN_Mode member */ CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; /* Initialize the CAN_SJW member */ CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; /* Initialize the CAN_BS1 member */ CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; /* Initialize the CAN_BS2 member */ CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; /* Initialize the CAN_Prescaler member */ CAN_InitStruct->CAN_Prescaler = 1; } /** * @brief Select the start bank filter for slave CAN. * @param CAN_BankNumber: Select the start slave bank filter from 1..27. * @retval None */ void CAN_SlaveStartBank(uint8_t CAN_BankNumber) { /* Check the parameters */ assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); /* Enter Initialisation mode for the filter */ CAN1->FMR |= FMR_FINIT; /* Select the start slave bank */ CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; /* Leave Initialisation mode for the filter */ CAN1->FMR &= ~FMR_FINIT; } /** * @brief Enables or disables the DBG Freeze for CAN. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param NewState: new state of the CAN peripheral. * This parameter can be: ENABLE (CAN reception/transmission is frozen * during debug. Reception FIFOs can still be accessed/controlled normally) * or DISABLE (CAN is working during debug). * @retval None */ void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable Debug Freeze */ CANx->MCR |= MCR_DBF; } else { /* Disable Debug Freeze */ CANx->MCR &= ~MCR_DBF; } } /** * @brief Enables or disables the CAN Time TriggerOperation communication mode. * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be * sent over the CAN bus. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE. * When enabled, Time stamp (TIME[15:0]) value is sent in the last two * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] * in data byte 7. * @retval None */ void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the TTCM mode */ CANx->MCR |= CAN_MCR_TTCM; /* Set TGT bits */ CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); } else { /* Disable the TTCM mode */ CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); /* Reset TGT bits */ CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); } } /** * @} */ /** @defgroup CAN_Group2 CAN Frames Transmission functions * @brief CAN Frames Transmission functions * @verbatim =============================================================================== ##### CAN Frames Transmission functions ##### =============================================================================== [..] This section provides functions allowing to (+) Initiate and transmit a CAN frame message (if there is an empty mailbox). (+) Check the transmission status of a CAN Frame (+) Cancel a transmit request @endverbatim * @{ */ /** * @brief Initiates and transmits a CAN frame message. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. * @retval The number of the mailbox that is used for transmission or * CAN_TxStatus_NoMailBox if there is no empty mailbox. */ uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) { uint8_t transmit_mailbox = 0; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); assert_param(IS_CAN_RTR(TxMessage->RTR)); assert_param(IS_CAN_DLC(TxMessage->DLC)); /* Select one empty transmit mailbox */ if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) { transmit_mailbox = 0; } else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) { transmit_mailbox = 1; } else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) { transmit_mailbox = 2; } else { transmit_mailbox = CAN_TxStatus_NoMailBox; } if (transmit_mailbox != CAN_TxStatus_NoMailBox) { /* Set up the Id */ CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; if (TxMessage->IDE == CAN_Id_Standard) { assert_param(IS_CAN_STDID(TxMessage->StdId)); CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ TxMessage->RTR); } else { assert_param(IS_CAN_EXTID(TxMessage->ExtId)); CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ TxMessage->IDE | \ TxMessage->RTR); } /* Set up the DLC */ TxMessage->DLC &= (uint8_t)0x0000000F; CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; /* Set up the data field */ CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | ((uint32_t)TxMessage->Data[2] << 16) | ((uint32_t)TxMessage->Data[1] << 8) | ((uint32_t)TxMessage->Data[0])); CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | ((uint32_t)TxMessage->Data[6] << 16) | ((uint32_t)TxMessage->Data[5] << 8) | ((uint32_t)TxMessage->Data[4])); /* Request transmission */ CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; } return transmit_mailbox; } /** * @brief Checks the transmission status of a CAN Frame. * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @param TransmitMailbox: the number of the mailbox that is used for transmission. * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, * CAN_TxStatus_Failed in an other case. */ uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) { uint32_t state = 0; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); switch (TransmitMailbox) { case (CAN_TXMAILBOX_0): state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); break; case (CAN_TXMAILBOX_1): state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); break; case (CAN_TXMAILBOX_2): state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); break; default: state = CAN_TxStatus_Failed; break; } switch (state) { /* transmit pending */ case (0x0): state = CAN_TxStatus_Pending; break; /* transmit failed */ case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; break; case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; break; case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; break; /* transmit succeeded */ case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; break; case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; break; case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; break; default: state = CAN_TxStatus_Failed; break; } return (uint8_t) state; } /** * @brief Cancels a transmit request. * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @param Mailbox: Mailbox number. * @retval None */ void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) { /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); /* abort transmission */ switch (Mailbox) { case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; break; case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; break; case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; break; default: break; } } /** * @} */ /** @defgroup CAN_Group3 CAN Frames Reception functions * @brief CAN Frames Reception functions * @verbatim =============================================================================== ##### CAN Frames Reception functions ##### =============================================================================== [..] This section provides functions allowing to (+) Receive a correct CAN frame (+) Release a specified receive FIFO (2 FIFOs are available) (+) Return the number of the pending received CAN frames @endverbatim * @{ */ /** * @brief Receives a correct CAN frame. * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. * @param RxMessage: pointer to a structure receive frame which contains CAN Id, * CAN DLC, CAN data and FMI number. * @retval None */ void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) { /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_FIFO(FIFONumber)); /* Get the Id */ RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; if (RxMessage->IDE == CAN_Id_Standard) { RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); } else { RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); } RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; /* Get the DLC */ RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; /* Get the FMI */ RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); /* Get the data field */ RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); /* Release the FIFO */ /* Release FIFO0 */ if (FIFONumber == CAN_FIFO0) { CANx->RF0R |= CAN_RF0R_RFOM0; } /* Release FIFO1 */ else /* FIFONumber == CAN_FIFO1 */ { CANx->RF1R |= CAN_RF1R_RFOM1; } } /** * @brief Releases the specified receive FIFO. * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. * @retval None */ void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) { /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_FIFO(FIFONumber)); /* Release FIFO0 */ if (FIFONumber == CAN_FIFO0) { CANx->RF0R |= CAN_RF0R_RFOM0; } /* Release FIFO1 */ else /* FIFONumber == CAN_FIFO1 */ { CANx->RF1R |= CAN_RF1R_RFOM1; } } /** * @brief Returns the number of pending received messages. * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. * @retval NbMessage : which is the number of pending message. */ uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) { uint8_t message_pending=0; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_FIFO(FIFONumber)); if (FIFONumber == CAN_FIFO0) { message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); } else if (FIFONumber == CAN_FIFO1) { message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); } else { message_pending = 0; } return message_pending; } /** * @} */ /** @defgroup CAN_Group4 CAN Operation modes functions * @brief CAN Operation modes functions * @verbatim =============================================================================== ##### CAN Operation modes functions ##### =============================================================================== [..] This section provides functions allowing to select the CAN Operation modes (+) sleep mode (+) normal mode (+) initialization mode @endverbatim * @{ */ /** * @brief Selects the CAN Operation mode. * @param CAN_OperatingMode: CAN Operating Mode. * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration. * @retval status of the requested mode which can be * - CAN_ModeStatus_Failed: CAN failed entering the specific mode * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode */ uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) { uint8_t status = CAN_ModeStatus_Failed; /* Timeout for INAK or also for SLAK bits*/ uint32_t timeout = INAK_TIMEOUT; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); if (CAN_OperatingMode == CAN_OperatingMode_Initialization) { /* Request initialisation */ CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); /* Wait the acknowledge */ while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) { timeout--; } if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) { status = CAN_ModeStatus_Failed; } else { status = CAN_ModeStatus_Success; } } else if (CAN_OperatingMode == CAN_OperatingMode_Normal) { /* Request leave initialisation and sleep mode and enter Normal mode */ CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); /* Wait the acknowledge */ while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) { timeout--; } if ((CANx->MSR & CAN_MODE_MASK) != 0) { status = CAN_ModeStatus_Failed; } else { status = CAN_ModeStatus_Success; } } else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) { /* Request Sleep mode */ CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); /* Wait the acknowledge */ while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) { timeout--; } if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) { status = CAN_ModeStatus_Failed; } else { status = CAN_ModeStatus_Success; } } else { status = CAN_ModeStatus_Failed; } return (uint8_t) status; } /** * @brief Enters the Sleep (low power) mode. * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise. */ uint8_t CAN_Sleep(CAN_TypeDef* CANx) { uint8_t sleepstatus = CAN_Sleep_Failed; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); /* Request Sleep mode */ CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); /* Sleep mode status */ if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) { /* Sleep mode not entered */ sleepstatus = CAN_Sleep_Ok; } /* return sleep mode status */ return (uint8_t)sleepstatus; } /** * @brief Wakes up the CAN peripheral from sleep mode . * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise. */ uint8_t CAN_WakeUp(CAN_TypeDef* CANx) { uint32_t wait_slak = SLAK_TIMEOUT; uint8_t wakeupstatus = CAN_WakeUp_Failed; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); /* Wake up request */ CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; /* Sleep mode status */ while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) { wait_slak--; } if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) { /* wake up done : Sleep mode exited */ wakeupstatus = CAN_WakeUp_Ok; } /* return wakeup status */ return (uint8_t)wakeupstatus; } /** * @} */ /** @defgroup CAN_Group5 CAN Bus Error management functions * @brief CAN Bus Error management functions * @verbatim =============================================================================== ##### CAN Bus Error management functions ##### =============================================================================== [..] This section provides functions allowing to (+) Return the CANx's last error code (LEC) (+) Return the CANx Receive Error Counter (REC) (+) Return the LSB of the 9-bit CANx Transmit Error Counter(TEC). -@- If TEC is greater than 255, The CAN is in bus-off state. -@- if REC or TEC are greater than 96, an Error warning flag occurs. -@- if REC or TEC are greater than 127, an Error Passive Flag occurs. @endverbatim * @{ */ /** * @brief Returns the CANx's last error code (LEC). * @param CANx: where x can be 1 or 2 to select the CAN peripheral. * @retval Error code: * - CAN_ERRORCODE_NoErr: No Error * - CAN_ERRORCODE_StuffErr: Stuff Error * - CAN_ERRORCODE_FormErr: Form Error * - CAN_ERRORCODE_ACKErr : Acknowledgment Error * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error * - CAN_ERRORCODE_CRCErr: CRC Error * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error */ uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) { uint8_t errorcode=0; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); /* Get the error code*/ errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); /* Return the error code*/ return errorcode; } /** * @brief Returns the CANx Receive Error Counter (REC). * @note In case of an error during reception, this counter is incremented * by 1 or by 8 depending on the error condition as defined by the CAN * standard. After every successful reception, the counter is * decremented by 1 or reset to 120 if its value was higher than 128. * When the counter value exceeds 127, the CAN controller enters the * error passive state. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @retval CAN Receive Error Counter. */ uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) { uint8_t counter=0; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); /* Get the Receive Error Counter*/ counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); /* Return the Receive Error Counter*/ return counter; } /** * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @retval LSB of the 9-bit CAN Transmit Error Counter. */ uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) { uint8_t counter=0; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ return counter; } /** * @} */ /** @defgroup CAN_Group6 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== [..] This section provides functions allowing to configure the CAN Interrupts and to get the status and clear flags and Interrupts pending bits. The CAN provides 14 Interrupts sources and 15 Flags: *** Flags *** ============= [..] The 15 flags can be divided on 4 groups: (+) Transmit Flags (++) CAN_FLAG_RQCP0, (++) CAN_FLAG_RQCP1, (++) CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags Set when when the last request (transmit or abort) has been performed. (+) Receive Flags (++) CAN_FLAG_FMP0, (++) CAN_FLAG_FMP1 : FIFO 0 and 1 Message Pending Flags set to signal that messages are pending in the receive FIFO. These Flags are cleared only by hardware. (++) CAN_FLAG_FF0, (++) CAN_FLAG_FF1 : FIFO 0 and 1 Full Flags set when three messages are stored in the selected FIFO. (++) CAN_FLAG_FOV0 (++) CAN_FLAG_FOV1 : FIFO 0 and 1 Overrun Flags set when a new message has been received and passed the filter while the FIFO was full. (+) Operating Mode Flags (++) CAN_FLAG_WKU : Wake up Flag set to signal that a SOF bit has been detected while the CAN hardware was in Sleep mode. (++) CAN_FLAG_SLAK : Sleep acknowledge Flag Set to signal that the CAN has entered Sleep Mode. (+) Error Flags (++) CAN_FLAG_EWG : Error Warning Flag Set when the warning limit has been reached (Receive Error Counter or Transmit Error Counter greater than 96). This Flag is cleared only by hardware. (++) CAN_FLAG_EPV : Error Passive Flag Set when the Error Passive limit has been reached (Receive Error Counter or Transmit Error Counter greater than 127). This Flag is cleared only by hardware. (++) CAN_FLAG_BOF : Bus-Off Flag set when CAN enters the bus-off state. The bus-off state is entered on TEC overflow, greater than 255. This Flag is cleared only by hardware. (++) CAN_FLAG_LEC : Last error code Flag set If a message has been transferred (reception or transmission) with error, and the error code is hold. *** Interrupts *** ================== [..] The 14 interrupts can be divided on 4 groups: (+) Transmit interrupt (++) CAN_IT_TME : Transmit mailbox empty Interrupt if enabled, this interrupt source is pending when no transmit request are pending for Tx mailboxes. (+) Receive Interrupts (++) CAN_IT_FMP0, (++) CAN_IT_FMP1 : FIFO 0 and FIFO1 message pending Interrupts if enabled, these interrupt sources are pending when messages are pending in the receive FIFO. The corresponding interrupt pending bits are cleared only by hardware. (++) CAN_IT_FF0, (++) CAN_IT_FF1 : FIFO 0 and FIFO1 full Interrupts if enabled, these interrupt sources are pending when three messages are stored in the selected FIFO. (++) CAN_IT_FOV0, (++) CAN_IT_FOV1 : FIFO 0 and FIFO1 overrun Interrupts if enabled, these interrupt sources are pending when a new message has been received and passed the filter while the FIFO was full. (+) Operating Mode Interrupts (++) CAN_IT_WKU : Wake-up Interrupt if enabled, this interrupt source is pending when a SOF bit has been detected while the CAN hardware was in Sleep mode. (++) CAN_IT_SLK : Sleep acknowledge Interrupt if enabled, this interrupt source is pending when the CAN has entered Sleep Mode. (+) Error Interrupts (++) CAN_IT_EWG : Error warning Interrupt if enabled, this interrupt source is pending when the warning limit has been reached (Receive Error Counter or Transmit Error Counter=96). (++) CAN_IT_EPV : Error passive Interrupt if enabled, this interrupt source is pending when the Error Passive limit has been reached (Receive Error Counter or Transmit Error Counter>127). (++) CAN_IT_BOF : Bus-off Interrupt if enabled, this interrupt source is pending when CAN enters the bus-off state. The bus-off state is entered on TEC overflow, greater than 255. This Flag is cleared only by hardware. (++) CAN_IT_LEC : Last error code Interrupt if enabled, this interrupt source is pending when a message has been transferred (reception or transmission) with error, and the error code is hold. (++) CAN_IT_ERR : Error Interrupt if enabled, this interrupt source is pending when an error condition is pending. [..] Managing the CAN controller events : The user should identify which mode will be used in his application to manage the CAN controller events: Polling mode or Interrupt mode. (#) In the Polling Mode it is advised to use the following functions: (++) CAN_GetFlagStatus() : to check if flags events occur. (++) CAN_ClearFlag() : to clear the flags events. (#) In the Interrupt Mode it is advised to use the following functions: (++) CAN_ITConfig() : to enable or disable the interrupt source. (++) CAN_GetITStatus() : to check if Interrupt occurs. (++) CAN_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag). -@@- This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts pending bits since there are cleared only by hardware. @endverbatim * @{ */ /** * @brief Enables or disables the specified CANx interrupts. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. * This parameter can be: * @arg CAN_IT_TME: Transmit mailbox empty Interrupt * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt * @arg CAN_IT_FF0: FIFO 0 full Interrupt * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt * @arg CAN_IT_FF1: FIFO 1 full Interrupt * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt * @arg CAN_IT_WKU: Wake-up Interrupt * @arg CAN_IT_SLK: Sleep acknowledge Interrupt * @arg CAN_IT_EWG: Error warning Interrupt * @arg CAN_IT_EPV: Error passive Interrupt * @arg CAN_IT_BOF: Bus-off Interrupt * @arg CAN_IT_LEC: Last error code Interrupt * @arg CAN_IT_ERR: Error Interrupt * @param NewState: new state of the CAN interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_IT(CAN_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected CANx interrupt */ CANx->IER |= CAN_IT; } else { /* Disable the selected CANx interrupt */ CANx->IER &= ~CAN_IT; } } /** * @brief Checks whether the specified CAN flag is set or not. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param CAN_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag * @arg CAN_FLAG_FF0: FIFO 0 Full Flag * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag * @arg CAN_FLAG_FF1: FIFO 1 Full Flag * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag * @arg CAN_FLAG_WKU: Wake up Flag * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag * @arg CAN_FLAG_EWG: Error Warning Flag * @arg CAN_FLAG_EPV: Error Passive Flag * @arg CAN_FLAG_BOF: Bus-Off Flag * @arg CAN_FLAG_LEC: Last error code Flag * @retval The new state of CAN_FLAG (SET or RESET). */ FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) { /* Check the status of the specified CAN flag */ if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) { /* CAN_FLAG is set */ bitstatus = SET; } else { /* CAN_FLAG is reset */ bitstatus = RESET; } } else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) { /* Check the status of the specified CAN flag */ if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) { /* CAN_FLAG is set */ bitstatus = SET; } else { /* CAN_FLAG is reset */ bitstatus = RESET; } } else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) { /* Check the status of the specified CAN flag */ if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) { /* CAN_FLAG is set */ bitstatus = SET; } else { /* CAN_FLAG is reset */ bitstatus = RESET; } } else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) { /* Check the status of the specified CAN flag */ if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) { /* CAN_FLAG is set */ bitstatus = SET; } else { /* CAN_FLAG is reset */ bitstatus = RESET; } } else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ { /* Check the status of the specified CAN flag */ if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) { /* CAN_FLAG is set */ bitstatus = SET; } else { /* CAN_FLAG is reset */ bitstatus = RESET; } } /* Return the CAN_FLAG status */ return bitstatus; } /** * @brief Clears the CAN's pending flags. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param CAN_FLAG: specifies the flag to clear. * This parameter can be one of the following values: * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag * @arg CAN_FLAG_FF0: FIFO 0 Full Flag * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag * @arg CAN_FLAG_FF1: FIFO 1 Full Flag * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag * @arg CAN_FLAG_WKU: Wake up Flag * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag * @arg CAN_FLAG_LEC: Last error code Flag * @retval None */ void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) { uint32_t flagtmp=0; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ { /* Clear the selected CAN flags */ CANx->ESR = (uint32_t)RESET; } else /* MSR or TSR or RF0R or RF1R */ { flagtmp = CAN_FLAG & 0x000FFFFF; if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) { /* Receive Flags */ CANx->RF0R = (uint32_t)(flagtmp); } else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) { /* Receive Flags */ CANx->RF1R = (uint32_t)(flagtmp); } else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) { /* Transmit Flags */ CANx->TSR = (uint32_t)(flagtmp); } else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ { /* Operating mode Flags */ CANx->MSR = (uint32_t)(flagtmp); } } } /** * @brief Checks whether the specified CANx interrupt has occurred or not. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param CAN_IT: specifies the CAN interrupt source to check. * This parameter can be one of the following values: * @arg CAN_IT_TME: Transmit mailbox empty Interrupt * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt * @arg CAN_IT_FF0: FIFO 0 full Interrupt * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt * @arg CAN_IT_FF1: FIFO 1 full Interrupt * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt * @arg CAN_IT_WKU: Wake-up Interrupt * @arg CAN_IT_SLK: Sleep acknowledge Interrupt * @arg CAN_IT_EWG: Error warning Interrupt * @arg CAN_IT_EPV: Error passive Interrupt * @arg CAN_IT_BOF: Bus-off Interrupt * @arg CAN_IT_LEC: Last error code Interrupt * @arg CAN_IT_ERR: Error Interrupt * @retval The current state of CAN_IT (SET or RESET). */ ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) { ITStatus itstatus = RESET; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_IT(CAN_IT)); /* check the interrupt enable bit */ if((CANx->IER & CAN_IT) != RESET) { /* in case the Interrupt is enabled, .... */ switch (CAN_IT) { case CAN_IT_TME: /* Check CAN_TSR_RQCPx bits */ itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); break; case CAN_IT_FMP0: /* Check CAN_RF0R_FMP0 bit */ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); break; case CAN_IT_FF0: /* Check CAN_RF0R_FULL0 bit */ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); break; case CAN_IT_FOV0: /* Check CAN_RF0R_FOVR0 bit */ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); break; case CAN_IT_FMP1: /* Check CAN_RF1R_FMP1 bit */ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); break; case CAN_IT_FF1: /* Check CAN_RF1R_FULL1 bit */ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); break; case CAN_IT_FOV1: /* Check CAN_RF1R_FOVR1 bit */ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); break; case CAN_IT_WKU: /* Check CAN_MSR_WKUI bit */ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); break; case CAN_IT_SLK: /* Check CAN_MSR_SLAKI bit */ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); break; case CAN_IT_EWG: /* Check CAN_ESR_EWGF bit */ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); break; case CAN_IT_EPV: /* Check CAN_ESR_EPVF bit */ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); break; case CAN_IT_BOF: /* Check CAN_ESR_BOFF bit */ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); break; case CAN_IT_LEC: /* Check CAN_ESR_LEC bit */ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); break; case CAN_IT_ERR: /* Check CAN_MSR_ERRI bit */ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); break; default: /* in case of error, return RESET */ itstatus = RESET; break; } } else { /* in case the Interrupt is not enabled, return RESET */ itstatus = RESET; } /* Return the CAN_IT status */ return itstatus; } /** * @brief Clears the CANx's interrupt pending bits. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param CAN_IT: specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg CAN_IT_TME: Transmit mailbox empty Interrupt * @arg CAN_IT_FF0: FIFO 0 full Interrupt * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt * @arg CAN_IT_FF1: FIFO 1 full Interrupt * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt * @arg CAN_IT_WKU: Wake-up Interrupt * @arg CAN_IT_SLK: Sleep acknowledge Interrupt * @arg CAN_IT_EWG: Error warning Interrupt * @arg CAN_IT_EPV: Error passive Interrupt * @arg CAN_IT_BOF: Bus-off Interrupt * @arg CAN_IT_LEC: Last error code Interrupt * @arg CAN_IT_ERR: Error Interrupt * @retval None */ void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) { /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_CAN_CLEAR_IT(CAN_IT)); switch (CAN_IT) { case CAN_IT_TME: /* Clear CAN_TSR_RQCPx (rc_w1)*/ CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; break; case CAN_IT_FF0: /* Clear CAN_RF0R_FULL0 (rc_w1)*/ CANx->RF0R = CAN_RF0R_FULL0; break; case CAN_IT_FOV0: /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ CANx->RF0R = CAN_RF0R_FOVR0; break; case CAN_IT_FF1: /* Clear CAN_RF1R_FULL1 (rc_w1)*/ CANx->RF1R = CAN_RF1R_FULL1; break; case CAN_IT_FOV1: /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ CANx->RF1R = CAN_RF1R_FOVR1; break; case CAN_IT_WKU: /* Clear CAN_MSR_WKUI (rc_w1)*/ CANx->MSR = CAN_MSR_WKUI; break; case CAN_IT_SLK: /* Clear CAN_MSR_SLAKI (rc_w1)*/ CANx->MSR = CAN_MSR_SLAKI; break; case CAN_IT_EWG: /* Clear CAN_MSR_ERRI (rc_w1) */ CANx->MSR = CAN_MSR_ERRI; /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ break; case CAN_IT_EPV: /* Clear CAN_MSR_ERRI (rc_w1) */ CANx->MSR = CAN_MSR_ERRI; /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ break; case CAN_IT_BOF: /* Clear CAN_MSR_ERRI (rc_w1) */ CANx->MSR = CAN_MSR_ERRI; /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ break; case CAN_IT_LEC: /* Clear LEC bits */ CANx->ESR = RESET; /* Clear CAN_MSR_ERRI (rc_w1) */ CANx->MSR = CAN_MSR_ERRI; break; case CAN_IT_ERR: /*Clear LEC bits */ CANx->ESR = RESET; /* Clear CAN_MSR_ERRI (rc_w1) */ CANx->MSR = CAN_MSR_ERRI; /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/ break; default: break; } } /** * @} */ /** * @brief Checks whether the CAN interrupt has occurred or not. * @param CAN_Reg: specifies the CAN interrupt register to check. * @param It_Bit: specifies the interrupt source bit to check. * @retval The new state of the CAN Interrupt (SET or RESET). */ static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) { ITStatus pendingbitstatus = RESET; if ((CAN_Reg & It_Bit) != (uint32_t)RESET) { /* CAN_IT is set */ pendingbitstatus = SET; } else { /* CAN_IT is reset */ pendingbitstatus = RESET; } return pendingbitstatus; } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c ================================================ /** ****************************************************************************** * @file stm32f4xx_crc.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides all the CRC firmware functions. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_crc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup CRC * @brief CRC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup CRC_Private_Functions * @{ */ /** * @brief Resets the CRC Data register (DR). * @param None * @retval None */ void CRC_ResetDR(void) { /* Reset CRC generator */ CRC->CR = CRC_CR_RESET; } /** * @brief Computes the 32-bit CRC of a given data word(32-bit). * @param Data: data word(32-bit) to compute its CRC * @retval 32-bit CRC */ uint32_t CRC_CalcCRC(uint32_t Data) { CRC->DR = Data; return (CRC->DR); } /** * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). * @param pBuffer: pointer to the buffer containing the data to be computed * @param BufferLength: length of the buffer to be computed * @retval 32-bit CRC */ uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) { uint32_t index = 0; for(index = 0; index < BufferLength; index++) { CRC->DR = pBuffer[index]; } return (CRC->DR); } /** * @brief Returns the current CRC value. * @param None * @retval 32-bit CRC */ uint32_t CRC_GetCRC(void) { return (CRC->DR); } /** * @brief Stores a 8-bit data in the Independent Data(ID) register. * @param IDValue: 8-bit value to be stored in the ID register * @retval None */ void CRC_SetIDRegister(uint8_t IDValue) { CRC->IDR = IDValue; } /** * @brief Returns the 8-bit data stored in the Independent Data(ID) register * @param None * @retval 8-bit value of the ID register */ uint8_t CRC_GetIDRegister(void) { return (CRC->IDR); } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c ================================================ /** ****************************************************************************** * @file stm32f4xx_cryp.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Cryptographic processor (CRYP) peripheral: * + Initialization and Configuration functions * + Data treatment functions * + Context swapping functions * + DMA interface function * + Interrupts and flags management * @verbatim =================================================================== ##### How to use this driver ##### =================================================================== [..] (#) Enable the CRYP controller clock using RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. (#) Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if needed CRYP_IVInit(). (#) Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function. (#) Enable the CRYP controller using the CRYP_Cmd() function. (#) If using DMA for Data input and output transfer, activate the needed DMA Requests using CRYP_DMACmd() function (#) If DMA is not used for data transfer, use CRYP_DataIn() and CRYP_DataOut() functions to enter data to IN FIFO and get result from OUT FIFO. (#) To control CRYP events you can use one of the following two methods: (++) Check on CRYP flags using the CRYP_GetFlagStatus() function. (++) Use CRYP interrupts through the function CRYP_ITConfig() at initialization phase and CRYP_GetITStatus() function into interrupt routines in processing phase. (#) Save and restore Cryptographic processor context using CRYP_SaveContext() and CRYP_RestoreContext() functions. *** Procedure to perform an encryption or a decryption *** ========================================================== *** Initialization *** ====================== [..] (#) Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and CRYP_IVInit functions: (++) Configure the key size (128-, 192- or 256-bit, in the AES only) (++) Enter the symmetric key (++) Configure the data type (++) In case of decryption in AES-ECB or AES-CBC, you must prepare the key: configure the key preparation mode. Then Enable the CRYP peripheral using CRYP_Cmd() function: the BUSY flag is set. Wait until BUSY flag is reset : the key is prepared for decryption (++) Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the AES in ECB/CBC/CTR) (++) Configure the direction (encryption/decryption). (++) Write the initialization vectors (in CBC or CTR modes only) (#) Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function *** Basic Processing mode (polling mode) *** ============================================ [..] (#) Enable the cryptographic processor using CRYP_Cmd() function. (#) Write the first blocks in the input FIFO (2 to 8 words) using CRYP_DataIn() function. (#) Repeat the following sequence until the complete message has been processed: (++) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() function), then read the OUT-FIFO using CRYP_DataOut() function (1 block or until the FIFO is empty) (++) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() function then write the IN FIFO using CRYP_DataIn() function (1 block or until the FIFO is full) (#) At the end of the processing, CRYP_FLAG_BUSY flag will be reset and both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). You can disable the peripheral using CRYP_Cmd() function. *** Interrupts Processing mode *** ================================== [..] In this mode, Processing is done when the data are transferred by the CPU during interrupts. (#) Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using CRYP_ITConfig() function. (#) Enable the cryptographic processor using CRYP_Cmd() function. (#) In the CRYP_IT_INI interrupt handler : load the input message into the IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a time, or load data until the IN FIFO is full. When the last word of the message has been entered into the IN FIFO, disable the CRYP_IT_INI interrupt (using CRYP_ITConfig() function). (#) In the CRYP_IT_OUTI interrupt handler : read the output message from the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or 4 words) at a time or read data until the FIFO is empty. When the last word has been read, INIM=0, BUSY=0 and both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() function) and you can disable the peripheral using CRYP_Cmd() function. *** DMA Processing mode *** =========================== [..] In this mode, Processing is done when the DMA is used to transfer the data from/to the memory. (#) Configure the DMA controller to transfer the input data from the memory using DMA_Init() function. The transfer length is the length of the message. As message padding is not managed by the peripheral, the message length must be an entire number of blocks. The data are transferred in burst mode. The burst length is 4 words in the AES and 2 or 4 words in the DES/TDES. The DMA should be configured to set an interrupt on transfer completion of the output data to indicate that the processing is finished. Refer to DMA peripheral driver for more details. (#) Enable the cryptographic processor using CRYP_Cmd() function. Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT using CRYP_DMACmd() function. (#) All the transfers and processing are managed by the DMA and the cryptographic processor. The DMA transfer complete interrupt indicates that the processing is complete. Both FIFOs are normally empty and CRYP_FLAG_BUSY flag is reset. @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_cryp.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup CRYP * @brief CRYP driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define FLAG_MASK ((uint8_t)0x20) #define MAX_TIMEOUT ((uint16_t)0xFFFF) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup CRYP_Private_Functions * @{ */ /** @defgroup CRYP_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This section provides functions allowing to (+) Initialize the cryptographic Processor using CRYP_Init() function (++) Encrypt or Decrypt (++) mode : TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, AES-CBC, AES-CTR, AES-Key, AES-GCM, AES-CCM (++) DataType : 32-bit data, 16-bit data, bit data or bit-string (++) Key Size (only in AES modes) (+) Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function (+) Configure the Initialization Vectors(IV) for CBC and CTR modes using CRYP_IVInit() function. (+) Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function. (+) Enable or disable the CRYP Processor using CRYP_Cmd() function @endverbatim * @{ */ /** * @brief Deinitializes the CRYP peripheral registers to their default reset values * @param None * @retval None */ void CRYP_DeInit(void) { /* Enable CRYP reset state */ RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE); /* Release CRYP from reset state */ RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE); } /** * @brief Initializes the CRYP peripheral according to the specified parameters * in the CRYP_InitStruct. * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains * the configuration information for the CRYP peripheral. * @retval None */ void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct) { /* Check the parameters */ assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode)); assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType)); assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir)); /* Select Algorithm mode*/ CRYP->CR &= ~CRYP_CR_ALGOMODE; CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode; /* Select dataType */ CRYP->CR &= ~CRYP_CR_DATATYPE; CRYP->CR |= CRYP_InitStruct->CRYP_DataType; /* select Key size (used only with AES algorithm) */ if ((CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_ECB) && (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_CBC) && (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_ECB) && (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_CBC)) { assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize)); CRYP->CR &= ~CRYP_CR_KEYSIZE; CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be configured once the key has been prepared */ } /* Select data Direction */ CRYP->CR &= ~CRYP_CR_ALGODIR; CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir; } /** * @brief Fills each CRYP_InitStruct member with its default value. * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will * be initialized. * @retval None */ void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct) { /* Initialize the CRYP_AlgoDir member */ CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; /* initialize the CRYP_AlgoMode member */ CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; /* initialize the CRYP_DataType member */ CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b; /* Initialize the CRYP_KeySize member */ CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b; } /** * @brief Initializes the CRYP Keys according to the specified parameters in * the CRYP_KeyInitStruct. * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that * contains the configuration information for the CRYP Keys. * @retval None */ void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) { /* Key Initialisation */ CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; } /** * @brief Fills each CRYP_KeyInitStruct member with its default value. * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure * which will be initialized. * @retval None */ void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) { CRYP_KeyInitStruct->CRYP_Key0Left = 0; CRYP_KeyInitStruct->CRYP_Key0Right = 0; CRYP_KeyInitStruct->CRYP_Key1Left = 0; CRYP_KeyInitStruct->CRYP_Key1Right = 0; CRYP_KeyInitStruct->CRYP_Key2Left = 0; CRYP_KeyInitStruct->CRYP_Key2Right = 0; CRYP_KeyInitStruct->CRYP_Key3Left = 0; CRYP_KeyInitStruct->CRYP_Key3Right = 0; } /** * @brief Initializes the CRYP Initialization Vectors(IV) according to the * specified parameters in the CRYP_IVInitStruct. * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains * the configuration information for the CRYP Initialization Vectors(IV). * @retval None */ void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) { CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left; CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right; CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left; CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right; } /** * @brief Fills each CRYP_IVInitStruct member with its default value. * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization * Vectors(IV) structure which will be initialized. * @retval None */ void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) { CRYP_IVInitStruct->CRYP_IV0Left = 0; CRYP_IVInitStruct->CRYP_IV0Right = 0; CRYP_IVInitStruct->CRYP_IV1Left = 0; CRYP_IVInitStruct->CRYP_IV1Right = 0; } /** * @brief Configures the AES-CCM and AES-GCM phases * @note This function is used only with AES-CCM or AES-GCM Algorithms * @param CRYP_Phase: specifies the CRYP AES-CCM and AES-GCM phase to be configured. * This parameter can be one of the following values: * @arg CRYP_Phase_Init: Initialization phase * @arg CRYP_Phase_Header: Header phase * @arg CRYP_Phase_Payload: Payload phase * @arg CRYP_Phase_Final: Final phase * @retval None */ void CRYP_PhaseConfig(uint32_t CRYP_Phase) { uint32_t tempcr = 0; /* Check the parameter */ assert_param(IS_CRYP_PHASE(CRYP_Phase)); /* Get the CR register */ tempcr = CRYP->CR; /* Reset the phase configuration bits: GCMP_CCMPH */ tempcr &= (uint32_t)(~CRYP_CR_GCM_CCMPH); /* Set the selected phase */ tempcr |= (uint32_t)CRYP_Phase; /* Set the CR register */ CRYP->CR = tempcr; } /** * @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the * FIFOs are reset) * @note The FIFOs must be flushed only when BUSY flag is reset. * @param None * @retval None */ void CRYP_FIFOFlush(void) { /* Reset the read and write pointers of the FIFOs */ CRYP->CR |= CRYP_CR_FFLUSH; } /** * @brief Enables or disables the CRYP peripheral. * @param NewState: new state of the CRYP peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void CRYP_Cmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the Cryptographic processor */ CRYP->CR |= CRYP_CR_CRYPEN; } else { /* Disable the Cryptographic processor */ CRYP->CR &= ~CRYP_CR_CRYPEN; } } /** * @} */ /** @defgroup CRYP_Group2 CRYP Data processing functions * @brief CRYP Data processing functions * @verbatim =============================================================================== ##### CRYP Data processing functions ##### =============================================================================== [..] This section provides functions allowing the encryption and decryption operations: (+) Enter data to be treated in the IN FIFO : using CRYP_DataIn() function. (+) Get the data result from the OUT FIFO : using CRYP_DataOut() function. @endverbatim * @{ */ /** * @brief Writes data in the Data Input register (DIN). * @note After the DIN register has been read once or several times, * the FIFO must be flushed (using CRYP_FIFOFlush() function). * @param Data: data to write in Data Input register * @retval None */ void CRYP_DataIn(uint32_t Data) { CRYP->DR = Data; } /** * @brief Returns the last data entered into the output FIFO. * @param None * @retval Last data entered into the output FIFO. */ uint32_t CRYP_DataOut(void) { return CRYP->DOUT; } /** * @} */ /** @defgroup CRYP_Group3 Context swapping functions * @brief Context swapping functions * @verbatim =============================================================================== ##### Context swapping functions ##### =============================================================================== [..] This section provides functions allowing to save and store CRYP Context [..] It is possible to interrupt an encryption/ decryption/ key generation process to perform another processing with a higher priority, and to complete the interrupted process later on, when the higher-priority task is complete. To do so, the context of the interrupted task must be saved from the CRYP registers to memory, and then be restored from memory to the CRYP registers. (#) To save the current context, use CRYP_SaveContext() function (#) To restore the saved context, use CRYP_RestoreContext() function @endverbatim * @{ */ /** * @brief Saves the CRYP peripheral Context. * @note This function stops DMA transfer before to save the context. After * restoring the context, you have to enable the DMA again (if the DMA * was previously used). * @param CRYP_ContextSave: pointer to a CRYP_Context structure that contains * the repository for current context. * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that * contains the configuration information for the CRYP Keys. * @retval None */ ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) { __IO uint32_t timeout = 0; uint32_t ckeckmask = 0, bitstatus; ErrorStatus status = ERROR; /* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */ CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN; /* Wait until both the IN and OUT FIFOs are empty (IFEM=1 and OFNE=0 in the CRYP_SR register) and the BUSY bit is cleared. */ if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */ { ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY ; } else /* AES or DES */ { ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE; } do { bitstatus = CRYP->SR & ckeckmask; timeout++; } while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM)); if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM) { status = ERROR; } else { /* Stop DMA transfers on the OUT FIFO by - writing the DOEN bit to 0 in the CRYP_DMACR register - and clear the CRYPEN bit. */ CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN; CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN; /* Save the current configuration (bit 19, bit[17:16] and bits [9:2] in the CRYP_CR register) */ CRYP_ContextSave->CR_CurrentConfig = CRYP->CR & (CRYP_CR_GCM_CCMPH | CRYP_CR_KEYSIZE | CRYP_CR_DATATYPE | CRYP_CR_ALGOMODE | CRYP_CR_ALGODIR); /* and, if not in ECB mode, the initialization vectors. */ CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR; CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR; CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR; CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR; /* save The key value */ CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; /* Save the content of context swap registers */ CRYP_ContextSave->CRYP_CSGCMCCMR[0] = CRYP->CSGCMCCM0R; CRYP_ContextSave->CRYP_CSGCMCCMR[1] = CRYP->CSGCMCCM1R; CRYP_ContextSave->CRYP_CSGCMCCMR[2] = CRYP->CSGCMCCM2R; CRYP_ContextSave->CRYP_CSGCMCCMR[3] = CRYP->CSGCMCCM3R; CRYP_ContextSave->CRYP_CSGCMCCMR[4] = CRYP->CSGCMCCM4R; CRYP_ContextSave->CRYP_CSGCMCCMR[5] = CRYP->CSGCMCCM5R; CRYP_ContextSave->CRYP_CSGCMCCMR[6] = CRYP->CSGCMCCM6R; CRYP_ContextSave->CRYP_CSGCMCCMR[7] = CRYP->CSGCMCCM7R; CRYP_ContextSave->CRYP_CSGCMR[0] = CRYP->CSGCM0R; CRYP_ContextSave->CRYP_CSGCMR[1] = CRYP->CSGCM1R; CRYP_ContextSave->CRYP_CSGCMR[2] = CRYP->CSGCM2R; CRYP_ContextSave->CRYP_CSGCMR[3] = CRYP->CSGCM3R; CRYP_ContextSave->CRYP_CSGCMR[4] = CRYP->CSGCM4R; CRYP_ContextSave->CRYP_CSGCMR[5] = CRYP->CSGCM5R; CRYP_ContextSave->CRYP_CSGCMR[6] = CRYP->CSGCM6R; CRYP_ContextSave->CRYP_CSGCMR[7] = CRYP->CSGCM7R; /* When needed, save the DMA status (pointers for IN and OUT messages, number of remaining bytes, etc.) */ status = SUCCESS; } return status; } /** * @brief Restores the CRYP peripheral Context. * @note Since teh DMA transfer is stopped in CRYP_SaveContext() function, * after restoring the context, you have to enable the DMA again (if the * DMA was previously used). * @param CRYP_ContextRestore: pointer to a CRYP_Context structure that contains * the repository for saved context. * @note The data that were saved during context saving must be rewrited into * the IN FIFO. * @retval None */ void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore) { /* Configure the processor with the saved configuration */ CRYP->CR = CRYP_ContextRestore->CR_CurrentConfig; /* restore The key value */ CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR; CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR; CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR; CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR; CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR; CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR; CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR; CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR; /* and the initialization vectors. */ CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR; CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR; CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR; CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR; /* Restore the content of context swap registers */ CRYP->CSGCMCCM0R = CRYP_ContextRestore->CRYP_CSGCMCCMR[0]; CRYP->CSGCMCCM1R = CRYP_ContextRestore->CRYP_CSGCMCCMR[1]; CRYP->CSGCMCCM2R = CRYP_ContextRestore->CRYP_CSGCMCCMR[2]; CRYP->CSGCMCCM3R = CRYP_ContextRestore->CRYP_CSGCMCCMR[3]; CRYP->CSGCMCCM4R = CRYP_ContextRestore->CRYP_CSGCMCCMR[4]; CRYP->CSGCMCCM5R = CRYP_ContextRestore->CRYP_CSGCMCCMR[5]; CRYP->CSGCMCCM6R = CRYP_ContextRestore->CRYP_CSGCMCCMR[6]; CRYP->CSGCMCCM7R = CRYP_ContextRestore->CRYP_CSGCMCCMR[7]; CRYP->CSGCM0R = CRYP_ContextRestore->CRYP_CSGCMR[0]; CRYP->CSGCM1R = CRYP_ContextRestore->CRYP_CSGCMR[1]; CRYP->CSGCM2R = CRYP_ContextRestore->CRYP_CSGCMR[2]; CRYP->CSGCM3R = CRYP_ContextRestore->CRYP_CSGCMR[3]; CRYP->CSGCM4R = CRYP_ContextRestore->CRYP_CSGCMR[4]; CRYP->CSGCM5R = CRYP_ContextRestore->CRYP_CSGCMR[5]; CRYP->CSGCM6R = CRYP_ContextRestore->CRYP_CSGCMR[6]; CRYP->CSGCM7R = CRYP_ContextRestore->CRYP_CSGCMR[7]; /* Enable the cryptographic processor */ CRYP->CR |= CRYP_CR_CRYPEN; } /** * @} */ /** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function * @brief CRYP's DMA interface Configuration function * @verbatim =============================================================================== ##### CRYP's DMA interface Configuration function ##### =============================================================================== [..] This section provides functions allowing to configure the DMA interface for CRYP data input and output transfer. [..] When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be transferred: (+) From memory to the CRYP IN FIFO using the DMA peripheral by enabling the CRYP_DMAReq_DataIN request. (+) From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling the CRYP_DMAReq_DataOUT request. @endverbatim * @{ */ /** * @brief Enables or disables the CRYP DMA interface. * @param CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled. * This parameter can be any combination of the following values: * @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer * @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer * @param NewState: new state of the selected CRYP DMA transfer request. * This parameter can be: ENABLE or DISABLE. * @retval None */ void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected CRYP DMA request */ CRYP->DMACR |= CRYP_DMAReq; } else { /* Disable the selected CRYP DMA request */ CRYP->DMACR &= (uint8_t)~CRYP_DMAReq; } } /** * @} */ /** @defgroup CRYP_Group5 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== [..] This section provides functions allowing to configure the CRYP Interrupts and to get the status and Interrupts pending bits. [..] The CRYP provides 2 Interrupts sources and 7 Flags: *** Flags : *** =============== [..] (#) CRYP_FLAG_IFEM : Set when Input FIFO is empty. This Flag is cleared only by hardware. (#) CRYP_FLAG_IFNF : Set when Input FIFO is not full. This Flag is cleared only by hardware. (#) CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending it gives the raw interrupt state prior to masking of the input FIFO service interrupt. This Flag is cleared only by hardware. (#) CRYP_FLAG_OFNE : Set when Output FIFO not empty. This Flag is cleared only by hardware. (#) CRYP_FLAG_OFFU : Set when Output FIFO is full. This Flag is cleared only by hardware. (#) CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending it gives the raw interrupt state prior to masking of the output FIFO service interrupt. This Flag is cleared only by hardware. (#) CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a block of data or a key preparation (for AES decryption). This Flag is cleared only by hardware. To clear it, the CRYP core must be disabled and the last processing has completed. *** Interrupts : *** ==================== [..] (#) CRYP_IT_INI : The input FIFO service interrupt is asserted when there are less than 4 words in the input FIFO. This interrupt is associated to CRYP_FLAG_INRIS flag. -@- This interrupt is cleared by performing write operations to the input FIFO until it holds 4 or more words. The input FIFO service interrupt INMIS is enabled with the CRYP enable bit. Consequently, when CRYP is disabled, the INMIS signal is low even if the input FIFO is empty. (#) CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there is one or more (32-bit word) data items in the output FIFO. This interrupt is associated to CRYP_FLAG_OUTRIS flag. -@- This interrupt is cleared by reading data from the output FIFO until there is no valid (32-bit) word left (that is, the interrupt follows the state of the OFNE (output FIFO not empty) flag). *** Managing the CRYP controller events : *** ============================================= [..] The user should identify which mode will be used in his application to manage the CRYP controller events: Polling mode or Interrupt mode. (#) In the Polling Mode it is advised to use the following functions: (++) CRYP_GetFlagStatus() : to check if flags events occur. -@@- The CRYPT flags do not need to be cleared since they are cleared as soon as the associated event are reset. (#) In the Interrupt Mode it is advised to use the following functions: (++) CRYP_ITConfig() : to enable or disable the interrupt source. (++) CRYP_GetITStatus() : to check if Interrupt occurs. -@@- The CRYPT interrupts have no pending bits, the interrupt is cleared as soon as the associated event is reset. @endverbatim * @{ */ /** * @brief Enables or disables the specified CRYP interrupts. * @param CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled. * This parameter can be any combination of the following values: * @arg CRYP_IT_INI: Input FIFO interrupt * @arg CRYP_IT_OUTI: Output FIFO interrupt * @param NewState: new state of the specified CRYP interrupt. * This parameter can be: ENABLE or DISABLE. * @retval None */ void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_CRYP_CONFIG_IT(CRYP_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected CRYP interrupt */ CRYP->IMSCR |= CRYP_IT; } else { /* Disable the selected CRYP interrupt */ CRYP->IMSCR &= (uint8_t)~CRYP_IT; } } /** * @brief Checks whether the specified CRYP interrupt has occurred or not. * @note This function checks the status of the masked interrupt (i.e the * interrupt should be previously enabled). * @param CRYP_IT: specifies the CRYP (masked) interrupt source to check. * This parameter can be one of the following values: * @arg CRYP_IT_INI: Input FIFO interrupt * @arg CRYP_IT_OUTI: Output FIFO interrupt * @retval The new state of CRYP_IT (SET or RESET). */ ITStatus CRYP_GetITStatus(uint8_t CRYP_IT) { ITStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_CRYP_GET_IT(CRYP_IT)); /* Check the status of the specified CRYP interrupt */ if ((CRYP->MISR & CRYP_IT) != (uint8_t)RESET) { /* CRYP_IT is set */ bitstatus = SET; } else { /* CRYP_IT is reset */ bitstatus = RESET; } /* Return the CRYP_IT status */ return bitstatus; } /** * @brief Returns whether CRYP peripheral is enabled or disabled. * @param none. * @retval Current state of the CRYP peripheral (ENABLE or DISABLE). */ FunctionalState CRYP_GetCmdStatus(void) { FunctionalState state = DISABLE; if ((CRYP->CR & CRYP_CR_CRYPEN) != 0) { /* CRYPEN bit is set */ state = ENABLE; } else { /* CRYPEN bit is reset */ state = DISABLE; } return state; } /** * @brief Checks whether the specified CRYP flag is set or not. * @param CRYP_FLAG: specifies the CRYP flag to check. * This parameter can be one of the following values: * @arg CRYP_FLAG_IFEM: Input FIFO Empty flag. * @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag. * @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag. * @arg CRYP_FLAG_OFFU: Output FIFO Full flag. * @arg CRYP_FLAG_BUSY: Busy flag. * @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag. * @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag. * @retval The new state of CRYP_FLAG (SET or RESET). */ FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG) { FlagStatus bitstatus = RESET; uint32_t tempreg = 0; /* Check the parameters */ assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG)); /* check if the FLAG is in RISR register */ if ((CRYP_FLAG & FLAG_MASK) != 0x00) { tempreg = CRYP->RISR; } else /* The FLAG is in SR register */ { tempreg = CRYP->SR; } /* Check the status of the specified CRYP flag */ if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET) { /* CRYP_FLAG is set */ bitstatus = SET; } else { /* CRYP_FLAG is reset */ bitstatus = RESET; } /* Return the CRYP_FLAG status */ return bitstatus; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c ================================================ /** ****************************************************************************** * @file stm32f4xx_cryp_aes.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides high level functions to encrypt and decrypt an * input message using AES in ECB/CBC/CTR/GCM/CCM modes. * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP * peripheral. * AES-ECB/CBC/CTR/GCM/CCM modes are available on STM32F437x Devices. * For STM32F41xx Devices, only AES-ECB/CBC/CTR modes are available. * @verbatim =================================================================== ##### How to use this driver ##### =================================================================== [..] (#) Enable The CRYP controller clock using RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. (#) Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB() function. (#) Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC() function. (#) Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR() function. (#) Encrypt and decrypt using AES in GCM Mode using CRYP_AES_GCM() function. (#) Encrypt and decrypt using AES in CCM Mode using CRYP_AES_CCM() function. @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_cryp.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup CRYP * @brief CRYP driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define AESBUSY_TIMEOUT ((uint32_t) 0x00010000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup CRYP_Private_Functions * @{ */ /** @defgroup CRYP_Group6 High Level AES functions * @brief High Level AES functions * @verbatim =============================================================================== ##### High Level AES functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Encrypt and decrypt using AES in ECB Mode * @param Mode: encryption or decryption Mode. * This parameter can be one of the following values: * @arg MODE_ENCRYPT: Encryption * @arg MODE_DECRYPT: Decryption * @param Key: Key used for AES algorithm. * @param Keysize: length of the Key, must be a 128, 192 or 256. * @param Input: pointer to the Input buffer. * @param Ilength: length of the Input buffer, must be a multiple of 16. * @param Output: pointer to the returned buffer. * @retval An ErrorStatus enumeration value: * - SUCCESS: Operation done * - ERROR: Operation failed */ ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize, uint8_t* Input, uint32_t Ilength, uint8_t* Output) { CRYP_InitTypeDef AES_CRYP_InitStructure; CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure; __IO uint32_t counter = 0; uint32_t busystatus = 0; ErrorStatus status = SUCCESS; uint32_t keyaddr = (uint32_t)Key; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; uint32_t i = 0; /* Crypto structures initialisation*/ CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure); switch(Keysize) { case 128: AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); break; case 192: AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b; AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); break; case 256: AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b; AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); break; default: break; } /*------------------ AES Decryption ------------------*/ if(Mode == MODE_DECRYPT) /* AES decryption */ { /* Flush IN/OUT FIFOs */ CRYP_FIFOFlush(); /* Crypto Init for Key preparation for decryption process */ AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key; AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b; CRYP_Init(&AES_CRYP_InitStructure); /* Key Initialisation */ CRYP_KeyInit(&AES_CRYP_KeyInitStructure); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); /* wait until the Busy flag is RESET */ do { busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); counter++; }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); if (busystatus != RESET) { status = ERROR; } else { /* Crypto Init for decryption process */ AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; } } /*------------------ AES Encryption ------------------*/ else /* AES encryption */ { CRYP_KeyInit(&AES_CRYP_KeyInitStructure); /* Crypto Init for Encryption process */ AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; } AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB; AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; CRYP_Init(&AES_CRYP_InitStructure); /* Flush IN/OUT FIFOs */ CRYP_FIFOFlush(); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); if(CRYP_GetCmdStatus() == DISABLE) { /* The CRYP peripheral clock is not enabled or the device doesn't embedd the CRYP peripheral (please check the device sales type. */ return(ERROR); } for(i=0; ((i>32)); CRYP_DataIn(__REV(headerlength)); CRYP_DataIn(__REV(inputlength>>32)); CRYP_DataIn(__REV(inputlength)); /* Wait until the OFNE flag is reset */ while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) { } tagaddr = (uint32_t)AuthTAG; /* Read the Auth TAG in the IN FIFO */ *(uint32_t*)(tagaddr) = CRYP_DataOut(); tagaddr+=4; *(uint32_t*)(tagaddr) = CRYP_DataOut(); tagaddr+=4; *(uint32_t*)(tagaddr) = CRYP_DataOut(); tagaddr+=4; *(uint32_t*)(tagaddr) = CRYP_DataOut(); tagaddr+=4; } /*------------------ AES Decryption ------------------*/ else /* AES decryption */ { /* Flush IN/OUT FIFOs */ CRYP_FIFOFlush(); /* Key Initialisation */ CRYP_KeyInit(&AES_CRYP_KeyInitStructure); /* CRYP Initialization Vectors */ CRYP_IVInit(&AES_CRYP_IVInitStructure); /* Crypto Init for Key preparation for decryption process */ AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_GCM; AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; CRYP_Init(&AES_CRYP_InitStructure); /***************************** Init phase *********************************/ /* Select init phase */ CRYP_PhaseConfig(CRYP_Phase_Init); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); /* Wait for CRYPEN bit to be 0 */ while(CRYP_GetCmdStatus() == ENABLE) { } /***************************** header phase *******************************/ if(HLength != 0) { /* Select header phase */ CRYP_PhaseConfig(CRYP_Phase_Header); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); if(CRYP_GetCmdStatus() == DISABLE) { /* The CRYP peripheral clock is not enabled or the device doesn't embedd the CRYP peripheral (please check the device sales type. */ return(ERROR); } for(loopcounter = 0; (loopcounter < HLength); loopcounter+=16) { /* Wait until the IFEM flag is reset */ while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) { } /* Write the Input block in the IN FIFO */ CRYP_DataIn(*(uint32_t*)(headeraddr)); headeraddr+=4; CRYP_DataIn(*(uint32_t*)(headeraddr)); headeraddr+=4; CRYP_DataIn(*(uint32_t*)(headeraddr)); headeraddr+=4; CRYP_DataIn(*(uint32_t*)(headeraddr)); headeraddr+=4; } /* Wait until the complete message has been processed */ counter = 0; do { busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); counter++; }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); if (busystatus != RESET) { status = ERROR; } } /**************************** payload phase *******************************/ if(ILength != 0) { /* Select payload phase */ CRYP_PhaseConfig(CRYP_Phase_Payload); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); if(CRYP_GetCmdStatus() == DISABLE) { /* The CRYP peripheral clock is not enabled or the device doesn't embedd the CRYP peripheral (please check the device sales type. */ return(ERROR); } for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16) { /* Wait until the IFEM flag is reset */ while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) { } /* Write the Input block in the IN FIFO */ CRYP_DataIn(*(uint32_t*)(inputaddr)); inputaddr+=4; CRYP_DataIn(*(uint32_t*)(inputaddr)); inputaddr+=4; CRYP_DataIn(*(uint32_t*)(inputaddr)); inputaddr+=4; CRYP_DataIn(*(uint32_t*)(inputaddr)); inputaddr+=4; /* Wait until the complete message has been processed */ counter = 0; do { busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); counter++; }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); if (busystatus != RESET) { status = ERROR; } else { /* Wait until the OFNE flag is reset */ while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) { } /* Read the Output block from the Output FIFO */ *(uint32_t*)(outputaddr) = CRYP_DataOut(); outputaddr+=4; *(uint32_t*)(outputaddr) = CRYP_DataOut(); outputaddr+=4; *(uint32_t*)(outputaddr) = CRYP_DataOut(); outputaddr+=4; *(uint32_t*)(outputaddr) = CRYP_DataOut(); outputaddr+=4; } } } /***************************** final phase ********************************/ /* Select final phase */ CRYP_PhaseConfig(CRYP_Phase_Final); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); if(CRYP_GetCmdStatus() == DISABLE) { /* The CRYP peripheral clock is not enabled or the device doesn't embedd the CRYP peripheral (please check the device sales type. */ return(ERROR); } /* Write number of bits concatenated with header in the IN FIFO */ CRYP_DataIn(__REV(headerlength>>32)); CRYP_DataIn(__REV(headerlength)); CRYP_DataIn(__REV(inputlength>>32)); CRYP_DataIn(__REV(inputlength)); /* Wait until the OFNE flag is reset */ while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) { } tagaddr = (uint32_t)AuthTAG; /* Read the Auth TAG in the IN FIFO */ *(uint32_t*)(tagaddr) = CRYP_DataOut(); tagaddr+=4; *(uint32_t*)(tagaddr) = CRYP_DataOut(); tagaddr+=4; *(uint32_t*)(tagaddr) = CRYP_DataOut(); tagaddr+=4; *(uint32_t*)(tagaddr) = CRYP_DataOut(); tagaddr+=4; } /* Disable Crypto */ CRYP_Cmd(DISABLE); return status; } /** * @brief Encrypt and decrypt using AES in CCM Mode. The GCM and CCM modes * are available only on STM32F437x Devices. * @param Mode: encryption or decryption Mode. * This parameter can be one of the following values: * @arg MODE_ENCRYPT: Encryption * @arg MODE_DECRYPT: Decryption * @param Nonce: the nounce used for AES algorithm. It shall be unique for each processing. * @param Key: Key used for AES algorithm. * @param Keysize: length of the Key, must be a 128, 192 or 256. * @param Input: pointer to the Input buffer. * @param Ilength: length of the Input buffer in bytes, must be a multiple of 16. * @param Header: pointer to the header buffer. * @param Hlength: length of the header buffer in bytes. * @param HBuffer: pointer to temporary buffer used to append the header * HBuffer size must be equal to Hlength + 21 * @param Output: pointer to the returned buffer. * @param AuthTAG: pointer to the authentication TAG buffer. * @param TAGSize: the size of the TAG (called also MAC). * @retval An ErrorStatus enumeration value: * - SUCCESS: Operation done * - ERROR: Operation failed */ ErrorStatus CRYP_AES_CCM(uint8_t Mode, uint8_t* Nonce, uint32_t NonceSize, uint8_t *Key, uint16_t Keysize, uint8_t *Input, uint32_t ILength, uint8_t *Header, uint32_t HLength, uint8_t *HBuffer, uint8_t *Output, uint8_t *AuthTAG, uint32_t TAGSize) { CRYP_InitTypeDef AES_CRYP_InitStructure; CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure; CRYP_IVInitTypeDef AES_CRYP_IVInitStructure; __IO uint32_t counter = 0; uint32_t busystatus = 0; ErrorStatus status = SUCCESS; uint32_t keyaddr = (uint32_t)Key; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; uint32_t headeraddr = (uint32_t)Header; uint32_t tagaddr = (uint32_t)AuthTAG; uint32_t headersize = HLength; uint32_t loopcounter = 0; uint32_t bufferidx = 0; uint8_t blockb0[16] = {0};/* Block B0 */ uint8_t ctr[16] = {0}; /* Counter */ uint32_t temptag[4] = {0}; /* temporary TAG (MAC) */ uint32_t ctraddr = (uint32_t)ctr; uint32_t b0addr = (uint32_t)blockb0; /************************ Formatting the header block ***********************/ if(headersize != 0) { /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */ if(headersize < 65280) { HBuffer[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF); HBuffer[bufferidx++] = (uint8_t) ((headersize) & 0xFF); headersize += 2; } else { /* header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */ HBuffer[bufferidx++] = 0xFF; HBuffer[bufferidx++] = 0xFE; HBuffer[bufferidx++] = headersize & 0xff000000; HBuffer[bufferidx++] = headersize & 0x00ff0000; HBuffer[bufferidx++] = headersize & 0x0000ff00; HBuffer[bufferidx++] = headersize & 0x000000ff; headersize += 6; } /* Copy the header buffer in internal buffer "HBuffer" */ for(loopcounter = 0; loopcounter < headersize; loopcounter++) { HBuffer[bufferidx++] = Header[loopcounter]; } /* Check if the header size is modulo 16 */ if ((headersize % 16) != 0) { /* Padd the header buffer with 0s till the HBuffer length is modulo 16 */ for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++) { HBuffer[loopcounter] = 0; } /* Set the header size to modulo 16 */ headersize = ((headersize/16) + 1) * 16; } /* set the pointer headeraddr to HBuffer */ headeraddr = (uint32_t)HBuffer; } /************************* Formatting the block B0 **************************/ if(headersize != 0) { blockb0[0] = 0x40; } /* Flags byte */ blockb0[0] |= 0u | (((( (uint8_t) TAGSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - NonceSize) - 1) & 0x07); for (loopcounter = 0; loopcounter < NonceSize; loopcounter++) { blockb0[loopcounter+1] = Nonce[loopcounter]; } for ( ; loopcounter < 13; loopcounter++) { blockb0[loopcounter+1] = 0; } blockb0[14] = ((ILength >> 8) & 0xFF); blockb0[15] = (ILength & 0xFF); /************************* Formatting the initial counter *******************/ /* Byte 0: Bits 7 and 6 are reserved and shall be set to 0 Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks are distinct from B0 Bits 0, 1, and 2 contain the same encoding of q as in B0 */ ctr[0] = blockb0[0] & 0x07; /* byte 1 to NonceSize is the IV (Nonce) */ for(loopcounter = 1; loopcounter < NonceSize + 1; loopcounter++) { ctr[loopcounter] = blockb0[loopcounter]; } /* Set the LSB to 1 */ ctr[15] |= 0x01; /* Crypto structures initialisation*/ CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure); switch(Keysize) { case 128: AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); break; case 192: AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b; AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); break; case 256: AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b; AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); break; default: break; } /* CRYP Initialization Vectors */ AES_CRYP_IVInitStructure.CRYP_IV0Left = (__REV(*(uint32_t*)(ctraddr))); ctraddr+=4; AES_CRYP_IVInitStructure.CRYP_IV0Right= (__REV(*(uint32_t*)(ctraddr))); ctraddr+=4; AES_CRYP_IVInitStructure.CRYP_IV1Left = (__REV(*(uint32_t*)(ctraddr))); ctraddr+=4; AES_CRYP_IVInitStructure.CRYP_IV1Right= (__REV(*(uint32_t*)(ctraddr))); /*------------------ AES Encryption ------------------*/ if(Mode == MODE_ENCRYPT) /* AES encryption */ { /* Flush IN/OUT FIFOs */ CRYP_FIFOFlush(); /* Key Initialisation */ CRYP_KeyInit(&AES_CRYP_KeyInitStructure); /* CRYP Initialization Vectors */ CRYP_IVInit(&AES_CRYP_IVInitStructure); /* Crypto Init for Key preparation for decryption process */ AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CCM; AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; CRYP_Init(&AES_CRYP_InitStructure); /***************************** Init phase *********************************/ /* Select init phase */ CRYP_PhaseConfig(CRYP_Phase_Init); b0addr = (uint32_t)blockb0; /* Write the blockb0 block in the IN FIFO */ CRYP_DataIn((*(uint32_t*)(b0addr))); b0addr+=4; CRYP_DataIn((*(uint32_t*)(b0addr))); b0addr+=4; CRYP_DataIn((*(uint32_t*)(b0addr))); b0addr+=4; CRYP_DataIn((*(uint32_t*)(b0addr))); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); /* Wait for CRYPEN bit to be 0 */ while(CRYP_GetCmdStatus() == ENABLE) { } /***************************** header phase *******************************/ if(headersize != 0) { /* Select header phase */ CRYP_PhaseConfig(CRYP_Phase_Header); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); if(CRYP_GetCmdStatus() == DISABLE) { /* The CRYP peripheral clock is not enabled or the device doesn't embedd the CRYP peripheral (please check the device sales type. */ return(ERROR); } for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) { /* Wait until the IFEM flag is reset */ while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) { } /* Write the Input block in the IN FIFO */ CRYP_DataIn(*(uint32_t*)(headeraddr)); headeraddr+=4; CRYP_DataIn(*(uint32_t*)(headeraddr)); headeraddr+=4; CRYP_DataIn(*(uint32_t*)(headeraddr)); headeraddr+=4; CRYP_DataIn(*(uint32_t*)(headeraddr)); headeraddr+=4; } /* Wait until the complete message has been processed */ counter = 0; do { busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); counter++; }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); if (busystatus != RESET) { status = ERROR; } } /**************************** payload phase *******************************/ if(ILength != 0) { /* Select payload phase */ CRYP_PhaseConfig(CRYP_Phase_Payload); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); if(CRYP_GetCmdStatus() == DISABLE) { /* The CRYP peripheral clock is not enabled or the device doesn't embedd the CRYP peripheral (please check the device sales type. */ return(ERROR); } for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16) { /* Wait until the IFEM flag is reset */ while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) { } /* Write the Input block in the IN FIFO */ CRYP_DataIn(*(uint32_t*)(inputaddr)); inputaddr+=4; CRYP_DataIn(*(uint32_t*)(inputaddr)); inputaddr+=4; CRYP_DataIn(*(uint32_t*)(inputaddr)); inputaddr+=4; CRYP_DataIn(*(uint32_t*)(inputaddr)); inputaddr+=4; /* Wait until the complete message has been processed */ counter = 0; do { busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); counter++; }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); if (busystatus != RESET) { status = ERROR; } else { /* Wait until the OFNE flag is reset */ while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) { } /* Read the Output block from the Output FIFO */ *(uint32_t*)(outputaddr) = CRYP_DataOut(); outputaddr+=4; *(uint32_t*)(outputaddr) = CRYP_DataOut(); outputaddr+=4; *(uint32_t*)(outputaddr) = CRYP_DataOut(); outputaddr+=4; *(uint32_t*)(outputaddr) = CRYP_DataOut(); outputaddr+=4; } } } /***************************** final phase ********************************/ /* Select final phase */ CRYP_PhaseConfig(CRYP_Phase_Final); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); if(CRYP_GetCmdStatus() == DISABLE) { /* The CRYP peripheral clock is not enabled or the device doesn't embedd the CRYP peripheral (please check the device sales type. */ return(ERROR); } ctraddr = (uint32_t)ctr; /* Write the counter block in the IN FIFO */ CRYP_DataIn(*(uint32_t*)(ctraddr)); ctraddr+=4; CRYP_DataIn(*(uint32_t*)(ctraddr)); ctraddr+=4; CRYP_DataIn(*(uint32_t*)(ctraddr)); ctraddr+=4; /* Reset bit 0 (after 8-bit swap) is equivalent to reset bit 24 (before 8-bit swap) */ CRYP_DataIn(*(uint32_t*)(ctraddr) & 0xfeffffff); /* Wait until the OFNE flag is reset */ while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) { } /* Read the Auth TAG in the IN FIFO */ temptag[0] = CRYP_DataOut(); temptag[1] = CRYP_DataOut(); temptag[2] = CRYP_DataOut(); temptag[3] = CRYP_DataOut(); } /*------------------ AES Decryption ------------------*/ else /* AES decryption */ { /* Flush IN/OUT FIFOs */ CRYP_FIFOFlush(); /* Key Initialisation */ CRYP_KeyInit(&AES_CRYP_KeyInitStructure); /* CRYP Initialization Vectors */ CRYP_IVInit(&AES_CRYP_IVInitStructure); /* Crypto Init for Key preparation for decryption process */ AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CCM; AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; CRYP_Init(&AES_CRYP_InitStructure); /***************************** Init phase *********************************/ /* Select init phase */ CRYP_PhaseConfig(CRYP_Phase_Init); b0addr = (uint32_t)blockb0; /* Write the blockb0 block in the IN FIFO */ CRYP_DataIn((*(uint32_t*)(b0addr))); b0addr+=4; CRYP_DataIn((*(uint32_t*)(b0addr))); b0addr+=4; CRYP_DataIn((*(uint32_t*)(b0addr))); b0addr+=4; CRYP_DataIn((*(uint32_t*)(b0addr))); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); /* Wait for CRYPEN bit to be 0 */ while(CRYP_GetCmdStatus() == ENABLE) { } /***************************** header phase *******************************/ if(headersize != 0) { /* Select header phase */ CRYP_PhaseConfig(CRYP_Phase_Header); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); if(CRYP_GetCmdStatus() == DISABLE) { /* The CRYP peripheral clock is not enabled or the device doesn't embedd the CRYP peripheral (please check the device sales type. */ return(ERROR); } for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) { /* Wait until the IFEM flag is reset */ while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) { } /* Write the Input block in the IN FIFO */ CRYP_DataIn(*(uint32_t*)(headeraddr)); headeraddr+=4; CRYP_DataIn(*(uint32_t*)(headeraddr)); headeraddr+=4; CRYP_DataIn(*(uint32_t*)(headeraddr)); headeraddr+=4; CRYP_DataIn(*(uint32_t*)(headeraddr)); headeraddr+=4; } /* Wait until the complete message has been processed */ counter = 0; do { busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); counter++; }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); if (busystatus != RESET) { status = ERROR; } } /**************************** payload phase *******************************/ if(ILength != 0) { /* Select payload phase */ CRYP_PhaseConfig(CRYP_Phase_Payload); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); if(CRYP_GetCmdStatus() == DISABLE) { /* The CRYP peripheral clock is not enabled or the device doesn't embedd the CRYP peripheral (please check the device sales type. */ return(ERROR); } for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16) { /* Wait until the IFEM flag is reset */ while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) { } /* Write the Input block in the IN FIFO */ CRYP_DataIn(*(uint32_t*)(inputaddr)); inputaddr+=4; CRYP_DataIn(*(uint32_t*)(inputaddr)); inputaddr+=4; CRYP_DataIn(*(uint32_t*)(inputaddr)); inputaddr+=4; CRYP_DataIn(*(uint32_t*)(inputaddr)); inputaddr+=4; /* Wait until the complete message has been processed */ counter = 0; do { busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); counter++; }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); if (busystatus != RESET) { status = ERROR; } else { /* Wait until the OFNE flag is reset */ while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) { } /* Read the Output block from the Output FIFO */ *(uint32_t*)(outputaddr) = CRYP_DataOut(); outputaddr+=4; *(uint32_t*)(outputaddr) = CRYP_DataOut(); outputaddr+=4; *(uint32_t*)(outputaddr) = CRYP_DataOut(); outputaddr+=4; *(uint32_t*)(outputaddr) = CRYP_DataOut(); outputaddr+=4; } } } /***************************** final phase ********************************/ /* Select final phase */ CRYP_PhaseConfig(CRYP_Phase_Final); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); if(CRYP_GetCmdStatus() == DISABLE) { /* The CRYP peripheral clock is not enabled or the device doesn't embedd the CRYP peripheral (please check the device sales type. */ return(ERROR); } ctraddr = (uint32_t)ctr; /* Write the counter block in the IN FIFO */ CRYP_DataIn(*(uint32_t*)(ctraddr)); ctraddr+=4; CRYP_DataIn(*(uint32_t*)(ctraddr)); ctraddr+=4; CRYP_DataIn(*(uint32_t*)(ctraddr)); ctraddr+=4; /* Reset bit 0 (after 8-bit swap) is equivalent to reset bit 24 (before 8-bit swap) */ CRYP_DataIn(*(uint32_t*)(ctraddr) & 0xfeffffff); /* Wait until the OFNE flag is reset */ while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) { } /* Read the Authentaication TAG (MAC) in the IN FIFO */ temptag[0] = CRYP_DataOut(); temptag[1] = CRYP_DataOut(); temptag[2] = CRYP_DataOut(); temptag[3] = CRYP_DataOut(); } /* Copy temporary authentication TAG in user TAG buffer */ for(loopcounter = 0; (loopcounter < TAGSize); loopcounter++) { /* Set the authentication TAG buffer */ *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter); } /* Disable Crypto */ CRYP_Cmd(DISABLE); return status; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c ================================================ /** ****************************************************************************** * @file stm32f4xx_cryp_des.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides high level functions to encrypt and decrypt an * input message using DES in ECB/CBC modes. * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP * peripheral. * @verbatim =================================================================== ##### How to use this driver ##### =================================================================== [..] (#) Enable The CRYP controller clock using RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. (#) Encrypt and decrypt using DES in ECB Mode using CRYP_DES_ECB() function. (#) Encrypt and decrypt using DES in CBC Mode using CRYP_DES_CBC() function. @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_cryp.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup CRYP * @brief CRYP driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define DESBUSY_TIMEOUT ((uint32_t) 0x00010000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup CRYP_Private_Functions * @{ */ /** @defgroup CRYP_Group8 High Level DES functions * @brief High Level DES functions * @verbatim =============================================================================== ##### High Level DES functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Encrypt and decrypt using DES in ECB Mode * @param Mode: encryption or decryption Mode. * This parameter can be one of the following values: * @arg MODE_ENCRYPT: Encryption * @arg MODE_DECRYPT: Decryption * @param Key: Key used for DES algorithm. * @param Ilength: length of the Input buffer, must be a multiple of 8. * @param Input: pointer to the Input buffer. * @param Output: pointer to the returned buffer. * @retval An ErrorStatus enumeration value: * - SUCCESS: Operation done * - ERROR: Operation failed */ ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, uint32_t Ilength, uint8_t *Output) { CRYP_InitTypeDef DES_CRYP_InitStructure; CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure; __IO uint32_t counter = 0; uint32_t busystatus = 0; ErrorStatus status = SUCCESS; uint32_t keyaddr = (uint32_t)Key; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; uint32_t i = 0; /* Crypto structures initialisation*/ CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure); /* Crypto Init for Encryption process */ if( Mode == MODE_ENCRYPT ) /* DES encryption */ { DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; } else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */ { DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; } DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB; DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; CRYP_Init(&DES_CRYP_InitStructure); /* Key Initialisation */ DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); CRYP_KeyInit(& DES_CRYP_KeyInitStructure); /* Flush IN/OUT FIFO */ CRYP_FIFOFlush(); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); if(CRYP_GetCmdStatus() == DISABLE) { /* The CRYP peripheral clock is not enabled or the device doesn't embedd the CRYP peripheral (please check the device sales type. */ return(ERROR); } for(i=0; ((i
© COPYRIGHT 2013 STMicroelectronics
* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_cryp.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup CRYP * @brief CRYP driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define TDESBUSY_TIMEOUT ((uint32_t) 0x00010000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup CRYP_Private_Functions * @{ */ /** @defgroup CRYP_Group7 High Level TDES functions * @brief High Level TDES functions * @verbatim =============================================================================== ##### High Level TDES functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Encrypt and decrypt using TDES in ECB Mode * @param Mode: encryption or decryption Mode. * This parameter can be one of the following values: * @arg MODE_ENCRYPT: Encryption * @arg MODE_DECRYPT: Decryption * @param Key: Key used for TDES algorithm. * @param Ilength: length of the Input buffer, must be a multiple of 8. * @param Input: pointer to the Input buffer. * @param Output: pointer to the returned buffer. * @retval An ErrorStatus enumeration value: * - SUCCESS: Operation done * - ERROR: Operation failed */ ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input, uint32_t Ilength, uint8_t *Output) { CRYP_InitTypeDef TDES_CRYP_InitStructure; CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure; __IO uint32_t counter = 0; uint32_t busystatus = 0; ErrorStatus status = SUCCESS; uint32_t keyaddr = (uint32_t)Key; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; uint32_t i = 0; /* Crypto structures initialisation*/ CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure); /* Crypto Init for Encryption process */ if(Mode == MODE_ENCRYPT) /* TDES encryption */ { TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; } else /*if(Mode == MODE_DECRYPT)*/ /* TDES decryption */ { TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; } TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; CRYP_Init(&TDES_CRYP_InitStructure); /* Key Initialisation */ TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); CRYP_KeyInit(& TDES_CRYP_KeyInitStructure); /* Flush IN/OUT FIFO */ CRYP_FIFOFlush(); /* Enable Crypto processor */ CRYP_Cmd(ENABLE); if(CRYP_GetCmdStatus() == DISABLE) { /* The CRYP peripheral clock is not enabled or the device doesn't embedd the CRYP peripheral (please check the device sales type. */ return(ERROR); } for(i=0; ((i
© COPYRIGHT 2013 STMicroelectronics
* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_dac.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup DAC * @brief DAC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* CR register Mask */ #define CR_CLEAR_MASK ((uint32_t)0x00000FFE) /* DAC Dual Channels SWTRIG masks */ #define DUAL_SWTRIG_SET ((uint32_t)0x00000003) #define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) /* DHR registers offsets */ #define DHR12R1_OFFSET ((uint32_t)0x00000008) #define DHR12R2_OFFSET ((uint32_t)0x00000014) #define DHR12RD_OFFSET ((uint32_t)0x00000020) /* DOR register offset */ #define DOR_OFFSET ((uint32_t)0x0000002C) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup DAC_Private_Functions * @{ */ /** @defgroup DAC_Group1 DAC channels configuration * @brief DAC channels configuration: trigger, output buffer, data format * @verbatim =============================================================================== ##### DAC channels configuration: trigger, output buffer, data format ##### =============================================================================== @endverbatim * @{ */ /** * @brief Deinitializes the DAC peripheral registers to their default reset values. * @param None * @retval None */ void DAC_DeInit(void) { /* Enable DAC reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); /* Release DAC from reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); } /** * @brief Initializes the DAC peripheral according to the specified parameters * in the DAC_InitStruct. * @param DAC_Channel: the selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains * the configuration information for the specified DAC channel. * @retval None */ void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) { uint32_t tmpreg1 = 0, tmpreg2 = 0; /* Check the DAC parameters */ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); /*---------------------------- DAC CR Configuration --------------------------*/ /* Get the DAC CR value */ tmpreg1 = DAC->CR; /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); /* Configure for the selected DAC channel: buffer output, trigger, wave generation, mask/amplitude for wave generation */ /* Set TSELx and TENx bits according to DAC_Trigger value */ /* Set WAVEx bits according to DAC_WaveGeneration value */ /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ /* Set BOFFx bit according to DAC_OutputBuffer value */ tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \ DAC_InitStruct->DAC_OutputBuffer); /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << DAC_Channel; /* Write to DAC CR */ DAC->CR = tmpreg1; } /** * @brief Fills each DAC_InitStruct member with its default value. * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will * be initialized. * @retval None */ void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) { /*--------------- Reset DAC init structure parameters values -----------------*/ /* Initialize the DAC_Trigger member */ DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; /* Initialize the DAC_WaveGeneration member */ DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; /* Initialize the DAC_OutputBuffer member */ DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; } /** * @brief Enables or disables the specified DAC channel. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param NewState: new state of the DAC channel. * This parameter can be: ENABLE or DISABLE. * @note When the DAC channel is enabled the trigger source can no more be modified. * @retval None */ void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected DAC channel */ DAC->CR |= (DAC_CR_EN1 << DAC_Channel); } else { /* Disable the selected DAC channel */ DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel)); } } /** * @brief Enables or disables the selected DAC channel software trigger. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param NewState: new state of the selected DAC channel software trigger. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable software trigger for the selected DAC channel */ DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); } else { /* Disable software trigger for the selected DAC channel */ DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); } } /** * @brief Enables or disables simultaneously the two DAC channels software triggers. * @param NewState: new state of the DAC channels software triggers. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable software trigger for both DAC channels */ DAC->SWTRIGR |= DUAL_SWTRIG_SET; } else { /* Disable software trigger for both DAC channels */ DAC->SWTRIGR &= DUAL_SWTRIG_RESET; } } /** * @brief Enables or disables the selected DAC channel wave generation. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_Wave: specifies the wave type to enable or disable. * This parameter can be one of the following values: * @arg DAC_Wave_Noise: noise wave generation * @arg DAC_Wave_Triangle: triangle wave generation * @param NewState: new state of the selected DAC channel wave generation. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_WAVE(DAC_Wave)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected wave generation for the selected DAC channel */ DAC->CR |= DAC_Wave << DAC_Channel; } else { /* Disable the selected wave generation for the selected DAC channel */ DAC->CR &= ~(DAC_Wave << DAC_Channel); } } /** * @brief Set the specified data holding register value for DAC channel1. * @param DAC_Align: Specifies the data alignment for DAC channel1. * This parameter can be one of the following values: * @arg DAC_Align_8b_R: 8bit right data alignment selected * @arg DAC_Align_12b_L: 12bit left data alignment selected * @arg DAC_Align_12b_R: 12bit right data alignment selected * @param Data: Data to be loaded in the selected data holding register. * @retval None */ void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_DAC_ALIGN(DAC_Align)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t)DAC_BASE; tmp += DHR12R1_OFFSET + DAC_Align; /* Set the DAC channel1 selected data holding register */ *(__IO uint32_t *) tmp = Data; } /** * @brief Set the specified data holding register value for DAC channel2. * @param DAC_Align: Specifies the data alignment for DAC channel2. * This parameter can be one of the following values: * @arg DAC_Align_8b_R: 8bit right data alignment selected * @arg DAC_Align_12b_L: 12bit left data alignment selected * @arg DAC_Align_12b_R: 12bit right data alignment selected * @param Data: Data to be loaded in the selected data holding register. * @retval None */ void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_DAC_ALIGN(DAC_Align)); assert_param(IS_DAC_DATA(Data)); tmp = (uint32_t)DAC_BASE; tmp += DHR12R2_OFFSET + DAC_Align; /* Set the DAC channel2 selected data holding register */ *(__IO uint32_t *)tmp = Data; } /** * @brief Set the specified data holding register value for dual channel DAC. * @param DAC_Align: Specifies the data alignment for dual channel DAC. * This parameter can be one of the following values: * @arg DAC_Align_8b_R: 8bit right data alignment selected * @arg DAC_Align_12b_L: 12bit left data alignment selected * @arg DAC_Align_12b_R: 12bit right data alignment selected * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register. * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register. * @note In dual mode, a unique register access is required to write in both * DAC channels at the same time. * @retval None */ void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) { uint32_t data = 0, tmp = 0; /* Check the parameters */ assert_param(IS_DAC_ALIGN(DAC_Align)); assert_param(IS_DAC_DATA(Data1)); assert_param(IS_DAC_DATA(Data2)); /* Calculate and set dual DAC data holding register value */ if (DAC_Align == DAC_Align_8b_R) { data = ((uint32_t)Data2 << 8) | Data1; } else { data = ((uint32_t)Data2 << 16) | Data1; } tmp = (uint32_t)DAC_BASE; tmp += DHR12RD_OFFSET + DAC_Align; /* Set the dual DAC selected data holding register */ *(__IO uint32_t *)tmp = data; } /** * @brief Returns the last data output value of the selected DAC channel. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @retval The selected DAC channel data output value. */ uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); tmp = (uint32_t) DAC_BASE ; tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); /* Returns the DAC channel data output register value */ return (uint16_t) (*(__IO uint32_t*) tmp); } /** * @} */ /** @defgroup DAC_Group2 DMA management functions * @brief DMA management functions * @verbatim =============================================================================== ##### DMA management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified DAC channel DMA request. * @note When enabled DMA1 is generated when an external trigger (EXTI Line9, * TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param NewState: new state of the selected DAC channel DMA request. * This parameter can be: ENABLE or DISABLE. * @note The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be * already configured. * @note The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be * already configured. * @retval None */ void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected DAC channel DMA request */ DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); } else { /* Disable the selected DAC channel DMA request */ DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel)); } } /** * @} */ /** @defgroup DAC_Group3 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified DAC interrupts. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. * This parameter can be the following values: * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask * @note The DMA underrun occurs when a second external trigger arrives before the * acknowledgement for the first external trigger is received (first request). * @param NewState: new state of the specified DAC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_DAC_IT(DAC_IT)); if (NewState != DISABLE) { /* Enable the selected DAC interrupts */ DAC->CR |= (DAC_IT << DAC_Channel); } else { /* Disable the selected DAC interrupts */ DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); } } /** * @brief Checks whether the specified DAC flag is set or not. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_FLAG: specifies the flag to check. * This parameter can be only of the following value: * @arg DAC_FLAG_DMAUDR: DMA underrun flag * @note The DMA underrun occurs when a second external trigger arrives before the * acknowledgement for the first external trigger is received (first request). * @retval The new state of DAC_FLAG (SET or RESET). */ FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_FLAG(DAC_FLAG)); /* Check the status of the specified DAC flag */ if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) { /* DAC_FLAG is set */ bitstatus = SET; } else { /* DAC_FLAG is reset */ bitstatus = RESET; } /* Return the DAC_FLAG status */ return bitstatus; } /** * @brief Clears the DAC channel's pending flags. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_FLAG: specifies the flag to clear. * This parameter can be of the following value: * @arg DAC_FLAG_DMAUDR: DMA underrun flag * @note The DMA underrun occurs when a second external trigger arrives before the * acknowledgement for the first external trigger is received (first request). * @retval None */ void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_FLAG(DAC_FLAG)); /* Clear the selected DAC flags */ DAC->SR = (DAC_FLAG << DAC_Channel); } /** * @brief Checks whether the specified DAC interrupt has occurred or not. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_IT: specifies the DAC interrupt source to check. * This parameter can be the following values: * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask * @note The DMA underrun occurs when a second external trigger arrives before the * acknowledgement for the first external trigger is received (first request). * @retval The new state of DAC_IT (SET or RESET). */ ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) { ITStatus bitstatus = RESET; uint32_t enablestatus = 0; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_IT(DAC_IT)); /* Get the DAC_IT enable bit status */ enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; /* Check the status of the specified DAC interrupt */ if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) { /* DAC_IT is set */ bitstatus = SET; } else { /* DAC_IT is reset */ bitstatus = RESET; } /* Return the DAC_IT status */ return bitstatus; } /** * @brief Clears the DAC channel's interrupt pending bits. * @param DAC_Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_Channel_1: DAC Channel1 selected * @arg DAC_Channel_2: DAC Channel2 selected * @param DAC_IT: specifies the DAC interrupt pending bit to clear. * This parameter can be the following values: * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask * @note The DMA underrun occurs when a second external trigger arrives before the * acknowledgement for the first external trigger is received (first request). * @retval None */ void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(DAC_Channel)); assert_param(IS_DAC_IT(DAC_IT)); /* Clear the selected DAC interrupt pending bits */ DAC->SR = (DAC_IT << DAC_Channel); } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c ================================================ /** ****************************************************************************** * @file stm32f4xx_dbgmcu.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides all the DBGMCU firmware functions. ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_dbgmcu.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup DBGMCU * @brief DBGMCU driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup DBGMCU_Private_Functions * @{ */ /** * @brief Returns the device revision identifier. * @param None * @retval Device revision identifier */ uint32_t DBGMCU_GetREVID(void) { return(DBGMCU->IDCODE >> 16); } /** * @brief Returns the device identifier. * @param None * @retval Device identifier */ uint32_t DBGMCU_GetDEVID(void) { return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); } /** * @brief Configures low power mode behavior when the MCU is in Debug mode. * @param DBGMCU_Periph: specifies the low power mode. * This parameter can be any combination of the following values: * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode * @arg DBGMCU_STOP: Keep debugger connection during STOP mode * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode * @param NewState: new state of the specified low power mode in Debug mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { DBGMCU->CR |= DBGMCU_Periph; } else { DBGMCU->CR &= ~DBGMCU_Periph; } } /** * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. * @param DBGMCU_Periph: specifies the APB1 peripheral. * This parameter can be any combination of the following values: * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted. * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted * @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted * @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted * This parameter can be: ENABLE or DISABLE. * @retval None */ void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { DBGMCU->APB1FZ |= DBGMCU_Periph; } else { DBGMCU->APB1FZ &= ~DBGMCU_Periph; } } /** * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. * @param DBGMCU_Periph: specifies the APB2 peripheral. * This parameter can be any combination of the following values: * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted * @param NewState: new state of the specified peripheral in Debug mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { DBGMCU->APB2FZ |= DBGMCU_Periph; } else { DBGMCU->APB2FZ &= ~DBGMCU_Periph; } } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c ================================================ /** ****************************************************************************** * @file stm32f4xx_dcmi.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the DCMI peripheral: * + Initialization and Configuration * + Image capture functions * + Interrupts and flags management * @verbatim =============================================================================== ##### How to use this driver ##### =============================================================================== [..] The sequence below describes how to use this driver to capture image from a camera module connected to the DCMI Interface. This sequence does not take into account the configuration of the camera module, which should be made before to configure and enable the DCMI to capture images. (#) Enable the clock for the DCMI and associated GPIOs using the following functions: RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE); RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); (#) DCMI pins configuration (++) Connect the involved DCMI pins to AF13 using the following function GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI); (++) Configure these DCMI pins in alternate function mode by calling the function GPIO_Init(); (#) Declare a DCMI_InitTypeDef structure, for example: DCMI_InitTypeDef DCMI_InitStructure; and fill the DCMI_InitStructure variable with the allowed values of the structure member. (#) Initialize the DCMI interface by calling the function DCMI_Init(&DCMI_InitStructure); (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR register to the destination memory buffer. (#) Enable DCMI interface using the function DCMI_Cmd(ENABLE); (#) Start the image capture using the function DCMI_CaptureCmd(ENABLE); (#) At this stage the DCMI interface waits for the first start of frame, then a DMA request is generated continuously/once (depending on the mode used, Continuous/Snapshot) to transfer the received data into the destination memory. -@- If you need to capture only a rectangular window from the received image, you have to use the DCMI_CROPConfig() function to configure the coordinates and size of the window to be captured, then enable the Crop feature using DCMI_CROPCmd(ENABLE); In this case, the Crop configuration should be made before to enable and start the DCMI interface. @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_dcmi.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup DCMI * @brief DCMI driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup DCMI_Private_Functions * @{ */ /** @defgroup DCMI_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Deinitializes the DCMI registers to their default reset values. * @param None * @retval None */ void DCMI_DeInit(void) { DCMI->CR = 0x0; DCMI->IER = 0x0; DCMI->ICR = 0x1F; DCMI->ESCR = 0x0; DCMI->ESUR = 0x0; DCMI->CWSTRTR = 0x0; DCMI->CWSIZER = 0x0; } /** * @brief Initializes the DCMI according to the specified parameters in the DCMI_InitStruct. * @param DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains * the configuration information for the DCMI. * @retval None */ void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct) { uint32_t temp = 0x0; /* Check the parameters */ assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode)); assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode)); assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity)); assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity)); assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity)); assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate)); assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode)); /* The DCMI configuration registers should be programmed correctly before enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */ DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE); /* Reset the old DCMI configuration */ temp = DCMI->CR; temp &= ~((uint32_t)DCMI_CR_CM | DCMI_CR_ESS | DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1); /* Sets the new configuration of the DCMI peripheral */ temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode | DCMI_InitStruct->DCMI_SynchroMode | DCMI_InitStruct->DCMI_PCKPolarity | DCMI_InitStruct->DCMI_VSPolarity | DCMI_InitStruct->DCMI_HSPolarity | DCMI_InitStruct->DCMI_CaptureRate | DCMI_InitStruct->DCMI_ExtendedDataMode); DCMI->CR = temp; } /** * @brief Fills each DCMI_InitStruct member with its default value. * @param DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will * be initialized. * @retval None */ void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct) { /* Set the default configuration */ DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous; DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware; DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling; DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low; DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low; DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame; DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b; } /** * @brief Initializes the DCMI peripheral CROP mode according to the specified * parameters in the DCMI_CROPInitStruct. * @note This function should be called before to enable and start the DCMI interface. * @param DCMI_CROPInitStruct: pointer to a DCMI_CROPInitTypeDef structure that * contains the configuration information for the DCMI peripheral CROP mode. * @retval None */ void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct) { /* Sets the CROP window coordinates */ DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount | ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16)); /* Sets the CROP window size */ DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount | ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16)); } /** * @brief Enables or disables the DCMI Crop feature. * @note This function should be called before to enable and start the DCMI interface. * @param NewState: new state of the DCMI Crop feature. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DCMI_CROPCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the DCMI Crop feature */ DCMI->CR |= (uint32_t)DCMI_CR_CROP; } else { /* Disable the DCMI Crop feature */ DCMI->CR &= ~(uint32_t)DCMI_CR_CROP; } } /** * @brief Sets the embedded synchronization codes * @param DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that * contains the embedded synchronization codes for the DCMI peripheral. * @retval None */ void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct) { DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode | ((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)| ((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)| ((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24)); } /** * @brief Enables or disables the DCMI JPEG format. * @note The Crop and Embedded Synchronization features cannot be used in this mode. * @param NewState: new state of the DCMI JPEG format. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DCMI_JPEGCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the DCMI JPEG format */ DCMI->CR |= (uint32_t)DCMI_CR_JPEG; } else { /* Disable the DCMI JPEG format */ DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG; } } /** * @} */ /** @defgroup DCMI_Group2 Image capture functions * @brief Image capture functions * @verbatim =============================================================================== ##### Image capture functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the DCMI interface. * @param NewState: new state of the DCMI interface. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DCMI_Cmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the DCMI by setting ENABLE bit */ DCMI->CR |= (uint32_t)DCMI_CR_ENABLE; } else { /* Disable the DCMI by clearing ENABLE bit */ DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE; } } /** * @brief Enables or disables the DCMI Capture. * @param NewState: new state of the DCMI capture. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DCMI_CaptureCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the DCMI Capture */ DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE; } else { /* Disable the DCMI Capture */ DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE; } } /** * @brief Reads the data stored in the DR register. * @param None * @retval Data register value */ uint32_t DCMI_ReadData(void) { return DCMI->DR; } /** * @} */ /** @defgroup DCMI_Group3 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the DCMI interface interrupts. * @param DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask * @arg DCMI_IT_OVF: Overflow interrupt mask * @arg DCMI_IT_ERR: Synchronization error interrupt mask * @arg DCMI_IT_VSYNC: VSYNC interrupt mask * @arg DCMI_IT_LINE: Line interrupt mask * @param NewState: new state of the specified DCMI interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DCMI_CONFIG_IT(DCMI_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the Interrupt sources */ DCMI->IER |= DCMI_IT; } else { /* Disable the Interrupt sources */ DCMI->IER &= (uint16_t)(~DCMI_IT); } } /** * @brief Checks whether the DCMI interface flag is set or not. * @param DCMI_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask * @arg DCMI_FLAG_LINERI: Line Raw flag mask * @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask * @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask * @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask * @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask * @arg DCMI_FLAG_LINEMI: Line Masked flag mask * @arg DCMI_FLAG_HSYNC: HSYNC flag mask * @arg DCMI_FLAG_VSYNC: VSYNC flag mask * @arg DCMI_FLAG_FNE: Fifo not empty flag mask * @retval The new state of DCMI_FLAG (SET or RESET). */ FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG) { FlagStatus bitstatus = RESET; uint32_t dcmireg, tempreg = 0; /* Check the parameters */ assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG)); /* Get the DCMI register index */ dcmireg = (((uint16_t)DCMI_FLAG) >> 12); if (dcmireg == 0x00) /* The FLAG is in RISR register */ { tempreg= DCMI->RISR; } else if (dcmireg == 0x02) /* The FLAG is in SR register */ { tempreg = DCMI->SR; } else /* The FLAG is in MISR register */ { tempreg = DCMI->MISR; } if ((tempreg & DCMI_FLAG) != (uint16_t)RESET ) { bitstatus = SET; } else { bitstatus = RESET; } /* Return the DCMI_FLAG status */ return bitstatus; } /** * @brief Clears the DCMI's pending flags. * @param DCMI_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask * @arg DCMI_FLAG_LINERI: Line Raw flag mask * @retval None */ void DCMI_ClearFlag(uint16_t DCMI_FLAG) { /* Check the parameters */ assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG)); /* Clear the flag by writing in the ICR register 1 in the corresponding Flag position*/ DCMI->ICR = DCMI_FLAG; } /** * @brief Checks whether the DCMI interrupt has occurred or not. * @param DCMI_IT: specifies the DCMI interrupt source to check. * This parameter can be one of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask * @arg DCMI_IT_OVF: Overflow interrupt mask * @arg DCMI_IT_ERR: Synchronization error interrupt mask * @arg DCMI_IT_VSYNC: VSYNC interrupt mask * @arg DCMI_IT_LINE: Line interrupt mask * @retval The new state of DCMI_IT (SET or RESET). */ ITStatus DCMI_GetITStatus(uint16_t DCMI_IT) { ITStatus bitstatus = RESET; uint32_t itstatus = 0; /* Check the parameters */ assert_param(IS_DCMI_GET_IT(DCMI_IT)); itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */ if ((itstatus != (uint16_t)RESET)) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the DCMI's interrupt pending bits. * @param DCMI_IT: specifies the DCMI interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask * @arg DCMI_IT_OVF: Overflow interrupt mask * @arg DCMI_IT_ERR: Synchronization error interrupt mask * @arg DCMI_IT_VSYNC: VSYNC interrupt mask * @arg DCMI_IT_LINE: Line interrupt mask * @retval None */ void DCMI_ClearITPendingBit(uint16_t DCMI_IT) { /* Clear the interrupt pending Bit by writing in the ICR register 1 in the corresponding pending Bit position*/ DCMI->ICR = DCMI_IT; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c ================================================ /** ****************************************************************************** * @file stm32f4xx_dma.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Direct Memory Access controller (DMA): * + Initialization and Configuration * + Data Counter * + Double Buffer mode configuration and command * + Interrupts and flags management * @verbatim =============================================================================== ##### How to use this driver ##### =============================================================================== [..] (#) Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE) function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE) function for DMA2. (#) Enable and configure the peripheral to be connected to the DMA Stream (except for internal SRAM / FLASH memories: no initialization is necessary). (#) For a given Stream, program the required configuration through following parameters: Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination data formats, Circular or Normal mode, Stream Priority level, Source and Destination Incrementation mode, FIFO mode and its Threshold (if needed), Burst mode for Source and/or Destination (if needed) using the DMA_Init() function. To avoid filling unneccessary fields, you can call DMA_StructInit() function to initialize a given structure with default values (reset values), the modify only necessary fields (ie. Source and Destination addresses, Transfer size and Data Formats). (#) Enable the NVIC and the corresponding interrupt(s) using the function DMA_ITConfig() if you need to use DMA interrupts. (#) Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring the second Memory address and the first Memory to be used through the function DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function DMA_DoubleBufferModeCmd(). These operations must be done before step 6. (#) Enable the DMA stream using the DMA_Cmd() function. (#) Activate the needed Stream Request using PPP_DMACmd() function for any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) The function allowing this operation is provided in each PPP peripheral driver (ie. SPI_DMACmd for SPI peripheral). Once the Stream is enabled, it is not possible to modify its configuration unless the stream is stopped and disabled. After enabling the Stream, it is advised to monitor the EN bit status using the function DMA_GetCmdStatus(). In case of configuration errors or bus errors this bit will remain reset and all transfers on this Stream will remain on hold. (#) Optionally, you can configure the number of data to be transferred when the Stream is disabled (ie. after each Transfer Complete event or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). And you can get the number of remaining data to be transferred using the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is enabled and running). (#) To control DMA events you can use one of the following two methods: (##) Check on DMA Stream flags using the function DMA_GetFlagStatus(). (##) Use DMA interrupts through the function DMA_ITConfig() at initialization phase and DMA_GetITStatus() function into interrupt routines in communication phase. [..] After checking on a flag you should clear it using DMA_ClearFlag() function. And after checking on an interrupt event you should clear it using DMA_ClearITPendingBit() function. (#) Optionally, if Circular mode and Double Buffer mode are enabled, you can modify the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that the Memory Address to be modified is not the one currently in use by DMA Stream. This condition can be monitored using the function DMA_GetCurrentMemoryTarget(). (#) Optionally, Pause-Resume operations may be performed: The DMA_Cmd() function may be used to perform Pause-Resume operation. When a transfer is ongoing, calling this function to disable the Stream will cause the transfer to be paused. All configuration registers and the number of remaining data will be preserved. When calling again this function to re-enable the Stream, the transfer will be resumed from the point where it was paused. -@- Memory-to-Memory transfer is possible by setting the address of the memory into the Peripheral registers. In this mode, Circular mode and Double Buffer mode are not allowed. -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set Half-Word data size for the peripheral to access its data register and set Word data size for the Memory to gain in access time. Each two Half-words will be packed and written in a single access to a Word in the Memory). -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source and Destination. In this case the Peripheral Data Size will be applied to both Source and Destination. @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_dma.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup DMA * @brief DMA driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Masks Definition */ #define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \ DMA_SxCR_TEIE | DMA_SxCR_DMEIE) #define DMA_Stream0_IT_MASK (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \ DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \ DMA_LISR_TCIF0) #define DMA_Stream1_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 6) #define DMA_Stream2_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 16) #define DMA_Stream3_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 22) #define DMA_Stream4_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000) #define DMA_Stream5_IT_MASK (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000) #define DMA_Stream6_IT_MASK (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000) #define DMA_Stream7_IT_MASK (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000) #define TRANSFER_IT_MASK (uint32_t)0x0F3C0F3C #define HIGH_ISR_MASK (uint32_t)0x20000000 #define RESERVED_MASK (uint32_t)0x0F7D0F7D /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup DMA_Private_Functions * @{ */ /** @defgroup DMA_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This subsection provides functions allowing to initialize the DMA Stream source and destination addresses, incrementation and data sizes, transfer direction, buffer size, circular/normal mode selection, memory-to-memory mode selection and Stream priority value. [..] The DMA_Init() function follows the DMA configuration procedures as described in reference manual (RM0090) except the first point: waiting on EN bit to be reset. This condition should be checked by user application using the function DMA_GetCmdStatus() before calling the DMA_Init() function. @endverbatim * @{ */ /** * @brief Deinitialize the DMAy Streamx registers to their default reset values. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @retval None */ void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); /* Disable the selected DMAy Streamx */ DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN); /* Reset DMAy Streamx control register */ DMAy_Streamx->CR = 0; /* Reset DMAy Streamx Number of Data to Transfer register */ DMAy_Streamx->NDTR = 0; /* Reset DMAy Streamx peripheral address register */ DMAy_Streamx->PAR = 0; /* Reset DMAy Streamx memory 0 address register */ DMAy_Streamx->M0AR = 0; /* Reset DMAy Streamx memory 1 address register */ DMAy_Streamx->M1AR = 0; /* Reset DMAy Streamx FIFO control register */ DMAy_Streamx->FCR = (uint32_t)0x00000021; /* Reset interrupt pending bits for the selected stream */ if (DMAy_Streamx == DMA1_Stream0) { /* Reset interrupt pending bits for DMA1 Stream0 */ DMA1->LIFCR = DMA_Stream0_IT_MASK; } else if (DMAy_Streamx == DMA1_Stream1) { /* Reset interrupt pending bits for DMA1 Stream1 */ DMA1->LIFCR = DMA_Stream1_IT_MASK; } else if (DMAy_Streamx == DMA1_Stream2) { /* Reset interrupt pending bits for DMA1 Stream2 */ DMA1->LIFCR = DMA_Stream2_IT_MASK; } else if (DMAy_Streamx == DMA1_Stream3) { /* Reset interrupt pending bits for DMA1 Stream3 */ DMA1->LIFCR = DMA_Stream3_IT_MASK; } else if (DMAy_Streamx == DMA1_Stream4) { /* Reset interrupt pending bits for DMA1 Stream4 */ DMA1->HIFCR = DMA_Stream4_IT_MASK; } else if (DMAy_Streamx == DMA1_Stream5) { /* Reset interrupt pending bits for DMA1 Stream5 */ DMA1->HIFCR = DMA_Stream5_IT_MASK; } else if (DMAy_Streamx == DMA1_Stream6) { /* Reset interrupt pending bits for DMA1 Stream6 */ DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK; } else if (DMAy_Streamx == DMA1_Stream7) { /* Reset interrupt pending bits for DMA1 Stream7 */ DMA1->HIFCR = DMA_Stream7_IT_MASK; } else if (DMAy_Streamx == DMA2_Stream0) { /* Reset interrupt pending bits for DMA2 Stream0 */ DMA2->LIFCR = DMA_Stream0_IT_MASK; } else if (DMAy_Streamx == DMA2_Stream1) { /* Reset interrupt pending bits for DMA2 Stream1 */ DMA2->LIFCR = DMA_Stream1_IT_MASK; } else if (DMAy_Streamx == DMA2_Stream2) { /* Reset interrupt pending bits for DMA2 Stream2 */ DMA2->LIFCR = DMA_Stream2_IT_MASK; } else if (DMAy_Streamx == DMA2_Stream3) { /* Reset interrupt pending bits for DMA2 Stream3 */ DMA2->LIFCR = DMA_Stream3_IT_MASK; } else if (DMAy_Streamx == DMA2_Stream4) { /* Reset interrupt pending bits for DMA2 Stream4 */ DMA2->HIFCR = DMA_Stream4_IT_MASK; } else if (DMAy_Streamx == DMA2_Stream5) { /* Reset interrupt pending bits for DMA2 Stream5 */ DMA2->HIFCR = DMA_Stream5_IT_MASK; } else if (DMAy_Streamx == DMA2_Stream6) { /* Reset interrupt pending bits for DMA2 Stream6 */ DMA2->HIFCR = DMA_Stream6_IT_MASK; } else { if (DMAy_Streamx == DMA2_Stream7) { /* Reset interrupt pending bits for DMA2 Stream7 */ DMA2->HIFCR = DMA_Stream7_IT_MASK; } } } /** * @brief Initializes the DMAy Streamx according to the specified parameters in * the DMA_InitStruct structure. * @note Before calling this function, it is recommended to check that the Stream * is actually disabled using the function DMA_GetCmdStatus(). * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel)); assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR)); assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode)); assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold)); assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst)); /*------------------------- DMAy Streamx CR Configuration ------------------*/ /* Get the DMAy_Streamx CR value */ tmpreg = DMAy_Streamx->CR; /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR)); /* Configure DMAy Streamx: */ /* Set CHSEL bits according to DMA_CHSEL value */ /* Set DIR bits according to DMA_DIR value */ /* Set PINC bit according to DMA_PeripheralInc value */ /* Set MINC bit according to DMA_MemoryInc value */ /* Set PSIZE bits according to DMA_PeripheralDataSize value */ /* Set MSIZE bits according to DMA_MemoryDataSize value */ /* Set CIRC bit according to DMA_Mode value */ /* Set PL bits according to DMA_Priority value */ /* Set MBURST bits according to DMA_MemoryBurst value */ /* Set PBURST bits according to DMA_PeripheralBurst value */ tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst; /* Write to DMAy Streamx CR register */ DMAy_Streamx->CR = tmpreg; /*------------------------- DMAy Streamx FCR Configuration -----------------*/ /* Get the DMAy_Streamx FCR value */ tmpreg = DMAy_Streamx->FCR; /* Clear DMDIS and FTH bits */ tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); /* Configure DMAy Streamx FIFO: Set DMDIS bits according to DMA_FIFOMode value Set FTH bits according to DMA_FIFOThreshold value */ tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold; /* Write to DMAy Streamx CR */ DMAy_Streamx->FCR = tmpreg; /*------------------------- DMAy Streamx NDTR Configuration ----------------*/ /* Write to DMAy Streamx NDTR register */ DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize; /*------------------------- DMAy Streamx PAR Configuration -----------------*/ /* Write to DMAy Streamx PAR */ DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr; /*------------------------- DMAy Streamx M0AR Configuration ----------------*/ /* Write to DMAy Streamx M0AR */ DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr; } /** * @brief Fills each DMA_InitStruct member with its default value. * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will * be initialized. * @retval None */ void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) { /*-------------- Reset DMA init structure parameters values ----------------*/ /* Initialize the DMA_Channel member */ DMA_InitStruct->DMA_Channel = 0; /* Initialize the DMA_PeripheralBaseAddr member */ DMA_InitStruct->DMA_PeripheralBaseAddr = 0; /* Initialize the DMA_Memory0BaseAddr member */ DMA_InitStruct->DMA_Memory0BaseAddr = 0; /* Initialize the DMA_DIR member */ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory; /* Initialize the DMA_BufferSize member */ DMA_InitStruct->DMA_BufferSize = 0; /* Initialize the DMA_PeripheralInc member */ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; /* Initialize the DMA_MemoryInc member */ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; /* Initialize the DMA_PeripheralDataSize member */ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; /* Initialize the DMA_MemoryDataSize member */ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; /* Initialize the DMA_Mode member */ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; /* Initialize the DMA_Priority member */ DMA_InitStruct->DMA_Priority = DMA_Priority_Low; /* Initialize the DMA_FIFOMode member */ DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable; /* Initialize the DMA_FIFOThreshold member */ DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull; /* Initialize the DMA_MemoryBurst member */ DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single; /* Initialize the DMA_PeripheralBurst member */ DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single; } /** * @brief Enables or disables the specified DMAy Streamx. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param NewState: new state of the DMAy Streamx. * This parameter can be: ENABLE or DISABLE. * * @note This function may be used to perform Pause-Resume operation. When a * transfer is ongoing, calling this function to disable the Stream will * cause the transfer to be paused. All configuration registers and the * number of remaining data will be preserved. When calling again this * function to re-enable the Stream, the transfer will be resumed from * the point where it was paused. * * @note After configuring the DMA Stream (DMA_Init() function) and enabling the * stream, it is recommended to check (or wait until) the DMA Stream is * effectively enabled. A Stream may remain disabled if a configuration * parameter is wrong. * After disabling a DMA Stream, it is also recommended to check (or wait * until) the DMA Stream is effectively disabled. If a Stream is disabled * while a data transfer is ongoing, the current data will be transferred * and the Stream will be effectively disabled only after the transfer of * this single data is finished. * * @retval None */ void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected DMAy Streamx by setting EN bit */ DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN; } else { /* Disable the selected DMAy Streamx by clearing EN bit */ DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN; } } /** * @brief Configures, when the PINC (Peripheral Increment address mode) bit is * set, if the peripheral address should be incremented with the data * size (configured with PSIZE bits) or by a fixed offset equal to 4 * (32-bit aligned addresses). * * @note This function has no effect if the Peripheral Increment mode is disabled. * * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param DMA_Pincos: specifies the Peripheral increment offset size. * This parameter can be one of the following values: * @arg DMA_PINCOS_Psize: Peripheral address increment is done * accordingly to PSIZE parameter. * @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is * fixed to 4 (32-bit aligned addresses). * @retval None */ void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos)); /* Check the needed Peripheral increment offset */ if(DMA_Pincos != DMA_PINCOS_Psize) { /* Configure DMA_SxCR_PINCOS bit with the input parameter */ DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS; } else { /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */ DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS; } } /** * @brief Configures, when the DMAy Streamx is disabled, the flow controller for * the next transactions (Peripheral or Memory). * * @note Before enabling this feature, check if the used peripheral supports * the Flow Controller mode or not. * * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param DMA_FlowCtrl: specifies the DMA flow controller. * This parameter can be one of the following values: * @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is * the DMA controller. * @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller * is the peripheral. * @retval None */ void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl)); /* Check the needed flow controller */ if(DMA_FlowCtrl != DMA_FlowCtrl_Memory) { /* Configure DMA_SxCR_PFCTRL bit with the input parameter */ DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL; } else { /* Clear the PFCTRL bit: Memory is the flow controller */ DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL; } } /** * @} */ /** @defgroup DMA_Group2 Data Counter functions * @brief Data Counter functions * @verbatim =============================================================================== ##### Data Counter functions ##### =============================================================================== [..] This subsection provides function allowing to configure and read the buffer size (number of data to be transferred). [..] The DMA data counter can be written only when the DMA Stream is disabled (ie. after transfer complete event). [..] The following function can be used to write the Stream data counter value: (+) void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); -@- It is advised to use this function rather than DMA_Init() in situations where only the Data buffer needs to be reloaded. -@- If the Source and Destination Data Sizes are different, then the value written in data counter, expressing the number of transfers, is relative to the number of transfers from the Peripheral point of view. ie. If Memory data size is Word, Peripheral data size is Half-Words, then the value to be configured in the data counter is the number of Half-Words to be transferred from/to the peripheral. [..] The DMA data counter can be read to indicate the number of remaining transfers for the relative DMA Stream. This counter is decremented at the end of each data transfer and when the transfer is complete: (+) If Normal mode is selected: the counter is set to 0. (+) If Circular mode is selected: the counter is reloaded with the initial value (configured before enabling the DMA Stream) [..] The following function can be used to read the Stream data counter value: (+) uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); @endverbatim * @{ */ /** * @brief Writes the number of data units to be transferred on the DMAy Streamx. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param Counter: Number of data units to be transferred (from 0 to 65535) * Number of data items depends only on the Peripheral data format. * * @note If Peripheral data format is Bytes: number of data units is equal * to total number of bytes to be transferred. * * @note If Peripheral data format is Half-Word: number of data units is * equal to total number of bytes to be transferred / 2. * * @note If Peripheral data format is Word: number of data units is equal * to total number of bytes to be transferred / 4. * * @note In Memory-to-Memory transfer mode, the memory buffer pointed by * DMAy_SxPAR register is considered as Peripheral. * * @retval The number of remaining data units in the current DMAy Streamx transfer. */ void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); /* Write the number of data units to be transferred */ DMAy_Streamx->NDTR = (uint16_t)Counter; } /** * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @retval The number of remaining data units in the current DMAy Streamx transfer. */ uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); /* Return the number of remaining data units for DMAy Streamx */ return ((uint16_t)(DMAy_Streamx->NDTR)); } /** * @} */ /** @defgroup DMA_Group3 Double Buffer mode functions * @brief Double Buffer mode functions * @verbatim =============================================================================== ##### Double Buffer mode functions ##### =============================================================================== [..] This subsection provides function allowing to configure and control the double buffer mode parameters. [..] The Double Buffer mode can be used only when Circular mode is enabled. The Double Buffer mode cannot be used when transferring data from Memory to Memory. [..] The Double Buffer mode allows to set two different Memory addresses from/to which the DMA controller will access alternatively (after completing transfer to/from target memory 0, it will start transfer to/from target memory 1). This allows to reduce software overhead for double buffering and reduce the CPU access time. [..] Two functions must be called before calling the DMA_Init() function: (+) void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory); (+) void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); [..] DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address and the first Memory target from/to which the transfer will start after enabling the DMA Stream. Then DMA_DoubleBufferModeCmd() must be called to enable the Double Buffer mode (or disable it when it should not be used). [..] Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is stopped) to modify on of the target Memories addresses or to check wich Memory target is currently used: (+) void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget); (+) uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); [..] DMA_MemoryTargetConfig() can be called to modify the base address of one of the two target Memories. The Memory of which the base address will be modified must not be currently be used by the DMA Stream (ie. if the DMA Stream is currently transferring from Memory 1 then you can only modify base address of target Memory 0 and vice versa). To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which returns the index of the Memory target currently in use by the DMA Stream. @endverbatim * @{ */ /** * @brief Configures, when the DMAy Streamx is disabled, the double buffer mode * and the current memory target. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param Memory1BaseAddr: the base address of the second buffer (Memory 1) * @param DMA_CurrentMemory: specifies which memory will be first buffer for * the transactions when the Stream will be enabled. * This parameter can be one of the following values: * @arg DMA_Memory_0: Memory 0 is the current buffer. * @arg DMA_Memory_1: Memory 1 is the current buffer. * * @note Memory0BaseAddr is set by the DMA structure configuration in DMA_Init(). * * @retval None */ void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory)); if (DMA_CurrentMemory != DMA_Memory_0) { /* Set Memory 1 as current memory address */ DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT); } else { /* Set Memory 0 as current memory address */ DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT); } /* Write to DMAy Streamx M1AR */ DMAy_Streamx->M1AR = Memory1BaseAddr; } /** * @brief Enables or disables the double buffer mode for the selected DMA stream. * @note This function can be called only when the DMA Stream is disabled. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param NewState: new state of the DMAy Streamx double buffer mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Configure the Double Buffer mode */ if (NewState != DISABLE) { /* Enable the Double buffer mode */ DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM; } else { /* Disable the Double buffer mode */ DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM; } } /** * @brief Configures the Memory address for the next buffer transfer in double * buffer mode (for dynamic use). This function can be called when the * DMA Stream is enabled and when the transfer is ongoing. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param MemoryBaseAddr: The base address of the target memory buffer * @param DMA_MemoryTarget: Next memory target to be used. * This parameter can be one of the following values: * @arg DMA_Memory_0: To use the memory address 0 * @arg DMA_Memory_1: To use the memory address 1 * * @note It is not allowed to modify the Base Address of a target Memory when * this target is involved in the current transfer. ie. If the DMA Stream * is currently transferring to/from Memory 1, then it not possible to * modify Base address of Memory 1, but it is possible to modify Base * address of Memory 0. * To know which Memory is currently used, you can use the function * DMA_GetCurrentMemoryTarget(). * * @retval None */ void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget)); /* Check the Memory target to be configured */ if (DMA_MemoryTarget != DMA_Memory_0) { /* Write to DMAy Streamx M1AR */ DMAy_Streamx->M1AR = MemoryBaseAddr; } else { /* Write to DMAy Streamx M0AR */ DMAy_Streamx->M0AR = MemoryBaseAddr; } } /** * @brief Returns the current memory target used by double buffer transfer. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @retval The memory target number: 0 for Memory0 or 1 for Memory1. */ uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx) { uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); /* Get the current memory target */ if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0) { /* Current memory buffer used is Memory 1 */ tmp = 1; } else { /* Current memory buffer used is Memory 0 */ tmp = 0; } return tmp; } /** * @} */ /** @defgroup DMA_Group4 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== [..] This subsection provides functions allowing to (+) Check the DMA enable status (+) Check the FIFO status (+) Configure the DMA Interrupts sources and check or clear the flags or pending bits status. [..] (#) DMA Enable status: After configuring the DMA Stream (DMA_Init() function) and enabling the stream, it is recommended to check (or wait until) the DMA Stream is effectively enabled. A Stream may remain disabled if a configuration parameter is wrong. After disabling a DMA Stream, it is also recommended to check (or wait until) the DMA Stream is effectively disabled. If a Stream is disabled while a data transfer is ongoing, the current data will be transferred and the Stream will be effectively disabled only after this data transfer completion. To monitor this state it is possible to use the following function: (++) FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); (#) FIFO Status: It is possible to monitor the FIFO status when a transfer is ongoing using the following function: (++) uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); (#) DMA Interrupts and Flags: The user should identify which mode will be used in his application to manage the DMA controller events: Polling mode or Interrupt mode. *** Polling Mode *** ==================== [..] Each DMA stream can be managed through 4 event Flags: (x : DMA Stream number ) (#) DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred. (#) DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred. (#) DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred. (#) DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred. (#) DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred . [..] In this Mode it is advised to use the following functions: (+) FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); (+) void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); *** Interrupt Mode *** ====================== [..] Each DMA Stream can be managed through 4 Interrupts: *** Interrupt Source *** ======================== [..] (#) DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event. (#) DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event. (#) DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event. (#) DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event. (#) DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event. [..] In this Mode it is advised to use the following functions: (+) void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); (+) ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); (+) void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); @endverbatim * @{ */ /** * @brief Returns the status of EN bit for the specified DMAy Streamx. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * * @note After configuring the DMA Stream (DMA_Init() function) and enabling * the stream, it is recommended to check (or wait until) the DMA Stream * is effectively enabled. A Stream may remain disabled if a configuration * parameter is wrong. * After disabling a DMA Stream, it is also recommended to check (or wait * until) the DMA Stream is effectively disabled. If a Stream is disabled * while a data transfer is ongoing, the current data will be transferred * and the Stream will be effectively disabled only after the transfer * of this single data is finished. * * @retval Current state of the DMAy Streamx (ENABLE or DISABLE). */ FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx) { FunctionalState state = DISABLE; /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0) { /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */ state = ENABLE; } else { /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and all transfers are complete) */ state = DISABLE; } return state; } /** * @brief Returns the current DMAy Streamx FIFO filled level. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @retval The FIFO filling state. * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full * and not empty. * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. * - DMA_FIFOStatus_Empty: when FIFO is empty * - DMA_FIFOStatus_Full: when FIFO is full */ uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); /* Get the FIFO level bits */ tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS)); return tmpreg; } /** * @brief Checks whether the specified DMAy Streamx flag is set or not. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param DMA_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag * @arg DMA_FLAG_TEIFx: Streamx transfer error flag * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag * Where x can be 0 to 7 to select the DMA Stream. * @retval The new state of DMA_FLAG (SET or RESET). */ FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) { FlagStatus bitstatus = RESET; DMA_TypeDef* DMAy; uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); /* Determine the DMA to which belongs the stream */ if (DMAy_Streamx < DMA2_Stream0) { /* DMAy_Streamx belongs to DMA1 */ DMAy = DMA1; } else { /* DMAy_Streamx belongs to DMA2 */ DMAy = DMA2; } /* Check if the flag is in HISR or LISR */ if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) { /* Get DMAy HISR register value */ tmpreg = DMAy->HISR; } else { /* Get DMAy LISR register value */ tmpreg = DMAy->LISR; } /* Mask the reserved bits */ tmpreg &= (uint32_t)RESERVED_MASK; /* Check the status of the specified DMA flag */ if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) { /* DMA_FLAG is set */ bitstatus = SET; } else { /* DMA_FLAG is reset */ bitstatus = RESET; } /* Return the DMA_FLAG status */ return bitstatus; } /** * @brief Clears the DMAy Streamx's pending flags. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param DMA_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag * @arg DMA_FLAG_TEIFx: Streamx transfer error flag * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag * Where x can be 0 to 7 to select the DMA Stream. * @retval None */ void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) { DMA_TypeDef* DMAy; /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); /* Determine the DMA to which belongs the stream */ if (DMAy_Streamx < DMA2_Stream0) { /* DMAy_Streamx belongs to DMA1 */ DMAy = DMA1; } else { /* DMAy_Streamx belongs to DMA2 */ DMAy = DMA2; } /* Check if LIFCR or HIFCR register is targeted */ if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) { /* Set DMAy HIFCR register clear flag bits */ DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); } else { /* Set DMAy LIFCR register clear flag bits */ DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); } } /** * @brief Enables or disables the specified DMAy Streamx interrupts. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA_IT_TC: Transfer complete interrupt mask * @arg DMA_IT_HT: Half transfer complete interrupt mask * @arg DMA_IT_TE: Transfer error interrupt mask * @arg DMA_IT_FE: FIFO error interrupt mask * @param NewState: new state of the specified DMA interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_CONFIG_IT(DMA_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Check if the DMA_IT parameter contains a FIFO interrupt */ if ((DMA_IT & DMA_IT_FE) != 0) { if (NewState != DISABLE) { /* Enable the selected DMA FIFO interrupts */ DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE; } else { /* Disable the selected DMA FIFO interrupts */ DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE; } } /* Check if the DMA_IT parameter contains a Transfer interrupt */ if (DMA_IT != DMA_IT_FE) { if (NewState != DISABLE) { /* Enable the selected DMA transfer interrupts */ DMAy_Streamx->CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); } else { /* Disable the selected DMA transfer interrupts */ DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); } } } /** * @brief Checks whether the specified DMAy Streamx interrupt has occurred or not. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param DMA_IT: specifies the DMA interrupt source to check. * This parameter can be one of the following values: * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt * @arg DMA_IT_TEIFx: Streamx transfer error interrupt * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt * Where x can be 0 to 7 to select the DMA Stream. * @retval The new state of DMA_IT (SET or RESET). */ ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) { ITStatus bitstatus = RESET; DMA_TypeDef* DMAy; uint32_t tmpreg = 0, enablestatus = 0; /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_GET_IT(DMA_IT)); /* Determine the DMA to which belongs the stream */ if (DMAy_Streamx < DMA2_Stream0) { /* DMAy_Streamx belongs to DMA1 */ DMAy = DMA1; } else { /* DMAy_Streamx belongs to DMA2 */ DMAy = DMA2; } /* Check if the interrupt enable bit is in the CR or FCR register */ if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET) { /* Get the interrupt enable position mask in CR register */ tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK); /* Check the enable bit in CR register */ enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg); } else { /* Check the enable bit in FCR register */ enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE); } /* Check if the interrupt pending flag is in LISR or HISR */ if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) { /* Get DMAy HISR register value */ tmpreg = DMAy->HISR ; } else { /* Get DMAy LISR register value */ tmpreg = DMAy->LISR ; } /* mask all reserved bits */ tmpreg &= (uint32_t)RESERVED_MASK; /* Check the status of the specified DMA interrupt */ if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) { /* DMA_IT is set */ bitstatus = SET; } else { /* DMA_IT is reset */ bitstatus = RESET; } /* Return the DMA_IT status */ return bitstatus; } /** * @brief Clears the DMAy Streamx's interrupt pending bits. * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 * to 7 to select the DMA Stream. * @param DMA_IT: specifies the DMA interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt * @arg DMA_IT_TEIFx: Streamx transfer error interrupt * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt * Where x can be 0 to 7 to select the DMA Stream. * @retval None */ void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) { DMA_TypeDef* DMAy; /* Check the parameters */ assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); assert_param(IS_DMA_CLEAR_IT(DMA_IT)); /* Determine the DMA to which belongs the stream */ if (DMAy_Streamx < DMA2_Stream0) { /* DMAy_Streamx belongs to DMA1 */ DMAy = DMA1; } else { /* DMAy_Streamx belongs to DMA2 */ DMAy = DMA2; } /* Check if LIFCR or HIFCR register is targeted */ if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) { /* Set DMAy HIFCR register clear interrupt bits */ DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); } else { /* Set DMAy LIFCR register clear interrupt bits */ DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); } } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c ================================================ /** ****************************************************************************** * @file stm32f4xx_dma2d.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the DMA2D controller (DMA2D) peripheral: * + Initialization and configuration * + Interrupts and flags management * @verbatim =============================================================================== ##### How to use this driver ##### =============================================================================== [..] (#) Enable DMA2D clock using RCC_APB2PeriphResetCmd(RCC_APB2Periph_DMA2D, ENABLE) function. (#) Configures DMA2D (++) transfer mode (++) pixel format, line_number, pixel_per_line (++) output memory address (++) alpha value (++) output offset (++) Default color (RGB) (#) Configures Foreground or/and background (++) memory address (++) alpha value (++) offset and default color (#) Call the DMA2D_Start() to enable the DMA2D controller. @endverbatim ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * *

© COPYRIGHT 2013 STMicroelectronics

****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_dma2d.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup DMA2D * @brief DMA2D driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ #define CR_MASK ((uint32_t)0xFFFCE0FC) /* DMA2D CR Mask */ #define PFCCR_MASK ((uint32_t)0x00FC00C0) /* DMA2D FGPFCCR Mask */ #define DEAD_MASK ((uint32_t)0xFFFF00FE) /* DMA2D DEAD Mask */ /** @defgroup DMA2D_Private_Functions * @{ */ /** @defgroup DMA2D_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the DMA2D (+) Start/Abort/Suspend Transfer (+) Initialize, configure and set Foreground and background (+) configure and enable DeadTime (+) configure lineWatermark @endverbatim * @{ */ /** * @brief Deinitializes the DMA2D peripheral registers to their default reset * values. * @param None * @retval None */ void DMA2D_DeInit(void) { /* Enable DMA2D reset state */ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2D, ENABLE); /* Release DMA2D from reset state */ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2D, DISABLE); } /** * @brief Initializes the DMA2D peripheral according to the specified parameters * in the DMA2D_InitStruct. * @note This function can be used only when the DMA2D is disabled. * @param DMA2D_InitStruct: pointer to a DMA2D_InitTypeDef structure that contains * the configuration information for the specified DMA2D peripheral. * @retval None */ void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct) { uint32_t outgreen = 0; uint32_t outred = 0; uint32_t outalpha = 0; uint32_t pixline = 0; /* Check the parameters */ assert_param(IS_DMA2D_MODE(DMA2D_InitStruct->DMA2D_Mode)); assert_param(IS_DMA2D_CMODE(DMA2D_InitStruct->DMA2D_CMode)); assert_param(IS_DMA2D_OGREEN(DMA2D_InitStruct->DMA2D_OutputGreen)); assert_param(IS_DMA2D_ORED(DMA2D_InitStruct->DMA2D_OutputRed)); assert_param(IS_DMA2D_OBLUE(DMA2D_InitStruct->DMA2D_OutputBlue)); assert_param(IS_DMA2D_OALPHA(DMA2D_InitStruct->DMA2D_OutputAlpha)); assert_param(IS_DMA2D_OUTPUT_OFFSET(DMA2D_InitStruct->DMA2D_OutputOffset)); assert_param(IS_DMA2D_LINE(DMA2D_InitStruct->DMA2D_NumberOfLine)); assert_param(IS_DMA2D_PIXEL(DMA2D_InitStruct->DMA2D_PixelPerLine)); /* Configures the DMA2D operation mode */ DMA2D->CR &= (uint32_t)CR_MASK; DMA2D->CR |= (DMA2D_InitStruct->DMA2D_Mode); /* Configures the color mode of the output image */ DMA2D->OPFCCR &= ~(uint32_t)DMA2D_OPFCCR_CM; DMA2D->OPFCCR |= (DMA2D_InitStruct->DMA2D_CMode); /* Configures the output color */ if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_ARGB8888) { outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 8; outred = DMA2D_InitStruct->DMA2D_OutputRed << 16; outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 24; } else if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_RGB888) { outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 8; outred = DMA2D_InitStruct->DMA2D_OutputRed << 16; outalpha = (uint32_t)0x00000000; } else if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_RGB565) { outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 5; outred = DMA2D_InitStruct->DMA2D_OutputRed << 11; outalpha = (uint32_t)0x00000000; } else if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_ARGB1555) { outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 5; outred = DMA2D_InitStruct->DMA2D_OutputRed << 10; outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 15; } else /* DMA2D_CMode = DMA2D_ARGB4444 */ { outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 4; outred = DMA2D_InitStruct->DMA2D_OutputRed << 8; outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 12; } DMA2D->OCOLR |= ((outgreen) | (outred) | (DMA2D_InitStruct->DMA2D_OutputBlue) | (outalpha)); /* Configures the output memory address */ DMA2D->OMAR = (DMA2D_InitStruct->DMA2D_OutputMemoryAdd); /* Configure the line Offset */ DMA2D->OOR &= ~(uint32_t)DMA2D_OOR_LO; DMA2D->OOR |= (DMA2D_InitStruct->DMA2D_OutputOffset); /* Configure the number of line and pixel per line */ pixline = DMA2D_InitStruct->DMA2D_PixelPerLine << 16; DMA2D->NLR &= ~(DMA2D_NLR_NL | DMA2D_NLR_PL); DMA2D->NLR |= ((DMA2D_InitStruct->DMA2D_NumberOfLine) | (pixline)); /** * @brief Fills each DMA2D_InitStruct member with its default value. * @param DMA2D_InitStruct: pointer to a DMA2D_InitTypeDef structure which will * be initialized. * @retval None */ } void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct) { /* Initialize the transfer mode member */ DMA2D_InitStruct->DMA2D_Mode = DMA2D_M2M; /* Initialize the output color mode members */ DMA2D_InitStruct->DMA2D_CMode = DMA2D_ARGB8888; /* Initialize the alpha and RGB values */ DMA2D_InitStruct->DMA2D_OutputGreen = 0x00; DMA2D_InitStruct->DMA2D_OutputBlue = 0x00; DMA2D_InitStruct->DMA2D_OutputRed = 0x00; DMA2D_InitStruct->DMA2D_OutputAlpha = 0x00; /* Initialize the output memory address */ DMA2D_InitStruct->DMA2D_OutputMemoryAdd = 0x00; /* Initialize the output offset */ DMA2D_InitStruct->DMA2D_OutputOffset = 0x00; /* Initialize the number of line and the number of pixel per line */ DMA2D_InitStruct->DMA2D_NumberOfLine = 0x00; DMA2D_InitStruct->DMA2D_PixelPerLine = 0x00; } /** * @brief Start the DMA2D transfer. * @param * @retval None */ void DMA2D_StartTransfer(void) { /* Start DMA2D transfer by setting START bit */ DMA2D->CR |= (uint32_t)DMA2D_CR_START; } /** * @brief Aboart the DMA2D transfer. * @param * @retval None */ void DMA2D_AbortTransfer(void) { /* Start DMA2D transfer by setting START bit */ DMA2D->CR |= (uint32_t)DMA2D_CR_ABORT; } /** * @brief Stop or continue the DMA2D transfer. * @param NewState: new state of the DMA2D peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DMA2D_Suspend(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Suspend DMA2D transfer by setting STOP bit */ DMA2D->CR |= (uint32_t)DMA2D_CR_SUSP; } else { /* Continue DMA2D transfer by clearing STOP bit */ DMA2D->CR &= ~(uint32_t)DMA2D_CR_SUSP; } } /** * @brief Configures the Foreground according to the specified parameters * in the DMA2D_FGStruct. * @note This function can be used only when the transfer is disabled. * @param DMA2D_FGStruct: pointer to a DMA2D_FGTypeDef structure that contains * the configuration information for the specified Background. * @retval None */ void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct) { uint32_t fg_clutcolormode = 0; uint32_t fg_clutsize = 0; uint32_t fg_alpha_mode = 0; uint32_t fg_alphavalue = 0; uint32_t fg_colorgreen = 0; uint32_t fg_colorred = 0; assert_param(IS_DMA2D_FGO(DMA2D_FG_InitStruct->DMA2D_FGO)); assert_param(IS_DMA2D_FGCM(DMA2D_FG_InitStruct->DMA2D_FGCM)); assert_param(IS_DMA2D_FG_CLUT_CM(DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM)); assert_param(IS_DMA2D_FG_CLUT_SIZE(DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE)); assert_param(IS_DMA2D_FG_ALPHA_MODE(DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE)); assert_param(IS_DMA2D_FG_ALPHA_VALUE(DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE)); assert_param(IS_DMA2D_FGC_BLUE(DMA2D_FG_InitStruct->DMA2D_FGC_BLUE)); assert_param(IS_DMA2D_FGC_GREEN(DMA2D_FG_InitStruct->DMA2D_FGC_GREEN)); assert_param(IS_DMA2D_FGC_RED(DMA2D_FG_InitStruct->DMA2D_FGC_RED)); /* Configures the FG memory address */ DMA2D->FGMAR = (DMA2D_FG_InitStruct->DMA2D_FGMA); /* Configures the FG offset */ DMA2D->FGOR &= ~(uint32_t)DMA2D_FGOR_LO; DMA2D->FGOR |= (DMA2D_FG_InitStruct->DMA2D_FGO); /* Configures foreground Pixel Format Convertor */ DMA2D->FGPFCCR &= (uint32_t)PFCCR_MASK; fg_clutcolormode = DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM << 4; fg_clutsize = DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE << 8; fg_alpha_mode = DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE << 16; fg_alphavalue = DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE << 24; DMA2D->FGPFCCR |= (DMA2D_FG_InitStruct->DMA2D_FGCM | fg_clutcolormode | fg_clutsize | \ fg_alpha_mode | fg_alphavalue); /* Configures foreground color */ DMA2D->FGCOLR &= ~(DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_RED); fg_colorgreen = DMA2D_FG_InitStruct->DMA2D_FGC_GREEN << 8; fg_colorred = DMA2D_FG_InitStruct->DMA2D_FGC_RED << 16; DMA2D->FGCOLR |= (DMA2D_FG_InitStruct->DMA2D_FGC_BLUE | fg_colorgreen | fg_colorred); /* Configures foreground CLUT memory address */ DMA2D->FGCMAR = DMA2D_FG_InitStruct->DMA2D_FGCMAR; } /** * @brief Fills each DMA2D_FGStruct member with its default value. * @param DMA2D_FGStruct: pointer to a DMA2D_FGTypeDef structure which will * be initialized. * @retval None */ void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct) { /*!< Initialize the DMA2D foreground memory address */ DMA2D_FG_InitStruct->DMA2D_FGMA = 0x00; /*!< Initialize the DMA2D foreground offset */ DMA2D_FG_InitStruct->DMA2D_FGO = 0x00; /*!< Initialize the DMA2D foreground color mode */ DMA2D_FG_InitStruct->DMA2D_FGCM = CM_ARGB8888; /*!< Initialize the DMA2D foreground CLUT color mode */ DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM = CLUT_CM_ARGB8888; /*!< Initialize the DMA2D foreground CLUT size */ DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE = 0x00; /*!< Initialize the DMA2D foreground alpha mode */ DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE; /*!< Initialize the DMA2D foreground alpha value */ DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE = 0x00; /*!< Initialize the DMA2D foreground blue value */ DMA2D_FG_InitStruct->DMA2D_FGC_BLUE = 0x00; /*!< Initialize the DMA2D foreground green value */ DMA2D_FG_InitStruct->DMA2D_FGC_GREEN = 0x00; /*!< Initialize the DMA2D foreground red value */ DMA2D_FG_InitStruct->DMA2D_FGC_RED = 0x00; /*!< Initialize the DMA2D foreground CLUT memory address */ DMA2D_FG_InitStruct->DMA2D_FGCMAR = 0x00; } /** * @brief Configures the Background according to the specified parameters * in the DMA2D_BGStruct. * @note This function can be used only when the transfer is disabled. * @param DMA2D_BGStruct: pointer to a DMA2D_BGTypeDef structure that contains * the configuration information for the specified Background. * @retval None */ void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct) { uint32_t bg_clutcolormode = 0; uint32_t bg_clutsize = 0; uint32_t bg_alpha_mode = 0; uint32_t bg_alphavalue = 0; uint32_t bg_colorgreen = 0; uint32_t bg_colorred = 0; assert_param(IS_DMA2D_BGO(DMA2D_BG_InitStruct->DMA2D_BGO)); assert_param(IS_DMA2D_BGCM(DMA2D_BG_InitStruct->DMA2D_BGCM)); assert_param(IS_DMA2D_BG_CLUT_CM(DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM)); assert_param(IS_DMA2D_BG_CLUT_SIZE(DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE)); assert_param(IS_DMA2D_BG_ALPHA_MODE(DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE)); assert_param(IS_DMA2D_BG_ALPHA_VALUE(DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE)); assert_param(IS_DMA2D_BGC_BLUE(DMA2D_BG_InitStruct->DMA2D_BGC_BLUE)); assert_param(IS_DMA2D_BGC_GREEN(DMA2D_BG_InitStruct->DMA2D_BGC_GREEN)); assert_param(IS_DMA2D_BGC_RED(DMA2D_BG_InitStruct->DMA2D_BGC_RED)); /* Configures the BG memory address */ DMA2D->BGMAR = (DMA2D_BG_InitStruct->DMA2D_BGMA); /* Configures the BG offset */ DMA2D->BGOR &= ~(uint32_t)DMA2D_BGOR_LO; DMA2D->BGOR |= (DMA2D_BG_InitStruct->DMA2D_BGO); /* Configures background Pixel Format Convertor */ DMA2D->BGPFCCR &= (uint32_t)PFCCR_MASK; bg_clutcolormode = DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM << 4; bg_clutsize = DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE << 8; bg_alpha_mode = DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE << 16; bg_alphavalue = DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE << 24; DMA2D->BGPFCCR |= (DMA2D_BG_InitStruct->DMA2D_BGCM | bg_clutcolormode | bg_clutsize | \ bg_alpha_mode | bg_alphavalue); /* Configures background color */ DMA2D->BGCOLR &= ~(DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_RED); bg_colorgreen = DMA2D_BG_InitStruct->DMA2D_BGC_GREEN << 8; bg_colorred = DMA2D_BG_InitStruct->DMA2D_BGC_RED << 16; DMA2D->BGCOLR |= (DMA2D_BG_InitStruct->DMA2D_BGC_BLUE | bg_colorgreen | bg_colorred); /* Configures background CLUT memory address */ DMA2D->BGCMAR = DMA2D_BG_InitStruct->DMA2D_BGCMAR; } /** * @brief Fills each DMA2D_BGStruct member with its default value. * @param DMA2D_BGStruct: pointer to a DMA2D_BGTypeDef structure which will * be initialized. * @retval None */ void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct) { /*!< Initialize the DMA2D background memory address */ DMA2D_BG_InitStruct->DMA2D_BGMA = 0x00; /*!< Initialize the DMA2D background offset */ DMA2D_BG_InitStruct->DMA2D_BGO = 0x00; /*!< Initialize the DMA2D background color mode */ DMA2D_BG_InitStruct->DMA2D_BGCM = CM_ARGB8888; /*!< Initialize the DMA2D background CLUT color mode */ DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM = CLUT_CM_ARGB8888; /*!< Initialize the DMA2D background CLUT size */ DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE = 0x00; /*!< Initialize the DMA2D background alpha mode */ DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE; /*!< Initialize the DMA2D background alpha value */ DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE = 0x00; /*!< Initialize the DMA2D background blue value */ DMA2D_BG_InitStruct->DMA2D_BGC_BLUE = 0x00; /*!< Initialize the DMA2D background green value */ DMA2D_BG_InitStruct->DMA2D_BGC_GREEN = 0x00; /*!< Initialize the DMA2D background red value */ DMA2D_BG_InitStruct->DMA2D_BGC_RED = 0x00; /*!< Initialize the DMA2D background CLUT memory address */ DMA2D_BG_InitStruct->DMA2D_BGCMAR = 0x00; } /** * @brief Start the automatic loading of the CLUT or abort the transfer. * @param NewState: new state of the DMA2D peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DMA2D_FGStart(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Start the automatic loading of the CLUT */ DMA2D->FGPFCCR |= DMA2D_FGPFCCR_START; } else { /* abort the transfer */ DMA2D->FGPFCCR &= (uint32_t)~DMA2D_FGPFCCR_START; } } /** * @brief Start the automatic loading of the CLUT or abort the transfer. * @param NewState: new state of the DMA2D peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DMA2D_BGStart(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Start the automatic loading of the CLUT */ DMA2D->BGPFCCR |= DMA2D_BGPFCCR_START; } else { /* abort the transfer */ DMA2D->BGPFCCR &= (uint32_t)~DMA2D_BGPFCCR_START; } } /** * @brief Configures the DMA2D dead time. * @param DMA2D_DeadTime: specifies the DMA2D dead time. * This parameter can be one of the following values: * @retval None */ void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState) { uint32_t DeadTime; /* Check the parameters */ assert_param(IS_DMA2D_DEAD_TIME(DMA2D_DeadTime)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable and Configures the dead time */ DMA2D->AMTCR &= (uint32_t)DEAD_MASK; DeadTime = DMA2D_DeadTime << 8; DMA2D->AMTCR |= (DeadTime | DMA2D_AMTCR_EN); } else { DMA2D->AMTCR &= ~(uint32_t)DMA2D_AMTCR_EN; } } /** * @brief Define the configuration of the line watermark . * @param DMA2D_LWatermarkConfig: Line Watermark configuration. * @retval None */ void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig) { /* Check the parameters */ assert_param(IS_DMA2D_LineWatermark(DMA2D_LWatermarkConfig)); /* Sets the Line watermark configuration */ DMA2D->LWR = (uint32_t)DMA2D_LWatermarkConfig; } /** * @} */ /** @defgroup DMA2D_Group2 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== [..] This section provides functions allowing to configure the DMA2D Interrupts and to get the status and clear flags and Interrupts pending bits. [..] The DMA2D provides 6 Interrupts sources and 6 Flags *** Flags *** ============= [..] (+) DMA2D_FLAG_CE : Configuration Error Interrupt flag (+) DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag (+) DMA2D_FLAG_TW: Transfer Watermark Interrupt flag (+) DMA2D_FLAG_TC: Transfer Complete interrupt flag (+) DMA2D_FLAG_TE: Transfer Error interrupt flag (+) DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag *** Interrupts *** ================== [..] (+) DMA2D_IT_CE: Configuration Error Interrupt is generated when a wrong configuration is detected (+) DMA2D_IT_CAE: CLUT Access Error Interrupt (+) DMA2D_IT_TW: Transfer Watermark Interrupt is generated when the programmed watermark is reached (+) DMA2D_IT_TE: Transfer Error interrupt is generated when the CPU trying to access the CLUT while a CLUT loading or a DMA2D1 transfer is on going (+) DMA2D_IT_CTC: CLUT Transfer Complete Interrupt (+) DMA2D_IT_TC: Transfer Complete interrupt @endverbatim * @{ */ /** * @brief Enables or disables the specified DMA2D's interrupts. * @param DMA2D_IT: specifies the DMA2D interrupts sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg DMA2D_IT_CE: Configuration Error Interrupt Enable. * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable. * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt Enable. * @arg DMA2D_IT_TW: Transfer Watermark Interrupt Enable. * @arg DMA2D_IT_TC: Transfer Complete interrupt enable. * @arg DMA2D_IT_TE: Transfer Error interrupt enable. * @param NewState: new state of the specified DMA2D interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_DMA2D_IT(DMA2D_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected DMA2D interrupts */ DMA2D->CR |= DMA2D_IT; } else { /* Disable the selected DMA2D interrupts */ DMA2D->CR &= (uint32_t)~DMA2D_IT; } } /** * @brief Checks whether the specified DMA2D's flag is set or not. * @param DMA2D_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg DMA2D_FLAG_CE: Configuration Error Interrupt flag. * @arg DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag. * @arg DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag. * @arg DMA2D_FLAG_TW: Transfer Watermark Interrupt flag. * @arg DMA2D_FLAG_TC: Transfer Complete interrupt flag. * @arg DMA2D_FLAG_TE: Transfer Error interrupt flag. * @retval The new state of DMA2D_FLAG (SET or RESET). */ FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_DMA2D_GET_FLAG(DMA2D_FLAG)); /* Check the status of the specified DMA2D flag */ if (((DMA2D->ISR) & DMA2D_FLAG) != (uint32_t)RESET) { /* DMA2D_FLAG is set */ bitstatus = SET; } else { /* DMA2D_FLAG is reset */ bitstatus = RESET; } /* Return the DMA2D_FLAG status */ return bitstatus; } /** * @brief Clears the DMA2D's pending flags. * @param DMA2D_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA2D_FLAG_CE: Configuration Error Interrupt flag. * @arg DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag. * @arg DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag. * @arg DMA2D_FLAG_TW: Transfer Watermark Interrupt flag. * @arg DMA2D_FLAG_TC: Transfer Complete interrupt flag. * @arg DMA2D_FLAG_TE: Transfer Error interrupt flag. * @retval None */ void DMA2D_ClearFlag(uint32_t DMA2D_FLAG) { /* Check the parameters */ assert_param(IS_DMA2D_GET_FLAG(DMA2D_FLAG)); /* Clear the corresponding DMA2D flag */ DMA2D->IFCR = (uint32_t)DMA2D_FLAG; } /** * @brief Checks whether the specified DMA2D's interrupt has occurred or not. * @param DMA2D_IT: specifies the DMA2D interrupts sources to check. * This parameter can be one of the following values: * @arg DMA2D_IT_CE: Configuration Error Interrupt Enable. * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable. * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt Enable. * @arg DMA2D_IT_TW: Transfer Watermark Interrupt Enable. * @arg DMA2D_IT_TC: Transfer Complete interrupt enable. * @arg DMA2D_IT_TE: Transfer Error interrupt enable. * @retval The new state of the DMA2D_IT (SET or RESET). */ ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT) { ITStatus bitstatus = RESET; uint32_t DMA2D_IT_FLAG = DMA2D_IT >> 8; /* Check the parameters */ assert_param(IS_DMA2D_IT(DMA2D_IT)); if ((DMA2D->ISR & DMA2D_IT_FLAG) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } if (((DMA2D->CR & DMA2D_IT) != (uint32_t)RESET) && (bitstatus != (uint32_t)RESET)) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the DMA2D's interrupt pending bits. * @param DMA2D_IT: specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg DMA2D_IT_CE: Configuration Error Interrupt. * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt. * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt. * @arg DMA2D_IT_TW: Transfer Watermark Interrupt. * @arg DMA2D_IT_TC: Transfer Complete interrupt. * @arg DMA2D_IT_TE: Transfer Error interrupt. * @retval None */ void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT) { /* Check the parameters */ assert_param(IS_DMA2D_IT(DMA2D_IT)); DMA2D_IT = DMA2D_IT >> 8; /* Clear the corresponding DMA2D Interrupt */ DMA2D->IFCR = (uint32_t)DMA2D_IT; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c ================================================ /** ****************************************************************************** * @file stm32f4xx_exti.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the EXTI peripheral: * + Initialization and Configuration * + Interrupts and flags management * @verbatim =================================================================== ##### EXTI features ##### =================================================================== [..] External interrupt/event lines are mapped as following: (#) All available GPIO pins are connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. (#) EXTI line 16 is connected to the PVD Output (#) EXTI line 17 is connected to the RTC Alarm event (#) EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event (#) EXTI line 19 is connected to the Ethernet Wakeup event (#) EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event (#) EXTI line 21 is connected to the RTC Tamper and Time Stamp events (#) EXTI line 22 is connected to the RTC Wakeup event ##### How to use this driver ##### =================================================================== [..] In order to use an I/O pin as an external interrupt source, follow steps below: (#) Configure the I/O in input mode using GPIO_Init() (#) Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig() (#) Select the mode(interrupt, event) and configure the trigger selection (Rising, falling or both) using EXTI_Init() (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init() [..] (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_exti.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup EXTI * @brief EXTI driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup EXTI_Private_Functions * @{ */ /** @defgroup EXTI_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Deinitializes the EXTI peripheral registers to their default reset values. * @param None * @retval None */ void EXTI_DeInit(void) { EXTI->IMR = 0x00000000; EXTI->EMR = 0x00000000; EXTI->RTSR = 0x00000000; EXTI->FTSR = 0x00000000; EXTI->PR = 0x007FFFFF; } /** * @brief Initializes the EXTI peripheral according to the specified * parameters in the EXTI_InitStruct. * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure * that contains the configuration information for the EXTI peripheral. * @retval None */ void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) { uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); tmp = (uint32_t)EXTI_BASE; if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) { /* Clear EXTI line configuration */ EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; tmp += EXTI_InitStruct->EXTI_Mode; *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; /* Clear Rising Falling edge configuration */ EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; /* Select the trigger for the selected external interrupts */ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) { /* Rising Falling edge */ EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; } else { tmp = (uint32_t)EXTI_BASE; tmp += EXTI_InitStruct->EXTI_Trigger; *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; } } else { tmp += EXTI_InitStruct->EXTI_Mode; /* Disable the selected external lines */ *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; } } /** * @brief Fills each EXTI_InitStruct member with its reset value. * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will * be initialized. * @retval None */ void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) { EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; EXTI_InitStruct->EXTI_LineCmd = DISABLE; } /** * @brief Generates a Software interrupt on selected EXTI line. * @param EXTI_Line: specifies the EXTI line on which the software interrupt * will be generated. * This parameter can be any combination of EXTI_Linex where x can be (0..22) * @retval None */ void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) { /* Check the parameters */ assert_param(IS_EXTI_LINE(EXTI_Line)); EXTI->SWIER |= EXTI_Line; } /** * @} */ /** @defgroup EXTI_Group2 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Checks whether the specified EXTI line flag is set or not. * @param EXTI_Line: specifies the EXTI line flag to check. * This parameter can be EXTI_Linex where x can be(0..22) * @retval The new state of EXTI_Line (SET or RESET). */ FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_GET_EXTI_LINE(EXTI_Line)); if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the EXTI's line pending flags. * @param EXTI_Line: specifies the EXTI lines flags to clear. * This parameter can be any combination of EXTI_Linex where x can be (0..22) * @retval None */ void EXTI_ClearFlag(uint32_t EXTI_Line) { /* Check the parameters */ assert_param(IS_EXTI_LINE(EXTI_Line)); EXTI->PR = EXTI_Line; } /** * @brief Checks whether the specified EXTI line is asserted or not. * @param EXTI_Line: specifies the EXTI line to check. * This parameter can be EXTI_Linex where x can be(0..22) * @retval The new state of EXTI_Line (SET or RESET). */ ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_GET_EXTI_LINE(EXTI_Line)); if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the EXTI's line pending bits. * @param EXTI_Line: specifies the EXTI lines to clear. * This parameter can be any combination of EXTI_Linex where x can be (0..22) * @retval None */ void EXTI_ClearITPendingBit(uint32_t EXTI_Line) { /* Check the parameters */ assert_param(IS_EXTI_LINE(EXTI_Line)); EXTI->PR = EXTI_Line; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c ================================================ /** ****************************************************************************** * @file stm32f4xx_flash.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the FLASH peripheral: * + FLASH Interface configuration * + FLASH Memory Programming * + Option Bytes Programming * + Interrupts and flags management * @verbatim =============================================================================== ##### How to use this driver ##### =============================================================================== [..] This driver provides functions to configure and program the FLASH memory of all STM32F4xx devices. These functions are split in 4 groups: (#) FLASH Interface configuration functions: this group includes the management of the following features: (++) Set the latency (++) Enable/Disable the prefetch buffer (++) Enable/Disable the Instruction cache and the Data cache (++) Reset the Instruction cache and the Data cache (#) FLASH Memory Programming functions: this group includes all needed functions to erase and program the main memory: (++) Lock and Unlock the FLASH interface (++) Erase function: Erase sector, erase all sectors (++) Program functions: byte, half word, word and double word (#) Option Bytes Programming functions: this group includes all needed functions to manage the Option Bytes: (++) Set/Reset the write protection (++) Set the Read protection Level (++) Set the BOR level (++) Program the user Option Bytes (++) Launch the Option Bytes loader (#) Interrupts and flags management functions: this group includes all needed functions to: (++) Enable/Disable the FLASH interrupt sources (++) Get flags status (++) Clear flags (++) Get FLASH operation status (++) Wait for last FLASH operation @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_flash.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup FLASH * @brief FLASH driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define SECTOR_MASK ((uint32_t)0xFFFFFF07) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup FLASH_Private_Functions * @{ */ /** @defgroup FLASH_Group1 FLASH Interface configuration functions * @brief FLASH Interface configuration functions * @verbatim =============================================================================== ##### FLASH Interface configuration functions ##### =============================================================================== [..] This group includes the following functions: (+) void FLASH_SetLatency(uint32_t FLASH_Latency) To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. [..] For STM32F405xx/07xx and STM32F415xx/17xx devices +-------------------------------------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |---------------------------------------------------------------------| | | voltage range | voltage range | voltage range | voltage range | | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | |---------------|----------------|----------------|-----------------|-----------------| |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | |---------------|----------------|----------------|-----------------|-----------------| |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | |---------------|----------------|----------------|-----------------|-----------------| |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | |---------------|----------------|----------------|-----------------|-----------------| |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | |---------------|----------------|----------------|-----------------|-----------------| |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | |---------------|----------------|----------------|-----------------|-----------------| |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| |---------------|----------------|----------------|-----------------|-----------------| |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| |---------------|----------------|----------------|-----------------|-----------------| |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160| +---------------|----------------|----------------|-----------------|-----------------+ [..] For STM32F42xxx/43xxx devices +-------------------------------------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |---------------------------------------------------------------------| | | voltage range | voltage range | voltage range | voltage range | | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | |---------------|----------------|----------------|-----------------|-----------------| |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | |---------------|----------------|----------------|-----------------|-----------------| |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | |---------------|----------------|----------------|-----------------|-----------------| |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | |---------------|----------------|----------------|-----------------|-----------------| |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | |---------------|----------------|----------------|-----------------|-----------------| |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | |---------------|----------------|----------------|-----------------|-----------------| |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| |---------------|----------------|----------------|-----------------|-----------------| |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| |---------------|----------------|----------------|-----------------|-----------------| |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160| |---------------|----------------|----------------|-----------------|-----------------| |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168| +-------------------------------------------------------------------------------------+ [..] For STM32F401x devices +-------------------------------------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |---------------------------------------------------------------------| | | voltage range | voltage range | voltage range | voltage range | | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | |---------------|----------------|----------------|-----------------|-----------------| |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | |---------------|----------------|----------------|-----------------|-----------------| |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | |---------------|----------------|----------------|-----------------|-----------------| |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | |---------------|----------------|----------------|-----------------|-----------------| |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 | |---------------|----------------|----------------|-----------------|-----------------| |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 | +-------------------------------------------------------------------------------------+ [..] +-------------------------------------------------------------------------------------------------------------------+ | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V | | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V | |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| |Max Parallelism| x32 | x16 | x8 | x64 | |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| |PSIZE[1:0] | 10 | 01 | 00 | 11 | +-------------------------------------------------------------------------------------------------------------------+ -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: (++) when VOS = '0' Scale 2 mode, the maximum value of fHCLK = 144MHz. (++) when VOS = '1' Scale 1 mode, the maximum value of fHCLK = 168MHz. [..] On STM32F42xxx/43xxx devices: (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 120MHz. (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 144MHz if OverDrive OFF and 168MHz if OverDrive ON. (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 168MHz if OverDrive OFF and 180MHz if OverDrive ON. [..] On STM32F401x devices: (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz. (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz. For more details please refer product DataSheet You can use PWR_MainRegulatorModeConfig() function to control VOS bits. (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState) (+) void FLASH_InstructionCacheCmd(FunctionalState NewState) (+) void FLASH_DataCacheCmd(FunctionalState NewState) (+) void FLASH_InstructionCacheReset(void) (+) void FLASH_DataCacheReset(void) [..] The unlock sequence is not needed for these functions. @endverbatim * @{ */ /** * @brief Sets the code latency value. * @param FLASH_Latency: specifies the FLASH Latency value. * This parameter can be one of the following values: * @arg FLASH_Latency_0: FLASH Zero Latency cycle * @arg FLASH_Latency_1: FLASH One Latency cycle * @arg FLASH_Latency_2: FLASH Two Latency cycles * @arg FLASH_Latency_3: FLASH Three Latency cycles * @arg FLASH_Latency_4: FLASH Four Latency cycles * @arg FLASH_Latency_5: FLASH Five Latency cycles * @arg FLASH_Latency_6: FLASH Six Latency cycles * @arg FLASH_Latency_7: FLASH Seven Latency cycles * @arg FLASH_Latency_8: FLASH Eight Latency cycles * @arg FLASH_Latency_9: FLASH Nine Latency cycles * @arg FLASH_Latency_10: FLASH Teen Latency cycles * @arg FLASH_Latency_11: FLASH Eleven Latency cycles * @arg FLASH_Latency_12: FLASH Twelve Latency cycles * @arg FLASH_Latency_13: FLASH Thirteen Latency cycles * @arg FLASH_Latency_14: FLASH Fourteen Latency cycles * @arg FLASH_Latency_15: FLASH Fifteen Latency cycles * * @note For STM32F405xx/407xx, STM32F415xx/417xx and STM32F401xx devices this parameter * can be a value between FLASH_Latency_0 and FLASH_Latency_7. * * @note For STM32F42xxx/43xxx devices this parameter can be a value between * FLASH_Latency_0 and FLASH_Latency_15. * * @retval None */ void FLASH_SetLatency(uint32_t FLASH_Latency) { /* Check the parameters */ assert_param(IS_FLASH_LATENCY(FLASH_Latency)); /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */ *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency; } /** * @brief Enables or disables the Prefetch Buffer. * @param NewState: new state of the Prefetch Buffer. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FLASH_PrefetchBufferCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Enable or disable the Prefetch Buffer */ if(NewState != DISABLE) { FLASH->ACR |= FLASH_ACR_PRFTEN; } else { FLASH->ACR &= (~FLASH_ACR_PRFTEN); } } /** * @brief Enables or disables the Instruction Cache feature. * @param NewState: new state of the Instruction Cache. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FLASH_InstructionCacheCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if(NewState != DISABLE) { FLASH->ACR |= FLASH_ACR_ICEN; } else { FLASH->ACR &= (~FLASH_ACR_ICEN); } } /** * @brief Enables or disables the Data Cache feature. * @param NewState: new state of the Data Cache. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FLASH_DataCacheCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if(NewState != DISABLE) { FLASH->ACR |= FLASH_ACR_DCEN; } else { FLASH->ACR &= (~FLASH_ACR_DCEN); } } /** * @brief Resets the Instruction Cache. * @note This function must be used only when the Instruction Cache is disabled. * @param None * @retval None */ void FLASH_InstructionCacheReset(void) { FLASH->ACR |= FLASH_ACR_ICRST; } /** * @brief Resets the Data Cache. * @note This function must be used only when the Data Cache is disabled. * @param None * @retval None */ void FLASH_DataCacheReset(void) { FLASH->ACR |= FLASH_ACR_DCRST; } /** * @} */ /** @defgroup FLASH_Group2 FLASH Memory Programming functions * @brief FLASH Memory Programming functions * @verbatim =============================================================================== ##### FLASH Memory Programming functions ##### =============================================================================== [..] This group includes the following functions: (+) void FLASH_Unlock(void) (+) void FLASH_Lock(void) (+) FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) (+) FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) (+) FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) (+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) The following functions can be used only for STM32F42xxx/43xxx devices. (+) FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange) (+) FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange) [..] Any operation of erase or program should follow these steps: (#) Call the FLASH_Unlock() function to enable the FLASH control register access (#) Call the desired function to erase sector(s) or program data (#) Call the FLASH_Lock() function to disable the FLASH control register access (recommended to protect the FLASH memory against possible unwanted operation) @endverbatim * @{ */ /** * @brief Unlocks the FLASH control register access * @param None * @retval None */ void FLASH_Unlock(void) { if((FLASH->CR & FLASH_CR_LOCK) != RESET) { /* Authorize the FLASH Registers access */ FLASH->KEYR = FLASH_KEY1; FLASH->KEYR = FLASH_KEY2; } } /** * @brief Locks the FLASH control register access * @param None * @retval None */ void FLASH_Lock(void) { /* Set the LOCK Bit to lock the FLASH Registers access */ FLASH->CR |= FLASH_CR_LOCK; } /** * @brief Erases a specified FLASH Sector. * * @note If an erase and a program operations are requested simustaneously, * the erase operation is performed before the program one. * * @param FLASH_Sector: The Sector number to be erased. * * @note For STM32F405xx/407xx and STM32F415xx/417xx devices this parameter can * be a value between FLASH_Sector_0 and FLASH_Sector_11. * * For STM32F42xxx/43xxx devices this parameter can be a value between * FLASH_Sector_0 and FLASH_Sector_23. * * For STM32F401xx devices this parameter can be a value between * FLASH_Sector_0 and FLASH_Sector_5. * * @param VoltageRange: The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, * the operation will be done by half word (16-bit) * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, * the operation will be done by word (32-bit) * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, * the operation will be done by double word (64-bit) * * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) { uint32_t tmp_psize = 0x0; FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_FLASH_SECTOR(FLASH_Sector)); assert_param(IS_VOLTAGERANGE(VoltageRange)); if(VoltageRange == VoltageRange_1) { tmp_psize = FLASH_PSIZE_BYTE; } else if(VoltageRange == VoltageRange_2) { tmp_psize = FLASH_PSIZE_HALF_WORD; } else if(VoltageRange == VoltageRange_3) { tmp_psize = FLASH_PSIZE_WORD; } else { tmp_psize = FLASH_PSIZE_DOUBLE_WORD; } /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { /* if the previous operation is completed, proceed to erase the sector */ FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= tmp_psize; FLASH->CR &= SECTOR_MASK; FLASH->CR |= FLASH_CR_SER | FLASH_Sector; FLASH->CR |= FLASH_CR_STRT; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); /* if the erase operation is completed, disable the SER Bit */ FLASH->CR &= (~FLASH_CR_SER); FLASH->CR &= SECTOR_MASK; } /* Return the Erase Status */ return status; } /** * @brief Erases all FLASH Sectors. * * @note If an erase and a program operations are requested simustaneously, * the erase operation is performed before the program one. * * @param VoltageRange: The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, * the operation will be done by half word (16-bit) * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, * the operation will be done by word (32-bit) * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, * the operation will be done by double word (64-bit) * * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) { uint32_t tmp_psize = 0x0; FLASH_Status status = FLASH_COMPLETE; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); assert_param(IS_VOLTAGERANGE(VoltageRange)); if(VoltageRange == VoltageRange_1) { tmp_psize = FLASH_PSIZE_BYTE; } else if(VoltageRange == VoltageRange_2) { tmp_psize = FLASH_PSIZE_HALF_WORD; } else if(VoltageRange == VoltageRange_3) { tmp_psize = FLASH_PSIZE_WORD; } else { tmp_psize = FLASH_PSIZE_DOUBLE_WORD; } if(status == FLASH_COMPLETE) { /* if the previous operation is completed, proceed to erase all sectors */ #if defined (STM32F427_437xx) || defined (STM32F429_439xx) FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= tmp_psize; FLASH->CR |= (FLASH_CR_MER1 | FLASH_CR_MER2); FLASH->CR |= FLASH_CR_STRT; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); /* if the erase operation is completed, disable the MER Bit */ FLASH->CR &= ~(FLASH_CR_MER1 | FLASH_CR_MER2); #endif /* STM32F427_437xx || STM32F429_439xx */ #if defined (STM32F40_41xxx) || defined (STM32F401xx) FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= tmp_psize; FLASH->CR |= FLASH_CR_MER; FLASH->CR |= FLASH_CR_STRT; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); /* if the erase operation is completed, disable the MER Bit */ FLASH->CR &= (~FLASH_CR_MER); #endif /* STM32F40_41xxx || STM32F401xx */ } /* Return the Erase Status */ return status; } /** * @brief Erases all FLASH Sectors in Bank 1. * * @note This function can be used only for STM32F42xxx/43xxx devices. * * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * * @param VoltageRange: The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, * the operation will be done by half word (16-bit) * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, * the operation will be done by word (32-bit) * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, * the operation will be done by double word (64-bit) * * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange) { uint32_t tmp_psize = 0x0; FLASH_Status status = FLASH_COMPLETE; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); assert_param(IS_VOLTAGERANGE(VoltageRange)); if(VoltageRange == VoltageRange_1) { tmp_psize = FLASH_PSIZE_BYTE; } else if(VoltageRange == VoltageRange_2) { tmp_psize = FLASH_PSIZE_HALF_WORD; } else if(VoltageRange == VoltageRange_3) { tmp_psize = FLASH_PSIZE_WORD; } else { tmp_psize = FLASH_PSIZE_DOUBLE_WORD; } if(status == FLASH_COMPLETE) { /* if the previous operation is completed, proceed to erase all sectors */ FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= tmp_psize; FLASH->CR |= FLASH_CR_MER1; FLASH->CR |= FLASH_CR_STRT; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); /* if the erase operation is completed, disable the MER Bit */ FLASH->CR &= (~FLASH_CR_MER1); } /* Return the Erase Status */ return status; } /** * @brief Erases all FLASH Sectors in Bank 2. * * @note This function can be used only for STM32F42xxx/43xxx devices. * * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * * @param VoltageRange: The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, * the operation will be done by half word (16-bit) * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, * the operation will be done by word (32-bit) * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, * the operation will be done by double word (64-bit) * * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange) { uint32_t tmp_psize = 0x0; FLASH_Status status = FLASH_COMPLETE; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); assert_param(IS_VOLTAGERANGE(VoltageRange)); if(VoltageRange == VoltageRange_1) { tmp_psize = FLASH_PSIZE_BYTE; } else if(VoltageRange == VoltageRange_2) { tmp_psize = FLASH_PSIZE_HALF_WORD; } else if(VoltageRange == VoltageRange_3) { tmp_psize = FLASH_PSIZE_WORD; } else { tmp_psize = FLASH_PSIZE_DOUBLE_WORD; } if(status == FLASH_COMPLETE) { /* if the previous operation is completed, proceed to erase all sectors */ FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= tmp_psize; FLASH->CR |= FLASH_CR_MER2; FLASH->CR |= FLASH_CR_STRT; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); /* if the erase operation is completed, disable the MER Bit */ FLASH->CR &= (~FLASH_CR_MER2); } /* Return the Erase Status */ return status; } /** * @brief Programs a double word (64-bit) at a specified address. * @note This function must be used when the device voltage range is from * 2.7V to 3.6V and an External Vpp is present. * * @note If an erase and a program operations are requested simustaneously, * the erase operation is performed before the program one. * * @param Address: specifies the address to be programmed. * @param Data: specifies the data to be programmed. * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_FLASH_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { /* if the previous operation is completed, proceed to program the new data */ FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; FLASH->CR |= FLASH_CR_PG; *(__IO uint64_t*)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); /* if the program operation is completed, disable the PG Bit */ FLASH->CR &= (~FLASH_CR_PG); } /* Return the Program Status */ return status; } /** * @brief Programs a word (32-bit) at a specified address. * * @note This function must be used when the device voltage range is from 2.7V to 3.6V. * * @note If an erase and a program operations are requested simustaneously, * the erase operation is performed before the program one. * * @param Address: specifies the address to be programmed. * This parameter can be any address in Program memory zone or in OTP zone. * @param Data: specifies the data to be programmed. * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_FLASH_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { /* if the previous operation is completed, proceed to program the new data */ FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= FLASH_PSIZE_WORD; FLASH->CR |= FLASH_CR_PG; *(__IO uint32_t*)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); /* if the program operation is completed, disable the PG Bit */ FLASH->CR &= (~FLASH_CR_PG); } /* Return the Program Status */ return status; } /** * @brief Programs a half word (16-bit) at a specified address. * @note This function must be used when the device voltage range is from 2.1V to 3.6V. * * @note If an erase and a program operations are requested simustaneously, * the erase operation is performed before the program one. * * @param Address: specifies the address to be programmed. * This parameter can be any address in Program memory zone or in OTP zone. * @param Data: specifies the data to be programmed. * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_FLASH_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { /* if the previous operation is completed, proceed to program the new data */ FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= FLASH_PSIZE_HALF_WORD; FLASH->CR |= FLASH_CR_PG; *(__IO uint16_t*)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); /* if the program operation is completed, disable the PG Bit */ FLASH->CR &= (~FLASH_CR_PG); } /* Return the Program Status */ return status; } /** * @brief Programs a byte (8-bit) at a specified address. * @note This function can be used within all the device supply voltage ranges. * * @note If an erase and a program operations are requested simustaneously, * the erase operation is performed before the program one. * * @param Address: specifies the address to be programmed. * This parameter can be any address in Program memory zone or in OTP zone. * @param Data: specifies the data to be programmed. * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_FLASH_ADDRESS(Address)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { /* if the previous operation is completed, proceed to program the new data */ FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= FLASH_PSIZE_BYTE; FLASH->CR |= FLASH_CR_PG; *(__IO uint8_t*)Address = Data; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); /* if the program operation is completed, disable the PG Bit */ FLASH->CR &= (~FLASH_CR_PG); } /* Return the Program Status */ return status; } /** * @} */ /** @defgroup FLASH_Group3 Option Bytes Programming functions * @brief Option Bytes Programming functions * @verbatim =============================================================================== ##### Option Bytes Programming functions ##### =============================================================================== [..] This group includes the following functions: (+) void FLASH_OB_Unlock(void) (+) void FLASH_OB_Lock(void) (+) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) (+) void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState) (+) void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PCROPSelect) (+) void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState) (+) void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState) (+) void FLASH_OB_RDPConfig(uint8_t OB_RDP) (+) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) (+) void FLASH_OB_BORConfig(uint8_t OB_BOR) (+) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) (+) FLASH_Status FLASH_OB_Launch(void) (+) uint32_t FLASH_OB_GetUser(void) (+) uint8_t FLASH_OB_GetWRP(void) (+) uint8_t FLASH_OB_GetWRP1(void) (+) uint8_t FLASH_OB_GetPCROP(void) (+) uint8_t FLASH_OB_GetPCROP1(void) (+) uint8_t FLASH_OB_GetRDP(void) (+) uint8_t FLASH_OB_GetBOR(void) [..] The following function can be used only for STM32F42xxx/43xxx devices. (+) void FLASH_OB_BootConfig(uint8_t OB_BOOT) [..] Any operation of erase or program should follow these steps: (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control register access (#) Call one or several functions to program the desired Option Bytes: (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable the desired sector write protection (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure the user Option Bytes. (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level (#) Once all needed Option Bytes to be programmed are correctly written, call the FLASH_OB_Launch() function to launch the Option Bytes programming process. -@- When changing the IWDG mode from HW to SW or from SW to HW, a system reset is needed to make the change effective. (#) Call the FLASH_OB_Lock() function to disable the FLASH option control register access (recommended to protect the Option Bytes against possible unwanted operations) @endverbatim * @{ */ /** * @brief Unlocks the FLASH Option Control Registers access. * @param None * @retval None */ void FLASH_OB_Unlock(void) { if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) { /* Authorizes the Option Byte register programming */ FLASH->OPTKEYR = FLASH_OPT_KEY1; FLASH->OPTKEYR = FLASH_OPT_KEY2; } } /** * @brief Locks the FLASH Option Control Registers access. * @param None * @retval None */ void FLASH_OB_Lock(void) { /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; } /** * @brief Enables or disables the write protection of the desired sectors, for the first * 1 Mb of the Flash * * @note When the memory read protection level is selected (RDP level = 1), * it is not possible to program or erase the flash sector i if CortexM4 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). * * @param OB_WRP: specifies the sector(s) to be write protected or unprotected. * This parameter can be one of the following values: * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11 * @arg OB_WRP_Sector_All * @param Newstate: new state of the Write Protection. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_OB_WRP(OB_WRP)); assert_param(IS_FUNCTIONAL_STATE(NewState)); status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { if(NewState != DISABLE) { *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP); } else { *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP; } } } /** * @brief Enables or disables the write protection of the desired sectors, for the second * 1 Mb of the Flash * * @note This function can be used only for STM32F42xxx/43xxx devices. * * @note When the memory read out protection is selected (RDP level = 1), * it is not possible to program or erase the flash sector i if CortexM4 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). * * @param OB_WRP: specifies the sector(s) to be write protected or unprotected. * This parameter can be one of the following values: * @arg OB_WRP: A value between OB_WRP_Sector12 and OB_WRP_Sector23 * @arg OB_WRP_Sector_All * @param Newstate: new state of the Write Protection. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_OB_WRP(OB_WRP)); assert_param(IS_FUNCTIONAL_STATE(NewState)); status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { if(NewState != DISABLE) { *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_WRP); } else { *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_WRP; } } } /** * @brief Select the Protection Mode (SPRMOD). * * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx devices. * * @note After PCROP activation, Option Byte modification is not possible. * Exception made for the global Read Out Protection modification level (level1 to level0) * @note Once SPRMOD bit is active unprotection of a protected sector is not possible * * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag * * @note Some Precautions should be taken when activating the PCROP feature : * The active value of nWRPi bits is inverted when PCROP mode is active, this means if SPRMOD = 1 * and WRPi = 1 (default value), then the user sector i is read/write protected. * In order to avoid activation of PCROP Mode for undesired sectors, please follow the * below safety sequence : * - Disable PCROP for all Sectors using FLASH_OB_PCROPConfig(OB_PCROP_Sector_All, DISABLE) function * for Bank1 or FLASH_OB_PCROP1Config(OB_PCROP_Sector_All, DISABLE) function for Bank2 * - Enable PCROP for the desired Sector i using FLASH_OB_PCROPConfig(Sector i, ENABLE) function * - Activate the PCROP Mode FLASH_OB_PCROPSelectionConfig() function. * * @param OB_PCROP: Select the Protection Mode of nWPRi bits * This parameter can be one of the following values: * @arg OB_PcROP_Disable: nWRPi control the write protection of respective user sectors. * @arg OB_PcROP_Enable: nWRPi control the read&write protection (PCROP) of respective user sectors. * @retval None */ void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP) { uint8_t optiontmp = 0xFF; /* Check the parameters */ assert_param(IS_OB_PCROP_SELECT(OB_PcROP)); /* Mask SPRMOD bit */ optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); /* Update Option Byte */ *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PcROP | optiontmp); } /** * @brief Enables or disables the read/write protection (PCROP) of the desired * sectors, for the first 1 MB of the Flash. * * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx devices. * * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected. * This parameter can be one of the following values: * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector11 for * STM32F42xxx/43xxx devices and between OB_PCROP_Sector0 and * OB_PCROP_Sector5 for STM32F401xx devices. * @arg OB_PCROP_Sector_All * @param Newstate: new state of the Write Protection. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_OB_PCROP(OB_PCROP)); assert_param(IS_FUNCTIONAL_STATE(NewState)); status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { if(NewState != DISABLE) { *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_PCROP; } else { *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_PCROP); } } } /** * @brief Enables or disables the read/write protection (PCROP) of the desired * sectors * * @note This function can be used only for STM32F42xxx/43xxx devices. * * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected. * This parameter can be one of the following values: * @arg OB_PCROP: A value between OB_PCROP_Sector12 and OB_PCROP_Sector23 * @arg OB_PCROP_Sector_All * @param Newstate: new state of the Write Protection. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_OB_PCROP(OB_PCROP)); assert_param(IS_FUNCTIONAL_STATE(NewState)); status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { if(NewState != DISABLE) { *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_PCROP; } else { *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_PCROP); } } } /** * @brief Sets the read protection level. * @param OB_RDP: specifies the read protection level. * This parameter can be one of the following values: * @arg OB_RDP_Level_0: No protection * @arg OB_RDP_Level_1: Read protection of the memory * @arg OB_RDP_Level_2: Full chip protection * * /!\ Warning /!\ When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 * * @retval None */ void FLASH_OB_RDPConfig(uint8_t OB_RDP) { FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_OB_RDP(OB_RDP)); status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP; } } /** * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. * @param OB_IWDG: Selects the IWDG mode * This parameter can be one of the following values: * @arg OB_IWDG_SW: Software IWDG selected * @arg OB_IWDG_HW: Hardware IWDG selected * @param OB_STOP: Reset event when entering STOP mode. * This parameter can be one of the following values: * @arg OB_STOP_NoRST: No reset generated when entering in STOP * @arg OB_STOP_RST: Reset generated when entering in STOP * @param OB_STDBY: Reset event when entering Standby mode. * This parameter can be one of the following values: * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY * @arg OB_STDBY_RST: Reset generated when entering in STANDBY * @retval None */ void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) { uint8_t optiontmp = 0xFF; FLASH_Status status = FLASH_COMPLETE; /* Check the parameters */ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); assert_param(IS_OB_STOP_SOURCE(OB_STOP)); assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); if(status == FLASH_COMPLETE) { #if defined (STM32F427_437xx) || defined (STM32F429_439xx) /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */ optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F); #endif /* STM32F427_437xx || STM32F429_439xx */ #if defined (STM32F40_41xxx) || defined (STM32F401xx) /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */ optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F); #endif /* STM32F40_41xxx || STM32F401xx */ /* Update User Option Byte */ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp))); } } /** * @brief Configure the Dual Bank Boot. * * @note This function can be used only for STM32F42xxx/43xxx devices. * * @param OB_BOOT: specifies the Dual Bank Boot Option byte. * This parameter can be one of the following values: * @arg OB_Dual_BootEnabled: Dual Bank Boot Enable * @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled * @retval None */ void FLASH_OB_BootConfig(uint8_t OB_BOOT) { /* Check the parameters */ assert_param(IS_OB_BOOT(OB_BOOT)); /* Set Dual Bank Boot */ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2); *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOOT; } /** * @brief Sets the BOR Level. * @param OB_BOR: specifies the Option Bytes BOR Reset Level. * This parameter can be one of the following values: * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V * @retval None */ void FLASH_OB_BORConfig(uint8_t OB_BOR) { /* Check the parameters */ assert_param(IS_OB_BOR(OB_BOR)); /* Set the BOR Level */ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV); *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR; } /** * @brief Launch the option byte loading. * @param None * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_OB_Launch(void) { FLASH_Status status = FLASH_COMPLETE; /* Set the OPTSTRT bit in OPTCR register */ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT; /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation(); return status; } /** * @brief Returns the FLASH User Option Bytes values. * @param None * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) * and RST_STDBY(Bit2). */ uint8_t FLASH_OB_GetUser(void) { /* Return the User Option Byte */ return (uint8_t)(FLASH->OPTCR >> 5); } /** * @brief Returns the FLASH Write Protection Option Bytes value. * @param None * @retval The FLASH Write Protection Option Bytes value */ uint16_t FLASH_OB_GetWRP(void) { /* Return the FLASH write protection Register value */ return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); } /** * @brief Returns the FLASH Write Protection Option Bytes value. * * @note This function can be used only for STM32F42xxx/43xxx devices. * * @param None * @retval The FLASH Write Protection Option Bytes value */ uint16_t FLASH_OB_GetWRP1(void) { /* Return the FLASH write protection Register value */ return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); } /** * @brief Returns the FLASH PC Read/Write Protection Option Bytes value. * * @note This function can be used only for STM32F42xxx/43xxx devices and STM32F401xx devices. * * @param None * @retval The FLASH PC Read/Write Protection Option Bytes value */ uint16_t FLASH_OB_GetPCROP(void) { /* Return the FLASH PC Read/write protection Register value */ return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); } /** * @brief Returns the FLASH PC Read/Write Protection Option Bytes value. * * @note This function can be used only for STM32F42xxx/43xxx devices. * * @param None * @retval The FLASH PC Read/Write Protection Option Bytes value */ uint16_t FLASH_OB_GetPCROP1(void) { /* Return the FLASH write protection Register value */ return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); } /** * @brief Returns the FLASH Read Protection level. * @param None * @retval FLASH ReadOut Protection Status: * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set * - RESET, when OB_RDP_Level_0 is set */ FlagStatus FLASH_OB_GetRDP(void) { FlagStatus readstatus = RESET; if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0)) { readstatus = SET; } else { readstatus = RESET; } return readstatus; } /** * @brief Returns the FLASH BOR level. * @param None * @retval The FLASH BOR level: * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V */ uint8_t FLASH_OB_GetBOR(void) { /* Return the FLASH BOR level */ return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C); } /** * @} */ /** @defgroup FLASH_Group4 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified FLASH interrupts. * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg FLASH_IT_ERR: FLASH Error Interrupt * @arg FLASH_IT_EOP: FLASH end of operation Interrupt * @retval None */ void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FLASH_IT(FLASH_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if(NewState != DISABLE) { /* Enable the interrupt sources */ FLASH->CR |= FLASH_IT; } else { /* Disable the interrupt sources */ FLASH->CR &= ~(uint32_t)FLASH_IT; } } /** * @brief Checks whether the specified FLASH flag is set or not. * @param FLASH_FLAG: specifies the FLASH flag to check. * This parameter can be one of the following values: * @arg FLASH_FLAG_EOP: FLASH End of Operation flag * @arg FLASH_FLAG_OPERR: FLASH operation Error flag * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag * @arg FLASH_FLAG_RDERR: FLASH (PCROP) Read Protection error flag (STM32F42/43xxx and STM32F401xx devices) * @arg FLASH_FLAG_BSY: FLASH Busy flag * @retval The new state of FLASH_FLAG (SET or RESET). */ FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } /* Return the new state of FLASH_FLAG (SET or RESET) */ return bitstatus; } /** * @brief Clears the FLASH's pending flags. * @param FLASH_FLAG: specifies the FLASH flags to clear. * This parameter can be any combination of the following values: * @arg FLASH_FLAG_EOP: FLASH End of Operation flag * @arg FLASH_FLAG_OPERR: FLASH operation Error flag * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag * @arg FLASH_FLAG_RDERR: FLASH Read Protection error flag (STM32F42/43xxx and STM32F401xx devices) * @retval None */ void FLASH_ClearFlag(uint32_t FLASH_FLAG) { /* Check the parameters */ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); /* Clear the flags */ FLASH->SR = FLASH_FLAG; } /** * @brief Returns the FLASH Status. * @param None * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_RD, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_GetStatus(void) { FLASH_Status flashstatus = FLASH_COMPLETE; if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) { flashstatus = FLASH_BUSY; } else { if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00) { flashstatus = FLASH_ERROR_WRP; } else { if((FLASH->SR & FLASH_FLAG_RDERR) != (uint32_t)0x00) { flashstatus = FLASH_ERROR_RD; } else { if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00) { flashstatus = FLASH_ERROR_PROGRAM; } else { if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00) { flashstatus = FLASH_ERROR_OPERATION; } else { flashstatus = FLASH_COMPLETE; } } } } } /* Return the FLASH Status */ return flashstatus; } /** * @brief Waits for a FLASH operation to complete. * @param None * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. */ FLASH_Status FLASH_WaitForLastOperation(void) { __IO FLASH_Status status = FLASH_COMPLETE; /* Check for the FLASH Status */ status = FLASH_GetStatus(); /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ while(status == FLASH_BUSY) { status = FLASH_GetStatus(); } /* Return the operation status */ return status; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c ================================================ /** ****************************************************************************** * @file stm32f4xx_fmc.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the FMC peripheral: * + Interface with SRAM, PSRAM, NOR and OneNAND memories * + Interface with NAND memories * + Interface with 16-bit PC Card compatible memories * + Interface with SDRAM memories * + Interrupts and flags management * ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_fmc.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup FMC * @brief FMC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* --------------------- FMC registers bit mask ---------------------------- */ /* FMC BCRx Mask */ #define BCR_MBKEN_SET ((uint32_t)0x00000001) #define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE) #define BCR_FACCEN_SET ((uint32_t)0x00000040) /* FMC PCRx Mask */ #define PCR_PBKEN_SET ((uint32_t)0x00000004) #define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB) #define PCR_ECCEN_SET ((uint32_t)0x00000040) #define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF) #define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008) /* FMC SDCRx write protection Mask*/ #define SDCR_WriteProtection_RESET ((uint32_t)0x00007DFF) /* FMC SDCMR Mask*/ #define SDCMR_CTB1_RESET ((uint32_t)0x003FFFEF) #define SDCMR_CTB2_RESET ((uint32_t)0x003FFFF7) #define SDCMR_CTB1_2_RESET ((uint32_t)0x003FFFE7) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup FMC_Private_Functions * @{ */ /** @defgroup FMC_Group1 NOR/SRAM Controller functions * @brief NOR/SRAM Controller functions * @verbatim =============================================================================== ##### NOR and SRAM Controller functions ##### =============================================================================== [..] The following sequence should be followed to configure the FMC to interface with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank: (#) Enable the clock for the FMC and associated GPIOs using the following functions: RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); (#) FMC pins configuration (++) Connect the involved FMC pins to AF12 using the following function GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); (++) Configure these FMC pins in alternate function mode by calling the function GPIO_Init(); (#) Declare a FMC_NORSRAMInitTypeDef structure, for example: FMC_NORSRAMInitTypeDef FMC_NORSRAMInitStructure; and fill the FMC_NORSRAMInitStructure variable with the allowed values of the structure member. (#) Initialize the NOR/SRAM Controller by calling the function FMC_NORSRAMInit(&FMC_NORSRAMInitStructure); (#) Then enable the NOR/SRAM Bank, for example: FMC_NORSRAMCmd(FMC_Bank1_NORSRAM2, ENABLE); (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. @endverbatim * @{ */ /** * @brief De-initializes the FMC NOR/SRAM Banks registers to their default * reset values. * @param FMC_Bank: specifies the FMC Bank to be used * This parameter can be one of the following values: * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1 * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2 * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3 * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4 * @retval None */ void FMC_NORSRAMDeInit(uint32_t FMC_Bank) { /* Check the parameter */ assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank)); /* FMC_Bank1_NORSRAM1 */ if(FMC_Bank == FMC_Bank1_NORSRAM1) { FMC_Bank1->BTCR[FMC_Bank] = 0x000030DB; } /* FMC_Bank1_NORSRAM2, FMC_Bank1_NORSRAM3 or FMC_Bank1_NORSRAM4 */ else { FMC_Bank1->BTCR[FMC_Bank] = 0x000030D2; } FMC_Bank1->BTCR[FMC_Bank + 1] = 0x0FFFFFFF; FMC_Bank1E->BWTR[FMC_Bank] = 0x0FFFFFFF; } /** * @brief Initializes the FMC NOR/SRAM Banks according to the specified * parameters in the FMC_NORSRAMInitStruct. * @param FMC_NORSRAMInitStruct : pointer to a FMC_NORSRAMInitTypeDef structure * that contains the configuration information for the FMC NOR/SRAM * specified Banks. * @retval None */ void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct) { uint32_t tmpr = 0; /* Check the parameters */ assert_param(IS_FMC_NORSRAM_BANK(FMC_NORSRAMInitStruct->FMC_Bank)); assert_param(IS_FMC_MUX(FMC_NORSRAMInitStruct->FMC_DataAddressMux)); assert_param(IS_FMC_MEMORY(FMC_NORSRAMInitStruct->FMC_MemoryType)); assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(FMC_NORSRAMInitStruct->FMC_MemoryDataWidth)); assert_param(IS_FMC_BURSTMODE(FMC_NORSRAMInitStruct->FMC_BurstAccessMode)); assert_param(IS_FMC_WAIT_POLARITY(FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity)); assert_param(IS_FMC_WRAP_MODE(FMC_NORSRAMInitStruct->FMC_WrapMode)); assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(FMC_NORSRAMInitStruct->FMC_WaitSignalActive)); assert_param(IS_FMC_WRITE_OPERATION(FMC_NORSRAMInitStruct->FMC_WriteOperation)); assert_param(IS_FMC_WAITE_SIGNAL(FMC_NORSRAMInitStruct->FMC_WaitSignal)); assert_param(IS_FMC_EXTENDED_MODE(FMC_NORSRAMInitStruct->FMC_ExtendedMode)); assert_param(IS_FMC_ASYNWAIT(FMC_NORSRAMInitStruct->FMC_AsynchronousWait)); assert_param(IS_FMC_WRITE_BURST(FMC_NORSRAMInitStruct->FMC_WriteBurst)); assert_param(IS_FMC_CONTINOUS_CLOCK(FMC_NORSRAMInitStruct->FMC_ContinousClock)); assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime)); assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime)); assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime)); assert_param(IS_FMC_TURNAROUND_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration)); assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)); assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency)); assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode)); /* NOR/SRAM Bank control register configuration */ FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] = (uint32_t)FMC_NORSRAMInitStruct->FMC_DataAddressMux | FMC_NORSRAMInitStruct->FMC_MemoryType | FMC_NORSRAMInitStruct->FMC_MemoryDataWidth | FMC_NORSRAMInitStruct->FMC_BurstAccessMode | FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity | FMC_NORSRAMInitStruct->FMC_WrapMode | FMC_NORSRAMInitStruct->FMC_WaitSignalActive | FMC_NORSRAMInitStruct->FMC_WriteOperation | FMC_NORSRAMInitStruct->FMC_WaitSignal | FMC_NORSRAMInitStruct->FMC_ExtendedMode | FMC_NORSRAMInitStruct->FMC_AsynchronousWait | FMC_NORSRAMInitStruct->FMC_WriteBurst | FMC_NORSRAMInitStruct->FMC_ContinousClock; if(FMC_NORSRAMInitStruct->FMC_MemoryType == FMC_MemoryType_NOR) { FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] |= (uint32_t)BCR_FACCEN_SET; } /* Configure Continuous clock feature when bank2..4 is used */ if((FMC_NORSRAMInitStruct->FMC_ContinousClock == FMC_CClock_SyncAsync) && (FMC_NORSRAMInitStruct->FMC_Bank != FMC_Bank1_NORSRAM1)) { tmpr = (uint32_t)((FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1]) & ~(((uint32_t)0x0F) << 20)); FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_NORSRAMInitStruct->FMC_ContinousClock; FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_BurstAccessMode_Enable; FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1] = (uint32_t)(tmpr | (((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)-1) << 20)); } /* NOR/SRAM Bank timing register configuration */ FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank+1] = (uint32_t)FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime | (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime << 4) | (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime << 8) | (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration << 16) | ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision) << 20) | ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency) << 24) | FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode; /* NOR/SRAM Bank timing register for write configuration, if extended mode is used */ if(FMC_NORSRAMInitStruct->FMC_ExtendedMode == FMC_ExtendedMode_Enable) { assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime)); assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime)); assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime)); assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision)); assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency)); assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode)); FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] = (uint32_t)FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime | (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime << 4 )| (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime << 8) | ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision) << 20) | ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency) << 24) | FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode; } else { FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] = 0x0FFFFFFF; } } /** * @brief Fills each FMC_NORSRAMInitStruct member with its default value. * @param FMC_NORSRAMInitStruct: pointer to a FMC_NORSRAMInitTypeDef structure * which will be initialized. * @retval None */ void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct) { /* Reset NOR/SRAM Init structure parameters values */ FMC_NORSRAMInitStruct->FMC_Bank = FMC_Bank1_NORSRAM1; FMC_NORSRAMInitStruct->FMC_DataAddressMux = FMC_DataAddressMux_Enable; FMC_NORSRAMInitStruct->FMC_MemoryType = FMC_MemoryType_SRAM; FMC_NORSRAMInitStruct->FMC_MemoryDataWidth = FMC_NORSRAM_MemoryDataWidth_16b; FMC_NORSRAMInitStruct->FMC_BurstAccessMode = FMC_BurstAccessMode_Disable; FMC_NORSRAMInitStruct->FMC_AsynchronousWait = FMC_AsynchronousWait_Disable; FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low; FMC_NORSRAMInitStruct->FMC_WrapMode = FMC_WrapMode_Disable; FMC_NORSRAMInitStruct->FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState; FMC_NORSRAMInitStruct->FMC_WriteOperation = FMC_WriteOperation_Enable; FMC_NORSRAMInitStruct->FMC_WaitSignal = FMC_WaitSignal_Enable; FMC_NORSRAMInitStruct->FMC_ExtendedMode = FMC_ExtendedMode_Disable; FMC_NORSRAMInitStruct->FMC_WriteBurst = FMC_WriteBurst_Disable; FMC_NORSRAMInitStruct->FMC_ContinousClock = FMC_CClock_SyncOnly; FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime = 15; FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime = 15; FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime = 255; FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration = 15; FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision = 15; FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency = 15; FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode = FMC_AccessMode_A; FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime = 15; FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime = 15; FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime = 255; FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_BusTurnAroundDuration = 15; FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision = 15; FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency = 15; FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode = FMC_AccessMode_A; } /** * @brief Enables or disables the specified NOR/SRAM Memory Bank. * @param FMC_Bank: specifies the FMC Bank to be used * This parameter can be one of the following values: * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1 * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2 * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3 * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4 * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE. * @retval None */ void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState) { assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ FMC_Bank1->BTCR[FMC_Bank] |= BCR_MBKEN_SET; } else { /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ FMC_Bank1->BTCR[FMC_Bank] &= BCR_MBKEN_RESET; } } /** * @} */ /** @defgroup FMC_Group2 NAND Controller functions * @brief NAND Controller functions * @verbatim =============================================================================== ##### NAND Controller functions ##### =============================================================================== [..] The following sequence should be followed to configure the FMC to interface with 8-bit or 16-bit NAND memory connected to the NAND Bank: (#) Enable the clock for the FMC and associated GPIOs using the following functions: (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); (#) FMC pins configuration (++) Connect the involved FMC pins to AF12 using the following function GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); (++) Configure these FMC pins in alternate function mode by calling the function GPIO_Init(); (#) Declare a FMC_NANDInitTypeDef structure, for example: FMC_NANDInitTypeDef FMC_NANDInitStructure; and fill the FMC_NANDInitStructure variable with the allowed values of the structure member. (#) Initialize the NAND Controller by calling the function FMC_NANDInit(&FMC_NANDInitStructure); (#) Then enable the NAND Bank, for example: FMC_NANDCmd(FMC_Bank3_NAND, ENABLE); (#) At this stage you can read/write from/to the memory connected to the NAND Bank. [..] (@) To enable the Error Correction Code (ECC), you have to use the function FMC_NANDECCCmd(FMC_Bank3_NAND, ENABLE); [..] (@) and to get the current ECC value you have to use the function ECCval = FMC_GetECC(FMC_Bank3_NAND); @endverbatim * @{ */ /** * @brief De-initializes the FMC NAND Banks registers to their default reset values. * @param FMC_Bank: specifies the FMC Bank to be used * This parameter can be one of the following values: * @arg FMC_Bank2_NAND: FMC Bank2 NAND * @arg FMC_Bank3_NAND: FMC Bank3 NAND * @retval None */ void FMC_NANDDeInit(uint32_t FMC_Bank) { /* Check the parameter */ assert_param(IS_FMC_NAND_BANK(FMC_Bank)); if(FMC_Bank == FMC_Bank2_NAND) { /* Set the FMC_Bank2 registers to their reset values */ FMC_Bank2->PCR2 = 0x00000018; FMC_Bank2->SR2 = 0x00000040; FMC_Bank2->PMEM2 = 0xFCFCFCFC; FMC_Bank2->PATT2 = 0xFCFCFCFC; } /* FMC_Bank3_NAND */ else { /* Set the FMC_Bank3 registers to their reset values */ FMC_Bank3->PCR3 = 0x00000018; FMC_Bank3->SR3 = 0x00000040; FMC_Bank3->PMEM3 = 0xFCFCFCFC; FMC_Bank3->PATT3 = 0xFCFCFCFC; } } /** * @brief Initializes the FMC NAND Banks according to the specified parameters * in the FMC_NANDInitStruct. * @param FMC_NANDInitStruct : pointer to a FMC_NANDInitTypeDef structure that * contains the configuration information for the FMC NAND specified Banks. * @retval None */ void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct) { uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; /* Check the parameters */ assert_param(IS_FMC_NAND_BANK(FMC_NANDInitStruct->FMC_Bank)); assert_param(IS_FMC_WAIT_FEATURE(FMC_NANDInitStruct->FMC_Waitfeature)); assert_param(IS_FMC_NAND_MEMORY_WIDTH(FMC_NANDInitStruct->FMC_MemoryDataWidth)); assert_param(IS_FMC_ECC_STATE(FMC_NANDInitStruct->FMC_ECC)); assert_param(IS_FMC_ECCPAGE_SIZE(FMC_NANDInitStruct->FMC_ECCPageSize)); assert_param(IS_FMC_TCLR_TIME(FMC_NANDInitStruct->FMC_TCLRSetupTime)); assert_param(IS_FMC_TAR_TIME(FMC_NANDInitStruct->FMC_TARSetupTime)); assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime)); assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime)); assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime)); assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime)); assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime)); assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime)); assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime)); assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime)); /* Set the tmppcr value according to FMC_NANDInitStruct parameters */ tmppcr = (uint32_t)FMC_NANDInitStruct->FMC_Waitfeature | PCR_MEMORYTYPE_NAND | FMC_NANDInitStruct->FMC_MemoryDataWidth | FMC_NANDInitStruct->FMC_ECC | FMC_NANDInitStruct->FMC_ECCPageSize | (FMC_NANDInitStruct->FMC_TCLRSetupTime << 9 )| (FMC_NANDInitStruct->FMC_TARSetupTime << 13); /* Set tmppmem value according to FMC_CommonSpaceTimingStructure parameters */ tmppmem = (uint32_t)FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime | (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) | (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)| (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24); /* Set tmppatt value according to FMC_AttributeSpaceTimingStructure parameters */ tmppatt = (uint32_t)FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime | (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) | (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)| (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24); if(FMC_NANDInitStruct->FMC_Bank == FMC_Bank2_NAND) { /* FMC_Bank2_NAND registers configuration */ FMC_Bank2->PCR2 = tmppcr; FMC_Bank2->PMEM2 = tmppmem; FMC_Bank2->PATT2 = tmppatt; } else { /* FMC_Bank3_NAND registers configuration */ FMC_Bank3->PCR3 = tmppcr; FMC_Bank3->PMEM3 = tmppmem; FMC_Bank3->PATT3 = tmppatt; } } /** * @brief Fills each FMC_NANDInitStruct member with its default value. * @param FMC_NANDInitStruct: pointer to a FMC_NANDInitTypeDef structure which * will be initialized. * @retval None */ void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct) { /* Reset NAND Init structure parameters values */ FMC_NANDInitStruct->FMC_Bank = FMC_Bank2_NAND; FMC_NANDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable; FMC_NANDInitStruct->FMC_MemoryDataWidth = FMC_NAND_MemoryDataWidth_16b; FMC_NANDInitStruct->FMC_ECC = FMC_ECC_Disable; FMC_NANDInitStruct->FMC_ECCPageSize = FMC_ECCPageSize_256Bytes; FMC_NANDInitStruct->FMC_TCLRSetupTime = 0x0; FMC_NANDInitStruct->FMC_TARSetupTime = 0x0; FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252; FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252; FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252; FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252; FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252; FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252; FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252; FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252; } /** * @brief Enables or disables the specified NAND Memory Bank. * @param FMC_Bank: specifies the FMC Bank to be used * This parameter can be one of the following values: * @arg FMC_Bank2_NAND: FMC Bank2 NAND * @arg FMC_Bank3_NAND: FMC Bank3 NAND * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE. * @retval None */ void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState) { assert_param(IS_FMC_NAND_BANK(FMC_Bank)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ if(FMC_Bank == FMC_Bank2_NAND) { FMC_Bank2->PCR2 |= PCR_PBKEN_SET; } else { FMC_Bank3->PCR3 |= PCR_PBKEN_SET; } } else { /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ if(FMC_Bank == FMC_Bank2_NAND) { FMC_Bank2->PCR2 &= PCR_PBKEN_RESET; } else { FMC_Bank3->PCR3 &= PCR_PBKEN_RESET; } } } /** * @brief Enables or disables the FMC NAND ECC feature. * @param FMC_Bank: specifies the FMC Bank to be used * This parameter can be one of the following values: * @arg FMC_Bank2_NAND: FMC Bank2 NAND * @arg FMC_Bank3_NAND: FMC Bank3 NAND * @param NewState: new state of the FMC NAND ECC feature. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState) { assert_param(IS_FMC_NAND_BANK(FMC_Bank)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ if(FMC_Bank == FMC_Bank2_NAND) { FMC_Bank2->PCR2 |= PCR_ECCEN_SET; } else { FMC_Bank3->PCR3 |= PCR_ECCEN_SET; } } else { /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ if(FMC_Bank == FMC_Bank2_NAND) { FMC_Bank2->PCR2 &= PCR_ECCEN_RESET; } else { FMC_Bank3->PCR3 &= PCR_ECCEN_RESET; } } } /** * @brief Returns the error correction code register value. * @param FMC_Bank: specifies the FMC Bank to be used * This parameter can be one of the following values: * @arg FMC_Bank2_NAND: FMC Bank2 NAND * @arg FMC_Bank3_NAND: FMC Bank3 NAND * @retval The Error Correction Code (ECC) value. */ uint32_t FMC_GetECC(uint32_t FMC_Bank) { uint32_t eccval = 0x00000000; if(FMC_Bank == FMC_Bank2_NAND) { /* Get the ECCR2 register value */ eccval = FMC_Bank2->ECCR2; } else { /* Get the ECCR3 register value */ eccval = FMC_Bank3->ECCR3; } /* Return the error correction code value */ return(eccval); } /** * @} */ /** @defgroup FMC_Group3 PCCARD Controller functions * @brief PCCARD Controller functions * @verbatim =============================================================================== ##### PCCARD Controller functions ##### =============================================================================== [..] he following sequence should be followed to configure the FMC to interface with 16-bit PC Card compatible memory connected to the PCCARD Bank: (#) Enable the clock for the FMC and associated GPIOs using the following functions: (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); (#) FMC pins configuration (++) Connect the involved FMC pins to AF12 using the following function GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); (++) Configure these FMC pins in alternate function mode by calling the function GPIO_Init(); (#) Declare a FMC_PCCARDInitTypeDef structure, for example: FMC_PCCARDInitTypeDef FMC_PCCARDInitStructure; and fill the FMC_PCCARDInitStructure variable with the allowed values of the structure member. (#) Initialize the PCCARD Controller by calling the function FMC_PCCARDInit(&FMC_PCCARDInitStructure); (#) Then enable the PCCARD Bank: FMC_PCCARDCmd(ENABLE); (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank. @endverbatim * @{ */ /** * @brief De-initializes the FMC PCCARD Bank registers to their default reset values. * @param None * @retval None */ void FMC_PCCARDDeInit(void) { /* Set the FMC_Bank4 registers to their reset values */ FMC_Bank4->PCR4 = 0x00000018; FMC_Bank4->SR4 = 0x00000000; FMC_Bank4->PMEM4 = 0xFCFCFCFC; FMC_Bank4->PATT4 = 0xFCFCFCFC; FMC_Bank4->PIO4 = 0xFCFCFCFC; } /** * @brief Initializes the FMC PCCARD Bank according to the specified parameters * in the FMC_PCCARDInitStruct. * @param FMC_PCCARDInitStruct : pointer to a FMC_PCCARDInitTypeDef structure * that contains the configuration information for the FMC PCCARD Bank. * @retval None */ void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct) { /* Check the parameters */ assert_param(IS_FMC_WAIT_FEATURE(FMC_PCCARDInitStruct->FMC_Waitfeature)); assert_param(IS_FMC_TCLR_TIME(FMC_PCCARDInitStruct->FMC_TCLRSetupTime)); assert_param(IS_FMC_TAR_TIME(FMC_PCCARDInitStruct->FMC_TARSetupTime)); assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime)); assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime)); assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime)); assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime)); assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime)); assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime)); assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime)); assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime)); assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime)); assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime)); assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime)); assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime)); /* Set the PCR4 register value according to FMC_PCCARDInitStruct parameters */ FMC_Bank4->PCR4 = (uint32_t)FMC_PCCARDInitStruct->FMC_Waitfeature | FMC_NAND_MemoryDataWidth_16b | (FMC_PCCARDInitStruct->FMC_TCLRSetupTime << 9) | (FMC_PCCARDInitStruct->FMC_TARSetupTime << 13); /* Set PMEM4 register value according to FMC_CommonSpaceTimingStructure parameters */ FMC_Bank4->PMEM4 = (uint32_t)FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime | (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) | (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)| (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24); /* Set PATT4 register value according to FMC_AttributeSpaceTimingStructure parameters */ FMC_Bank4->PATT4 = (uint32_t)FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime | (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) | (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)| (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24); /* Set PIO4 register value according to FMC_IOSpaceTimingStructure parameters */ FMC_Bank4->PIO4 = (uint32_t)FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime | (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime << 8) | (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime << 16)| (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime << 24); } /** * @brief Fills each FMC_PCCARDInitStruct member with its default value. * @param FMC_PCCARDInitStruct: pointer to a FMC_PCCARDInitTypeDef structure * which will be initialized. * @retval None */ void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct) { /* Reset PCCARD Init structure parameters values */ FMC_PCCARDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable; FMC_PCCARDInitStruct->FMC_TCLRSetupTime = 0; FMC_PCCARDInitStruct->FMC_TARSetupTime = 0; FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252; FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252; FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252; FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252; FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252; FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252; FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252; FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252; FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime = 252; FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime = 252; FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime = 252; FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime = 252; } /** * @brief Enables or disables the PCCARD Memory Bank. * @param NewState: new state of the PCCARD Memory Bank. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FMC_PCCARDCmd(FunctionalState NewState) { assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ FMC_Bank4->PCR4 |= PCR_PBKEN_SET; } else { /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ FMC_Bank4->PCR4 &= PCR_PBKEN_RESET; } } /** * @} */ /** @defgroup FMC_Group4 SDRAM Controller functions * @brief SDRAM Controller functions * @verbatim =============================================================================== ##### SDRAM Controller functions ##### =============================================================================== [..] The following sequence should be followed to configure the FMC to interface with SDRAM memory connected to the SDRAM Bank 1 or SDRAM bank 2: (#) Enable the clock for the FMC and associated GPIOs using the following functions: (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); (#) FMC pins configuration (++) Connect the involved FMC pins to AF12 using the following function GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); (++) Configure these FMC pins in alternate function mode by calling the function GPIO_Init(); (#) Declare a FMC_SDRAMInitTypeDef structure, for example: FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure; and fill the FMC_SDRAMInitStructure variable with the allowed values of the structure member. (#) Initialize the SDRAM Controller by calling the function FMC_SDRAMInit(&FMC_SDRAMInitStructure); (#) Declare a FMC_SDRAMCommandTypeDef structure, for example: FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; and fill the FMC_SDRAMCommandStructure variable with the allowed values of the structure member. (#) Configure the SDCMR register with the desired command parameters by calling the function FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); (#) At this stage, the SDRAM memory is ready for any valid command. @endverbatim * @{ */ /** * @brief De-initializes the FMC SDRAM Banks registers to their default * reset values. * @param FMC_Bank: specifies the FMC Bank to be used * This parameter can be one of the following values: * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM * @retval None */ void FMC_SDRAMDeInit(uint32_t FMC_Bank) { /* Check the parameter */ assert_param(IS_FMC_SDRAM_BANK(FMC_Bank)); FMC_Bank5_6->SDCR[FMC_Bank] = 0x000002D0; FMC_Bank5_6->SDTR[FMC_Bank] = 0x0FFFFFFF; FMC_Bank5_6->SDCMR = 0x00000000; FMC_Bank5_6->SDRTR = 0x00000000; FMC_Bank5_6->SDSR = 0x00000000; } /** * @brief Initializes the FMC SDRAM Banks according to the specified * parameters in the FMC_SDRAMInitStruct. * @param FMC_SDRAMInitStruct : pointer to a FMC_SDRAMInitTypeDef structure * that contains the configuration information for the FMC SDRAM * specified Banks. * @retval None */ void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct) { /* temporary registers */ uint32_t tmpr1 = 0; uint32_t tmpr2 = 0; uint32_t tmpr3 = 0; uint32_t tmpr4 = 0; /* Check the parameters */ /* Control parameters */ assert_param(IS_FMC_SDRAM_BANK(FMC_SDRAMInitStruct->FMC_Bank)); assert_param(IS_FMC_COLUMNBITS_NUMBER(FMC_SDRAMInitStruct->FMC_ColumnBitsNumber)); assert_param(IS_FMC_ROWBITS_NUMBER(FMC_SDRAMInitStruct->FMC_RowBitsNumber)); assert_param(IS_FMC_SDMEMORY_WIDTH(FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth)); assert_param(IS_FMC_INTERNALBANK_NUMBER(FMC_SDRAMInitStruct->FMC_InternalBankNumber)); assert_param(IS_FMC_CAS_LATENCY(FMC_SDRAMInitStruct->FMC_CASLatency)); assert_param(IS_FMC_WRITE_PROTECTION(FMC_SDRAMInitStruct->FMC_WriteProtection)); assert_param(IS_FMC_SDCLOCK_PERIOD(FMC_SDRAMInitStruct->FMC_SDClockPeriod)); assert_param(IS_FMC_READ_BURST(FMC_SDRAMInitStruct->FMC_ReadBurst)); assert_param(IS_FMC_READPIPE_DELAY(FMC_SDRAMInitStruct->FMC_ReadPipeDelay)); /* Timing parameters */ assert_param(IS_FMC_LOADTOACTIVE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)); assert_param(IS_FMC_EXITSELFREFRESH_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)); assert_param(IS_FMC_SELFREFRESH_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)); assert_param(IS_FMC_ROWCYCLE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)); assert_param(IS_FMC_WRITE_RECOVERY_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)); assert_param(IS_FMC_RP_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)); assert_param(IS_FMC_RCD_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)); /* SDRAM bank control register configuration */ tmpr1 = (uint32_t)FMC_SDRAMInitStruct->FMC_ColumnBitsNumber | FMC_SDRAMInitStruct->FMC_RowBitsNumber | FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth | FMC_SDRAMInitStruct->FMC_InternalBankNumber | FMC_SDRAMInitStruct->FMC_CASLatency | FMC_SDRAMInitStruct->FMC_WriteProtection | FMC_SDRAMInitStruct->FMC_SDClockPeriod | FMC_SDRAMInitStruct->FMC_ReadBurst | FMC_SDRAMInitStruct->FMC_ReadPipeDelay; if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM ) { FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1; } else /* SDCR2 "don't care" bits configuration */ { tmpr3 = (uint32_t)FMC_SDRAMInitStruct->FMC_SDClockPeriod | FMC_SDRAMInitStruct->FMC_ReadBurst | FMC_SDRAMInitStruct->FMC_ReadPipeDelay; FMC_Bank5_6->SDCR[FMC_Bank1_SDRAM] = tmpr3; FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1; } /* SDRAM bank timing register configuration */ if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM ) { tmpr2 = (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) | (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) | (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) | (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) | (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16) | (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20) | (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)-1) << 24); FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2; } else /* SDTR "don't care bits configuration */ { tmpr2 = (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) | (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) | (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) | (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16); tmpr4 = (uint32_t)(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) | (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20); FMC_Bank5_6->SDTR[FMC_Bank1_SDRAM] = tmpr4; FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2; } } /** * @brief Fills each FMC_SDRAMInitStruct member with its default value. * @param FMC_SDRAMInitStruct: pointer to a FMC_SDRAMInitTypeDef structure * which will be initialized. * @retval None */ void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct) { /* Reset SDRAM Init structure parameters values */ FMC_SDRAMInitStruct->FMC_Bank = FMC_Bank1_SDRAM; FMC_SDRAMInitStruct->FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; FMC_SDRAMInitStruct->FMC_RowBitsNumber = FMC_RowBits_Number_11b; FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b; FMC_SDRAMInitStruct->FMC_InternalBankNumber = FMC_InternalBank_Number_4; FMC_SDRAMInitStruct->FMC_CASLatency = FMC_CAS_Latency_1; FMC_SDRAMInitStruct->FMC_WriteProtection = FMC_Write_Protection_Enable; FMC_SDRAMInitStruct->FMC_SDClockPeriod = FMC_SDClock_Disable; FMC_SDRAMInitStruct->FMC_ReadBurst = FMC_Read_Burst_Disable; FMC_SDRAMInitStruct->FMC_ReadPipeDelay = FMC_ReadPipe_Delay_0; FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay = 16; FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay = 16; FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime = 16; FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay = 16; FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime = 16; FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay = 16; FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay = 16; } /** * @brief Configures the SDRAM memory command issued when the device is accessed. * @param FMC_SDRAMCommandStruct: pointer to a FMC_SDRAMCommandTypeDef structure * which will be configured. * @retval None */ void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct) { uint32_t tmpr = 0x0; /* check parameters */ assert_param(IS_FMC_COMMAND_MODE(FMC_SDRAMCommandStruct->FMC_CommandMode)); assert_param(IS_FMC_COMMAND_TARGET(FMC_SDRAMCommandStruct->FMC_CommandTarget)); assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber)); assert_param(IS_FMC_MODE_REGISTER(FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition)); tmpr = (uint32_t)(FMC_SDRAMCommandStruct->FMC_CommandMode | FMC_SDRAMCommandStruct->FMC_CommandTarget | (((FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber)-1)<<5) | ((FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition)<<9)); FMC_Bank5_6->SDCMR = tmpr; } /** * @brief Returns the indicated FMC SDRAM bank mode status. * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. * @retval The FMC SDRAM bank mode status */ uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank) { uint32_t tmpreg = 0; /* Check the parameter */ assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank)); /* Get the busy flag status */ if(SDRAM_Bank == FMC_Bank1_SDRAM) { tmpreg = (uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES1); } else { tmpreg = ((uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES2) >> 2); } /* Return the mode status */ return tmpreg; } /** * @brief defines the SDRAM Memory Refresh rate. * @param FMC_Count: specifies the Refresh timer count. * @retval None */ void FMC_SetRefreshCount(uint32_t FMC_Count) { /* check the parameters */ assert_param(IS_FMC_REFRESH_COUNT(FMC_Count)); FMC_Bank5_6->SDRTR |= (FMC_Count<<1); } /** * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. * @param FMC_Number: specifies the auto Refresh number. * @retval None */ void FMC_SetAutoRefresh_Number(uint32_t FMC_Number) { /* check the parameters */ assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_Number)); FMC_Bank5_6->SDCMR |= (FMC_Number << 5); } /** * @brief Enables or disables write protection to the specified FMC SDRAM Bank. * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. * @param NewState: new state of the write protection flag. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState) { /* Check the parameter */ assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank)); if (NewState != DISABLE) { FMC_Bank5_6->SDCR[SDRAM_Bank] |= FMC_Write_Protection_Enable; } else { FMC_Bank5_6->SDCR[SDRAM_Bank] &= SDCR_WriteProtection_RESET; } } /** * @} */ /** @defgroup FMC_Group5 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified FMC interrupts. * @param FMC_Bank: specifies the FMC Bank to be used * This parameter can be one of the following values: * @arg FMC_Bank2_NAND: FMC Bank2 NAND * @arg FMC_Bank3_NAND: FMC Bank3 NAND * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM * @param FMC_IT: specifies the FMC interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg FMC_IT_RisingEdge: Rising edge detection interrupt. * @arg FMC_IT_Level: Level edge detection interrupt. * @arg FMC_IT_FallingEdge: Falling edge detection interrupt. * @arg FMC_IT_Refresh: Refresh error detection interrupt. * @param NewState: new state of the specified FMC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState) { assert_param(IS_FMC_IT_BANK(FMC_Bank)); assert_param(IS_FMC_IT(FMC_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected FMC_Bank2 interrupts */ if(FMC_Bank == FMC_Bank2_NAND) { FMC_Bank2->SR2 |= FMC_IT; } /* Enable the selected FMC_Bank3 interrupts */ else if (FMC_Bank == FMC_Bank3_NAND) { FMC_Bank3->SR3 |= FMC_IT; } /* Enable the selected FMC_Bank4 interrupts */ else if (FMC_Bank == FMC_Bank4_PCCARD) { FMC_Bank4->SR4 |= FMC_IT; } /* Enable the selected FMC_Bank5_6 interrupt */ else { /* Enables the interrupt if the refresh error flag is set */ FMC_Bank5_6->SDRTR |= FMC_IT; } } else { /* Disable the selected FMC_Bank2 interrupts */ if(FMC_Bank == FMC_Bank2_NAND) { FMC_Bank2->SR2 &= (uint32_t)~FMC_IT; } /* Disable the selected FMC_Bank3 interrupts */ else if (FMC_Bank == FMC_Bank3_NAND) { FMC_Bank3->SR3 &= (uint32_t)~FMC_IT; } /* Disable the selected FMC_Bank4 interrupts */ else if(FMC_Bank == FMC_Bank4_PCCARD) { FMC_Bank4->SR4 &= (uint32_t)~FMC_IT; } /* Disable the selected FMC_Bank5_6 interrupt */ else { /* Disables the interrupt if the refresh error flag is not set */ FMC_Bank5_6->SDRTR &= (uint32_t)~FMC_IT; } } } /** * @brief Checks whether the specified FMC flag is set or not. * @param FMC_Bank: specifies the FMC Bank to be used * This parameter can be one of the following values: * @arg FMC_Bank2_NAND: FMC Bank2 NAND * @arg FMC_Bank3_NAND: FMC Bank3 NAND * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM * @arg FMC_Bank1_SDRAM | FMC_Bank2_SDRAM: FMC Bank1 or Bank2 SDRAM * @param FMC_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag. * @arg FMC_FLAG_Level: Level detection Flag. * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag. * @arg FMC_FLAG_FEMPT: Fifo empty Flag. * @arg FMC_FLAG_Refresh: Refresh error Flag. * @arg FMC_FLAG_Busy: Busy status Flag. * @retval The new state of FMC_FLAG (SET or RESET). */ FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG) { FlagStatus bitstatus = RESET; uint32_t tmpsr = 0x00000000; /* Check the parameters */ assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank)); assert_param(IS_FMC_GET_FLAG(FMC_FLAG)); if(FMC_Bank == FMC_Bank2_NAND) { tmpsr = FMC_Bank2->SR2; } else if(FMC_Bank == FMC_Bank3_NAND) { tmpsr = FMC_Bank3->SR3; } else if(FMC_Bank == FMC_Bank4_PCCARD) { tmpsr = FMC_Bank4->SR4; } else { tmpsr = FMC_Bank5_6->SDSR; } /* Get the flag status */ if ((tmpsr & FMC_FLAG) != FMC_FLAG ) { bitstatus = RESET; } else { bitstatus = SET; } /* Return the flag status */ return bitstatus; } /** * @brief Clears the FMC's pending flags. * @param FMC_Bank: specifies the FMC Bank to be used * This parameter can be one of the following values: * @arg FMC_Bank2_NAND: FMC Bank2 NAND * @arg FMC_Bank3_NAND: FMC Bank3 NAND * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM * @param FMC_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag. * @arg FMC_FLAG_Level: Level detection Flag. * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag. * @arg FMC_FLAG_Refresh: Refresh error Flag. * @retval None */ void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG) { /* Check the parameters */ assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank)); assert_param(IS_FMC_CLEAR_FLAG(FMC_FLAG)) ; if(FMC_Bank == FMC_Bank2_NAND) { FMC_Bank2->SR2 &= (~FMC_FLAG); } else if(FMC_Bank == FMC_Bank3_NAND) { FMC_Bank3->SR3 &= (~FMC_FLAG); } else if(FMC_Bank == FMC_Bank4_PCCARD) { FMC_Bank4->SR4 &= (~FMC_FLAG); } /* FMC_Bank5_6 SDRAM*/ else { FMC_Bank5_6->SDRTR &= (~FMC_FLAG); } } /** * @brief Checks whether the specified FMC interrupt has occurred or not. * @param FMC_Bank: specifies the FMC Bank to be used * This parameter can be one of the following values: * @arg FMC_Bank2_NAND: FMC Bank2 NAND * @arg FMC_Bank3_NAND: FMC Bank3 NAND * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM * @param FMC_IT: specifies the FMC interrupt source to check. * This parameter can be one of the following values: * @arg FMC_IT_RisingEdge: Rising edge detection interrupt. * @arg FMC_IT_Level: Level edge detection interrupt. * @arg FMC_IT_FallingEdge: Falling edge detection interrupt. * @arg FMC_IT_Refresh: Refresh error detection interrupt. * @retval The new state of FMC_IT (SET or RESET). */ ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT) { ITStatus bitstatus = RESET; uint32_t tmpsr = 0x0; uint32_t tmpsr2 = 0x0; uint32_t itstatus = 0x0; uint32_t itenable = 0x0; /* Check the parameters */ assert_param(IS_FMC_IT_BANK(FMC_Bank)); assert_param(IS_FMC_GET_IT(FMC_IT)); if(FMC_Bank == FMC_Bank2_NAND) { tmpsr = FMC_Bank2->SR2; } else if(FMC_Bank == FMC_Bank3_NAND) { tmpsr = FMC_Bank3->SR3; } else if(FMC_Bank == FMC_Bank4_PCCARD) { tmpsr = FMC_Bank4->SR4; } /* FMC_Bank5_6 SDRAM*/ else { tmpsr = FMC_Bank5_6->SDRTR; tmpsr2 = FMC_Bank5_6->SDSR; } /* get the IT enable bit status*/ itenable = tmpsr & FMC_IT; /* get the corresponding IT Flag status*/ if((FMC_Bank == FMC_Bank1_SDRAM) || (FMC_Bank == FMC_Bank2_SDRAM)) { itstatus = tmpsr2 & FMC_SDSR_RE; } else { itstatus = tmpsr & (FMC_IT >> 3); } if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the FMC's interrupt pending bits. * @param FMC_Bank: specifies the FMC Bank to be used * This parameter can be one of the following values: * @arg FMC_Bank2_NAND: FMC Bank2 NAND * @arg FMC_Bank3_NAND: FMC Bank3 NAND * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM * @param FMC_IT: specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg FMC_IT_RisingEdge: Rising edge detection interrupt. * @arg FMC_IT_Level: Level edge detection interrupt. * @arg FMC_IT_FallingEdge: Falling edge detection interrupt. * @arg FMC_IT_Refresh: Refresh error detection interrupt. * @retval None */ void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT) { /* Check the parameters */ assert_param(IS_FMC_IT_BANK(FMC_Bank)); assert_param(IS_FMC_IT(FMC_IT)); if(FMC_Bank == FMC_Bank2_NAND) { FMC_Bank2->SR2 &= ~(FMC_IT >> 3); } else if(FMC_Bank == FMC_Bank3_NAND) { FMC_Bank3->SR3 &= ~(FMC_IT >> 3); } else if(FMC_Bank == FMC_Bank4_PCCARD) { FMC_Bank4->SR4 &= ~(FMC_IT >> 3); } /* FMC_Bank5_6 SDRAM*/ else { FMC_Bank5_6->SDRTR |= FMC_SDRTR_CRE; } } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c ================================================ /** ****************************************************************************** * @file stm32f4xx_fsmc.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the FSMC peripheral: * + Interface with SRAM, PSRAM, NOR and OneNAND memories * + Interface with NAND memories * + Interface with 16-bit PC Card compatible memories * + Interrupts and flags management * ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_fsmc.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup FSMC * @brief FSMC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* --------------------- FSMC registers bit mask ---------------------------- */ /* FSMC BCRx Mask */ #define BCR_MBKEN_SET ((uint32_t)0x00000001) #define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE) #define BCR_FACCEN_SET ((uint32_t)0x00000040) /* FSMC PCRx Mask */ #define PCR_PBKEN_SET ((uint32_t)0x00000004) #define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB) #define PCR_ECCEN_SET ((uint32_t)0x00000040) #define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF) #define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup FSMC_Private_Functions * @{ */ /** @defgroup FSMC_Group1 NOR/SRAM Controller functions * @brief NOR/SRAM Controller functions * @verbatim =============================================================================== ##### NOR and SRAM Controller functions ##### =============================================================================== [..] The following sequence should be followed to configure the FSMC to interface with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank: (#) Enable the clock for the FSMC and associated GPIOs using the following functions: RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); (#) FSMC pins configuration (++) Connect the involved FSMC pins to AF12 using the following function GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); (++) Configure these FSMC pins in alternate function mode by calling the function GPIO_Init(); (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example: FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; and fill the FSMC_NORSRAMInitStructure variable with the allowed values of the structure member. (#) Initialize the NOR/SRAM Controller by calling the function FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); (#) Then enable the NOR/SRAM Bank, for example: FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. @endverbatim * @{ */ /** * @brief De-initializes the FSMC NOR/SRAM Banks registers to their default * reset values. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 * @retval None */ void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) { /* Check the parameter */ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); /* FSMC_Bank1_NORSRAM1 */ if(FSMC_Bank == FSMC_Bank1_NORSRAM1) { FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; } /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ else { FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; } FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; } /** * @brief Initializes the FSMC NOR/SRAM Banks according to the specified * parameters in the FSMC_NORSRAMInitStruct. * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure * that contains the configuration information for the FSMC NOR/SRAM * specified Banks. * @retval None */ void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) { /* Check the parameters */ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); /* Bank1 NOR/SRAM control register configuration */ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | FSMC_NORSRAMInitStruct->FSMC_MemoryType | FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | FSMC_NORSRAMInitStruct->FSMC_WrapMode | FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | FSMC_NORSRAMInitStruct->FSMC_WriteOperation | FSMC_NORSRAMInitStruct->FSMC_WaitSignal | FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | FSMC_NORSRAMInitStruct->FSMC_WriteBurst; if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) { FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET; } /* Bank1 NOR/SRAM timing register configuration */ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) { assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; } else { FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; } } /** * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure * which will be initialized. * @retval None */ void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) { /* Reset NOR/SRAM Init structure parameters values */ FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; } /** * @brief Enables or disables the specified NOR/SRAM Memory Bank. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. * @retval None */ void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) { assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET; } else { /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET; } } /** * @} */ /** @defgroup FSMC_Group2 NAND Controller functions * @brief NAND Controller functions * @verbatim =============================================================================== ##### NAND Controller functions ##### =============================================================================== [..] The following sequence should be followed to configure the FSMC to interface with 8-bit or 16-bit NAND memory connected to the NAND Bank: (#) Enable the clock for the FSMC and associated GPIOs using the following functions: (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); (#) FSMC pins configuration (++) Connect the involved FSMC pins to AF12 using the following function GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); (++) Configure these FSMC pins in alternate function mode by calling the function GPIO_Init(); (#) Declare a FSMC_NANDInitTypeDef structure, for example: FSMC_NANDInitTypeDef FSMC_NANDInitStructure; and fill the FSMC_NANDInitStructure variable with the allowed values of the structure member. (#) Initialize the NAND Controller by calling the function FSMC_NANDInit(&FSMC_NANDInitStructure); (#) Then enable the NAND Bank, for example: FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE); (#) At this stage you can read/write from/to the memory connected to the NAND Bank. [..] (@) To enable the Error Correction Code (ECC), you have to use the function FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE); [..] (@) and to get the current ECC value you have to use the function ECCval = FSMC_GetECC(FSMC_Bank3_NAND); @endverbatim * @{ */ /** * @brief De-initializes the FSMC NAND Banks registers to their default reset values. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @retval None */ void FSMC_NANDDeInit(uint32_t FSMC_Bank) { /* Check the parameter */ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); if(FSMC_Bank == FSMC_Bank2_NAND) { /* Set the FSMC_Bank2 registers to their reset values */ FSMC_Bank2->PCR2 = 0x00000018; FSMC_Bank2->SR2 = 0x00000040; FSMC_Bank2->PMEM2 = 0xFCFCFCFC; FSMC_Bank2->PATT2 = 0xFCFCFCFC; } /* FSMC_Bank3_NAND */ else { /* Set the FSMC_Bank3 registers to their reset values */ FSMC_Bank3->PCR3 = 0x00000018; FSMC_Bank3->SR3 = 0x00000040; FSMC_Bank3->PMEM3 = 0xFCFCFCFC; FSMC_Bank3->PATT3 = 0xFCFCFCFC; } } /** * @brief Initializes the FSMC NAND Banks according to the specified parameters * in the FSMC_NANDInitStruct. * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that * contains the configuration information for the FSMC NAND specified Banks. * @retval None */ void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) { uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; /* Check the parameters */ assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | PCR_MEMORYTYPE_NAND | FSMC_NANDInitStruct->FSMC_MemoryDataWidth | FSMC_NANDInitStruct->FSMC_ECC | FSMC_NANDInitStruct->FSMC_ECCPageSize | (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) { /* FSMC_Bank2_NAND registers configuration */ FSMC_Bank2->PCR2 = tmppcr; FSMC_Bank2->PMEM2 = tmppmem; FSMC_Bank2->PATT2 = tmppatt; } else { /* FSMC_Bank3_NAND registers configuration */ FSMC_Bank3->PCR3 = tmppcr; FSMC_Bank3->PMEM3 = tmppmem; FSMC_Bank3->PATT3 = tmppatt; } } /** * @brief Fills each FSMC_NANDInitStruct member with its default value. * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which * will be initialized. * @retval None */ void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) { /* Reset NAND Init structure parameters values */ FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; } /** * @brief Enables or disables the specified NAND Memory Bank. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. * @retval None */ void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) { assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->PCR2 |= PCR_PBKEN_SET; } else { FSMC_Bank3->PCR3 |= PCR_PBKEN_SET; } } else { /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET; } else { FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET; } } } /** * @brief Enables or disables the FSMC NAND ECC feature. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @param NewState: new state of the FSMC NAND ECC feature. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) { assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->PCR2 |= PCR_ECCEN_SET; } else { FSMC_Bank3->PCR3 |= PCR_ECCEN_SET; } } else { /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET; } else { FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET; } } } /** * @brief Returns the error correction code register value. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @retval The Error Correction Code (ECC) value. */ uint32_t FSMC_GetECC(uint32_t FSMC_Bank) { uint32_t eccval = 0x00000000; if(FSMC_Bank == FSMC_Bank2_NAND) { /* Get the ECCR2 register value */ eccval = FSMC_Bank2->ECCR2; } else { /* Get the ECCR3 register value */ eccval = FSMC_Bank3->ECCR3; } /* Return the error correction code value */ return(eccval); } /** * @} */ /** @defgroup FSMC_Group3 PCCARD Controller functions * @brief PCCARD Controller functions * @verbatim =============================================================================== ##### PCCARD Controller functions ##### =============================================================================== [..] he following sequence should be followed to configure the FSMC to interface with 16-bit PC Card compatible memory connected to the PCCARD Bank: (#) Enable the clock for the FSMC and associated GPIOs using the following functions: (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); (#) FSMC pins configuration (++) Connect the involved FSMC pins to AF12 using the following function GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); (++) Configure these FSMC pins in alternate function mode by calling the function GPIO_Init(); (#) Declare a FSMC_PCCARDInitTypeDef structure, for example: FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure; and fill the FSMC_PCCARDInitStructure variable with the allowed values of the structure member. (#) Initialize the PCCARD Controller by calling the function FSMC_PCCARDInit(&FSMC_PCCARDInitStructure); (#) Then enable the PCCARD Bank: FSMC_PCCARDCmd(ENABLE); (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank. @endverbatim * @{ */ /** * @brief De-initializes the FSMC PCCARD Bank registers to their default reset values. * @param None * @retval None */ void FSMC_PCCARDDeInit(void) { /* Set the FSMC_Bank4 registers to their reset values */ FSMC_Bank4->PCR4 = 0x00000018; FSMC_Bank4->SR4 = 0x00000000; FSMC_Bank4->PMEM4 = 0xFCFCFCFC; FSMC_Bank4->PATT4 = 0xFCFCFCFC; FSMC_Bank4->PIO4 = 0xFCFCFCFC; } /** * @brief Initializes the FSMC PCCARD Bank according to the specified parameters * in the FSMC_PCCARDInitStruct. * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure * that contains the configuration information for the FSMC PCCARD Bank. * @retval None */ void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) { /* Check the parameters */ assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | FSMC_MemoryDataWidth_16b | (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); } /** * @brief Fills each FSMC_PCCARDInitStruct member with its default value. * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure * which will be initialized. * @retval None */ void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) { /* Reset PCCARD Init structure parameters values */ FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; } /** * @brief Enables or disables the PCCARD Memory Bank. * @param NewState: new state of the PCCARD Memory Bank. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FSMC_PCCARDCmd(FunctionalState NewState) { assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ FSMC_Bank4->PCR4 |= PCR_PBKEN_SET; } else { /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET; } } /** * @} */ /** @defgroup FSMC_Group4 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified FSMC interrupts. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. * @arg FSMC_IT_Level: Level edge detection interrupt. * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. * @param NewState: new state of the specified FSMC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) { assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); assert_param(IS_FSMC_IT(FSMC_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected FSMC_Bank2 interrupts */ if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->SR2 |= FSMC_IT; } /* Enable the selected FSMC_Bank3 interrupts */ else if (FSMC_Bank == FSMC_Bank3_NAND) { FSMC_Bank3->SR3 |= FSMC_IT; } /* Enable the selected FSMC_Bank4 interrupts */ else { FSMC_Bank4->SR4 |= FSMC_IT; } } else { /* Disable the selected FSMC_Bank2 interrupts */ if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; } /* Disable the selected FSMC_Bank3 interrupts */ else if (FSMC_Bank == FSMC_Bank3_NAND) { FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; } /* Disable the selected FSMC_Bank4 interrupts */ else { FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; } } } /** * @brief Checks whether the specified FSMC flag is set or not. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD * @param FSMC_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. * @arg FSMC_FLAG_Level: Level detection Flag. * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. * @retval The new state of FSMC_FLAG (SET or RESET). */ FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) { FlagStatus bitstatus = RESET; uint32_t tmpsr = 0x00000000; /* Check the parameters */ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); if(FSMC_Bank == FSMC_Bank2_NAND) { tmpsr = FSMC_Bank2->SR2; } else if(FSMC_Bank == FSMC_Bank3_NAND) { tmpsr = FSMC_Bank3->SR3; } /* FSMC_Bank4_PCCARD*/ else { tmpsr = FSMC_Bank4->SR4; } /* Get the flag status */ if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) { bitstatus = SET; } else { bitstatus = RESET; } /* Return the flag status */ return bitstatus; } /** * @brief Clears the FSMC's pending flags. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD * @param FSMC_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. * @arg FSMC_FLAG_Level: Level detection Flag. * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. * @retval None */ void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) { /* Check the parameters */ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->SR2 &= ~FSMC_FLAG; } else if(FSMC_Bank == FSMC_Bank3_NAND) { FSMC_Bank3->SR3 &= ~FSMC_FLAG; } /* FSMC_Bank4_PCCARD*/ else { FSMC_Bank4->SR4 &= ~FSMC_FLAG; } } /** * @brief Checks whether the specified FSMC interrupt has occurred or not. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD * @param FSMC_IT: specifies the FSMC interrupt source to check. * This parameter can be one of the following values: * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. * @arg FSMC_IT_Level: Level edge detection interrupt. * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. * @retval The new state of FSMC_IT (SET or RESET). */ ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) { ITStatus bitstatus = RESET; uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; /* Check the parameters */ assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); assert_param(IS_FSMC_GET_IT(FSMC_IT)); if(FSMC_Bank == FSMC_Bank2_NAND) { tmpsr = FSMC_Bank2->SR2; } else if(FSMC_Bank == FSMC_Bank3_NAND) { tmpsr = FSMC_Bank3->SR3; } /* FSMC_Bank4_PCCARD*/ else { tmpsr = FSMC_Bank4->SR4; } itstatus = tmpsr & FSMC_IT; itenable = tmpsr & (FSMC_IT >> 3); if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the FSMC's interrupt pending bits. * @param FSMC_Bank: specifies the FSMC Bank to be used * This parameter can be one of the following values: * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD * @param FSMC_IT: specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. * @arg FSMC_IT_Level: Level edge detection interrupt. * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. * @retval None */ void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) { /* Check the parameters */ assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); assert_param(IS_FSMC_IT(FSMC_IT)); if(FSMC_Bank == FSMC_Bank2_NAND) { FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); } else if(FSMC_Bank == FSMC_Bank3_NAND) { FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); } /* FSMC_Bank4_PCCARD*/ else { FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); } } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c ================================================ /** ****************************************************************************** * @file stm32f4xx_gpio.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the GPIO peripheral: * + Initialization and Configuration * + GPIO Read and Write * + GPIO Alternate functions configuration * @verbatim =============================================================================== ##### How to use this driver ##### =============================================================================== [..] (#) Enable the GPIO AHB clock using the following function RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); (#) Configure the GPIO pin(s) using GPIO_Init() Four possible configuration are available for each pin: (++) Input: Floating, Pull-up, Pull-down. (++) Output: Push-Pull (Pull-up, Pull-down or no Pull) Open Drain (Pull-up, Pull-down or no Pull). In output mode, the speed is configurable: 2 MHz, 25 MHz, 50 MHz or 100 MHz. (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) Open Drain (Pull-up, Pull-down or no Pull). (++) Analog: required mode when a pin is to be used as ADC channel or DAC output. (#) Peripherals alternate function: (++) For ADC and DAC, configure the desired pin in analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN; (+++) For other peripherals (TIM, USART...): (+++) Connect the pin to the desired peripherals' Alternate Function (AF) using GPIO_PinAFConfig() function (+++) Configure the desired pin in alternate function mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF (+++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd, GPIO_OType and GPIO_Speed members (+++) Call GPIO_Init() function (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() (#) To set/reset the level of a pin configured in output mode use GPIO_SetBits()/GPIO_ResetBits() (#) During and just after reset, the alternate functions are not active and the GPIO pins are configured in input floating mode (except JTAG pins). (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has priority over the GPIO function. (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general purpose PH0 and PH1, respectively, when the HSE oscillator is off. The HSE has priority over the GPIO function. @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_gpio.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup GPIO * @brief GPIO driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup GPIO_Private_Functions * @{ */ /** @defgroup GPIO_Group1 Initialization and Configuration * @brief Initialization and Configuration * @verbatim =============================================================================== ##### Initialization and Configuration ##### =============================================================================== @endverbatim * @{ */ /** * @brief De-initializes the GPIOx peripheral registers to their default reset values. * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins). * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @retval None */ void GPIO_DeInit(GPIO_TypeDef* GPIOx) { /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); if (GPIOx == GPIOA) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE); } else if (GPIOx == GPIOB) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE); } else if (GPIOx == GPIOC) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE); } else if (GPIOx == GPIOD) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE); } else if (GPIOx == GPIOE) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE); } else if (GPIOx == GPIOF) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE); } else if (GPIOx == GPIOG) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE); } else if (GPIOx == GPIOH) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE); } else if (GPIOx == GPIOI) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE); } else if (GPIOx == GPIOJ) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, DISABLE); } else { if (GPIOx == GPIOK) { RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, ENABLE); RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, DISABLE); } } } /** * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) { uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); /* ------------------------- Configure the port pins ---------------- */ /*-- GPIO Mode Configuration --*/ for (pinpos = 0x00; pinpos < 0x10; pinpos++) { pos = ((uint32_t)0x01) << pinpos; /* Get the port pins position */ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; if (currentpin == pos) { GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) { /* Check Speed mode parameters */ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); /* Speed mode configuration */ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); /* Check Output mode parameters */ assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); /* Output mode configuration*/ GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ; GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); } /* Pull-up Pull down resistor configuration*/ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); } } } /** * @brief Fills each GPIO_InitStruct member with its default value. * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized. * @retval None */ void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) { /* Reset GPIO init structure parameters values */ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; } /** * @brief Locks GPIO Pins configuration registers. * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param GPIO_Pin: specifies the port bit to be locked. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { __IO uint32_t tmp = 0x00010000; /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); tmp |= GPIO_Pin; /* Set LCKK bit */ GPIOx->LCKR = tmp; /* Reset LCKK bit */ GPIOx->LCKR = GPIO_Pin; /* Set LCKK bit */ GPIOx->LCKR = tmp; /* Read LCKK bit*/ tmp = GPIOx->LCKR; /* Read LCKK bit*/ tmp = GPIOx->LCKR; } /** * @} */ /** @defgroup GPIO_Group2 GPIO Read and Write * @brief GPIO Read and Write * @verbatim =============================================================================== ##### GPIO Read and Write ##### =============================================================================== @endverbatim * @{ */ /** * @brief Reads the specified input port pin. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_Pin_x where x can be (0..15). * @retval The input port pin value. */ uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { uint8_t bitstatus = 0x00; /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) { bitstatus = (uint8_t)Bit_SET; } else { bitstatus = (uint8_t)Bit_RESET; } return bitstatus; } /** * @brief Reads the specified GPIO input data port. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @retval GPIO input data port value. */ uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) { /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); return ((uint16_t)GPIOx->IDR); } /** * @brief Reads the specified output data port bit. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param GPIO_Pin: specifies the port bit to read. * This parameter can be GPIO_Pin_x where x can be (0..15). * @retval The output port pin value. */ uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { uint8_t bitstatus = 0x00; /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); if (((GPIOx->ODR) & GPIO_Pin) != (uint32_t)Bit_RESET) { bitstatus = (uint8_t)Bit_SET; } else { bitstatus = (uint8_t)Bit_RESET; } return bitstatus; } /** * @brief Reads the specified GPIO output data port. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @retval GPIO output data port value. */ uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) { /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); return ((uint16_t)GPIOx->ODR); } /** * @brief Sets the selected data port bits. * @note This functions uses GPIOx_BSRR register to allow atomic read/modify * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param GPIO_Pin: specifies the port bits to be written. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); GPIOx->BSRRL = GPIO_Pin; } /** * @brief Clears the selected data port bits. * @note This functions uses GPIOx_BSRR register to allow atomic read/modify * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param GPIO_Pin: specifies the port bits to be written. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval None */ void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Pin)); GPIOx->BSRRH = GPIO_Pin; } /** * @brief Sets or clears the selected data port bit. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param GPIO_Pin: specifies the port bit to be written. * This parameter can be one of GPIO_Pin_x where x can be (0..15). * @param BitVal: specifies the value to be written to the selected bit. * This parameter can be one of the BitAction enum values: * @arg Bit_RESET: to clear the port pin * @arg Bit_SET: to set the port pin * @retval None */ void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) { /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_BIT_ACTION(BitVal)); if (BitVal != Bit_RESET) { GPIOx->BSRRL = GPIO_Pin; } else { GPIOx->BSRRH = GPIO_Pin ; } } /** * @brief Writes data to the specified GPIO data port. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param PortVal: specifies the value to be written to the port output data register. * @retval None */ void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) { /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); GPIOx->ODR = PortVal; } /** * @brief Toggles the specified GPIO pins.. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); GPIOx->ODR ^= GPIO_Pin; } /** * @} */ /** @defgroup GPIO_Group3 GPIO Alternate functions configuration function * @brief GPIO Alternate functions configuration function * @verbatim =============================================================================== ##### GPIO Alternate functions configuration function ##### =============================================================================== @endverbatim * @{ */ /** * @brief Changes the mapping of the specified pin. * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. * @param GPIO_PinSource: specifies the pin for the Alternate function. * This parameter can be GPIO_PinSourcex where x can be (0..15). * @param GPIO_AFSelection: selects the pin to used as Alternate function. * This parameter can be one of the following values: * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset) * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1 * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1 * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2 * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2 * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2 * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3 * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3 * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3 * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3 * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4 * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4 * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4 * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5 * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5 * @arg GPIO_AF_SPI4: Connect SPI4 pins to AF5 * @arg GPIO_AF_SPI5: Connect SPI5 pins to AF5 * @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5 * @arg GPIO_AF_SAI1: Connect SAI1 pins to AF6 for STM32F42xxx/43xxx devices. * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6 * @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7 * @arg GPIO_AF_USART1: Connect USART1 pins to AF7 * @arg GPIO_AF_USART2: Connect USART2 pins to AF7 * @arg GPIO_AF_USART3: Connect USART3 pins to AF7 * @arg GPIO_AF_UART4: Connect UART4 pins to AF8 * @arg GPIO_AF_UART5: Connect UART5 pins to AF8 * @arg GPIO_AF_USART6: Connect USART6 pins to AF8 * @arg GPIO_AF_UART7: Connect UART7 pins to AF8 * @arg GPIO_AF_UART8: Connect UART8 pins to AF8 * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9 * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9 * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9 * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9 * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9 * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10 * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10 * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11 * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 * @arg GPIO_AF_FMC: Connect FMC pins to AF12 for STM32F42xxx/43xxx devices. * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12 * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12 * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13 * @arg GPIO_AF_LTDC: Connect LTDC pins to AF14 for STM32F429xx/439xx devices. * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15 * @retval None */ void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) { uint32_t temp = 0x00; uint32_t temp_2 = 0x00; /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); assert_param(IS_GPIO_AF(GPIO_AF)); temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c ================================================ /** ****************************************************************************** * @file stm32f4xx_hash.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the HASH / HMAC Processor (HASH) peripheral: * - Initialization and Configuration functions * - Message Digest generation functions * - context swapping functions * - DMA interface function * - Interrupts and flags management * @verbatim =================================================================== ##### How to use this driver ##### =================================================================== *** HASH operation : *** ======================== [..] (#) Enable the HASH controller clock using RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function. (#) Initialise the HASH using HASH_Init() function. (#) Reset the HASH processor core, so that the HASH will be ready to compute he message digest of a new message by using HASH_Reset() function. (#) Enable the HASH controller using the HASH_Cmd() function. (#) if using DMA for Data input transfer, Activate the DMA Request using HASH_DMACmd() function (#) if DMA is not used for data transfer, use HASH_DataIn() function to enter data to IN FIFO. (#) Configure the Number of valid bits in last word of the message using HASH_SetLastWordValidBitsNbr() function. (#) if the message length is not an exact multiple of 512 bits, then the function HASH_StartDigest() must be called to launch the computation of the final digest. (#) Once computed, the digest can be read using HASH_GetDigest() function. (#) To control HASH events you can use one of the following wo methods: (++) Check on HASH flags using the HASH_GetFlagStatus() function. (++) Use HASH interrupts through the function HASH_ITConfig() at initialization phase and HASH_GetITStatus() function into interrupt routines in hashing phase. After checking on a flag you should clear it using HASH_ClearFlag() function. And after checking on an interrupt event you should clear it using HASH_ClearITPendingBit() function. (#) Save and restore hash processor context using HASH_SaveContext() and HASH_RestoreContext() functions. *** HMAC operation : *** ======================== [..] The HMAC algorithm is used for message authentication, by irreversibly binding the message being processed to a key chosen by the user. For HMAC specifications, refer to "HMAC: keyed-hashing for message authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997" [..] Basically, the HMAC algorithm consists of two nested hash operations: HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)] where: (+) "pad" is a sequence of zeroes needed to extend the key to the length of the underlying hash function data block (that is 512 bits for both the SHA-1 and MD5 hash algorithms) (+) "|" represents the concatenation operator [..]To compute the HMAC, four different phases are required: (#) Initialise the HASH using HASH_Init() function to do HMAC operation. (#) The key (to be used for the inner hash function) is then given to the core. This operation follows the same mechanism as the one used to send the message in the hash operation (that is, by HASH_DataIn() function and, finally, HASH_StartDigest() function. (#) Once the last word has been entered and computation has started, the hash processor elaborates the key. It is then ready to accept the message text using the same mechanism as the one used to send the message in the hash operation. (#) After the first hash round, the hash processor returns "ready" to indicate that it is ready to receive the key to be used for the outer hash function (normally, this key is the same as the one used for the inner hash function). When the last word of the key is entered and computation starts, the HMAC result is made available using HASH_GetDigest() function. @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hash.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup HASH * @brief HASH driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup HASH_Private_Functions * @{ */ /** @defgroup HASH_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This section provides functions allowing to (+) Initialize the HASH peripheral (+) Configure the HASH Processor (+) MD5/SHA1, (+) HASH/HMAC, (+) datatype (+) HMAC Key (if mode = HMAC) (+) Reset the HASH Processor @endverbatim * @{ */ /** * @brief De-initializes the HASH peripheral registers to their default reset values * @param None * @retval None */ void HASH_DeInit(void) { /* Enable HASH reset state */ RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE); /* Release HASH from reset state */ RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE); } /** * @brief Initializes the HASH peripheral according to the specified parameters * in the HASH_InitStruct structure. * @note the hash processor is reset when calling this function so that the * HASH will be ready to compute the message digest of a new message. * There is no need to call HASH_Reset() function. * @param HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains * the configuration information for the HASH peripheral. * @note The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only * if the algorithm mode is HMAC. * @retval None */ void HASH_Init(HASH_InitTypeDef* HASH_InitStruct) { /* Check the parameters */ assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection)); assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType)); assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode)); /* Configure the Algorithm used, algorithm mode and the datatype */ HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE); HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \ HASH_InitStruct->HASH_DataType | \ HASH_InitStruct->HASH_AlgoMode); /* if algorithm mode is HMAC, set the Key */ if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC) { assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType)); HASH->CR &= ~HASH_CR_LKEY; HASH->CR |= HASH_InitStruct->HASH_HMACKeyType; } /* Reset the HASH processor core, so that the HASH will be ready to compute the message digest of a new message */ HASH->CR |= HASH_CR_INIT; } /** * @brief Fills each HASH_InitStruct member with its default value. * @param HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will * be initialized. * @note The default values set are : Processor mode is HASH, Algorithm selected is SHA1, * Data type selected is 32b and HMAC Key Type is short key. * @retval None */ void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct) { /* Initialize the HASH_AlgoSelection member */ HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1; /* Initialize the HASH_AlgoMode member */ HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH; /* Initialize the HASH_DataType member */ HASH_InitStruct->HASH_DataType = HASH_DataType_32b; /* Initialize the HASH_HMACKeyType member */ HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; } /** * @brief Resets the HASH processor core, so that the HASH will be ready * to compute the message digest of a new message. * @note Calling this function will clear the HASH_SR_DCIS (Digest calculation * completion interrupt status) bit corresponding to HASH_IT_DCI * interrupt and HASH_FLAG_DCIS flag. * @param None * @retval None */ void HASH_Reset(void) { /* Reset the HASH processor core */ HASH->CR |= HASH_CR_INIT; } /** * @} */ /** @defgroup HASH_Group2 Message Digest generation functions * @brief Message Digest generation functions * @verbatim =============================================================================== ##### Message Digest generation functions ##### =============================================================================== [..] This section provides functions allowing the generation of message digest: (+) Push data in the IN FIFO : using HASH_DataIn() (+) Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr() (+) set the last word valid bits number using HASH_SetLastWordValidBitsNbr() (+) start digest calculation : using HASH_StartDigest() (+) Get the Digest message : using HASH_GetDigest() @endverbatim * @{ */ /** * @brief Configure the Number of valid bits in last word of the message * @param ValidNumber: Number of valid bits in last word of the message. * This parameter must be a number between 0 and 0x1F. * - 0x00: All 32 bits of the last data written are valid * - 0x01: Only bit [0] of the last data written is valid * - 0x02: Only bits[1:0] of the last data written are valid * - 0x03: Only bits[2:0] of the last data written are valid * - ... * - 0x1F: Only bits[30:0] of the last data written are valid * @note The Number of valid bits must be set before to start the message * digest competition (in Hash and HMAC) and key treatment(in HMAC). * @retval None */ void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber) { /* Check the parameters */ assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber)); /* Configure the Number of valid bits in last word of the message */ HASH->STR &= ~(HASH_STR_NBW); HASH->STR |= ValidNumber; } /** * @brief Writes data in the Data Input FIFO * @param Data: new data of the message to be processed. * @retval None */ void HASH_DataIn(uint32_t Data) { /* Write in the DIN register a new data */ HASH->DIN = Data; } /** * @brief Returns the number of words already pushed into the IN FIFO. * @param None * @retval The value of words already pushed into the IN FIFO. */ uint8_t HASH_GetInFIFOWordsNbr(void) { /* Return the value of NBW bits */ return ((HASH->CR & HASH_CR_NBW) >> 8); } /** * @brief Provides the message digest result. * @note In MD5 mode, Data[7] to Data[4] filed of HASH_MsgDigest structure is not used * and is read as zero. * In SHA-1 mode, Data[7] to Data[5] filed of HASH_MsgDigest structure is not used * and is read as zero. * In SHA-224 mode, Data[7] filed of HASH_MsgDigest structure is not used * and is read as zero. * @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will * hold the message digest result * @retval None */ void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest) { /* Get the data field */ HASH_MessageDigest->Data[0] = HASH->HR[0]; HASH_MessageDigest->Data[1] = HASH->HR[1]; HASH_MessageDigest->Data[2] = HASH->HR[2]; HASH_MessageDigest->Data[3] = HASH->HR[3]; HASH_MessageDigest->Data[4] = HASH->HR[4]; HASH_MessageDigest->Data[5] = HASH_DIGEST->HR[5]; HASH_MessageDigest->Data[6] = HASH_DIGEST->HR[6]; HASH_MessageDigest->Data[7] = HASH_DIGEST->HR[7]; } /** * @brief Starts the message padding and calculation of the final message * @param None * @retval None */ void HASH_StartDigest(void) { /* Start the Digest calculation */ HASH->STR |= HASH_STR_DCAL; } /** * @} */ /** @defgroup HASH_Group3 Context swapping functions * @brief Context swapping functions * @verbatim =============================================================================== ##### Context swapping functions ##### =============================================================================== [..] This section provides functions allowing to save and store HASH Context [..] It is possible to interrupt a HASH/HMAC process to perform another processing with a higher priority, and to complete the interrupted process later on, when the higher priority task is complete. To do so, the context of the interrupted task must be saved from the HASH registers to memory, and then be restored from memory to the HASH registers. (#) To save the current context, use HASH_SaveContext() function (#) To restore the saved context, use HASH_RestoreContext() function @endverbatim * @{ */ /** * @brief Save the Hash peripheral Context. * @note The context can be saved only when no block is currently being * processed. So user must wait for DINIS = 1 (the last block has been * processed and the input FIFO is empty) or NBW != 0 (the FIFO is not * full and no processing is ongoing). * @param HASH_ContextSave: pointer to a HASH_Context structure that contains * the repository for current context. * @retval None */ void HASH_SaveContext(HASH_Context* HASH_ContextSave) { uint8_t i = 0; /* save context registers */ HASH_ContextSave->HASH_IMR = HASH->IMR; HASH_ContextSave->HASH_STR = HASH->STR; HASH_ContextSave->HASH_CR = HASH->CR; for(i=0; i<=53;i++) { HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i]; } } /** * @brief Restore the Hash peripheral Context. * @note After calling this function, user can restart the processing from the * point where it has been interrupted. * @param HASH_ContextRestore: pointer to a HASH_Context structure that contains * the repository for saved context. * @retval None */ void HASH_RestoreContext(HASH_Context* HASH_ContextRestore) { uint8_t i = 0; /* restore context registers */ HASH->IMR = HASH_ContextRestore->HASH_IMR; HASH->STR = HASH_ContextRestore->HASH_STR; HASH->CR = HASH_ContextRestore->HASH_CR; /* Initialize the hash processor */ HASH->CR |= HASH_CR_INIT; /* continue restoring context registers */ for(i=0; i<=53;i++) { HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i]; } } /** * @} */ /** @defgroup HASH_Group4 HASH's DMA interface Configuration function * @brief HASH's DMA interface Configuration function * @verbatim =============================================================================== ##### HASH's DMA interface Configuration function ##### =============================================================================== [..] This section provides functions allowing to configure the DMA interface for HASH/ HMAC data input transfer. [..] When the DMA mode is enabled (using the HASH_DMACmd() function), data can be sent to the IN FIFO using the DMA peripheral. @endverbatim * @{ */ /** * @brief Enables or disables auto-start message padding and * calculation of the final message digest at the end of DMA transfer. * @param NewState: new state of the selected HASH DMA transfer request. * This parameter can be: ENABLE or DISABLE. * @retval None */ void HASH_AutoStartDigest(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the auto start of the final message digest at the end of DMA transfer */ HASH->CR &= ~HASH_CR_MDMAT; } else { /* Disable the auto start of the final message digest at the end of DMA transfer */ HASH->CR |= HASH_CR_MDMAT; } } /** * @brief Enables or disables the HASH DMA interface. * @note The DMA is disabled by hardware after the end of transfer. * @param NewState: new state of the selected HASH DMA transfer request. * This parameter can be: ENABLE or DISABLE. * @retval None */ void HASH_DMACmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the HASH DMA request */ HASH->CR |= HASH_CR_DMAE; } else { /* Disable the HASH DMA request */ HASH->CR &= ~HASH_CR_DMAE; } } /** * @} */ /** @defgroup HASH_Group5 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== [..] This section provides functions allowing to configure the HASH Interrupts and to get the status and clear flags and Interrupts pending bits. [..] The HASH provides 2 Interrupts sources and 5 Flags: *** Flags : *** =============== [..] (#) HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO which means that a new block (512 bit) can be entered into the input buffer. (#) HASH_FLAG_DCIS : set when Digest calculation is complete (#) HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or a transfer is ongoing. This Flag is cleared only by hardware. (#) HASH_FLAG_BUSY : set when The hash core is processing a block of data This Flag is cleared only by hardware. (#) HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that the Data IN FIFO contains at least one word of data. This Flag is cleared only by hardware. *** Interrupts : *** ==================== [..] (#) HASH_IT_DINI : if enabled, this interrupt source is pending when 16 locations are free in the Data IN FIFO which means that a new block (512 bit) can be entered into the input buffer. This interrupt source is cleared using HASH_ClearITPendingBit(HASH_IT_DINI) function. (#) HASH_IT_DCI : if enabled, this interrupt source is pending when Digest calculation is complete. This interrupt source is cleared using HASH_ClearITPendingBit(HASH_IT_DCI) function. *** Managing the HASH controller events : *** ============================================= [..] The user should identify which mode will be used in his application to manage the HASH controller events: Polling mode or Interrupt mode. (#) In the Polling Mode it is advised to use the following functions: (++) HASH_GetFlagStatus() : to check if flags events occur. (++) HASH_ClearFlag() : to clear the flags events. (#) In the Interrupt Mode it is advised to use the following functions: (++) HASH_ITConfig() : to enable or disable the interrupt source. (++) HASH_GetITStatus() : to check if Interrupt occurs. (++) HASH_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag). @endverbatim * @{ */ /** * @brief Enables or disables the specified HASH interrupts. * @param HASH_IT: specifies the HASH interrupt source to be enabled or disabled. * This parameter can be any combination of the following values: * @arg HASH_IT_DINI: Data Input interrupt * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt * @param NewState: new state of the specified HASH interrupt. * This parameter can be: ENABLE or DISABLE. * @retval None */ void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_HASH_IT(HASH_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected HASH interrupt */ HASH->IMR |= HASH_IT; } else { /* Disable the selected HASH interrupt */ HASH->IMR &= (uint32_t)(~HASH_IT); } } /** * @brief Checks whether the specified HASH flag is set or not. * @param HASH_FLAG: specifies the HASH flag to check. * This parameter can be one of the following values: * @arg HASH_FLAG_DINIS: Data input interrupt status flag * @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag * @arg HASH_FLAG_BUSY: Busy flag * @arg HASH_FLAG_DMAS: DMAS Status flag * @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag * @retval The new state of HASH_FLAG (SET or RESET) */ FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG) { FlagStatus bitstatus = RESET; uint32_t tempreg = 0; /* Check the parameters */ assert_param(IS_HASH_GET_FLAG(HASH_FLAG)); /* check if the FLAG is in CR register */ if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint32_t)RESET ) { tempreg = HASH->CR; } else /* The FLAG is in SR register */ { tempreg = HASH->SR; } /* Check the status of the specified HASH flag */ if ((tempreg & HASH_FLAG) != (uint32_t)RESET) { /* HASH is set */ bitstatus = SET; } else { /* HASH_FLAG is reset */ bitstatus = RESET; } /* Return the HASH_FLAG status */ return bitstatus; } /** * @brief Clears the HASH flags. * @param HASH_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg HASH_FLAG_DINIS: Data Input Flag * @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag * @retval None */ void HASH_ClearFlag(uint32_t HASH_FLAG) { /* Check the parameters */ assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG)); /* Clear the selected HASH flags */ HASH->SR = ~(uint32_t)HASH_FLAG; } /** * @brief Checks whether the specified HASH interrupt has occurred or not. * @param HASH_IT: specifies the HASH interrupt source to check. * This parameter can be one of the following values: * @arg HASH_IT_DINI: Data Input interrupt * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt * @retval The new state of HASH_IT (SET or RESET). */ ITStatus HASH_GetITStatus(uint32_t HASH_IT) { ITStatus bitstatus = RESET; uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_HASH_GET_IT(HASH_IT)); /* Check the status of the specified HASH interrupt */ tmpreg = HASH->SR; if (((HASH->IMR & tmpreg) & HASH_IT) != RESET) { /* HASH_IT is set */ bitstatus = SET; } else { /* HASH_IT is reset */ bitstatus = RESET; } /* Return the HASH_IT status */ return bitstatus; } /** * @brief Clears the HASH interrupt pending bit(s). * @param HASH_IT: specifies the HASH interrupt pending bit(s) to clear. * This parameter can be any combination of the following values: * @arg HASH_IT_DINI: Data Input interrupt * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt * @retval None */ void HASH_ClearITPendingBit(uint32_t HASH_IT) { /* Check the parameters */ assert_param(IS_HASH_IT(HASH_IT)); /* Clear the selected HASH interrupt pending bit */ HASH->SR = (uint32_t)(~HASH_IT); } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c ================================================ /** ****************************************************************************** * @file stm32f4xx_hash_md5.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides high level functions to compute the HASH MD5 and * HMAC MD5 Digest of an input message. * It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH * peripheral. * @verbatim =================================================================== ##### How to use this driver ##### =================================================================== [..] (#) Enable The HASH controller clock using RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function. (#) Calculate the HASH MD5 Digest using HASH_MD5() function. (#) Calculate the HMAC MD5 Digest using HMAC_MD5() function. @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hash.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup HASH * @brief HASH driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define MD5BUSY_TIMEOUT ((uint32_t) 0x00010000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup HASH_Private_Functions * @{ */ /** @defgroup HASH_Group7 High Level MD5 functions * @brief High Level MD5 Hash and HMAC functions * @verbatim =============================================================================== ##### High Level MD5 Hash and HMAC functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Compute the HASH MD5 digest. * @param Input: pointer to the Input buffer to be treated. * @param Ilen: length of the Input buffer. * @param Output: the returned digest * @retval An ErrorStatus enumeration value: * - SUCCESS: digest computation done * - ERROR: digest computation failed */ ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]) { HASH_InitTypeDef MD5_HASH_InitStructure; HASH_MsgDigest MD5_MessageDigest; __IO uint16_t nbvalidbitsdata = 0; uint32_t i = 0; __IO uint32_t counter = 0; uint32_t busystatus = 0; ErrorStatus status = SUCCESS; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; /* Number of valid bits in last word of the Input data */ nbvalidbitsdata = 8 * (Ilen % 4); /* HASH peripheral initialization */ HASH_DeInit(); /* HASH Configuration */ MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5; MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; HASH_Init(&MD5_HASH_InitStructure); /* Configure the number of valid bits in last word of the data */ HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); /* Write the Input block in the IN FIFO */ for(i=0; i 64) { /* HMAC long Key */ MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; } else { /* HMAC short Key */ MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; } HASH_Init(&MD5_HASH_InitStructure); /* Configure the number of valid bits in last word of the Key */ HASH_SetLastWordValidBitsNbr(nbvalidbitskey); /* Write the Key */ for(i=0; i
© COPYRIGHT 2013 STMicroelectronics
* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hash.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup HASH * @brief HASH driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define SHA1BUSY_TIMEOUT ((uint32_t) 0x00010000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup HASH_Private_Functions * @{ */ /** @defgroup HASH_Group6 High Level SHA1 functions * @brief High Level SHA1 Hash and HMAC functions * @verbatim =============================================================================== ##### High Level SHA1 Hash and HMAC functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Compute the HASH SHA1 digest. * @param Input: pointer to the Input buffer to be treated. * @param Ilen: length of the Input buffer. * @param Output: the returned digest * @retval An ErrorStatus enumeration value: * - SUCCESS: digest computation done * - ERROR: digest computation failed */ ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]) { HASH_InitTypeDef SHA1_HASH_InitStructure; HASH_MsgDigest SHA1_MessageDigest; __IO uint16_t nbvalidbitsdata = 0; uint32_t i = 0; __IO uint32_t counter = 0; uint32_t busystatus = 0; ErrorStatus status = SUCCESS; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; /* Number of valid bits in last word of the Input data */ nbvalidbitsdata = 8 * (Ilen % 4); /* HASH peripheral initialization */ HASH_DeInit(); /* HASH Configuration */ SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1; SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; HASH_Init(&SHA1_HASH_InitStructure); /* Configure the number of valid bits in last word of the data */ HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); /* Write the Input block in the IN FIFO */ for(i=0; i 64) { /* HMAC long Key */ SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; } else { /* HMAC short Key */ SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; } HASH_Init(&SHA1_HASH_InitStructure); /* Configure the number of valid bits in last word of the Key */ HASH_SetLastWordValidBitsNbr(nbvalidbitskey); /* Write the Key */ for(i=0; iGPIO_Mode = GPIO_Mode_AF (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd, GPIO_OType and GPIO_Speed members (++) Call GPIO_Init() function Recommended configuration is Push-Pull, Pull-up, Open-Drain. Add an external pull up if necessary (typically 4.7 KOhm). (#) Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged Address using the I2C_Init() function. (#) Optionally you can enable/configure the following parameters without re-initialization (i.e there is no need to call again I2C_Init() function): (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function (++) Enable the dual addressing mode using I2C_DualAddressCmd() function (++) Enable the general call using the I2C_GeneralCallCmd() function (++) Enable the clock stretching using I2C_StretchClockCmd() function (++) Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig() function. (++) Configure the NACK position for Master Receiver mode in case of 2 bytes reception using the function I2C_NACKPositionConfig(). (++) Enable the PEC Calculation using I2C_CalculatePEC() function (++) For SMBus Mode: (+++) Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function (+++) Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function (#) Enable the NVIC and the corresponding interrupt using the function I2C_ITConfig() if you need to use interrupt mode. (#) When using the DMA mode (++) Configure the DMA using DMA_Init() function (++) Active the needed channel Request using I2C_DMACmd() or I2C_DMALastTransferCmd() function. -@@- When using DMA mode, I2C interrupts may be used at the same time to control the communication flow (Start/Stop/Ack... events and errors). (#) Enable the I2C using the I2C_Cmd() function. (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the transfers. @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_i2c.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup I2C * @brief I2C driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ #define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*I2C_ClockSpeed)); assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); /*---------------------------- I2Cx CR2 Configuration ------------------------*/ /* Get the I2Cx CR2 value */ tmpreg = I2Cx->CR2; /* Clear frequency FREQ[5:0] bits */ tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ); /* Get pclk1 frequency value */ RCC_GetClocksFreq(&rcc_clocks); pclk1 = rcc_clocks.PCLK1_Frequency; /* Set frequency bits depending on pclk1 value */ freqrange = (uint16_t)(pclk1 / 1000000); tmpreg |= freqrange; /* Write to I2Cx CR2 */ I2Cx->CR2 = tmpreg; /*---------------------------- I2Cx CCR Configuration ------------------------*/ /* Disable the selected I2C peripheral to configure TRISE */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); /* Reset tmpreg value */ /* Clear F/S, DUTY and CCR[11:0] bits */ tmpreg = 0; /* Configure speed in standard mode */ if (I2C_InitStruct->I2C_ClockSpeed <= 100000) { /* Standard mode speed calculate */ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); /* Test if CCR value is under 0x4*/ if (result < 0x04) { /* Set minimum allowed value */ result = 0x04; } /* Set speed value for standard mode */ tmpreg |= result; /* Set Maximum Rise Time for standard mode */ I2Cx->TRISE = freqrange + 1; } /* Configure speed in fast mode */ /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral input clock) must be a multiple of 10 MHz */ else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ { if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) { /* Fast mode speed calculate: Tlow/Thigh = 2 */ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); } else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ { /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); /* Set DUTY bit */ result |= I2C_DutyCycle_16_9; } /* Test if CCR value is under 0x1*/ if ((result & I2C_CCR_CCR) == 0) { /* Set minimum allowed value */ result |= (uint16_t)0x0001; } /* Set speed value and set F/S bit for fast mode */ tmpreg |= (uint16_t)(result | I2C_CCR_FS); /* Set Maximum Rise Time for fast mode */ I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); } /* Write to I2Cx CCR */ I2Cx->CCR = tmpreg; /* Enable the selected I2C peripheral */ I2Cx->CR1 |= I2C_CR1_PE; /*---------------------------- I2Cx CR1 Configuration ------------------------*/ /* Get the I2Cx CR1 value */ tmpreg = I2Cx->CR1; /* Clear ACK, SMBTYPE and SMBUS bits */ tmpreg &= CR1_CLEAR_MASK; /* Configure I2Cx: mode and acknowledgement */ /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ /* Set ACK bit according to I2C_Ack value */ tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); /* Write to I2Cx CR1 */ I2Cx->CR1 = tmpreg; /*---------------------------- I2Cx OAR1 Configuration -----------------------*/ /* Set I2Cx Own Address1 and acknowledged address */ I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); } /** * @brief Fills each I2C_InitStruct member with its default value. * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. * @retval None */ void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) { /*---------------- Reset I2C init structure parameters values ----------------*/ /* initialize the I2C_ClockSpeed member */ I2C_InitStruct->I2C_ClockSpeed = 5000; /* Initialize the I2C_Mode member */ I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; /* Initialize the I2C_DutyCycle member */ I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; /* Initialize the I2C_OwnAddress1 member */ I2C_InitStruct->I2C_OwnAddress1 = 0; /* Initialize the I2C_Ack member */ I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; /* Initialize the I2C_AcknowledgedAddress member */ I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; } /** * @brief Enables or disables the specified I2C peripheral. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2Cx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected I2C peripheral */ I2Cx->CR1 |= I2C_CR1_PE; } else { /* Disable the selected I2C peripheral */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); } } /** * @brief Enables or disables the Analog filter of I2C peripheral. * * @note This function can be used only for STM32F42xxx/STM3243xxx and STM32F401xx devices. * * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the Analog filter. * This parameter can be: ENABLE or DISABLE. * @note This function should be called before initializing and enabling the I2C Peripheral. * @retval None */ void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the analog filter */ I2Cx->FLTR &= (uint16_t)~((uint16_t)I2C_FLTR_ANOFF); } else { /* Disable the analog filter */ I2Cx->FLTR |= I2C_FLTR_ANOFF; } } /** * @brief Configures the Digital noise filter of I2C peripheral. * * @note This function can be used only for STM32F42xxx/STM3243xxx and STM32F401xx devices. * * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_DigitalFilter: Coefficient of digital noise filter. * This parameter can be a number between 0x00 and 0x0F. * @note This function should be called before initializing and enabling the I2C Peripheral. * @retval None */ void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter) { uint16_t tmpreg = 0; /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_DIGITAL_FILTER(I2C_DigitalFilter)); /* Get the old register value */ tmpreg = I2Cx->FLTR; /* Reset I2Cx DNF bit [3:0] */ tmpreg &= (uint16_t)~((uint16_t)I2C_FLTR_DNF); /* Set I2Cx DNF coefficient */ tmpreg |= (uint16_t)((uint16_t)I2C_DigitalFilter & I2C_FLTR_DNF); /* Store the new register value */ I2Cx->FLTR = tmpreg; } /** * @brief Generates I2Cx communication START condition. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2C START condition generation. * This parameter can be: ENABLE or DISABLE. * @retval None. */ void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Generate a START condition */ I2Cx->CR1 |= I2C_CR1_START; } else { /* Disable the START condition generation */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START); } } /** * @brief Generates I2Cx communication STOP condition. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2C STOP condition generation. * This parameter can be: ENABLE or DISABLE. * @retval None. */ void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Generate a STOP condition */ I2Cx->CR1 |= I2C_CR1_STOP; } else { /* Disable the STOP condition generation */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP); } } /** * @brief Transmits the address byte to select the slave device. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param Address: specifies the slave address which will be transmitted * @param I2C_Direction: specifies whether the I2C device will be a Transmitter * or a Receiver. * This parameter can be one of the following values * @arg I2C_Direction_Transmitter: Transmitter mode * @arg I2C_Direction_Receiver: Receiver mode * @retval None. */ void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_DIRECTION(I2C_Direction)); /* Test on the direction to set/reset the read/write bit */ if (I2C_Direction != I2C_Direction_Transmitter) { /* Set the address bit0 for read */ Address |= I2C_OAR1_ADD0; } else { /* Reset the address bit0 for write */ Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0); } /* Send the address */ I2Cx->DR = Address; } /** * @brief Enables or disables the specified I2C acknowledge feature. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2C Acknowledgement. * This parameter can be: ENABLE or DISABLE. * @retval None. */ void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the acknowledgement */ I2Cx->CR1 |= I2C_CR1_ACK; } else { /* Disable the acknowledgement */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK); } } /** * @brief Configures the specified I2C own address2. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param Address: specifies the 7bit I2C own address2. * @retval None. */ void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) { uint16_t tmpreg = 0; /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); /* Get the old register value */ tmpreg = I2Cx->OAR2; /* Reset I2Cx Own address2 bit [7:1] */ tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2); /* Set I2Cx Own address2 */ tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); /* Store the new register value */ I2Cx->OAR2 = tmpreg; } /** * @brief Enables or disables the specified I2C dual addressing mode. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2C dual addressing mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable dual addressing mode */ I2Cx->OAR2 |= I2C_OAR2_ENDUAL; } else { /* Disable dual addressing mode */ I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL); } } /** * @brief Enables or disables the specified I2C general call feature. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2C General call. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable generall call */ I2Cx->CR1 |= I2C_CR1_ENGC; } else { /* Disable generall call */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC); } } /** * @brief Enables or disables the specified I2C software reset. * @note When software reset is enabled, the I2C IOs are released (this can * be useful to recover from bus errors). * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2C software reset. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Peripheral under reset */ I2Cx->CR1 |= I2C_CR1_SWRST; } else { /* Peripheral not under reset */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST); } } /** * @brief Enables or disables the specified I2C Clock stretching. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2Cx Clock stretching. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState == DISABLE) { /* Enable the selected I2C Clock stretching */ I2Cx->CR1 |= I2C_CR1_NOSTRETCH; } else { /* Disable the selected I2C Clock stretching */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH); } } /** * @brief Selects the specified I2C fast mode duty cycle. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_DutyCycle: specifies the fast mode duty cycle. * This parameter can be one of the following values: * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 * @retval None */ void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); if (I2C_DutyCycle != I2C_DutyCycle_16_9) { /* I2C fast mode Tlow/Thigh=2 */ I2Cx->CCR &= I2C_DutyCycle_2; } else { /* I2C fast mode Tlow/Thigh=16/9 */ I2Cx->CCR |= I2C_DutyCycle_16_9; } } /** * @brief Selects the specified I2C NACK position in master receiver mode. * @note This function is useful in I2C Master Receiver mode when the number * of data to be received is equal to 2. In this case, this function * should be called (with parameter I2C_NACKPosition_Next) before data * reception starts,as described in the 2-byte reception procedure * recommended in Reference Manual in Section: Master receiver. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_NACKPosition: specifies the NACK position. * This parameter can be one of the following values: * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last * received byte. * @arg I2C_NACKPosition_Current: indicates that current byte is the last * received byte. * * @note This function configures the same bit (POS) as I2C_PECPositionConfig() * but is intended to be used in I2C mode while I2C_PECPositionConfig() * is intended to used in SMBUS mode. * * @retval None */ void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); /* Check the input parameter */ if (I2C_NACKPosition == I2C_NACKPosition_Next) { /* Next byte in shift register is the last received byte */ I2Cx->CR1 |= I2C_NACKPosition_Next; } else { /* Current byte in shift register is the last received byte */ I2Cx->CR1 &= I2C_NACKPosition_Current; } } /** * @brief Drives the SMBusAlert pin high or low for the specified I2C. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_SMBusAlert: specifies SMBAlert pin level. * This parameter can be one of the following values: * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low * @arg I2C_SMBusAlert_High: SMBAlert pin driven high * @retval None */ void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); if (I2C_SMBusAlert == I2C_SMBusAlert_Low) { /* Drive the SMBusAlert pin Low */ I2Cx->CR1 |= I2C_SMBusAlert_Low; } else { /* Drive the SMBusAlert pin High */ I2Cx->CR1 &= I2C_SMBusAlert_High; } } /** * @brief Enables or disables the specified I2C ARP. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2Cx ARP. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected I2C ARP */ I2Cx->CR1 |= I2C_CR1_ENARP; } else { /* Disable the selected I2C ARP */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP); } } /** * @} */ /** @defgroup I2C_Group2 Data transfers functions * @brief Data transfers functions * @verbatim =============================================================================== ##### Data transfers functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Sends a data byte through the I2Cx peripheral. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param Data: Byte to be transmitted.. * @retval None */ void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); /* Write in the DR register the data to be sent */ I2Cx->DR = Data; } /** * @brief Returns the most recent received data by the I2Cx peripheral. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @retval The value of the received data. */ uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); /* Return the data in the DR register */ return (uint8_t)I2Cx->DR; } /** * @} */ /** @defgroup I2C_Group3 PEC management functions * @brief PEC management functions * @verbatim =============================================================================== ##### PEC management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified I2C PEC transfer. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2C PEC transmission. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected I2C PEC transmission */ I2Cx->CR1 |= I2C_CR1_PEC; } else { /* Disable the selected I2C PEC transmission */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC); } } /** * @brief Selects the specified I2C PEC position. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_PECPosition: specifies the PEC position. * This parameter can be one of the following values: * @arg I2C_PECPosition_Next: indicates that the next byte is PEC * @arg I2C_PECPosition_Current: indicates that current byte is PEC * * @note This function configures the same bit (POS) as I2C_NACKPositionConfig() * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() * is intended to used in I2C mode. * * @retval None */ void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); if (I2C_PECPosition == I2C_PECPosition_Next) { /* Next byte in shift register is PEC */ I2Cx->CR1 |= I2C_PECPosition_Next; } else { /* Current byte in shift register is PEC */ I2Cx->CR1 &= I2C_PECPosition_Current; } } /** * @brief Enables or disables the PEC value calculation of the transferred bytes. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2Cx PEC value calculation. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected I2C PEC calculation */ I2Cx->CR1 |= I2C_CR1_ENPEC; } else { /* Disable the selected I2C PEC calculation */ I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC); } } /** * @brief Returns the PEC value for the specified I2C. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @retval The PEC value. */ uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); /* Return the selected I2C PEC value */ return ((I2Cx->SR2) >> 8); } /** * @} */ /** @defgroup I2C_Group4 DMA transfers management functions * @brief DMA transfers management functions * @verbatim =============================================================================== ##### DMA transfers management functions ##### =============================================================================== This section provides functions allowing to configure the I2C DMA channels requests. @endverbatim * @{ */ /** * @brief Enables or disables the specified I2C DMA requests. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2C DMA transfer. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected I2C DMA requests */ I2Cx->CR2 |= I2C_CR2_DMAEN; } else { /* Disable the selected I2C DMA requests */ I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN); } } /** * @brief Specifies that the next DMA transfer is the last one. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param NewState: new state of the I2C DMA last transfer. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Next DMA transfer is the last transfer */ I2Cx->CR2 |= I2C_CR2_LAST; } else { /* Next DMA transfer is not the last transfer */ I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST); } } /** * @} */ /** @defgroup I2C_Group5 Interrupts events and flags management functions * @brief Interrupts, events and flags management functions * @verbatim =============================================================================== ##### Interrupts, events and flags management functions ##### =============================================================================== [..] This section provides functions allowing to configure the I2C Interrupts sources and check or clear the flags or pending bits status. The user should identify which mode will be used in his application to manage the communication: Polling mode, Interrupt mode or DMA mode. ##### I2C State Monitoring Functions ##### =============================================================================== [..] This I2C driver provides three different ways for I2C state monitoring depending on the application requirements and constraints: (#) Basic state monitoring (Using I2C_CheckEvent() function) It compares the status registers (SR1 and SR2) content to a given event (can be the combination of one or more flags). It returns SUCCESS if the current status includes the given flags and returns ERROR if one or more flags are missing in the current status. (++) When to use (+++) This function is suitable for most applications as well as for startup activity since the events are fully described in the product reference manual (RM0090). (+++) It is also suitable for users who need to define their own events. (++) Limitations If an error occurs (ie. error flags are set besides to the monitored flags), the I2C_CheckEvent() function may return SUCCESS despite the communication hold or corrupted real state. In this case, it is advised to use error interrupts to monitor the error events and handle them in the interrupt IRQ handler. -@@- For error management, it is advised to use the following functions: (+@@) I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). (+@@) I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. Where x is the peripheral instance (I2C1, I2C2 ...) (+@@) I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the I2Cx_ER_IRQHandler() function in order to determine which error occurred. (+@@) I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() and/or I2C_GenerateStop() in order to clear the error flag and source and return to correct communication status. (#) Advanced state monitoring (Using the function I2C_GetLastEvent()) Using the function I2C_GetLastEvent() which returns the image of both status registers in a single word (uint32_t) (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). (++) When to use (+++) This function is suitable for the same applications above but it allows to overcome the mentioned limitation of I2C_GetFlagStatus() function. (+++) The returned value could be compared to events already defined in the library (stm32f4xx_i2c.h) or to custom values defined by user. This function is suitable when multiple flags are monitored at the same time. (+++) At the opposite of I2C_CheckEvent() function, this function allows user to choose when an event is accepted (when all events flags are set and no other flags are set or just when the needed flags are set like I2C_CheckEvent() function. (++) Limitations (+++) User may need to define his own events. (+++) Same remark concerning the error management is applicable for this function if user decides to check only regular communication flags (and ignores error flags). (#) Flag-based state monitoring (Using the function I2C_GetFlagStatus()) Using the function I2C_GetFlagStatus() which simply returns the status of one single flag (ie. I2C_FLAG_RXNE ...). (++) When to use (+++) This function could be used for specific applications or in debug phase. (+++) It is suitable when only one flag checking is needed (most I2C events are monitored through multiple flags). (++) Limitations: (+++) When calling this function, the Status register is accessed. Some flags are cleared when the status register is accessed. So checking the status of one Flag, may clear other ones. (+++) Function may need to be called twice or more in order to monitor one single event. For detailed description of Events, please refer to section I2C_Events in stm32f4xx_i2c.h file. @endverbatim * @{ */ /** * @brief Reads the specified I2C register and returns its value. * @param I2C_Register: specifies the register to read. * This parameter can be one of the following values: * @arg I2C_Register_CR1: CR1 register. * @arg I2C_Register_CR2: CR2 register. * @arg I2C_Register_OAR1: OAR1 register. * @arg I2C_Register_OAR2: OAR2 register. * @arg I2C_Register_DR: DR register. * @arg I2C_Register_SR1: SR1 register. * @arg I2C_Register_SR2: SR2 register. * @arg I2C_Register_CCR: CCR register. * @arg I2C_Register_TRISE: TRISE register. * @retval The value of the read register. */ uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_REGISTER(I2C_Register)); tmp = (uint32_t) I2Cx; tmp += I2C_Register; /* Return the selected register value */ return (*(__IO uint16_t *) tmp); } /** * @brief Enables or disables the specified I2C interrupts. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg I2C_IT_BUF: Buffer interrupt mask * @arg I2C_IT_EVT: Event interrupt mask * @arg I2C_IT_ERR: Error interrupt mask * @param NewState: new state of the specified I2C interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_I2C_CONFIG_IT(I2C_IT)); if (NewState != DISABLE) { /* Enable the selected I2C interrupts */ I2Cx->CR2 |= I2C_IT; } else { /* Disable the selected I2C interrupts */ I2Cx->CR2 &= (uint16_t)~I2C_IT; } } /* =============================================================================== 1. Basic state monitoring =============================================================================== */ /** * @brief Checks whether the last I2Cx Event is equal to the one passed * as parameter. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_EVENT: specifies the event to be checked. * This parameter can be one of the following values: * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1 * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1 * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1 * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1 * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1 * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2 * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2 * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2 * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3 * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3 * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3 * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2 * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4 * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5 * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6 * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6 * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7 * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8 * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2 * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9 * * @note For detailed description of Events, please refer to section I2C_Events * in stm32f4xx_i2c.h file. * * @retval An ErrorStatus enumeration value: * - SUCCESS: Last event is equal to the I2C_EVENT * - ERROR: Last event is different from the I2C_EVENT */ ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) { uint32_t lastevent = 0; uint32_t flag1 = 0, flag2 = 0; ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_EVENT(I2C_EVENT)); /* Read the I2Cx status register */ flag1 = I2Cx->SR1; flag2 = I2Cx->SR2; flag2 = flag2 << 16; /* Get the last event value from I2C status register */ lastevent = (flag1 | flag2) & FLAG_MASK; /* Check whether the last event contains the I2C_EVENT */ if ((lastevent & I2C_EVENT) == I2C_EVENT) { /* SUCCESS: last event is equal to I2C_EVENT */ status = SUCCESS; } else { /* ERROR: last event is different from I2C_EVENT */ status = ERROR; } /* Return status */ return status; } /* =============================================================================== 2. Advanced state monitoring =============================================================================== */ /** * @brief Returns the last I2Cx Event. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * * @note For detailed description of Events, please refer to section I2C_Events * in stm32f4xx_i2c.h file. * * @retval The last event */ uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) { uint32_t lastevent = 0; uint32_t flag1 = 0, flag2 = 0; /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); /* Read the I2Cx status register */ flag1 = I2Cx->SR1; flag2 = I2Cx->SR2; flag2 = flag2 << 16; /* Get the last event value from I2C status register */ lastevent = (flag1 | flag2) & FLAG_MASK; /* Return status */ return lastevent; } /* =============================================================================== 3. Flag-based state monitoring =============================================================================== */ /** * @brief Checks whether the specified I2C flag is set or not. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) * @arg I2C_FLAG_TRA: Transmitter/Receiver flag * @arg I2C_FLAG_BUSY: Bus busy flag * @arg I2C_FLAG_MSL: Master/Slave flag * @arg I2C_FLAG_SMBALERT: SMBus Alert flag * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag * @arg I2C_FLAG_PECERR: PEC error in reception flag * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) * @arg I2C_FLAG_AF: Acknowledge failure flag * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) * @arg I2C_FLAG_BERR: Bus error flag * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) * @arg I2C_FLAG_BTF: Byte transfer finished flag * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" * Address matched flag (Slave mode)"ENDAD" * @arg I2C_FLAG_SB: Start bit flag (Master mode) * @retval The new state of I2C_FLAG (SET or RESET). */ FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) { FlagStatus bitstatus = RESET; __IO uint32_t i2creg = 0, i2cxbase = 0; /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); /* Get the I2Cx peripheral base address */ i2cxbase = (uint32_t)I2Cx; /* Read flag register index */ i2creg = I2C_FLAG >> 28; /* Get bit[23:0] of the flag */ I2C_FLAG &= FLAG_MASK; if(i2creg != 0) { /* Get the I2Cx SR1 register address */ i2cxbase += 0x14; } else { /* Flag in I2Cx SR2 Register */ I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); /* Get the I2Cx SR2 register address */ i2cxbase += 0x18; } if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) { /* I2C_FLAG is set */ bitstatus = SET; } else { /* I2C_FLAG is reset */ bitstatus = RESET; } /* Return the I2C_FLAG status */ return bitstatus; } /** * @brief Clears the I2Cx's pending flags. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg I2C_FLAG_SMBALERT: SMBus Alert flag * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag * @arg I2C_FLAG_PECERR: PEC error in reception flag * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) * @arg I2C_FLAG_AF: Acknowledge failure flag * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) * @arg I2C_FLAG_BERR: Bus error flag * * @note STOPF (STOP detection) is cleared by software sequence: a read operation * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). * @note ADD10 (10-bit header sent) is cleared by software sequence: a read * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the * second byte of the address in DR register. * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a * read/write to I2C_DR register (I2C_SendData()). * @note ADDR (Address sent) is cleared by software sequence: a read operation to * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to * I2C_SR2 register ((void)(I2Cx->SR2)). * @note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR * register (I2C_SendData()). * * @retval None */ void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) { uint32_t flagpos = 0; /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); /* Get the I2C flag position */ flagpos = I2C_FLAG & FLAG_MASK; /* Clear the selected I2C flag */ I2Cx->SR1 = (uint16_t)~flagpos; } /** * @brief Checks whether the specified I2C interrupt has occurred or not. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_IT: specifies the interrupt source to check. * This parameter can be one of the following values: * @arg I2C_IT_SMBALERT: SMBus Alert flag * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag * @arg I2C_IT_PECERR: PEC error in reception flag * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) * @arg I2C_IT_AF: Acknowledge failure flag * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) * @arg I2C_IT_BERR: Bus error flag * @arg I2C_IT_TXE: Data register empty flag (Transmitter) * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) * @arg I2C_IT_BTF: Byte transfer finished flag * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" * Address matched flag (Slave mode)"ENDAD" * @arg I2C_IT_SB: Start bit flag (Master mode) * @retval The new state of I2C_IT (SET or RESET). */ ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) { ITStatus bitstatus = RESET; uint32_t enablestatus = 0; /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_GET_IT(I2C_IT)); /* Check if the interrupt source is enabled or not */ enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ; /* Get bit[23:0] of the flag */ I2C_IT &= FLAG_MASK; /* Check the status of the specified I2C flag */ if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) { /* I2C_IT is set */ bitstatus = SET; } else { /* I2C_IT is reset */ bitstatus = RESET; } /* Return the I2C_IT status */ return bitstatus; } /** * @brief Clears the I2Cx's interrupt pending bits. * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. * @param I2C_IT: specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg I2C_IT_SMBALERT: SMBus Alert interrupt * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt * @arg I2C_IT_PECERR: PEC error in reception interrupt * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) * @arg I2C_IT_AF: Acknowledge failure interrupt * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) * @arg I2C_IT_BERR: Bus error interrupt * * @note STOPF (STOP detection) is cleared by software sequence: a read operation * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). * @note ADD10 (10-bit header sent) is cleared by software sequence: a read * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second * byte of the address in I2C_DR register. * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a * read/write to I2C_DR register (I2C_SendData()). * @note ADDR (Address sent) is cleared by software sequence: a read operation to * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to * I2C_SR2 register ((void)(I2Cx->SR2)). * @note SB (Start Bit) is cleared by software sequence: a read operation to * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to * I2C_DR register (I2C_SendData()). * @retval None */ void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) { uint32_t flagpos = 0; /* Check the parameters */ assert_param(IS_I2C_ALL_PERIPH(I2Cx)); assert_param(IS_I2C_CLEAR_IT(I2C_IT)); /* Get the I2C flag position */ flagpos = I2C_IT & FLAG_MASK; /* Clear the selected I2C flag */ I2Cx->SR1 = (uint16_t)~flagpos; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c ================================================ /** ****************************************************************************** * @file stm32f4xx_iwdg.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Independent watchdog (IWDG) peripheral: * + Prescaler and Counter configuration * + IWDG activation * + Flag management * @verbatim =============================================================================== ##### IWDG features ##### =============================================================================== [..] The IWDG can be started by either software or hardware (configurable through option byte). The IWDG is clocked by its own dedicated low-speed clock (LSI) and thus stays active even if the main clock fails. Once the IWDG is started, the LSI is forced ON and cannot be disabled (LSI cannot be disabled too), and the counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000) a system reset is generated. The IWDG counter should be reloaded at regular intervals to prevent an MCU reset. The IWDG is implemented in the VDD voltage domain that is still functional in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). IWDGRST flag in RCC_CSR register can be used to inform when a IWDG reset occurs. Min-max timeout value @32KHz (LSI): ~125us / ~32.7s The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx devices provide the capability to measure the LSI frequency (LSI clock connected internally to TIM5 CH4 input capture). The measured value can be used to have an IWDG timeout with an acceptable accuracy. For more information, please refer to the STM32F4xx Reference manual ##### How to use this driver ##### =============================================================================== [..] (#) Enable write access to IWDG_PR and IWDG_RLR registers using IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function (#) Configure the IWDG prescaler using IWDG_SetPrescaler() function (#) Configure the IWDG counter value using IWDG_SetReload() function. This value will be loaded in the IWDG counter each time the counter is reloaded, then the IWDG will start counting down from this value. (#) Start the IWDG using IWDG_Enable() function, when the IWDG is used in software mode (no need to enable the LSI, it will be enabled by hardware) (#) Then the application program must reload the IWDG counter at regular intervals during normal operation to prevent an MCU reset, using IWDG_ReloadCounter() function. @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_iwdg.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup IWDG * @brief IWDG driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* KR register bit mask */ #define KR_KEY_RELOAD ((uint16_t)0xAAAA) #define KR_KEY_ENABLE ((uint16_t)0xCCCC) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup IWDG_Private_Functions * @{ */ /** @defgroup IWDG_Group1 Prescaler and Counter configuration functions * @brief Prescaler and Counter configuration functions * @verbatim =============================================================================== ##### Prescaler and Counter configuration functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. * This parameter can be one of the following values: * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers * @retval None */ void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) { /* Check the parameters */ assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); IWDG->KR = IWDG_WriteAccess; } /** * @brief Sets IWDG Prescaler value. * @param IWDG_Prescaler: specifies the IWDG Prescaler value. * This parameter can be one of the following values: * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 * @retval None */ void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) { /* Check the parameters */ assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); IWDG->PR = IWDG_Prescaler; } /** * @brief Sets IWDG Reload value. * @param Reload: specifies the IWDG Reload value. * This parameter must be a number between 0 and 0x0FFF. * @retval None */ void IWDG_SetReload(uint16_t Reload) { /* Check the parameters */ assert_param(IS_IWDG_RELOAD(Reload)); IWDG->RLR = Reload; } /** * @brief Reloads IWDG counter with value defined in the reload register * (write access to IWDG_PR and IWDG_RLR registers disabled). * @param None * @retval None */ void IWDG_ReloadCounter(void) { IWDG->KR = KR_KEY_RELOAD; } /** * @} */ /** @defgroup IWDG_Group2 IWDG activation function * @brief IWDG activation function * @verbatim =============================================================================== ##### IWDG activation function ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). * @param None * @retval None */ void IWDG_Enable(void) { IWDG->KR = KR_KEY_ENABLE; } /** * @} */ /** @defgroup IWDG_Group3 Flag management function * @brief Flag management function * @verbatim =============================================================================== ##### Flag management function ##### =============================================================================== @endverbatim * @{ */ /** * @brief Checks whether the specified IWDG flag is set or not. * @param IWDG_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg IWDG_FLAG_PVU: Prescaler Value Update on going * @arg IWDG_FLAG_RVU: Reload Value Update on going * @retval The new state of IWDG_FLAG (SET or RESET). */ FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_IWDG_FLAG(IWDG_FLAG)); if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } /* Return the flag status */ return bitstatus; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c ================================================ /** ****************************************************************************** * @file stm32f4xx_ltdc.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the LTDC controller (LTDC) peripheral: * + Initialization and configuration * + Interrupts and flags management * * @verbatim =============================================================================== ##### How to use this driver ##### =============================================================================== [..] (#) Enable LTDC clock using RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, ENABLE) function. (#) Configures LTDC (++) Configure the required Pixel clock following the panel datasheet (++) Configure the Synchronous timings: VSYNC, HSYNC, Vertical and Horizontal back proch, active data area and the front proch timings (++) Configure the synchronous signals and clock polarity in the LTDC_GCR register (#) Configures Layer1/2 parameters (++) The Layer window horizontal and vertical position in the LTDC_LxWHPCR and LTDC_WVPCR registers. The layer window must be in the active data area. (++) The pixel input format in the LTDC_LxPFCR register (++) The color frame buffer start address in the LTDC_LxCFBAR register (++) The line length and pitch of the color frame buffer in the LTDC_LxCFBLR register (++) The number of lines of the color frame buffer in the LTDC_LxCFBLNR register (++) if needed, load the CLUT with the RGB values and the address in the LTDC_LxCLUTWR register (++) If needed, configure the default color and the blending factors respectively in the LTDC_LxDCCR and LTDC_LxBFCR registers (++) If needed, Dithering and color keying can be be enabled respectively in the LTDC_GCR and LTDC_LxCKCR registers. It can be also enabled on the fly. (#) Enable Layer1/2 and if needed the CLUT in the LTDC_LxCR register (#) Reload the shadow registers to active register through the LTDC_SRCR register. -@- All layer parameters can be be modified on the fly except the CLUT. The new configuration has to be either reloaded immediately or during vertical blanking period by configuring the LTDC_SRCR register. (#) Call the LTDC_Cmd() to enable the LTDC controller. @endverbatim ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * *

© COPYRIGHT 2013 STMicroelectronics

****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_ltdc.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup LTDC * @brief LTDC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ #define GCR_MASK ((uint32_t)0x0FFE888F) /* LTDC GCR Mask */ /** @defgroup LTDC_Private_Functions * @{ */ /** @defgroup LTDC_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Initialize and configure the LTDC (+) Enable or Disable Dither (+) Define the position of the line interrupt (+) reload layers registers with new parameters (+) Initialize and configure layer1 and layer2 (+) Set and configure the color keying functionality (+) Configure and Enables or disables CLUT @endverbatim * @{ */ /** * @brief Deinitializes the LTDC peripheral registers to their default reset * values. * @param None * @retval None */ void LTDC_DeInit(void) { /* Enable LTDC reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, ENABLE); /* Release LTDC from reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, DISABLE); } /** * @brief Initializes the LTDC peripheral according to the specified parameters * in the LTDC_InitStruct. * @note This function can be used only when the LTDC is disabled. * @param LTDC_InitStruct: pointer to a LTDC_InitTypeDef structure that contains * the configuration information for the specified LTDC peripheral. * @retval None */ void LTDC_Init(LTDC_InitTypeDef* LTDC_InitStruct) { uint32_t horizontalsync = 0; uint32_t accumulatedHBP = 0; uint32_t accumulatedactiveW = 0; uint32_t totalwidth = 0; uint32_t backgreen = 0; uint32_t backred = 0; /* Check function parameters */ assert_param(IS_LTDC_HSYNC(LTDC_InitStruct->LTDC_HorizontalSync)); assert_param(IS_LTDC_VSYNC(LTDC_InitStruct->LTDC_VerticalSync)); assert_param(IS_LTDC_AHBP(LTDC_InitStruct->LTDC_AccumulatedHBP)); assert_param(IS_LTDC_AVBP(LTDC_InitStruct->LTDC_AccumulatedVBP)); assert_param(IS_LTDC_AAH(LTDC_InitStruct->LTDC_AccumulatedActiveH)); assert_param(IS_LTDC_AAW(LTDC_InitStruct->LTDC_AccumulatedActiveW)); assert_param(IS_LTDC_TOTALH(LTDC_InitStruct->LTDC_TotalHeigh)); assert_param(IS_LTDC_TOTALW(LTDC_InitStruct->LTDC_TotalWidth)); assert_param(IS_LTDC_HSPOL(LTDC_InitStruct->LTDC_HSPolarity)); assert_param(IS_LTDC_VSPOL(LTDC_InitStruct->LTDC_VSPolarity)); assert_param(IS_LTDC_DEPOL(LTDC_InitStruct->LTDC_DEPolarity)); assert_param(IS_LTDC_PCPOL(LTDC_InitStruct->LTDC_PCPolarity)); assert_param(IS_LTDC_BackBlueValue(LTDC_InitStruct->LTDC_BackgroundBlueValue)); assert_param(IS_LTDC_BackGreenValue(LTDC_InitStruct->LTDC_BackgroundGreenValue)); assert_param(IS_LTDC_BackRedValue(LTDC_InitStruct->LTDC_BackgroundRedValue)); /* Sets Synchronization size */ LTDC->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); horizontalsync = (LTDC_InitStruct->LTDC_HorizontalSync << 16); LTDC->SSCR |= (horizontalsync | LTDC_InitStruct->LTDC_VerticalSync); /* Sets Accumulated Back porch */ LTDC->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); accumulatedHBP = (LTDC_InitStruct->LTDC_AccumulatedHBP << 16); LTDC->BPCR |= (accumulatedHBP | LTDC_InitStruct->LTDC_AccumulatedVBP); /* Sets Accumulated Active Width */ LTDC->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); accumulatedactiveW = (LTDC_InitStruct->LTDC_AccumulatedActiveW << 16); LTDC->AWCR |= (accumulatedactiveW | LTDC_InitStruct->LTDC_AccumulatedActiveH); /* Sets Total Width */ LTDC->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); totalwidth = (LTDC_InitStruct->LTDC_TotalWidth << 16); LTDC->TWCR |= (totalwidth | LTDC_InitStruct->LTDC_TotalHeigh); LTDC->GCR &= (uint32_t)GCR_MASK; LTDC->GCR |= (uint32_t)(LTDC_InitStruct->LTDC_HSPolarity | LTDC_InitStruct->LTDC_VSPolarity | \ LTDC_InitStruct->LTDC_DEPolarity | LTDC_InitStruct->LTDC_PCPolarity); /* sets the background color value */ backgreen = (LTDC_InitStruct->LTDC_BackgroundGreenValue << 8); backred = (LTDC_InitStruct->LTDC_BackgroundRedValue << 16); LTDC->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); LTDC->BCCR |= (backred | backgreen | LTDC_InitStruct->LTDC_BackgroundBlueValue); } /** * @brief Fills each LTDC_InitStruct member with its default value. * @param LTDC_InitStruct: pointer to a LTDC_InitTypeDef structure which will * be initialized. * @retval None */ void LTDC_StructInit(LTDC_InitTypeDef* LTDC_InitStruct) { /*--------------- Reset LTDC init structure parameters values ----------------*/ LTDC_InitStruct->LTDC_HSPolarity = LTDC_HSPolarity_AL; /*!< Initialize the LTDC_HSPolarity member */ LTDC_InitStruct->LTDC_VSPolarity = LTDC_VSPolarity_AL; /*!< Initialize the LTDC_VSPolarity member */ LTDC_InitStruct->LTDC_DEPolarity = LTDC_DEPolarity_AL; /*!< Initialize the LTDC_DEPolarity member */ LTDC_InitStruct->LTDC_PCPolarity = LTDC_PCPolarity_IPC; /*!< Initialize the LTDC_PCPolarity member */ LTDC_InitStruct->LTDC_HorizontalSync = 0x00; /*!< Initialize the LTDC_HorizontalSync member */ LTDC_InitStruct->LTDC_VerticalSync = 0x00; /*!< Initialize the LTDC_VerticalSync member */ LTDC_InitStruct->LTDC_AccumulatedHBP = 0x00; /*!< Initialize the LTDC_AccumulatedHBP member */ LTDC_InitStruct->LTDC_AccumulatedVBP = 0x00; /*!< Initialize the LTDC_AccumulatedVBP member */ LTDC_InitStruct->LTDC_AccumulatedActiveW = 0x00; /*!< Initialize the LTDC_AccumulatedActiveW member */ LTDC_InitStruct->LTDC_AccumulatedActiveH = 0x00; /*!< Initialize the LTDC_AccumulatedActiveH member */ LTDC_InitStruct->LTDC_TotalWidth = 0x00; /*!< Initialize the LTDC_TotalWidth member */ LTDC_InitStruct->LTDC_TotalHeigh = 0x00; /*!< Initialize the LTDC_TotalHeigh member */ LTDC_InitStruct->LTDC_BackgroundRedValue = 0x00; /*!< Initialize the LTDC_BackgroundRedValue member */ LTDC_InitStruct->LTDC_BackgroundGreenValue = 0x00; /*!< Initialize the LTDC_BackgroundGreenValue member */ LTDC_InitStruct->LTDC_BackgroundBlueValue = 0x00; /*!< Initialize the LTDC_BackgroundBlueValue member */ } /** * @brief Enables or disables the LTDC Controller. * @param NewState: new state of the LTDC peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void LTDC_Cmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable LTDC by setting LTDCEN bit */ LTDC->GCR |= (uint32_t)LTDC_GCR_LTDCEN; } else { /* Disable LTDC by clearing LTDCEN bit */ LTDC->GCR &= ~(uint32_t)LTDC_GCR_LTDCEN; } } /** * @brief Enables or disables Dither. * @param NewState: new state of the Dither. * This parameter can be: ENABLE or DISABLE. * @retval None */ void LTDC_DitherCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable Dither by setting DTEN bit */ LTDC->GCR |= (uint32_t)LTDC_GCR_DTEN; } else { /* Disable Dither by clearing DTEN bit */ LTDC->GCR &= ~(uint32_t)LTDC_GCR_DTEN; } } /** * @brief Get the dither RGB width. * @param LTDC_RGB_InitStruct: pointer to a LTDC_RGBTypeDef structure that contains * the Dither RGB width. * @retval None */ LTDC_RGBTypeDef LTDC_GetRGBWidth(void) { LTDC_RGBTypeDef LTDC_RGB_InitStruct; LTDC->GCR &= (uint32_t)GCR_MASK; LTDC_RGB_InitStruct.LTDC_BlueWidth = (uint32_t)((LTDC->GCR >> 4) & 0x7); LTDC_RGB_InitStruct.LTDC_GreenWidth = (uint32_t)((LTDC->GCR >> 8) & 0x7); LTDC_RGB_InitStruct.LTDC_RedWidth = (uint32_t)((LTDC->GCR >> 12) & 0x7); return LTDC_RGB_InitStruct; } /** * @brief Fills each LTDC_RGBStruct member with its default value. * @param LTDC_RGB_InitStruct: pointer to a LTDC_RGBTypeDef structure which will * be initialized. * @retval None */ void LTDC_RGBStructInit(LTDC_RGBTypeDef* LTDC_RGB_InitStruct) { LTDC_RGB_InitStruct->LTDC_BlueWidth = 0x02; LTDC_RGB_InitStruct->LTDC_GreenWidth = 0x02; LTDC_RGB_InitStruct->LTDC_RedWidth = 0x02; } /** * @brief Define the position of the line interrupt . * @param LTDC_LIPositionConfig: Line Interrupt Position. * @retval None */ void LTDC_LIPConfig(uint32_t LTDC_LIPositionConfig) { /* Check the parameters */ assert_param(IS_LTDC_LIPOS(LTDC_LIPositionConfig)); /* Sets the Line Interrupt position */ LTDC->LIPCR = (uint32_t)LTDC_LIPositionConfig; } /** * @brief reload layers registers with new parameters * @param LTDC_Reload: specifies the type of reload. * This parameter can be one of the following values: * @arg LTDC_IMReload: Vertical blanking reload. * @arg LTDC_VBReload: Immediate reload. * @retval None */ void LTDC_ReloadConfig(uint32_t LTDC_Reload) { /* Check the parameters */ assert_param(IS_LTDC_RELOAD(LTDC_Reload)); /* Sets the Reload type */ LTDC->SRCR = (uint32_t)LTDC_Reload; } /** * @brief Initializes the LTDC Layer according to the specified parameters * in the LTDC_LayerStruct. * @note This function can be used only when the LTDC is disabled. * @param LTDC_layerx: Select the layer to be configured, this parameter can be * one of the following values: LTDC_Layer1, LTDC_Layer2 * @param LTDC_LayerStruct: pointer to a LTDC_LayerTypeDef structure that contains * the configuration information for the specified LTDC peripheral. * @retval None */ void LTDC_LayerInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_Layer_InitTypeDef* LTDC_Layer_InitStruct) { uint32_t whsppos = 0; uint32_t wvsppos = 0; uint32_t dcgreen = 0; uint32_t dcred = 0; uint32_t dcalpha = 0; uint32_t cfbp = 0; /* Check the parameters */ assert_param(IS_LTDC_Pixelformat(LTDC_Layer_InitStruct->LTDC_PixelFormat)); assert_param(IS_LTDC_BlendingFactor1(LTDC_Layer_InitStruct->LTDC_BlendingFactor_1)); assert_param(IS_LTDC_BlendingFactor2(LTDC_Layer_InitStruct->LTDC_BlendingFactor_2)); assert_param(IS_LTDC_HCONFIGST(LTDC_Layer_InitStruct->LTDC_HorizontalStart)); assert_param(IS_LTDC_HCONFIGSP(LTDC_Layer_InitStruct->LTDC_HorizontalStop)); assert_param(IS_LTDC_VCONFIGST(LTDC_Layer_InitStruct->LTDC_VerticalStart)); assert_param(IS_LTDC_VCONFIGSP(LTDC_Layer_InitStruct->LTDC_VerticalStop)); assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorBlue)); assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorGreen)); assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorRed)); assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorAlpha)); assert_param(IS_LTDC_CFBP(LTDC_Layer_InitStruct->LTDC_CFBPitch)); assert_param(IS_LTDC_CFBLL(LTDC_Layer_InitStruct->LTDC_CFBLineLength)); assert_param(IS_LTDC_CFBLNBR(LTDC_Layer_InitStruct->LTDC_CFBLineNumber)); /* Configures the horizontal start and stop position */ whsppos = LTDC_Layer_InitStruct->LTDC_HorizontalStop << 16; LTDC_Layerx->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); LTDC_Layerx->WHPCR = (LTDC_Layer_InitStruct->LTDC_HorizontalStart | whsppos); /* Configures the vertical start and stop position */ wvsppos = LTDC_Layer_InitStruct->LTDC_VerticalStop << 16; LTDC_Layerx->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); LTDC_Layerx->WVPCR = (LTDC_Layer_InitStruct->LTDC_VerticalStart | wvsppos); /* Specifies the pixel format */ LTDC_Layerx->PFCR &= ~(LTDC_LxPFCR_PF); LTDC_Layerx->PFCR = (LTDC_Layer_InitStruct->LTDC_PixelFormat); /* Configures the default color values */ dcgreen = (LTDC_Layer_InitStruct->LTDC_DefaultColorGreen << 8); dcred = (LTDC_Layer_InitStruct->LTDC_DefaultColorRed << 16); dcalpha = (LTDC_Layer_InitStruct->LTDC_DefaultColorAlpha << 24); LTDC_Layerx->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA); LTDC_Layerx->DCCR = (LTDC_Layer_InitStruct->LTDC_DefaultColorBlue | dcgreen | \ dcred | dcalpha); /* Specifies the constant alpha value */ LTDC_Layerx->CACR &= ~(LTDC_LxCACR_CONSTA); LTDC_Layerx->CACR = (LTDC_Layer_InitStruct->LTDC_ConstantAlpha); /* Specifies the blending factors */ LTDC_Layerx->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1); LTDC_Layerx->BFCR = (LTDC_Layer_InitStruct->LTDC_BlendingFactor_1 | LTDC_Layer_InitStruct->LTDC_BlendingFactor_2); /* Configures the color frame buffer start address */ LTDC_Layerx->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); LTDC_Layerx->CFBAR = (LTDC_Layer_InitStruct->LTDC_CFBStartAdress); /* Configures the color frame buffer pitch in byte */ cfbp = (LTDC_Layer_InitStruct->LTDC_CFBPitch << 16); LTDC_Layerx->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); LTDC_Layerx->CFBLR = (LTDC_Layer_InitStruct->LTDC_CFBLineLength | cfbp); /* Configures the frame buffer line number */ LTDC_Layerx->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); LTDC_Layerx->CFBLNR = (LTDC_Layer_InitStruct->LTDC_CFBLineNumber); } /** * @brief Fills each LTDC_Layer_InitStruct member with its default value. * @param LTDC_Layer_InitStruct: pointer to a LTDC_LayerTypeDef structure which will * be initialized. * @retval None */ void LTDC_LayerStructInit(LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct) { /*--------------- Reset Layer structure parameters values -------------------*/ /*!< Initialize the horizontal limit member */ LTDC_Layer_InitStruct->LTDC_HorizontalStart = 0x00; LTDC_Layer_InitStruct->LTDC_HorizontalStop = 0x00; /*!< Initialize the vertical limit member */ LTDC_Layer_InitStruct->LTDC_VerticalStart = 0x00; LTDC_Layer_InitStruct->LTDC_VerticalStop = 0x00; /*!< Initialize the pixel format member */ LTDC_Layer_InitStruct->LTDC_PixelFormat = LTDC_Pixelformat_ARGB8888; /*!< Initialize the constant alpha value */ LTDC_Layer_InitStruct->LTDC_ConstantAlpha = 0xFF; /*!< Initialize the default color values */ LTDC_Layer_InitStruct->LTDC_DefaultColorBlue = 0x00; LTDC_Layer_InitStruct->LTDC_DefaultColorGreen = 0x00; LTDC_Layer_InitStruct->LTDC_DefaultColorRed = 0x00; LTDC_Layer_InitStruct->LTDC_DefaultColorAlpha = 0x00; /*!< Initialize the blending factors */ LTDC_Layer_InitStruct->LTDC_BlendingFactor_1 = LTDC_BlendingFactor1_PAxCA; LTDC_Layer_InitStruct->LTDC_BlendingFactor_2 = LTDC_BlendingFactor2_PAxCA; /*!< Initialize the frame buffer start address */ LTDC_Layer_InitStruct->LTDC_CFBStartAdress = 0x00; /*!< Initialize the frame buffer pitch and line length */ LTDC_Layer_InitStruct->LTDC_CFBLineLength = 0x00; LTDC_Layer_InitStruct->LTDC_CFBPitch = 0x00; /*!< Initialize the frame buffer line number */ LTDC_Layer_InitStruct->LTDC_CFBLineNumber = 0x00; } /** * @brief Enables or disables the LTDC_Layer Controller. * @param LTDC_layerx: Select the layer to be configured, this parameter can be * one of the following values: LTDC_Layer1, LTDC_Layer2 * @param NewState: new state of the LTDC_Layer peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void LTDC_LayerCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable LTDC_Layer by setting LEN bit */ LTDC_Layerx->CR |= (uint32_t)LTDC_LxCR_LEN; } else { /* Disable LTDC_Layer by clearing LEN bit */ LTDC_Layerx->CR &= ~(uint32_t)LTDC_LxCR_LEN; } } /** * @brief Get the current position. * @param LTDC_Pos_InitStruct: pointer to a LTDC_PosTypeDef structure that contains * the current position. * @retval None */ LTDC_PosTypeDef LTDC_GetPosStatus(void) { LTDC_PosTypeDef LTDC_Pos_InitStruct; LTDC->CPSR &= ~(LTDC_CPSR_CYPOS | LTDC_CPSR_CXPOS); LTDC_Pos_InitStruct.LTDC_POSX = (uint32_t)(LTDC->CPSR >> 16); LTDC_Pos_InitStruct.LTDC_POSY = (uint32_t)(LTDC->CPSR & 0xFFFF); return LTDC_Pos_InitStruct; } /** * @brief Fills each LTDC_Pos_InitStruct member with its default value. * @param LTDC_Pos_InitStruct: pointer to a LTDC_PosTypeDef structure which will * be initialized. * @retval None */ void LTDC_PosStructInit(LTDC_PosTypeDef* LTDC_Pos_InitStruct) { LTDC_Pos_InitStruct->LTDC_POSX = 0x00; LTDC_Pos_InitStruct->LTDC_POSY = 0x00; } /** * @brief Checks whether the specified LTDC's flag is set or not. * @param LTDC_CD: specifies the flag to check. * This parameter can be one of the following values: * @arg LTDC_CD_VDES: vertical data enable current status. * @arg LTDC_CD_HDES: horizontal data enable current status. * @arg LTDC_CD_VSYNC: Vertical Synchronization current status. * @arg LTDC_CD_HSYNC: Horizontal Synchronization current status. * @retval The new state of LTDC_CD (SET or RESET). */ FlagStatus LTDC_GetCDStatus(uint32_t LTDC_CD) { FlagStatus bitstatus; /* Check the parameters */ assert_param(IS_LTDC_GET_CD(LTDC_CD)); if ((LTDC->CDSR & LTDC_CD) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Set and configure the color keying. * @param LTDC_colorkeying_InitStruct: pointer to a LTDC_ColorKeying_InitTypeDef * structure that contains the color keying configuration. * @param LTDC_layerx: Select the layer to be configured, this parameter can be * one of the following values: LTDC_Layer1, LTDC_Layer2 * @retval None */ void LTDC_ColorKeyingConfig(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct, FunctionalState NewState) { uint32_t ckgreen = 0; uint32_t ckred = 0; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_LTDC_CKEYING(LTDC_colorkeying_InitStruct->LTDC_ColorKeyBlue)); assert_param(IS_LTDC_CKEYING(LTDC_colorkeying_InitStruct->LTDC_ColorKeyGreen)); assert_param(IS_LTDC_CKEYING(LTDC_colorkeying_InitStruct->LTDC_ColorKeyRed)); if (NewState != DISABLE) { /* Enable LTDC color keying by setting COLKEN bit */ LTDC_Layerx->CR |= (uint32_t)LTDC_LxCR_COLKEN; /* Sets the color keying values */ ckgreen = (LTDC_colorkeying_InitStruct->LTDC_ColorKeyGreen << 8); ckred = (LTDC_colorkeying_InitStruct->LTDC_ColorKeyRed << 16); LTDC_Layerx->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); LTDC_Layerx->CKCR |= (LTDC_colorkeying_InitStruct->LTDC_ColorKeyBlue | ckgreen | ckred); } else { /* Disable LTDC color keying by clearing COLKEN bit */ LTDC_Layerx->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; } /* Reload shadow register */ LTDC->SRCR = LTDC_IMReload; } /** * @brief Fills each LTDC_colorkeying_InitStruct member with its default value. * @param LTDC_colorkeying_InitStruct: pointer to a LTDC_ColorKeying_InitTypeDef structure which will * be initialized. * @retval None */ void LTDC_ColorKeyingStructInit(LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct) { /*!< Initialize the color keying values */ LTDC_colorkeying_InitStruct->LTDC_ColorKeyBlue = 0x00; LTDC_colorkeying_InitStruct->LTDC_ColorKeyGreen = 0x00; LTDC_colorkeying_InitStruct->LTDC_ColorKeyRed = 0x00; } /** * @brief Enables or disables CLUT. * @param NewState: new state of CLUT. * @param LTDC_layerx: Select the layer to be configured, this parameter can be * one of the following values: LTDC_Layer1, LTDC_Layer2 * This parameter can be: ENABLE or DISABLE. * @retval None */ void LTDC_CLUTCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable CLUT by setting CLUTEN bit */ LTDC_Layerx->CR |= (uint32_t)LTDC_LxCR_CLUTEN; } else { /* Disable CLUT by clearing CLUTEN bit */ LTDC_Layerx->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; } /* Reload shadow register */ LTDC->SRCR = LTDC_IMReload; } /** * @brief configure the CLUT. * @param LTDC_CLUT_InitStruct: pointer to a LTDC_CLUT_InitTypeDef structure that contains * the CLUT configuration. * @param LTDC_layerx: Select the layer to be configured, this parameter can be * one of the following values: LTDC_Layer1, LTDC_Layer2 * @retval None */ void LTDC_CLUTInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct) { uint32_t green = 0; uint32_t red = 0; uint32_t clutadd = 0; /* Check the parameters */ assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_CLUTAdress)); assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_RedValue)); assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_GreenValue)); assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_BlueValue)); /* Specifies the CLUT address and RGB value */ green = (LTDC_CLUT_InitStruct->LTDC_GreenValue << 8); red = (LTDC_CLUT_InitStruct->LTDC_RedValue << 16); clutadd = (LTDC_CLUT_InitStruct->LTDC_CLUTAdress << 24); LTDC_Layerx->CLUTWR = (clutadd | LTDC_CLUT_InitStruct->LTDC_BlueValue | \ green | red); } /** * @brief Fills each LTDC_CLUT_InitStruct member with its default value. * @param LTDC_CLUT_InitStruct: pointer to a LTDC_CLUT_InitTypeDef structure which will * be initialized. * @retval None */ void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct) { /*!< Initialize the CLUT adress and RGB values */ LTDC_CLUT_InitStruct->LTDC_CLUTAdress = 0x00; LTDC_CLUT_InitStruct->LTDC_BlueValue = 0x00; LTDC_CLUT_InitStruct->LTDC_GreenValue = 0x00; LTDC_CLUT_InitStruct->LTDC_RedValue = 0x00; } /** * @brief reconfigure the layer position. * @param OffsetX: horizontal offset from start active width . * @param OffsetY: vertical offset from start active height. * @param LTDC_layerx: Select the layer to be configured, this parameter can be * one of the following values: LTDC_Layer1, LTDC_Layer2 * @retval Reload of the shadow registers values must be applied after layer * position reconfiguration. */ void LTDC_LayerPosition(LTDC_Layer_TypeDef* LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY) { uint32_t tempreg, temp; uint32_t horizontal_start; uint32_t horizontal_stop; uint32_t vertical_start; uint32_t vertical_stop; LTDC_Layerx->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); LTDC_Layerx->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); /* Reconfigures the horizontal and vertical start position */ tempreg = LTDC->BPCR; horizontal_start = (tempreg >> 16) + 1 + OffsetX; vertical_start = (tempreg & 0xFFFF) + 1 + OffsetY; /* Reconfigures the horizontal and vertical stop position */ /* Get the number of byte per pixel */ tempreg = LTDC_Layerx->PFCR; if (tempreg == LTDC_Pixelformat_ARGB8888) { temp = 4; } else if (tempreg == LTDC_Pixelformat_RGB888) { temp = 3; } else if ((tempreg == LTDC_Pixelformat_ARGB4444) || (tempreg == LTDC_Pixelformat_RGB565) || (tempreg == LTDC_Pixelformat_ARGB1555) || (tempreg == LTDC_Pixelformat_AL88)) { temp = 2; } else { temp = 1; } tempreg = LTDC_Layerx->CFBLR; horizontal_stop = (((tempreg & 0x1FFF) - 3)/temp) + horizontal_start - 1; tempreg = LTDC_Layerx->CFBLNR; vertical_stop = (tempreg & 0x7FF) + vertical_start - 1; LTDC_Layerx->WHPCR = horizontal_start | (horizontal_stop << 16); LTDC_Layerx->WVPCR = vertical_start | (vertical_stop << 16); } /** * @brief reconfigure constant alpha. * @param ConstantAlpha: constant alpha value. * @param LTDC_layerx: Select the layer to be configured, this parameter can be * one of the following values: LTDC_Layer1, LTDC_Layer2 * @retval Reload of the shadow registers values must be applied after constant * alpha reconfiguration. */ void LTDC_LayerAlpha(LTDC_Layer_TypeDef* LTDC_Layerx, uint8_t ConstantAlpha) { /* reconfigure the constant alpha value */ LTDC_Layerx->CACR = ConstantAlpha; } /** * @brief reconfigure layer address. * @param Address: The color frame buffer start address. * @param LTDC_layerx: Select the layer to be configured, this parameter can be * one of the following values: LTDC_Layer1, LTDC_Layer2 * @retval Reload of the shadow registers values must be applied after layer * address reconfiguration. */ void LTDC_LayerAddress(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Address) { /* Reconfigures the color frame buffer start address */ LTDC_Layerx->CFBAR = Address; } /** * @brief reconfigure layer size. * @param Width: layer window width. * @param Height: layer window height. * @param LTDC_layerx: Select the layer to be configured, this parameter can be * one of the following values: LTDC_Layer1, LTDC_Layer2 * @retval Reload of the shadow registers values must be applied after layer * size reconfiguration. */ void LTDC_LayerSize(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Width, uint32_t Height) { uint8_t temp; uint32_t tempreg; uint32_t horizontal_start; uint32_t horizontal_stop; uint32_t vertical_start; uint32_t vertical_stop; tempreg = LTDC_Layerx->PFCR; if (tempreg == LTDC_Pixelformat_ARGB8888) { temp = 4; } else if (tempreg == LTDC_Pixelformat_RGB888) { temp = 3; } else if ((tempreg == LTDC_Pixelformat_ARGB4444) || \ (tempreg == LTDC_Pixelformat_RGB565) || \ (tempreg == LTDC_Pixelformat_ARGB1555) || \ (tempreg == LTDC_Pixelformat_AL88)) { temp = 2; } else { temp = 1; } /* update horizontal and vertical stop */ tempreg = LTDC_Layerx->WHPCR; horizontal_start = (tempreg & 0x1FFF); horizontal_stop = Width + horizontal_start - 1; tempreg = LTDC_Layerx->WVPCR; vertical_start = (tempreg & 0x1FFF); vertical_stop = Height + vertical_start - 1; LTDC_Layerx->WHPCR = horizontal_start | (horizontal_stop << 16); LTDC_Layerx->WVPCR = vertical_start | (vertical_stop << 16); /* Reconfigures the color frame buffer pitch in byte */ LTDC_Layerx->CFBLR = ((Width * temp) << 16) | ((Width * temp) + 3); /* Reconfigures the frame buffer line number */ LTDC_Layerx->CFBLNR = Height; } /** * @brief reconfigure layer pixel format. * @param PixelFormat: reconfigure the pixel format, this parameter can be * one of the following values:@ref LTDC_Pixelformat. * @param LTDC_layerx: Select the layer to be configured, this parameter can be * one of the following values: LTDC_Layer1, LTDC_Layer2 * @retval Reload of the shadow registers values must be applied after layer * pixel format reconfiguration. */ void LTDC_LayerPixelFormat(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t PixelFormat) { uint8_t temp; uint32_t tempreg; tempreg = LTDC_Layerx->PFCR; if (tempreg == LTDC_Pixelformat_ARGB8888) { temp = 4; } else if (tempreg == LTDC_Pixelformat_RGB888) { temp = 3; } else if ((tempreg == LTDC_Pixelformat_ARGB4444) || \ (tempreg == LTDC_Pixelformat_RGB565) || \ (tempreg == LTDC_Pixelformat_ARGB1555) || \ (tempreg == LTDC_Pixelformat_AL88)) { temp = 2; } else { temp = 1; } tempreg = (LTDC_Layerx->CFBLR >> 16); tempreg = (tempreg / temp); if (PixelFormat == LTDC_Pixelformat_ARGB8888) { temp = 4; } else if (PixelFormat == LTDC_Pixelformat_RGB888) { temp = 3; } else if ((PixelFormat == LTDC_Pixelformat_ARGB4444) || \ (PixelFormat == LTDC_Pixelformat_RGB565) || \ (PixelFormat == LTDC_Pixelformat_ARGB1555) || \ (PixelFormat == LTDC_Pixelformat_AL88)) { temp = 2; } else { temp = 1; } /* Reconfigures the color frame buffer pitch in byte */ LTDC_Layerx->CFBLR = ((tempreg * temp) << 16) | ((tempreg * temp) + 3); /* Reconfigures the color frame buffer start address */ LTDC_Layerx->PFCR = PixelFormat; } /** * @} */ /** @defgroup LTDC_Group2 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== [..] This section provides functions allowing to configure the LTDC Interrupts and to get the status and clear flags and Interrupts pending bits. [..] The LTDC provides 4 Interrupts sources and 4 Flags *** Flags *** ============= [..] (+) LTDC_FLAG_LI: Line Interrupt flag. (+) LTDC_FLAG_FU: FIFO Underrun Interrupt flag. (+) LTDC_FLAG_TERR: Transfer Error Interrupt flag. (+) LTDC_FLAG_RR: Register Reload interrupt flag. *** Interrupts *** ================== [..] (+) LTDC_IT_LI: Line Interrupt is generated when a programmed line is reached. The line interrupt position is programmed in the LTDC_LIPR register. (+) LTDC_IT_FU: FIFO Underrun interrupt is generated when a pixel is requested from an empty layer FIFO (+) LTDC_IT_TERR: Transfer Error interrupt is generated when an AHB bus error occurs during data transfer. (+) LTDC_IT_RR: Register Reload interrupt is generated when the shadow registers reload was performed during the vertical blanking period. @endverbatim * @{ */ /** * @brief Enables or disables the specified LTDC's interrupts. * @param LTDC_IT: specifies the LTDC interrupts sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg LTDC_IT_LI: Line Interrupt Enable. * @arg LTDC_IT_FU: FIFO Underrun Interrupt Enable. * @arg LTDC_IT_TERR: Transfer Error Interrupt Enable. * @arg LTDC_IT_RR: Register Reload interrupt enable. * @param NewState: new state of the specified LTDC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void LTDC_ITConfig(uint32_t LTDC_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_LTDC_IT(LTDC_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { LTDC->IER |= LTDC_IT; } else { LTDC->IER &= (uint32_t)~LTDC_IT; } } /** * @brief Checks whether the specified LTDC's flag is set or not. * @param LTDC_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg LTDC_FLAG_LI: Line Interrupt flag. * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag. * @arg LTDC_FLAG_TERR: Transfer Error Interrupt flag. * @arg LTDC_FLAG_RR: Register Reload interrupt flag. * @retval The new state of LTDC_FLAG (SET or RESET). */ FlagStatus LTDC_GetFlagStatus(uint32_t LTDC_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_LTDC_FLAG(LTDC_FLAG)); if ((LTDC->ISR & LTDC_FLAG) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the LTDC's pending flags. * @param LTDC_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg LTDC_FLAG_LI: Line Interrupt flag. * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag. * @arg LTDC_FLAG_TERR: Transfer Error Interrupt flag. * @arg LTDC_FLAG_RR: Register Reload interrupt flag. * @retval None */ void LTDC_ClearFlag(uint32_t LTDC_FLAG) { /* Check the parameters */ assert_param(IS_LTDC_FLAG(LTDC_FLAG)); /* Clear the corresponding LTDC flag */ LTDC->ICR = (uint32_t)LTDC_FLAG; } /** * @brief Checks whether the specified LTDC's interrupt has occurred or not. * @param LTDC_IT: specifies the LTDC interrupts sources to check. * This parameter can be one of the following values: * @arg LTDC_IT_LI: Line Interrupt Enable. * @arg LTDC_IT_FU: FIFO Underrun Interrupt Enable. * @arg LTDC_IT_TERR: Transfer Error Interrupt Enable. * @arg LTDC_IT_RR: Register Reload interrupt Enable. * @retval The new state of the LTDC_IT (SET or RESET). */ ITStatus LTDC_GetITStatus(uint32_t LTDC_IT) { ITStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_LTDC_IT(LTDC_IT)); if ((LTDC->ISR & LTDC_IT) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } if (((LTDC->IER & LTDC_IT) != (uint32_t)RESET) && (bitstatus != (uint32_t)RESET)) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the LTDC's interrupt pending bits. * @param LTDC_IT: specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg LTDC_IT_LIE: Line Interrupt. * @arg LTDC_IT_FUIE: FIFO Underrun Interrupt. * @arg LTDC_IT_TERRIE: Transfer Error Interrupt. * @arg LTDC_IT_RRIE: Register Reload interrupt. * @retval None */ void LTDC_ClearITPendingBit(uint32_t LTDC_IT) { /* Check the parameters */ assert_param(IS_LTDC_IT(LTDC_IT)); /* Clear the corresponding LTDC Interrupt */ LTDC->ICR = (uint32_t)LTDC_IT; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c ================================================ /** ****************************************************************************** * @file stm32f4xx_pwr.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: * + Backup Domain Access * + PVD configuration * + WakeUp pin configuration * + Main and Backup Regulators configuration * + FLASH Power Down configuration * + Low Power modes configuration * + Flags management * ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_pwr.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup PWR * @brief PWR driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* --------- PWR registers bit address in the alias region ---------- */ #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) /* --- CR Register ---*/ /* Alias word address of DBP bit */ #define CR_OFFSET (PWR_OFFSET + 0x00) #define DBP_BitNumber 0x08 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) /* Alias word address of PVDE bit */ #define PVDE_BitNumber 0x04 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) /* Alias word address of FPDS bit */ #define FPDS_BitNumber 0x09 #define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4)) /* Alias word address of PMODE bit */ #define PMODE_BitNumber 0x0E #define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4)) /* Alias word address of ODEN bit */ #define ODEN_BitNumber 0x10 #define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4)) /* Alias word address of ODSWEN bit */ #define ODSWEN_BitNumber 0x11 #define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4)) /* --- CSR Register ---*/ /* Alias word address of EWUP bit */ #define CSR_OFFSET (PWR_OFFSET + 0x04) #define EWUP_BitNumber 0x08 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) /* Alias word address of BRE bit */ #define BRE_BitNumber 0x09 #define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4)) /* ------------------ PWR registers bit mask ------------------------ */ /* CR register bit mask */ #define CR_DS_MASK ((uint32_t)0xFFFFF3FC) #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) #define CR_VOS_MASK ((uint32_t)0xFFFF3FFF) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup PWR_Private_Functions * @{ */ /** @defgroup PWR_Group1 Backup Domain Access function * @brief Backup Domain Access function * @verbatim =============================================================================== ##### Backup Domain Access function ##### =============================================================================== [..] After reset, the backup domain (RTC registers, RTC backup data registers and backup SRAM) is protected against possible unwanted write accesses. To enable access to the RTC Domain and RTC registers, proceed as follows: (+) Enable the Power Controller (PWR) APB1 interface clock using the RCC_APB1PeriphClockCmd() function. (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function. @endverbatim * @{ */ /** * @brief Deinitializes the PWR peripheral registers to their default reset values. * @param None * @retval None */ void PWR_DeInit(void) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); } /** * @brief Enables or disables access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the * Backup Domain Access should be kept enabled. * @param NewState: new state of the access to the backup domain. * This parameter can be: ENABLE or DISABLE. * @retval None */ void PWR_BackupAccessCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; } /** * @} */ /** @defgroup PWR_Group2 PVD configuration functions * @brief PVD configuration functions * @verbatim =============================================================================== ##### PVD configuration functions ##### =============================================================================== [..] (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. (+) The PVD is stopped in Standby mode. @endverbatim * @{ */ /** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). * @param PWR_PVDLevel: specifies the PVD detection level * This parameter can be one of the following values: * @arg PWR_PVDLevel_0 * @arg PWR_PVDLevel_1 * @arg PWR_PVDLevel_2 * @arg PWR_PVDLevel_3 * @arg PWR_PVDLevel_4 * @arg PWR_PVDLevel_5 * @arg PWR_PVDLevel_6 * @arg PWR_PVDLevel_7 * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage threshold corresponding to each * detection level. * @retval None */ void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); tmpreg = PWR->CR; /* Clear PLS[7:5] bits */ tmpreg &= CR_PLS_MASK; /* Set PLS[7:5] bits according to PWR_PVDLevel value */ tmpreg |= PWR_PVDLevel; /* Store the new value */ PWR->CR = tmpreg; } /** * @brief Enables or disables the Power Voltage Detector(PVD). * @param NewState: new state of the PVD. * This parameter can be: ENABLE or DISABLE. * @retval None */ void PWR_PVDCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; } /** * @} */ /** @defgroup PWR_Group3 WakeUp pin configuration functions * @brief WakeUp pin configuration functions * @verbatim =============================================================================== ##### WakeUp pin configuration functions ##### =============================================================================== [..] (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is forced in input pull down configuration and is active on rising edges. (+) There is only one WakeUp pin: WakeUp Pin 1 on PA.00. @endverbatim * @{ */ /** * @brief Enables or disables the WakeUp Pin functionality. * @param NewState: new state of the WakeUp Pin functionality. * This parameter can be: ENABLE or DISABLE. * @retval None */ void PWR_WakeUpPinCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; } /** * @} */ /** @defgroup PWR_Group4 Main and Backup Regulators configuration functions * @brief Main and Backup Regulators configuration functions * @verbatim =============================================================================== ##### Main and Backup Regulators configuration functions ##### =============================================================================== [..] (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained even in Standby or VBAT mode when the low power backup regulator is enabled. It can be considered as an internal EEPROM when VBAT is always present. You can use the PWR_BackupRegulatorCmd() function to enable the low power backup regulator and use the PWR_GetFlagStatus (PWR_FLAG_BRR) to check if it is ready or not. (+) When the backup domain is supplied by VDD (analog switch connected to VDD) the backup SRAM is powered from VDD which replaces the VBAT power supply to save battery life. (+) The backup SRAM is not mass erased by an tamper event. It is read protected to prevent confidential data, such as cryptographic private key, from being accessed. The backup SRAM can be erased only through the Flash interface when a protection level change from level 1 to level 0 is requested. -@- Refer to the description of Read protection (RDP) in the reference manual. (+) The main internal regulator can be configured to have a tradeoff between performance and power consumption when the device does not operate at the maximum frequency. (+) For STM32F405xx/407xx and STM32F415xx/417xx Devices, the regulator can be configured on the fly through PWR_MainRegulatorModeConfig() function which configure VOS bit in PWR_CR register: (++) When this bit is set (Regulator voltage output Scale 1 mode selected) the System frequency can go up to 168 MHz. (++) When this bit is reset (Regulator voltage output Scale 2 mode selected) the System frequency can go up to 144 MHz. (+) For STM32F42xxx/43xxx Devices, the regulator can be configured through PWR_MainRegulatorModeConfig() function which configure VOS[1:0] bits in PWR_CR register: which configure VOS[1:0] bits in PWR_CR register: (++) When VOS[1:0] = 11 (Regulator voltage output Scale 1 mode selected) the System frequency can go up to 168 MHz. (++) When VOS[1:0] = 10 (Regulator voltage output Scale 2 mode selected) the System frequency can go up to 144 MHz. (++) When VOS[1:0] = 01 (Regulator voltage output Scale 3 mode selected) the System frequency can go up to 120 MHz. (+) For STM32F42xxx/43xxx Devices, the scale can be modified only when the PLL is OFF and the HSI or HSE clock source is selected as system clock. The new value programmed is active only when the PLL is ON. When the PLL is OFF, the voltage scale 3 is automatically selected. Refer to the datasheets for more details. (+) For STM32F42xxx/43xxx Devices, in Run mode: the main regulator has 2 operating modes available: (++) Normal mode: The CPU and core logic operate at maximum frequency at a given voltage scaling (scale 1, scale 2 or scale 3) (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a higher frequency than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). This mode is enabled through PWR_OverDriveCmd() function and PWR_OverDriveSWCmd() function, to enter or exit from Over-drive mode please follow the sequence described in Reference manual. (+) For STM32F42xxx/43xxx Devices, in Stop mode: the main regulator or low power regulator supplies a low power voltage to the 1.2V domain, thus preserving the content of registers and internal SRAM. 2 operating modes are available: (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only available when the main regulator or the low power regulator is used in Scale 3 or low voltage mode. (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only available when the main regulator or the low power regulator is in low voltage mode. This mode is enabled through PWR_UnderDriveCmd() function. @endverbatim * @{ */ /** * @brief Enables or disables the Backup Regulator. * @param NewState: new state of the Backup Regulator. * This parameter can be: ENABLE or DISABLE. * @retval None */ void PWR_BackupRegulatorCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState; } /** * @brief Configures the main internal regulator output voltage. * @param PWR_Regulator_Voltage: specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption when the device does * not operate at the maximum frequency (refer to the datasheets for more details). * This parameter can be one of the following values: * @arg PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode, * System frequency up to 168 MHz. * @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode, * System frequency up to 144 MHz. * @arg PWR_Regulator_Voltage_Scale3: Regulator voltage output Scale 3 mode, * System frequency up to 120 MHz (only for STM32F42xxx/43xxx devices) * @retval None */ void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage)); tmpreg = PWR->CR; /* Clear VOS[15:14] bits */ tmpreg &= CR_VOS_MASK; /* Set VOS[15:14] bits according to PWR_Regulator_Voltage value */ tmpreg |= PWR_Regulator_Voltage; /* Store the new value */ PWR->CR = tmpreg; } /** * @brief Enables or disables the Over-Drive. * * @note This function can be used only for STM32F42xxx/STM3243xxx devices. * This mode allows the CPU and the core logic to operate at a higher frequency * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). * * @note It is recommended to enter or exit Over-drive mode when the application is not running * critical tasks and when the system clock source is either HSI or HSE. * During the Over-drive switch activation, no peripheral clocks should be enabled. * The peripheral clocks must be enabled once the Over-drive mode is activated. * * @param NewState: new state of the Over Drive mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void PWR_OverDriveCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Set/Reset the ODEN bit to enable/disable the Over Drive mode */ *(__IO uint32_t *) CR_ODEN_BB = (uint32_t)NewState; } /** * @brief Enables or disables the Over-Drive switching. * * @note This function can be used only for STM32F42xxx/STM3243xxx devices. * * @param NewState: new state of the Over Drive switching mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void PWR_OverDriveSWCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Set/Reset the ODSWEN bit to enable/disable the Over Drive switching mode */ *(__IO uint32_t *) CR_ODSWEN_BB = (uint32_t)NewState; } /** * @brief Enables or disables the Under-Drive mode. * * @note This function can be used only for STM32F42xxx/STM3243xxx devices. * @note This mode is enabled only with STOP low power mode. * In this mode, the 1.2V domain is preserved in reduced leakage mode. This * mode is only available when the main regulator or the low power regulator * is in low voltage mode * * @note If the Under-drive mode was enabled, it is automatically disabled after * exiting Stop mode. * When the voltage regulator operates in Under-drive mode, an additional * startup delay is induced when waking up from Stop mode. * * @param NewState: new state of the Under Drive mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void PWR_UnderDriveCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set the UDEN[1:0] bits to enable the Under Drive mode */ PWR->CR |= (uint32_t)PWR_CR_UDEN; } else { /* Reset the UDEN[1:0] bits to disable the Under Drive mode */ PWR->CR &= (uint32_t)(~PWR_CR_UDEN); } } /** * @} */ /** @defgroup PWR_Group5 FLASH Power Down configuration functions * @brief FLASH Power Down configuration functions * @verbatim =============================================================================== ##### FLASH Power Down configuration functions ##### =============================================================================== [..] (+) By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd() function, the Flash memory also enters power down mode when the device enters Stop mode. When the Flash memory is in power down mode, an additional startup delay is incurred when waking up from Stop mode. @endverbatim * @{ */ /** * @brief Enables or disables the Flash Power Down in STOP mode. * @param NewState: new state of the Flash power mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void PWR_FlashPowerDownCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState; } /** * @} */ /** @defgroup PWR_Group6 Low Power modes configuration functions * @brief Low Power modes configuration functions * @verbatim =============================================================================== ##### Low Power modes configuration functions ##### =============================================================================== [..] The devices feature 3 low-power modes: (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode (+) Standby mode: 1.2V domain powered off. *** Sleep mode *** ================== [..] (+) Entry: (++) The Sleep mode is entered by using the __WFI() or __WFE() functions. (+) Exit: (++) Any peripheral interrupt acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode. *** Stop mode *** ================= [..] In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, and the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved. The voltage regulator can be configured either in normal or low-power mode. To minimize the consumption In Stop mode, FLASH can be powered off before entering the Stop mode. It can be switched on again by software after exiting the Stop mode using the PWR_FlashPowerDownCmd() function. (+) Entry: (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_MainRegulator_ON) function with: (+++) Main regulator ON. (+++) Low Power regulator ON. (+) Exit: (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. *** Standby mode *** ==================== [..] The Standby mode allows to achieve the lowest power consumption. It is based on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for the RTC registers, RTC backup registers, backup SRAM and Standby circuitry. The voltage regulator is OFF. (+) Entry: (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function. (+) Exit: (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, tamper event, time-stamp event, external reset in NRST pin, IWDG reset. *** Auto-wakeup (AWU) from low-power mode *** ============================================= [..] The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC Wakeup event, a tamper event, a time-stamp event, or a comparator event, without depending on an external interrupt (Auto-wakeup mode). (#) RTC auto-wakeup (AWU) from the Stop mode (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to: (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event modes) using the EXTI_Init() function. (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() and RTC_AlarmCmd() functions. (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it is necessary to: (+++) Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt or Event modes) using the EXTI_Init() function. (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() function (+++) Configure the RTC to detect the tamper or time stamp event using the RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: (+++) Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt or Event modes) using the EXTI_Init() function. (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. (#) RTC auto-wakeup (AWU) from the Standby mode (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to: (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() and RTC_AlarmCmd() functions. (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it is necessary to: (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() function (+++) Configure the RTC to detect the tamper or time stamp event using the RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. @endverbatim * @{ */ /** * @brief Enters STOP mode. * * @note In Stop mode, all I/O pins keep the same state as in Run mode. * @note When exiting Stop mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock. * @note When the voltage regulator operates in low power mode, an additional * startup delay is incurred when waking up from Stop mode. * By keeping the internal regulator ON during Stop mode, the consumption * is higher although the startup time is reduced. * * @param PWR_Regulator: specifies the regulator state in STOP mode. * This parameter can be one of the following values: * @arg PWR_MainRegulator_ON: STOP mode with regulator ON * @arg PWR_LowPowerRegulator_ON: STOP mode with low power regulator ON * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction * @retval None */ void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_PWR_REGULATOR(PWR_Regulator)); assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); /* Select the regulator state in STOP mode ---------------------------------*/ tmpreg = PWR->CR; /* Clear PDDS and LPDS bits */ tmpreg &= CR_DS_MASK; /* Set LPDS, MRLVDS and LPLVDS bits according to PWR_Regulator value */ tmpreg |= PWR_Regulator; /* Store the new value */ PWR->CR = tmpreg; /* Set SLEEPDEEP bit of Cortex System Control Register */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /* Select STOP mode entry --------------------------------------------------*/ if(PWR_STOPEntry == PWR_STOPEntry_WFI) { /* Request Wait For Interrupt */ __WFI(); } else { /* Request Wait For Event */ __WFE(); } /* Reset SLEEPDEEP bit of Cortex System Control Register */ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); } /** * @brief Enters in Under-Drive STOP mode. * * @note This mode is only available for STM32F42xxx/STM3243xxx devices. * * @note This mode can be selected only when the Under-Drive is already active * * @note In Stop mode, all I/O pins keep the same state as in Run mode. * @note When exiting Stop mode by issuing an interrupt or a wakeup event, * the HSI RC oscillator is selected as system clock. * @note When the voltage regulator operates in low power mode, an additional * startup delay is incurred when waking up from Stop mode. * By keeping the internal regulator ON during Stop mode, the consumption * is higher although the startup time is reduced. * * @param PWR_Regulator: specifies the regulator state in STOP mode. * This parameter can be one of the following values: * @arg PWR_MainRegulator_UnderDrive_ON: Main Regulator in under-drive mode * and Flash memory in power-down when the device is in Stop under-drive mode * @arg PWR_LowPowerRegulator_UnderDrive_ON: Low Power Regulator in under-drive mode * and Flash memory in power-down when the device is in Stop under-drive mode * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction * @retval None */ void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_PWR_REGULATOR_UNDERDRIVE(PWR_Regulator)); assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); /* Select the regulator state in STOP mode ---------------------------------*/ tmpreg = PWR->CR; /* Clear PDDS and LPDS bits */ tmpreg &= CR_DS_MASK; /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ tmpreg |= PWR_Regulator; /* Store the new value */ PWR->CR = tmpreg; /* Set SLEEPDEEP bit of Cortex System Control Register */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /* Select STOP mode entry --------------------------------------------------*/ if(PWR_STOPEntry == PWR_STOPEntry_WFI) { /* Request Wait For Interrupt */ __WFI(); } else { /* Request Wait For Event */ __WFE(); } /* Reset SLEEPDEEP bit of Cortex System Control Register */ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); } /** * @brief Enters STANDBY mode. * @note In Standby mode, all I/O pins are high impedance except for: * - Reset pad (still available) * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC * Alarm out, or RTC clock calibration out. * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. * - WKUP pin 1 (PA0) if enabled. * @param None * @retval None */ void PWR_EnterSTANDBYMode(void) { /* Clear Wakeup flag */ PWR->CR |= PWR_CR_CWUF; /* Select STANDBY mode */ PWR->CR |= PWR_CR_PDDS; /* Set SLEEPDEEP bit of Cortex System Control Register */ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; /* This option is used to ensure that store operations are completed */ #if defined ( __CC_ARM ) __force_stores(); #endif /* Request Wait For Interrupt */ __WFI(); } /** * @} */ /** @defgroup PWR_Group7 Flags management functions * @brief Flags management functions * @verbatim =============================================================================== ##### Flags management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Checks whether the specified PWR flag is set or not. * @param PWR_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event * was received from the WKUP pin or from the RTC alarm (Alarm A * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. * An additional wakeup event is detected if the WKUP pin is enabled * (by setting the EWUP bit) when the WKUP pin level is already high. * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was * resumed from StandBy mode. * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode * For this reason, this bit is equal to 0 after Standby or reset * until the PVDE bit is set. * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset * when the device wakes up from Standby mode or by a system reset * or power reset. * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage * scaling output selection is ready. * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode * is ready (STM32F42xxx/43xxx devices) * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode * switcching is ready (STM32F42xxx/43xxx devices) * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode * is enabled in Stop mode (STM32F42xxx/43xxx devices) * @retval The new state of PWR_FLAG (SET or RESET). */ FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } /* Return the flag status */ return bitstatus; } /** * @brief Clears the PWR's pending flags. * @param PWR_FLAG: specifies the flag to clear. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag * @arg PWR_FLAG_SB: StandBy flag * @arg PWR_FLAG_UDRDY: Under-drive ready flag (STM32F42xxx/43xxx devices) * @retval None */ void PWR_ClearFlag(uint32_t PWR_FLAG) { /* Check the parameters */ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); #if defined (STM32F427_437xx) || defined (STM32F429_439xx) if (PWR_FLAG != PWR_FLAG_UDRDY) { PWR->CR |= PWR_FLAG << 2; } else { PWR->CSR |= PWR_FLAG_UDRDY; } #endif /* STM32F427_437xx || STM32F429_439xx */ #if defined (STM32F40_41xxx) || defined (STM32F401xx) PWR->CR |= PWR_FLAG << 2; #endif /* STM32F40_41xxx */ } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c ================================================ /** ****************************************************************************** * @file stm32f4xx_rcc.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Reset and clock control (RCC) peripheral: * + Internal/external clocks, PLL, CSS and MCO configuration * + System, AHB and APB busses clocks configuration * + Peripheral clocks configuration * + Interrupts and flags management * @verbatim =============================================================================== ##### RCC specific features ##### =============================================================================== [..] After reset the device is running from Internal High Speed oscillator (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache and I-Cache are disabled, and all peripherals are off except internal SRAM, Flash and JTAG. (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; all peripherals mapped on these busses are running at HSI speed. (+) The clock for all peripherals is switched off, except the SRAM and FLASH. (+) All GPIOs are in input floating state, except the JTAG pins which are assigned to be used for debug purpose. [..] Once the device started from reset, the user application has to: (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) (+) Configure the System clock frequency and Flash settings (+) Configure the AHB and APB busses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals which clocks are not derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup RCC * @brief RCC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* ------------ RCC registers bit address in the alias region ----------- */ #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) /* --- CR Register ---*/ /* Alias word address of HSION bit */ #define CR_OFFSET (RCC_OFFSET + 0x00) #define HSION_BitNumber 0x00 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) /* Alias word address of CSSON bit */ #define CSSON_BitNumber 0x13 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) /* Alias word address of PLLON bit */ #define PLLON_BitNumber 0x18 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) /* Alias word address of PLLI2SON bit */ #define PLLI2SON_BitNumber 0x1A #define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) /* Alias word address of PLLSAION bit */ #define PLLSAION_BitNumber 0x1C #define CR_PLLSAION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4)) /* --- CFGR Register ---*/ /* Alias word address of I2SSRC bit */ #define CFGR_OFFSET (RCC_OFFSET + 0x08) #define I2SSRC_BitNumber 0x17 #define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) /* --- BDCR Register ---*/ /* Alias word address of RTCEN bit */ #define BDCR_OFFSET (RCC_OFFSET + 0x70) #define RTCEN_BitNumber 0x0F #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) /* Alias word address of BDRST bit */ #define BDRST_BitNumber 0x10 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) /* --- CSR Register ---*/ /* Alias word address of LSION bit */ #define CSR_OFFSET (RCC_OFFSET + 0x74) #define LSION_BitNumber 0x00 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) /* --- DCKCFGR Register ---*/ /* Alias word address of TIMPRE bit */ #define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C) #define TIMPRE_BitNumber 0x18 #define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4)) /* ---------------------- RCC registers bit mask ------------------------ */ /* CFGR register bit mask */ #define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) #define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF) /* RCC Flag Mask */ #define FLAG_MASK ((uint8_t)0x1F) /* CR register byte 3 (Bits[23:16]) base address */ #define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) /* CIR register byte 2 (Bits[15:8]) base address */ #define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) /* CIR register byte 3 (Bits[23:16]) base address */ #define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) /* BDCR register base address */ #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup RCC_Private_Functions * @{ */ /** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions * @brief Internal and external clocks, PLL, CSS and MCO configuration functions * @verbatim =================================================================================== ##### Internal and external clocks, PLL, CSS and MCO configuration functions ##### =================================================================================== [..] This section provide functions allowing to configure the internal/external clocks, PLLs, CSS and MCO pins. (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through the PLL as System clock source. (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC clock source. (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or through the PLL as System clock source. Can be used also as RTC clock source. (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. (#) PLL (clocked by HSI or HSE), featuring two different output clocks: (++) The first output is used to generate the high speed system clock (up to 168 MHz) (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve high-quality audio performance on the I2S interface or SAI interface in case of STM32F429x/439x devices. (#) PLLSAI clocked by (HSI or HSE), used to generate an accurate clock to SAI interface and LCD TFT controller available only for STM32F42xxx/43xxx devices. (#) CSS (Clock security system), once enable and if a HSE clock failure occurs (HSE used directly or through PLL as System clock source), the System clock is automatically switched to HSI and an interrupt is generated if enabled. The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL clock (through a configurable prescaler) on PA8 pin. (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S clock (through a configurable prescaler) on PC9 pin. @endverbatim * @{ */ /** * @brief Resets the RCC clock configuration to the default reset state. * @note The default reset state of the clock configuration is given below: * - HSI ON and used as system clock source * - HSE, PLL and PLLI2S OFF * - AHB, APB1 and APB2 prescaler set to 1. * - CSS, MCO1 and MCO2 OFF * - All interrupts disabled * @note This function doesn't modify the configuration of the * - Peripheral clocks * - LSI, LSE and RTC clocks * @param None * @retval None */ void RCC_DeInit(void) { /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; /* Reset CFGR register */ RCC->CFGR = 0x00000000; /* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42/43xxx devices) bits */ RCC->CR &= (uint32_t)0xEAF6FFFF; /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x24003010; /* Reset PLLI2SCFGR register */ RCC->PLLI2SCFGR = 0x20003000; /* Reset PLLSAICFGR register, only available for STM32F42/43xxx devices */ RCC->PLLSAICFGR = 0x24003000; /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; /* Disable all interrupts */ RCC->CIR = 0x00000000; /* Disable Timers clock prescalers selection, only available for STM32F42/43xxx devices */ RCC->DCKCFGR = 0x00000000; } /** * @brief Configures the External High Speed oscillator (HSE). * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application * software should wait on HSERDY flag to be set indicating that HSE clock * is stable and can be used to clock the PLL and/or system clock. * @note HSE state can not be changed if it is used directly or through the * PLL as system clock. In this case, you have to select another source * of the system clock then change the HSE state (ex. disable it). * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. * @note This function reset the CSSON bit, so if the Clock security system(CSS) * was previously enabled you have to enable it again after calling this * function. * @param RCC_HSE: specifies the new state of the HSE. * This parameter can be one of the following values: * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after * 6 HSE oscillator clock cycles. * @arg RCC_HSE_ON: turn ON the HSE oscillator * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock * @retval None */ void RCC_HSEConfig(uint8_t RCC_HSE) { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_HSE)); /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF; /* Set the new HSE configuration -------------------------------------------*/ *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE; } /** * @brief Waits for HSE start-up. * @note This functions waits on HSERDY flag to be set and return SUCCESS if * this flag is set, otherwise returns ERROR if the timeout is reached * and this flag is not set. The timeout value is defined by the constant * HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending * on the HSE crystal used in your application. * @param None * @retval An ErrorStatus enumeration value: * - SUCCESS: HSE oscillator is stable and ready to use * - ERROR: HSE oscillator not yet ready */ ErrorStatus RCC_WaitForHSEStartUp(void) { __IO uint32_t startupcounter = 0; ErrorStatus status = ERROR; FlagStatus hsestatus = RESET; /* Wait till HSE is ready and if Time out is reached exit */ do { hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); startupcounter++; } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET)); if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) { status = SUCCESS; } else { status = ERROR; } return (status); } /** * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal HSI RC. * @param HSICalibrationValue: specifies the calibration trimming value. * This parameter must be a number between 0 and 0x1F. * @retval None */ void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); tmpreg = RCC->CR; /* Clear HSITRIM[4:0] bits */ tmpreg &= ~RCC_CR_HSITRIM; /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ tmpreg |= (uint32_t)HSICalibrationValue << 3; /* Store the new value */ RCC->CR = tmpreg; } /** * @brief Enables or disables the Internal High Speed oscillator (HSI). * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. * It is used (enabled by hardware) as system clock source after startup * from Reset, wakeup from STOP and STANDBY mode, or in case of failure * of the HSE used directly or indirectly as system clock (if the Clock * Security System CSS is enabled). * @note HSI can not be stopped if it is used as system clock source. In this case, * you have to select another source of the system clock then stop the HSI. * @note After enabling the HSI, the application software should wait on HSIRDY * flag to be set indicating that HSI clock is stable and can be used as * system clock source. * @param NewState: new state of the HSI. * This parameter can be: ENABLE or DISABLE. * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator * clock cycles. * @retval None */ void RCC_HSICmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; } /** * @brief Configures the External Low Speed oscillator (LSE). * @note As the LSE is in the Backup domain and write access is denied to * this domain after reset, you have to enable write access using * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE * (to be done once after reset). * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application * software should wait on LSERDY flag to be set indicating that LSE clock * is stable and can be used to clock the RTC. * @param RCC_LSE: specifies the new state of the LSE. * This parameter can be one of the following values: * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. * @arg RCC_LSE_ON: turn ON the LSE oscillator * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock * @retval None */ void RCC_LSEConfig(uint8_t RCC_LSE) { /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_LSE)); /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ /* Reset LSEON bit */ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; /* Reset LSEBYP bit */ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ switch (RCC_LSE) { case RCC_LSE_ON: /* Set LSEON bit */ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; break; case RCC_LSE_Bypass: /* Set LSEBYP and LSEON bits */ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; break; default: break; } } /** * @brief Enables or disables the Internal Low Speed oscillator (LSI). * @note After enabling the LSI, the application software should wait on * LSIRDY flag to be set indicating that LSI clock is stable and can * be used to clock the IWDG and/or the RTC. * @note LSI can not be disabled if the IWDG is running. * @param NewState: new state of the LSI. * This parameter can be: ENABLE or DISABLE. * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator * clock cycles. * @retval None */ void RCC_LSICmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; } /** * @brief Configures the main PLL clock source, multiplication and division factors. * @note This function must be used only when the main PLL is disabled. * * @param RCC_PLLSource: specifies the PLL entry clock source. * This parameter can be one of the following values: * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. * * @param PLLM: specifies the division factor for PLL VCO input clock * This parameter must be a number between 0 and 63. * @note You have to set the PLLM parameter correctly to ensure that the VCO input * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency * of 2 MHz to limit PLL jitter. * * @param PLLN: specifies the multiplication factor for PLL VCO output clock * This parameter must be a number between 192 and 432. * @note You have to set the PLLN parameter correctly to ensure that the VCO * output frequency is between 192 and 432 MHz. * * @param PLLP: specifies the division factor for main system clock (SYSCLK) * This parameter must be a number in the range {2, 4, 6, or 8}. * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on * the System clock frequency. * * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks * This parameter must be a number between 4 and 15. * @note If the USB OTG FS is used in your application, you have to set the * PLLQ parameter correctly to have 48 MHz clock for the USB. However, * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work * correctly. * * @retval None */ void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ) { /* Check the parameters */ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); assert_param(IS_RCC_PLLM_VALUE(PLLM)); assert_param(IS_RCC_PLLN_VALUE(PLLN)); assert_param(IS_RCC_PLLP_VALUE(PLLP)); assert_param(IS_RCC_PLLQ_VALUE(PLLQ)); RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) | (PLLQ << 24); } /** * @brief Enables or disables the main PLL. * @note After enabling the main PLL, the application software should wait on * PLLRDY flag to be set indicating that PLL clock is stable and can * be used as system clock source. * @note The main PLL can not be disabled if it is used as system clock source * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_PLLCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; } #if defined (STM32F40_41xxx) || defined (STM32F401xx) /** * @brief Configures the PLLI2S clock multiplication and division factors. * * @note This function can be used only for STM32F405xx/407xx, STM32F415xx/417xx * or STM32F401xx devices. * * @note This function must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * RCC_PLLConfig function ) * * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock * This parameter must be a number between 192 and 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between 192 and 432 MHz. * * @param PLLI2SR: specifies the division factor for I2S clock * This parameter must be a number between 2 and 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. * * @retval None */ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR) { /* Check the parameters */ assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28); } #endif /* STM32F40_41xxx || STM32F401xx */ #if defined (STM32F427_437xx) || defined (STM32F429_439xx) /** * @brief Configures the PLLI2S clock multiplication and division factors. * * @note This function can be used only for STM32F42xxx/43xxx devices * * @note This function must be used only when the PLLI2S is disabled. * @note PLLI2S clock source is common with the main PLL (configured in * RCC_PLLConfig function ) * * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock * This parameter must be a number between 192 and 432. * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO * output frequency is between 192 and 432 MHz. * * @param PLLI2SQ: specifies the division factor for SAI1 clock * This parameter must be a number between 2 and 15. * * @param PLLI2SR: specifies the division factor for I2S clock * This parameter must be a number between 2 and 7. * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. * @note the PLLI2SR parameter is only available with STM32F42xxx/43xxx devices. * * @retval None */ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR) { /* Check the parameters */ assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ)); assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SQ << 24) | (PLLI2SR << 28); } #endif /* STM32F427_437xx || STM32F429_439xx */ /** * @brief Enables or disables the PLLI2S. * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_PLLI2SCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState; } /** * @brief Configures the PLLSAI clock multiplication and division factors. * * @note This function can be used only for STM32F42xxx/43xxx devices * * @note This function must be used only when the PLLSAI is disabled. * @note PLLSAI clock source is common with the main PLL (configured in * RCC_PLLConfig function ) * * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock * This parameter must be a number between 192 and 432. * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO * output frequency is between 192 and 432 MHz. * * @param PLLSAIQ: specifies the division factor for SAI1 clock * This parameter must be a number between 2 and 15. * * @param PLLSAIR: specifies the division factor for LTDC clock * This parameter must be a number between 2 and 7. * * @retval None */ void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR) { /* Check the parameters */ assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN)); assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR)); RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIQ << 24) | (PLLSAIR << 28); } /** * @brief Enables or disables the PLLSAI. * * @note This function can be used only for STM32F42xxx/43xxx devices * * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. * @param NewState: new state of the PLLSAI. This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_PLLSAICmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_PLLSAION_BB = (uint32_t)NewState; } /** * @brief Enables or disables the Clock Security System. * @note If a failure is detected on the HSE oscillator clock, this oscillator * is automatically disabled and an interrupt is generated to inform the * software about the failure (Clock Security System Interrupt, CSSI), * allowing the MCU to perform rescue operations. The CSSI is linked to * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. * @param NewState: new state of the Clock Security System. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_ClockSecuritySystemCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; } /** * @brief Selects the clock source to output on MCO1 pin(PA8). * @note PA8 should be configured in alternate function mode. * @param RCC_MCO1Source: specifies the clock source to output. * This parameter can be one of the following values: * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source * @param RCC_MCO1Div: specifies the MCO1 prescaler. * This parameter can be one of the following values: * @arg RCC_MCO1Div_1: no division applied to MCO1 clock * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock * @retval None */ void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source)); assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div)); tmpreg = RCC->CFGR; /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */ tmpreg &= CFGR_MCO1_RESET_MASK; /* Select MCO1 clock source and prescaler */ tmpreg |= RCC_MCO1Source | RCC_MCO1Div; /* Store the new value */ RCC->CFGR = tmpreg; } /** * @brief Selects the clock source to output on MCO2 pin(PC9). * @note PC9 should be configured in alternate function mode. * @param RCC_MCO2Source: specifies the clock source to output. * This parameter can be one of the following values: * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source * @param RCC_MCO2Div: specifies the MCO2 prescaler. * This parameter can be one of the following values: * @arg RCC_MCO2Div_1: no division applied to MCO2 clock * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock * @retval None */ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source)); assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div)); tmpreg = RCC->CFGR; /* Clear MCO2 and MCO2PRE[2:0] bits */ tmpreg &= CFGR_MCO2_RESET_MASK; /* Select MCO2 clock source and prescaler */ tmpreg |= RCC_MCO2Source | RCC_MCO2Div; /* Store the new value */ RCC->CFGR = tmpreg; } /** * @} */ /** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions * @brief System, AHB and APB busses clocks configuration functions * @verbatim =============================================================================== ##### System, AHB and APB busses clocks configuration functions ##### =============================================================================== [..] This section provide functions allowing to configure the System, AHB, APB1 and APB2 busses clocks. (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, HSE and PLL. The AHB clock (HCLK) is derived from System clock through configurable prescaler and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through configurable prescalers and used to clock the peripherals mapped on these busses. You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or from an external clock mapped on the I2S_CKIN pin. You have to use RCC_I2SCLKConfig() function to configure this clock. (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd() functions to configure this clock. (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz to work correctly, while the SDIO require a frequency equal or lower than to 48. This clock is derived of the main PLL through PLLQ divider. (+@) IWDG clock which is always the LSI clock. (#) For STM32F405xx/407xx and STM32F415xx/417xx devices, the maximum frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum frequency should be adapted accordingly: +-------------------------------------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |---------------------------------------------------------------------| | | voltage range | voltage range | voltage range | voltage range | | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | |---------------|----------------|----------------|-----------------|-----------------| |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | |---------------|----------------|----------------|-----------------|-----------------| |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | |---------------|----------------|----------------|-----------------|-----------------| |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | |---------------|----------------|----------------|-----------------|-----------------| |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | |---------------|----------------|----------------|-----------------|-----------------| |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | |---------------|----------------|----------------|-----------------|-----------------| |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| |---------------|----------------|----------------|-----------------|-----------------| |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| |---------------|----------------|----------------|-----------------|-----------------| |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160| +---------------|----------------|----------------|-----------------|-----------------+ (#) For STM32F42xxx/43xxx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum frequency should be adapted accordingly: +-------------------------------------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |---------------------------------------------------------------------| | | voltage range | voltage range | voltage range | voltage range | | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | |---------------|----------------|----------------|-----------------|-----------------| |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | |---------------|----------------|----------------|-----------------|-----------------| |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | |---------------|----------------|----------------|-----------------|-----------------| |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | |---------------|----------------|----------------|-----------------|-----------------| |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | |---------------|----------------|----------------|-----------------|-----------------| |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | |---------------|----------------|----------------|-----------------|-----------------| |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| |---------------|----------------|----------------|-----------------|-----------------| |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| |---------------|----------------|----------------|-----------------|-----------------| |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160| |---------------|----------------|----------------|-----------------|-----------------| |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168| +-------------------------------------------------------------------------------------+ (#) For STM32F401xx devices, the maximum frequency of the SYSCLK and HCLK is 84 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum frequency should be adapted accordingly: +-------------------------------------------------------------------------------------+ | Latency | HCLK clock frequency (MHz) | | |---------------------------------------------------------------------| | | voltage range | voltage range | voltage range | voltage range | | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | |---------------|----------------|----------------|-----------------|-----------------| |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | |---------------|----------------|----------------|-----------------|-----------------| |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | |---------------|----------------|----------------|-----------------|-----------------| |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | |---------------|----------------|----------------|-----------------|-----------------| |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 | |---------------|----------------|----------------|-----------------|-----------------| |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 | +-------------------------------------------------------------------------------------+ -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: (++) when VOS = '0', the maximum value of fHCLK = 144MHz. (++) when VOS = '1', the maximum value of fHCLK = 168MHz. [..] On STM32F42xxx/43xxx devices: (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz. (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz. (++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz [..] On STM32F401x devices: (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 64MHz. (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 84MHz. You can use PWR_MainRegulatorModeConfig() function to control VOS bits. @endverbatim * @{ */ /** * @brief Configures the system clock (SYSCLK). * @note The HSI is used (enabled by hardware) as system clock source after * startup from Reset, wake-up from STOP and STANDBY mode, or in case * of failure of the HSE used directly or indirectly as system clock * (if the Clock Security System CSS is enabled). * @note A switch from one clock source to another occurs only if the target * clock source is ready (clock stable after startup delay or PLL locked). * If a clock source which is not yet ready is selected, the switch will * occur when the clock source will be ready. * You can use RCC_GetSYSCLKSource() function to know which clock is * currently used as system clock source. * @param RCC_SYSCLKSource: specifies the clock source used as system clock. * This parameter can be one of the following values: * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source * @retval None */ void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); tmpreg = RCC->CFGR; /* Clear SW[1:0] bits */ tmpreg &= ~RCC_CFGR_SW; /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ tmpreg |= RCC_SYSCLKSource; /* Store the new value */ RCC->CFGR = tmpreg; } /** * @brief Returns the clock source used as system clock. * @param None * @retval The clock source used as system clock. The returned value can be one * of the following: * - 0x00: HSI used as system clock * - 0x04: HSE used as system clock * - 0x08: PLL used as system clock */ uint8_t RCC_GetSYSCLKSource(void) { return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); } /** * @brief Configures the AHB clock (HCLK). * @note Depending on the device voltage range, the software has to set correctly * these bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above * "CPU, AHB and APB busses clocks configuration functions") * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from * the system clock (SYSCLK). * This parameter can be one of the following values: * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 * @retval None */ void RCC_HCLKConfig(uint32_t RCC_SYSCLK) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_HCLK(RCC_SYSCLK)); tmpreg = RCC->CFGR; /* Clear HPRE[3:0] bits */ tmpreg &= ~RCC_CFGR_HPRE; /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ tmpreg |= RCC_SYSCLK; /* Store the new value */ RCC->CFGR = tmpreg; } /** * @brief Configures the Low Speed APB clock (PCLK1). * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from * the AHB clock (HCLK). * This parameter can be one of the following values: * @arg RCC_HCLK_Div1: APB1 clock = HCLK * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 * @retval None */ void RCC_PCLK1Config(uint32_t RCC_HCLK) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_PCLK(RCC_HCLK)); tmpreg = RCC->CFGR; /* Clear PPRE1[2:0] bits */ tmpreg &= ~RCC_CFGR_PPRE1; /* Set PPRE1[2:0] bits according to RCC_HCLK value */ tmpreg |= RCC_HCLK; /* Store the new value */ RCC->CFGR = tmpreg; } /** * @brief Configures the High Speed APB clock (PCLK2). * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from * the AHB clock (HCLK). * This parameter can be one of the following values: * @arg RCC_HCLK_Div1: APB2 clock = HCLK * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 * @retval None */ void RCC_PCLK2Config(uint32_t RCC_HCLK) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_PCLK(RCC_HCLK)); tmpreg = RCC->CFGR; /* Clear PPRE2[2:0] bits */ tmpreg &= ~RCC_CFGR_PPRE2; /* Set PPRE2[2:0] bits according to RCC_HCLK value */ tmpreg |= RCC_HCLK << 3; /* Store the new value */ RCC->CFGR = tmpreg; } /** * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, * PCLK1 and PCLK2. * * @note The system frequency computed by this function is not the real * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. * @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value * 16 MHz) but the real value may vary depending on the variations * in voltage and temperature. * @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value * 25 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. * * @note The result of this function could be not correct when using fractional * value for HSE crystal. * * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold * the clocks frequencies. * * @note This function can be used by the user application to compute the * baudrate for the communication peripherals or configure other parameters. * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function * must be called to update the structure's field. Otherwise, any * configuration based on this function will be incorrect. * * @retval None */ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) { uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; switch (tmp) { case 0x00: /* HSI used as system clock source */ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; break; case 0x04: /* HSE used as system clock source */ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; break; case 0x08: /* PLL used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; if (pllsource != 0) { /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } else { /* HSI used as PLL clock source */ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); } pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; RCC_Clocks->SYSCLK_Frequency = pllvco/pllp; break; default: RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; break; } /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/ /* Get HCLK prescaler */ tmp = RCC->CFGR & RCC_CFGR_HPRE; tmp = tmp >> 4; presc = APBAHBPrescTable[tmp]; /* HCLK clock frequency */ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; /* Get PCLK1 prescaler */ tmp = RCC->CFGR & RCC_CFGR_PPRE1; tmp = tmp >> 10; presc = APBAHBPrescTable[tmp]; /* PCLK1 clock frequency */ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; /* Get PCLK2 prescaler */ tmp = RCC->CFGR & RCC_CFGR_PPRE2; tmp = tmp >> 13; presc = APBAHBPrescTable[tmp]; /* PCLK2 clock frequency */ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; } /** * @} */ /** @defgroup RCC_Group3 Peripheral clocks configuration functions * @brief Peripheral clocks configuration functions * @verbatim =============================================================================== ##### Peripheral clocks configuration functions ##### =============================================================================== [..] This section provide functions allowing to configure the Peripheral clocks. (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31. (#) After restart from Reset or wakeup from STANDBY, all peripherals are off except internal SRAM, Flash and JTAG. Before to start using a peripheral you have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. (#) To reset the peripherals configuration (to the default state after device reset) you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and RCC_APB1PeriphResetCmd() functions. (#) To further reduce power consumption in SLEEP mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions. You can do this using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions. @endverbatim * @{ */ /** * @brief Configures the RTC clock (RTCCLK). * @note As the RTC clock configuration bits are in the Backup domain and write * access is denied to this domain after reset, you have to enable write * access using PWR_BackupAccessCmd(ENABLE) function before to configure * the RTC clock source (to be done once after reset). * @note Once the RTC clock is configured it can't be changed unless the * Backup domain is reset using RCC_BackupResetCmd() function, or by * a Power On Reset (POR). * * @param RCC_RTCCLKSource: specifies the RTC clock source. * This parameter can be one of the following values: * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected * as RTC clock, where x:[2,31] * * @note If the LSE or LSI is used as RTC clock source, the RTC continues to * work in STOP and STANDBY modes, and can be used as wakeup source. * However, when the HSE clock is used as RTC clock source, the RTC * cannot be used in STOP and STANDBY modes. * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as * RTC clock source). * * @retval None */ void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300) { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */ tmpreg = RCC->CFGR; /* Clear RTCPRE[4:0] bits */ tmpreg &= ~RCC_CFGR_RTCPRE; /* Configure HSE division factor for RTC clock */ tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF); /* Store the new value */ RCC->CFGR = tmpreg; } /* Select the RTC clock source */ RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF); } /** * @brief Enables or disables the RTC clock. * @note This function must be used only after the RTC clock source was selected * using the RCC_RTCCLKConfig function. * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_RTCCLKCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; } /** * @brief Forces or releases the Backup domain reset. * @note This function resets the RTC peripheral (including the backup registers) * and the RTC clock source selection in RCC_CSR register. * @note The BKPSRAM is not affected by this reset. * @param NewState: new state of the Backup domain reset. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_BackupResetCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; } /** * @brief Configures the I2S clock source (I2SCLK). * @note This function must be called before enabling the I2S APB clock. * @param RCC_I2SCLKSource: specifies the I2S clock source. * This parameter can be one of the following values: * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin * used as I2S clock source * @retval None */ void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) { /* Check the parameters */ assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource; } /** * @brief Configures the SAI clock Divider coming from PLLI2S. * * @note This function can be used only for STM32F42xxx/43xxx devices. * * @note This function must be called before enabling the PLLI2S. * * @param RCC_PLLI2SDivQ: specifies the PLLI2S division factor for SAI1 clock . * This parameter must be a number between 1 and 32. * SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ * * @retval None */ void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(RCC_PLLI2SDivQ)); tmpreg = RCC->DCKCFGR; /* Clear PLLI2SDIVQ[4:0] bits */ tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVQ); /* Set PLLI2SDIVQ values */ tmpreg |= (RCC_PLLI2SDivQ - 1); /* Store the new value */ RCC->DCKCFGR = tmpreg; } /** * @brief Configures the SAI clock Divider coming from PLLSAI. * * @note This function can be used only for STM32F42xxx/43xxx devices. * * @note This function must be called before enabling the PLLSAI. * * @param RCC_PLLSAIDivQ: specifies the PLLSAI division factor for SAI1 clock . * This parameter must be a number between 1 and 32. * SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ * * @retval None */ void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(RCC_PLLSAIDivQ)); tmpreg = RCC->DCKCFGR; /* Clear PLLI2SDIVQ[4:0] and PLLSAIDIVQ[4:0] bits */ tmpreg &= ~(RCC_DCKCFGR_PLLSAIDIVQ); /* Set PLLSAIDIVQ values */ tmpreg |= ((RCC_PLLSAIDivQ - 1) << 8); /* Store the new value */ RCC->DCKCFGR = tmpreg; } /** * @brief Configures SAI1BlockA clock source selection. * * @note This function can be used only for STM32F42xxx/43xxx devices. * * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. * @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source. * This parameter can be one of the following values: * @arg RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used * as SAI1 Block A clock * @arg RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used * as SAI1 Block A clock * @arg RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin * used as SAI1 Block A clock * @retval None */ void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource)); tmpreg = RCC->DCKCFGR; /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */ tmpreg &= ~RCC_DCKCFGR_SAI1ASRC; /* Set SAI Block A source selection value */ tmpreg |= RCC_SAIBlockACLKSource; /* Store the new value */ RCC->DCKCFGR = tmpreg; } /** * @brief Configures SAI1BlockB clock source selection. * * @note This function can be used only for STM32F42xxx/43xxx devices. * * @note This function must be called before enabling PLLSAI, PLLI2S and * the SAI clock. * @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source. * This parameter can be one of the following values: * @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used * as SAI1 Block B clock * @arg RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used * as SAI1 Block B clock * @arg RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin * used as SAI1 Block B clock * @retval None */ void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource)); tmpreg = RCC->DCKCFGR; /* Clear RCC_DCKCFGR_SAI1BSRC[1:0] bits */ tmpreg &= ~RCC_DCKCFGR_SAI1BSRC; /* Set SAI Block B source selection value */ tmpreg |= RCC_SAIBlockBCLKSource; /* Store the new value */ RCC->DCKCFGR = tmpreg; } /** * @brief Configures the LTDC clock Divider coming from PLLSAI. * * @note The LTDC peripheral is only available with STM32F429xx/439xx Devices. * * @note This function must be called before enabling the PLLSAI. * * @param RCC_PLLSAIDivR: specifies the PLLSAI division factor for LTDC clock . * This parameter must be a number between 2 and 16. * LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR * * @retval None */ void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RCC_PLLSAI_DIVR_VALUE(RCC_PLLSAIDivR)); tmpreg = RCC->DCKCFGR; /* Clear PLLSAIDIVR[2:0] bits */ tmpreg &= ~RCC_DCKCFGR_PLLSAIDIVR; /* Set PLLSAIDIVR values */ tmpreg |= RCC_PLLSAIDivR; /* Store the new value */ RCC->DCKCFGR = tmpreg; } /** * @brief Configures the Timers clocks prescalers selection. * * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx devices. * * @param RCC_TIMCLKPrescaler : specifies the Timers clocks prescalers selection * This parameter can be one of the following values: * @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is * equal to HPRE if PPREx is corresponding to division by 1 or 2, * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to * division by 4 or more. * * @arg RCC_TIMPrescActivated: The Timers kernels clocks prescaler is * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding * to division by 8 or more. * @retval None */ void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler) { /* Check the parameters */ assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler)); *(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler; } /** * @brief Enables or disables the AHB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_AHB1Periph_GPIOA: GPIOA clock * @arg RCC_AHB1Periph_GPIOB: GPIOB clock * @arg RCC_AHB1Periph_GPIOC: GPIOC clock * @arg RCC_AHB1Periph_GPIOD: GPIOD clock * @arg RCC_AHB1Periph_GPIOE: GPIOE clock * @arg RCC_AHB1Periph_GPIOF: GPIOF clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOI: GPIOI clock * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) * @arg RCC_AHB1Periph_CRC: CRC clock * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock * @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock * @arg RCC_AHB1Periph_DMA1: DMA1 clock * @arg RCC_AHB1Periph_DMA2: DMA2 clock * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->AHB1ENR |= RCC_AHB1Periph; } else { RCC->AHB1ENR &= ~RCC_AHB1Periph; } } /** * @brief Enables or disables the AHB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_AHB2Periph_DCMI: DCMI clock * @arg RCC_AHB2Periph_CRYP: CRYP clock * @arg RCC_AHB2Periph_HASH: HASH clock * @arg RCC_AHB2Periph_RNG: RNG clock * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->AHB2ENR |= RCC_AHB2Periph; } else { RCC->AHB2ENR &= ~RCC_AHB2Periph; } } /** * @brief Enables or disables the AHB3 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. * This parameter must be: RCC_AHB3Periph_FSMC * or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices) * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->AHB3ENR |= RCC_AHB3Periph; } else { RCC->AHB3ENR &= ~RCC_AHB3Periph; } } /** * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_APB1Periph_TIM2: TIM2 clock * @arg RCC_APB1Periph_TIM3: TIM3 clock * @arg RCC_APB1Periph_TIM4: TIM4 clock * @arg RCC_APB1Periph_TIM5: TIM5 clock * @arg RCC_APB1Periph_TIM6: TIM6 clock * @arg RCC_APB1Periph_TIM7: TIM7 clock * @arg RCC_APB1Periph_TIM12: TIM12 clock * @arg RCC_APB1Periph_TIM13: TIM13 clock * @arg RCC_APB1Periph_TIM14: TIM14 clock * @arg RCC_APB1Periph_WWDG: WWDG clock * @arg RCC_APB1Periph_SPI2: SPI2 clock * @arg RCC_APB1Periph_SPI3: SPI3 clock * @arg RCC_APB1Periph_USART2: USART2 clock * @arg RCC_APB1Periph_USART3: USART3 clock * @arg RCC_APB1Periph_UART4: UART4 clock * @arg RCC_APB1Periph_UART5: UART5 clock * @arg RCC_APB1Periph_I2C1: I2C1 clock * @arg RCC_APB1Periph_I2C2: I2C2 clock * @arg RCC_APB1Periph_I2C3: I2C3 clock * @arg RCC_APB1Periph_CAN1: CAN1 clock * @arg RCC_APB1Periph_CAN2: CAN2 clock * @arg RCC_APB1Periph_PWR: PWR clock * @arg RCC_APB1Periph_DAC: DAC clock * @arg RCC_APB1Periph_UART7: UART7 clock * @arg RCC_APB1Periph_UART8: UART8 clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->APB1ENR |= RCC_APB1Periph; } else { RCC->APB1ENR &= ~RCC_APB1Periph; } } /** * @brief Enables or disables the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_APB2Periph_TIM1: TIM1 clock * @arg RCC_APB2Periph_TIM8: TIM8 clock * @arg RCC_APB2Periph_USART1: USART1 clock * @arg RCC_APB2Periph_USART6: USART6 clock * @arg RCC_APB2Periph_ADC1: ADC1 clock * @arg RCC_APB2Periph_ADC2: ADC2 clock * @arg RCC_APB2Periph_ADC3: ADC3 clock * @arg RCC_APB2Periph_SDIO: SDIO clock * @arg RCC_APB2Periph_SPI1: SPI1 clock * @arg RCC_APB2Periph_SPI4: SPI4 clock * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock * @arg RCC_APB2Periph_TIM9: TIM9 clock * @arg RCC_APB2Periph_TIM10: TIM10 clock * @arg RCC_APB2Periph_TIM11: TIM11 clock * @arg RCC_APB2Periph_SPI5: SPI5 clock * @arg RCC_APB2Periph_SPI6: SPI6 clock * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->APB2ENR |= RCC_APB2Periph; } else { RCC->APB2ENR &= ~RCC_APB2Periph; } } /** * @brief Forces or releases AHB1 peripheral reset. * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset. * This parameter can be any combination of the following values: * @arg RCC_AHB1Periph_GPIOA: GPIOA clock * @arg RCC_AHB1Periph_GPIOB: GPIOB clock * @arg RCC_AHB1Periph_GPIOC: GPIOC clock * @arg RCC_AHB1Periph_GPIOD: GPIOD clock * @arg RCC_AHB1Periph_GPIOE: GPIOE clock * @arg RCC_AHB1Periph_GPIOF: GPIOF clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOI: GPIOI clock * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices) * @arg RCC_AHB1Periph_CRC: CRC clock * @arg RCC_AHB1Periph_DMA1: DMA1 clock * @arg RCC_AHB1Periph_DMA2: DMA2 clock * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock * * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->AHB1RSTR |= RCC_AHB1Periph; } else { RCC->AHB1RSTR &= ~RCC_AHB1Periph; } } /** * @brief Forces or releases AHB2 peripheral reset. * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset. * This parameter can be any combination of the following values: * @arg RCC_AHB2Periph_DCMI: DCMI clock * @arg RCC_AHB2Periph_CRYP: CRYP clock * @arg RCC_AHB2Periph_HASH: HASH clock * @arg RCC_AHB2Periph_RNG: RNG clock * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->AHB2RSTR |= RCC_AHB2Periph; } else { RCC->AHB2RSTR &= ~RCC_AHB2Periph; } } /** * @brief Forces or releases AHB3 peripheral reset. * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset. * This parameter must be: RCC_AHB3Periph_FSMC * or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices) * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->AHB3RSTR |= RCC_AHB3Periph; } else { RCC->AHB3RSTR &= ~RCC_AHB3Periph; } } /** * @brief Forces or releases Low Speed APB (APB1) peripheral reset. * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. * This parameter can be any combination of the following values: * @arg RCC_APB1Periph_TIM2: TIM2 clock * @arg RCC_APB1Periph_TIM3: TIM3 clock * @arg RCC_APB1Periph_TIM4: TIM4 clock * @arg RCC_APB1Periph_TIM5: TIM5 clock * @arg RCC_APB1Periph_TIM6: TIM6 clock * @arg RCC_APB1Periph_TIM7: TIM7 clock * @arg RCC_APB1Periph_TIM12: TIM12 clock * @arg RCC_APB1Periph_TIM13: TIM13 clock * @arg RCC_APB1Periph_TIM14: TIM14 clock * @arg RCC_APB1Periph_WWDG: WWDG clock * @arg RCC_APB1Periph_SPI2: SPI2 clock * @arg RCC_APB1Periph_SPI3: SPI3 clock * @arg RCC_APB1Periph_USART2: USART2 clock * @arg RCC_APB1Periph_USART3: USART3 clock * @arg RCC_APB1Periph_UART4: UART4 clock * @arg RCC_APB1Periph_UART5: UART5 clock * @arg RCC_APB1Periph_I2C1: I2C1 clock * @arg RCC_APB1Periph_I2C2: I2C2 clock * @arg RCC_APB1Periph_I2C3: I2C3 clock * @arg RCC_APB1Periph_CAN1: CAN1 clock * @arg RCC_APB1Periph_CAN2: CAN2 clock * @arg RCC_APB1Periph_PWR: PWR clock * @arg RCC_APB1Periph_DAC: DAC clock * @arg RCC_APB1Periph_UART7: UART7 clock * @arg RCC_APB1Periph_UART8: UART8 clock * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->APB1RSTR |= RCC_APB1Periph; } else { RCC->APB1RSTR &= ~RCC_APB1Periph; } } /** * @brief Forces or releases High Speed APB (APB2) peripheral reset. * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. * This parameter can be any combination of the following values: * @arg RCC_APB2Periph_TIM1: TIM1 clock * @arg RCC_APB2Periph_TIM8: TIM8 clock * @arg RCC_APB2Periph_USART1: USART1 clock * @arg RCC_APB2Periph_USART6: USART6 clock * @arg RCC_APB2Periph_ADC1: ADC1 clock * @arg RCC_APB2Periph_ADC2: ADC2 clock * @arg RCC_APB2Periph_ADC3: ADC3 clock * @arg RCC_APB2Periph_SDIO: SDIO clock * @arg RCC_APB2Periph_SPI1: SPI1 clock * @arg RCC_APB2Periph_SPI4: SPI4 clock * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock * @arg RCC_APB2Periph_TIM9: TIM9 clock * @arg RCC_APB2Periph_TIM10: TIM10 clock * @arg RCC_APB2Periph_TIM11: TIM11 clock * @arg RCC_APB2Periph_SPI5: SPI5 clock * @arg RCC_APB2Periph_SPI6: SPI6 clock * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) * @param NewState: new state of the specified peripheral reset. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->APB2RSTR |= RCC_APB2Periph; } else { RCC->APB2RSTR &= ~RCC_APB2Periph; } } /** * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_AHB1Periph_GPIOA: GPIOA clock * @arg RCC_AHB1Periph_GPIOB: GPIOB clock * @arg RCC_AHB1Periph_GPIOC: GPIOC clock * @arg RCC_AHB1Periph_GPIOD: GPIOD clock * @arg RCC_AHB1Periph_GPIOE: GPIOE clock * @arg RCC_AHB1Periph_GPIOF: GPIOF clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOG: GPIOG clock * @arg RCC_AHB1Periph_GPIOI: GPIOI clock * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) * @arg RCC_AHB1Periph_CRC: CRC clock * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock * @arg RCC_AHB1Periph_DMA1: DMA1 clock * @arg RCC_AHB1Periph_DMA2: DMA2 clock * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->AHB1LPENR |= RCC_AHB1Periph; } else { RCC->AHB1LPENR &= ~RCC_AHB1Periph; } } /** * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_AHB2Periph_DCMI: DCMI clock * @arg RCC_AHB2Periph_CRYP: CRYP clock * @arg RCC_AHB2Periph_HASH: HASH clock * @arg RCC_AHB2Periph_RNG: RNG clock * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->AHB2LPENR |= RCC_AHB2Periph; } else { RCC->AHB2LPENR &= ~RCC_AHB2Periph; } } /** * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. * This parameter must be: RCC_AHB3Periph_FSMC * or RCC_AHB3Periph_FMC (STM32F429x/439x devices) * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->AHB3LPENR |= RCC_AHB3Periph; } else { RCC->AHB3LPENR &= ~RCC_AHB3Periph; } } /** * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_APB1Periph_TIM2: TIM2 clock * @arg RCC_APB1Periph_TIM3: TIM3 clock * @arg RCC_APB1Periph_TIM4: TIM4 clock * @arg RCC_APB1Periph_TIM5: TIM5 clock * @arg RCC_APB1Periph_TIM6: TIM6 clock * @arg RCC_APB1Periph_TIM7: TIM7 clock * @arg RCC_APB1Periph_TIM12: TIM12 clock * @arg RCC_APB1Periph_TIM13: TIM13 clock * @arg RCC_APB1Periph_TIM14: TIM14 clock * @arg RCC_APB1Periph_WWDG: WWDG clock * @arg RCC_APB1Periph_SPI2: SPI2 clock * @arg RCC_APB1Periph_SPI3: SPI3 clock * @arg RCC_APB1Periph_USART2: USART2 clock * @arg RCC_APB1Periph_USART3: USART3 clock * @arg RCC_APB1Periph_UART4: UART4 clock * @arg RCC_APB1Periph_UART5: UART5 clock * @arg RCC_APB1Periph_I2C1: I2C1 clock * @arg RCC_APB1Periph_I2C2: I2C2 clock * @arg RCC_APB1Periph_I2C3: I2C3 clock * @arg RCC_APB1Periph_CAN1: CAN1 clock * @arg RCC_APB1Periph_CAN2: CAN2 clock * @arg RCC_APB1Periph_PWR: PWR clock * @arg RCC_APB1Periph_DAC: DAC clock * @arg RCC_APB1Periph_UART7: UART7 clock * @arg RCC_APB1Periph_UART8: UART8 clock * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->APB1LPENR |= RCC_APB1Periph; } else { RCC->APB1LPENR &= ~RCC_APB1Periph; } } /** * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. * This parameter can be any combination of the following values: * @arg RCC_APB2Periph_TIM1: TIM1 clock * @arg RCC_APB2Periph_TIM8: TIM8 clock * @arg RCC_APB2Periph_USART1: USART1 clock * @arg RCC_APB2Periph_USART6: USART6 clock * @arg RCC_APB2Periph_ADC1: ADC1 clock * @arg RCC_APB2Periph_ADC2: ADC2 clock * @arg RCC_APB2Periph_ADC3: ADC3 clock * @arg RCC_APB2Periph_SDIO: SDIO clock * @arg RCC_APB2Periph_SPI1: SPI1 clock * @arg RCC_APB2Periph_SPI4: SPI4 clock * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock * @arg RCC_APB2Periph_TIM9: TIM9 clock * @arg RCC_APB2Periph_TIM10: TIM10 clock * @arg RCC_APB2Periph_TIM11: TIM11 clock * @arg RCC_APB2Periph_SPI5: SPI5 clock * @arg RCC_APB2Periph_SPI6: SPI6 clock * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices) * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { RCC->APB2LPENR |= RCC_APB2Periph; } else { RCC->APB2LPENR &= ~RCC_APB2Periph; } } /** * @} */ /** @defgroup RCC_Group4 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified RCC interrupts. * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt * @arg RCC_IT_LSERDY: LSE ready interrupt * @arg RCC_IT_HSIRDY: HSI ready interrupt * @arg RCC_IT_HSERDY: HSE ready interrupt * @arg RCC_IT_PLLRDY: main PLL ready interrupt * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices) * @param NewState: new state of the specified RCC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RCC_IT(RCC_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */ *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; } else { /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */ *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; } } /** * @brief Checks whether the specified RCC flag is set or not. * @param RCC_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready * @arg RCC_FLAG_PLLRDY: main PLL clock ready * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready * @arg RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx devices) * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset * @arg RCC_FLAG_PINRST: Pin reset * @arg RCC_FLAG_PORRST: POR/PDR reset * @arg RCC_FLAG_SFTRST: Software reset * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset * @arg RCC_FLAG_WWDGRST: Window Watchdog reset * @arg RCC_FLAG_LPWRRST: Low Power reset * @retval The new state of RCC_FLAG (SET or RESET). */ FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) { uint32_t tmp = 0; uint32_t statusreg = 0; FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_RCC_FLAG(RCC_FLAG)); /* Get the RCC register index */ tmp = RCC_FLAG >> 5; if (tmp == 1) /* The flag to check is in CR register */ { statusreg = RCC->CR; } else if (tmp == 2) /* The flag to check is in BDCR register */ { statusreg = RCC->BDCR; } else /* The flag to check is in CSR register */ { statusreg = RCC->CSR; } /* Get the flag position */ tmp = RCC_FLAG & FLAG_MASK; if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } /* Return the flag status */ return bitstatus; } /** * @brief Clears the RCC reset flags. * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST * @param None * @retval None */ void RCC_ClearFlag(void) { /* Set RMVF bit to clear the reset flags */ RCC->CSR |= RCC_CSR_RMVF; } /** * @brief Checks whether the specified RCC interrupt has occurred or not. * @param RCC_IT: specifies the RCC interrupt source to check. * This parameter can be one of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt * @arg RCC_IT_LSERDY: LSE ready interrupt * @arg RCC_IT_HSIRDY: HSI ready interrupt * @arg RCC_IT_HSERDY: HSE ready interrupt * @arg RCC_IT_PLLRDY: main PLL ready interrupt * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt * @arg RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx devices) * @arg RCC_IT_CSS: Clock Security System interrupt * @retval The new state of RCC_IT (SET or RESET). */ ITStatus RCC_GetITStatus(uint8_t RCC_IT) { ITStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_RCC_GET_IT(RCC_IT)); /* Check the status of the specified RCC interrupt */ if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } /* Return the RCC_IT status */ return bitstatus; } /** * @brief Clears the RCC's interrupt pending bits. * @param RCC_IT: specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg RCC_IT_LSIRDY: LSI ready interrupt * @arg RCC_IT_LSERDY: LSE ready interrupt * @arg RCC_IT_HSIRDY: HSI ready interrupt * @arg RCC_IT_HSERDY: HSE ready interrupt * @arg RCC_IT_PLLRDY: main PLL ready interrupt * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices) * @arg RCC_IT_CSS: Clock Security System interrupt * @retval None */ void RCC_ClearITPendingBit(uint8_t RCC_IT) { /* Check the parameters */ assert_param(IS_RCC_CLEAR_IT(RCC_IT)); /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt pending bits */ *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c ================================================ /** ****************************************************************************** * @file stm32f4xx_rng.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Random Number Generator (RNG) peripheral: * + Initialization and Configuration * + Get 32 bit Random number * + Interrupts and flags management * @verbatim =================================================================== ##### How to use this driver ##### =================================================================== [..] (#) Enable The RNG controller clock using RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function. (#) Activate the RNG peripheral using RNG_Cmd() function. (#) Wait until the 32 bit Random number Generator contains a valid random data (using polling/interrupt mode). For more details, refer to "Interrupts and flags management functions" module description. (#) Get the 32 bit Random number using RNG_GetRandomNumber() function (#) To get another 32 bit Random number, go to step 3. @endverbatim * ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_rng.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup RNG * @brief RNG driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup RNG_Private_Functions * @{ */ /** @defgroup RNG_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This section provides functions allowing to (+) Initialize the RNG peripheral (+) Enable or disable the RNG peripheral @endverbatim * @{ */ /** * @brief De-initializes the RNG peripheral registers to their default reset values. * @param None * @retval None */ void RNG_DeInit(void) { /* Enable RNG reset state */ RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE); /* Release RNG from reset state */ RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE); } /** * @brief Enables or disables the RNG peripheral. * @param NewState: new state of the RNG peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RNG_Cmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the RNG */ RNG->CR |= RNG_CR_RNGEN; } else { /* Disable the RNG */ RNG->CR &= ~RNG_CR_RNGEN; } } /** * @} */ /** @defgroup RNG_Group2 Get 32 bit Random number function * @brief Get 32 bit Random number function * @verbatim =============================================================================== ##### Get 32 bit Random number function ##### =============================================================================== [..] This section provides a function allowing to get the 32 bit Random number (@) Before to call this function you have to wait till DRDY flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. @endverbatim * @{ */ /** * @brief Returns a 32-bit random number. * * @note Before to call this function you have to wait till DRDY (data ready) * flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. * @note Each time the the Random number data is read (using RNG_GetRandomNumber() * function), the RNG_FLAG_DRDY flag is automatically cleared. * @note In the case of a seed error, the generation of random numbers is * interrupted for as long as the SECS bit is '1'. If a number is * available in the RNG_DR register, it must not be used because it may * not have enough entropy. In this case, it is recommended to clear the * SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable * and enable the RNG peripheral (using RNG_Cmd() function) to * reinitialize and restart the RNG. * @note In the case of a clock error, the RNG is no more able to generate * random numbers because the PLL48CLK clock is not correct. User have * to check that the clock controller is correctly configured to provide * the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS) * function) . The clock error has no impact on the previously generated * random numbers, and the RNG_DR register contents can be used. * * @param None * @retval 32-bit random number. */ uint32_t RNG_GetRandomNumber(void) { /* Return the 32 bit random number from the DR register */ return RNG->DR; } /** * @} */ /** @defgroup RNG_Group3 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== [..] This section provides functions allowing to configure the RNG Interrupts and to get the status and clear flags and Interrupts pending bits. [..] The RNG provides 3 Interrupts sources and 3 Flags: *** Flags : *** =============== [..] (#) RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid random data. it is cleared by reading the valid data(using RNG_GetRandomNumber() function). (#) RNG_FLAG_CECS : In the case of a seed error detection. (#) RNG_FLAG_SECS : In the case of a clock error detection. *** Interrupts *** ================== [..] If enabled, an RNG interrupt is pending : (#) In the case of the RNG_DR register contains valid random data. This interrupt source is cleared once the RNG_DR register has been read (using RNG_GetRandomNumber() function) until a new valid value is computed; or (#) In the case of a seed error : One of the following faulty sequences has been detected: (++) More than 64 consecutive bits at the same value (0 or 1) (++) More than 32 consecutive alternance of 0 and 1 (0101010101...01) This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI) function; or (#) In the case of a clock error : the PLL48CLK (RNG peripheral clock source) was not correctly detected (fPLL48CLK< fHCLK/16). This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_CEI) function. -@- note In this case, User have to check that the clock controller is correctly configured to provide the RNG clock. *** Managing the RNG controller events : *** ============================================ [..] The user should identify which mode will be used in his application to manage the RNG controller events: Polling mode or Interrupt mode. (#) In the Polling Mode it is advised to use the following functions: (++) RNG_GetFlagStatus() : to check if flags events occur. (++) RNG_ClearFlag() : to clear the flags events. -@@- RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only by reading the Random number data. (#) In the Interrupt Mode it is advised to use the following functions: (++) RNG_ITConfig() : to enable or disable the interrupt source. (++) RNG_GetITStatus() : to check if Interrupt occurs. (++) RNG_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag). @endverbatim * @{ */ /** * @brief Enables or disables the RNG interrupt. * @note The RNG provides 3 interrupt sources, * - Computed data is ready event (DRDY), and * - Seed error Interrupt (SEI) and * - Clock error Interrupt (CEI), * all these interrupts sources are enabled by setting the IE bit in * CR register. However, each interrupt have its specific status bit * (see RNG_GetITStatus() function) and clear bit except the DRDY event * (see RNG_ClearITPendingBit() function). * @param NewState: new state of the RNG interrupt. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RNG_ITConfig(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the RNG interrupt */ RNG->CR |= RNG_CR_IE; } else { /* Disable the RNG interrupt */ RNG->CR &= ~RNG_CR_IE; } } /** * @brief Checks whether the specified RNG flag is set or not. * @param RNG_FLAG: specifies the RNG flag to check. * This parameter can be one of the following values: * @arg RNG_FLAG_DRDY: Data Ready flag. * @arg RNG_FLAG_CECS: Clock Error Current flag. * @arg RNG_FLAG_SECS: Seed Error Current flag. * @retval The new state of RNG_FLAG (SET or RESET). */ FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_RNG_GET_FLAG(RNG_FLAG)); /* Check the status of the specified RNG flag */ if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET) { /* RNG_FLAG is set */ bitstatus = SET; } else { /* RNG_FLAG is reset */ bitstatus = RESET; } /* Return the RNG_FLAG status */ return bitstatus; } /** * @brief Clears the RNG flags. * @param RNG_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg RNG_FLAG_CECS: Clock Error Current flag. * @arg RNG_FLAG_SECS: Seed Error Current flag. * @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function. * This flag is cleared only by reading the Random number data (using * RNG_GetRandomNumber() function). * @retval None */ void RNG_ClearFlag(uint8_t RNG_FLAG) { /* Check the parameters */ assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG)); /* Clear the selected RNG flags */ RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4); } /** * @brief Checks whether the specified RNG interrupt has occurred or not. * @param RNG_IT: specifies the RNG interrupt source to check. * This parameter can be one of the following values: * @arg RNG_IT_CEI: Clock Error Interrupt. * @arg RNG_IT_SEI: Seed Error Interrupt. * @retval The new state of RNG_IT (SET or RESET). */ ITStatus RNG_GetITStatus(uint8_t RNG_IT) { ITStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_RNG_GET_IT(RNG_IT)); /* Check the status of the specified RNG interrupt */ if ((RNG->SR & RNG_IT) != (uint8_t)RESET) { /* RNG_IT is set */ bitstatus = SET; } else { /* RNG_IT is reset */ bitstatus = RESET; } /* Return the RNG_IT status */ return bitstatus; } /** * @brief Clears the RNG interrupt pending bit(s). * @param RNG_IT: specifies the RNG interrupt pending bit(s) to clear. * This parameter can be any combination of the following values: * @arg RNG_IT_CEI: Clock Error Interrupt. * @arg RNG_IT_SEI: Seed Error Interrupt. * @retval None */ void RNG_ClearITPendingBit(uint8_t RNG_IT) { /* Check the parameters */ assert_param(IS_RNG_IT(RNG_IT)); /* Clear the selected RNG interrupt pending bit */ RNG->SR = (uint8_t)~RNG_IT; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c ================================================ /** ****************************************************************************** * @file stm32f4xx_rtc.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Real-Time Clock (RTC) peripheral: * + Initialization * + Calendar (Time and Date) configuration * + Alarms (Alarm A and Alarm B) configuration * + WakeUp Timer configuration * + Daylight Saving configuration * + Output pin Configuration * + Coarse digital Calibration configuration * + Smooth digital Calibration configuration * + TimeStamp configuration * + Tampers configuration * + Backup Data Registers configuration * + Shift control synchronisation * + RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration * + Interrupts and flags management * @verbatim =================================================================== ##### Backup Domain Operating Condition ##### =================================================================== [..] The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM) can be powered from the VBAT voltage when the main VDD supply is powered off. To retain the content of the RTC backup registers, backup SRAM, and supply the RTC when VDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a battery or by another source. [..] To allow the RTC to operate even when the main digital supply (VDD) is turned off, the VBAT pin powers the following blocks: (#) The RTC (#) The LSE oscillator (#) The backup SRAM when the low power backup regulator is enabled (#) PC13 to PC15 I/Os, plus PI8 I/O (when available) [..] When the backup domain is supplied by VDD (analog switch connected to VDD), the following functions are available: (#) PC14 and PC15 can be used as either GPIO or LSE pins (#) PC13 can be used as a GPIO or as the RTC_AF1 pin (#) PI8 can be used as a GPIO or as the RTC_AF2 pin [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT because VDD is not present), the following functions are available: (#) PC14 and PC15 can be used as LSE pins only (#) PC13 can be used as the RTC_AF1 pin (#) PI8 can be used as the RTC_AF2 pin ##### Backup Domain Reset ##### =================================================================== [..] The backup domain reset sets all RTC registers and the RCC_BDCR register to their reset values. The BKPSRAM is not affected by this reset. The only way of resetting the BKPSRAM is through the Flash interface by requesting a protection level change from 1 to 0. [..] A backup domain reset is generated when one of the following events occurs: (#) Software reset, triggered by setting the BDRST bit in the RCC Backup domain control register (RCC_BDCR). You can use the RCC_BackupResetCmd(). (#) VDD or VBAT power on, if both supplies have previously been powered off. ##### Backup Domain Access ##### =================================================================== [..] After reset, the backup domain (RTC registers, RTC backup data registers and backup SRAM) is protected against possible unwanted write accesses. [..] To enable access to the RTC Domain and RTC registers, proceed as follows: (+) Enable the Power Controller (PWR) APB1 interface clock using the RCC_APB1PeriphClockCmd() function. (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function. (+) Select the RTC clock source using the RCC_RTCCLKConfig() function. (+) Enable RTC Clock using the RCC_RTCCLKCmd() function. ##### How to use RTC Driver ##### =================================================================== [..] (+) Enable the RTC domain access (see description in the section above) (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour format using the RTC_Init() function. *** Time and Date configuration *** =================================== [..] (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime() and RTC_SetDate() functions. (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() functions. (+) Use the RTC_DayLightSavingConfig() function to add or sub one hour to the RTC Calendar. *** Alarm configuration *** =========================== [..] (+) To configure the RTC Alarm use the RTC_SetAlarm() function. (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function (+) To read the RTC Alarm, use the RTC_GetAlarm() function. (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function. *** RTC Wakeup configuration *** ================================ [..] (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig() function. (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() function (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() function. *** Outputs configuration *** ============================= [..] The RTC has 2 different outputs: (+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B and WaKeUp signals. To output the selected RTC signal on RTC_AF1 pin, use the RTC_OutputConfig() function. (+) AFO_CALIB: this output is 512Hz signal or 1Hz. To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd() function. *** Smooth digital Calibration configuration *** ================================================ [..] (+) Configure the RTC Original Digital Calibration Value and the corresponding calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() function. *** Coarse digital Calibration configuration *** ================================================ [..] (+) Configure the RTC Coarse Calibration Value and the corresponding sign using the RTC_CoarseCalibConfig() function. (+) Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() function *** TimeStamp configuration *** =============================== [..] (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp using the RTC _TimeStampCmd() function. (+) To read the RTC TimeStamp Time and Date register, use the RTC_GetTimeStamp() function. (+) To read the RTC TimeStamp SubSecond register, use the RTC_GetTimeStampSubSecond() function. (+) The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13) or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in RTC_TAFCR register. You can use the RTC_TamperPinSelection() function to select the corresponding pin. *** Tamper configuration *** ============================ [..] (+) Enable the RTC Tamper using the RTC_TamperCmd() function. (+) Configure the Tamper filter count using RTC_TamperFilterConfig() function. (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function. (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig() function. (+) Configure the Tamper precharge or discharge duration using RTC_TamperPinsPrechargeDuration() function. (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function. (+) Enable the Time stamp on Tamper detection event using TC_TSOnTamperDetecCmd() function. (+) The TIMESTAMP alternate function can be mapped to either RTC_AF1 or RTC_AF2 depending on the value of the TSINSEL bit in the RTC_TAFCR register. You can use the RTC_TimeStampPinSelection() function to select the corresponding pin. *** Backup Data Registers configuration *** =========================================== [..] (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister() function. (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister() function. ##### RTC and low power modes ##### =================================================================== [..] The MCU can be woken up from a low power mode by an RTC alternate function. [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), RTC wakeup, RTC tamper event detection and RTC time stamp event detection. These RTC alternate functions can wake up the system from the Stop and Standby lowpower modes. [..] The system can also wake up from low power modes without depending on an external interrupt (Auto-wakeup mode), by using the RTC alarm or the RTC wakeup events. [..] The RTC provides a programmable time base for waking up from the Stop or Standby mode at regular intervals. Wakeup from STOP and Standby modes is possible only when the RTC clock source is LSE or LSI. ##### Selection of RTC_AF1 alternate functions ##### =================================================================== [..] The RTC_AF1 pin (PC13) can be used for the following purposes: (+) AFO_ALARM output (+) AFO_CALIB output (+) AFI_TAMPER (+) AFI_TIMESTAMP [..] +-------------------------------------------------------------------------------------------------------------+ | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | | and function | | | | | selection | selection |Configuration | |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| | Alarm out | | | | | Don't | Don't | | | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 | |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| | Alarm out | | | | | Don't | Don't | | | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 | |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| | Calibration out | | | | | Don't | Don't | | | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care | |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| | TAMPER input | | | | | | Don't | | | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care | |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| | TIMESTAMP and | | | | | | | | | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care | | floating | | | | | | | | |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| | TIMESTAMP input | | | | | Don't | | | | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care | |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care | +-------------------------------------------------------------------------------------------------------------+ ##### Selection of RTC_AF2 alternate functions ##### =================================================================== [..] The RTC_AF2 pin (PI8) can be used for the following purposes: (+) AFI_TAMPER (+) AFI_TIMESTAMP [..] +---------------------------------------------------------------------------------------+ | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | | and function | | | selection | selection |Configuration | |-----------------|-----------|--------------|------------|--------------|--------------| | TAMPER input | | | | Don't | | | floating | 1 | 0 | 1 | care | Don't care | |-----------------|-----------|--------------|------------|--------------|--------------| | TIMESTAMP and | | | | | | | TAMPER input | 1 | 1 | 1 | 1 | Don't care | | floating | | | | | | |-----------------|-----------|--------------|------------|--------------|--------------| | TIMESTAMP input | | | Don't | | | | floating | 0 | 1 | care | 1 | Don't care | |-----------------|-----------|--------------|------------|--------------|--------------| | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care | +---------------------------------------------------------------------------------------+ @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_rtc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup RTC * @brief RTC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Masks Definition */ #define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) #define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) #define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) #define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) #define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \ RTC_FLAG_RECALPF | RTC_FLAG_SHPF)) #define INITMODE_TIMEOUT ((uint32_t) 0x00010000) #define SYNCHRO_TIMEOUT ((uint32_t) 0x00020000) #define RECALPF_TIMEOUT ((uint32_t) 0x00020000) #define SHPF_TIMEOUT ((uint32_t) 0x00001000) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static uint8_t RTC_ByteToBcd2(uint8_t Value); static uint8_t RTC_Bcd2ToByte(uint8_t Value); /* Private functions ---------------------------------------------------------*/ /** @defgroup RTC_Private_Functions * @{ */ /** @defgroup RTC_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This section provide functions allowing to initialize and configure the RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers Write protection, enter and exit the RTC initialization mode, RTC registers synchronization check and reference clock detection enable. (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is split into 2 programmable prescalers to minimize power consumption. (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. (++) When both prescalers are used, it is recommended to configure the asynchronous prescaler to a high value to minimize consumption. (#) All RTC registers are Write protected. Writing to the RTC registers is enabled by writing a key into the Write Protection register, RTC_WPR. (#) To Configure the RTC Calendar, user application should enter initialization mode. In this mode, the calendar counter is stopped and its value can be updated. When the initialization sequence is complete, the calendar restarts counting after 4 RTCCLK cycles. (#) To read the calendar through the shadow registers after Calendar initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the RTC_TR and RTC_DR shadow registers. The RTC_WaitForSynchro() function implements the above software sequence (RSF clear and RSF check). @endverbatim * @{ */ /** * @brief Deinitializes the RTC registers to their default reset values. * @note This function doesn't reset the RTC Clock source and RTC Backup Data * registers. * @param None * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC registers are deinitialized * - ERROR: RTC registers are not deinitialized */ ErrorStatus RTC_DeInit(void) { __IO uint32_t wutcounter = 0x00; uint32_t wutwfstatus = 0x00; ErrorStatus status = ERROR; /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Set Initialization mode */ if (RTC_EnterInitMode() == ERROR) { status = ERROR; } else { /* Reset TR, DR and CR registers */ RTC->TR = (uint32_t)0x00000000; RTC->DR = (uint32_t)0x00002101; /* Reset All CR bits except CR[2:0] */ RTC->CR &= (uint32_t)0x00000007; /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ do { wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; wutcounter++; } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) { status = ERROR; } else { /* Reset all RTC CR register bits */ RTC->CR &= (uint32_t)0x00000000; RTC->WUTR = (uint32_t)0x0000FFFF; RTC->PRER = (uint32_t)0x007F00FF; RTC->CALIBR = (uint32_t)0x00000000; RTC->ALRMAR = (uint32_t)0x00000000; RTC->ALRMBR = (uint32_t)0x00000000; RTC->SHIFTR = (uint32_t)0x00000000; RTC->CALR = (uint32_t)0x00000000; RTC->ALRMASSR = (uint32_t)0x00000000; RTC->ALRMBSSR = (uint32_t)0x00000000; /* Reset ISR register and exit initialization mode */ RTC->ISR = (uint32_t)0x00000000; /* Reset Tamper and alternate functions configuration register */ RTC->TAFCR = 0x00000000; if(RTC_WaitForSynchro() == ERROR) { status = ERROR; } else { status = SUCCESS; } } } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return status; } /** * @brief Initializes the RTC registers according to the specified parameters * in RTC_InitStruct. * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains * the configuration information for the RTC peripheral. * @note The RTC Prescaler register is write protected and can be written in * initialization mode only. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC registers are initialized * - ERROR: RTC registers are not initialized */ ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct) { ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv)); assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Set Initialization mode */ if (RTC_EnterInitMode() == ERROR) { status = ERROR; } else { /* Clear RTC CR FMT Bit */ RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); /* Set RTC_CR register */ RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); /* Configure the RTC PRER */ RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); /* Exit Initialization mode */ RTC_ExitInitMode(); status = SUCCESS; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return status; } /** * @brief Fills each RTC_InitStruct member with its default value. * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be * initialized. * @retval None */ void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct) { /* Initialize the RTC_HourFormat member */ RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24; /* Initialize the RTC_AsynchPrediv member */ RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; /* Initialize the RTC_SynchPrediv member */ RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; } /** * @brief Enables or disables the RTC registers write protection. * @note All the RTC registers are write protected except for RTC_ISR[13:8], * RTC_TAFCR and RTC_BKPxR. * @note Writing a wrong key reactivates the write protection. * @note The protection mechanism is not affected by system reset. * @param NewState: new state of the write protection. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RTC_WriteProtectionCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } else { /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; } } /** * @brief Enters the RTC Initialization mode. * @note The RTC Initialization mode is write protected, use the * RTC_WriteProtectionCmd(DISABLE) before calling this function. * @param None * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC is in Init mode * - ERROR: RTC is not in Init mode */ ErrorStatus RTC_EnterInitMode(void) { __IO uint32_t initcounter = 0x00; ErrorStatus status = ERROR; uint32_t initstatus = 0x00; /* Check if the Initialization mode is set */ if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET) { /* Set the Initialization mode */ RTC->ISR = (uint32_t)RTC_INIT_MASK; /* Wait till RTC is in INIT state and if Time out is reached exit */ do { initstatus = RTC->ISR & RTC_ISR_INITF; initcounter++; } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); if ((RTC->ISR & RTC_ISR_INITF) != RESET) { status = SUCCESS; } else { status = ERROR; } } else { status = SUCCESS; } return (status); } /** * @brief Exits the RTC Initialization mode. * @note When the initialization sequence is complete, the calendar restarts * counting after 4 RTCCLK cycles. * @note The RTC Initialization mode is write protected, use the * RTC_WriteProtectionCmd(DISABLE) before calling this function. * @param None * @retval None */ void RTC_ExitInitMode(void) { /* Exit Initialization mode */ RTC->ISR &= (uint32_t)~RTC_ISR_INIT; } /** * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are * synchronized with RTC APB clock. * @note The RTC Resynchronization mode is write protected, use the * RTC_WriteProtectionCmd(DISABLE) before calling this function. * @note To read the calendar through the shadow registers after Calendar * initialization, calendar update or after wakeup from low power modes * the software must first clear the RSF flag. * The software must then wait until it is set again before reading * the calendar, which means that the calendar registers have been * correctly copied into the RTC_TR and RTC_DR shadow registers. * @param None * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC registers are synchronised * - ERROR: RTC registers are not synchronised */ ErrorStatus RTC_WaitForSynchro(void) { __IO uint32_t synchrocounter = 0; ErrorStatus status = ERROR; uint32_t synchrostatus = 0x00; /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Clear RSF flag */ RTC->ISR &= (uint32_t)RTC_RSF_MASK; /* Wait the registers to be synchronised */ do { synchrostatus = RTC->ISR & RTC_ISR_RSF; synchrocounter++; } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); if ((RTC->ISR & RTC_ISR_RSF) != RESET) { status = SUCCESS; } else { status = ERROR; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return (status); } /** * @brief Enables or disables the RTC reference clock detection. * @param NewState: new state of the RTC reference clock. * This parameter can be: ENABLE or DISABLE. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC reference clock detection is enabled * - ERROR: RTC reference clock detection is disabled */ ErrorStatus RTC_RefClockCmd(FunctionalState NewState) { ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Set Initialization mode */ if (RTC_EnterInitMode() == ERROR) { status = ERROR; } else { if (NewState != DISABLE) { /* Enable the RTC reference clock detection */ RTC->CR |= RTC_CR_REFCKON; } else { /* Disable the RTC reference clock detection */ RTC->CR &= ~RTC_CR_REFCKON; } /* Exit Initialization mode */ RTC_ExitInitMode(); status = SUCCESS; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return status; } /** * @brief Enables or Disables the Bypass Shadow feature. * @note When the Bypass Shadow is enabled the calendar value are taken * directly from the Calendar counter. * @param NewState: new state of the Bypass Shadow feature. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RTC_BypassShadowCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; if (NewState != DISABLE) { /* Set the BYPSHAD bit */ RTC->CR |= (uint8_t)RTC_CR_BYPSHAD; } else { /* Reset the BYPSHAD bit */ RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @} */ /** @defgroup RTC_Group2 Time and Date configuration functions * @brief Time and Date configuration functions * @verbatim =============================================================================== ##### Time and Date configuration functions ##### =============================================================================== [..] This section provide functions allowing to program and read the RTC Calendar (Time and Date). @endverbatim * @{ */ /** * @brief Set the RTC current time. * @param RTC_Format: specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_Format_BIN: Binary data format * @arg RTC_Format_BCD: BCD data format * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains * the time configuration information for the RTC. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Time register is configured * - ERROR: RTC Time register is not configured */ ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) { uint32_t tmpreg = 0; ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_RTC_FORMAT(RTC_Format)); if (RTC_Format == RTC_Format_BIN) { if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) { assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours)); assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); } else { RTC_TimeStruct->RTC_H12 = 0x00; assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours)); } assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes)); assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds)); } else { if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) { tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); assert_param(IS_RTC_HOUR12(tmpreg)); assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); } else { RTC_TimeStruct->RTC_H12 = 0x00; assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours))); } assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds))); } /* Check the input parameters format */ if (RTC_Format != RTC_Format_BIN) { tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \ ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \ ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \ ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); } else { tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \ ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \ ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \ (((uint32_t)RTC_TimeStruct->RTC_H12) << 16)); } /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Set Initialization mode */ if (RTC_EnterInitMode() == ERROR) { status = ERROR; } else { /* Set the RTC_TR register */ RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); /* Exit Initialization mode */ RTC_ExitInitMode(); /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) { if(RTC_WaitForSynchro() == ERROR) { status = ERROR; } else { status = SUCCESS; } } else { status = SUCCESS; } } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return status; } /** * @brief Fills each RTC_TimeStruct member with its default value * (Time = 00h:00min:00sec). * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be * initialized. * @retval None */ void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct) { /* Time = 00h:00min:00sec */ RTC_TimeStruct->RTC_H12 = RTC_H12_AM; RTC_TimeStruct->RTC_Hours = 0; RTC_TimeStruct->RTC_Minutes = 0; RTC_TimeStruct->RTC_Seconds = 0; } /** * @brief Get the RTC current Time. * @param RTC_Format: specifies the format of the returned parameters. * This parameter can be one of the following values: * @arg RTC_Format_BIN: Binary data format * @arg RTC_Format_BCD: BCD data format * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will * contain the returned current time configuration. * @retval None */ void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RTC_FORMAT(RTC_Format)); /* Get the RTC_TR register */ tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); /* Fill the structure fields with the read parameters */ RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); /* Check the input parameters format */ if (RTC_Format == RTC_Format_BIN) { /* Convert the structure parameters to Binary format */ RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes); RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); } } /** * @brief Gets the RTC current Calendar Sub seconds value. * @note This function freeze the Time and Date registers after reading the * SSR register. * @param None * @retval RTC current Calendar Sub seconds value. */ uint32_t RTC_GetSubSecond(void) { uint32_t tmpreg = 0; /* Get sub seconds values from the correspondent registers*/ tmpreg = (uint32_t)(RTC->SSR); /* Read DR register to unfroze calendar registers */ (void) (RTC->DR); return (tmpreg); } /** * @brief Set the RTC current date. * @param RTC_Format: specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_Format_BIN: Binary data format * @arg RTC_Format_BCD: BCD data format * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains * the date configuration information for the RTC. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Date register is configured * - ERROR: RTC Date register is not configured */ ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) { uint32_t tmpreg = 0; ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_RTC_FORMAT(RTC_Format)); if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10)) { RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A; } if (RTC_Format == RTC_Format_BIN) { assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year)); assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month)); assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date)); } else { assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year))); tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); assert_param(IS_RTC_MONTH(tmpreg)); tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); assert_param(IS_RTC_DATE(tmpreg)); } assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay)); /* Check the input parameters format */ if (RTC_Format != RTC_Format_BIN) { tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \ (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \ ((uint32_t)RTC_DateStruct->RTC_Date) | \ (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); } else { tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \ ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \ ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \ ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13)); } /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Set Initialization mode */ if (RTC_EnterInitMode() == ERROR) { status = ERROR; } else { /* Set the RTC_DR register */ RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK); /* Exit Initialization mode */ RTC_ExitInitMode(); /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) { if(RTC_WaitForSynchro() == ERROR) { status = ERROR; } else { status = SUCCESS; } } else { status = SUCCESS; } } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return status; } /** * @brief Fills each RTC_DateStruct member with its default value * (Monday, January 01 xx00). * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be * initialized. * @retval None */ void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct) { /* Monday, January 01 xx00 */ RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday; RTC_DateStruct->RTC_Date = 1; RTC_DateStruct->RTC_Month = RTC_Month_January; RTC_DateStruct->RTC_Year = 0; } /** * @brief Get the RTC current date. * @param RTC_Format: specifies the format of the returned parameters. * This parameter can be one of the following values: * @arg RTC_Format_BIN: Binary data format * @arg RTC_Format_BCD: BCD data format * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will * contain the returned current date configuration. * @retval None */ void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RTC_FORMAT(RTC_Format)); /* Get the RTC_TR register */ tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); /* Fill the structure fields with the read parameters */ RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU)); RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); /* Check the input parameters format */ if (RTC_Format == RTC_Format_BIN) { /* Convert the structure parameters to Binary format */ RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year); RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); } } /** * @} */ /** @defgroup RTC_Group3 Alarms configuration functions * @brief Alarms (Alarm A and Alarm B) configuration functions * @verbatim =============================================================================== ##### Alarms A and B configuration functions ##### =============================================================================== [..] This section provide functions allowing to program and read the RTC Alarms. @endverbatim * @{ */ /** * @brief Set the specified RTC Alarm. * @note The Alarm register can only be written when the corresponding Alarm * is disabled (Use the RTC_AlarmCmd(DISABLE)). * @param RTC_Format: specifies the format of the returned parameters. * This parameter can be one of the following values: * @arg RTC_Format_BIN: Binary data format * @arg RTC_Format_BCD: BCD data format * @param RTC_Alarm: specifies the alarm to be configured. * This parameter can be one of the following values: * @arg RTC_Alarm_A: to select Alarm A * @arg RTC_Alarm_B: to select Alarm B * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that * contains the alarm configuration parameters. * @retval None */ void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RTC_FORMAT(RTC_Format)); assert_param(IS_RTC_ALARM(RTC_Alarm)); assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)); if (RTC_Format == RTC_Format_BIN) { if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) { assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); } else { RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); } assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)); assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)); if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); } else { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); } } else { if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) { tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours); assert_param(IS_RTC_HOUR12(tmpreg)); assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); } else { RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours))); } assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds))); if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) { tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); } else { tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); } } /* Check the input parameters format */ if (RTC_Format != RTC_Format_BIN) { tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); } else { tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \ ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); } /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Configure the Alarm register */ if (RTC_Alarm == RTC_Alarm_A) { RTC->ALRMAR = (uint32_t)tmpreg; } else { RTC->ALRMBR = (uint32_t)tmpreg; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @brief Fills each RTC_AlarmStruct member with its default value * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = * all fields are masked). * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which * will be initialized. * @retval None */ void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct) { /* Alarm Time Settings : Time = 00h:00mn:00sec */ RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM; RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0; RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0; RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0; /* Alarm Date Settings : Date = 1st day of the month */ RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1; /* Alarm Masks Settings : Mask = all fields are not masked */ RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None; } /** * @brief Get the RTC Alarm value and masks. * @param RTC_Format: specifies the format of the output parameters. * This parameter can be one of the following values: * @arg RTC_Format_BIN: Binary data format * @arg RTC_Format_BCD: BCD data format * @param RTC_Alarm: specifies the alarm to be read. * This parameter can be one of the following values: * @arg RTC_Alarm_A: to select Alarm A * @arg RTC_Alarm_B: to select Alarm B * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will * contains the output alarm configuration values. * @retval None */ void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RTC_FORMAT(RTC_Format)); assert_param(IS_RTC_ALARM(RTC_Alarm)); /* Get the RTC_ALRMxR register */ if (RTC_Alarm == RTC_Alarm_A) { tmpreg = (uint32_t)(RTC->ALRMAR); } else { tmpreg = (uint32_t)(RTC->ALRMBR); } /* Fill the structure with the read parameters */ RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \ RTC_ALRMAR_HU)) >> 16); RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \ RTC_ALRMAR_MNU)) >> 8); RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \ RTC_ALRMAR_SU)); RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All); if (RTC_Format == RTC_Format_BIN) { RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ RTC_AlarmTime.RTC_Hours); RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ RTC_AlarmTime.RTC_Minutes); RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ RTC_AlarmTime.RTC_Seconds); RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); } } /** * @brief Enables or disables the specified RTC Alarm. * @param RTC_Alarm: specifies the alarm to be configured. * This parameter can be any combination of the following values: * @arg RTC_Alarm_A: to select Alarm A * @arg RTC_Alarm_B: to select Alarm B * @param NewState: new state of the specified alarm. * This parameter can be: ENABLE or DISABLE. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Alarm is enabled/disabled * - ERROR: RTC Alarm is not enabled/disabled */ ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) { __IO uint32_t alarmcounter = 0x00; uint32_t alarmstatus = 0x00; ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Configure the Alarm state */ if (NewState != DISABLE) { RTC->CR |= (uint32_t)RTC_Alarm; status = SUCCESS; } else { /* Disable the Alarm in RTC_CR register */ RTC->CR &= (uint32_t)~RTC_Alarm; /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ do { alarmstatus = RTC->ISR & (RTC_Alarm >> 8); alarmcounter++; } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET) { status = ERROR; } else { status = SUCCESS; } } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return status; } /** * @brief Configure the RTC AlarmA/B Sub seconds value and mask.* * @note This function is performed only when the Alarm is disabled. * @param RTC_Alarm: specifies the alarm to be configured. * This parameter can be one of the following values: * @arg RTC_Alarm_A: to select Alarm A * @arg RTC_Alarm_B: to select Alarm B * @param RTC_AlarmSubSecondValue: specifies the Sub seconds value. * This parameter can be a value from 0 to 0x00007FFF. * @param RTC_AlarmSubSecondMask: specifies the Sub seconds Mask. * This parameter can be any combination of the following values: * @arg RTC_AlarmSubSecondMask_All : All Alarm SS fields are masked. * There is no comparison on sub seconds for Alarm. * @arg RTC_AlarmSubSecondMask_SS14_1 : SS[14:1] are don't care in Alarm comparison. * Only SS[0] is compared * @arg RTC_AlarmSubSecondMask_SS14_2 : SS[14:2] are don't care in Alarm comparison. * Only SS[1:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_3 : SS[14:3] are don't care in Alarm comparison. * Only SS[2:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_4 : SS[14:4] are don't care in Alarm comparison. * Only SS[3:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_5 : SS[14:5] are don't care in Alarm comparison. * Only SS[4:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_6 : SS[14:6] are don't care in Alarm comparison. * Only SS[5:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_7 : SS[14:7] are don't care in Alarm comparison. * Only SS[6:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_8 : SS[14:8] are don't care in Alarm comparison. * Only SS[7:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_9 : SS[14:9] are don't care in Alarm comparison. * Only SS[8:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison. * Only SS[9:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison. * Only SS[10:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison. * Only SS[11:0] are compared * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison. * Only SS[12:0] are compared * @arg RTC_AlarmSubSecondMask_SS14 : SS[14] is don't care in Alarm comparison. * Only SS[13:0] are compared * @arg RTC_AlarmSubSecondMask_None : SS[14:0] are compared and must match * to activate alarm * @retval None */ void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RTC_ALARM(RTC_Alarm)); assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue)); assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Configure the Alarm A or Alarm B Sub Second registers */ tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask); if (RTC_Alarm == RTC_Alarm_A) { /* Configure the Alarm A Sub Second register */ RTC->ALRMASSR = tmpreg; } else { /* Configure the Alarm B Sub Second register */ RTC->ALRMBSSR = tmpreg; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @brief Gets the RTC Alarm Sub seconds value. * @param RTC_Alarm: specifies the alarm to be read. * This parameter can be one of the following values: * @arg RTC_Alarm_A: to select Alarm A * @arg RTC_Alarm_B: to select Alarm B * @param None * @retval RTC Alarm Sub seconds value. */ uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) { uint32_t tmpreg = 0; /* Get the RTC_ALRMxR register */ if (RTC_Alarm == RTC_Alarm_A) { tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS); } else { tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS); } return (tmpreg); } /** * @} */ /** @defgroup RTC_Group4 WakeUp Timer configuration functions * @brief WakeUp Timer configuration functions * @verbatim =============================================================================== ##### WakeUp Timer configuration functions ##### =============================================================================== [..] This section provide functions allowing to program and read the RTC WakeUp. @endverbatim * @{ */ /** * @brief Configures the RTC Wakeup clock source. * @note The WakeUp Clock source can only be changed when the RTC WakeUp * is disabled (Use the RTC_WakeUpCmd(DISABLE)). * @param RTC_WakeUpClock: Wakeup Clock source. * This parameter can be one of the following values: * @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16 * @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8 * @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4 * @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2 * @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE * @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE * @retval None */ void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock) { /* Check the parameters */ assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Clear the Wakeup Timer clock source bits in CR register */ RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL; /* Configure the clock source */ RTC->CR |= (uint32_t)RTC_WakeUpClock; /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @brief Configures the RTC Wakeup counter. * @note The RTC WakeUp counter can only be written when the RTC WakeUp * is disabled (Use the RTC_WakeUpCmd(DISABLE)). * @param RTC_WakeUpCounter: specifies the WakeUp counter. * This parameter can be a value from 0x0000 to 0xFFFF. * @retval None */ void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) { /* Check the parameters */ assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Configure the Wakeup Timer counter */ RTC->WUTR = (uint32_t)RTC_WakeUpCounter; /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @brief Returns the RTC WakeUp timer counter value. * @param None * @retval The RTC WakeUp Counter value. */ uint32_t RTC_GetWakeUpCounter(void) { /* Get the counter value */ return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT)); } /** * @brief Enables or Disables the RTC WakeUp timer. * @param NewState: new state of the WakeUp timer. * This parameter can be: ENABLE or DISABLE. * @retval None */ ErrorStatus RTC_WakeUpCmd(FunctionalState NewState) { __IO uint32_t wutcounter = 0x00; uint32_t wutwfstatus = 0x00; ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; if (NewState != DISABLE) { /* Enable the Wakeup Timer */ RTC->CR |= (uint32_t)RTC_CR_WUTE; status = SUCCESS; } else { /* Disable the Wakeup Timer */ RTC->CR &= (uint32_t)~RTC_CR_WUTE; /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ do { wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; wutcounter++; } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) { status = ERROR; } else { status = SUCCESS; } } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return status; } /** * @} */ /** @defgroup RTC_Group5 Daylight Saving configuration functions * @brief Daylight Saving configuration functions * @verbatim =============================================================================== ##### Daylight Saving configuration functions ##### =============================================================================== [..] This section provide functions allowing to configure the RTC DayLight Saving. @endverbatim * @{ */ /** * @brief Adds or substract one hour from the current time. * @param RTC_DayLightSaveOperation: the value of hour adjustment. * This parameter can be one of the following values: * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time) * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time) * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit * in CR register to store the operation. * This parameter can be one of the following values: * @arg RTC_StoreOperation_Reset: BCK Bit Reset * @arg RTC_StoreOperation_Set: BCK Bit Set * @retval None */ void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) { /* Check the parameters */ assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Clear the bits to be configured */ RTC->CR &= (uint32_t)~(RTC_CR_BCK); /* Configure the RTC_CR register */ RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @brief Returns the RTC Day Light Saving stored operation. * @param None * @retval RTC Day Light Saving stored operation. * - RTC_StoreOperation_Reset * - RTC_StoreOperation_Set */ uint32_t RTC_GetStoreOperation(void) { return (RTC->CR & RTC_CR_BCK); } /** * @} */ /** @defgroup RTC_Group6 Output pin Configuration function * @brief Output pin Configuration function * @verbatim =============================================================================== ##### Output pin Configuration function ##### =============================================================================== [..] This section provide functions allowing to configure the RTC Output source. @endverbatim * @{ */ /** * @brief Configures the RTC output source (AFO_ALARM). * @param RTC_Output: Specifies which signal will be routed to the RTC output. * This parameter can be one of the following values: * @arg RTC_Output_Disable: No output selected * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output * @param RTC_OutputPolarity: Specifies the polarity of the output signal. * This parameter can be one of the following: * @arg RTC_OutputPolarity_High: The output pin is high when the * ALRAF/ALRBF/WUTF is high (depending on OSEL) * @arg RTC_OutputPolarity_Low: The output pin is low when the * ALRAF/ALRBF/WUTF is high (depending on OSEL) * @retval None */ void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) { /* Check the parameters */ assert_param(IS_RTC_OUTPUT(RTC_Output)); assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Clear the bits to be configured */ RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL); /* Configure the output selection and polarity */ RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity); /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @} */ /** @defgroup RTC_Group7 Digital Calibration configuration functions * @brief Coarse Calibration configuration functions * @verbatim =============================================================================== ##### Digital Calibration configuration functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Configures the Coarse calibration parameters. * @param RTC_CalibSign: specifies the sign of the coarse calibration value. * This parameter can be one of the following values: * @arg RTC_CalibSign_Positive: The value sign is positive * @arg RTC_CalibSign_Negative: The value sign is negative * @param Value: value of coarse calibration expressed in ppm (coded on 5 bits). * * @note This Calibration value should be between 0 and 63 when using negative * sign with a 2-ppm step. * * @note This Calibration value should be between 0 and 126 when using positive * sign with a 4-ppm step. * * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Coarse calibration are initialized * - ERROR: RTC Coarse calibration are not initialized */ ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value) { ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign)); assert_param(IS_RTC_CALIB_VALUE(Value)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Set Initialization mode */ if (RTC_EnterInitMode() == ERROR) { status = ERROR; } else { /* Set the coarse calibration value */ RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value); /* Exit Initialization mode */ RTC_ExitInitMode(); status = SUCCESS; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return status; } /** * @brief Enables or disables the Coarse calibration process. * @param NewState: new state of the Coarse calibration. * This parameter can be: ENABLE or DISABLE. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Coarse calibration are enabled/disabled * - ERROR: RTC Coarse calibration are not enabled/disabled */ ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState) { ErrorStatus status = ERROR; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Set Initialization mode */ if (RTC_EnterInitMode() == ERROR) { status = ERROR; } else { if (NewState != DISABLE) { /* Enable the Coarse Calibration */ RTC->CR |= (uint32_t)RTC_CR_DCE; } else { /* Disable the Coarse Calibration */ RTC->CR &= (uint32_t)~RTC_CR_DCE; } /* Exit Initialization mode */ RTC_ExitInitMode(); status = SUCCESS; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return status; } /** * @brief Enables or disables the RTC clock to be output through the relative pin. * @param NewState: new state of the digital calibration Output. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RTC_CalibOutputCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; if (NewState != DISABLE) { /* Enable the RTC clock output */ RTC->CR |= (uint32_t)RTC_CR_COE; } else { /* Disable the RTC clock output */ RTC->CR &= (uint32_t)~RTC_CR_COE; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). * @param RTC_CalibOutput : Select the Calibration output Selection . * This parameter can be one of the following values: * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. * @arg RTC_CalibOutput_1Hz : A signal has a regular waveform at 1Hz. * @retval None */ void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput) { /* Check the parameters */ assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /*clear flags before configuration */ RTC->CR &= (uint32_t)~(RTC_CR_COSEL); /* Configure the RTC_CR register */ RTC->CR |= (uint32_t)RTC_CalibOutput; /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @brief Configures the Smooth Calibration Settings. * @param RTC_SmoothCalibPeriod : Select the Smooth Calibration Period. * This parameter can be can be one of the following values: * @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration period is 32s. * @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration period is 16s. * @arg RTC_SmoothCalibPeriod_8sec : The smooth calibartion period is 8s. * @param RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit. * This parameter can be one of the following values: * @arg RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK puls every 2**11 pulses. * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added. * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. * This parameter can be one any value from 0 to 0x000001FF. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Calib registers are configured * - ERROR: RTC Calib registers are not configured */ ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, uint32_t RTC_SmoothCalibPlusPulses, uint32_t RTC_SmouthCalibMinusPulsesValue) { ErrorStatus status = ERROR; uint32_t recalpfcount = 0; /* Check the parameters */ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod)); assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses)); assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* check if a calibration is pending*/ if ((RTC->ISR & RTC_ISR_RECALPF) != RESET) { /* wait until the Calibration is completed*/ while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT)) { recalpfcount++; } } /* check if the calibration pending is completed or if there is no calibration operation at all*/ if ((RTC->ISR & RTC_ISR_RECALPF) == RESET) { /* Configure the Smooth calibration settings */ RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue); status = SUCCESS; } else { status = ERROR; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return (ErrorStatus)(status); } /** * @} */ /** @defgroup RTC_Group8 TimeStamp configuration functions * @brief TimeStamp configuration functions * @verbatim =============================================================================== ##### TimeStamp configuration functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or Disables the RTC TimeStamp functionality with the * specified time stamp pin stimulating edge. * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is * activated. * This parameter can be one of the following: * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising * edge of the related pin. * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the * falling edge of the related pin. * @param NewState: new state of the TimeStamp. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Get the RTC_CR register and clear the bits to be configured */ tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); /* Get the new configuration */ if (NewState != DISABLE) { tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE); } else { tmpreg |= (uint32_t)(RTC_TimeStampEdge); } /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Configure the Time Stamp TSEDGE and Enable bits */ RTC->CR = (uint32_t)tmpreg; /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @brief Get the RTC TimeStamp value and masks. * @param RTC_Format: specifies the format of the output parameters. * This parameter can be one of the following values: * @arg RTC_Format_BIN: Binary data format * @arg RTC_Format_BCD: BCD data format * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will * contains the TimeStamp time values. * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will * contains the TimeStamp date values. * @retval None */ void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, RTC_DateTypeDef* RTC_StampDateStruct) { uint32_t tmptime = 0, tmpdate = 0; /* Check the parameters */ assert_param(IS_RTC_FORMAT(RTC_Format)); /* Get the TimeStamp time and date registers values */ tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK); tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK); /* Fill the Time structure fields with the read parameters */ RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); /* Fill the Date structure fields with the read parameters */ RTC_StampDateStruct->RTC_Year = 0; RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); /* Check the input parameters format */ if (RTC_Format == RTC_Format_BIN) { /* Convert the Time structure parameters to Binary format */ RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours); RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes); RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds); /* Convert the Date structure parameters to Binary format */ RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month); RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date); RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay); } } /** * @brief Get the RTC timestamp Sub seconds value. * @param None * @retval RTC current timestamp Sub seconds value. */ uint32_t RTC_GetTimeStampSubSecond(void) { /* Get timestamp sub seconds values from the correspondent registers */ return (uint32_t)(RTC->TSSSR); } /** * @} */ /** @defgroup RTC_Group9 Tampers configuration functions * @brief Tampers configuration functions * @verbatim =============================================================================== ##### Tampers configuration functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Configures the select Tamper pin edge. * @param RTC_Tamper: Selected tamper pin. * This parameter can be RTC_Tamper_1. * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that * stimulates tamper event. * This parameter can be one of the following values: * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event. * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event. * @retval None */ void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) { /* Check the parameters */ assert_param(IS_RTC_TAMPER(RTC_Tamper)); assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge) { /* Configure the RTC_TAFCR register */ RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); } else { /* Configure the RTC_TAFCR register */ RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); } } /** * @brief Enables or Disables the Tamper detection. * @param RTC_Tamper: Selected tamper pin. * This parameter can be RTC_Tamper_1. * @param NewState: new state of the tamper pin. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RTC_TAMPER(RTC_Tamper)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected Tamper pin */ RTC->TAFCR |= (uint32_t)RTC_Tamper; } else { /* Disable the selected Tamper pin */ RTC->TAFCR &= (uint32_t)~RTC_Tamper; } } /** * @brief Configures the Tampers Filter. * @param RTC_TamperFilter: Specifies the tampers filter. * This parameter can be one of the following values: * @arg RTC_TamperFilter_Disable: Tamper filter is disabled. * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive * samples at the active level * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive * samples at the active level * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive * samples at the active level * @retval None */ void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter) { /* Check the parameters */ assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter)); /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT); /* Configure the RTC_TAFCR register */ RTC->TAFCR |= (uint32_t)RTC_TamperFilter; } /** * @brief Configures the Tampers Sampling Frequency. * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency. * This parameter can be one of the following values: * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled * with a frequency = RTCCLK / 32768 * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled * with a frequency = RTCCLK / 16384 * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled * with a frequency = RTCCLK / 8192 * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled * with a frequency = RTCCLK / 4096 * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled * with a frequency = RTCCLK / 2048 * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled * with a frequency = RTCCLK / 1024 * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled * with a frequency = RTCCLK / 512 * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled * with a frequency = RTCCLK / 256 * @retval None */ void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq) { /* Check the parameters */ assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq)); /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ); /* Configure the RTC_TAFCR register */ RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq; } /** * @brief Configures the Tampers Pins input Precharge Duration. * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input * Precharge Duration. * This parameter can be one of the following values: * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are precharged before sampling during 1 RTCCLK cycle * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are precharged before sampling during 2 RTCCLK cycle * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are precharged before sampling during 4 RTCCLK cycle * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are precharged before sampling during 8 RTCCLK cycle * @retval None */ void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) { /* Check the parameters */ assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration)); /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */ RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH); /* Configure the RTC_TAFCR register */ RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration; } /** * @brief Enables or Disables the TimeStamp on Tamper Detection Event. * @note The timestamp is valid even the TSE bit in tamper control register * is reset. * @param NewState: new state of the timestamp on tamper event. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Save timestamp on tamper detection event */ RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS; } else { /* Tamper detection does not cause a timestamp to be saved */ RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS; } } /** * @brief Enables or Disables the Precharge of Tamper pin. * @param NewState: new state of tamper pull up. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RTC_TamperPullUpCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable precharge of the selected Tamper pin */ RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; } else { /* Disable precharge of the selected Tamper pin */ RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS; } } /** * @} */ /** @defgroup RTC_Group10 Backup Data Registers configuration functions * @brief Backup Data Registers configuration functions * @verbatim =============================================================================== ##### Backup Data Registers configuration functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Writes a data in a specified RTC Backup data register. * @param RTC_BKP_DR: RTC Backup data Register number. * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to * specify the register. * @param Data: Data to be written in the specified RTC Backup data register. * @retval None */ void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_RTC_BKP(RTC_BKP_DR)); tmp = RTC_BASE + 0x50; tmp += (RTC_BKP_DR * 4); /* Write the specified register */ *(__IO uint32_t *)tmp = (uint32_t)Data; } /** * @brief Reads data from the specified RTC Backup data Register. * @param RTC_BKP_DR: RTC Backup data Register number. * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to * specify the register. * @retval None */ uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_RTC_BKP(RTC_BKP_DR)); tmp = RTC_BASE + 0x50; tmp += (RTC_BKP_DR * 4); /* Read the specified register */ return (*(__IO uint32_t *)tmp); } /** * @} */ /** @defgroup RTC_Group11 RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions * @brief RTC Tamper and TimeStamp Pins Selection and Output Type Config * configuration functions * @verbatim ================================================================================================== ##### RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions ##### ================================================================================================== @endverbatim * @{ */ /** * @brief Selects the RTC Tamper Pin. * @param RTC_TamperPin: specifies the RTC Tamper Pin. * This parameter can be one of the following values: * @arg RTC_TamperPin_PC13: PC13 is selected as RTC Tamper Pin. * @arg RTC_TamperPin_PI8: PI8 is selected as RTC Tamper Pin. * @retval None */ void RTC_TamperPinSelection(uint32_t RTC_TamperPin) { /* Check the parameters */ assert_param(IS_RTC_TAMPER_PIN(RTC_TamperPin)); RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPINSEL); RTC->TAFCR |= (uint32_t)(RTC_TamperPin); } /** * @brief Selects the RTC TimeStamp Pin. * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: * @arg RTC_TimeStampPin_PC13: PC13 is selected as RTC TimeStamp Pin. * @arg RTC_TimeStampPin_PI8: PI8 is selected as RTC TimeStamp Pin. * @retval None */ void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin) { /* Check the parameters */ assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TSINSEL); RTC->TAFCR |= (uint32_t)(RTC_TimeStampPin); } /** * @brief Configures the RTC Output Pin mode. * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode. * This parameter can be one of the following values: * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in * Open Drain mode. * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in * Push Pull mode. * @retval None */ void RTC_OutputTypeConfig(uint32_t RTC_OutputType) { /* Check the parameters */ assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE); RTC->TAFCR |= (uint32_t)(RTC_OutputType); } /** * @} */ /** @defgroup RTC_Group12 Shift control synchronisation functions * @brief Shift control synchronisation functions * @verbatim =============================================================================== ##### Shift control synchronisation functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Configures the Synchronization Shift Control Settings. * @note When REFCKON is set, firmware must not write to Shift control register * @param RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar. * This parameter can be one of the following values : * @arg RTC_ShiftAdd1S_Set : Add one second to the clock calendar. * @arg RTC_ShiftAdd1S_Reset: No effect. * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute. * This parameter can be one any value from 0 to 0x7FFF. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Shift registers are configured * - ERROR: RTC Shift registers are not configured */ ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS) { ErrorStatus status = ERROR; uint32_t shpfcount = 0; /* Check the parameters */ assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S)); assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; /* Check if a Shift is pending*/ if ((RTC->ISR & RTC_ISR_SHPF) != RESET) { /* Wait until the shift is completed*/ while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT)) { shpfcount++; } } /* Check if the Shift pending is completed or if there is no Shift operation at all*/ if ((RTC->ISR & RTC_ISR_SHPF) == RESET) { /* check if the reference clock detection is disabled */ if((RTC->CR & RTC_CR_REFCKON) == RESET) { /* Configure the Shift settings */ RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S); if(RTC_WaitForSynchro() == ERROR) { status = ERROR; } else { status = SUCCESS; } } else { status = ERROR; } } else { status = ERROR; } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; return (ErrorStatus)(status); } /** * @} */ /** @defgroup RTC_Group13 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== [..] All RTC interrupts are connected to the EXTI controller. (+) To enable the RTC Alarm interrupt, the following sequence is required: (++) Configure and enable the EXTI Line 17 in interrupt mode and select the rising edge sensitivity using the EXTI_Init() function. (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init() function. (++) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using the RTC_SetAlarm() and RTC_AlarmCmd() functions. (+) To enable the RTC Wakeup interrupt, the following sequence is required: (++) Configure and enable the EXTI Line 22 in interrupt mode and select the rising edge sensitivity using the EXTI_Init() function. (++) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the NVIC_Init() function. (++) Configure the RTC to generate the RTC wakeup timer event using the RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. (+) To enable the RTC Tamper interrupt, the following sequence is required: (++) Configure and enable the EXTI Line 21 in interrupt mode and select the rising edge sensitivity using the EXTI_Init() function. (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() function. (++) Configure the RTC to detect the RTC tamper event using the RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. (+) To enable the RTC TimeStamp interrupt, the following sequence is required: (++) Configure and enable the EXTI Line 21 in interrupt mode and select the rising edge sensitivity using the EXTI_Init() function. (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() function. (++) Configure the RTC to detect the RTC time stamp event using the RTC_TimeStampCmd() functions. @endverbatim * @{ */ /** * @brief Enables or disables the specified RTC interrupts. * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg RTC_IT_TS: Time Stamp interrupt mask * @arg RTC_IT_WUT: WakeUp Timer interrupt mask * @arg RTC_IT_ALRB: Alarm B interrupt mask * @arg RTC_IT_ALRA: Alarm A interrupt mask * @arg RTC_IT_TAMP: Tamper event interrupt mask * @param NewState: new state of the specified RTC interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_RTC_CONFIG_IT(RTC_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* Disable the write protection for RTC registers */ RTC->WPR = 0xCA; RTC->WPR = 0x53; if (NewState != DISABLE) { /* Configure the Interrupts in the RTC_CR register */ RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE); /* Configure the Tamper Interrupt in the RTC_TAFCR */ RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE); } else { /* Configure the Interrupts in the RTC_CR register */ RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE); /* Configure the Tamper Interrupt in the RTC_TAFCR */ RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE); } /* Enable the write protection for RTC registers */ RTC->WPR = 0xFF; } /** * @brief Checks whether the specified RTC flag is set or not. * @param RTC_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg RTC_FLAG_RECALPF: RECALPF event flag. * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag * @arg RTC_FLAG_TSF: Time Stamp event flag * @arg RTC_FLAG_WUTF: WakeUp Timer flag * @arg RTC_FLAG_ALRBF: Alarm B flag * @arg RTC_FLAG_ALRAF: Alarm A flag * @arg RTC_FLAG_INITF: Initialization mode flag * @arg RTC_FLAG_RSF: Registers Synchronized flag * @arg RTC_FLAG_INITS: Registers Configured flag * @arg RTC_FLAG_SHPF: Shift operation pending flag. * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag * @arg RTC_FLAG_ALRBWF: Alarm B Write flag * @arg RTC_FLAG_ALRAWF: Alarm A write flag * @retval The new state of RTC_FLAG (SET or RESET). */ FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) { FlagStatus bitstatus = RESET; uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); /* Get all the flags */ tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK); /* Return the status of the flag */ if ((tmpreg & RTC_FLAG) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the RTC's pending flags. * @param RTC_FLAG: specifies the RTC flag to clear. * This parameter can be any combination of the following values: * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag * @arg RTC_FLAG_TSF: Time Stamp event flag * @arg RTC_FLAG_WUTF: WakeUp Timer flag * @arg RTC_FLAG_ALRBF: Alarm B flag * @arg RTC_FLAG_ALRAF: Alarm A flag * @arg RTC_FLAG_RSF: Registers Synchronized flag * @retval None */ void RTC_ClearFlag(uint32_t RTC_FLAG) { /* Check the parameters */ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); /* Clear the Flags in the RTC_ISR register */ RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); } /** * @brief Checks whether the specified RTC interrupt has occurred or not. * @param RTC_IT: specifies the RTC interrupt source to check. * This parameter can be one of the following values: * @arg RTC_IT_TS: Time Stamp interrupt * @arg RTC_IT_WUT: WakeUp Timer interrupt * @arg RTC_IT_ALRB: Alarm B interrupt * @arg RTC_IT_ALRA: Alarm A interrupt * @arg RTC_IT_TAMP1: Tamper 1 event interrupt * @retval The new state of RTC_IT (SET or RESET). */ ITStatus RTC_GetITStatus(uint32_t RTC_IT) { ITStatus bitstatus = RESET; uint32_t tmpreg = 0, enablestatus = 0; /* Check the parameters */ assert_param(IS_RTC_GET_IT(RTC_IT)); /* Get the TAMPER Interrupt enable bit and pending bit */ tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE)); /* Get the Interrupt enable Status */ enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15))); /* Get the Interrupt pending bit */ tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4))); /* Get the status of the Interrupt */ if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET)) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the RTC's interrupt pending bits. * @param RTC_IT: specifies the RTC interrupt pending bit to clear. * This parameter can be any combination of the following values: * @arg RTC_IT_TS: Time Stamp interrupt * @arg RTC_IT_WUT: WakeUp Timer interrupt * @arg RTC_IT_ALRB: Alarm B interrupt * @arg RTC_IT_ALRA: Alarm A interrupt * @arg RTC_IT_TAMP1: Tamper 1 event interrupt * @retval None */ void RTC_ClearITPendingBit(uint32_t RTC_IT) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_RTC_CLEAR_IT(RTC_IT)); /* Get the RTC_ISR Interrupt pending bits mask */ tmpreg = (uint32_t)(RTC_IT >> 4); /* Clear the interrupt pending bits in the RTC_ISR register */ RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); } /** * @} */ /** * @brief Converts a 2 digit decimal to BCD format. * @param Value: Byte to be converted. * @retval Converted byte */ static uint8_t RTC_ByteToBcd2(uint8_t Value) { uint8_t bcdhigh = 0; while (Value >= 10) { bcdhigh++; Value -= 10; } return ((uint8_t)(bcdhigh << 4) | Value); } /** * @brief Convert from 2 digit BCD to Binary. * @param Value: BCD value to be converted. * @retval Converted word */ static uint8_t RTC_Bcd2ToByte(uint8_t Value) { uint8_t tmp = 0; tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; return (tmp + (Value & (uint8_t)0x0F)); } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c ================================================ /** ****************************************************************************** * @file stm32f4xx_sai.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Serial Audio Interface (SAI): * + Initialization and Configuration * + Data transfers functions * + DMA transfers management * + Interrupts and flags management * @verbatim =============================================================================== ##### How to use this driver ##### =============================================================================== [..] (#) Enable peripheral clock using the following functions RCC_APB2PeriphClockCmd(RCC_APB2Periph_SAI1, ENABLE) for SAI1 (#) For each SAI Block A/B enable SCK, SD, FS and MCLK GPIO clocks using RCC_AHB1PeriphClockCmd() function. (#) Peripherals alternate function: (++) Connect the pin to the desired peripherals' Alternate Function (AF) using GPIO_PinAFConfig() function. (++) Configure the desired pin in alternate function by: GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd, GPIO_OType and GPIO_Speed members (++) Call GPIO_Init() function -@@- If an external clock source is used then the I2S CKIN pin should be also configured in Alternate function Push-pull pull-up mode. (#) The SAI clock can be generated from different clock source : PLL I2S, PLL SAI or external clock source. (++) The PLL I2S is configured using the following functions RCC_PLLI2SConfig(), RCC_PLLI2SCmd(ENABLE), RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY) and RCC_SAIPLLI2SClkDivConfig() or; (++) The PLL SAI is configured using the following functions RCC_PLLSAIConfig(), RCC_PLLSAICmd(ENABLE), RCC_GetFlagStatus(RCC_FLAG_PLLSAIRDY) and RCC_SAIPLLSAIClkDivConfig()or; (++) External clock source is configured using the function RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the define constant I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. (#) Each SAI Block A or B has its own clock generator to make these two blocks completely independent. The Clock generator is configured using RCC_SAIBlockACLKConfig() and RCC_SAIBlockBCLKConfig() functions. (#) Each SAI Block A or B can be configured separetely : (++) Program the Master clock divider, Audio mode, Protocol, Data Length, Clock Strobing Edge, Synchronous mode, Output drive and FIFO Thresold using SAI_Init() function. In case of master mode, program the Master clock divider (MCKDIV) using the following formula : (+++) MCLK_x = SAI_CK_x / (MCKDIV * 2) with MCLK_x = 256 * FS (+++) FS = SAI_CK_x / (MCKDIV * 2) * 256 (+++) MCKDIV = SAI_CK_x / FS * 512 (++) Program the Frame Length, Frame active Length, FS Definition, FS Polarity, FS Offset using SAI_FrameInit() function. (++) Program the Slot First Bit Offset, Slot Size, Slot Number, Slot Active using SAI_SlotInit() function. (#) Enable the NVIC and the corresponding interrupt using the function SAI_ITConfig() if you need to use interrupt mode. (#) When using the DMA mode (++) Configure the DMA using DMA_Init() function (++) Active the needed channel Request using SAI_DMACmd() function (#) Enable the SAI using the SAI_Cmd() function. (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. (#) The SAI has some specific functions which can be useful depending on the audio protocol selected. (++) Enable Mute mode when the audio block is a transmitter using SAI_MuteModeCmd() function and configure the value transmitted during mute using SAI_MuteValueConfig(). (++) Detect the Mute mode when audio block is a receiver using SAI_MuteFrameCounterConfig(). (++) Enable the MONO mode without any data preprocessing in memory when the number of slot is equal to 2 using SAI_MonoModeConfig() function. (++) Enable data companding algorithm (U law and A law) using SAI_CompandingModeConfig(). (++) Choose the behavior of the SD line in output when an inactive slot is sent on the data line using SAI_TRIStateConfig() function. [..] (@) In master TX mode: enabling the audio block immediately generates the bit clock for the external slaves even if there is no data in the FIFO, However FS signal generation is conditioned by the presence of data in the FIFO. (@) In master RX mode: enabling the audio block immediately generates the bit clock and FS signal for the external slaves. (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior: (+@) First bit Offset <= (SLOT size - Data size) (+@) Data size <= SLOT size (+@) Number of SLOT x SLOT size = Frame length (+@) The number of slots should be even when bit FSDEF in the SAI_xFRCR is set. @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_sai.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup SAI * @brief SAI driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* *SAI registers Masks */ #define CR1_CLEAR_MASK ((uint32_t)0xFF07C010) #define FRCR_CLEAR_MASK ((uint32_t)0xFFF88000) #define SLOTR_CLEAR_MASK ((uint32_t)0x0000F020) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup SAI_Private_Functions * @{ */ /** @defgroup SAI_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This section provides a set of functions allowing to initialize the SAI Audio Block Mode, Audio Protocol, Data size, Synchronization between audio block, Master clock Divider, Fifo threshold, Frame configuration, slot configuration, Tristate mode, Companding mode and Mute mode. [..] The SAI_Init(), SAI_FrameInit() and SAI_SlotInit() functions follows the SAI Block configuration procedures for Master mode and Slave mode (details for these procedures are available in reference manual(RM0090). @endverbatim * @{ */ /** * @brief Deinitialize the SAIx peripheral registers to their default reset values. * @param SAIx: To select the SAIx peripheral, where x can be the different instances * * @retval None */ void SAI_DeInit(SAI_TypeDef* SAIx) { /* Check the parameters */ assert_param(IS_SAI_PERIPH(SAIx)); /* Enable SAI1 reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI1, ENABLE); /* Release SAI1 from reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI1, DISABLE); } /** * @brief Initializes the SAI Block x peripheral according to the specified * parameters in the SAI_InitStruct. * * @note SAI clock is generated from a specific output of the PLLSAI or a specific * output of the PLLI2S or from an alternate function bypassing the PLL I2S. * * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * @param SAI_InitStruct: pointer to a SAI_InitTypeDef structure that * contains the configuration information for the specified SAI Block peripheral. * @retval None */ void SAI_Init(SAI_Block_TypeDef* SAI_Block_x, SAI_InitTypeDef* SAI_InitStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); /* Check the SAI Block parameters */ assert_param(IS_SAI_BLOCK_MODE(SAI_InitStruct->SAI_AudioMode)); assert_param(IS_SAI_BLOCK_PROTOCOL(SAI_InitStruct->SAI_Protocol)); assert_param(IS_SAI_BLOCK_DATASIZE(SAI_InitStruct->SAI_DataSize)); assert_param(IS_SAI_BLOCK_FIRST_BIT(SAI_InitStruct->SAI_FirstBit)); assert_param(IS_SAI_BLOCK_CLOCK_STROBING(SAI_InitStruct->SAI_ClockStrobing)); assert_param(IS_SAI_BLOCK_SYNCHRO(SAI_InitStruct->SAI_Synchro)); assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(SAI_InitStruct->SAI_OUTDRIV)); assert_param(IS_SAI_BLOCK_NODIVIDER(SAI_InitStruct->SAI_NoDivider)); assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(SAI_InitStruct->SAI_MasterDivider)); assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(SAI_InitStruct->SAI_FIFOThreshold)); /* SAI Block_x CR1 Configuration */ /* Get the SAI Block_x CR1 value */ tmpreg = SAI_Block_x->CR1; /* Clear MODE, PRTCFG, DS, LSBFIRST, CKSTR, SYNCEN, OUTDRIV, NODIV, and MCKDIV bits */ tmpreg &= CR1_CLEAR_MASK; /* Configure SAI_Block_x: Audio mode, Protocol, Data Size, first transmitted bit, Clock strobing edge, Synchronization mode, Output drive, Master Divider and FIFO level */ /* Set MODE bits according to SAI_AudioMode value */ /* Set PRTCFG bits according to SAI_Protocol value */ /* Set DS bits according to SAI_DataSize value */ /* Set LSBFIRST bit according to SAI_FirstBit value */ /* Set CKSTR bit according to SAI_ClockStrobing value */ /* Set SYNCEN bit according to SAI_Synchro value */ /* Set OUTDRIV bit according to SAI_OUTDRIV value */ /* Set NODIV bit according to SAI_NoDivider value */ /* Set MCKDIV bits according to SAI_MasterDivider value */ tmpreg |= (uint32_t)(SAI_InitStruct->SAI_AudioMode | SAI_InitStruct->SAI_Protocol | SAI_InitStruct->SAI_DataSize | SAI_InitStruct->SAI_FirstBit | SAI_InitStruct->SAI_ClockStrobing | SAI_InitStruct->SAI_Synchro | SAI_InitStruct->SAI_OUTDRIV | SAI_InitStruct->SAI_NoDivider | (uint32_t)((SAI_InitStruct->SAI_MasterDivider) << 20)); /* Write to SAI_Block_x CR1 */ SAI_Block_x->CR1 = tmpreg; /* SAI Block_x CR2 Configuration */ /* Get the SAIBlock_x CR2 value */ tmpreg = SAI_Block_x->CR2; /* Clear FTH bits */ tmpreg &= ~(SAI_xCR2_FTH); /* Configure the FIFO Level */ /* Set FTH bits according to SAI_FIFOThreshold value */ tmpreg |= (uint32_t)(SAI_InitStruct->SAI_FIFOThreshold); /* Write to SAI_Block_x CR2 */ SAI_Block_x->CR2 = tmpreg; } /** * @brief Initializes the SAI Block Audio frame according to the specified * parameters in the SAI_FrameInitStruct. * * @note this function has no meaning if the AC'97 or SPDIF audio protocol * are selected. * * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * @param SAI_FrameInitStruct: pointer to an SAI_FrameInitTypeDef structure that * contains the configuration of audio frame for a specified SAI Block * @retval None */ void SAI_FrameInit(SAI_Block_TypeDef* SAI_Block_x, SAI_FrameInitTypeDef* SAI_FrameInitStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); /* Check the SAI Block frame parameters */ assert_param(IS_SAI_BLOCK_FRAME_LENGTH(SAI_FrameInitStruct->SAI_FrameLength)); assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(SAI_FrameInitStruct->SAI_ActiveFrameLength)); assert_param(IS_SAI_BLOCK_FS_DEFINITION(SAI_FrameInitStruct->SAI_FSDefinition)); assert_param(IS_SAI_BLOCK_FS_POLARITY(SAI_FrameInitStruct->SAI_FSPolarity)); assert_param(IS_SAI_BLOCK_FS_OFFSET(SAI_FrameInitStruct->SAI_FSOffset)); /* SAI Block_x FRCR Configuration */ /* Get the SAI Block_x FRCR value */ tmpreg = SAI_Block_x->FRCR; /* Clear FRL, FSALL, FSDEF, FSPOL, FSOFF bits */ tmpreg &= FRCR_CLEAR_MASK; /* Configure SAI_Block_x Frame: Frame Length, Active Frame Length, Frame Synchronization Definition, Frame Synchronization Polarity and Frame Synchronization Polarity */ /* Set FRL bits according to SAI_FrameLength value */ /* Set FSALL bits according to SAI_ActiveFrameLength value */ /* Set FSDEF bit according to SAI_FSDefinition value */ /* Set FSPOL bit according to SAI_FSPolarity value */ /* Set FSOFF bit according to SAI_FSOffset value */ tmpreg |= (uint32_t)((uint32_t)(SAI_FrameInitStruct->SAI_FrameLength - 1) | SAI_FrameInitStruct->SAI_FSOffset | SAI_FrameInitStruct->SAI_FSDefinition | SAI_FrameInitStruct->SAI_FSPolarity | (uint32_t)((SAI_FrameInitStruct->SAI_ActiveFrameLength - 1) << 8)); /* Write to SAI_Block_x FRCR */ SAI_Block_x->FRCR = tmpreg; } /** * @brief Initializes the SAI Block audio Slot according to the specified * parameters in the SAI_SlotInitStruct. * * @note this function has no meaning if the AC'97 or SPDIF audio protocol * are selected. * * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * @param SAI_SlotInitStruct: pointer to an SAI_SlotInitTypeDef structure that * contains the configuration of audio slot for a specified SAI Block * @retval None */ void SAI_SlotInit(SAI_Block_TypeDef* SAI_Block_x, SAI_SlotInitTypeDef* SAI_SlotInitStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); /* Check the SAI Block Slot parameters */ assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(SAI_SlotInitStruct->SAI_FirstBitOffset)); assert_param(IS_SAI_BLOCK_SLOT_SIZE(SAI_SlotInitStruct->SAI_SlotSize)); assert_param(IS_SAI_BLOCK_SLOT_NUMBER(SAI_SlotInitStruct->SAI_SlotNumber)); assert_param(IS_SAI_SLOT_ACTIVE(SAI_SlotInitStruct->SAI_SlotActive)); /* SAI Block_x SLOTR Configuration */ /* Get the SAI Block_x SLOTR value */ tmpreg = SAI_Block_x->SLOTR; /* Clear FBOFF, SLOTSZ, NBSLOT, SLOTEN bits */ tmpreg &= SLOTR_CLEAR_MASK; /* Configure SAI_Block_x Slot: First bit offset, Slot size, Number of Slot in audio frame and slots activated in audio frame */ /* Set FBOFF bits according to SAI_FirstBitOffset value */ /* Set SLOTSZ bits according to SAI_SlotSize value */ /* Set NBSLOT bits according to SAI_SlotNumber value */ /* Set SLOTEN bits according to SAI_SlotActive value */ tmpreg |= (uint32_t)(SAI_SlotInitStruct->SAI_FirstBitOffset | SAI_SlotInitStruct->SAI_SlotSize | SAI_SlotInitStruct->SAI_SlotActive | (uint32_t)((SAI_SlotInitStruct->SAI_SlotNumber - 1) << 8)); /* Write to SAI_Block_x SLOTR */ SAI_Block_x->SLOTR = tmpreg; } /** * @brief Fills each SAI_InitStruct member with its default value. * @param SAI_InitStruct: pointer to a SAI_InitTypeDef structure which will * be initialized. * @retval None */ void SAI_StructInit(SAI_InitTypeDef* SAI_InitStruct) { /* Reset SAI init structure parameters values */ /* Initialize the SAI_AudioMode member */ SAI_InitStruct->SAI_AudioMode = SAI_Mode_MasterTx; /* Initialize the SAI_Protocol member */ SAI_InitStruct->SAI_Protocol = SAI_Free_Protocol; /* Initialize the SAI_DataSize member */ SAI_InitStruct->SAI_DataSize = SAI_DataSize_8b; /* Initialize the SAI_FirstBit member */ SAI_InitStruct->SAI_FirstBit = SAI_FirstBit_MSB; /* Initialize the SAI_ClockStrobing member */ SAI_InitStruct->SAI_ClockStrobing = SAI_ClockStrobing_FallingEdge; /* Initialize the SAI_Synchro member */ SAI_InitStruct->SAI_Synchro = SAI_Asynchronous; /* Initialize the SAI_OUTDRIV member */ SAI_InitStruct->SAI_OUTDRIV = SAI_OutputDrive_Disabled; /* Initialize the SAI_NoDivider member */ SAI_InitStruct->SAI_NoDivider = SAI_MasterDivider_Enabled; /* Initialize the SAI_MasterDivider member */ SAI_InitStruct->SAI_MasterDivider = 0; /* Initialize the SAI_FIFOThreshold member */ SAI_InitStruct->SAI_FIFOThreshold = SAI_Threshold_FIFOEmpty; } /** * @brief Fills each SAI_FrameInitStruct member with its default value. * @param SAI_FrameInitStruct: pointer to a SAI_FrameInitTypeDef structure * which will be initialized. * @retval None */ void SAI_FrameStructInit(SAI_FrameInitTypeDef* SAI_FrameInitStruct) { /* Reset SAI Frame init structure parameters values */ /* Initialize the SAI_FrameLength member */ SAI_FrameInitStruct->SAI_FrameLength = 8; /* Initialize the SAI_ActiveFrameLength member */ SAI_FrameInitStruct->SAI_ActiveFrameLength = 1; /* Initialize the SAI_FSDefinition member */ SAI_FrameInitStruct->SAI_FSDefinition = SAI_FS_StartFrame; /* Initialize the SAI_FSPolarity member */ SAI_FrameInitStruct->SAI_FSPolarity = SAI_FS_ActiveLow; /* Initialize the SAI_FSOffset member */ SAI_FrameInitStruct->SAI_FSOffset = SAI_FS_FirstBit; } /** * @brief Fills each SAI_SlotInitStruct member with its default value. * @param SAI_SlotInitStruct: pointer to a SAI_SlotInitTypeDef structure * which will be initialized. * @retval None */ void SAI_SlotStructInit(SAI_SlotInitTypeDef* SAI_SlotInitStruct) { /* Reset SAI Slot init structure parameters values */ /* Initialize the SAI_FirstBitOffset member */ SAI_SlotInitStruct->SAI_FirstBitOffset = 0; /* Initialize the SAI_SlotSize member */ SAI_SlotInitStruct->SAI_SlotSize = SAI_SlotSize_DataSize; /* Initialize the SAI_SlotNumber member */ SAI_SlotInitStruct->SAI_SlotNumber = 1; /* Initialize the SAI_SlotActive member */ SAI_SlotInitStruct->SAI_SlotActive = SAI_Slot_NotActive; } /** * @brief Enables or disables the specified SAI Block peripheral. * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * @param NewState: new state of the SAI_Block_x peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SAI_Cmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected SAI peripheral */ SAI_Block_x->CR1 |= SAI_xCR1_SAIEN; } else { /* Disable the selected SAI peripheral */ SAI_Block_x->CR1 &= ~(SAI_xCR1_SAIEN); } } /** * @brief Configures the mono mode for the selected SAI block. * * @note This function has a meaning only when the number of slot is equal to 2. * * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * @param SAI_MonoMode: specifies the SAI block mono mode. * This parameter can be one of the following values: * @arg SAI_MonoMode : Set mono audio mode * @arg SAI_StreoMode : Set streo audio mode * @retval None */ void SAI_MonoModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_Mono_StreoMode) { /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); assert_param(IS_SAI_BLOCK_MONO_STREO_MODE(SAI_MonoMode)); /* Clear MONO bit */ SAI_Block_x->CR1 &= ~(SAI_xCR1_MONO); /* Set new Mono Mode value */ SAI_Block_x->CR1 |= SAI_MonoMode; } /** * @brief Configures the TRIState managment on data line for the selected SAI block. * * @note This function has a meaning only when the SAI block is configured in transmitter * * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * @param SAI_TRIState: specifies the SAI block TRIState management. * This parameter can be one of the following values: * @arg SAI_Output_NotReleased : SD output line is still drived by the SAI. * @arg SAI_Output_Released : SD output line is released (HI-Z) * @retval None */ void SAI_TRIStateConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_TRIState) { /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(SAI_TRIState)); /* Clear MONO bit */ SAI_Block_x->CR1 &= ~(SAI_xCR1_MONO); /* Set new Mono Mode value */ SAI_Block_x->CR1 |= SAI_MonoMode; } /** * @brief Configures the companding mode for the selected SAI block. * * @note The data expansion or data compression are determined by the state of * SAI block selected (transmitter or receiver). * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * @param SAI_CompandingMode: specifies the SAI block companding mode. * This parameter can be one of the following values: * @arg SAI_NoCompanding : no companding algorithm set * @arg SAI_ULaw_1CPL_Companding : Set U law (algorithm 1's complement representation) * @arg SAI_ALaw_1CPL_Companding : Set A law (algorithm 1's complement repesentation) * @arg SAI_ULaw_2CPL_Companding : Set U law (algorithm 2's complement representation) * @arg SAI_ALaw_2CPL_Companding : Set A law (algorithm 2's complement repesentation) * @retval None */ void SAI_CompandingModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_CompandingMode) { /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); assert_param(IS_SAI_BLOCK_COMPANDING_MODE(SAI_CompandingMode)); /* Clear Companding Mode bits */ SAI_Block_x->CR2 &= ~(SAI_xCR2_COMP); /* Set new Companding Mode value */ SAI_Block_x->CR2 |= SAI_CompandingMode; } /** * @brief Enables or disables the Mute mode for the selected SAI block. * * @note This function has a meaning only when the audio block is transmitter * @note Mute mode is applied for an entire frame for all the valid slot * It becomes active at the end of an audio frame when set somewhere in a frame. * Mute mode exit occurs at the end of the frame in which the bit MUTE has been set. * * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * @param NewState: new state of the SAIx block. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SAI_MuteModeCmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected SAI block mute mode */ SAI_Block_x->CR2 |= SAI_xCR2_MUTE; } else { /* Disable the selected SAI SS output */ SAI_Block_x->CR2 &= ~(SAI_xCR2_MUTE); } } /** * @brief Configure the mute value for the selected SAI block. * * @note This function has a meaning only when the audio block is transmitter * @note the configuration last value sent during mute mode has only a meaning * when the number of slot is lower or equal to 2 and if the MUTE bit is set. * * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * @param SAI_MuteValue: specifies the SAI block mute value. * This parameter can be one of the following values: * @arg SAI_ZeroValue : bit value 0 is sent during Mute Mode * @arg SAI_LastSentValue : Last value is sent during Mute Mode * @retval None */ void SAI_MuteValueConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteValue) { /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); assert_param(IS_SAI_BLOCK_MUTE_VALUE(SAI_MuteValue)); /* Clear Mute value bits */ SAI_Block_x->CR2 &= ~(SAI_xCR2_MUTEVAL); /* Set new Mute value */ SAI_Block_x->CR2 |= SAI_MuteValue; } /** * @brief Enables or disables the Mute mode for the selected SAI block. * * @note This function has a meaning only when the audio block is Receiver * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * @param SAI_MuteCounter: specifies the SAI block mute value. * This parameter can be a number between 0 and 63. * @retval None */ void SAI_MuteFrameCounterConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteCounter) { /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); assert_param(IS_SAI_BLOCK_MUTE_COUNTER(SAI_MuteCounter)); /* Clear Mute value bits */ SAI_Block_x->CR2 &= ~(SAI_xCR2_MUTECNT); /* Set new Mute value */ SAI_Block_x->CR2 |= (SAI_MuteCounter << 7); } /** * @brief Reinitialize the FIFO pointer * * @note The FIFO pointers can be reinitialized at anytime The data present * into the FIFO, if it is not empty, will be lost. * * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * @param NewState: new state of the selected SAI TI communication mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SAI_FlushFIFO(SAI_Block_TypeDef* SAI_Block_x) { /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); /* FIFO flush */ SAI_Block_x->CR2 |= SAI_xCR2_FFLUSH; } /** * @} */ /** @defgroup SAI_Group2 Data transfers functions * @brief Data transfers functions * @verbatim =============================================================================== ##### Data transfers functions ##### =============================================================================== [..] This section provides a set of functions allowing to manage the SAI data transfers. [..] In reception, data are received and then stored into an internal FIFO while In transmission, data are first stored into an internal FIFO before being transmitted. [..] The read access of the SAI_xDR register can be done using the SAI_ReceiveData() function and returns the Rx buffered value. Whereas a write access to the SAI_DR can be done using SAI_SendData() function and stores the written data into Tx buffer. @endverbatim * @{ */ /** * @brief Returns the most recent received data by the SAI block x peripheral. * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * * @retval The value of the received data. */ uint32_t SAI_ReceiveData(SAI_Block_TypeDef* SAI_Block_x) { /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); /* Return the data in the DR register */ return SAI_Block_x->DR; } /** * @brief Transmits a Data through the SAI block x peripheral. * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * * @param Data: Data to be transmitted. * @retval None */ void SAI_SendData(SAI_Block_TypeDef* SAI_Block_x, uint32_t Data) { /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); /* Write in the DR register the data to be sent */ SAI_Block_x->DR = Data; } /** * @} */ /** @defgroup SAI_Group3 DMA transfers management functions * @brief DMA transfers management functions * @verbatim =============================================================================== ##### DMA transfers management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the SAI Block x DMA interface. * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * @param NewState: new state of the selected SAI block DMA transfer request. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected SAI block mute mode */ SAI_Block_x->CR1 |= SAI_xCR1_DMAEN; } else { /* Disable the selected SAI SS output */ SAI_Block_x->CR1 &= ~(SAI_xCR1_DMAEN); } } /** * @} */ /** @defgroup SAI_Group4 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== [..] This section provides a set of functions allowing to configure the SAI Interrupts sources and check or clear the flags or pending bits status. The user should identify which mode will be used in his application to manage the communication: Polling mode, Interrupt mode or DMA mode. *** Polling Mode *** ==================== [..] In Polling Mode, the SAI communication can be managed by 7 flags: (#) SAI_FLAG_FREQ : to indicate if there is a FIFO Request to write or to read. (#) SAI_FLAG_MUTEDET : to indicate if a MUTE frame detected (#) SAI_FLAG_OVRUDR : to indicate if an Overrun or Underrun error occur (#) SAI_FLAG_AFSDET : to indicate if there is the detection of a audio frame synchronisation (FS) earlier than expected (#) SAI_FLAG_LFSDET : to indicate if there is the detection of a audio frame synchronisation (FS) later than expected (#) SAI_FLAG_CNRDY : to indicate if the codec is not ready to communicate during the reception of the TAG 0 (slot0) of the AC97 audio frame (#) SAI_FLAG_WCKCFG: to indicate if wrong clock configuration in master mode error occurs. [..] In this Mode it is advised to use the following functions: (+) FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); (+) void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); *** Interrupt Mode *** ====================== [..] In Interrupt Mode, the SAI communication can be managed by 7 interrupt sources and 7 pending bits: (+) Pending Bits: (##) SAI_IT_FREQ : to indicate if there is a FIFO Request to write or to read. (##) SAI_IT_MUTEDET : to indicate if a MUTE frame detected. (##) SAI_IT_OVRUDR : to indicate if an Overrun or Underrun error occur. (##) SAI_IT_AFSDET : to indicate if there is the detection of a audio frame synchronisation (FS) earlier than expected. (##) SAI_IT_LFSDET : to indicate if there is the detection of a audio frame synchronisation (FS) later than expected. (##) SAI_IT_CNRDY : to indicate if the codec is not ready to communicate during the reception of the TAG 0 (slot0) of the AC97 audio frame. (##) SAI_IT_WCKCFG: to indicate if wrong clock configuration in master mode error occurs. (+) Interrupt Source: (##) SAI_IT_FREQ : specifies the interrupt source for FIFO Request. (##) SAI_IT_MUTEDET : specifies the interrupt source for MUTE frame detected. (##) SAI_IT_OVRUDR : specifies the interrupt source for overrun or underrun error. (##) SAI_IT_AFSDET : specifies the interrupt source for anticipated frame synchronization detection interrupt. (##) SAI_IT_LFSDET : specifies the interrupt source for late frame synchronization detection interrupt. (##) SAI_IT_CNRDY : specifies the interrupt source for codec not ready interrupt (##) SAI_IT_WCKCFG: specifies the interrupt source for wrong clock configuration interrupt. [..] In this Mode it is advised to use the following functions: (+) void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState); (+) ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); (+) void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); *** DMA Mode *** ================ [..] In DMA Mode, each SAI audio block has an independent DMA interface in order to read or to write into the SAI_xDR register (to hit the internal FIFO). There is one DMA channel by audio block following basic DMA request/acknowledge protocol. [..] In this Mode it is advised to use the following function: (+) void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); [..] This section provides also functions allowing to (+) Check the SAI Block enable status (+)Check the FIFO status *** SAI Block Enable status *** =============================== [..] After disabling a SAI Block, it is recommended to check (or wait until) the SAI Block is effectively disabled. If a Block is disabled while an audio frame transfer is ongoing the current frame will be transferred and the block will be effectively disabled only at the end of audio frame. To monitor this state it is possible to use the following function: (+) FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x); *** SAI Block FIFO status *** ============================= [..] It is possible to monitor the FIFO status when a transfer is ongoing using the following function: (+) uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x); @endverbatim * @{ */ /** * @brief Enables or disables the specified SAI Block interrupts. * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * @param SAI_IT: specifies the SAI interrupt source to be enabled or disabled. * This parameter can be one of the following values: * @arg SAI_IT_FREQ: FIFO Request interrupt mask * @arg SAI_IT_MUTEDET: MUTE detection interrupt mask * @arg SAI_IT_OVRUDR: overrun/underrun interrupt mask * @arg SAI_IT_AFSDET: anticipated frame synchronization detection * interrupt mask * @arg SAI_IT_LFSDET: late frame synchronization detection interrupt * mask * @arg SAI_IT_CNRDY: codec not ready interrupt mask * @arg SAI_IT_WCKCFG: wrong clock configuration interrupt mask * @param NewState: new state of the specified SAI interrupt. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_SAI_BLOCK_CONFIG_IT(SAI_IT)); if (NewState != DISABLE) { /* Enable the selected SAI Block interrupt */ SAI_Block_x->IMR |= SAI_IT; } else { /* Disable the selected SAI Block interrupt */ SAI_Block_x->IMR &= ~(SAI_IT); } } /** * @brief Checks whether the specified SAI block x flag is set or not. * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * @param SAI_FLAG: specifies the SAI block flag to check. * This parameter can be one of the following values: * @arg SAI_FLAG_FREQ: FIFO Request flag. * @arg SAI_FLAG_MUTEDET: MUTE detection flag. * @arg SAI_FLAG_OVRUDR: overrun/underrun flag. * @arg SAI_FLAG_WCKCFG: wrong clock configuration flag. * @arg SAI_FLAG_CNRDY: codec not ready flag. * @arg SAI_FLAG_AFSDET: anticipated frame synchronization detection flag. * @arg SAI_FLAG_LFSDET: late frame synchronization detection flag. * @retval The new state of SAI_FLAG (SET or RESET). */ FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); assert_param(IS_SAI_BLOCK_GET_FLAG(SAI_FLAG)); /* Check the status of the specified SAI flag */ if ((SAI_Block_x->SR & SAI_FLAG) != (uint32_t)RESET) { /* SAI_FLAG is set */ bitstatus = SET; } else { /* SAI_FLAG is reset */ bitstatus = RESET; } /* Return the SAI_FLAG status */ return bitstatus; } /** * @brief Clears the specified SAI Block x flag. * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * @param SAI_FLAG: specifies the SAI block flag to check. * This parameter can be one of the following values: * @arg SAI_FLAG_MUTEDET: MUTE detection flag. * @arg SAI_FLAG_OVRUDR: overrun/underrun flag. * @arg SAI_FLAG_WCKCFG: wrong clock configuration flag. * @arg SAI_FLAG_CNRDY: codec not ready flag. * @arg SAI_FLAG_AFSDET: anticipated frame synchronization detection flag. * @arg SAI_FLAG_LFSDET: late frame synchronization detection flag. * * @note FREQ (FIFO Request) flag is cleared : * - When the audio block is transmitter and the FIFO is full or the FIFO * has one data (one buffer mode) depending the bit FTH in the * SAI_xCR2 register. * - When the audio block is receiver and the FIFO is not empty * * @retval None */ void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG) { /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); assert_param(IS_SAI_BLOCK_CLEAR_FLAG(SAI_FLAG)); /* Clear the selected SAI Block flag */ SAI_Block_x->CLRFR |= SAI_FLAG; } /** * @brief Checks whether the specified SAI Block x interrupt has occurred or not. * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * @param SAI_IT: specifies the SAI interrupt source to be enabled or disabled. * This parameter can be one of the following values: * @arg SAI_IT_FREQ: FIFO Request interrupt * @arg SAI_IT_MUTEDET: MUTE detection interrupt * @arg SAI_IT_OVRUDR: overrun/underrun interrupt * @arg SAI_IT_AFSDET: anticipated frame synchronization detection interrupt * @arg SAI_IT_LFSDET: late frame synchronization detection interrupt * @arg SAI_IT_CNRDY: codec not ready interrupt * @arg SAI_IT_WCKCFG: wrong clock configuration interrupt * * @retval The new state of SAI_IT (SET or RESET). */ ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT) { ITStatus bitstatus = RESET; uint32_t enablestatus = 0; /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); assert_param(IS_SAI_BLOCK_CONFIG_IT(SAI_IT)); /* Get the SAI_IT enable bit status */ enablestatus = (SAI_Block_x->IMR & SAI_IT) ; /* Check the status of the specified SAI interrupt */ if (((SAI_Block_x->SR & SAI_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) { /* SAI_IT is set */ bitstatus = SET; } else { /* SAI_IT is reset */ bitstatus = RESET; } /* Return the SAI_IT status */ return bitstatus; } /** * @brief Clears the SAI Block x interrupt pending bit. * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * @param SAI_IT: specifies the SAI Block interrupt pending bit to clear. * This parameter can be one of the following values: * @arg SAI_IT_MUTEDET: MUTE detection interrupt. * @arg SAI_IT_OVRUDR: overrun/underrun interrupt. * @arg SAI_IT_WCKCFG: wrong clock configuration interrupt. * @arg SAI_IT_CNRDY: codec not ready interrupt. * @arg SAI_IT_AFSDET: anticipated frame synchronization detection interrupt. * @arg SAI_IT_LFSDET: late frame synchronization detection interrupt. * * @note FREQ (FIFO Request) flag is cleared : * - When the audio block is transmitter and the FIFO is full or the FIFO * has one data (one buffer mode) depending the bit FTH in the * SAI_xCR2 register. * - When the audio block is receiver and the FIFO is not empty * * @retval None */ void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT) { /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); assert_param(IS_SAI_BLOCK_CONFIG_IT(SAI_IT)); /* Clear the selected SAI Block x interrupt pending bit */ SAI_Block_x->CLRFR |= SAI_IT; } /** * @brief Returns the status of EN bit for the specified SAI Block x. * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * * @note After disabling a SAI Block, it is recommended to check (or wait until) * the SAI Block is effectively disabled. If a Block is disabled while * an audio frame transfer is ongoing, the current frame will be * transferred and the block will be effectively disabled only at * the end of audio frame. * * @retval Current state of the DMAy Streamx (ENABLE or DISABLE). */ FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x) { FunctionalState state = DISABLE; /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); if ((SAI_Block_x->CR1 & (uint32_t)SAI_xCR1_SAIEN) != 0) { /* The selected SAI Block x EN bit is set (audio frame transfer is ongoing) */ state = ENABLE; } else { /* The selected SAI Block x EN bit is cleared (SAI Block is disabled and all transfers are complete) */ state = DISABLE; } return state; } /** * @brief Returns the current SAI Block x FIFO filled level. * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. * * @retval The FIFO filling state. * - SAI_FIFOStatus_Empty: when FIFO is empty * - SAI_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full * and not empty. * - SAI_FIFOStatus_1QuarterFull: if more than 1 quarter-full. * - SAI_FIFOStatus_HalfFull: if more than 1 half-full. * - SAI_FIFOStatus_3QuartersFull: if more than 3 quarters-full. * - SAI_FIFOStatus_Full: when FIFO is full */ uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); /* Get the FIFO level bits */ tmpreg = (uint32_t)((SAI_Block_x->SR & SAI_xSR_FLVL)); return tmpreg; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c ================================================ /** ****************************************************************************** * @file stm32f4xx_sdio.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Secure digital input/output interface (SDIO) * peripheral: * + Initialization and Configuration * + Command path state machine (CPSM) management * + Data path state machine (DPSM) management * + SDIO IO Cards mode management * + CE-ATA mode management * + DMA transfers management * + Interrupts and flags management * @verbatim =================================================================== ##### How to use this driver ##### =================================================================== [..] (#) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL (PLL48CLK). Before to start working with SDIO peripheral make sure that the PLL is well configured. The SDIO peripheral uses two clock signals: (++) SDIO adapter clock (SDIOCLK = 48 MHz) (++) APB2 bus clock (PCLK2) -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition: Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)) (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE). (#) According to the SDIO mode, enable the GPIO clocks using RCC_AHB1PeriphClockCmd() function. The I/O can be one of the following configurations: (++) 1-bit data length: SDIO_CMD, SDIO_CK and D0. (++) 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0]. (++) 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0]. (#) Peripheral alternate function: (++) Connect the pin to the desired peripherals' Alternate Function (AF) using GPIO_PinAFConfig() function (++) Configure the desired pin in alternate function by: GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd, GPIO_OType and GPIO_Speed members (++) Call GPIO_Init() function (#) Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, hardware, flow control and the Clock Divider using the SDIO_Init() function. (#) Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) function. (#) Enable the clock using the SDIO_ClockCmd() function. (#) Enable the NVIC and the corresponding interrupt using the function SDIO_ITConfig() if you need to use interrupt mode. (#) When using the DMA mode (++) Configure the DMA using DMA_Init() function (++) Active the needed channel Request using SDIO_DMACmd() function (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. (#) To control the CPSM (Command Path State Machine) and send commands to the card use the SDIO_SendCommand(), SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has to fill the command structure (pointer to SDIO_CmdInitTypeDef) according to the selected command to be sent. The parameters that should be filled are: (++) Command Argument (++) Command Index (++) Command Response type (++) Command Wait (++) CPSM Status (Enable or Disable). -@@- To check if the command is well received, read the SDIO_CMDRESP register using the SDIO_GetCommandResponse(). The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the SDIO_GetResponse() function. (#) To control the DPSM (Data Path State Machine) and send/receive data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions. *** Read Operations *** ======================= [..] (#) First, user has to fill the data structure (pointer to SDIO_DataInitTypeDef) according to the selected data type to be received. The parameters that should be filled are: (++) Data TimeOut (++) Data Length (++) Data Block size (++) Data Transfer direction: should be from card (To SDIO) (++) Data Transfer mode (++) DPSM Status (Enable or Disable) (#) Configure the SDIO resources to receive the data from the card according to selected transfer mode (Refer to Step 8, 9 and 10). (#) Send the selected Read command (refer to step 11). (#) Use the SDIO flags/interrupts to check the transfer status. *** Write Operations *** ======================== [..] (#) First, user has to fill the data structure (pointer to SDIO_DataInitTypeDef) according to the selected data type to be received. The parameters that should be filled are: (++) Data TimeOut (++) Data Length (++) Data Block size (++) Data Transfer direction: should be to card (To CARD) (++) Data Transfer mode (++) DPSM Status (Enable or Disable) (#) Configure the SDIO resources to send the data to the card according to selected transfer mode (Refer to Step 8, 9 and 10). (#) Send the selected Write command (refer to step 11). (#) Use the SDIO flags/interrupts to check the transfer status. @endverbatim * * ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_sdio.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup SDIO * @brief SDIO driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* ------------ SDIO registers bit address in the alias region ----------- */ #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) /* --- CLKCR Register ---*/ /* Alias word address of CLKEN bit */ #define CLKCR_OFFSET (SDIO_OFFSET + 0x04) #define CLKEN_BitNumber 0x08 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) /* --- CMD Register ---*/ /* Alias word address of SDIOSUSPEND bit */ #define CMD_OFFSET (SDIO_OFFSET + 0x0C) #define SDIOSUSPEND_BitNumber 0x0B #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) /* Alias word address of ENCMDCOMPL bit */ #define ENCMDCOMPL_BitNumber 0x0C #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) /* Alias word address of NIEN bit */ #define NIEN_BitNumber 0x0D #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) /* Alias word address of ATACMD bit */ #define ATACMD_BitNumber 0x0E #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) /* --- DCTRL Register ---*/ /* Alias word address of DMAEN bit */ #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) #define DMAEN_BitNumber 0x03 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) /* Alias word address of RWSTART bit */ #define RWSTART_BitNumber 0x08 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) /* Alias word address of RWSTOP bit */ #define RWSTOP_BitNumber 0x09 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) /* Alias word address of RWMOD bit */ #define RWMOD_BitNumber 0x0A #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) /* Alias word address of SDIOEN bit */ #define SDIOEN_BitNumber 0x0B #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) /* ---------------------- SDIO registers bit mask ------------------------ */ /* --- CLKCR Register ---*/ /* CLKCR register clear mask */ #define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) /* --- PWRCTRL Register ---*/ /* SDIO PWRCTRL Mask */ #define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) /* --- DCTRL Register ---*/ /* SDIO DCTRL Clear Mask */ #define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) /* --- CMD Register ---*/ /* CMD Register clear mask */ #define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) /* SDIO RESP Registers Address */ #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup SDIO_Private_Functions * @{ */ /** @defgroup SDIO_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Deinitializes the SDIO peripheral registers to their default reset values. * @param None * @retval None */ void SDIO_DeInit(void) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE); } /** * @brief Initializes the SDIO peripheral according to the specified * parameters in the SDIO_InitStruct. * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure * that contains the configuration information for the SDIO peripheral. * @retval None */ void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); /*---------------------------- SDIO CLKCR Configuration ------------------------*/ /* Get the SDIO CLKCR value */ tmpreg = SDIO->CLKCR; /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ tmpreg &= CLKCR_CLEAR_MASK; /* Set CLKDIV bits according to SDIO_ClockDiv value */ /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ /* Set BYPASS bit according to SDIO_ClockBypass value */ /* Set WIDBUS bits according to SDIO_BusWide value */ /* Set NEGEDGE bits according to SDIO_ClockEdge value */ /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); /* Write to SDIO CLKCR */ SDIO->CLKCR = tmpreg; } /** * @brief Fills each SDIO_InitStruct member with its default value. * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which * will be initialized. * @retval None */ void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) { /* SDIO_InitStruct members default value */ SDIO_InitStruct->SDIO_ClockDiv = 0x00; SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; } /** * @brief Enables or disables the SDIO Clock. * @param NewState: new state of the SDIO Clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_ClockCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; } /** * @brief Sets the power status of the controller. * @param SDIO_PowerState: new state of the Power state. * This parameter can be one of the following values: * @arg SDIO_PowerState_OFF: SDIO Power OFF * @arg SDIO_PowerState_ON: SDIO Power ON * @retval None */ void SDIO_SetPowerState(uint32_t SDIO_PowerState) { /* Check the parameters */ assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); SDIO->POWER = SDIO_PowerState; } /** * @brief Gets the power status of the controller. * @param None * @retval Power status of the controller. The returned value can be one of the * following values: * - 0x00: Power OFF * - 0x02: Power UP * - 0x03: Power ON */ uint32_t SDIO_GetPowerState(void) { return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); } /** * @} */ /** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions * @brief Command path state machine (CPSM) management functions * @verbatim =============================================================================== ##### Command path state machine (CPSM) management functions ##### =============================================================================== This section provide functions allowing to program and read the Command path state machine (CPSM). @endverbatim * @{ */ /** * @brief Initializes the SDIO Command according to the specified * parameters in the SDIO_CmdInitStruct and send the command. * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef * structure that contains the configuration information for the SDIO * command. * @retval None */ void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); /*---------------------------- SDIO ARG Configuration ------------------------*/ /* Set the SDIO Argument value */ SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; /*---------------------------- SDIO CMD Configuration ------------------------*/ /* Get the SDIO CMD value */ tmpreg = SDIO->CMD; /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ tmpreg &= CMD_CLEAR_MASK; /* Set CMDINDEX bits according to SDIO_CmdIndex value */ /* Set WAITRESP bits according to SDIO_Response value */ /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ /* Set CPSMEN bits according to SDIO_CPSM value */ tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; /* Write to SDIO CMD */ SDIO->CMD = tmpreg; } /** * @brief Fills each SDIO_CmdInitStruct member with its default value. * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef * structure which will be initialized. * @retval None */ void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) { /* SDIO_CmdInitStruct members default value */ SDIO_CmdInitStruct->SDIO_Argument = 0x00; SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; } /** * @brief Returns command index of last command for which response received. * @param None * @retval Returns the command index of the last command response received. */ uint8_t SDIO_GetCommandResponse(void) { return (uint8_t)(SDIO->RESPCMD); } /** * @brief Returns response received from the card for the last command. * @param SDIO_RESP: Specifies the SDIO response register. * This parameter can be one of the following values: * @arg SDIO_RESP1: Response Register 1 * @arg SDIO_RESP2: Response Register 2 * @arg SDIO_RESP3: Response Register 3 * @arg SDIO_RESP4: Response Register 4 * @retval The Corresponding response register value. */ uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) { __IO uint32_t tmp = 0; /* Check the parameters */ assert_param(IS_SDIO_RESP(SDIO_RESP)); tmp = SDIO_RESP_ADDR + SDIO_RESP; return (*(__IO uint32_t *) tmp); } /** * @} */ /** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions * @brief Data path state machine (DPSM) management functions * @verbatim =============================================================================== ##### Data path state machine (DPSM) management functions ##### =============================================================================== This section provide functions allowing to program and read the Data path state machine (DPSM). @endverbatim * @{ */ /** * @brief Initializes the SDIO data path according to the specified * parameters in the SDIO_DataInitStruct. * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure * that contains the configuration information for the SDIO command. * @retval None */ void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); /*---------------------------- SDIO DTIMER Configuration ---------------------*/ /* Set the SDIO Data TimeOut value */ SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; /*---------------------------- SDIO DLEN Configuration -----------------------*/ /* Set the SDIO DataLength value */ SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; /*---------------------------- SDIO DCTRL Configuration ----------------------*/ /* Get the SDIO DCTRL value */ tmpreg = SDIO->DCTRL; /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ tmpreg &= DCTRL_CLEAR_MASK; /* Set DEN bit according to SDIO_DPSM value */ /* Set DTMODE bit according to SDIO_TransferMode value */ /* Set DTDIR bit according to SDIO_TransferDir value */ /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; /* Write to SDIO DCTRL */ SDIO->DCTRL = tmpreg; } /** * @brief Fills each SDIO_DataInitStruct member with its default value. * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure * which will be initialized. * @retval None */ void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) { /* SDIO_DataInitStruct members default value */ SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; SDIO_DataInitStruct->SDIO_DataLength = 0x00; SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; } /** * @brief Returns number of remaining data bytes to be transferred. * @param None * @retval Number of remaining data bytes to be transferred */ uint32_t SDIO_GetDataCounter(void) { return SDIO->DCOUNT; } /** * @brief Read one data word from Rx FIFO. * @param None * @retval Data received */ uint32_t SDIO_ReadData(void) { return SDIO->FIFO; } /** * @brief Write one data word to Tx FIFO. * @param Data: 32-bit data word to write. * @retval None */ void SDIO_WriteData(uint32_t Data) { SDIO->FIFO = Data; } /** * @brief Returns the number of words left to be written to or read from FIFO. * @param None * @retval Remaining number of words. */ uint32_t SDIO_GetFIFOCount(void) { return SDIO->FIFOCNT; } /** * @} */ /** @defgroup SDIO_Group4 SDIO IO Cards mode management functions * @brief SDIO IO Cards mode management functions * @verbatim =============================================================================== ##### SDIO IO Cards mode management functions ##### =============================================================================== This section provide functions allowing to program and read the SDIO IO Cards. @endverbatim * @{ */ /** * @brief Starts the SD I/O Read Wait operation. * @param NewState: new state of the Start SDIO Read Wait operation. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_StartSDIOReadWait(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; } /** * @brief Stops the SD I/O Read Wait operation. * @param NewState: new state of the Stop SDIO Read Wait operation. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_StopSDIOReadWait(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; } /** * @brief Sets one of the two options of inserting read wait interval. * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. * This parameter can be: * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 * @retval None */ void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) { /* Check the parameters */ assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; } /** * @brief Enables or disables the SD I/O Mode Operation. * @param NewState: new state of SDIO specific operation. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_SetSDIOOperation(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; } /** * @brief Enables or disables the SD I/O Mode suspend command sending. * @param NewState: new state of the SD I/O Mode suspend command. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; } /** * @} */ /** @defgroup SDIO_Group5 CE-ATA mode management functions * @brief CE-ATA mode management functions * @verbatim =============================================================================== ##### CE-ATA mode management functions ##### =============================================================================== This section provide functions allowing to program and read the CE-ATA card. @endverbatim * @{ */ /** * @brief Enables or disables the command completion signal. * @param NewState: new state of command completion signal. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_CommandCompletionCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; } /** * @brief Enables or disables the CE-ATA interrupt. * @param NewState: new state of CE-ATA interrupt. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_CEATAITCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); } /** * @brief Sends CE-ATA command (CMD61). * @param NewState: new state of CE-ATA command. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_SendCEATACmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; } /** * @} */ /** @defgroup SDIO_Group6 DMA transfers management functions * @brief DMA transfers management functions * @verbatim =============================================================================== ##### DMA transfers management functions ##### =============================================================================== This section provide functions allowing to program SDIO DMA transfer. @endverbatim * @{ */ /** * @brief Enables or disables the SDIO DMA request. * @param NewState: new state of the selected SDIO DMA request. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_DMACmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; } /** * @} */ /** @defgroup SDIO_Group7 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the SDIO interrupts. * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide * bus mode interrupt * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt * @arg SDIO_IT_TXACT: Data transmit in progress interrupt * @arg SDIO_IT_RXACT: Data receive in progress interrupt * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt * @param NewState: new state of the specified SDIO interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_SDIO_IT(SDIO_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the SDIO interrupts */ SDIO->MASK |= SDIO_IT; } else { /* Disable the SDIO interrupts */ SDIO->MASK &= ~SDIO_IT; } } /** * @brief Checks whether the specified SDIO flag is set or not. * @param SDIO_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) * @arg SDIO_FLAG_CTIMEOUT: Command response timeout * @arg SDIO_FLAG_DTIMEOUT: Data timeout * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDIO_FLAG_CMDACT: Command transfer in progress * @arg SDIO_FLAG_TXACT: Data transmit in progress * @arg SDIO_FLAG_RXACT: Data receive in progress * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 * @retval The new state of SDIO_FLAG (SET or RESET). */ FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_SDIO_FLAG(SDIO_FLAG)); if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the SDIO's pending flags. * @param SDIO_FLAG: specifies the flag to clear. * This parameter can be one or a combination of the following values: * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) * @arg SDIO_FLAG_CTIMEOUT: Command response timeout * @arg SDIO_FLAG_DTIMEOUT: Data timeout * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 * @retval None */ void SDIO_ClearFlag(uint32_t SDIO_FLAG) { /* Check the parameters */ assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); SDIO->ICR = SDIO_FLAG; } /** * @brief Checks whether the specified SDIO interrupt has occurred or not. * @param SDIO_IT: specifies the SDIO interrupt source to check. * This parameter can be one of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide * bus mode interrupt * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt * @arg SDIO_IT_TXACT: Data transmit in progress interrupt * @arg SDIO_IT_RXACT: Data receive in progress interrupt * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt * @retval The new state of SDIO_IT (SET or RESET). */ ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) { ITStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_SDIO_GET_IT(SDIO_IT)); if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the SDIO's interrupt pending bits. * @param SDIO_IT: specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide * bus mode interrupt * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 * @retval None */ void SDIO_ClearITPendingBit(uint32_t SDIO_IT) { /* Check the parameters */ assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); SDIO->ICR = SDIO_IT; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c ================================================ /** ****************************************************************************** * @file stm32f4xx_spi.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Serial peripheral interface (SPI): * + Initialization and Configuration * + Data transfers functions * + Hardware CRC Calculation * + DMA transfers management * + Interrupts and flags management * @verbatim =================================================================== ##### How to use this driver ##### =================================================================== [..] (#) Enable peripheral clock using the following functions RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1 RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI4 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI5 RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI6. (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd() function. In I2S mode, if an external clock source is used then the I2S CKIN pin GPIO clock should also be enabled. (#) Peripherals alternate function: (++) Connect the pin to the desired peripherals' Alternate Function (AF) using GPIO_PinAFConfig() function (++) Configure the desired pin in alternate function by: GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd, GPIO_OType and GPIO_Speed members (++) Call GPIO_Init() function In I2S mode, if an external clock source is used then the I2S CKIN pin should be also configured in Alternate function Push-pull pull-up mode. (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() function. In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity using I2S_Init() function. For I2S mode, make sure that either: (++) I2S PLL is configured using the functions RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), RCC_PLLI2SCmd(ENABLE) and RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY); or (++) External clock source is configured using the function RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the define constant I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. (#) Enable the NVIC and the corresponding interrupt using the function SPI_ITConfig() if you need to use interrupt mode. (#) When using the DMA mode (++) Configure the DMA using DMA_Init() function (++) Active the needed channel Request using SPI_I2S_DMACmd() function (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using I2S_Cmd(). (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. (#) Optionally, you can enable/configure the following parameters without re-initialization (i.e there is no need to call again SPI_Init() function): (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) is programmed as Data direction parameter using the SPI_Init() function it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx using the SPI_BiDirectionalLineConfig() function. (++) When SPI_NSS_Soft is selected as Slave Select Management parameter using the SPI_Init() function it can be possible to manage the NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. (++) Reconfigure the data size using the SPI_DataSizeConfig() function (++) Enable or disable the SS output using the SPI_SSOutputCmd() function (#) To use the CRC Hardware calculation feature refer to the Peripheral CRC hardware Calculation subsection. [..] It is possible to use SPI in I2S full duplex mode, in this case, each SPI peripheral is able to manage sending and receiving data simultaneously using two data lines. Each SPI peripheral has an extended block called I2Sxext (ie. I2S2ext for SPI2 and I2S3ext for SPI3). The extension block is not a full SPI IP, it is used only as I2S slave to implement full duplex mode. The extension block uses the same clock sources as its master. To configure I2S full duplex you have to: (#) Configure SPIx in I2S mode (I2S_Init() function) as described above. (#) Call the I2S_FullDuplexConfig() function using the same strucutre passed to I2S_Init() function. (#) Call I2S_Cmd() for SPIx then for its extended block. (#) To configure interrupts or DMA requests and to get/clear flag status, use I2Sxext instance for the extension block. [..] Functions that can be called with I2Sxext instances are: I2S_Cmd(), I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), SPI_I2S_ClearFlag(), SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit(). Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx): RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE); I2S_StructInit(&I2SInitStruct); I2SInitStruct.Mode = I2S_Mode_MasterTx; I2S_Init(SPI3, &I2SInitStruct); I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct) I2S_Cmd(SPI3, ENABLE); I2S_Cmd(SPI3ext, ENABLE); ... while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) {} SPI_I2S_SendData(SPI3, txdata[i]); ... while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET) {} rxdata[i] = SPI_I2S_ReceiveData(I2S3ext); ... [..] (@) In I2S mode: if an external clock is used as source clock for the I2S, then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should be enabled and set to the value of the source clock frequency (in Hz). (@) In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() just after calling the function SPI_Init(). @endverbatim * ****************************************************************************** * @attention * *

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* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_spi.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup SPI * @brief SPI driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* SPI registers Masks */ #define CR1_CLEAR_MASK ((uint16_t)0x3040) #define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040) /* RCC PLLs masks */ #define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000) #define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0) #define SPI_CR2_FRF ((uint16_t)0x0010) #define SPI_SR_TIFRFE ((uint16_t)0x0100) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup SPI_Private_Functions * @{ */ /** @defgroup SPI_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This section provides a set of functions allowing to initialize the SPI Direction, SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud Rate Prescaler, SPI First Bit and SPI CRC Polynomial. [..] The SPI_Init() function follows the SPI configuration procedures for Master mode and Slave mode (details for these procedures are available in reference manual (RM0090)). @endverbatim * @{ */ /** * @brief De-initialize the SPIx peripheral registers to their default reset values. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 * in SPI mode or 2 or 3 in I2S mode. * * @note The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are de-initialized * when the relative I2S peripheral is de-initialized (the extended block's clock * is managed by the I2S peripheral clock). * * @retval None */ void SPI_I2S_DeInit(SPI_TypeDef* SPIx) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); if (SPIx == SPI1) { /* Enable SPI1 reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); /* Release SPI1 from reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); } else if (SPIx == SPI2) { /* Enable SPI2 reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); /* Release SPI2 from reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); } else if (SPIx == SPI3) { /* Enable SPI3 reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); /* Release SPI3 from reset state */ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); } else if (SPIx == SPI4) { /* Enable SPI4 reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, ENABLE); /* Release SPI4 from reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, DISABLE); } else if (SPIx == SPI5) { /* Enable SPI5 reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, ENABLE); /* Release SPI5 from reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, DISABLE); } else { if (SPIx == SPI6) { /* Enable SPI6 reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, ENABLE); /* Release SPI6 from reset state */ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, DISABLE); } } } /** * @brief Initializes the SPIx peripheral according to the specified * parameters in the SPI_InitStruct. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that * contains the configuration information for the specified SPI peripheral. * @retval None */ void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) { uint16_t tmpreg = 0; /* check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); /* Check the SPI parameters */ assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); /*---------------------------- SPIx CR1 Configuration ------------------------*/ /* Get the SPIx CR1 value */ tmpreg = SPIx->CR1; /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ tmpreg &= CR1_CLEAR_MASK; /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler master/salve mode, CPOL and CPHA */ /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ /* Set LSBFirst bit according to SPI_FirstBit value */ /* Set BR bits according to SPI_BaudRatePrescaler value */ /* Set CPOL bit according to SPI_CPOL value */ /* Set CPHA bit according to SPI_CPHA value */ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); /* Write to SPIx CR1 */ SPIx->CR1 = tmpreg; /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ /* Write to SPIx CRCPOLY */ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; } /** * @brief Initializes the SPIx peripheral according to the specified * parameters in the I2S_InitStruct. * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode). * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that * contains the configuration information for the specified SPI peripheral * configured in I2S mode. * * @note The function calculates the optimal prescaler needed to obtain the most * accurate audio frequency (depending on the I2S clock source, the PLL values * and the product configuration). But in case the prescaler value is greater * than 511, the default value (0x02) will be configured instead. * * @note if an external clock is used as source clock for the I2S, then the define * I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should be enabled and set * to the value of the the source clock frequency (in Hz). * * @retval None */ void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) { uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; uint32_t tmp = 0, i2sclk = 0; #ifndef I2S_EXTERNAL_CLOCK_VAL uint32_t pllm = 0, plln = 0, pllr = 0; #endif /* I2S_EXTERNAL_CLOCK_VAL */ /* Check the I2S parameters */ assert_param(IS_SPI_23_PERIPH(SPIx)); assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; SPIx->I2SPR = 0x0002; /* Get the I2SCFGR register value */ tmpreg = SPIx->I2SCFGR; /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) { i2sodd = (uint16_t)0; i2sdiv = (uint16_t)2; } /* If the requested audio frequency is not the default, compute the prescaler */ else { /* Check the frame length (For the Prescaler computing) *******************/ if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) { /* Packet length is 16 bits */ packetlength = 1; } else { /* Packet length is 32 bits */ packetlength = 2; } /* Get I2S source Clock frequency ****************************************/ /* If an external I2S clock has to be used, this define should be set in the project configuration or in the stm32f4xx_conf.h file */ #ifdef I2S_EXTERNAL_CLOCK_VAL /* Set external clock as I2S clock source */ if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0) { RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC; } /* Set the I2S clock to the external clock value */ i2sclk = I2S_EXTERNAL_CLOCK_VAL; #else /* There is no define for External I2S clock source */ /* Set PLLI2S as I2S clock source */ if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0) { RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC; } /* Get the PLLI2SN value */ plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \ (RCC_PLLI2SCFGR_PLLI2SN >> 6)); /* Get the PLLI2SR value */ pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \ (RCC_PLLI2SCFGR_PLLI2SR >> 28)); /* Get the PLLM value */ pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); /* Get the I2S source clock value */ i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr); #endif /* I2S_EXTERNAL_CLOCK_VAL */ /* Compute the Real divider depending on the MCLK output state, with a floating point */ if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) { /* MCLK output is enabled */ tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); } else { /* MCLK output is disabled */ tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); } /* Remove the flatting point */ tmp = tmp / 10; /* Check the parity of the divider */ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); /* Compute the i2sdiv prescaler */ i2sdiv = (uint16_t)((tmp - i2sodd) / 2); /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ i2sodd = (uint16_t) (i2sodd << 8); } /* Test if the divider is 1 or 0 or greater than 0xFF */ if ((i2sdiv < 2) || (i2sdiv > 0xFF)) { /* Set the default values */ i2sdiv = 2; i2sodd = 0; } /* Write to SPIx I2SPR register the computed value */ SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); /* Configure the I2S with the SPI_InitStruct values */ tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \ (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ (uint16_t)I2S_InitStruct->I2S_CPOL)))); /* Write to SPIx I2SCFGR */ SPIx->I2SCFGR = tmpreg; } /** * @brief Fills each SPI_InitStruct member with its default value. * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. * @retval None */ void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) { /*--------------- Reset SPI init structure parameters values -----------------*/ /* Initialize the SPI_Direction member */ SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; /* initialize the SPI_Mode member */ SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; /* initialize the SPI_DataSize member */ SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; /* Initialize the SPI_CPOL member */ SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; /* Initialize the SPI_CPHA member */ SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; /* Initialize the SPI_NSS member */ SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; /* Initialize the SPI_BaudRatePrescaler member */ SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; /* Initialize the SPI_FirstBit member */ SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; /* Initialize the SPI_CRCPolynomial member */ SPI_InitStruct->SPI_CRCPolynomial = 7; } /** * @brief Fills each I2S_InitStruct member with its default value. * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized. * @retval None */ void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) { /*--------------- Reset I2S init structure parameters values -----------------*/ /* Initialize the I2S_Mode member */ I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; /* Initialize the I2S_Standard member */ I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; /* Initialize the I2S_DataFormat member */ I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; /* Initialize the I2S_MCLKOutput member */ I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; /* Initialize the I2S_AudioFreq member */ I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; /* Initialize the I2S_CPOL member */ I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; } /** * @brief Enables or disables the specified SPI peripheral. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @param NewState: new state of the SPIx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected SPI peripheral */ SPIx->CR1 |= SPI_CR1_SPE; } else { /* Disable the selected SPI peripheral */ SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); } } /** * @brief Enables or disables the specified SPI peripheral (in I2S mode). * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (or I2Sxext * for full duplex mode). * @param NewState: new state of the SPIx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_SPI_23_PERIPH_EXT(SPIx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected SPI peripheral (in I2S mode) */ SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE; } else { /* Disable the selected SPI peripheral in I2S mode */ SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); } } /** * @brief Configures the data size for the selected SPI. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @param SPI_DataSize: specifies the SPI data size. * This parameter can be one of the following values: * @arg SPI_DataSize_16b: Set data frame format to 16bit * @arg SPI_DataSize_8b: Set data frame format to 8bit * @retval None */ void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_SPI_DATASIZE(SPI_DataSize)); /* Clear DFF bit */ SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; /* Set new DFF bit value */ SPIx->CR1 |= SPI_DataSize; } /** * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. * This parameter can be one of the following values: * @arg SPI_Direction_Tx: Selects Tx transmission direction * @arg SPI_Direction_Rx: Selects Rx receive direction * @retval None */ void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_SPI_DIRECTION(SPI_Direction)); if (SPI_Direction == SPI_Direction_Tx) { /* Set the Tx only mode */ SPIx->CR1 |= SPI_Direction_Tx; } else { /* Set the Rx only mode */ SPIx->CR1 &= SPI_Direction_Rx; } } /** * @brief Configures internally by software the NSS pin for the selected SPI. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. * This parameter can be one of the following values: * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally * @retval None */ void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) { /* Set NSS pin internally by software */ SPIx->CR1 |= SPI_NSSInternalSoft_Set; } else { /* Reset NSS pin internally by software */ SPIx->CR1 &= SPI_NSSInternalSoft_Reset; } } /** * @brief Enables or disables the SS output for the selected SPI. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @param NewState: new state of the SPIx SS output. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected SPI SS output */ SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE; } else { /* Disable the selected SPI SS output */ SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); } } /** * @brief Enables or disables the SPIx/I2Sx DMA interface. * * @note This function can be called only after the SPI_Init() function has * been called. * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA * are not taken into consideration and are configured by hardware * respectively to the TI mode requirements. * * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 * @param NewState: new state of the selected SPI TI communication mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the TI mode for the selected SPI peripheral */ SPIx->CR2 |= SPI_CR2_FRF; } else { /* Disable the TI mode for the selected SPI peripheral */ SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF; } } /** * @brief Configures the full duplex mode for the I2Sx peripheral using its * extension I2Sxext according to the specified parameters in the * I2S_InitStruct. * @param I2Sxext: where x can be 2 or 3 to select the I2S peripheral extension block. * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that * contains the configuration information for the specified I2S peripheral * extension. * * @note The structure pointed by I2S_InitStruct parameter should be the same * used for the master I2S peripheral. In this case, if the master is * configured as transmitter, the slave will be receiver and vice versa. * Or you can force a different mode by modifying the field I2S_Mode to the * value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration. * * @note The I2S full duplex extension can be configured in slave mode only. * * @retval None */ void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct) { uint16_t tmpreg = 0, tmp = 0; /* Check the I2S parameters */ assert_param(IS_I2S_EXT_PERIPH(I2Sxext)); assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK; I2Sxext->I2SPR = 0x0002; /* Get the I2SCFGR register value */ tmpreg = I2Sxext->I2SCFGR; /* Get the mode to be configured for the extended I2S */ if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx)) { tmp = I2S_Mode_SlaveRx; } else { if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx)) { tmp = I2S_Mode_SlaveTx; } } /* Configure the I2S with the SPI_InitStruct values */ tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \ (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ (uint16_t)I2S_InitStruct->I2S_CPOL)))); /* Write to SPIx I2SCFGR */ I2Sxext->I2SCFGR = tmpreg; } /** * @} */ /** @defgroup SPI_Group2 Data transfers functions * @brief Data transfers functions * @verbatim =============================================================================== ##### Data transfers functions ##### =============================================================================== [..] This section provides a set of functions allowing to manage the SPI data transfers. In reception, data are received and then stored into an internal Rx buffer while. In transmission, data are first stored into an internal Tx buffer before being transmitted. [..] The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() function and returns the Rx buffered value. Whereas a write access to the SPI_DR can be done using SPI_I2S_SendData() function and stores the written data into Tx buffer. @endverbatim * @{ */ /** * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @retval The value of the received data. */ uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); /* Return the data in the DR register */ return SPIx->DR; } /** * @brief Transmits a Data through the SPIx/I2Sx peripheral. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param Data: Data to be transmitted. * @retval None */ void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); /* Write in the DR register the data to be sent */ SPIx->DR = Data; } /** * @} */ /** @defgroup SPI_Group3 Hardware CRC Calculation functions * @brief Hardware CRC Calculation functions * @verbatim =============================================================================== ##### Hardware CRC Calculation functions ##### =============================================================================== [..] This section provides a set of functions allowing to manage the SPI CRC hardware calculation [..] SPI communication using CRC is possible through the following procedure: (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() function. (#) Enable the CRC calculation using the SPI_CalculateCRC() function. (#) Enable the SPI using the SPI_Cmd() function (#) Before writing the last data to the TX buffer, set the CRCNext bit using the SPI_TransmitCRC() function to indicate that after transmission of the last data, the CRC should be transmitted. (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT bit is reset. The CRC is also received and compared against the SPI_RXCRCR value. If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt can be generated when the SPI_I2S_IT_ERR interrupt is enabled. [..] (@) It is advised not to read the calculated CRC values during the communication. (@) When the SPI is in slave mode, be careful to enable CRC calculation only when the clock is stable, that is, when the clock is in the steady state. If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive to the SCK slave input clock as soon as CRCEN is set, and this, whatever the value of the SPE bit. (@) With high bitrate frequencies, be careful when transmitting the CRC. As the number of used CPU cycles has to be as low as possible in the CRC transfer phase, it is forbidden to call software functions in the CRC transmission sequence to avoid errors in the last data and CRC reception. In fact, CRCNEXT bit has to be written before the end of the transmission/reception of the last data. (@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the degradation of the SPI speed performance due to CPU accesses impacting the SPI bandwidth. (@) When the STM32F4xx is configured as slave and the NSS hardware mode is used, the NSS pin needs to be kept low between the data phase and the CRC phase. (@) When the SPI is configured in slave mode with the CRC feature enabled, CRC calculation takes place even if a high level is applied on the NSS pin. This may happen for example in case of a multi-slave environment where the communication master addresses slaves alternately. (@) Between a slave de-selection (high level on NSS) and a new slave selection (low level on NSS), the CRC value should be cleared on both master and slave sides in order to resynchronize the master and slave for their respective CRC calculation. (@) To clear the CRC, follow the procedure below: (#@) Disable SPI using the SPI_Cmd() function (#@) Disable the CRC calculation using the SPI_CalculateCRC() function. (#@) Enable the CRC calculation using the SPI_CalculateCRC() function. (#@) Enable SPI using the SPI_Cmd() function. @endverbatim * @{ */ /** * @brief Enables or disables the CRC value calculation of the transferred bytes. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @param NewState: new state of the SPIx CRC value calculation. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected SPI CRC calculation */ SPIx->CR1 |= SPI_CR1_CRCEN; } else { /* Disable the selected SPI CRC calculation */ SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); } } /** * @brief Transmit the SPIx CRC value. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @retval None */ void SPI_TransmitCRC(SPI_TypeDef* SPIx) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); /* Enable the selected SPI CRC transmission */ SPIx->CR1 |= SPI_CR1_CRCNEXT; } /** * @brief Returns the transmit or the receive CRC register value for the specified SPI. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @param SPI_CRC: specifies the CRC register to be read. * This parameter can be one of the following values: * @arg SPI_CRC_Tx: Selects Tx CRC register * @arg SPI_CRC_Rx: Selects Rx CRC register * @retval The selected CRC register value.. */ uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) { uint16_t crcreg = 0; /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); assert_param(IS_SPI_CRC(SPI_CRC)); if (SPI_CRC != SPI_CRC_Rx) { /* Get the Tx CRC register */ crcreg = SPIx->TXCRCR; } else { /* Get the Rx CRC register */ crcreg = SPIx->RXCRCR; } /* Return the selected CRC register */ return crcreg; } /** * @brief Returns the CRC Polynomial register value for the specified SPI. * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. * @retval The CRC Polynomial register value. */ uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH(SPIx)); /* Return the CRC polynomial register */ return SPIx->CRCPR; } /** * @} */ /** @defgroup SPI_Group4 DMA transfers management functions * @brief DMA transfers management functions * @verbatim =============================================================================== ##### DMA transfers management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the SPIx/I2Sx DMA interface. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. * This parameter can be any combination of the following values: * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request * @param NewState: new state of the selected SPI DMA transfer request. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); if (NewState != DISABLE) { /* Enable the selected SPI DMA requests */ SPIx->CR2 |= SPI_I2S_DMAReq; } else { /* Disable the selected SPI DMA requests */ SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; } } /** * @} */ /** @defgroup SPI_Group5 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== [..] This section provides a set of functions allowing to configure the SPI Interrupts sources and check or clear the flags or pending bits status. The user should identify which mode will be used in his application to manage the communication: Polling mode, Interrupt mode or DMA mode. *** Polling Mode *** ==================== [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags: (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur (#) I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs. (#) I2S_FLAG_UDR: to indicate an Underrun error occurs. (#) I2S_FLAG_CHSIDE: to indicate Channel Side. (@) Do not use the BSY flag to handle each data transmission or reception. It is better to use the TXE and RXNE flags instead. [..] In this Mode it is advised to use the following functions: (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); *** Interrupt Mode *** ====================== [..] In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources and 7 pending bits: (+) Pending Bits: (##) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register (##) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register (##) SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only) (##) SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only) (##) SPI_I2S_IT_OVR : to indicate if an Overrun error occur (##) I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only). (##) I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only). (+) Interrupt Source: (##) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty interrupt. (##) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not empty interrupt. (##) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. [..] In this Mode it is advised to use the following functions: (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); (+) void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); *** DMA Mode *** ================ [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request [..] In this Mode it is advised to use the following function: (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); @endverbatim * @{ */ /** * @brief Enables or disables the specified SPI/I2S interrupts. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. * This parameter can be one of the following values: * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask * @arg SPI_I2S_IT_ERR: Error interrupt mask * @param NewState: new state of the specified SPI interrupt. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) { uint16_t itpos = 0, itmask = 0 ; /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); /* Get the SPI IT index */ itpos = SPI_I2S_IT >> 4; /* Set the IT mask */ itmask = (uint16_t)1 << (uint16_t)itpos; if (NewState != DISABLE) { /* Enable the selected SPI interrupt */ SPIx->CR2 |= itmask; } else { /* Disable the selected SPI interrupt */ SPIx->CR2 &= (uint16_t)~itmask; } } /** * @brief Checks whether the specified SPIx/I2Sx flag is set or not. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param SPI_I2S_FLAG: specifies the SPI flag to check. * This parameter can be one of the following values: * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. * @arg SPI_I2S_FLAG_BSY: Busy flag. * @arg SPI_I2S_FLAG_OVR: Overrun flag. * @arg SPI_FLAG_MODF: Mode Fault flag. * @arg SPI_FLAG_CRCERR: CRC Error flag. * @arg SPI_I2S_FLAG_TIFRFE: Format Error. * @arg I2S_FLAG_UDR: Underrun Error flag. * @arg I2S_FLAG_CHSIDE: Channel Side flag. * @retval The new state of SPI_I2S_FLAG (SET or RESET). */ FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); /* Check the status of the specified SPI flag */ if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) { /* SPI_I2S_FLAG is set */ bitstatus = SET; } else { /* SPI_I2S_FLAG is reset */ bitstatus = RESET; } /* Return the SPI_I2S_FLAG status */ return bitstatus; } /** * @brief Clears the SPIx CRC Error (CRCERR) flag. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param SPI_I2S_FLAG: specifies the SPI flag to clear. * This function clears only CRCERR flag. * @arg SPI_FLAG_CRCERR: CRC Error flag. * * @note OVR (OverRun error) flag is cleared by software sequence: a read * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). * @note UDR (UnderRun error) flag is cleared by a read operation to * SPI_SR register (SPI_I2S_GetFlagStatus()). * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). * * @retval None */ void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) { /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); /* Clear the selected SPI CRC Error (CRCERR) flag */ SPIx->SR = (uint16_t)~SPI_I2S_FLAG; } /** * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param SPI_I2S_IT: specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. * @arg SPI_I2S_IT_OVR: Overrun interrupt. * @arg SPI_IT_MODF: Mode Fault interrupt. * @arg SPI_IT_CRCERR: CRC Error interrupt. * @arg I2S_IT_UDR: Underrun interrupt. * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt. * @retval The new state of SPI_I2S_IT (SET or RESET). */ ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) { ITStatus bitstatus = RESET; uint16_t itpos = 0, itmask = 0, enablestatus = 0; /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); /* Get the SPI_I2S_IT index */ itpos = 0x01 << (SPI_I2S_IT & 0x0F); /* Get the SPI_I2S_IT IT mask */ itmask = SPI_I2S_IT >> 4; /* Set the IT mask */ itmask = 0x01 << itmask; /* Get the SPI_I2S_IT enable bit status */ enablestatus = (SPIx->CR2 & itmask) ; /* Check the status of the specified SPI interrupt */ if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) { /* SPI_I2S_IT is set */ bitstatus = SET; } else { /* SPI_I2S_IT is reset */ bitstatus = RESET; } /* Return the SPI_I2S_IT status */ return bitstatus; } /** * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. * This function clears only CRCERR interrupt pending bit. * @arg SPI_IT_CRCERR: CRC Error interrupt. * * @note OVR (OverRun Error) interrupt pending bit is cleared by software * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read * operation to SPI_SR register (SPI_I2S_GetITStatus()). * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence: * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable * the SPI). * @retval None */ void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) { uint16_t itpos = 0; /* Check the parameters */ assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); /* Get the SPI_I2S IT index */ itpos = 0x01 << (SPI_I2S_IT & 0x0F); /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ SPIx->SR = (uint16_t)~itpos; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c ================================================ /** ****************************************************************************** * @file stm32f4xx_syscfg.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the SYSCFG peripheral. * @verbatim =============================================================================== ##### How to use this driver ##### =============================================================================== [..] This driver provides functions for: (#) Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig() (#) Swapping the internal flash Bank1 and Bank2 this features is only visible for STM32F42xxx/43xxx devices Devices. (#) Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig() (#) Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig() -@- SYSCFG APB clock must be enabled to get write access to SYSCFG registers, using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_syscfg.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup SYSCFG * @brief SYSCFG driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* ------------ RCC registers bit address in the alias region ----------- */ #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) /* --- MEMRMP Register ---*/ /* Alias word address of UFB_MODE bit */ #define MEMRMP_OFFSET SYSCFG_OFFSET #define UFB_MODE_BitNumber ((uint8_t)0x8) #define UFB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BitNumber * 4)) /* --- PMC Register ---*/ /* Alias word address of MII_RMII_SEL bit */ #define PMC_OFFSET (SYSCFG_OFFSET + 0x04) #define MII_RMII_SEL_BitNumber ((uint8_t)0x17) #define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) /* --- CMPCR Register ---*/ /* Alias word address of CMP_PD bit */ #define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20) #define CMP_PD_BitNumber ((uint8_t)0x00) #define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup SYSCFG_Private_Functions * @{ */ /** * @brief Deinitializes the Alternate Functions (remap and EXTI configuration) * registers to their default reset values. * @param None * @retval None */ void SYSCFG_DeInit(void) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE); } /** * @brief Changes the mapping of the specified pin. * @param SYSCFG_Memory: selects the memory remapping. * This parameter can be one of the following values: * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000 * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F405xx/407xx and STM32F415xx/417xx devices. * @arg SYSCFG_MemoryRemap_FMC: FMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F42xxx/43xxx devices. * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000 * @arg SYSCFG_MemoryRemap_SDRAM: FMC (External SDRAM) mapped at 0x00000000 for STM32F42xxx/43xxx devices. * @retval None */ void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap) { /* Check the parameters */ assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap)); SYSCFG->MEMRMP = SYSCFG_MemoryRemap; } /** * @brief Enables or disables the Interal FLASH Bank Swapping. * * @note This function can be used only for STM32F42xxx/43xxx devices. * * @param NewState: new state of Interal FLASH Bank swapping. * This parameter can be one of the following values: * @arg ENABLE: Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000) * @arg DISABLE:(the default state) Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000) and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) * @retval None */ void SYSCFG_MemorySwappingBank(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) UFB_MODE_BB = (uint32_t)NewState; } /** * @brief Selects the GPIO pin used as EXTI Line. * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for * EXTI lines where x can be (A..K) for STM32F42xxx/43xxx devices, (A..I) * for STM32F405xx/407xx and STM32F415xx/417xx devices or (A, B, C, D and H) * for STM32401xx devices. * * @param EXTI_PinSourcex: specifies the EXTI line to be configured. * This parameter can be EXTI_PinSourcex where x can be (0..15, except * for EXTI_PortSourceGPIOI x can be (0..11) for STM32F405xx/407xx * and STM32F405xx/407xx devices and for EXTI_PortSourceGPIOK x can * be (0..7) for STM32F42xxx/43xxx devices. * * @retval None */ void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) { uint32_t tmp = 0x00; /* Check the parameters */ assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); } /** * @brief Selects the ETHERNET media interface * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. * This parameter can be one of the following values: * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected * @retval None */ void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) { assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); /* Configure MII_RMII selection bit */ *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; } /** * @brief Enables or disables the I/O Compensation Cell. * @note The I/O compensation cell can be used only when the device supply * voltage ranges from 2.4 to 3.6 V. * @param NewState: new state of the I/O Compensation Cell. * This parameter can be one of the following values: * @arg ENABLE: I/O compensation cell enabled * @arg DISABLE: I/O compensation cell power-down mode * @retval None */ void SYSCFG_CompensationCellCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState; } /** * @brief Checks whether the I/O Compensation Cell ready flag is set or not. * @param None * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET) */ FlagStatus SYSCFG_GetCompensationCellStatus(void) { FlagStatus bitstatus = RESET; if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c ================================================ /** ****************************************************************************** * @file stm32f4xx_tim.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the TIM peripheral: * + TimeBase management * + Output Compare management * + Input Capture management * + Advanced-control timers (TIM1 and TIM8) specific features * + Interrupts, DMA and flags management * + Clocks management * + Synchronization management * + Specific interface management * + Specific remapping management * @verbatim =============================================================================== ##### How to use this driver ##### =============================================================================== [..] This driver provides functions to configure and program the TIM of all STM32F4xx devices. These functions are split in 9 groups: (#) TIM TimeBase management: this group includes all needed functions to configure the TM Timebase unit: (++) Set/Get Prescaler (++) Set/Get Autoreload (++) Counter modes configuration (++) Set Clock division (++) Select the One Pulse mode (++) Update Request Configuration (++) Update Disable Configuration (++) Auto-Preload Configuration (++) Enable/Disable the counter (#) TIM Output Compare management: this group includes all needed functions to configure the Capture/Compare unit used in Output compare mode: (++) Configure each channel, independently, in Output Compare mode (++) Select the output compare modes (++) Select the Polarities of each channel (++) Set/Get the Capture/Compare register values (++) Select the Output Compare Fast mode (++) Select the Output Compare Forced mode (++) Output Compare-Preload Configuration (++) Clear Output Compare Reference (++) Select the OCREF Clear signal (++) Enable/Disable the Capture/Compare Channels (#) TIM Input Capture management: this group includes all needed functions to configure the Capture/Compare unit used in Input Capture mode: (++) Configure each channel in input capture mode (++) Configure Channel1/2 in PWM Input mode (++) Set the Input Capture Prescaler (++) Get the Capture/Compare values (#) Advanced-control timers (TIM1 and TIM8) specific features (++) Configures the Break input, dead time, Lock level, the OSSI, the OSSR State and the AOE(automatic output enable) (++) Enable/Disable the TIM peripheral Main Outputs (++) Select the Commutation event (++) Set/Reset the Capture Compare Preload Control bit (#) TIM interrupts, DMA and flags management (++) Enable/Disable interrupt sources (++) Get flags status (++) Clear flags/ Pending bits (++) Enable/Disable DMA requests (++) Configure DMA burst mode (++) Select CaptureCompare DMA request (#) TIM clocks management: this group includes all needed functions to configure the clock controller unit: (++) Select internal/External clock (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx (#) TIM synchronization management: this group includes all needed functions to configure the Synchronization unit: (++) Select Input Trigger (++) Select Output Trigger (++) Select Master Slave Mode (++) ETR Configuration when used as external trigger (#) TIM specific interface management, this group includes all needed functions to use the specific TIM interface: (++) Encoder Interface Configuration (++) Select Hall Sensor (#) TIM specific remapping management includes the Remapping configuration of specific timers @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_tim.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup TIM * @brief TIM driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* ---------------------- TIM registers bit mask ------------------------ */ #define SMCR_ETR_MASK ((uint16_t)0x00FF) #define CCMR_OFFSET ((uint16_t)0x0018) #define CCER_CCE_SET ((uint16_t)0x0001) #define CCER_CCNE_SET ((uint16_t)0x0004) #define CCMR_OC13M_MASK ((uint16_t)0xFF8F) #define CCMR_OC24M_MASK ((uint16_t)0x8FFF) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter); static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter); static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter); static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter); /* Private functions ---------------------------------------------------------*/ /** @defgroup TIM_Private_Functions * @{ */ /** @defgroup TIM_Group1 TimeBase management functions * @brief TimeBase management functions * @verbatim =============================================================================== ##### TimeBase management functions ##### =============================================================================== ##### TIM Driver: how to use it in Timing(Time base) Mode ##### =============================================================================== [..] To use the Timer in Timing(Time base) mode, the following steps are mandatory: (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function (#) Fill the TIM_TimeBaseInitStruct with the desired parameters. (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit with the corresponding configuration (#) Enable the NVIC if you need to generate the update interrupt. (#) Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. -@- All other functions can be used separately to modify, if needed, a specific feature of the Timer. @endverbatim * @{ */ /** * @brief Deinitializes the TIMx peripheral registers to their default reset values. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @retval None */ void TIM_DeInit(TIM_TypeDef* TIMx) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); if (TIMx == TIM1) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); } else if (TIMx == TIM2) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); } else if (TIMx == TIM3) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); } else if (TIMx == TIM4) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); } else if (TIMx == TIM5) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); } else if (TIMx == TIM6) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); } else if (TIMx == TIM7) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); } else if (TIMx == TIM8) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); } else if (TIMx == TIM9) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); } else if (TIMx == TIM10) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); } else if (TIMx == TIM11) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); } else if (TIMx == TIM12) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); } else if (TIMx == TIM13) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); } else { if (TIMx == TIM14) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); } } } /** * @brief Initializes the TIMx Time Base Unit peripheral according to * the specified parameters in the TIM_TimeBaseInitStruct. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure * that contains the configuration information for the specified TIM peripheral. * @retval None */ void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) { uint16_t tmpcr1 = 0; /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); tmpcr1 = TIMx->CR1; if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)|| (TIMx == TIM4) || (TIMx == TIM5)) { /* Select the Counter Mode */ tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS)); tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; } if((TIMx != TIM6) && (TIMx != TIM7)) { /* Set the clock division */ tmpcr1 &= (uint16_t)(~TIM_CR1_CKD); tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; } TIMx->CR1 = tmpcr1; /* Set the Autoreload value */ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; /* Set the Prescaler value */ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; if ((TIMx == TIM1) || (TIMx == TIM8)) { /* Set the Repetition Counter value */ TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; } /* Generate an update event to reload the Prescaler and the repetition counter(only for TIM1 and TIM8) value immediatly */ TIMx->EGR = TIM_PSCReloadMode_Immediate; } /** * @brief Fills each TIM_TimeBaseInitStruct member with its default value. * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef * structure which will be initialized. * @retval None */ void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) { /* Set the default configuration */ TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; } /** * @brief Configures the TIMx Prescaler. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param Prescaler: specifies the Prescaler Register value * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode * This parameter can be one of the following values: * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. * @retval None */ void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); /* Set the Prescaler value */ TIMx->PSC = Prescaler; /* Set or reset the UG Bit */ TIMx->EGR = TIM_PSCReloadMode; } /** * @brief Specifies the TIMx Counter Mode to be used. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_CounterMode: specifies the Counter Mode to be used * This parameter can be one of the following values: * @arg TIM_CounterMode_Up: TIM Up Counting Mode * @arg TIM_CounterMode_Down: TIM Down Counting Mode * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 * @retval None */ void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) { uint16_t tmpcr1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); tmpcr1 = TIMx->CR1; /* Reset the CMS and DIR Bits */ tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS); /* Set the Counter Mode */ tmpcr1 |= TIM_CounterMode; /* Write to TIMx CR1 register */ TIMx->CR1 = tmpcr1; } /** * @brief Sets the TIMx Counter Register value * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param Counter: specifies the Counter register new value. * @retval None */ void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Set the Counter Register value */ TIMx->CNT = Counter; } /** * @brief Sets the TIMx Autoreload Register value * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param Autoreload: specifies the Autoreload register new value. * @retval None */ void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Set the Autoreload Register value */ TIMx->ARR = Autoreload; } /** * @brief Gets the TIMx Counter value. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @retval Counter Register value */ uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Get the Counter Register value */ return TIMx->CNT; } /** * @brief Gets the TIMx Prescaler value. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @retval Prescaler Register value. */ uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Get the Prescaler Register value */ return TIMx->PSC; } /** * @brief Enables or Disables the TIMx Update event. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param NewState: new state of the TIMx UDIS bit * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set the Update Disable Bit */ TIMx->CR1 |= TIM_CR1_UDIS; } else { /* Reset the Update Disable Bit */ TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS; } } /** * @brief Configures the TIMx Update Request Interrupt source. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param TIM_UpdateSource: specifies the Update source. * This parameter can be one of the following values: * @arg TIM_UpdateSource_Global: Source of update is the counter * overflow/underflow or the setting of UG bit, or an update * generation through the slave mode controller. * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow. * @retval None */ void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); if (TIM_UpdateSource != TIM_UpdateSource_Global) { /* Set the URS Bit */ TIMx->CR1 |= TIM_CR1_URS; } else { /* Reset the URS Bit */ TIMx->CR1 &= (uint16_t)~TIM_CR1_URS; } } /** * @brief Enables or disables TIMx peripheral Preload register on ARR. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param NewState: new state of the TIMx peripheral Preload register * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set the ARR Preload Bit */ TIMx->CR1 |= TIM_CR1_ARPE; } else { /* Reset the ARR Preload Bit */ TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE; } } /** * @brief Selects the TIMx's One Pulse Mode. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param TIM_OPMode: specifies the OPM Mode to be used. * This parameter can be one of the following values: * @arg TIM_OPMode_Single * @arg TIM_OPMode_Repetitive * @retval None */ void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); /* Reset the OPM Bit */ TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM; /* Configure the OPM Mode */ TIMx->CR1 |= TIM_OPMode; } /** * @brief Sets the TIMx Clock Division value. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_CKD: specifies the clock division value. * This parameter can be one of the following value: * @arg TIM_CKD_DIV1: TDTS = Tck_tim * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim * @retval None */ void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) { /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_CKD_DIV(TIM_CKD)); /* Reset the CKD Bits */ TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD); /* Set the CKD value */ TIMx->CR1 |= TIM_CKD; } /** * @brief Enables or disables the specified TIM peripheral. * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. * @param NewState: new state of the TIMx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the TIM Counter */ TIMx->CR1 |= TIM_CR1_CEN; } else { /* Disable the TIM Counter */ TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN; } } /** * @} */ /** @defgroup TIM_Group2 Output Compare management functions * @brief Output Compare management functions * @verbatim =============================================================================== ##### Output Compare management functions ##### =============================================================================== ##### TIM Driver: how to use it in Output Compare Mode ##### =============================================================================== [..] To use the Timer in Output Compare mode, the following steps are mandatory: (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function (#) Configure the TIM pins by configuring the corresponding GPIO pins (#) Configure the Time base unit as described in the first part of this driver, (++) if needed, else the Timer will run with the default configuration: Autoreload value = 0xFFFF (++) Prescaler value = 0x0000 (++) Counter mode = Up counting (++) Clock Division = TIM_CKD_DIV1 (#) Fill the TIM_OCInitStruct with the desired parameters including: (++) The TIM Output Compare mode: TIM_OCMode (++) TIM Output State: TIM_OutputState (++) TIM Pulse value: TIM_Pulse (++) TIM Output Compare Polarity : TIM_OCPolarity (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the corresponding configuration (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. -@- All other functions can be used separately to modify, if needed, a specific feature of the Timer. -@- In case of PWM mode, this function is mandatory: TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); -@- If the corresponding interrupt or DMA request are needed, the user should: (+@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). (+@) Enable the corresponding interrupt (or DMA request) using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) @endverbatim * @{ */ /** * @brief Initializes the TIMx Channel1 according to the specified parameters in * the TIM_OCInitStruct. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains * the configuration information for the specified TIM peripheral. * @retval None */ void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) { uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; /* Reset the Output Compare Mode Bits */ tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M; tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S; /* Select the Output Compare Mode */ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; /* Reset the Output Polarity level */ tmpccer &= (uint16_t)~TIM_CCER_CC1P; /* Set the Output Compare Polarity */ tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; /* Set the Output State */ tmpccer |= TIM_OCInitStruct->TIM_OutputState; if((TIMx == TIM1) || (TIMx == TIM8)) { assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); /* Reset the Output N Polarity level */ tmpccer &= (uint16_t)~TIM_CCER_CC1NP; /* Set the Output N Polarity */ tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; /* Reset the Output N State */ tmpccer &= (uint16_t)~TIM_CCER_CC1NE; /* Set the Output N State */ tmpccer |= TIM_OCInitStruct->TIM_OutputNState; /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= (uint16_t)~TIM_CR2_OIS1; tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N; /* Set the Output Idle state */ tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; /* Set the Output N Idle state */ tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Initializes the TIMx Channel2 according to the specified parameters * in the TIM_OCInitStruct. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains * the configuration information for the specified TIM peripheral. * @retval None */ void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) { uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M; tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S; /* Select the Output Compare Mode */ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); /* Reset the Output Polarity level */ tmpccer &= (uint16_t)~TIM_CCER_CC2P; /* Set the Output Compare Polarity */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); /* Set the Output State */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); if((TIMx == TIM1) || (TIMx == TIM8)) { assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); /* Reset the Output N Polarity level */ tmpccer &= (uint16_t)~TIM_CCER_CC2NP; /* Set the Output N Polarity */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); /* Reset the Output N State */ tmpccer &= (uint16_t)~TIM_CCER_CC2NE; /* Set the Output N State */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= (uint16_t)~TIM_CR2_OIS2; tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N; /* Set the Output Idle state */ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); /* Set the Output N Idle state */ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Initializes the TIMx Channel3 according to the specified parameters * in the TIM_OCInitStruct. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains * the configuration information for the specified TIM peripheral. * @retval None */ void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) { uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M; tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S; /* Select the Output Compare Mode */ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; /* Reset the Output Polarity level */ tmpccer &= (uint16_t)~TIM_CCER_CC3P; /* Set the Output Compare Polarity */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); /* Set the Output State */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); if((TIMx == TIM1) || (TIMx == TIM8)) { assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); /* Reset the Output N Polarity level */ tmpccer &= (uint16_t)~TIM_CCER_CC3NP; /* Set the Output N Polarity */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); /* Reset the Output N State */ tmpccer &= (uint16_t)~TIM_CCER_CC3NE; /* Set the Output N State */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= (uint16_t)~TIM_CR2_OIS3; tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N; /* Set the Output Idle state */ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); /* Set the Output N Idle state */ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Initializes the TIMx Channel4 according to the specified parameters * in the TIM_OCInitStruct. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains * the configuration information for the specified TIM peripheral. * @retval None */ void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) { uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M; tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S; /* Select the Output Compare Mode */ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); /* Reset the Output Polarity level */ tmpccer &= (uint16_t)~TIM_CCER_CC4P; /* Set the Output Compare Polarity */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); /* Set the Output State */ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); if((TIMx == TIM1) || (TIMx == TIM8)) { assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4; /* Set the Output Idle state */ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; /* Set the Capture Compare Register value */ TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Fills each TIM_OCInitStruct member with its default value. * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will * be initialized. * @retval None */ void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) { /* Set the default configuration */ TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; TIM_OCInitStruct->TIM_Pulse = 0x00000000; TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; } /** * @brief Selects the TIM Output Compare Mode. * @note This function disables the selected channel before changing the Output * Compare Mode. If needed, user has to enable this channel using * TIM_CCxCmd() and TIM_CCxNCmd() functions. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_Channel: specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 * @arg TIM_Channel_4: TIM Channel 4 * @param TIM_OCMode: specifies the TIM Output Compare Mode. * This parameter can be one of the following values: * @arg TIM_OCMode_Timing * @arg TIM_OCMode_Active * @arg TIM_OCMode_Toggle * @arg TIM_OCMode_PWM1 * @arg TIM_OCMode_PWM2 * @arg TIM_ForcedAction_Active * @arg TIM_ForcedAction_InActive * @retval None */ void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) { uint32_t tmp = 0; uint16_t tmp1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_CHANNEL(TIM_Channel)); assert_param(IS_TIM_OCM(TIM_OCMode)); tmp = (uint32_t) TIMx; tmp += CCMR_OFFSET; tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; /* Disable the Channel: Reset the CCxE Bit */ TIMx->CCER &= (uint16_t) ~tmp1; if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) { tmp += (TIM_Channel>>1); /* Reset the OCxM bits in the CCMRx register */ *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK; /* Configure the OCxM bits in the CCMRx register */ *(__IO uint32_t *) tmp |= TIM_OCMode; } else { tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; /* Reset the OCxM bits in the CCMRx register */ *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK; /* Configure the OCxM bits in the CCMRx register */ *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); } } /** * @brief Sets the TIMx Capture Compare1 Register value * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param Compare1: specifies the Capture Compare1 register new value. * @retval None */ void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) { /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); /* Set the Capture Compare1 Register value */ TIMx->CCR1 = Compare1; } /** * @brief Sets the TIMx Capture Compare2 Register value * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param Compare2: specifies the Capture Compare2 register new value. * @retval None */ void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) { /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); /* Set the Capture Compare2 Register value */ TIMx->CCR2 = Compare2; } /** * @brief Sets the TIMx Capture Compare3 Register value * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param Compare3: specifies the Capture Compare3 register new value. * @retval None */ void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) { /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); /* Set the Capture Compare3 Register value */ TIMx->CCR3 = Compare3; } /** * @brief Sets the TIMx Capture Compare4 Register value * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param Compare4: specifies the Capture Compare4 register new value. * @retval None */ void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) { /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); /* Set the Capture Compare4 Register value */ TIMx->CCR4 = Compare4; } /** * @brief Forces the TIMx output 1 waveform to active or inactive level. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. * This parameter can be one of the following values: * @arg TIM_ForcedAction_Active: Force active level on OC1REF * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. * @retval None */ void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) { uint16_t tmpccmr1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); tmpccmr1 = TIMx->CCMR1; /* Reset the OC1M Bits */ tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M; /* Configure The Forced output Mode */ tmpccmr1 |= TIM_ForcedAction; /* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; } /** * @brief Forces the TIMx output 2 waveform to active or inactive level. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. * This parameter can be one of the following values: * @arg TIM_ForcedAction_Active: Force active level on OC2REF * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. * @retval None */ void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) { uint16_t tmpccmr1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); tmpccmr1 = TIMx->CCMR1; /* Reset the OC2M Bits */ tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M; /* Configure The Forced output Mode */ tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); /* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; } /** * @brief Forces the TIMx output 3 waveform to active or inactive level. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. * This parameter can be one of the following values: * @arg TIM_ForcedAction_Active: Force active level on OC3REF * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. * @retval None */ void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) { uint16_t tmpccmr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); tmpccmr2 = TIMx->CCMR2; /* Reset the OC1M Bits */ tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M; /* Configure The Forced output Mode */ tmpccmr2 |= TIM_ForcedAction; /* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; } /** * @brief Forces the TIMx output 4 waveform to active or inactive level. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. * This parameter can be one of the following values: * @arg TIM_ForcedAction_Active: Force active level on OC4REF * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. * @retval None */ void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) { uint16_t tmpccmr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); tmpccmr2 = TIMx->CCMR2; /* Reset the OC2M Bits */ tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M; /* Configure The Forced output Mode */ tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); /* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; } /** * @brief Enables or disables the TIMx peripheral Preload register on CCR1. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_OCPreload: new state of the TIMx peripheral Preload register * This parameter can be one of the following values: * @arg TIM_OCPreload_Enable * @arg TIM_OCPreload_Disable * @retval None */ void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) { uint16_t tmpccmr1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); tmpccmr1 = TIMx->CCMR1; /* Reset the OC1PE Bit */ tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE); /* Enable or Disable the Output Compare Preload feature */ tmpccmr1 |= TIM_OCPreload; /* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; } /** * @brief Enables or disables the TIMx peripheral Preload register on CCR2. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_OCPreload: new state of the TIMx peripheral Preload register * This parameter can be one of the following values: * @arg TIM_OCPreload_Enable * @arg TIM_OCPreload_Disable * @retval None */ void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) { uint16_t tmpccmr1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); tmpccmr1 = TIMx->CCMR1; /* Reset the OC2PE Bit */ tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE); /* Enable or Disable the Output Compare Preload feature */ tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); /* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; } /** * @brief Enables or disables the TIMx peripheral Preload register on CCR3. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCPreload: new state of the TIMx peripheral Preload register * This parameter can be one of the following values: * @arg TIM_OCPreload_Enable * @arg TIM_OCPreload_Disable * @retval None */ void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) { uint16_t tmpccmr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); tmpccmr2 = TIMx->CCMR2; /* Reset the OC3PE Bit */ tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE); /* Enable or Disable the Output Compare Preload feature */ tmpccmr2 |= TIM_OCPreload; /* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; } /** * @brief Enables or disables the TIMx peripheral Preload register on CCR4. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCPreload: new state of the TIMx peripheral Preload register * This parameter can be one of the following values: * @arg TIM_OCPreload_Enable * @arg TIM_OCPreload_Disable * @retval None */ void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) { uint16_t tmpccmr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); tmpccmr2 = TIMx->CCMR2; /* Reset the OC4PE Bit */ tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE); /* Enable or Disable the Output Compare Preload feature */ tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); /* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; } /** * @brief Configures the TIMx Output Compare 1 Fast feature. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. * This parameter can be one of the following values: * @arg TIM_OCFast_Enable: TIM output compare fast enable * @arg TIM_OCFast_Disable: TIM output compare fast disable * @retval None */ void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) { uint16_t tmpccmr1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Reset the OC1FE Bit */ tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE; /* Enable or Disable the Output Compare Fast Bit */ tmpccmr1 |= TIM_OCFast; /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmr1; } /** * @brief Configures the TIMx Output Compare 2 Fast feature. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. * This parameter can be one of the following values: * @arg TIM_OCFast_Enable: TIM output compare fast enable * @arg TIM_OCFast_Disable: TIM output compare fast disable * @retval None */ void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) { uint16_t tmpccmr1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Reset the OC2FE Bit */ tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE); /* Enable or Disable the Output Compare Fast Bit */ tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmr1; } /** * @brief Configures the TIMx Output Compare 3 Fast feature. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. * This parameter can be one of the following values: * @arg TIM_OCFast_Enable: TIM output compare fast enable * @arg TIM_OCFast_Disable: TIM output compare fast disable * @retval None */ void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) { uint16_t tmpccmr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); /* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2; /* Reset the OC3FE Bit */ tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE; /* Enable or Disable the Output Compare Fast Bit */ tmpccmr2 |= TIM_OCFast; /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmr2; } /** * @brief Configures the TIMx Output Compare 4 Fast feature. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. * This parameter can be one of the following values: * @arg TIM_OCFast_Enable: TIM output compare fast enable * @arg TIM_OCFast_Disable: TIM output compare fast disable * @retval None */ void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) { uint16_t tmpccmr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); /* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2; /* Reset the OC4FE Bit */ tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE); /* Enable or Disable the Output Compare Fast Bit */ tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmr2; } /** * @brief Clears or safeguards the OCREF1 signal on an external event * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. * This parameter can be one of the following values: * @arg TIM_OCClear_Enable: TIM Output clear enable * @arg TIM_OCClear_Disable: TIM Output clear disable * @retval None */ void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) { uint16_t tmpccmr1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); tmpccmr1 = TIMx->CCMR1; /* Reset the OC1CE Bit */ tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE; /* Enable or Disable the Output Compare Clear Bit */ tmpccmr1 |= TIM_OCClear; /* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; } /** * @brief Clears or safeguards the OCREF2 signal on an external event * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. * This parameter can be one of the following values: * @arg TIM_OCClear_Enable: TIM Output clear enable * @arg TIM_OCClear_Disable: TIM Output clear disable * @retval None */ void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) { uint16_t tmpccmr1 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); tmpccmr1 = TIMx->CCMR1; /* Reset the OC2CE Bit */ tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE; /* Enable or Disable the Output Compare Clear Bit */ tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); /* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; } /** * @brief Clears or safeguards the OCREF3 signal on an external event * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. * This parameter can be one of the following values: * @arg TIM_OCClear_Enable: TIM Output clear enable * @arg TIM_OCClear_Disable: TIM Output clear disable * @retval None */ void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) { uint16_t tmpccmr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); tmpccmr2 = TIMx->CCMR2; /* Reset the OC3CE Bit */ tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE; /* Enable or Disable the Output Compare Clear Bit */ tmpccmr2 |= TIM_OCClear; /* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; } /** * @brief Clears or safeguards the OCREF4 signal on an external event * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. * This parameter can be one of the following values: * @arg TIM_OCClear_Enable: TIM Output clear enable * @arg TIM_OCClear_Disable: TIM Output clear disable * @retval None */ void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) { uint16_t tmpccmr2 = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); tmpccmr2 = TIMx->CCMR2; /* Reset the OC4CE Bit */ tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE; /* Enable or Disable the Output Compare Clear Bit */ tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); /* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; } /** * @brief Configures the TIMx channel 1 polarity. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_OCPolarity: specifies the OC1 Polarity * This parameter can be one of the following values: * @arg TIM_OCPolarity_High: Output Compare active high * @arg TIM_OCPolarity_Low: Output Compare active low * @retval None */ void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) { uint16_t tmpccer = 0; /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); tmpccer = TIMx->CCER; /* Set or Reset the CC1P Bit */ tmpccer &= (uint16_t)(~TIM_CCER_CC1P); tmpccer |= TIM_OCPolarity; /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; } /** * @brief Configures the TIMx Channel 1N polarity. * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. * @param TIM_OCNPolarity: specifies the OC1N Polarity * This parameter can be one of the following values: * @arg TIM_OCNPolarity_High: Output Compare active high * @arg TIM_OCNPolarity_Low: Output Compare active low * @retval None */ void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) { uint16_t tmpccer = 0; /* Check the parameters */ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); tmpccer = TIMx->CCER; /* Set or Reset the CC1NP Bit */ tmpccer &= (uint16_t)~TIM_CCER_CC1NP; tmpccer |= TIM_OCNPolarity; /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; } /** * @brief Configures the TIMx channel 2 polarity. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_OCPolarity: specifies the OC2 Polarity * This parameter can be one of the following values: * @arg TIM_OCPolarity_High: Output Compare active high * @arg TIM_OCPolarity_Low: Output Compare active low * @retval None */ void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) { uint16_t tmpccer = 0; /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); tmpccer = TIMx->CCER; /* Set or Reset the CC2P Bit */ tmpccer &= (uint16_t)(~TIM_CCER_CC2P); tmpccer |= (uint16_t)(TIM_OCPolarity << 4); /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; } /** * @brief Configures the TIMx Channel 2N polarity. * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. * @param TIM_OCNPolarity: specifies the OC2N Polarity * This parameter can be one of the following values: * @arg TIM_OCNPolarity_High: Output Compare active high * @arg TIM_OCNPolarity_Low: Output Compare active low * @retval None */ void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) { uint16_t tmpccer = 0; /* Check the parameters */ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); tmpccer = TIMx->CCER; /* Set or Reset the CC2NP Bit */ tmpccer &= (uint16_t)~TIM_CCER_CC2NP; tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; } /** * @brief Configures the TIMx channel 3 polarity. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCPolarity: specifies the OC3 Polarity * This parameter can be one of the following values: * @arg TIM_OCPolarity_High: Output Compare active high * @arg TIM_OCPolarity_Low: Output Compare active low * @retval None */ void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) { uint16_t tmpccer = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); tmpccer = TIMx->CCER; /* Set or Reset the CC3P Bit */ tmpccer &= (uint16_t)~TIM_CCER_CC3P; tmpccer |= (uint16_t)(TIM_OCPolarity << 8); /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; } /** * @brief Configures the TIMx Channel 3N polarity. * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. * @param TIM_OCNPolarity: specifies the OC3N Polarity * This parameter can be one of the following values: * @arg TIM_OCNPolarity_High: Output Compare active high * @arg TIM_OCNPolarity_Low: Output Compare active low * @retval None */ void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) { uint16_t tmpccer = 0; /* Check the parameters */ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); tmpccer = TIMx->CCER; /* Set or Reset the CC3NP Bit */ tmpccer &= (uint16_t)~TIM_CCER_CC3NP; tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; } /** * @brief Configures the TIMx channel 4 polarity. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_OCPolarity: specifies the OC4 Polarity * This parameter can be one of the following values: * @arg TIM_OCPolarity_High: Output Compare active high * @arg TIM_OCPolarity_Low: Output Compare active low * @retval None */ void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) { uint16_t tmpccer = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); tmpccer = TIMx->CCER; /* Set or Reset the CC4P Bit */ tmpccer &= (uint16_t)~TIM_CCER_CC4P; tmpccer |= (uint16_t)(TIM_OCPolarity << 12); /* Write to TIMx CCER register */ TIMx->CCER = tmpccer; } /** * @brief Enables or disables the TIM Capture Compare Channel x. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_Channel: specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 * @arg TIM_Channel_4: TIM Channel 4 * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. * @retval None */ void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) { uint16_t tmp = 0; /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_CHANNEL(TIM_Channel)); assert_param(IS_TIM_CCX(TIM_CCx)); tmp = CCER_CCE_SET << TIM_Channel; /* Reset the CCxE Bit */ TIMx->CCER &= (uint16_t)~ tmp; /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); } /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. * @param TIM_Channel: specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. * @retval None */ void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) { uint16_t tmp = 0; /* Check the parameters */ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); assert_param(IS_TIM_CCXN(TIM_CCxN)); tmp = CCER_CCNE_SET << TIM_Channel; /* Reset the CCxNE Bit */ TIMx->CCER &= (uint16_t) ~tmp; /* Set or reset the CCxNE Bit */ TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); } /** * @} */ /** @defgroup TIM_Group3 Input Capture management functions * @brief Input Capture management functions * @verbatim =============================================================================== ##### Input Capture management functions ##### =============================================================================== ##### TIM Driver: how to use it in Input Capture Mode ##### =============================================================================== [..] To use the Timer in Input Capture mode, the following steps are mandatory: (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function (#) Configure the TIM pins by configuring the corresponding GPIO pins (#) Configure the Time base unit as described in the first part of this driver, if needed, else the Timer will run with the default configuration: (++) Autoreload value = 0xFFFF (++) Prescaler value = 0x0000 (++) Counter mode = Up counting (++) Clock Division = TIM_CKD_DIV1 (#) Fill the TIM_ICInitStruct with the desired parameters including: (++) TIM Channel: TIM_Channel (++) TIM Input Capture polarity: TIM_ICPolarity (++) TIM Input Capture selection: TIM_ICSelection (++) TIM Input Capture Prescaler: TIM_ICPrescaler (++) TIM Input CApture filter value: TIM_ICFilter (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the corresponding configuration and to measure only frequency or duty cycle of the input signal, or, Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the corresponding configuration and to measure the frequency and the duty cycle of the input signal (#) Enable the NVIC or the DMA to read the measured frequency. (#) Enable the corresponding interrupt (or DMA request) to read the Captured value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. (#) Use TIM_GetCapturex(TIMx); to read the captured value. -@- All other functions can be used separately to modify, if needed, a specific feature of the Timer. @endverbatim * @{ */ /** * @brief Initializes the TIM peripheral according to the specified parameters * in the TIM_ICInitStruct. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains * the configuration information for the specified TIM peripheral. * @retval None */ void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) { /* TI1 Configuration */ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); } else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) { /* TI2 Configuration */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); } else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) { /* TI3 Configuration */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); } else { /* TI4 Configuration */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); } } /** * @brief Fills each TIM_ICInitStruct member with its default value. * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will * be initialized. * @retval None */ void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) { /* Set the default configuration */ TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; TIM_ICInitStruct->TIM_ICFilter = 0x00; } /** * @brief Configures the TIM peripheral according to the specified parameters * in the TIM_ICInitStruct to measure an external PWM signal. * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM * peripheral. * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains * the configuration information for the specified TIM peripheral. * @retval None */ void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) { uint16_t icoppositepolarity = TIM_ICPolarity_Rising; uint16_t icoppositeselection = TIM_ICSelection_DirectTI; /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); /* Select the Opposite Input Polarity */ if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) { icoppositepolarity = TIM_ICPolarity_Falling; } else { icoppositepolarity = TIM_ICPolarity_Rising; } /* Select the Opposite Input */ if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) { icoppositeselection = TIM_ICSelection_IndirectTI; } else { icoppositeselection = TIM_ICSelection_DirectTI; } if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) { /* TI1 Configuration */ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); /* TI2 Configuration */ TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); } else { /* TI2 Configuration */ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); /* TI1 Configuration */ TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); /* Set the Input Capture Prescaler value */ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); } } /** * @brief Gets the TIMx Input Capture 1 value. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @retval Capture Compare 1 Register value. */ uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) { /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); /* Get the Capture 1 Register value */ return TIMx->CCR1; } /** * @brief Gets the TIMx Input Capture 2 value. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @retval Capture Compare 2 Register value. */ uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) { /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); /* Get the Capture 2 Register value */ return TIMx->CCR2; } /** * @brief Gets the TIMx Input Capture 3 value. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @retval Capture Compare 3 Register value. */ uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) { /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); /* Get the Capture 3 Register value */ return TIMx->CCR3; } /** * @brief Gets the TIMx Input Capture 4 value. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @retval Capture Compare 4 Register value. */ uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) { /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); /* Get the Capture 4 Register value */ return TIMx->CCR4; } /** * @brief Sets the TIMx Input Capture 1 prescaler. * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) { /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); /* Reset the IC1PSC Bits */ TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC; /* Set the IC1PSC value */ TIMx->CCMR1 |= TIM_ICPSC; } /** * @brief Sets the TIMx Input Capture 2 prescaler. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) { /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); /* Reset the IC2PSC Bits */ TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC; /* Set the IC2PSC value */ TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); } /** * @brief Sets the TIMx Input Capture 3 prescaler. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) { /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); /* Reset the IC3PSC Bits */ TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC; /* Set the IC3PSC value */ TIMx->CCMR2 |= TIM_ICPSC; } /** * @brief Sets the TIMx Input Capture 4 prescaler. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. * This parameter can be one of the following values: * @arg TIM_ICPSC_DIV1: no prescaler * @arg TIM_ICPSC_DIV2: capture is done once every 2 events * @arg TIM_ICPSC_DIV4: capture is done once every 4 events * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) { /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); /* Reset the IC4PSC Bits */ TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC; /* Set the IC4PSC value */ TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); } /** * @} */ /** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features * @brief Advanced-control timers (TIM1 and TIM8) specific features * @verbatim =============================================================================== ##### Advanced-control timers (TIM1 and TIM8) specific features ##### =============================================================================== ##### TIM Driver: how to use the Break feature ##### =============================================================================== [..] After configuring the Timer channel(s) in the appropriate Output Compare mode: (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer Break Polarity, dead time, Lock level, the OSSI/OSSR State and the AOE(automatic output enable). (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) (#) Once the break even occurs, the Timer's output signals are put in reset state or in a known state (according to the configuration made in TIM_BDTRConfig() function). @endverbatim * @{ */ /** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). * @param TIMx: where x can be 1 or 8 to select the TIM * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. * @retval None */ void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) { /* Check the parameters */ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | TIM_BDTRInitStruct->TIM_AutomaticOutput; } /** * @brief Fills each TIM_BDTRInitStruct member with its default value. * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which * will be initialized. * @retval None */ void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) { /* Set the default configuration */ TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; TIM_BDTRInitStruct->TIM_DeadTime = 0x00; TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; } /** * @brief Enables or disables the TIM peripheral Main Outputs. * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. * @param NewState: new state of the TIM peripheral Main Outputs. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the TIM Main Output */ TIMx->BDTR |= TIM_BDTR_MOE; } else { /* Disable the TIM Main Output */ TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE; } } /** * @brief Selects the TIM peripheral Commutation event. * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral * @param NewState: new state of the Commutation event. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set the COM Bit */ TIMx->CR2 |= TIM_CR2_CCUS; } else { /* Reset the COM Bit */ TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS; } } /** * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral * @param NewState: new state of the Capture Compare Preload Control bit * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_LIST4_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set the CCPC Bit */ TIMx->CR2 |= TIM_CR2_CCPC; } else { /* Reset the CCPC Bit */ TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC; } } /** * @} */ /** @defgroup TIM_Group5 Interrupts DMA and flags management functions * @brief Interrupts, DMA and flags management functions * @verbatim =============================================================================== ##### Interrupts, DMA and flags management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the specified TIM interrupts. * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg TIM_IT_Update: TIM update Interrupt source * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source * @arg TIM_IT_COM: TIM Commutation Interrupt source * @arg TIM_IT_Trigger: TIM Trigger Interrupt source * @arg TIM_IT_Break: TIM Break Interrupt source * * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update, * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can * be used: TIM_IT_Update or TIM_IT_CC1 * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 * * @param NewState: new state of the TIM interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_IT(TIM_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the Interrupt sources */ TIMx->DIER |= TIM_IT; } else { /* Disable the Interrupt sources */ TIMx->DIER &= (uint16_t)~TIM_IT; } } /** * @brief Configures the TIMx event to be generate by software. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param TIM_EventSource: specifies the event source. * This parameter can be one or more of the following values: * @arg TIM_EventSource_Update: Timer update Event source * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source * @arg TIM_EventSource_COM: Timer COM event source * @arg TIM_EventSource_Trigger: Timer Trigger Event source * @arg TIM_EventSource_Break: Timer Break event source * * @note TIM6 and TIM7 can only generate an update event. * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. * * @retval None */ void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); /* Set the event sources */ TIMx->EGR = TIM_EventSource; } /** * @brief Checks whether the specified TIM flag is set or not. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param TIM_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg TIM_FLAG_Update: TIM update Flag * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag * @arg TIM_FLAG_COM: TIM Commutation Flag * @arg TIM_FLAG_Trigger: TIM Trigger Flag * @arg TIM_FLAG_Break: TIM Break Flag * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag * * @note TIM6 and TIM7 can have only one update flag. * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. * * @retval The new state of TIM_FLAG (SET or RESET). */ FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) { ITStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the TIMx's pending flags. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param TIM_FLAG: specifies the flag bit to clear. * This parameter can be any combination of the following values: * @arg TIM_FLAG_Update: TIM update Flag * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag * @arg TIM_FLAG_COM: TIM Commutation Flag * @arg TIM_FLAG_Trigger: TIM Trigger Flag * @arg TIM_FLAG_Break: TIM Break Flag * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag * * @note TIM6 and TIM7 can have only one update flag. * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. * * @retval None */ void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Clear the flags */ TIMx->SR = (uint16_t)~TIM_FLAG; } /** * @brief Checks whether the TIM interrupt has occurred or not. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param TIM_IT: specifies the TIM interrupt source to check. * This parameter can be one of the following values: * @arg TIM_IT_Update: TIM update Interrupt source * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source * @arg TIM_IT_COM: TIM Commutation Interrupt source * @arg TIM_IT_Trigger: TIM Trigger Interrupt source * @arg TIM_IT_Break: TIM Break Interrupt source * * @note TIM6 and TIM7 can generate only an update interrupt. * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. * * @retval The new state of the TIM_IT(SET or RESET). */ ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) { ITStatus bitstatus = RESET; uint16_t itstatus = 0x0, itenable = 0x0; /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_GET_IT(TIM_IT)); itstatus = TIMx->SR & TIM_IT; itenable = TIMx->DIER & TIM_IT; if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the TIMx's interrupt pending bits. * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param TIM_IT: specifies the pending bit to clear. * This parameter can be any combination of the following values: * @arg TIM_IT_Update: TIM1 update Interrupt source * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source * @arg TIM_IT_COM: TIM Commutation Interrupt source * @arg TIM_IT_Trigger: TIM Trigger Interrupt source * @arg TIM_IT_Break: TIM Break Interrupt source * * @note TIM6 and TIM7 can generate only an update interrupt. * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. * * @retval None */ void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) { /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Clear the IT pending Bit */ TIMx->SR = (uint16_t)~TIM_IT; } /** * @brief Configures the TIMx's DMA interface. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_DMABase: DMA Base address. * This parameter can be one of the following values: * @arg TIM_DMABase_CR1 * @arg TIM_DMABase_CR2 * @arg TIM_DMABase_SMCR * @arg TIM_DMABase_DIER * @arg TIM1_DMABase_SR * @arg TIM_DMABase_EGR * @arg TIM_DMABase_CCMR1 * @arg TIM_DMABase_CCMR2 * @arg TIM_DMABase_CCER * @arg TIM_DMABase_CNT * @arg TIM_DMABase_PSC * @arg TIM_DMABase_ARR * @arg TIM_DMABase_RCR * @arg TIM_DMABase_CCR1 * @arg TIM_DMABase_CCR2 * @arg TIM_DMABase_CCR3 * @arg TIM_DMABase_CCR4 * @arg TIM_DMABase_BDTR * @arg TIM_DMABase_DCR * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. * @retval None */ void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) { /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); /* Set the DMA Base and the DMA Burst Length */ TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; } /** * @brief Enables or disables the TIMx's DMA Requests. * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. * @param TIM_DMASource: specifies the DMA Request sources. * This parameter can be any combination of the following values: * @arg TIM_DMA_Update: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_Trigger: TIM Trigger DMA source * @param NewState: new state of the DMA Request sources. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_LIST5_PERIPH(TIMx)); assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the DMA sources */ TIMx->DIER |= TIM_DMASource; } else { /* Disable the DMA sources */ TIMx->DIER &= (uint16_t)~TIM_DMASource; } } /** * @brief Selects the TIMx peripheral Capture Compare DMA source. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param NewState: new state of the Capture Compare DMA source * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set the CCDS Bit */ TIMx->CR2 |= TIM_CR2_CCDS; } else { /* Reset the CCDS Bit */ TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS; } } /** * @} */ /** @defgroup TIM_Group6 Clocks management functions * @brief Clocks management functions * @verbatim =============================================================================== ##### Clocks management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Configures the TIMx internal Clock * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @retval None */ void TIM_InternalClockConfig(TIM_TypeDef* TIMx) { /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); /* Disable slave mode to clock the prescaler directly with the internal clock */ TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; } /** * @brief Configures the TIMx Internal Trigger as External Clock * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_InputTriggerSource: Trigger source. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal Trigger 0 * @arg TIM_TS_ITR1: Internal Trigger 1 * @arg TIM_TS_ITR2: Internal Trigger 2 * @arg TIM_TS_ITR3: Internal Trigger 3 * @retval None */ void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) { /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); /* Select the Internal Trigger */ TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); /* Select the External clock mode1 */ TIMx->SMCR |= TIM_SlaveMode_External1; } /** * @brief Configures the TIMx Trigger as External Clock * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 * to select the TIM peripheral. * @param TIM_TIxExternalCLKSource: Trigger source. * This parameter can be one of the following values: * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 * @param TIM_ICPolarity: specifies the TIx Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @param ICFilter: specifies the filter value. * This parameter must be a value between 0x0 and 0xF. * @retval None */ void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter) { /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); assert_param(IS_TIM_IC_FILTER(ICFilter)); /* Configure the Timer Input Clock Source */ if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) { TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); } else { TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); } /* Select the Trigger source */ TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); /* Select the External clock mode1 */ TIMx->SMCR |= TIM_SlaveMode_External1; } /** * @brief Configures the External clock Mode1 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. * @param TIM_ExtTRGPolarity: The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. * @param ExtTRGFilter: External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) { uint16_t tmpsmcr = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); /* Configure the ETR Clock source */ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; /* Reset the SMS Bits */ tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; /* Select the External clock mode1 */ tmpsmcr |= TIM_SlaveMode_External1; /* Select the Trigger selection : ETRF */ tmpsmcr &= (uint16_t)~TIM_SMCR_TS; tmpsmcr |= TIM_TS_ETRF; /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; } /** * @brief Configures the External clock Mode2 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. * @param TIM_ExtTRGPolarity: The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. * @param ExtTRGFilter: External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) { /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); /* Configure the ETR Clock source */ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); /* Enable the External clock mode2 */ TIMx->SMCR |= TIM_SMCR_ECE; } /** * @} */ /** @defgroup TIM_Group7 Synchronization management functions * @brief Synchronization management functions * @verbatim =============================================================================== ##### Synchronization management functions ##### =============================================================================== ##### TIM Driver: how to use it in synchronization Mode ##### =============================================================================== [..] *** Case of two/several Timers *** ================================== [..] (#) Configure the Master Timers using the following functions: (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); (#) Configure the Slave Timers using the following functions: (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); *** Case of Timers and external trigger(ETR pin) *** ==================================================== [..] (#) Configure the External trigger using this function: (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); (#) Configure the Slave Timers using the following functions: (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); @endverbatim * @{ */ /** * @brief Selects the Input Trigger source * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 * to select the TIM peripheral. * @param TIM_InputTriggerSource: The Input Trigger source. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal Trigger 0 * @arg TIM_TS_ITR1: Internal Trigger 1 * @arg TIM_TS_ITR2: Internal Trigger 2 * @arg TIM_TS_ITR3: Internal Trigger 3 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) { uint16_t tmpsmcr = 0; /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; /* Reset the TS Bits */ tmpsmcr &= (uint16_t)~TIM_SMCR_TS; /* Set the Input Trigger source */ tmpsmcr |= TIM_InputTriggerSource; /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; } /** * @brief Selects the TIMx Trigger Output Mode. * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. * * @param TIM_TRGOSource: specifies the Trigger Output source. * This parameter can be one of the following values: * * - For all TIMx * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO) * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO) * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO) * * - For all TIMx except TIM6 and TIM7 * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag * is to be set, as soon as a capture or compare match occurs(TRGO) * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO) * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO) * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO) * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO) * * @retval None */ void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) { /* Check the parameters */ assert_param(IS_TIM_LIST5_PERIPH(TIMx)); assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); /* Reset the MMS Bits */ TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS; /* Select the TRGO source */ TIMx->CR2 |= TIM_TRGOSource; } /** * @brief Selects the TIMx Slave Mode. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. * @param TIM_SlaveMode: specifies the Timer Slave Mode. * This parameter can be one of the following values: * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize * the counter and triggers an update of the registers * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter * @retval None */ void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) { /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); /* Reset the SMS Bits */ TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; /* Select the Slave Mode */ TIMx->SMCR |= TIM_SlaveMode; } /** * @brief Sets or Resets the TIMx Master/Slave Mode. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. * This parameter can be one of the following values: * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer * and its slaves (through TRGO) * @arg TIM_MasterSlaveMode_Disable: No action * @retval None */ void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) { /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); /* Reset the MSM Bit */ TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM; /* Set or Reset the MSM Bit */ TIMx->SMCR |= TIM_MasterSlaveMode; } /** * @brief Configures the TIMx External Trigger (ETR). * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. * @param TIM_ExtTRGPolarity: The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. * @param ExtTRGFilter: External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) { uint16_t tmpsmcr = 0; /* Check the parameters */ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); tmpsmcr = TIMx->SMCR; /* Reset the ETR Bits */ tmpsmcr &= SMCR_ETR_MASK; /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; } /** * @} */ /** @defgroup TIM_Group8 Specific interface management functions * @brief Specific interface management functions * @verbatim =============================================================================== ##### Specific interface management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Configures the TIMx Encoder Interface. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. * This parameter can be one of the following values: * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending * on the level of the other input. * @param TIM_IC1Polarity: specifies the IC1 Polarity * This parameter can be one of the following values: * @arg TIM_ICPolarity_Falling: IC Falling edge. * @arg TIM_ICPolarity_Rising: IC Rising edge. * @param TIM_IC2Polarity: specifies the IC2 Polarity * This parameter can be one of the following values: * @arg TIM_ICPolarity_Falling: IC Falling edge. * @arg TIM_ICPolarity_Rising: IC Rising edge. * @retval None */ void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) { uint16_t tmpsmcr = 0; uint16_t tmpccmr1 = 0; uint16_t tmpccer = 0; /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; /* Set the encoder Mode */ tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; tmpsmcr |= TIM_EncoderMode; /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S); tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; /* Set the TI1 and the TI2 Polarities */ tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P); tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmr1; /* Write to TIMx CCER */ TIMx->CCER = tmpccer; } /** * @brief Enables or disables the TIMx's Hall sensor interface. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param NewState: new state of the TIMx Hall sensor interface. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_TIM_LIST2_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Set the TI1S Bit */ TIMx->CR2 |= TIM_CR2_TI1S; } else { /* Reset the TI1S Bit */ TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S; } } /** * @} */ /** @defgroup TIM_Group9 Specific remapping management function * @brief Specific remapping management function * @verbatim =============================================================================== ##### Specific remapping management function ##### =============================================================================== @endverbatim * @{ */ /** * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral. * @param TIM_Remap: specifies the TIM input remapping source. * This parameter can be one of the following values: * @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output. * @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. * @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. * @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) * @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock. * @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock. * @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. * @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) * @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock * (HSE divided by a programmable prescaler) * @retval None */ void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) { /* Check the parameters */ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); assert_param(IS_TIM_REMAP(TIM_Remap)); /* Set the Timer remapping configuration */ TIMx->OR = TIM_Remap; } /** * @} */ /** * @brief Configure the TI1 as Input. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 * to select the TIM peripheral. * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge * @param TIM_ICSelection: specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. * @param TIM_ICFilter: Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter) { uint16_t tmpccmr1 = 0, tmpccer = 0; /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; tmpccmr1 = TIMx->CCMR1; tmpccer = TIMx->CCER; /* Select the Input and set the filter */ tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F); tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); /* Select the Polarity and set the CC1E Bit */ tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; TIMx->CCER = tmpccer; } /** * @brief Configure the TI2 as Input. * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM * peripheral. * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge * @param TIM_ICSelection: specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. * @param TIM_ICFilter: Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter) { uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; tmpccmr1 = TIMx->CCMR1; tmpccer = TIMx->CCER; tmp = (uint16_t)(TIM_ICPolarity << 4); /* Select the Input and set the filter */ tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); /* Select the Polarity and set the CC2E Bit */ tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; TIMx->CCER = tmpccer; } /** * @brief Configure the TI3 as Input. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge * @param TIM_ICSelection: specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. * @param TIM_ICFilter: Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter) { uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; tmpccmr2 = TIMx->CCMR2; tmpccer = TIMx->CCER; tmp = (uint16_t)(TIM_ICPolarity << 8); /* Select the Input and set the filter */ tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F); tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); /* Select the Polarity and set the CC3E Bit */ tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP); tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; TIMx->CCER = tmpccer; } /** * @brief Configure the TI4 as Input. * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. * @param TIM_ICPolarity : The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge * @param TIM_ICSelection: specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. * @param TIM_ICFilter: Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, uint16_t TIM_ICFilter) { uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; tmpccmr2 = TIMx->CCMR2; tmpccer = TIMx->CCER; tmp = (uint16_t)(TIM_ICPolarity << 12); /* Select the Input and set the filter */ tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); /* Select the Polarity and set the CC4E Bit */ tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP); tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; TIMx->CCER = tmpccer ; } /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c ================================================ /** ****************************************************************************** * @file stm32f4xx_usart.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Universal synchronous asynchronous receiver * transmitter (USART): * + Initialization and Configuration * + Data transfers * + Multi-Processor Communication * + LIN mode * + Half-duplex mode * + Smartcard mode * + IrDA mode * + DMA transfers management * + Interrupts and flags management * @verbatim =============================================================================== ##### How to use this driver ##### =============================================================================== [..] (#) Enable peripheral clock using the following functions RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, UART4 or UART5. (#) According to the USART mode, enable the GPIO clocks using RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, or/and SCLK). (#) Peripheral's alternate function: (++) Connect the pin to the desired peripherals' Alternate Function (AF) using GPIO_PinAFConfig() function (++) Configure the desired pin in alternate function by: GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd, GPIO_OType and GPIO_Speed members (++) Call GPIO_Init() function (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware flow control and Mode(Receiver/Transmitter) using the USART_Init() function. (#) For synchronous mode, enable the clock and program the polarity, phase and last bit using the USART_ClockInit() function. (#) Enable the NVIC and the corresponding interrupt using the function USART_ITConfig() if you need to use interrupt mode. (#) When using the DMA mode (++) Configure the DMA using DMA_Init() function (++) Active the needed channel Request using USART_DMACmd() function (#) Enable the USART using the USART_Cmd() function. (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. -@- Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections for more details [..] In order to reach higher communication baudrates, it is possible to enable the oversampling by 8 mode using the function USART_OverSampling8Cmd(). This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd()) and before calling the function USART_Init(). @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_usart.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup USART * @brief USART driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */ #define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \ USART_CR1_PS | USART_CR1_TE | \ USART_CR1_RE)) /*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */ #define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ USART_CR2_CPHA | USART_CR2_LBCL)) /*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */ #define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE)) /*!< USART Interrupts mask */ #define IT_MASK ((uint16_t)0x001F) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup USART_Private_Functions * @{ */ /** @defgroup USART_Group1 Initialization and Configuration functions * @brief Initialization and Configuration functions * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to initialize the USART in asynchronous and in synchronous modes. (+) For the asynchronous mode only these parameters can be configured: (++) Baud Rate (++) Word Length (++) Stop Bit (++) Parity: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. Depending on the frame length defined by the M bit (8-bits or 9-bits), the possible USART frame formats are as listed in the following table: +-------------------------------------------------------------+ | M bit | PCE bit | USART frame | |---------------------|---------------------------------------| | 0 | 0 | | SB | 8 bit data | STB | | |---------|-----------|---------------------------------------| | 0 | 1 | | SB | 7 bit data | PB | STB | | |---------|-----------|---------------------------------------| | 1 | 0 | | SB | 9 bit data | STB | | |---------|-----------|---------------------------------------| | 1 | 1 | | SB | 8 bit data | PB | STB | | +-------------------------------------------------------------+ (++) Hardware flow control (++) Receiver/transmitter modes [..] The USART_Init() function follows the USART asynchronous configuration procedure (details for the procedure are available in reference manual (RM0090)). (+) For the synchronous mode in addition to the asynchronous mode parameters these parameters should be also configured: (++) USART Clock Enabled (++) USART polarity (++) USART phase (++) USART LastBit [..] These parameters can be configured using the USART_ClockInit() function. @endverbatim * @{ */ /** * @brief Deinitializes the USARTx peripheral registers to their default reset values. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None */ void USART_DeInit(USART_TypeDef* USARTx) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); if (USARTx == USART1) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); } else if (USARTx == USART2) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); } else if (USARTx == USART3) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); } else if (USARTx == UART4) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); } else if (USARTx == UART5) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); } else if (USARTx == USART6) { RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); } else if (USARTx == UART7) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE); } else { if (USARTx == UART8) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE); } } } /** * @brief Initializes the USARTx peripheral according to the specified * parameters in the USART_InitStruct . * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains * the configuration information for the specified USART peripheral. * @retval None */ void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) { uint32_t tmpreg = 0x00, apbclock = 0x00; uint32_t integerdivider = 0x00; uint32_t fractionaldivider = 0x00; RCC_ClocksTypeDef RCC_ClocksStatus; /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */ if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) { assert_param(IS_USART_1236_PERIPH(USARTx)); } /*---------------------------- USART CR2 Configuration -----------------------*/ tmpreg = USARTx->CR2; /* Clear STOP[13:12] bits */ tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit : Set STOP[13:12] bits according to USART_StopBits value */ tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; /* Write to USART CR2 */ USARTx->CR2 = (uint16_t)tmpreg; /*---------------------------- USART CR1 Configuration -----------------------*/ tmpreg = USARTx->CR1; /* Clear M, PCE, PS, TE and RE bits */ tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); /* Configure the USART Word Length, Parity and mode: Set the M bits according to USART_WordLength value Set PCE and PS bits according to USART_Parity value Set TE and RE bits according to USART_Mode value */ tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | USART_InitStruct->USART_Mode; /* Write to USART CR1 */ USARTx->CR1 = (uint16_t)tmpreg; /*---------------------------- USART CR3 Configuration -----------------------*/ tmpreg = USARTx->CR3; /* Clear CTSE and RTSE bits */ tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); /* Configure the USART HFC : Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ tmpreg |= USART_InitStruct->USART_HardwareFlowControl; /* Write to USART CR3 */ USARTx->CR3 = (uint16_t)tmpreg; /*---------------------------- USART BRR Configuration -----------------------*/ /* Configure the USART Baud Rate */ RCC_GetClocksFreq(&RCC_ClocksStatus); if ((USARTx == USART1) || (USARTx == USART6)) { apbclock = RCC_ClocksStatus.PCLK2_Frequency; } else { apbclock = RCC_ClocksStatus.PCLK1_Frequency; } /* Determine the integer part */ if ((USARTx->CR1 & USART_CR1_OVER8) != 0) { /* Integer part computing in case Oversampling mode is 8 Samples */ integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); } else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ { /* Integer part computing in case Oversampling mode is 16 Samples */ integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); } tmpreg = (integerdivider / 100) << 4; /* Determine the fractional part */ fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); /* Implement the fractional part in the register */ if ((USARTx->CR1 & USART_CR1_OVER8) != 0) { tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); } else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ { tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); } /* Write to USART BRR register */ USARTx->BRR = (uint16_t)tmpreg; } /** * @brief Fills each USART_InitStruct member with its default value. * @param USART_InitStruct: pointer to a USART_InitTypeDef structure which will * be initialized. * @retval None */ void USART_StructInit(USART_InitTypeDef* USART_InitStruct) { /* USART_InitStruct members default value */ USART_InitStruct->USART_BaudRate = 9600; USART_InitStruct->USART_WordLength = USART_WordLength_8b; USART_InitStruct->USART_StopBits = USART_StopBits_1; USART_InitStruct->USART_Parity = USART_Parity_No ; USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; } /** * @brief Initializes the USARTx peripheral Clock according to the * specified parameters in the USART_ClockInitStruct . * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral. * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that * contains the configuration information for the specified USART peripheral. * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. * @retval None */ void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) { uint32_t tmpreg = 0x00; /* Check the parameters */ assert_param(IS_USART_1236_PERIPH(USARTx)); assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); /*---------------------------- USART CR2 Configuration -----------------------*/ tmpreg = USARTx->CR2; /* Clear CLKEN, CPOL, CPHA and LBCL bits */ tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK); /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ /* Set CLKEN bit according to USART_Clock value */ /* Set CPOL bit according to USART_CPOL value */ /* Set CPHA bit according to USART_CPHA value */ /* Set LBCL bit according to USART_LastBit value */ tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; /* Write to USART CR2 */ USARTx->CR2 = (uint16_t)tmpreg; } /** * @brief Fills each USART_ClockInitStruct member with its default value. * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure * which will be initialized. * @retval None */ void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) { /* USART_ClockInitStruct members default value */ USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; } /** * @brief Enables or disables the specified USART peripheral. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param NewState: new state of the USARTx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the selected USART by setting the UE bit in the CR1 register */ USARTx->CR1 |= USART_CR1_UE; } else { /* Disable the selected USART by clearing the UE bit in the CR1 register */ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE); } } /** * @brief Sets the system clock prescaler. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_Prescaler: specifies the prescaler clock. * @note The function is used for IrDA mode with UART4 and UART5. * @retval None */ void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); /* Clear the USART prescaler */ USARTx->GTPR &= USART_GTPR_GT; /* Set the USART prescaler */ USARTx->GTPR |= USART_Prescaler; } /** * @brief Enables or disables the USART's 8x oversampling mode. * @note This function has to be called before calling USART_Init() function * in order to have correct baudrate Divider value. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param NewState: new state of the USART 8x oversampling mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ USARTx->CR1 |= USART_CR1_OVER8; } else { /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8); } } /** * @brief Enables or disables the USART's one bit sampling method. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param NewState: new state of the USART one bit sampling method. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ USARTx->CR3 |= USART_CR3_ONEBIT; } else { /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT); } } /** * @} */ /** @defgroup USART_Group2 Data transfers functions * @brief Data transfers functions * @verbatim =============================================================================== ##### Data transfers functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to manage the USART data transfers. [..] During an USART reception, data shifts in least significant bit first through the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) between the internal bus and the received shift register. [..] When a transmission is taking place, a write instruction to the USART_DR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission. [..] The read access of the USART_DR register can be done using the USART_ReceiveData() function and returns the RDR buffered value. Whereas a write access to the USART_DR can be done using USART_SendData() function and stores the written data into TDR buffer. @endverbatim * @{ */ /** * @brief Transmits single data through the USARTx peripheral. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param Data: the data to transmit. * @retval None */ void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_DATA(Data)); /* Transmit Data */ USARTx->DR = (Data & (uint16_t)0x01FF); } /** * @brief Returns the most recent received data by the USARTx peripheral. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval The received data. */ uint16_t USART_ReceiveData(USART_TypeDef* USARTx) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); /* Receive Data */ return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); } /** * @} */ /** @defgroup USART_Group3 MultiProcessor Communication functions * @brief Multi-Processor Communication functions * @verbatim =============================================================================== ##### Multi-Processor Communication functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to manage the USART multiprocessor communication. [..] For instance one of the USARTs can be the master, its TX output is connected to the RX input of the other USART. The others are slaves, their respective TX outputs are logically ANDed together and connected to the RX input of the master. [..] USART multiprocessor communication is possible through the following procedure: (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter or Mode receiver and hardware flow control values using the USART_Init() function. (#) Configures the USART address using the USART_SetAddress() function. (#) Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only for the slaves. (#) Enable the USART using the USART_Cmd() function. (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function. [..] The USART Slave exit from mute mode when receive the wake up condition. @endverbatim * @{ */ /** * @brief Sets the address of the USART node. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_Address: Indicates the address of the USART node. * @retval None */ void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_ADDRESS(USART_Address)); /* Clear the USART address */ USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD); /* Set the USART address node */ USARTx->CR2 |= USART_Address; } /** * @brief Determines if the USART is in mute mode or not. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param NewState: new state of the USART mute mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ USARTx->CR1 |= USART_CR1_RWU; } else { /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU); } } /** * @brief Selects the USART WakeUp method. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_WakeUp: specifies the USART wakeup method. * This parameter can be one of the following values: * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection * @arg USART_WakeUp_AddressMark: WakeUp by an address mark * @retval None */ void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_WAKEUP(USART_WakeUp)); USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE); USARTx->CR1 |= USART_WakeUp; } /** * @} */ /** @defgroup USART_Group4 LIN mode functions * @brief LIN mode functions * @verbatim =============================================================================== ##### LIN mode functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to manage the USART LIN Mode communication. [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance with the LIN standard. [..] Only this LIN Feature is supported by the USART IP: (+) LIN Master Synchronous Break send capability and LIN slave break detection capability : 13-bit break generation and 10/11 bit break detection [..] USART LIN Master transmitter communication is possible through the following procedure: (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, Mode transmitter or Mode receiver and hardware flow control values using the USART_Init() function. (#) Enable the USART using the USART_Cmd() function. (#) Enable the LIN mode using the USART_LINCmd() function. (#) Send the break character using USART_SendBreak() function. [..] USART LIN Master receiver communication is possible through the following procedure: (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, Mode transmitter or Mode receiver and hardware flow control values using the USART_Init() function. (#) Enable the USART using the USART_Cmd() function. (#) Configures the break detection length using the USART_LINBreakDetectLengthConfig() function. (#) Enable the LIN mode using the USART_LINCmd() function. -@- In LIN mode, the following bits must be kept cleared: (+@) CLKEN in the USART_CR2 register, (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. @endverbatim * @{ */ /** * @brief Sets the USART LIN Break detection length. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_LINBreakDetectLength: specifies the LIN break detection length. * This parameter can be one of the following values: * @arg USART_LINBreakDetectLength_10b: 10-bit break detection * @arg USART_LINBreakDetectLength_11b: 11-bit break detection * @retval None */ void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL); USARTx->CR2 |= USART_LINBreakDetectLength; } /** * @brief Enables or disables the USART's LIN mode. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param NewState: new state of the USART LIN mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ USARTx->CR2 |= USART_CR2_LINEN; } else { /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN); } } /** * @brief Transmits break characters. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @retval None */ void USART_SendBreak(USART_TypeDef* USARTx) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); /* Send break characters */ USARTx->CR1 |= USART_CR1_SBK; } /** * @} */ /** @defgroup USART_Group5 Halfduplex mode function * @brief Half-duplex mode function * @verbatim =============================================================================== ##### Half-duplex mode function ##### =============================================================================== [..] This subsection provides a set of functions allowing to manage the USART Half-duplex communication. [..] The USART can be configured to follow a single-wire half-duplex protocol where the TX and RX lines are internally connected. [..] USART Half duplex communication is possible through the following procedure: (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter or Mode receiver and hardware flow control values using the USART_Init() function. (#) Configures the USART address using the USART_SetAddress() function. (#) Enable the USART using the USART_Cmd() function. (#) Enable the half duplex mode using USART_HalfDuplexCmd() function. -@- The RX pin is no longer used -@- In Half-duplex mode the following bits must be kept cleared: (+@) LINEN and CLKEN bits in the USART_CR2 register. (+@) SCEN and IREN bits in the USART_CR3 register. @endverbatim * @{ */ /** * @brief Enables or disables the USART's Half Duplex communication. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param NewState: new state of the USART Communication. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ USARTx->CR3 |= USART_CR3_HDSEL; } else { /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL); } } /** * @} */ /** @defgroup USART_Group6 Smartcard mode functions * @brief Smartcard mode functions * @verbatim =============================================================================== ##### Smartcard mode functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to manage the USART Smartcard communication. [..] The Smartcard interface is designed to support asynchronous protocol Smartcards as defined in the ISO 7816-3 standard. [..] The USART can provide a clock to the smartcard through the SCLK output. In smartcard mode, SCLK is not associated to the communication but is simply derived from the internal peripheral input clock through a 5-bit prescaler. [..] Smartcard communication is possible through the following procedure: (#) Configures the Smartcard Prescaler using the USART_SetPrescaler() function. (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() function. (#) Program the USART clock using the USART_ClockInit() function as following: (++) USART Clock enabled (++) USART CPOL Low (++) USART CPHA on first edge (++) USART Last Bit Clock Enabled (#) Program the Smartcard interface using the USART_Init() function as following: (++) Word Length = 9 Bits (++) 1.5 Stop Bit (++) Even parity (++) BaudRate = 12096 baud (++) Hardware flow control disabled (RTS and CTS signals) (++) Tx and Rx enabled (#) POptionally you can enable the parity error interrupt using the USART_ITConfig() function (#) PEnable the USART using the USART_Cmd() function. (#) PEnable the Smartcard NACK using the USART_SmartCardNACKCmd() function. (#) PEnable the Smartcard interface using the USART_SmartCardCmd() function. Please refer to the ISO 7816-3 specification for more details. -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended to use 1.5 stop bits for both transmitting and receiving to avoid switching between the two configurations. -@- In smartcard mode, the following bits must be kept cleared: (+@) LINEN bit in the USART_CR2 register. (+@) HDSEL and IREN bits in the USART_CR3 register. -@- Smartcard mode is available on USART peripherals only (not available on UART4 and UART5 peripherals). @endverbatim * @{ */ /** * @brief Sets the specified USART guard time. * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or * UART peripheral. * @param USART_GuardTime: specifies the guard time. * @retval None */ void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) { /* Check the parameters */ assert_param(IS_USART_1236_PERIPH(USARTx)); /* Clear the USART Guard time */ USARTx->GTPR &= USART_GTPR_PSC; /* Set the USART guard time */ USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); } /** * @brief Enables or disables the USART's Smart Card mode. * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or * UART peripheral. * @param NewState: new state of the Smart Card mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_1236_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the SC mode by setting the SCEN bit in the CR3 register */ USARTx->CR3 |= USART_CR3_SCEN; } else { /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN); } } /** * @brief Enables or disables NACK transmission. * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or * UART peripheral. * @param NewState: new state of the NACK transmission. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_1236_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ USARTx->CR3 |= USART_CR3_NACK; } else { /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK); } } /** * @} */ /** @defgroup USART_Group7 IrDA mode functions * @brief IrDA mode functions * @verbatim =============================================================================== ##### IrDA mode functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to manage the USART IrDA communication. [..] IrDA is a half duplex communication protocol. If the Transmitter is busy, any data on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. While receiving data, transmission should be avoided as the data to be transmitted could be corrupted. [..] IrDA communication is possible through the following procedure: (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver modes and hardware flow control values using the USART_Init() function. (#) Enable the USART using the USART_Cmd() function. (#) Configures the IrDA pulse width by configuring the prescaler using the USART_SetPrescaler() function. (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode using the USART_IrDAConfig() function. (#) Enable the IrDA using the USART_IrDACmd() function. -@- A pulse of width less than two and greater than one PSC period(s) may or may not be rejected. -@- The receiver set up time should be managed by software. The IrDA physical layer specification specifies a minimum of 10 ms delay between transmission and reception (IrDA is a half duplex protocol). -@- In IrDA mode, the following bits must be kept cleared: (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register. (+@) SCEN and HDSEL bits in the USART_CR3 register. @endverbatim * @{ */ /** * @brief Configures the USART's IrDA interface. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_IrDAMode: specifies the IrDA mode. * This parameter can be one of the following values: * @arg USART_IrDAMode_LowPower * @arg USART_IrDAMode_Normal * @retval None */ void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP); USARTx->CR3 |= USART_IrDAMode; } /** * @brief Enables or disables the USART's IrDA interface. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param NewState: new state of the IrDA mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ USARTx->CR3 |= USART_CR3_IREN; } else { /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN); } } /** * @} */ /** @defgroup USART_Group8 DMA transfers management functions * @brief DMA transfers management functions * @verbatim =============================================================================== ##### DMA transfers management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables or disables the USART's DMA interface. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_DMAReq: specifies the DMA request. * This parameter can be any combination of the following values: * @arg USART_DMAReq_Tx: USART DMA transmit request * @arg USART_DMAReq_Rx: USART DMA receive request * @param NewState: new state of the DMA Request sources. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_DMAREQ(USART_DMAReq)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) { /* Enable the DMA transfer for selected requests by setting the DMAT and/or DMAR bits in the USART CR3 register */ USARTx->CR3 |= USART_DMAReq; } else { /* Disable the DMA transfer for selected requests by clearing the DMAT and/or DMAR bits in the USART CR3 register */ USARTx->CR3 &= (uint16_t)~USART_DMAReq; } } /** * @} */ /** @defgroup USART_Group9 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== [..] This subsection provides a set of functions allowing to configure the USART Interrupts sources, DMA channels requests and check or clear the flags or pending bits status. The user should identify which mode will be used in his application to manage the communication: Polling mode, Interrupt mode or DMA mode. *** Polling Mode *** ==================== [..] In Polling Mode, the SPI communication can be managed by 10 flags: (#) USART_FLAG_TXE : to indicate the status of the transmit buffer register (#) USART_FLAG_RXNE : to indicate the status of the receive buffer register (#) USART_FLAG_TC : to indicate the status of the transmit operation (#) USART_FLAG_IDLE : to indicate the status of the Idle Line (#) USART_FLAG_CTS : to indicate the status of the nCTS input (#) USART_FLAG_LBD : to indicate the status of the LIN break detection (#) USART_FLAG_NE : to indicate if a noise error occur (#) USART_FLAG_FE : to indicate if a frame error occur (#) USART_FLAG_PE : to indicate if a parity error occur (#) USART_FLAG_ORE : to indicate if an Overrun error occur [..] In this Mode it is advised to use the following functions: (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); *** Interrupt Mode *** ====================== [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt sources and 10 pending bits: (#) Pending Bits: (##) USART_IT_TXE : to indicate the status of the transmit buffer register (##) USART_IT_RXNE : to indicate the status of the receive buffer register (##) USART_IT_TC : to indicate the status of the transmit operation (##) USART_IT_IDLE : to indicate the status of the Idle Line (##) USART_IT_CTS : to indicate the status of the nCTS input (##) USART_IT_LBD : to indicate the status of the LIN break detection (##) USART_IT_NE : to indicate if a noise error occur (##) USART_IT_FE : to indicate if a frame error occur (##) USART_IT_PE : to indicate if a parity error occur (##) USART_IT_ORE : to indicate if an Overrun error occur (#) Interrupt Source: (##) USART_IT_TXE : specifies the interrupt source for the Tx buffer empty interrupt. (##) USART_IT_RXNE : specifies the interrupt source for the Rx buffer not empty interrupt. (##) USART_IT_TC : specifies the interrupt source for the Transmit complete interrupt. (##) USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. (##) USART_IT_CTS : specifies the interrupt source for the CTS interrupt. (##) USART_IT_LBD : specifies the interrupt source for the LIN break detection interrupt. (##) USART_IT_PE : specifies the interrupt source for the parity error interrupt. (##) USART_IT_ERR : specifies the interrupt source for the errors interrupt. -@@- Some parameters are coded in order to use them as interrupt source or as pending bits. [..] In this Mode it is advised to use the following functions: (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); *** DMA Mode *** ================ [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel requests: (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request [..] In this Mode it is advised to use the following function: (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); @endverbatim * @{ */ /** * @brief Enables or disables the specified USART interrupts. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. * This parameter can be one of the following values: * @arg USART_IT_CTS: CTS change interrupt * @arg USART_IT_LBD: LIN Break detection interrupt * @arg USART_IT_TXE: Transmit Data Register empty interrupt * @arg USART_IT_TC: Transmission complete interrupt * @arg USART_IT_RXNE: Receive Data register not empty interrupt * @arg USART_IT_IDLE: Idle line detection interrupt * @arg USART_IT_PE: Parity Error interrupt * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) * @param NewState: new state of the specified USARTx interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) { uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; uint32_t usartxbase = 0x00; /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_CONFIG_IT(USART_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); /* The CTS interrupt is not available for UART4 and UART5 */ if (USART_IT == USART_IT_CTS) { assert_param(IS_USART_1236_PERIPH(USARTx)); } usartxbase = (uint32_t)USARTx; /* Get the USART register index */ usartreg = (((uint8_t)USART_IT) >> 0x05); /* Get the interrupt position */ itpos = USART_IT & IT_MASK; itmask = (((uint32_t)0x01) << itpos); if (usartreg == 0x01) /* The IT is in CR1 register */ { usartxbase += 0x0C; } else if (usartreg == 0x02) /* The IT is in CR2 register */ { usartxbase += 0x10; } else /* The IT is in CR3 register */ { usartxbase += 0x14; } if (NewState != DISABLE) { *(__IO uint32_t*)usartxbase |= itmask; } else { *(__IO uint32_t*)usartxbase &= ~itmask; } } /** * @brief Checks whether the specified USART flag is set or not. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_FLAG: specifies the flag to check. * This parameter can be one of the following values: * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) * @arg USART_FLAG_LBD: LIN Break detection flag * @arg USART_FLAG_TXE: Transmit data register empty flag * @arg USART_FLAG_TC: Transmission Complete flag * @arg USART_FLAG_RXNE: Receive data register not empty flag * @arg USART_FLAG_IDLE: Idle Line detection flag * @arg USART_FLAG_ORE: OverRun Error flag * @arg USART_FLAG_NE: Noise Error flag * @arg USART_FLAG_FE: Framing Error flag * @arg USART_FLAG_PE: Parity Error flag * @retval The new state of USART_FLAG (SET or RESET). */ FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) { FlagStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_FLAG(USART_FLAG)); /* The CTS flag is not available for UART4 and UART5 */ if (USART_FLAG == USART_FLAG_CTS) { assert_param(IS_USART_1236_PERIPH(USARTx)); } if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the USARTx's pending flags. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_FLAG: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). * @arg USART_FLAG_LBD: LIN Break detection flag. * @arg USART_FLAG_TC: Transmission Complete flag. * @arg USART_FLAG_RXNE: Receive data register not empty flag. * * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun * error) and IDLE (Idle line detected) flags are cleared by software * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) * followed by a read operation to USART_DR register (USART_ReceiveData()). * @note RXNE flag can be also cleared by a read to the USART_DR register * (USART_ReceiveData()). * @note TC flag can be also cleared by software sequence: a read operation to * USART_SR register (USART_GetFlagStatus()) followed by a write operation * to USART_DR register (USART_SendData()). * @note TXE flag is cleared only by a write to the USART_DR register * (USART_SendData()). * * @retval None */ void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) { /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); /* The CTS flag is not available for UART4 and UART5 */ if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) { assert_param(IS_USART_1236_PERIPH(USARTx)); } USARTx->SR = (uint16_t)~USART_FLAG; } /** * @brief Checks whether the specified USART interrupt has occurred or not. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_IT: specifies the USART interrupt source to check. * This parameter can be one of the following values: * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) * @arg USART_IT_LBD: LIN Break detection interrupt * @arg USART_IT_TXE: Transmit Data Register empty interrupt * @arg USART_IT_TC: Transmission complete interrupt * @arg USART_IT_RXNE: Receive Data register not empty interrupt * @arg USART_IT_IDLE: Idle line detection interrupt * @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set * @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set * @arg USART_IT_NE: Noise Error interrupt * @arg USART_IT_FE: Framing Error interrupt * @arg USART_IT_PE: Parity Error interrupt * @retval The new state of USART_IT (SET or RESET). */ ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) { uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; ITStatus bitstatus = RESET; /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_GET_IT(USART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */ if (USART_IT == USART_IT_CTS) { assert_param(IS_USART_1236_PERIPH(USARTx)); } /* Get the USART register index */ usartreg = (((uint8_t)USART_IT) >> 0x05); /* Get the interrupt position */ itmask = USART_IT & IT_MASK; itmask = (uint32_t)0x01 << itmask; if (usartreg == 0x01) /* The IT is in CR1 register */ { itmask &= USARTx->CR1; } else if (usartreg == 0x02) /* The IT is in CR2 register */ { itmask &= USARTx->CR2; } else /* The IT is in CR3 register */ { itmask &= USARTx->CR3; } bitpos = USART_IT >> 0x08; bitpos = (uint32_t)0x01 << bitpos; bitpos &= USARTx->SR; if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears the USARTx's interrupt pending bits. * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or * UART peripheral. * @param USART_IT: specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) * @arg USART_IT_LBD: LIN Break detection interrupt * @arg USART_IT_TC: Transmission complete interrupt. * @arg USART_IT_RXNE: Receive Data register not empty interrupt. * * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun * error) and IDLE (Idle line detected) pending bits are cleared by * software sequence: a read operation to USART_SR register * (USART_GetITStatus()) followed by a read operation to USART_DR register * (USART_ReceiveData()). * @note RXNE pending bit can be also cleared by a read to the USART_DR register * (USART_ReceiveData()). * @note TC pending bit can be also cleared by software sequence: a read * operation to USART_SR register (USART_GetITStatus()) followed by a write * operation to USART_DR register (USART_SendData()). * @note TXE pending bit is cleared only by a write to the USART_DR register * (USART_SendData()). * * @retval None */ void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) { uint16_t bitpos = 0x00, itmask = 0x00; /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_CLEAR_IT(USART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */ if (USART_IT == USART_IT_CTS) { assert_param(IS_USART_1236_PERIPH(USARTx)); } bitpos = USART_IT >> 0x08; itmask = ((uint16_t)0x01 << (uint16_t)bitpos); USARTx->SR = (uint16_t)~itmask; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c ================================================ /** ****************************************************************************** * @file stm32f4xx_wwdg.c * @author MCD Application Team * @version V1.3.0 * @date 08-November-2013 * @brief This file provides firmware functions to manage the following * functionalities of the Window watchdog (WWDG) peripheral: * + Prescaler, Refresh window and Counter configuration * + WWDG activation * + Interrupts and flags management * @verbatim =============================================================================== ##### WWDG features ##### =============================================================================== [..] Once enabled the WWDG generates a system reset on expiry of a programmed time period, unless the program refreshes the counter (downcounter) before to reach 0x3F value (i.e. a reset is generated when the counter value rolls over from 0x40 to 0x3F). An MCU reset is also generated if the counter value is refreshed before the counter has reached the refresh window value. This implies that the counter must be refreshed in a limited window. Once enabled the WWDG cannot be disabled except by a system reset. WWDGRST flag in RCC_CSR register can be used to inform when a WWDG reset occurs. The WWDG counter input clock is derived from the APB clock divided by a programmable prescaler. WWDG counter clock = PCLK1 / Prescaler WWDG timeout = (WWDG counter clock) * (counter value) Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms ##### How to use this driver ##### =============================================================================== [..] (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function (#) Set the WWDG counter value and start it using WWDG_Enable() function. When the WWDG is enabled the counter value should be configured to a value greater than 0x40 to prevent generating an immediate reset. (#) Optionally you can enable the Early wakeup interrupt which is generated when the counter reach 0x40. Once enabled this interrupt cannot be disabled except by a system reset. (#) Then the application program must refresh the WWDG counter at regular intervals during normal operation to prevent an MCU reset, using WWDG_SetCounter() function. This operation must occur only when the counter value is lower than the refresh window value, programmed using WWDG_SetWindowValue(). @endverbatim ****************************************************************************** * @attention * *

© COPYRIGHT 2013 STMicroelectronics

* * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); * You may not use this file except in compliance with the License. * You may obtain a copy of the License at: * * http://www.st.com/software_license_agreement_liberty_v2 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_wwdg.h" #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup WWDG * @brief WWDG driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* ----------- WWDG registers bit address in the alias region ----------- */ #define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) /* Alias word address of EWI bit */ #define CFR_OFFSET (WWDG_OFFSET + 0x04) #define EWI_BitNumber 0x09 #define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) /* --------------------- WWDG registers bit mask ------------------------ */ /* CFR register bit mask */ #define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) #define CFR_W_MASK ((uint32_t)0xFFFFFF80) #define BIT_MASK ((uint8_t)0x7F) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup WWDG_Private_Functions * @{ */ /** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions * @brief Prescaler, Refresh window and Counter configuration functions * @verbatim =============================================================================== ##### Prescaler, Refresh window and Counter configuration functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Deinitializes the WWDG peripheral registers to their default reset values. * @param None * @retval None */ void WWDG_DeInit(void) { RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); } /** * @brief Sets the WWDG Prescaler. * @param WWDG_Prescaler: specifies the WWDG Prescaler. * This parameter can be one of the following values: * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 * @retval None */ void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) { uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); /* Clear WDGTB[1:0] bits */ tmpreg = WWDG->CFR & CFR_WDGTB_MASK; /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ tmpreg |= WWDG_Prescaler; /* Store the new value */ WWDG->CFR = tmpreg; } /** * @brief Sets the WWDG window value. * @param WindowValue: specifies the window value to be compared to the downcounter. * This parameter value must be lower than 0x80. * @retval None */ void WWDG_SetWindowValue(uint8_t WindowValue) { __IO uint32_t tmpreg = 0; /* Check the parameters */ assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); /* Clear W[6:0] bits */ tmpreg = WWDG->CFR & CFR_W_MASK; /* Set W[6:0] bits according to WindowValue value */ tmpreg |= WindowValue & (uint32_t) BIT_MASK; /* Store the new value */ WWDG->CFR = tmpreg; } /** * @brief Enables the WWDG Early Wakeup interrupt(EWI). * @note Once enabled this interrupt cannot be disabled except by a system reset. * @param None * @retval None */ void WWDG_EnableIT(void) { *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; } /** * @brief Sets the WWDG counter value. * @param Counter: specifies the watchdog counter value. * This parameter must be a number between 0x40 and 0x7F (to prevent generating * an immediate reset) * @retval None */ void WWDG_SetCounter(uint8_t Counter) { /* Check the parameters */ assert_param(IS_WWDG_COUNTER(Counter)); /* Write to T[6:0] bits to configure the counter value, no need to do a read-modify-write; writing a 0 to WDGA bit does nothing */ WWDG->CR = Counter & BIT_MASK; } /** * @} */ /** @defgroup WWDG_Group2 WWDG activation functions * @brief WWDG activation functions * @verbatim =============================================================================== ##### WWDG activation function ##### =============================================================================== @endverbatim * @{ */ /** * @brief Enables WWDG and load the counter value. * @param Counter: specifies the watchdog counter value. * This parameter must be a number between 0x40 and 0x7F (to prevent generating * an immediate reset) * @retval None */ void WWDG_Enable(uint8_t Counter) { /* Check the parameters */ assert_param(IS_WWDG_COUNTER(Counter)); WWDG->CR = WWDG_CR_WDGA | Counter; } /** * @} */ /** @defgroup WWDG_Group3 Interrupts and flags management functions * @brief Interrupts and flags management functions * @verbatim =============================================================================== ##### Interrupts and flags management functions ##### =============================================================================== @endverbatim * @{ */ /** * @brief Checks whether the Early Wakeup interrupt flag is set or not. * @param None * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) */ FlagStatus WWDG_GetFlagStatus(void) { FlagStatus bitstatus = RESET; if ((WWDG->SR) != (uint32_t)RESET) { bitstatus = SET; } else { bitstatus = RESET; } return bitstatus; } /** * @brief Clears Early Wakeup interrupt flag. * @param None * @retval None */ void WWDG_ClearFlag(void) { WWDG->SR = (uint32_t)RESET; } /** * @} */ /** * @} */ /** * @} */ /** * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ ================================================ FILE: Libraries/eMPL/dmpKey.h ================================================ /* $License: Copyright (C) 2011 InvenSense Corporation, All Rights Reserved. $ */ #ifndef DMPKEY_H__ #define DMPKEY_H__ #define KEY_CFG_25 (0) #define KEY_CFG_24 (KEY_CFG_25 + 1) #define KEY_CFG_26 (KEY_CFG_24 + 1) #define KEY_CFG_27 (KEY_CFG_26 + 1) #define KEY_CFG_21 (KEY_CFG_27 + 1) #define KEY_CFG_20 (KEY_CFG_21 + 1) #define KEY_CFG_TAP4 (KEY_CFG_20 + 1) #define KEY_CFG_TAP5 (KEY_CFG_TAP4 + 1) #define KEY_CFG_TAP6 (KEY_CFG_TAP5 + 1) #define KEY_CFG_TAP7 (KEY_CFG_TAP6 + 1) #define KEY_CFG_TAP0 (KEY_CFG_TAP7 + 1) #define KEY_CFG_TAP1 (KEY_CFG_TAP0 + 1) #define KEY_CFG_TAP2 (KEY_CFG_TAP1 + 1) #define KEY_CFG_TAP3 (KEY_CFG_TAP2 + 1) #define KEY_CFG_TAP_QUANTIZE (KEY_CFG_TAP3 + 1) #define KEY_CFG_TAP_JERK (KEY_CFG_TAP_QUANTIZE + 1) #define KEY_CFG_DR_INT (KEY_CFG_TAP_JERK + 1) #define KEY_CFG_AUTH (KEY_CFG_DR_INT + 1) #define KEY_CFG_TAP_SAVE_ACCB (KEY_CFG_AUTH + 1) #define KEY_CFG_TAP_CLEAR_STICKY (KEY_CFG_TAP_SAVE_ACCB + 1) #define KEY_CFG_FIFO_ON_EVENT (KEY_CFG_TAP_CLEAR_STICKY + 1) #define KEY_FCFG_ACCEL_INPUT (KEY_CFG_FIFO_ON_EVENT + 1) #define KEY_FCFG_ACCEL_INIT (KEY_FCFG_ACCEL_INPUT + 1) #define KEY_CFG_23 (KEY_FCFG_ACCEL_INIT + 1) #define KEY_FCFG_1 (KEY_CFG_23 + 1) #define KEY_FCFG_3 (KEY_FCFG_1 + 1) #define KEY_FCFG_2 (KEY_FCFG_3 + 1) #define KEY_CFG_3D (KEY_FCFG_2 + 1) #define KEY_CFG_3B (KEY_CFG_3D + 1) #define KEY_CFG_3C (KEY_CFG_3B + 1) #define KEY_FCFG_5 (KEY_CFG_3C + 1) #define KEY_FCFG_4 (KEY_FCFG_5 + 1) #define KEY_FCFG_7 (KEY_FCFG_4 + 1) #define KEY_FCFG_FSCALE (KEY_FCFG_7 + 1) #define KEY_FCFG_AZ (KEY_FCFG_FSCALE + 1) #define KEY_FCFG_6 (KEY_FCFG_AZ + 1) #define KEY_FCFG_LSB4 (KEY_FCFG_6 + 1) #define KEY_CFG_12 (KEY_FCFG_LSB4 + 1) #define KEY_CFG_14 (KEY_CFG_12 + 1) #define KEY_CFG_15 (KEY_CFG_14 + 1) #define KEY_CFG_16 (KEY_CFG_15 + 1) #define KEY_CFG_18 (KEY_CFG_16 + 1) #define KEY_CFG_6 (KEY_CFG_18 + 1) #define KEY_CFG_7 (KEY_CFG_6 + 1) #define KEY_CFG_4 (KEY_CFG_7 + 1) #define KEY_CFG_5 (KEY_CFG_4 + 1) #define KEY_CFG_2 (KEY_CFG_5 + 1) #define KEY_CFG_3 (KEY_CFG_2 + 1) #define KEY_CFG_1 (KEY_CFG_3 + 1) #define KEY_CFG_EXTERNAL (KEY_CFG_1 + 1) #define KEY_CFG_8 (KEY_CFG_EXTERNAL + 1) #define KEY_CFG_9 (KEY_CFG_8 + 1) #define KEY_CFG_ORIENT_3 (KEY_CFG_9 + 1) #define KEY_CFG_ORIENT_2 (KEY_CFG_ORIENT_3 + 1) #define KEY_CFG_ORIENT_1 (KEY_CFG_ORIENT_2 + 1) #define KEY_CFG_GYRO_SOURCE (KEY_CFG_ORIENT_1 + 1) #define KEY_CFG_ORIENT_IRQ_1 (KEY_CFG_GYRO_SOURCE + 1) #define KEY_CFG_ORIENT_IRQ_2 (KEY_CFG_ORIENT_IRQ_1 + 1) #define KEY_CFG_ORIENT_IRQ_3 (KEY_CFG_ORIENT_IRQ_2 + 1) #define KEY_FCFG_MAG_VAL (KEY_CFG_ORIENT_IRQ_3 + 1) #define KEY_FCFG_MAG_MOV (KEY_FCFG_MAG_VAL + 1) #define KEY_CFG_LP_QUAT (KEY_FCFG_MAG_MOV + 1) /* MPU6050 keys */ #define KEY_CFG_ACCEL_FILTER (KEY_CFG_LP_QUAT + 1) #define KEY_CFG_MOTION_BIAS (KEY_CFG_ACCEL_FILTER + 1) #define KEY_TEMPLABEL (KEY_CFG_MOTION_BIAS + 1) #define KEY_D_0_22 (KEY_TEMPLABEL + 1) #define KEY_D_0_24 (KEY_D_0_22 + 1) #define KEY_D_0_36 (KEY_D_0_24 + 1) #define KEY_D_0_52 (KEY_D_0_36 + 1) #define KEY_D_0_96 (KEY_D_0_52 + 1) #define KEY_D_0_104 (KEY_D_0_96 + 1) #define KEY_D_0_108 (KEY_D_0_104 + 1) #define KEY_D_0_163 (KEY_D_0_108 + 1) #define KEY_D_0_188 (KEY_D_0_163 + 1) #define KEY_D_0_192 (KEY_D_0_188 + 1) #define KEY_D_0_224 (KEY_D_0_192 + 1) #define KEY_D_0_228 (KEY_D_0_224 + 1) #define KEY_D_0_232 (KEY_D_0_228 + 1) #define KEY_D_0_236 (KEY_D_0_232 + 1) #define KEY_DMP_PREVPTAT (KEY_D_0_236 + 1) #define KEY_D_1_2 (KEY_DMP_PREVPTAT + 1) #define KEY_D_1_4 (KEY_D_1_2 + 1) #define KEY_D_1_8 (KEY_D_1_4 + 1) #define KEY_D_1_10 (KEY_D_1_8 + 1) #define KEY_D_1_24 (KEY_D_1_10 + 1) #define KEY_D_1_28 (KEY_D_1_24 + 1) #define KEY_D_1_36 (KEY_D_1_28 + 1) #define KEY_D_1_40 (KEY_D_1_36 + 1) #define KEY_D_1_44 (KEY_D_1_40 + 1) #define KEY_D_1_72 (KEY_D_1_44 + 1) #define KEY_D_1_74 (KEY_D_1_72 + 1) #define KEY_D_1_79 (KEY_D_1_74 + 1) #define KEY_D_1_88 (KEY_D_1_79 + 1) #define KEY_D_1_90 (KEY_D_1_88 + 1) #define KEY_D_1_92 (KEY_D_1_90 + 1) #define KEY_D_1_96 (KEY_D_1_92 + 1) #define KEY_D_1_98 (KEY_D_1_96 + 1) #define KEY_D_1_100 (KEY_D_1_98 + 1) #define KEY_D_1_106 (KEY_D_1_100 + 1) #define KEY_D_1_108 (KEY_D_1_106 + 1) #define KEY_D_1_112 (KEY_D_1_108 + 1) #define KEY_D_1_128 (KEY_D_1_112 + 1) #define KEY_D_1_152 (KEY_D_1_128 + 1) #define KEY_D_1_160 (KEY_D_1_152 + 1) #define KEY_D_1_168 (KEY_D_1_160 + 1) #define KEY_D_1_175 (KEY_D_1_168 + 1) #define KEY_D_1_176 (KEY_D_1_175 + 1) #define KEY_D_1_178 (KEY_D_1_176 + 1) #define KEY_D_1_179 (KEY_D_1_178 + 1) #define KEY_D_1_218 (KEY_D_1_179 + 1) #define KEY_D_1_232 (KEY_D_1_218 + 1) #define KEY_D_1_236 (KEY_D_1_232 + 1) #define KEY_D_1_240 (KEY_D_1_236 + 1) #define KEY_D_1_244 (KEY_D_1_240 + 1) #define KEY_D_1_250 (KEY_D_1_244 + 1) #define KEY_D_1_252 (KEY_D_1_250 + 1) #define KEY_D_2_12 (KEY_D_1_252 + 1) #define KEY_D_2_96 (KEY_D_2_12 + 1) #define KEY_D_2_108 (KEY_D_2_96 + 1) #define KEY_D_2_208 (KEY_D_2_108 + 1) #define KEY_FLICK_MSG (KEY_D_2_208 + 1) #define KEY_FLICK_COUNTER (KEY_FLICK_MSG + 1) #define KEY_FLICK_LOWER (KEY_FLICK_COUNTER + 1) #define KEY_CFG_FLICK_IN (KEY_FLICK_LOWER + 1) #define KEY_FLICK_UPPER (KEY_CFG_FLICK_IN + 1) #define KEY_CGNOTICE_INTR (KEY_FLICK_UPPER + 1) #define KEY_D_2_224 (KEY_CGNOTICE_INTR + 1) #define KEY_D_2_244 (KEY_D_2_224 + 1) #define KEY_D_2_248 (KEY_D_2_244 + 1) #define KEY_D_2_252 (KEY_D_2_248 + 1) #define KEY_D_GYRO_BIAS_X (KEY_D_2_252 + 1) #define KEY_D_GYRO_BIAS_Y (KEY_D_GYRO_BIAS_X + 1) #define KEY_D_GYRO_BIAS_Z (KEY_D_GYRO_BIAS_Y + 1) #define KEY_D_ACC_BIAS_X (KEY_D_GYRO_BIAS_Z + 1) #define KEY_D_ACC_BIAS_Y (KEY_D_ACC_BIAS_X + 1) #define KEY_D_ACC_BIAS_Z (KEY_D_ACC_BIAS_Y + 1) #define KEY_D_GYRO_ENABLE (KEY_D_ACC_BIAS_Z + 1) #define KEY_D_ACCEL_ENABLE (KEY_D_GYRO_ENABLE + 1) #define KEY_D_QUAT_ENABLE (KEY_D_ACCEL_ENABLE +1) #define KEY_D_OUTPUT_ENABLE (KEY_D_QUAT_ENABLE + 1) #define KEY_D_CR_TIME_G (KEY_D_OUTPUT_ENABLE + 1) #define KEY_D_CR_TIME_A (KEY_D_CR_TIME_G + 1) #define KEY_D_CR_TIME_Q (KEY_D_CR_TIME_A + 1) #define KEY_D_CS_TAX (KEY_D_CR_TIME_Q + 1) #define KEY_D_CS_TAY (KEY_D_CS_TAX + 1) #define KEY_D_CS_TAZ (KEY_D_CS_TAY + 1) #define KEY_D_CS_TGX (KEY_D_CS_TAZ + 1) #define KEY_D_CS_TGY (KEY_D_CS_TGX + 1) #define KEY_D_CS_TGZ (KEY_D_CS_TGY + 1) #define KEY_D_CS_TQ0 (KEY_D_CS_TGZ + 1) #define KEY_D_CS_TQ1 (KEY_D_CS_TQ0 + 1) #define KEY_D_CS_TQ2 (KEY_D_CS_TQ1 + 1) #define KEY_D_CS_TQ3 (KEY_D_CS_TQ2 + 1) /* Compass keys */ #define KEY_CPASS_BIAS_X (KEY_D_CS_TQ3 + 1) #define KEY_CPASS_BIAS_Y (KEY_CPASS_BIAS_X + 1) #define KEY_CPASS_BIAS_Z (KEY_CPASS_BIAS_Y + 1) #define KEY_CPASS_MTX_00 (KEY_CPASS_BIAS_Z + 1) #define KEY_CPASS_MTX_01 (KEY_CPASS_MTX_00 + 1) #define KEY_CPASS_MTX_02 (KEY_CPASS_MTX_01 + 1) #define KEY_CPASS_MTX_10 (KEY_CPASS_MTX_02 + 1) #define KEY_CPASS_MTX_11 (KEY_CPASS_MTX_10 + 1) #define KEY_CPASS_MTX_12 (KEY_CPASS_MTX_11 + 1) #define KEY_CPASS_MTX_20 (KEY_CPASS_MTX_12 + 1) #define KEY_CPASS_MTX_21 (KEY_CPASS_MTX_20 + 1) #define KEY_CPASS_MTX_22 (KEY_CPASS_MTX_21 + 1) /* Gesture Keys */ #define KEY_DMP_TAPW_MIN (KEY_CPASS_MTX_22 + 1) #define KEY_DMP_TAP_THR_X (KEY_DMP_TAPW_MIN + 1) #define KEY_DMP_TAP_THR_Y (KEY_DMP_TAP_THR_X + 1) #define KEY_DMP_TAP_THR_Z (KEY_DMP_TAP_THR_Y + 1) #define KEY_DMP_SH_TH_Y (KEY_DMP_TAP_THR_Z + 1) #define KEY_DMP_SH_TH_X (KEY_DMP_SH_TH_Y + 1) #define KEY_DMP_SH_TH_Z (KEY_DMP_SH_TH_X + 1) #define KEY_DMP_ORIENT (KEY_DMP_SH_TH_Z + 1) #define KEY_D_ACT0 (KEY_DMP_ORIENT + 1) #define KEY_D_ACSX (KEY_D_ACT0 + 1) #define KEY_D_ACSY (KEY_D_ACSX + 1) #define KEY_D_ACSZ (KEY_D_ACSY + 1) #define KEY_X_GRT_Y_TMP (KEY_D_ACSZ + 1) #define KEY_SKIP_X_GRT_Y_TMP (KEY_X_GRT_Y_TMP + 1) #define KEY_SKIP_END_COMPARE (KEY_SKIP_X_GRT_Y_TMP + 1) #define KEY_END_COMPARE_Y_X_TMP2 (KEY_SKIP_END_COMPARE + 1) #define KEY_CFG_ANDROID_ORIENT_INT (KEY_END_COMPARE_Y_X_TMP2 + 1) #define KEY_NO_ORIENT_INTERRUPT (KEY_CFG_ANDROID_ORIENT_INT + 1) #define KEY_END_COMPARE_Y_X_TMP (KEY_NO_ORIENT_INTERRUPT + 1) #define KEY_END_ORIENT_1 (KEY_END_COMPARE_Y_X_TMP + 1) #define KEY_END_COMPARE_Y_X (KEY_END_ORIENT_1 + 1) #define KEY_END_ORIENT (KEY_END_COMPARE_Y_X + 1) #define KEY_X_GRT_Y (KEY_END_ORIENT + 1) #define KEY_NOT_TIME_MINUS_1 (KEY_X_GRT_Y + 1) #define KEY_END_COMPARE_Y_X_TMP3 (KEY_NOT_TIME_MINUS_1 + 1) #define KEY_X_GRT_Y_TMP2 (KEY_END_COMPARE_Y_X_TMP3 + 1) /* Authenticate Keys */ #define KEY_D_AUTH_OUT (KEY_X_GRT_Y_TMP2 + 1) #define KEY_D_AUTH_IN (KEY_D_AUTH_OUT + 1) #define KEY_D_AUTH_A (KEY_D_AUTH_IN + 1) #define KEY_D_AUTH_B (KEY_D_AUTH_A + 1) /* Pedometer standalone only keys */ #define KEY_D_PEDSTD_BP_B (KEY_D_AUTH_B + 1) #define KEY_D_PEDSTD_HP_A (KEY_D_PEDSTD_BP_B + 1) #define KEY_D_PEDSTD_HP_B (KEY_D_PEDSTD_HP_A + 1) #define KEY_D_PEDSTD_BP_A4 (KEY_D_PEDSTD_HP_B + 1) #define KEY_D_PEDSTD_BP_A3 (KEY_D_PEDSTD_BP_A4 + 1) #define KEY_D_PEDSTD_BP_A2 (KEY_D_PEDSTD_BP_A3 + 1) #define KEY_D_PEDSTD_BP_A1 (KEY_D_PEDSTD_BP_A2 + 1) #define KEY_D_PEDSTD_INT_THRSH (KEY_D_PEDSTD_BP_A1 + 1) #define KEY_D_PEDSTD_CLIP (KEY_D_PEDSTD_INT_THRSH + 1) #define KEY_D_PEDSTD_SB (KEY_D_PEDSTD_CLIP + 1) #define KEY_D_PEDSTD_SB_TIME (KEY_D_PEDSTD_SB + 1) #define KEY_D_PEDSTD_PEAKTHRSH (KEY_D_PEDSTD_SB_TIME + 1) #define KEY_D_PEDSTD_TIML (KEY_D_PEDSTD_PEAKTHRSH + 1) #define KEY_D_PEDSTD_TIMH (KEY_D_PEDSTD_TIML + 1) #define KEY_D_PEDSTD_PEAK (KEY_D_PEDSTD_TIMH + 1) #define KEY_D_PEDSTD_TIMECTR (KEY_D_PEDSTD_PEAK + 1) #define KEY_D_PEDSTD_STEPCTR (KEY_D_PEDSTD_TIMECTR + 1) #define KEY_D_PEDSTD_WALKTIME (KEY_D_PEDSTD_STEPCTR + 1) #define KEY_D_PEDSTD_DECI (KEY_D_PEDSTD_WALKTIME + 1) /*Host Based No Motion*/ #define KEY_D_HOST_NO_MOT (KEY_D_PEDSTD_DECI + 1) /* EIS keys */ #define KEY_P_EIS_FIFO_FOOTER (KEY_D_HOST_NO_MOT + 1) #define KEY_P_EIS_FIFO_YSHIFT (KEY_P_EIS_FIFO_FOOTER + 1) #define KEY_P_EIS_DATA_RATE (KEY_P_EIS_FIFO_YSHIFT + 1) #define KEY_P_EIS_FIFO_XSHIFT (KEY_P_EIS_DATA_RATE + 1) #define KEY_P_EIS_FIFO_SYNC (KEY_P_EIS_FIFO_XSHIFT + 1) #define KEY_P_EIS_FIFO_ZSHIFT (KEY_P_EIS_FIFO_SYNC + 1) #define KEY_P_EIS_FIFO_READY (KEY_P_EIS_FIFO_ZSHIFT + 1) #define KEY_DMP_FOOTER (KEY_P_EIS_FIFO_READY + 1) #define KEY_DMP_INTX_HC (KEY_DMP_FOOTER + 1) #define KEY_DMP_INTX_PH (KEY_DMP_INTX_HC + 1) #define KEY_DMP_INTX_SH (KEY_DMP_INTX_PH + 1) #define KEY_DMP_AINV_SH (KEY_DMP_INTX_SH + 1) #define KEY_DMP_A_INV_XH (KEY_DMP_AINV_SH + 1) #define KEY_DMP_AINV_PH (KEY_DMP_A_INV_XH + 1) #define KEY_DMP_CTHX_H (KEY_DMP_AINV_PH + 1) #define KEY_DMP_CTHY_H (KEY_DMP_CTHX_H + 1) #define KEY_DMP_CTHZ_H (KEY_DMP_CTHY_H + 1) #define KEY_DMP_NCTHX_H (KEY_DMP_CTHZ_H + 1) #define KEY_DMP_NCTHY_H (KEY_DMP_NCTHX_H + 1) #define KEY_DMP_NCTHZ_H (KEY_DMP_NCTHY_H + 1) #define KEY_DMP_CTSQ_XH (KEY_DMP_NCTHZ_H + 1) #define KEY_DMP_CTSQ_YH (KEY_DMP_CTSQ_XH + 1) #define KEY_DMP_CTSQ_ZH (KEY_DMP_CTSQ_YH + 1) #define KEY_DMP_INTX_H (KEY_DMP_CTSQ_ZH + 1) #define KEY_DMP_INTY_H (KEY_DMP_INTX_H + 1) #define KEY_DMP_INTZ_H (KEY_DMP_INTY_H + 1) //#define KEY_DMP_HPX_H (KEY_DMP_INTZ_H + 1) //#define KEY_DMP_HPY_H (KEY_DMP_HPX_H + 1) //#define KEY_DMP_HPZ_H (KEY_DMP_HPY_H + 1) /* Stream keys */ #define KEY_STREAM_P_GYRO_Z (KEY_DMP_INTZ_H + 1) #define KEY_STREAM_P_GYRO_Y (KEY_STREAM_P_GYRO_Z + 1) #define KEY_STREAM_P_GYRO_X (KEY_STREAM_P_GYRO_Y + 1) #define KEY_STREAM_P_TEMP (KEY_STREAM_P_GYRO_X + 1) #define KEY_STREAM_P_AUX_Y (KEY_STREAM_P_TEMP + 1) #define KEY_STREAM_P_AUX_X (KEY_STREAM_P_AUX_Y + 1) #define KEY_STREAM_P_AUX_Z (KEY_STREAM_P_AUX_X + 1) #define KEY_STREAM_P_ACCEL_Y (KEY_STREAM_P_AUX_Z + 1) #define KEY_STREAM_P_ACCEL_X (KEY_STREAM_P_ACCEL_Y + 1) #define KEY_STREAM_P_FOOTER (KEY_STREAM_P_ACCEL_X + 1) #define KEY_STREAM_P_ACCEL_Z (KEY_STREAM_P_FOOTER + 1) #define NUM_KEYS (KEY_STREAM_P_ACCEL_Z + 1) typedef struct { unsigned short key; unsigned short addr; } tKeyLabel; #define DINA0A 0x0a #define DINA22 0x22 #define DINA42 0x42 #define DINA5A 0x5a #define DINA06 0x06 #define DINA0E 0x0e #define DINA16 0x16 #define DINA1E 0x1e #define DINA26 0x26 #define DINA2E 0x2e #define DINA36 0x36 #define DINA3E 0x3e #define DINA46 0x46 #define DINA4E 0x4e #define DINA56 0x56 #define DINA5E 0x5e #define DINA66 0x66 #define DINA6E 0x6e #define DINA76 0x76 #define DINA7E 0x7e #define DINA00 0x00 #define DINA08 0x08 #define DINA10 0x10 #define DINA18 0x18 #define DINA20 0x20 #define DINA28 0x28 #define DINA30 0x30 #define DINA38 0x38 #define DINA40 0x40 #define DINA48 0x48 #define DINA50 0x50 #define DINA58 0x58 #define DINA60 0x60 #define DINA68 0x68 #define DINA70 0x70 #define DINA78 0x78 #define DINA04 0x04 #define DINA0C 0x0c #define DINA14 0x14 #define DINA1C 0x1C #define DINA24 0x24 #define DINA2C 0x2c #define DINA34 0x34 #define DINA3C 0x3c #define DINA44 0x44 #define DINA4C 0x4c #define DINA54 0x54 #define DINA5C 0x5c #define DINA64 0x64 #define DINA6C 0x6c #define DINA74 0x74 #define DINA7C 0x7c #define DINA01 0x01 #define DINA09 0x09 #define DINA11 0x11 #define DINA19 0x19 #define DINA21 0x21 #define DINA29 0x29 #define DINA31 0x31 #define DINA39 0x39 #define DINA41 0x41 #define DINA49 0x49 #define DINA51 0x51 #define DINA59 0x59 #define DINA61 0x61 #define DINA69 0x69 #define DINA71 0x71 #define DINA79 0x79 #define DINA25 0x25 #define DINA2D 0x2d #define DINA35 0x35 #define DINA3D 0x3d #define DINA4D 0x4d #define DINA55 0x55 #define DINA5D 0x5D #define DINA6D 0x6d #define DINA75 0x75 #define DINA7D 0x7d #define DINADC 0xdc #define DINAF2 0xf2 #define DINAAB 0xab #define DINAAA 0xaa #define DINAF1 0xf1 #define DINADF 0xdf #define DINADA 0xda #define DINAB1 0xb1 #define DINAB9 0xb9 #define DINAF3 0xf3 #define DINA8B 0x8b #define DINAA3 0xa3 #define DINA91 0x91 #define DINAB6 0xb6 #define DINAB4 0xb4 #define DINC00 0x00 #define DINC01 0x01 #define DINC02 0x02 #define DINC03 0x03 #define DINC08 0x08 #define DINC09 0x09 #define DINC0A 0x0a #define DINC0B 0x0b #define DINC10 0x10 #define DINC11 0x11 #define DINC12 0x12 #define DINC13 0x13 #define DINC18 0x18 #define DINC19 0x19 #define DINC1A 0x1a #define DINC1B 0x1b #define DINC20 0x20 #define DINC21 0x21 #define DINC22 0x22 #define DINC23 0x23 #define DINC28 0x28 #define DINC29 0x29 #define DINC2A 0x2a #define DINC2B 0x2b #define DINC30 0x30 #define DINC31 0x31 #define DINC32 0x32 #define DINC33 0x33 #define DINC38 0x38 #define DINC39 0x39 #define DINC3A 0x3a #define DINC3B 0x3b #define DINC40 0x40 #define DINC41 0x41 #define DINC42 0x42 #define DINC43 0x43 #define DINC48 0x48 #define DINC49 0x49 #define DINC4A 0x4a #define DINC4B 0x4b #define DINC50 0x50 #define DINC51 0x51 #define DINC52 0x52 #define DINC53 0x53 #define DINC58 0x58 #define DINC59 0x59 #define DINC5A 0x5a #define DINC5B 0x5b #define DINC60 0x60 #define DINC61 0x61 #define DINC62 0x62 #define DINC63 0x63 #define DINC68 0x68 #define DINC69 0x69 #define DINC6A 0x6a #define DINC6B 0x6b #define DINC70 0x70 #define DINC71 0x71 #define DINC72 0x72 #define DINC73 0x73 #define DINC78 0x78 #define DINC79 0x79 #define DINC7A 0x7a #define DINC7B 0x7b #define DIND40 0x40 #define DINA80 0x80 #define DINA90 0x90 #define DINAA0 0xa0 #define DINAC9 0xc9 #define DINACB 0xcb #define DINACD 0xcd #define DINACF 0xcf #define DINAC8 0xc8 #define DINACA 0xca #define DINACC 0xcc #define DINACE 0xce #define DINAD8 0xd8 #define DINADD 0xdd #define DINAF8 0xf0 #define DINAFE 0xfe #define DINBF8 0xf8 #define DINAC0 0xb0 #define DINAC1 0xb1 #define DINAC2 0xb4 #define DINAC3 0xb5 #define DINAC4 0xb8 #define DINAC5 0xb9 #define DINBC0 0xc0 #define DINBC2 0xc2 #define DINBC4 0xc4 #define DINBC6 0xc6 #endif // DMPKEY_H__ ================================================ FILE: Libraries/eMPL/dmpmap.h ================================================ /* $License: Copyright (C) 2011 InvenSense Corporation, All Rights Reserved. $ */ #ifndef DMPMAP_H #define DMPMAP_H #ifdef __cplusplus extern "C" { #endif #define DMP_PTAT 0 #define DMP_XGYR 2 #define DMP_YGYR 4 #define DMP_ZGYR 6 #define DMP_XACC 8 #define DMP_YACC 10 #define DMP_ZACC 12 #define DMP_ADC1 14 #define DMP_ADC2 16 #define DMP_ADC3 18 #define DMP_BIASUNC 20 #define DMP_FIFORT 22 #define DMP_INVGSFH 24 #define DMP_INVGSFL 26 #define DMP_1H 28 #define DMP_1L 30 #define DMP_BLPFSTCH 32 #define DMP_BLPFSTCL 34 #define DMP_BLPFSXH 36 #define DMP_BLPFSXL 38 #define DMP_BLPFSYH 40 #define DMP_BLPFSYL 42 #define DMP_BLPFSZH 44 #define DMP_BLPFSZL 46 #define DMP_BLPFMTC 48 #define DMP_SMC 50 #define DMP_BLPFMXH 52 #define DMP_BLPFMXL 54 #define DMP_BLPFMYH 56 #define DMP_BLPFMYL 58 #define DMP_BLPFMZH 60 #define DMP_BLPFMZL 62 #define DMP_BLPFC 64 #define DMP_SMCTH 66 #define DMP_0H2 68 #define DMP_0L2 70 #define DMP_BERR2H 72 #define DMP_BERR2L 74 #define DMP_BERR2NH 76 #define DMP_SMCINC 78 #define DMP_ANGVBXH 80 #define DMP_ANGVBXL 82 #define DMP_ANGVBYH 84 #define DMP_ANGVBYL 86 #define DMP_ANGVBZH 88 #define DMP_ANGVBZL 90 #define DMP_BERR1H 92 #define DMP_BERR1L 94 #define DMP_ATCH 96 #define DMP_BIASUNCSF 98 #define DMP_ACT2H 100 #define DMP_ACT2L 102 #define DMP_GSFH 104 #define DMP_GSFL 106 #define DMP_GH 108 #define DMP_GL 110 #define DMP_0_5H 112 #define DMP_0_5L 114 #define DMP_0_0H 116 #define DMP_0_0L 118 #define DMP_1_0H 120 #define DMP_1_0L 122 #define DMP_1_5H 124 #define DMP_1_5L 126 #define DMP_TMP1AH 128 #define DMP_TMP1AL 130 #define DMP_TMP2AH 132 #define DMP_TMP2AL 134 #define DMP_TMP3AH 136 #define DMP_TMP3AL 138 #define DMP_TMP4AH 140 #define DMP_TMP4AL 142 #define DMP_XACCW 144 #define DMP_TMP5 146 #define DMP_XACCB 148 #define DMP_TMP8 150 #define DMP_YACCB 152 #define DMP_TMP9 154 #define DMP_ZACCB 156 #define DMP_TMP10 158 #define DMP_DZH 160 #define DMP_DZL 162 #define DMP_XGCH 164 #define DMP_XGCL 166 #define DMP_YGCH 168 #define DMP_YGCL 170 #define DMP_ZGCH 172 #define DMP_ZGCL 174 #define DMP_YACCW 176 #define DMP_TMP7 178 #define DMP_AFB1H 180 #define DMP_AFB1L 182 #define DMP_AFB2H 184 #define DMP_AFB2L 186 #define DMP_MAGFBH 188 #define DMP_MAGFBL 190 #define DMP_QT1H 192 #define DMP_QT1L 194 #define DMP_QT2H 196 #define DMP_QT2L 198 #define DMP_QT3H 200 #define DMP_QT3L 202 #define DMP_QT4H 204 #define DMP_QT4L 206 #define DMP_CTRL1H 208 #define DMP_CTRL1L 210 #define DMP_CTRL2H 212 #define DMP_CTRL2L 214 #define DMP_CTRL3H 216 #define DMP_CTRL3L 218 #define DMP_CTRL4H 220 #define DMP_CTRL4L 222 #define DMP_CTRLS1 224 #define DMP_CTRLSF1 226 #define DMP_CTRLS2 228 #define DMP_CTRLSF2 230 #define DMP_CTRLS3 232 #define DMP_CTRLSFNLL 234 #define DMP_CTRLS4 236 #define DMP_CTRLSFNL2 238 #define DMP_CTRLSFNL 240 #define DMP_TMP30 242 #define DMP_CTRLSFJT 244 #define DMP_TMP31 246 #define DMP_TMP11 248 #define DMP_CTRLSF2_2 250 #define DMP_TMP12 252 #define DMP_CTRLSF1_2 254 #define DMP_PREVPTAT 256 #define DMP_ACCZB 258 #define DMP_ACCXB 264 #define DMP_ACCYB 266 #define DMP_1HB 272 #define DMP_1LB 274 #define DMP_0H 276 #define DMP_0L 278 #define DMP_ASR22H 280 #define DMP_ASR22L 282 #define DMP_ASR6H 284 #define DMP_ASR6L 286 #define DMP_TMP13 288 #define DMP_TMP14 290 #define DMP_FINTXH 292 #define DMP_FINTXL 294 #define DMP_FINTYH 296 #define DMP_FINTYL 298 #define DMP_FINTZH 300 #define DMP_FINTZL 302 #define DMP_TMP1BH 304 #define DMP_TMP1BL 306 #define DMP_TMP2BH 308 #define DMP_TMP2BL 310 #define DMP_TMP3BH 312 #define DMP_TMP3BL 314 #define DMP_TMP4BH 316 #define DMP_TMP4BL 318 #define DMP_STXG 320 #define DMP_ZCTXG 322 #define DMP_STYG 324 #define DMP_ZCTYG 326 #define DMP_STZG 328 #define DMP_ZCTZG 330 #define DMP_CTRLSFJT2 332 #define DMP_CTRLSFJTCNT 334 #define DMP_PVXG 336 #define DMP_TMP15 338 #define DMP_PVYG 340 #define DMP_TMP16 342 #define DMP_PVZG 344 #define DMP_TMP17 346 #define DMP_MNMFLAGH 352 #define DMP_MNMFLAGL 354 #define DMP_MNMTMH 356 #define DMP_MNMTML 358 #define DMP_MNMTMTHRH 360 #define DMP_MNMTMTHRL 362 #define DMP_MNMTHRH 364 #define DMP_MNMTHRL 366 #define DMP_ACCQD4H 368 #define DMP_ACCQD4L 370 #define DMP_ACCQD5H 372 #define DMP_ACCQD5L 374 #define DMP_ACCQD6H 376 #define DMP_ACCQD6L 378 #define DMP_ACCQD7H 380 #define DMP_ACCQD7L 382 #define DMP_ACCQD0H 384 #define DMP_ACCQD0L 386 #define DMP_ACCQD1H 388 #define DMP_ACCQD1L 390 #define DMP_ACCQD2H 392 #define DMP_ACCQD2L 394 #define DMP_ACCQD3H 396 #define DMP_ACCQD3L 398 #define DMP_XN2H 400 #define DMP_XN2L 402 #define DMP_XN1H 404 #define DMP_XN1L 406 #define DMP_YN2H 408 #define DMP_YN2L 410 #define DMP_YN1H 412 #define DMP_YN1L 414 #define DMP_YH 416 #define DMP_YL 418 #define DMP_B0H 420 #define DMP_B0L 422 #define DMP_A1H 424 #define DMP_A1L 426 #define DMP_A2H 428 #define DMP_A2L 430 #define DMP_SEM1 432 #define DMP_FIFOCNT 434 #define DMP_SH_TH_X 436 #define DMP_PACKET 438 #define DMP_SH_TH_Y 440 #define DMP_FOOTER 442 #define DMP_SH_TH_Z 444 #define DMP_TEMP29 448 #define DMP_TEMP30 450 #define DMP_XACCB_PRE 452 #define DMP_XACCB_PREL 454 #define DMP_YACCB_PRE 456 #define DMP_YACCB_PREL 458 #define DMP_ZACCB_PRE 460 #define DMP_ZACCB_PREL 462 #define DMP_TMP22 464 #define DMP_TAP_TIMER 466 #define DMP_TAP_THX 468 #define DMP_TAP_THY 472 #define DMP_TAP_THZ 476 #define DMP_TAPW_MIN 478 #define DMP_TMP25 480 #define DMP_TMP26 482 #define DMP_TMP27 484 #define DMP_TMP28 486 #define DMP_ORIENT 488 #define DMP_THRSH 490 #define DMP_ENDIANH 492 #define DMP_ENDIANL 494 #define DMP_BLPFNMTCH 496 #define DMP_BLPFNMTCL 498 #define DMP_BLPFNMXH 500 #define DMP_BLPFNMXL 502 #define DMP_BLPFNMYH 504 #define DMP_BLPFNMYL 506 #define DMP_BLPFNMZH 508 #define DMP_BLPFNMZL 510 #ifdef __cplusplus } #endif #endif // DMPMAP_H ================================================ FILE: Libraries/eMPL/inv_mpu.c ================================================ /* $License: Copyright (C) 2011-2012 InvenSense Corporation, All Rights Reserved. See included License.txt for License information. $ */ /** * @addtogroup DRIVERS Sensor Driver Layer * @brief Hardware drivers to communicate with sensors via I2C. * * @{ * @file inv_mpu.c * @brief An I2C-based driver for Invensense gyroscopes. * @details This driver currently works for the following devices: * MPU6050 * MPU6500 * MPU9150 (or MPU6050 w/ AK8975 on the auxiliary bus) * MPU9250 (or MPU6500 w/ AK8963 on the auxiliary bus) */ #include #include #include #include #include #include "inv_mpu.h" /* The following functions must be defined for this platform: * i2c_write(unsigned char slave_addr, unsigned char reg_addr, * unsigned char length, unsigned char const *data) * i2c_read(unsigned char slave_addr, unsigned char reg_addr, * unsigned char length, unsigned char *data) * delay_ms(unsigned long num_ms) * get_ms(unsigned long *count) * reg_int_cb(void (*cb)(void), unsigned char port, unsigned char pin) * labs(long x) * fabsf(float x) * min(int a, int b) */ #if defined MOTION_DRIVER_TARGET_MSP430 #include "msp430.h" #include "msp430_i2c.h" #include "msp430_clock.h" #include "msp430_interrupt.h" #define i2c_write msp430_i2c_write #define i2c_read msp430_i2c_read #define delay_ms msp430_delay_ms #define get_ms msp430_get_clock_ms static inline int reg_int_cb(struct int_param_s *int_param) { return msp430_reg_int_cb(int_param->cb, int_param->pin, int_param->lp_exit, int_param->active_low); } #define log_i(...) do {} while (0) #define log_e(...) do {} while (0) /* labs is already defined by TI's toolchain. */ /* fabs is for doubles. fabsf is for floats. */ #define fabs fabsf #define min(a,b) ((acb, int_param->pin, int_param->lp_exit, int_param->active_low); } #define log_i MPL_LOGI #define log_e MPL_LOGE /* labs is already defined by TI's toolchain. */ /* fabs is for doubles. fabsf is for floats. */ #define fabs fabsf #define min(a,b) ((apin, int_param->cb, int_param->arg); return 0; } #define log_i MPL_LOGI #define log_e MPL_LOGE /* UC3 is a 32-bit processor, so abs and labs are equivalent. */ #define labs abs #define fabs(x) (((x)>0)?(x):-(x)) #elif defined STM32F40_41xxx #include "stm32f4_mpu9250.h" #include "stm32f4_delay.h" #define log_i(...) do {} while (0) #define log_e(...) do {} while (0) #define delay_ms Delay_Ms #define get_ms Get_Ms #define min(a,b) ((a> 3 & 0x03 */ unsigned char gyro_fsr; /* Matches accel_cfg >> 3 & 0x03 */ unsigned char accel_fsr; /* Enabled sensors. Uses same masks as fifo_en, NOT pwr_mgmt_2. */ unsigned char sensors; /* Matches config register. */ unsigned char lpf; unsigned char clk_src; /* Sample rate, NOT rate divider. */ unsigned short sample_rate; /* Matches fifo_en register. */ unsigned char fifo_enable; /* Matches int enable register. */ unsigned char int_enable; /* 1 if devices on auxiliary I2C bus appear on the primary. */ unsigned char bypass_mode; /* 1 if half-sensitivity. * NOTE: This doesn't belong here, but everything else in hw_s is const, * and this allows us to save some precious RAM. */ unsigned char accel_half; /* 1 if device in low-power accel-only mode. */ unsigned char lp_accel_mode; /* 1 if interrupts are only triggered on motion events. */ unsigned char int_motion_only; struct motion_int_cache_s cache; /* 1 for active low interrupts. */ unsigned char active_low_int; /* 1 for latched interrupts. */ unsigned char latched_int; /* 1 if DMP is enabled. */ unsigned char dmp_on; /* Ensures that DMP will only be loaded once. */ unsigned char dmp_loaded; /* Sampling rate used when DMP is enabled. */ unsigned short dmp_sample_rate; #ifdef AK89xx_SECONDARY /* Compass sample rate. */ unsigned short compass_sample_rate; unsigned char compass_addr; short mag_sens_adj[3]; #endif }; /* Information for self-test. */ struct test_s { unsigned long gyro_sens; unsigned long accel_sens; unsigned char reg_rate_div; unsigned char reg_lpf; unsigned char reg_gyro_fsr; unsigned char reg_accel_fsr; unsigned short wait_ms; unsigned char packet_thresh; float min_dps; float max_dps; float max_gyro_var; float min_g; float max_g; float max_accel_var; #ifdef MPU6500 float max_g_offset; unsigned short sample_wait_ms; #endif }; /* Gyro driver state variables. */ struct gyro_state_s { const struct gyro_reg_s *reg; const struct hw_s *hw; struct chip_cfg_s chip_cfg; const struct test_s *test; }; /* Filter configurations. */ enum lpf_e { INV_FILTER_256HZ_NOLPF2 = 0, INV_FILTER_188HZ, INV_FILTER_98HZ, INV_FILTER_42HZ, INV_FILTER_20HZ, INV_FILTER_10HZ, INV_FILTER_5HZ, INV_FILTER_2100HZ_NOLPF, NUM_FILTER }; /* Full scale ranges. */ enum gyro_fsr_e { INV_FSR_250DPS = 0, INV_FSR_500DPS, INV_FSR_1000DPS, INV_FSR_2000DPS, NUM_GYRO_FSR }; /* Full scale ranges. */ enum accel_fsr_e { INV_FSR_2G = 0, INV_FSR_4G, INV_FSR_8G, INV_FSR_16G, NUM_ACCEL_FSR }; /* Clock sources. */ enum clock_sel_e { INV_CLK_INTERNAL = 0, INV_CLK_PLL, NUM_CLK }; /* Low-power accel wakeup rates. */ enum lp_accel_rate_e { #if defined MPU6050 INV_LPA_1_25HZ, INV_LPA_5HZ, INV_LPA_20HZ, INV_LPA_40HZ #elif defined MPU6500 INV_LPA_0_3125HZ, INV_LPA_0_625HZ, INV_LPA_1_25HZ, INV_LPA_2_5HZ, INV_LPA_5HZ, INV_LPA_10HZ, INV_LPA_20HZ, INV_LPA_40HZ, INV_LPA_80HZ, INV_LPA_160HZ, INV_LPA_320HZ, INV_LPA_640HZ #endif }; #define BIT_I2C_MST_VDDIO (0x80) #define BIT_FIFO_EN (0x40) #define BIT_DMP_EN (0x80) #define BIT_FIFO_RST (0x04) #define BIT_DMP_RST (0x08) #define BIT_FIFO_OVERFLOW (0x10) #define BIT_DATA_RDY_EN (0x01) #define BIT_DMP_INT_EN (0x02) #define BIT_MOT_INT_EN (0x40) #define BITS_FSR (0x18) #define BITS_LPF (0x07) #define BITS_HPF (0x07) #define BITS_CLK (0x07) #define BIT_FIFO_SIZE_1024 (0x40) #define BIT_FIFO_SIZE_2048 (0x80) #define BIT_FIFO_SIZE_4096 (0xC0) #define BIT_RESET (0x80) #define BIT_SLEEP (0x40) #define BIT_S0_DELAY_EN (0x01) #define BIT_S2_DELAY_EN (0x04) #define BITS_SLAVE_LENGTH (0x0F) #define BIT_SLAVE_BYTE_SW (0x40) #define BIT_SLAVE_GROUP (0x10) #define BIT_SLAVE_EN (0x80) #define BIT_I2C_READ (0x80) #define BITS_I2C_MASTER_DLY (0x1F) #define BIT_AUX_IF_EN (0x20) #define BIT_ACTL (0x80) #define BIT_LATCH_EN (0x20) #define BIT_ANY_RD_CLR (0x10) #define BIT_BYPASS_EN (0x02) #define BITS_WOM_EN (0xC0) #define BIT_LPA_CYCLE (0x20) #define BIT_STBY_XA (0x20) #define BIT_STBY_YA (0x10) #define BIT_STBY_ZA (0x08) #define BIT_STBY_XG (0x04) #define BIT_STBY_YG (0x02) #define BIT_STBY_ZG (0x01) #define BIT_STBY_XYZA (BIT_STBY_XA | BIT_STBY_YA | BIT_STBY_ZA) #define BIT_STBY_XYZG (BIT_STBY_XG | BIT_STBY_YG | BIT_STBY_ZG) #if defined AK8975_SECONDARY #define SUPPORTS_AK89xx_HIGH_SENS (0x00) #define AK89xx_FSR (9830) #elif defined AK8963_SECONDARY #define SUPPORTS_AK89xx_HIGH_SENS (0x10) #define AK89xx_FSR (4915) #endif #ifdef AK89xx_SECONDARY #define AKM_REG_WHOAMI (0x00) #define AKM_REG_ST1 (0x02) #define AKM_REG_HXL (0x03) #define AKM_REG_ST2 (0x09) #define AKM_REG_CNTL (0x0A) #define AKM_REG_ASTC (0x0C) #define AKM_REG_ASAX (0x10) #define AKM_REG_ASAY (0x11) #define AKM_REG_ASAZ (0x12) #define AKM_DATA_READY (0x01) #define AKM_DATA_OVERRUN (0x02) #define AKM_OVERFLOW (0x80) #define AKM_DATA_ERROR (0x40) #define AKM_BIT_SELF_TEST (0x40) #define AKM_POWER_DOWN (0x00 | SUPPORTS_AK89xx_HIGH_SENS) #define AKM_SINGLE_MEASUREMENT (0x01 | SUPPORTS_AK89xx_HIGH_SENS) #define AKM_FUSE_ROM_ACCESS (0x0F | SUPPORTS_AK89xx_HIGH_SENS) #define AKM_MODE_SELF_TEST (0x08 | SUPPORTS_AK89xx_HIGH_SENS) #define AKM_WHOAMI (0x48) #endif #if defined MPU6050 const struct gyro_reg_s reg = { .who_am_i = 0x75, .rate_div = 0x19, .lpf = 0x1A, .prod_id = 0x0C, .user_ctrl = 0x6A, .fifo_en = 0x23, .gyro_cfg = 0x1B, .accel_cfg = 0x1C, .motion_thr = 0x1F, .motion_dur = 0x20, .fifo_count_h = 0x72, .fifo_r_w = 0x74, .raw_gyro = 0x43, .raw_accel = 0x3B, .temp = 0x41, .int_enable = 0x38, .dmp_int_status = 0x39, .int_status = 0x3A, .pwr_mgmt_1 = 0x6B, .pwr_mgmt_2 = 0x6C, .int_pin_cfg = 0x37, .mem_r_w = 0x6F, .accel_offs = 0x06, .i2c_mst = 0x24, .bank_sel = 0x6D, .mem_start_addr = 0x6E, .prgm_start_h = 0x70 #ifdef AK89xx_SECONDARY ,.raw_compass = 0x49, .yg_offs_tc = 0x01, .s0_addr = 0x25, .s0_reg = 0x26, .s0_ctrl = 0x27, .s1_addr = 0x28, .s1_reg = 0x29, .s1_ctrl = 0x2A, .s4_ctrl = 0x34, .s0_do = 0x63, .s1_do = 0x64, .i2c_delay_ctrl = 0x67 #endif }; const struct hw_s hw = { .addr = 0x68, .max_fifo = 1024, .num_reg = 118, .temp_sens = 340, .temp_offset = -521, .bank_size = 256 #if defined AK89xx_SECONDARY ,.compass_fsr = AK89xx_FSR #endif }; const struct test_s test = { .gyro_sens = 32768/250, .accel_sens = 32768/16, .reg_rate_div = 0, /* 1kHz. */ .reg_lpf = 1, /* 188Hz. */ .reg_gyro_fsr = 0, /* 250dps. */ .reg_accel_fsr = 0x18, /* 16g. */ .wait_ms = 50, .packet_thresh = 5, /* 5% */ .min_dps = 10.f, .max_dps = 105.f, .max_gyro_var = 0.14f, .min_g = 0.3f, .max_g = 0.95f, .max_accel_var = 0.14f }; static struct gyro_state_s st = { .reg = ®, .hw = &hw, .test = &test }; #elif defined MPU6500 const struct gyro_reg_s reg = { /*.who_am_i = */0x75, /*.rate_div = */0x19, /*.lpf = */0x1A, /*.prod_id = */0x0C, /*.user_ctrl = */0x6A, /*.fifo_en = */0x23, /*.gyro_cfg = */0x1B, /*.accel_cfg = */0x1C, /*.accel_cfg2 = */0x1D, /*.lp_accel_odr = */0x1E, /*.motion_thr = */0x1F, /*.motion_dur = */0x20, /*.fifo_count_h = */0x72, /*.fifo_r_w = */0x74, /*.raw_gyro = */0x43, /*.raw_accel = */0x3B, /*.temp = */0x41, /*.int_enable = */0x38, /*.dmp_int_status = */0x39, /*.int_status = */0x3A, /*.accel_intel = */0x69, /*.pwr_mgmt_1 = */0x6B, /*.pwr_mgmt_2 = */0x6C, /*.int_pin_cfg = */0x37, /*.mem_r_w = */0x6F, /*.accel_offs = */0x77, /*.i2c_mst = */0x24, /*.bank_sel = */0x6D, /*.mem_start_addr = */0x6E, /*.prgm_start_h = */0x70 #ifdef AK89xx_SECONDARY ,/*.s0_addr = */0x25, /*.s0_reg = */0x26, /*.s0_ctrl = */0x27, /*.s1_addr = */0x28, /*.s1_reg = */0x29, /*.s1_ctrl = */0x2A, /*.s4_ctrl = */0x34, /*.s0_do = */0x63, /*.s1_do = */0x64, /*.i2c_delay_ctrl = */0x67, /*.raw_compass = */0x49 #endif }; const struct hw_s hw = { /*.addr = */0x68, /*.max_fifo = */1024, /*.num_reg = */128, /*.temp_sens = */321, /*.temp_offset = */0, /*.bank_size = */256 #if defined AK89xx_SECONDARY ,/*.compass_fsr = */AK89xx_FSR #endif }; const struct test_s test = { /*.gyro_sens = */32768/250, /*.accel_sens = */32768/2, //FSR = +-2G = 16384 LSB/G /*.reg_rate_div = */0, /* 1kHz. */ /*.reg_lpf = */2, /* 92Hz low pass filter*/ /*.reg_gyro_fsr = */0, /* 250dps. */ /*.reg_accel_fsr = */0x0, /* Accel FSR setting = 2g. */ /*.wait_ms = */200, //200ms stabilization time /*.packet_thresh = */200, /* 200 samples */ /*.min_dps = */20.f, //20 dps for Gyro Criteria C /*.max_dps = */60.f, //Must exceed 60 dps threshold for Gyro Criteria B /*.max_gyro_var = */.5f, //Must exceed +50% variation for Gyro Criteria A /*.min_g = */.225f, //Accel must exceed Min 225 mg for Criteria B /*.max_g = */.675f, //Accel cannot exceed Max 675 mg for Criteria B /*.max_accel_var = */.5f, //Accel must be within 50% variation for Criteria A /*.max_g_offset = */.5f, //500 mg for Accel Criteria C /*.sample_wait_ms = */10 //10ms sample time wait }; static struct gyro_state_s st = { /*.reg = */®, /*.hw = */&hw, {0}, /*.test = */&test }; #endif #define MAX_PACKET_LENGTH (12) #ifdef MPU6500 #define HWST_MAX_PACKET_LENGTH (512) #endif #ifdef AK89xx_SECONDARY static int setup_compass(void); #define MAX_COMPASS_SAMPLE_RATE (100) #endif /** * @brief Enable/disable data ready interrupt. * If the DMP is on, the DMP interrupt is enabled. Otherwise, the data ready * interrupt is used. * @param[in] enable 1 to enable interrupt. * @return 0 if successful. */ static int set_int_enable(unsigned char enable) { unsigned char tmp; if (st.chip_cfg.dmp_on) { if (enable) tmp = BIT_DMP_INT_EN; else tmp = 0x00; if (i2c_write(st.hw->addr, st.reg->int_enable, 1, &tmp)) return -1; st.chip_cfg.int_enable = tmp; } else { if (!st.chip_cfg.sensors) return -1; if (enable && st.chip_cfg.int_enable) return 0; if (enable) tmp = BIT_DATA_RDY_EN; else tmp = 0x00; if (i2c_write(st.hw->addr, st.reg->int_enable, 1, &tmp)) return -1; st.chip_cfg.int_enable = tmp; } return 0; } /** * @brief Register dump for testing. * @return 0 if successful. */ int mpu_reg_dump(void) { unsigned char ii; unsigned char data; for (ii = 0; ii < st.hw->num_reg; ii++) { if (ii == st.reg->fifo_r_w || ii == st.reg->mem_r_w) continue; if (i2c_read(st.hw->addr, ii, 1, &data)) return -1; log_i("%#5x: %#5x\r\n", ii, data); } return 0; } /** * @brief Read from a single register. * NOTE: The memory and FIFO read/write registers cannot be accessed. * @param[in] reg Register address. * @param[out] data Register data. * @return 0 if successful. */ int mpu_read_reg(unsigned char reg, unsigned char *data) { if (reg == st.reg->fifo_r_w || reg == st.reg->mem_r_w) return -1; if (reg >= st.hw->num_reg) return -1; return i2c_read(st.hw->addr, reg, 1, data); } /** * @brief Initialize hardware. * Initial configuration:\n * Gyro FSR: +/- 2000DPS\n * Accel FSR +/- 2G\n * DLPF: 42Hz\n * FIFO rate: 50Hz\n * Clock source: Gyro PLL\n * FIFO: Disabled.\n * Data ready interrupt: Disabled, active low, unlatched. * @param[in] int_param Platform-specific parameters to interrupt API. * @return 0 if successful. */ int mpu_init(struct int_param_s *int_param) { unsigned char data[6]; /* Reset device. */ data[0] = BIT_RESET; if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 1, data)) return -1; delay_ms(100); /* Wake up chip. */ data[0] = 0x00; if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 1, data)) return -1; /* user control */ data[0] = MPU9250_I2C_IF_DIS | MPU9250_I2C_MST_EN; if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, data)) return -1; if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, data)) return -1; st.chip_cfg.accel_half = 0; #ifdef MPU6500 /* MPU6500 shares 4kB of memory between the DMP and the FIFO. Since the * first 3kB are needed by the DMP, we'll use the last 1kB for the FIFO. */ data[0] = BIT_FIFO_SIZE_1024 | 0x8; if (i2c_write(st.hw->addr, st.reg->accel_cfg2, 1, data)) return -1; #endif /* Set to invalid values to ensure no I2C writes are skipped. */ st.chip_cfg.sensors = 0xFF; st.chip_cfg.gyro_fsr = 0xFF; st.chip_cfg.accel_fsr = 0xFF; st.chip_cfg.lpf = 0xFF; st.chip_cfg.sample_rate = 0xFFFF; st.chip_cfg.fifo_enable = 0xFF; st.chip_cfg.bypass_mode = 0xFF; #ifdef AK89xx_SECONDARY st.chip_cfg.compass_sample_rate = 0xFFFF; #endif /* mpu_set_sensors always preserves this setting. */ st.chip_cfg.clk_src = INV_CLK_PLL; /* Handled in next call to mpu_set_bypass. */ st.chip_cfg.active_low_int = 1; st.chip_cfg.latched_int = 0; st.chip_cfg.int_motion_only = 0; st.chip_cfg.lp_accel_mode = 0; memset(&st.chip_cfg.cache, 0, sizeof(st.chip_cfg.cache)); st.chip_cfg.dmp_on = 0; st.chip_cfg.dmp_loaded = 0; st.chip_cfg.dmp_sample_rate = 0; if (mpu_set_gyro_fsr(2000)) return -1; if (mpu_set_accel_fsr(2)) return -1; if (mpu_set_lpf(42)) return -1; // modified by hetao.su //if (mpu_set_sample_rate(50)) if (mpu_set_sample_rate(100)) return -1; if (mpu_configure_fifo(0)) return -1; if (int_param) reg_int_cb(int_param); #ifdef AK89xx_SECONDARY if (setup_compass()) return -1; //modified by hetao.su //if (mpu_set_compass_sample_rate(10)) if (mpu_set_compass_sample_rate(100)) return -1; #else /* Already disabled by setup_compass. */ if (mpu_set_bypass(0)) return -1; #endif mpu_set_sensors(0); return 0; } /** * @brief Enter low-power accel-only mode. * In low-power accel mode, the chip goes to sleep and only wakes up to sample * the accelerometer at one of the following frequencies: * \n MPU6050: 1.25Hz, 5Hz, 20Hz, 40Hz * \n MPU6500: 1.25Hz, 2.5Hz, 5Hz, 10Hz, 20Hz, 40Hz, 80Hz, 160Hz, 320Hz, 640Hz * \n If the requested rate is not one listed above, the device will be set to * the next highest rate. Requesting a rate above the maximum supported * frequency will result in an error. * \n To select a fractional wake-up frequency, round down the value passed to * @e rate. * @param[in] rate Minimum sampling rate, or zero to disable LP * accel mode. * @return 0 if successful. */ int mpu_lp_accel_mode(unsigned char rate) { unsigned char tmp[2]; if (rate > 40) return -1; if (!rate) { mpu_set_int_latched(0); tmp[0] = 0; tmp[1] = BIT_STBY_XYZG; if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 2, tmp)) return -1; st.chip_cfg.lp_accel_mode = 0; return 0; } /* For LP accel, we automatically configure the hardware to produce latched * interrupts. In LP accel mode, the hardware cycles into sleep mode before * it gets a chance to deassert the interrupt pin; therefore, we shift this * responsibility over to the MCU. * * Any register read will clear the interrupt. */ mpu_set_int_latched(1); #if defined MPU6050 tmp[0] = BIT_LPA_CYCLE; if (rate == 1) { tmp[1] = INV_LPA_1_25HZ; mpu_set_lpf(5); } else if (rate <= 5) { tmp[1] = INV_LPA_5HZ; mpu_set_lpf(5); } else if (rate <= 20) { tmp[1] = INV_LPA_20HZ; mpu_set_lpf(10); } else { tmp[1] = INV_LPA_40HZ; mpu_set_lpf(20); } tmp[1] = (tmp[1] << 6) | BIT_STBY_XYZG; if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 2, tmp)) return -1; #elif defined MPU6500 /* Set wake frequency. */ if (rate == 1) tmp[0] = INV_LPA_1_25HZ; else if (rate == 2) tmp[0] = INV_LPA_2_5HZ; else if (rate <= 5) tmp[0] = INV_LPA_5HZ; else if (rate <= 10) tmp[0] = INV_LPA_10HZ; else if (rate <= 20) tmp[0] = INV_LPA_20HZ; else if (rate <= 40) tmp[0] = INV_LPA_40HZ; else if (rate <= 80) tmp[0] = INV_LPA_80HZ; else if (rate <= 160) tmp[0] = INV_LPA_160HZ; else if (rate <= 320) tmp[0] = INV_LPA_320HZ; else tmp[0] = INV_LPA_640HZ; if (i2c_write(st.hw->addr, st.reg->lp_accel_odr, 1, tmp)) return -1; tmp[0] = BIT_LPA_CYCLE; if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 1, tmp)) return -1; #endif st.chip_cfg.sensors = INV_XYZ_ACCEL; st.chip_cfg.clk_src = 0; st.chip_cfg.lp_accel_mode = 1; mpu_configure_fifo(0); return 0; } /** * @brief Read raw gyro data directly from the registers. * @param[out] data Raw data in hardware units. * @param[out] timestamp Timestamp in milliseconds. Null if not needed. * @return 0 if successful. */ int mpu_get_gyro_reg(short *data, unsigned long *timestamp) { unsigned char tmp[6]; if (!(st.chip_cfg.sensors & INV_XYZ_GYRO)) return -1; if (i2c_read(st.hw->addr, st.reg->raw_gyro, 6, tmp)) return -1; data[0] = (tmp[0] << 8) | tmp[1]; data[1] = (tmp[2] << 8) | tmp[3]; data[2] = (tmp[4] << 8) | tmp[5]; if (timestamp) get_ms(timestamp); return 0; } /** * @brief Read raw accel data directly from the registers. * @param[out] data Raw data in hardware units. * @param[out] timestamp Timestamp in milliseconds. Null if not needed. * @return 0 if successful. */ int mpu_get_accel_reg(short *data, unsigned long *timestamp) { unsigned char tmp[6]; if (!(st.chip_cfg.sensors & INV_XYZ_ACCEL)) return -1; if (i2c_read(st.hw->addr, st.reg->raw_accel, 6, tmp)) return -1; data[0] = (tmp[0] << 8) | tmp[1]; data[1] = (tmp[2] << 8) | tmp[3]; data[2] = (tmp[4] << 8) | tmp[5]; if (timestamp) get_ms(timestamp); return 0; } /** * @brief Read temperature data directly from the registers. * @param[out] data Data in q16 format. * @param[out] timestamp Timestamp in milliseconds. Null if not needed. * @return 0 if successful. */ int mpu_get_temperature(long *data, unsigned long *timestamp) { unsigned char tmp[2]; short raw; if (!(st.chip_cfg.sensors)) return -1; if (i2c_read(st.hw->addr, st.reg->temp, 2, tmp)) return -1; raw = (tmp[0] << 8) | tmp[1]; if (timestamp) get_ms(timestamp); data[0] = (long)((21 + ((raw - (float)st.hw->temp_offset) / st.hw->temp_sens)) * 65536L); return 0; } /** * @brief Read biases to the accel bias 6500 registers. * This function reads from the MPU6500 accel offset cancellations registers. * The format are G in +-8G format. The register is initialized with OTP * factory trim values. * @param[in] accel_bias returned structure with the accel bias * @return 0 if successful. */ int mpu_read_6500_accel_bias(long *accel_bias) { unsigned char data[6]; if (i2c_read(st.hw->addr, 0x77, 2, &data[0])) return -1; if (i2c_read(st.hw->addr, 0x7A, 2, &data[2])) return -1; if (i2c_read(st.hw->addr, 0x7D, 2, &data[4])) return -1; accel_bias[0] = ((long)data[0]<<8) | data[1]; accel_bias[1] = ((long)data[2]<<8) | data[3]; accel_bias[2] = ((long)data[4]<<8) | data[5]; return 0; } /** * @brief Read biases to the accel bias 6050 registers. * This function reads from the MPU6050 accel offset cancellations registers. * The format are G in +-8G format. The register is initialized with OTP * factory trim values. * @param[in] accel_bias returned structure with the accel bias * @return 0 if successful. */ int mpu_read_6050_accel_bias(long *accel_bias) { unsigned char data[6]; if (i2c_read(st.hw->addr, 0x06, 2, &data[0])) return -1; if (i2c_read(st.hw->addr, 0x08, 2, &data[2])) return -1; if (i2c_read(st.hw->addr, 0x0A, 2, &data[4])) return -1; accel_bias[0] = ((long)data[0]<<8) | data[1]; accel_bias[1] = ((long)data[2]<<8) | data[3]; accel_bias[2] = ((long)data[4]<<8) | data[5]; return 0; } int mpu_read_6500_gyro_bias(long *gyro_bias) { unsigned char data[6]; if (i2c_read(st.hw->addr, 0x13, 2, &data[0])) return -1; if (i2c_read(st.hw->addr, 0x15, 2, &data[2])) return -1; if (i2c_read(st.hw->addr, 0x17, 2, &data[4])) return -1; gyro_bias[0] = ((long)data[0]<<8) | data[1]; gyro_bias[1] = ((long)data[2]<<8) | data[3]; gyro_bias[2] = ((long)data[4]<<8) | data[5]; return 0; } /** * @brief Push biases to the gyro bias 6500/6050 registers. * This function expects biases relative to the current sensor output, and * these biases will be added to the factory-supplied values. Bias inputs are LSB * in +-1000dps format. * @param[in] gyro_bias New biases. * @return 0 if successful. */ int mpu_set_gyro_bias_reg(long *gyro_bias) { unsigned char data[6] = {0, 0, 0, 0, 0, 0}; int i=0; for(i=0;i<3;i++) { gyro_bias[i]= (-gyro_bias[i]); } data[0] = (gyro_bias[0] >> 8) & 0xff; data[1] = (gyro_bias[0]) & 0xff; data[2] = (gyro_bias[1] >> 8) & 0xff; data[3] = (gyro_bias[1]) & 0xff; data[4] = (gyro_bias[2] >> 8) & 0xff; data[5] = (gyro_bias[2]) & 0xff; if (i2c_write(st.hw->addr, 0x13, 2, &data[0])) return -1; if (i2c_write(st.hw->addr, 0x15, 2, &data[2])) return -1; if (i2c_write(st.hw->addr, 0x17, 2, &data[4])) return -1; return 0; } /** * @brief Push biases to the accel bias 6050 registers. * This function expects biases relative to the current sensor output, and * these biases will be added to the factory-supplied values. Bias inputs are LSB * in +-8G format. * @param[in] accel_bias New biases. * @return 0 if successful. */ int mpu_set_accel_bias_6050_reg(const long *accel_bias) { unsigned char data[6] = {0, 0, 0, 0, 0, 0}; long accel_reg_bias[3] = {0, 0, 0}; long mask = 0x0001; unsigned char mask_bit[3] = {0, 0, 0}; unsigned char i = 0; if(mpu_read_6050_accel_bias(accel_reg_bias)) return -1; //bit 0 of the 2 byte bias is for temp comp //calculations need to compensate for this and not change it for(i=0; i<3; i++) { if(accel_reg_bias[i]&mask) mask_bit[i] = 0x01; } accel_reg_bias[0] -= accel_bias[0]; accel_reg_bias[1] -= accel_bias[1]; accel_reg_bias[2] -= accel_bias[2]; data[0] = (accel_reg_bias[0] >> 8) & 0xff; data[1] = (accel_reg_bias[0]) & 0xff; data[1] = data[1]|mask_bit[0]; data[2] = (accel_reg_bias[1] >> 8) & 0xff; data[3] = (accel_reg_bias[1]) & 0xff; data[3] = data[3]|mask_bit[1]; data[4] = (accel_reg_bias[2] >> 8) & 0xff; data[5] = (accel_reg_bias[2]) & 0xff; data[5] = data[5]|mask_bit[2]; if (i2c_write(st.hw->addr, 0x06, 2, &data[0])) return -1; if (i2c_write(st.hw->addr, 0x08, 2, &data[2])) return -1; if (i2c_write(st.hw->addr, 0x0A, 2, &data[4])) return -1; return 0; } /** * @brief Push biases to the accel bias 6500 registers. * This function expects biases relative to the current sensor output, and * these biases will be added to the factory-supplied values. Bias inputs are LSB * in +-8G format. * @param[in] accel_bias New biases. * @return 0 if successful. */ int mpu_set_accel_bias_6500_reg(const long *accel_bias) { unsigned char data[6] = {0, 0, 0, 0, 0, 0}; long accel_reg_bias[3] = {0, 0, 0}; long mask = 0x0001; unsigned char mask_bit[3] = {0, 0, 0}; unsigned char i = 0; if(mpu_read_6500_accel_bias(accel_reg_bias)) return -1; //bit 0 of the 2 byte bias is for temp comp //calculations need to compensate for this for(i=0; i<3; i++) { if(accel_reg_bias[i]&mask) mask_bit[i] = 0x01; } accel_reg_bias[0] -= accel_bias[0]; accel_reg_bias[1] -= accel_bias[1]; accel_reg_bias[2] -= accel_bias[2]; data[0] = (accel_reg_bias[0] >> 8) & 0xff; data[1] = (accel_reg_bias[0]) & 0xff; data[1] = data[1]|mask_bit[0]; data[2] = (accel_reg_bias[1] >> 8) & 0xff; data[3] = (accel_reg_bias[1]) & 0xff; data[3] = data[3]|mask_bit[1]; data[4] = (accel_reg_bias[2] >> 8) & 0xff; data[5] = (accel_reg_bias[2]) & 0xff; data[5] = data[5]|mask_bit[2]; if (i2c_write(st.hw->addr, 0x77, 2, &data[0])) return -1; if (i2c_write(st.hw->addr, 0x7A, 2, &data[2])) return -1; if (i2c_write(st.hw->addr, 0x7D, 2, &data[4])) return -1; return 0; } /** * @brief Reset FIFO read/write pointers. * @return 0 if successful. */ int mpu_reset_fifo(void) { unsigned char data; if (!(st.chip_cfg.sensors)) return -1; data = 0; if (i2c_write(st.hw->addr, st.reg->int_enable, 1, &data)) return -1; if (i2c_write(st.hw->addr, st.reg->fifo_en, 1, &data)) return -1; if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, &data)) return -1; if (st.chip_cfg.dmp_on) { data = BIT_FIFO_RST | BIT_DMP_RST; if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, &data)) return -1; delay_ms(50); data = BIT_DMP_EN | BIT_FIFO_EN; if (st.chip_cfg.sensors & INV_XYZ_COMPASS) data |= BIT_AUX_IF_EN; if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, &data)) return -1; if (st.chip_cfg.int_enable) data = BIT_DMP_INT_EN; else data = 0; if (i2c_write(st.hw->addr, st.reg->int_enable, 1, &data)) return -1; data = 0; if (i2c_write(st.hw->addr, st.reg->fifo_en, 1, &data)) return -1; } else { data = BIT_FIFO_RST; if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, &data)) return -1; if (st.chip_cfg.bypass_mode || !(st.chip_cfg.sensors & INV_XYZ_COMPASS)) data = BIT_FIFO_EN; else data = BIT_FIFO_EN | BIT_AUX_IF_EN; if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, &data)) return -1; delay_ms(50); if (st.chip_cfg.int_enable) data = BIT_DATA_RDY_EN; else data = 0; if (i2c_write(st.hw->addr, st.reg->int_enable, 1, &data)) return -1; if (i2c_write(st.hw->addr, st.reg->fifo_en, 1, &st.chip_cfg.fifo_enable)) return -1; } return 0; } /** * @brief Get the gyro full-scale range. * @param[out] fsr Current full-scale range. * @return 0 if successful. */ int mpu_get_gyro_fsr(unsigned short *fsr) { switch (st.chip_cfg.gyro_fsr) { case INV_FSR_250DPS: fsr[0] = 250; break; case INV_FSR_500DPS: fsr[0] = 500; break; case INV_FSR_1000DPS: fsr[0] = 1000; break; case INV_FSR_2000DPS: fsr[0] = 2000; break; default: fsr[0] = 0; break; } return 0; } /** * @brief Set the gyro full-scale range. * @param[in] fsr Desired full-scale range. * @return 0 if successful. */ int mpu_set_gyro_fsr(unsigned short fsr) { unsigned char data; if (!(st.chip_cfg.sensors)) return -1; switch (fsr) { case 250: data = INV_FSR_250DPS << 3; break; case 500: data = INV_FSR_500DPS << 3; break; case 1000: data = INV_FSR_1000DPS << 3; break; case 2000: data = INV_FSR_2000DPS << 3; break; default: return -1; } if (st.chip_cfg.gyro_fsr == (data >> 3)) return 0; if (i2c_write(st.hw->addr, st.reg->gyro_cfg, 1, &data)) return -1; st.chip_cfg.gyro_fsr = data >> 3; return 0; } /** * @brief Get the accel full-scale range. * @param[out] fsr Current full-scale range. * @return 0 if successful. */ int mpu_get_accel_fsr(unsigned char *fsr) { switch (st.chip_cfg.accel_fsr) { case INV_FSR_2G: fsr[0] = 2; break; case INV_FSR_4G: fsr[0] = 4; break; case INV_FSR_8G: fsr[0] = 8; break; case INV_FSR_16G: fsr[0] = 16; break; default: return -1; } if (st.chip_cfg.accel_half) fsr[0] <<= 1; return 0; } /** * @brief Set the accel full-scale range. * @param[in] fsr Desired full-scale range. * @return 0 if successful. */ int mpu_set_accel_fsr(unsigned char fsr) { unsigned char data; if (!(st.chip_cfg.sensors)) return -1; switch (fsr) { case 2: data = INV_FSR_2G << 3; break; case 4: data = INV_FSR_4G << 3; break; case 8: data = INV_FSR_8G << 3; break; case 16: data = INV_FSR_16G << 3; break; default: return -1; } if (st.chip_cfg.accel_fsr == (data >> 3)) return 0; if (i2c_write(st.hw->addr, st.reg->accel_cfg, 1, &data)) return -1; st.chip_cfg.accel_fsr = data >> 3; return 0; } /** * @brief Get the current DLPF setting. * @param[out] lpf Current LPF setting. * 0 if successful. */ int mpu_get_lpf(unsigned short *lpf) { switch (st.chip_cfg.lpf) { case INV_FILTER_188HZ: lpf[0] = 188; break; case INV_FILTER_98HZ: lpf[0] = 98; break; case INV_FILTER_42HZ: lpf[0] = 42; break; case INV_FILTER_20HZ: lpf[0] = 20; break; case INV_FILTER_10HZ: lpf[0] = 10; break; case INV_FILTER_5HZ: lpf[0] = 5; break; case INV_FILTER_256HZ_NOLPF2: case INV_FILTER_2100HZ_NOLPF: default: lpf[0] = 0; break; } return 0; } /** * @brief Set digital low pass filter. * The following LPF settings are supported: 188, 98, 42, 20, 10, 5. * @param[in] lpf Desired LPF setting. * @return 0 if successful. */ int mpu_set_lpf(unsigned short lpf) { unsigned char data; if (!(st.chip_cfg.sensors)) return -1; if (lpf >= 188) data = INV_FILTER_188HZ; else if (lpf >= 98) data = INV_FILTER_98HZ; else if (lpf >= 42) data = INV_FILTER_42HZ; else if (lpf >= 20) data = INV_FILTER_20HZ; else if (lpf >= 10) data = INV_FILTER_10HZ; else data = INV_FILTER_5HZ; if (st.chip_cfg.lpf == data) return 0; if (i2c_write(st.hw->addr, st.reg->lpf, 1, &data)) return -1; st.chip_cfg.lpf = data; return 0; } /** * @brief Get sampling rate. * @param[out] rate Current sampling rate (Hz). * @return 0 if successful. */ int mpu_get_sample_rate(unsigned short *rate) { if (st.chip_cfg.dmp_on) return -1; else rate[0] = st.chip_cfg.sample_rate; return 0; } /** * @brief Set sampling rate. * Sampling rate must be between 4Hz and 1kHz. * @param[in] rate Desired sampling rate (Hz). * @return 0 if successful. */ int mpu_set_sample_rate(unsigned short rate) { unsigned char data; if (!(st.chip_cfg.sensors)) return -1; if (st.chip_cfg.dmp_on) return -1; else { if (st.chip_cfg.lp_accel_mode) { if (rate && (rate <= 40)) { /* Just stay in low-power accel mode. */ mpu_lp_accel_mode(rate); return 0; } /* Requested rate exceeds the allowed frequencies in LP accel mode, * switch back to full-power mode. */ mpu_lp_accel_mode(0); } if (rate < 4) rate = 4; else if (rate > 1000) rate = 1000; data = 1000 / rate - 1; if (i2c_write(st.hw->addr, st.reg->rate_div, 1, &data)) return -1; st.chip_cfg.sample_rate = 1000 / (1 + data); #ifdef AK89xx_SECONDARY mpu_set_compass_sample_rate(min(st.chip_cfg.compass_sample_rate, MAX_COMPASS_SAMPLE_RATE)); #endif /* Automatically set LPF to 1/2 sampling rate. */ mpu_set_lpf(st.chip_cfg.sample_rate >> 1); return 0; } } /** * @brief Get compass sampling rate. * @param[out] rate Current compass sampling rate (Hz). * @return 0 if successful. */ int mpu_get_compass_sample_rate(unsigned short *rate) { #ifdef AK89xx_SECONDARY rate[0] = st.chip_cfg.compass_sample_rate; return 0; #else rate[0] = 0; return -1; #endif } /** * @brief Set compass sampling rate. * The compass on the auxiliary I2C bus is read by the MPU hardware at a * maximum of 100Hz. The actual rate can be set to a fraction of the gyro * sampling rate. * * \n WARNING: The new rate may be different than what was requested. Call * mpu_get_compass_sample_rate to check the actual setting. * @param[in] rate Desired compass sampling rate (Hz). * @return 0 if successful. */ int mpu_set_compass_sample_rate(unsigned short rate) { #ifdef AK89xx_SECONDARY unsigned char div; if (!rate || rate > st.chip_cfg.sample_rate || rate > MAX_COMPASS_SAMPLE_RATE) return -1; div = st.chip_cfg.sample_rate / rate - 1; if (i2c_write(st.hw->addr, st.reg->s4_ctrl, 1, &div)) return -1; st.chip_cfg.compass_sample_rate = st.chip_cfg.sample_rate / (div + 1); return 0; #else return -1; #endif } /** * @brief Get gyro sensitivity scale factor. * @param[out] sens Conversion from hardware units to dps. * @return 0 if successful. */ int mpu_get_gyro_sens(float *sens) { switch (st.chip_cfg.gyro_fsr) { case INV_FSR_250DPS: sens[0] = 131.f; break; case INV_FSR_500DPS: sens[0] = 65.5f; break; case INV_FSR_1000DPS: sens[0] = 32.8f; break; case INV_FSR_2000DPS: sens[0] = 16.4f; break; default: return -1; } return 0; } /** * @brief Get accel sensitivity scale factor. * @param[out] sens Conversion from hardware units to g's. * @return 0 if successful. */ int mpu_get_accel_sens(unsigned short *sens) { switch (st.chip_cfg.accel_fsr) { case INV_FSR_2G: sens[0] = 16384; break; case INV_FSR_4G: sens[0] = 8092; break; case INV_FSR_8G: sens[0] = 4096; break; case INV_FSR_16G: sens[0] = 2048; break; default: return -1; } if (st.chip_cfg.accel_half) sens[0] >>= 1; return 0; } /** * @brief Get current FIFO configuration. * @e sensors can contain a combination of the following flags: * \n INV_X_GYRO, INV_Y_GYRO, INV_Z_GYRO * \n INV_XYZ_GYRO * \n INV_XYZ_ACCEL * @param[out] sensors Mask of sensors in FIFO. * @return 0 if successful. */ int mpu_get_fifo_config(unsigned char *sensors) { sensors[0] = st.chip_cfg.fifo_enable; return 0; } /** * @brief Select which sensors are pushed to FIFO. * @e sensors can contain a combination of the following flags: * \n INV_X_GYRO, INV_Y_GYRO, INV_Z_GYRO * \n INV_XYZ_GYRO * \n INV_XYZ_ACCEL * @param[in] sensors Mask of sensors to push to FIFO. * @return 0 if successful. */ int mpu_configure_fifo(unsigned char sensors) { unsigned char prev; int result = 0; /* Compass data isn't going into the FIFO. Stop trying. */ sensors &= ~INV_XYZ_COMPASS; if (st.chip_cfg.dmp_on) return 0; else { if (!(st.chip_cfg.sensors)) return -1; prev = st.chip_cfg.fifo_enable; st.chip_cfg.fifo_enable = sensors & st.chip_cfg.sensors; if (st.chip_cfg.fifo_enable != sensors) /* You're not getting what you asked for. Some sensors are * asleep. */ result = -1; else result = 0; if (sensors || st.chip_cfg.lp_accel_mode) set_int_enable(1); else set_int_enable(0); if (sensors) { if (mpu_reset_fifo()) { st.chip_cfg.fifo_enable = prev; return -1; } } } return result; } /** * @brief Get current power state. * @param[in] power_on 1 if turned on, 0 if suspended. * @return 0 if successful. */ int mpu_get_power_state(unsigned char *power_on) { if (st.chip_cfg.sensors) power_on[0] = 1; else power_on[0] = 0; return 0; } /** * @brief Turn specific sensors on/off. * @e sensors can contain a combination of the following flags: * \n INV_X_GYRO, INV_Y_GYRO, INV_Z_GYRO * \n INV_XYZ_GYRO * \n INV_XYZ_ACCEL * \n INV_XYZ_COMPASS * @param[in] sensors Mask of sensors to wake. * @return 0 if successful. */ int mpu_set_sensors(unsigned char sensors) { unsigned char data; #ifdef AK89xx_SECONDARY unsigned char user_ctrl; #endif if (sensors & INV_XYZ_GYRO) data = INV_CLK_PLL; else if (sensors) data = 0; else data = BIT_SLEEP; if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 1, &data)) { st.chip_cfg.sensors = 0; return -1; } st.chip_cfg.clk_src = data & ~BIT_SLEEP; data = 0; if (!(sensors & INV_X_GYRO)) data |= BIT_STBY_XG; if (!(sensors & INV_Y_GYRO)) data |= BIT_STBY_YG; if (!(sensors & INV_Z_GYRO)) data |= BIT_STBY_ZG; if (!(sensors & INV_XYZ_ACCEL)) data |= BIT_STBY_XYZA; if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_2, 1, &data)) { st.chip_cfg.sensors = 0; return -1; } if (sensors && (sensors != INV_XYZ_ACCEL)) /* Latched interrupts only used in LP accel mode. */ mpu_set_int_latched(0); #ifdef AK89xx_SECONDARY #ifdef AK89xx_BYPASS if (sensors & INV_XYZ_COMPASS) mpu_set_bypass(1); else mpu_set_bypass(0); #else if (i2c_read(st.hw->addr, st.reg->user_ctrl, 1, &user_ctrl)) return -1; /* Handle AKM power management. */ if (sensors & INV_XYZ_COMPASS) { data = AKM_SINGLE_MEASUREMENT; user_ctrl |= BIT_AUX_IF_EN; } else { data = AKM_POWER_DOWN; user_ctrl &= ~BIT_AUX_IF_EN; } if (st.chip_cfg.dmp_on) user_ctrl |= BIT_DMP_EN; else user_ctrl &= ~BIT_DMP_EN; if (i2c_write(st.hw->addr, st.reg->s1_do, 1, &data)) return -1; /* Enable/disable I2C master mode. */ if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, &user_ctrl)) return -1; #endif #endif st.chip_cfg.sensors = sensors; st.chip_cfg.lp_accel_mode = 0; delay_ms(50); return 0; } /** * @brief Read the MPU interrupt status registers. * @param[out] status Mask of interrupt bits. * @return 0 if successful. */ int mpu_get_int_status(short *status) { unsigned char tmp[2]; if (!st.chip_cfg.sensors) return -1; if (i2c_read(st.hw->addr, st.reg->dmp_int_status, 2, tmp)) return -1; status[0] = (tmp[0] << 8) | tmp[1]; return 0; } /** * @brief Get one packet from the FIFO. * If @e sensors does not contain a particular sensor, disregard the data * returned to that pointer. * \n @e sensors can contain a combination of the following flags: * \n INV_X_GYRO, INV_Y_GYRO, INV_Z_GYRO * \n INV_XYZ_GYRO * \n INV_XYZ_ACCEL * \n If the FIFO has no new data, @e sensors will be zero. * \n If the FIFO is disabled, @e sensors will be zero and this function will * return a non-zero error code. * @param[out] gyro Gyro data in hardware units. * @param[out] accel Accel data in hardware units. * @param[out] timestamp Timestamp in milliseconds. * @param[out] sensors Mask of sensors read from FIFO. * @param[out] more Number of remaining packets. * @return 0 if successful. */ int mpu_read_fifo(short *gyro, short *accel, unsigned long *timestamp, unsigned char *sensors, unsigned char *more) { /* Assumes maximum packet size is gyro (6) + accel (6). */ unsigned char data[MAX_PACKET_LENGTH]; unsigned char packet_size = 0; unsigned short fifo_count, index = 0; if (st.chip_cfg.dmp_on) return -1; sensors[0] = 0; if (!st.chip_cfg.sensors) return -1; if (!st.chip_cfg.fifo_enable) return -1; if (st.chip_cfg.fifo_enable & INV_X_GYRO) packet_size += 2; if (st.chip_cfg.fifo_enable & INV_Y_GYRO) packet_size += 2; if (st.chip_cfg.fifo_enable & INV_Z_GYRO) packet_size += 2; if (st.chip_cfg.fifo_enable & INV_XYZ_ACCEL) packet_size += 6; if (i2c_read(st.hw->addr, st.reg->fifo_count_h, 2, data)) return -1; fifo_count = (data[0] << 8) | data[1]; if (fifo_count < packet_size) return 0; // log_i("FIFO count: %hd\n", fifo_count); if (fifo_count > (st.hw->max_fifo >> 1)) { /* FIFO is 50% full, better check overflow bit. */ if (i2c_read(st.hw->addr, st.reg->int_status, 1, data)) return -1; if (data[0] & BIT_FIFO_OVERFLOW) { mpu_reset_fifo(); return -2; } } get_ms((unsigned long*)timestamp); if (i2c_read(st.hw->addr, st.reg->fifo_r_w, packet_size, data)) return -1; more[0] = fifo_count / packet_size - 1; sensors[0] = 0; if ((index != packet_size) && st.chip_cfg.fifo_enable & INV_XYZ_ACCEL) { accel[0] = (data[index+0] << 8) | data[index+1]; accel[1] = (data[index+2] << 8) | data[index+3]; accel[2] = (data[index+4] << 8) | data[index+5]; sensors[0] |= INV_XYZ_ACCEL; index += 6; } if ((index != packet_size) && st.chip_cfg.fifo_enable & INV_X_GYRO) { gyro[0] = (data[index+0] << 8) | data[index+1]; sensors[0] |= INV_X_GYRO; index += 2; } if ((index != packet_size) && st.chip_cfg.fifo_enable & INV_Y_GYRO) { gyro[1] = (data[index+0] << 8) | data[index+1]; sensors[0] |= INV_Y_GYRO; index += 2; } if ((index != packet_size) && st.chip_cfg.fifo_enable & INV_Z_GYRO) { gyro[2] = (data[index+0] << 8) | data[index+1]; sensors[0] |= INV_Z_GYRO; index += 2; } return 0; } /** * @brief Get one unparsed packet from the FIFO. * This function should be used if the packet is to be parsed elsewhere. * @param[in] length Length of one FIFO packet. * @param[in] data FIFO packet. * @param[in] more Number of remaining packets. */ int mpu_read_fifo_stream(unsigned short length, unsigned char *data, unsigned char *more) { unsigned char tmp[2]; unsigned short fifo_count; if (!st.chip_cfg.dmp_on) return -1; if (!st.chip_cfg.sensors) return -1; if (i2c_read(st.hw->addr, st.reg->fifo_count_h, 2, tmp)) return -1; fifo_count = (tmp[0] << 8) | tmp[1]; if (fifo_count < length) { more[0] = 0; return -1; } //modified by hetao.su #if 1 if (fifo_count > (st.hw->max_fifo >> 1)) { /* FIFO is 50% full, better check overflow bit. */ if (i2c_read(st.hw->addr, st.reg->int_status, 1, tmp)) return -1; if (tmp[0] & BIT_FIFO_OVERFLOW) { mpu_reset_fifo(); return -2; } } #endif if (i2c_read(st.hw->addr, st.reg->fifo_r_w, length, data)) return -1; more[0] = fifo_count / length - 1; return 0; } /** * @brief Set device to bypass mode. * @param[in] bypass_on 1 to enable bypass mode. * @return 0 if successful. */ int mpu_set_bypass(unsigned char bypass_on) { unsigned char tmp; if (st.chip_cfg.bypass_mode == bypass_on) return 0; if (bypass_on) { if (i2c_read(st.hw->addr, st.reg->user_ctrl, 1, &tmp)) return -1; tmp &= ~BIT_AUX_IF_EN; if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, &tmp)) return -1; delay_ms(3); tmp = BIT_BYPASS_EN; if (st.chip_cfg.active_low_int) tmp |= BIT_ACTL; if (st.chip_cfg.latched_int) tmp |= BIT_LATCH_EN | BIT_ANY_RD_CLR; if (i2c_write(st.hw->addr, st.reg->int_pin_cfg, 1, &tmp)) return -1; } else { /* Enable I2C master mode if compass is being used. */ if (i2c_read(st.hw->addr, st.reg->user_ctrl, 1, &tmp)) return -1; if (st.chip_cfg.sensors & INV_XYZ_COMPASS) tmp |= BIT_AUX_IF_EN; else tmp &= ~BIT_AUX_IF_EN; if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, &tmp)) return -1; delay_ms(3); if (st.chip_cfg.active_low_int) tmp = BIT_ACTL; else tmp = 0; if (st.chip_cfg.latched_int) tmp |= BIT_LATCH_EN | BIT_ANY_RD_CLR; if (i2c_write(st.hw->addr, st.reg->int_pin_cfg, 1, &tmp)) return -1; } st.chip_cfg.bypass_mode = bypass_on; return 0; } /** * @brief Set interrupt level. * @param[in] active_low 1 for active low, 0 for active high. * @return 0 if successful. */ int mpu_set_int_level(unsigned char active_low) { st.chip_cfg.active_low_int = active_low; return 0; } /** * @brief Enable latched interrupts. * Any MPU register will clear the interrupt. * @param[in] enable 1 to enable, 0 to disable. * @return 0 if successful. */ int mpu_set_int_latched(unsigned char enable) { unsigned char tmp; if (st.chip_cfg.latched_int == enable) return 0; if (enable) tmp = BIT_LATCH_EN | BIT_ANY_RD_CLR; else tmp = 0; if (st.chip_cfg.bypass_mode) tmp |= BIT_BYPASS_EN; if (st.chip_cfg.active_low_int) tmp |= BIT_ACTL; if (i2c_write(st.hw->addr, st.reg->int_pin_cfg, 1, &tmp)) return -1; st.chip_cfg.latched_int = enable; return 0; } #ifdef MPU6050 static int get_accel_prod_shift(float *st_shift) { unsigned char tmp[4], shift_code[3], ii; if (i2c_read(st.hw->addr, 0x0D, 4, tmp)) return 0x07; shift_code[0] = ((tmp[0] & 0xE0) >> 3) | ((tmp[3] & 0x30) >> 4); shift_code[1] = ((tmp[1] & 0xE0) >> 3) | ((tmp[3] & 0x0C) >> 2); shift_code[2] = ((tmp[2] & 0xE0) >> 3) | (tmp[3] & 0x03); for (ii = 0; ii < 3; ii++) { if (!shift_code[ii]) { st_shift[ii] = 0.f; continue; } /* Equivalent to.. * st_shift[ii] = 0.34f * powf(0.92f/0.34f, (shift_code[ii]-1) / 30.f) */ st_shift[ii] = 0.34f; while (--shift_code[ii]) st_shift[ii] *= 1.034f; } return 0; } static int accel_self_test(long *bias_regular, long *bias_st) { int jj, result = 0; float st_shift[3], st_shift_cust, st_shift_var; get_accel_prod_shift(st_shift); for(jj = 0; jj < 3; jj++) { st_shift_cust = labs(bias_regular[jj] - bias_st[jj]) / 65536.f; if (st_shift[jj]) { st_shift_var = st_shift_cust / st_shift[jj] - 1.f; if (fabs(st_shift_var) > test.max_accel_var) result |= 1 << jj; } else if ((st_shift_cust < test.min_g) || (st_shift_cust > test.max_g)) result |= 1 << jj; } return result; } static int gyro_self_test(long *bias_regular, long *bias_st) { int jj, result = 0; unsigned char tmp[3]; float st_shift, st_shift_cust, st_shift_var; if (i2c_read(st.hw->addr, 0x0D, 3, tmp)) return 0x07; tmp[0] &= 0x1F; tmp[1] &= 0x1F; tmp[2] &= 0x1F; for (jj = 0; jj < 3; jj++) { st_shift_cust = labs(bias_regular[jj] - bias_st[jj]) / 65536.f; if (tmp[jj]) { st_shift = 3275.f / test.gyro_sens; while (--tmp[jj]) st_shift *= 1.046f; st_shift_var = st_shift_cust / st_shift - 1.f; if (fabs(st_shift_var) > test.max_gyro_var) result |= 1 << jj; } else if ((st_shift_cust < test.min_dps) || (st_shift_cust > test.max_dps)) result |= 1 << jj; } return result; } #endif #ifdef AK89xx_SECONDARY static int compass_self_test(void) { unsigned char tmp[6]; unsigned char tries = 10; int result = 0x07; short data; mpu_set_bypass(0); tmp[0] = AKM_POWER_DOWN; if (MPU9250_AK8963_SPIx_Writes(st.chip_cfg.compass_addr, AKM_REG_CNTL, 1, tmp)) return 0x07; tmp[0] = AKM_BIT_SELF_TEST; if (MPU9250_AK8963_SPIx_Writes(st.chip_cfg.compass_addr, AKM_REG_ASTC, 1, tmp)) goto AKM_restore; tmp[0] = AKM_MODE_SELF_TEST; if (MPU9250_AK8963_SPIx_Writes(st.chip_cfg.compass_addr, AKM_REG_CNTL, 1, tmp)) goto AKM_restore; do { delay_ms(10); if (MPU9250_AK8963_SPIx_Reads(st.chip_cfg.compass_addr, AKM_REG_ST1, 1, tmp)) goto AKM_restore; if (tmp[0] & AKM_DATA_READY) break; } while (tries--); if (!(tmp[0] & AKM_DATA_READY)) goto AKM_restore; if(MPU9250_AK8963_SPIx_Reads(st.chip_cfg.compass_addr, AKM_REG_HXL, 6, tmp)) goto AKM_restore; result = 0; #if defined MPU9150 data = (short)(tmp[1] << 8) | tmp[0]; if ((data > 100) || (data < -100)) result |= 0x01; data = (short)(tmp[3] << 8) | tmp[2]; if ((data > 100) || (data < -100)) result |= 0x02; data = (short)(tmp[5] << 8) | tmp[4]; if ((data > -300) || (data < -1000)) result |= 0x04; #elif defined MPU9250 data = (short)(tmp[1] << 8) | tmp[0]; if ((data > 200) || (data < -200)) result |= 0x01; data = (short)(tmp[3] << 8) | tmp[2]; if ((data > 200) || (data < -200)) result |= 0x02; data = (short)(tmp[5] << 8) | tmp[4]; if ((data > -800) || (data < -3200)) result |= 0x04; #endif AKM_restore: tmp[0] = 0 | SUPPORTS_AK89xx_HIGH_SENS; MPU9250_AK8963_SPIx_Writes(st.chip_cfg.compass_addr, AKM_REG_ASTC, 1, tmp); tmp[0] = SUPPORTS_AK89xx_HIGH_SENS; MPU9250_AK8963_SPIx_Writes(st.chip_cfg.compass_addr, AKM_REG_CNTL, 1, tmp); mpu_set_bypass(0); return result; } #endif static int get_st_biases(long *gyro, long *accel, unsigned char hw_test) { unsigned char data[MAX_PACKET_LENGTH]; unsigned char packet_count, ii; unsigned short fifo_count; data[0] = 0x01; data[1] = 0; if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 2, data)) return -1; delay_ms(200); data[0] = 0; if (i2c_write(st.hw->addr, st.reg->int_enable, 1, data)) return -1; if (i2c_write(st.hw->addr, st.reg->fifo_en, 1, data)) return -1; if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 1, data)) return -1; if (i2c_write(st.hw->addr, st.reg->i2c_mst, 1, data)) return -1; if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, data)) return -1; data[0] = BIT_FIFO_RST | BIT_DMP_RST; if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, data)) return -1; delay_ms(15); data[0] = st.test->reg_lpf; if (i2c_write(st.hw->addr, st.reg->lpf, 1, data)) return -1; data[0] = st.test->reg_rate_div; if (i2c_write(st.hw->addr, st.reg->rate_div, 1, data)) return -1; if (hw_test) data[0] = st.test->reg_gyro_fsr | 0xE0; else data[0] = st.test->reg_gyro_fsr; if (i2c_write(st.hw->addr, st.reg->gyro_cfg, 1, data)) return -1; if (hw_test) data[0] = st.test->reg_accel_fsr | 0xE0; else data[0] = test.reg_accel_fsr; if (i2c_write(st.hw->addr, st.reg->accel_cfg, 1, data)) return -1; if (hw_test) delay_ms(200); /* Fill FIFO for test.wait_ms milliseconds. */ data[0] = BIT_FIFO_EN; if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, data)) return -1; data[0] = INV_XYZ_GYRO | INV_XYZ_ACCEL; if (i2c_write(st.hw->addr, st.reg->fifo_en, 1, data)) return -1; delay_ms(test.wait_ms); data[0] = 0; if (i2c_write(st.hw->addr, st.reg->fifo_en, 1, data)) return -1; if (i2c_read(st.hw->addr, st.reg->fifo_count_h, 2, data)) return -1; fifo_count = (data[0] << 8) | data[1]; packet_count = fifo_count / MAX_PACKET_LENGTH; gyro[0] = gyro[1] = gyro[2] = 0; accel[0] = accel[1] = accel[2] = 0; for (ii = 0; ii < packet_count; ii++) { short accel_cur[3], gyro_cur[3]; if (i2c_read(st.hw->addr, st.reg->fifo_r_w, MAX_PACKET_LENGTH, data)) return -1; accel_cur[0] = ((short)data[0] << 8) | data[1]; accel_cur[1] = ((short)data[2] << 8) | data[3]; accel_cur[2] = ((short)data[4] << 8) | data[5]; accel[0] += (long)accel_cur[0]; accel[1] += (long)accel_cur[1]; accel[2] += (long)accel_cur[2]; gyro_cur[0] = (((short)data[6] << 8) | data[7]); gyro_cur[1] = (((short)data[8] << 8) | data[9]); gyro_cur[2] = (((short)data[10] << 8) | data[11]); gyro[0] += (long)gyro_cur[0]; gyro[1] += (long)gyro_cur[1]; gyro[2] += (long)gyro_cur[2]; } #ifdef EMPL_NO_64BIT gyro[0] = (long)(((float)gyro[0]*65536.f) / test.gyro_sens / packet_count); gyro[1] = (long)(((float)gyro[1]*65536.f) / test.gyro_sens / packet_count); gyro[2] = (long)(((float)gyro[2]*65536.f) / test.gyro_sens / packet_count); if (has_accel) { accel[0] = (long)(((float)accel[0]*65536.f) / test.accel_sens / packet_count); accel[1] = (long)(((float)accel[1]*65536.f) / test.accel_sens / packet_count); accel[2] = (long)(((float)accel[2]*65536.f) / test.accel_sens / packet_count); /* Don't remove gravity! */ accel[2] -= 65536L; } #else gyro[0] = (long)(((long long)gyro[0]<<16) / test.gyro_sens / packet_count); gyro[1] = (long)(((long long)gyro[1]<<16) / test.gyro_sens / packet_count); gyro[2] = (long)(((long long)gyro[2]<<16) / test.gyro_sens / packet_count); accel[0] = (long)(((long long)accel[0]<<16) / test.accel_sens / packet_count); accel[1] = (long)(((long long)accel[1]<<16) / test.accel_sens / packet_count); accel[2] = (long)(((long long)accel[2]<<16) / test.accel_sens / packet_count); /* Don't remove gravity! */ if (accel[2] > 0L) accel[2] -= 65536L; else accel[2] += 65536L; #endif return 0; } #ifdef MPU6500 #define REG_6500_XG_ST_DATA 0x0 #define REG_6500_XA_ST_DATA 0xD static const unsigned short mpu_6500_st_tb[256] = { 2620,2646,2672,2699,2726,2753,2781,2808, //7 2837,2865,2894,2923,2952,2981,3011,3041, //15 3072,3102,3133,3165,3196,3228,3261,3293, //23 3326,3359,3393,3427,3461,3496,3531,3566, //31 3602,3638,3674,3711,3748,3786,3823,3862, //39 3900,3939,3979,4019,4059,4099,4140,4182, //47 4224,4266,4308,4352,4395,4439,4483,4528, //55 4574,4619,4665,4712,4759,4807,4855,4903, //63 4953,5002,5052,5103,5154,5205,5257,5310, //71 5363,5417,5471,5525,5581,5636,5693,5750, //79 5807,5865,5924,5983,6043,6104,6165,6226, //87 6289,6351,6415,6479,6544,6609,6675,6742, //95 6810,6878,6946,7016,7086,7157,7229,7301, //103 7374,7448,7522,7597,7673,7750,7828,7906, //111 7985,8065,8145,8227,8309,8392,8476,8561, //119 8647,8733,8820,8909,8998,9088,9178,9270, 9363,9457,9551,9647,9743,9841,9939,10038, 10139,10240,10343,10446,10550,10656,10763,10870, 10979,11089,11200,11312,11425,11539,11654,11771, 11889,12008,12128,12249,12371,12495,12620,12746, 12874,13002,13132,13264,13396,13530,13666,13802, 13940,14080,14221,14363,14506,14652,14798,14946, 15096,15247,15399,15553,15709,15866,16024,16184, 16346,16510,16675,16842,17010,17180,17352,17526, 17701,17878,18057,18237,18420,18604,18790,18978, 19167,19359,19553,19748,19946,20145,20347,20550, 20756,20963,21173,21385,21598,21814,22033,22253, 22475,22700,22927,23156,23388,23622,23858,24097, 24338,24581,24827,25075,25326,25579,25835,26093, 26354,26618,26884,27153,27424,27699,27976,28255, 28538,28823,29112,29403,29697,29994,30294,30597, 30903,31212,31524,31839,32157,32479,32804,33132 }; static int accel_6500_self_test(long *bias_regular, long *bias_st, int debug) { int i, result = 0, otp_value_zero = 0; float accel_st_al_min, accel_st_al_max; float st_shift_cust[3], st_shift_ratio[3], ct_shift_prod[3], accel_offset_max; unsigned char regs[3]; if (i2c_read(st.hw->addr, REG_6500_XA_ST_DATA, 3, regs)) { if(debug) log_i("Reading OTP Register Error.\n"); return 0x07; } if(debug) log_i("Accel OTP:%d, %d, %d\n", regs[0], regs[1], regs[2]); for (i = 0; i < 3; i++) { if (regs[i] != 0) { ct_shift_prod[i] = mpu_6500_st_tb[regs[i] - 1]; ct_shift_prod[i] *= 65536.f; ct_shift_prod[i] /= test.accel_sens; } else { ct_shift_prod[i] = 0; otp_value_zero = 1; } } if(otp_value_zero == 0) { if(debug) log_i("ACCEL:CRITERIA A\n"); for (i = 0; i < 3; i++) { st_shift_cust[i] = bias_st[i] - bias_regular[i]; if(debug) { log_i("Bias_Shift=%7.4f, Bias_Reg=%7.4f, Bias_HWST=%7.4f\r\n", st_shift_cust[i]/1.f, bias_regular[i]/1.f, bias_st[i]/1.f); log_i("OTP value: %7.4f\r\n", ct_shift_prod[i]/1.f); } st_shift_ratio[i] = st_shift_cust[i] / ct_shift_prod[i] - 1.f; if(debug) log_i("ratio=%7.4f, threshold=%7.4f\r\n", st_shift_ratio[i]/1.f, test.max_accel_var/1.f); if (fabs(st_shift_ratio[i]) > test.max_accel_var) { if(debug) log_i("ACCEL Fail Axis = %d\n", i); result |= 1 << i; //Error condition } } } else { /* Self Test Pass/Fail Criteria B */ accel_st_al_min = test.min_g * 65536.f; accel_st_al_max = test.max_g * 65536.f; if(debug) { log_i("ACCEL:CRITERIA B\r\n"); log_i("Min MG: %7.4f\r\n", accel_st_al_min/1.f); log_i("Max MG: %7.4f\r\n", accel_st_al_max/1.f); } for (i = 0; i < 3; i++) { st_shift_cust[i] = bias_st[i] - bias_regular[i]; if(debug) log_i("Bias_shift=%7.4f, st=%7.4f, reg=%7.4f\n", st_shift_cust[i]/1.f, bias_st[i]/1.f, bias_regular[i]/1.f); if(st_shift_cust[i] < accel_st_al_min || st_shift_cust[i] > accel_st_al_max) { if(debug) log_i("Accel FAIL axis:%d <= 225mg or >= 675mg\n", i); result |= 1 << i; //Error condition } } } if(result == 0) { /* Self Test Pass/Fail Criteria C */ accel_offset_max = test.max_g_offset * 65536.f; if(debug) log_i("Accel:CRITERIA C: bias less than %7.4f\n", accel_offset_max/1.f); for (i = 0; i < 3; i++) { if(fabs(bias_regular[i]) > accel_offset_max) { if(debug) log_i("FAILED: Accel axis:%d = %d > 500mg\n", i, bias_regular[i]); result |= 1 << i; //Error condition } } } return result; } static int gyro_6500_self_test(long *bias_regular, long *bias_st, int debug) { int i, result = 0, otp_value_zero = 0; float gyro_st_al_max; float st_shift_cust[3], st_shift_ratio[3], ct_shift_prod[3], gyro_offset_max; unsigned char regs[3]; if (i2c_read(st.hw->addr, REG_6500_XG_ST_DATA, 3, regs)) { if(debug) log_i("Reading OTP Register Error.\n"); return 0x07; } if(debug) log_i("Gyro OTP:%d, %d, %d\r\n", regs[0], regs[1], regs[2]); for (i = 0; i < 3; i++) { if (regs[i] != 0) { ct_shift_prod[i] = mpu_6500_st_tb[regs[i] - 1]; ct_shift_prod[i] *= 65536.f; ct_shift_prod[i] /= test.gyro_sens; } else { ct_shift_prod[i] = 0; otp_value_zero = 1; } } if(otp_value_zero == 0) { if(debug) log_i("GYRO:CRITERIA A\n"); /* Self Test Pass/Fail Criteria A */ for (i = 0; i < 3; i++) { st_shift_cust[i] = bias_st[i] - bias_regular[i]; if(debug) { log_i("Bias_Shift=%7.4f, Bias_Reg=%7.4f, Bias_HWST=%7.4f\r\n", st_shift_cust[i]/1.f, bias_regular[i]/1.f, bias_st[i]/1.f); log_i("OTP value: %7.4f\r\n", ct_shift_prod[i]/1.f); } st_shift_ratio[i] = st_shift_cust[i] / ct_shift_prod[i]; if(debug) log_i("ratio=%7.4f, threshold=%7.4f\r\n", st_shift_ratio[i]/1.f, test.max_gyro_var/1.f); if (fabs(st_shift_ratio[i]) < test.max_gyro_var) { if(debug) log_i("Gyro Fail Axis = %d\n", i); result |= 1 << i; //Error condition } } } else { /* Self Test Pass/Fail Criteria B */ gyro_st_al_max = test.max_dps * 65536.f; if(debug) { log_i("GYRO:CRITERIA B\r\n"); log_i("Max DPS: %7.4f\r\n", gyro_st_al_max/1.f); } for (i = 0; i < 3; i++) { st_shift_cust[i] = bias_st[i] - bias_regular[i]; if(debug) log_i("Bias_shift=%7.4f, st=%7.4f, reg=%7.4f\n", st_shift_cust[i]/1.f, bias_st[i]/1.f, bias_regular[i]/1.f); if(st_shift_cust[i] < gyro_st_al_max) { if(debug) log_i("GYRO FAIL axis:%d greater than 60dps\n", i); result |= 1 << i; //Error condition } } } if(result == 0) { /* Self Test Pass/Fail Criteria C */ gyro_offset_max = test.min_dps * 65536.f; if(debug) log_i("Gyro:CRITERIA C: bias less than %7.4f\n", gyro_offset_max/1.f); for (i = 0; i < 3; i++) { if(fabs(bias_regular[i]) > gyro_offset_max) { if(debug) log_i("FAILED: Gyro axis:%d = %d > 20dps\n", i, bias_regular[i]); result |= 1 << i; //Error condition } } } return result; } static int get_st_6500_biases(long *gyro, long *accel, unsigned char hw_test, int debug) { unsigned char data[HWST_MAX_PACKET_LENGTH]; unsigned char packet_count, ii; unsigned short fifo_count; int s = 0, read_size = 0, ind; data[0] = 0x01; data[1] = 0; if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 2, data)) return -1; delay_ms(200); data[0] = 0; if (i2c_write(st.hw->addr, st.reg->int_enable, 1, data)) return -1; if (i2c_write(st.hw->addr, st.reg->fifo_en, 1, data)) return -1; if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 1, data)) return -1; if (i2c_write(st.hw->addr, st.reg->i2c_mst, 1, data)) return -1; if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, data)) return -1; data[0] = BIT_FIFO_RST | BIT_DMP_RST; if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, data)) return -1; delay_ms(15); data[0] = st.test->reg_lpf; if (i2c_write(st.hw->addr, st.reg->lpf, 1, data)) return -1; data[0] = st.test->reg_rate_div; if (i2c_write(st.hw->addr, st.reg->rate_div, 1, data)) return -1; if (hw_test) data[0] = st.test->reg_gyro_fsr | 0xE0; else data[0] = st.test->reg_gyro_fsr; if (i2c_write(st.hw->addr, st.reg->gyro_cfg, 1, data)) return -1; if (hw_test) data[0] = st.test->reg_accel_fsr | 0xE0; else data[0] = test.reg_accel_fsr; if (i2c_write(st.hw->addr, st.reg->accel_cfg, 1, data)) return -1; delay_ms(test.wait_ms); //wait 200ms for sensors to stabilize /* Enable FIFO */ data[0] = BIT_FIFO_EN; if (i2c_write(st.hw->addr, st.reg->user_ctrl, 1, data)) return -1; data[0] = INV_XYZ_GYRO | INV_XYZ_ACCEL; if (i2c_write(st.hw->addr, st.reg->fifo_en, 1, data)) return -1; //initialize the bias return values gyro[0] = gyro[1] = gyro[2] = 0; accel[0] = accel[1] = accel[2] = 0; if(debug) log_i("Starting Bias Loop Reads\n"); //start reading samples while (s < test.packet_thresh) { delay_ms(test.sample_wait_ms); //wait 10ms to fill FIFO if (i2c_read(st.hw->addr, st.reg->fifo_count_h, 2, data)) return -1; fifo_count = (data[0] << 8) | data[1]; packet_count = fifo_count / MAX_PACKET_LENGTH; if ((test.packet_thresh - s) < packet_count) packet_count = test.packet_thresh - s; read_size = packet_count * MAX_PACKET_LENGTH; //burst read from FIFO if (i2c_read(st.hw->addr, st.reg->fifo_r_w, read_size, data)) return -1; ind = 0; for (ii = 0; ii < packet_count; ii++) { short accel_cur[3], gyro_cur[3]; accel_cur[0] = ((short)data[ind + 0] << 8) | data[ind + 1]; accel_cur[1] = ((short)data[ind + 2] << 8) | data[ind + 3]; accel_cur[2] = ((short)data[ind + 4] << 8) | data[ind + 5]; accel[0] += (long)accel_cur[0]; accel[1] += (long)accel_cur[1]; accel[2] += (long)accel_cur[2]; gyro_cur[0] = (((short)data[ind + 6] << 8) | data[ind + 7]); gyro_cur[1] = (((short)data[ind + 8] << 8) | data[ind + 9]); gyro_cur[2] = (((short)data[ind + 10] << 8) | data[ind + 11]); gyro[0] += (long)gyro_cur[0]; gyro[1] += (long)gyro_cur[1]; gyro[2] += (long)gyro_cur[2]; ind += MAX_PACKET_LENGTH; } s += packet_count; } if(debug) log_i("Samples: %d\n", s); //stop FIFO data[0] = 0; if (i2c_write(st.hw->addr, st.reg->fifo_en, 1, data)) return -1; gyro[0] = (long)(((long long)gyro[0]<<16) / test.gyro_sens / s); gyro[1] = (long)(((long long)gyro[1]<<16) / test.gyro_sens / s); gyro[2] = (long)(((long long)gyro[2]<<16) / test.gyro_sens / s); accel[0] = (long)(((long long)accel[0]<<16) / test.accel_sens / s); accel[1] = (long)(((long long)accel[1]<<16) / test.accel_sens / s); accel[2] = (long)(((long long)accel[2]<<16) / test.accel_sens / s); /* remove gravity from bias calculation */ if (accel[2] > 0L) accel[2] -= 65536L; else accel[2] += 65536L; if(debug) { log_i("Accel offset data HWST bit=%d: %7.4f %7.4f %7.4f\r\n", hw_test, accel[0]/65536.f, accel[1]/65536.f, accel[2]/65536.f); log_i("Gyro offset data HWST bit=%d: %7.4f %7.4f %7.4f\r\n", hw_test, gyro[0]/65536.f, gyro[1]/65536.f, gyro[2]/65536.f); } return 0; } /** * @brief Trigger gyro/accel/compass self-test for MPU6500/MPU9250 * On success/error, the self-test returns a mask representing the sensor(s) * that failed. For each bit, a one (1) represents a "pass" case; conversely, * a zero (0) indicates a failure. * * \n The mask is defined as follows: * \n Bit 0: Gyro. * \n Bit 1: Accel. * \n Bit 2: Compass. * * @param[out] gyro Gyro biases in q16 format. * @param[out] accel Accel biases (if applicable) in q16 format. * @param[in] debug Debug flag used to print out more detailed logs. Must first set up logging in Motion Driver. * @return Result mask (see above). */ int mpu_run_6500_self_test(long *gyro, long *accel, unsigned char debug) { const unsigned char tries = 2; long gyro_st[3], accel_st[3]; unsigned char accel_result, gyro_result; #ifdef AK89xx_SECONDARY unsigned char compass_result; #endif int ii; int result; unsigned char accel_fsr, fifo_sensors, sensors_on; unsigned short gyro_fsr, sample_rate, lpf; unsigned char dmp_was_on; if(debug) log_i("Starting MPU6500 HWST!\r\n"); if (st.chip_cfg.dmp_on) { mpu_set_dmp_state(0); dmp_was_on = 1; } else dmp_was_on = 0; /* Get initial settings. */ mpu_get_gyro_fsr(&gyro_fsr); mpu_get_accel_fsr(&accel_fsr); mpu_get_lpf(&lpf); mpu_get_sample_rate(&sample_rate); sensors_on = st.chip_cfg.sensors; mpu_get_fifo_config(&fifo_sensors); if(debug) log_i("Retrieving Biases\r\n"); for (ii = 0; ii < tries; ii++) if (!get_st_6500_biases(gyro, accel, 0, debug)) break; if (ii == tries) { /* If we reach this point, we most likely encountered an I2C error. * We'll just report an error for all three sensors. */ if(debug) log_i("Retrieving Biases Error - possible I2C error\n"); result = 0; goto restore; } if(debug) log_i("Retrieving ST Biases\n"); for (ii = 0; ii < tries; ii++) if (!get_st_6500_biases(gyro_st, accel_st, 1, debug)) break; if (ii == tries) { if(debug) log_i("Retrieving ST Biases Error - possible I2C error\n"); /* Again, probably an I2C error. */ result = 0; goto restore; } accel_result = accel_6500_self_test(accel, accel_st, debug); if(debug) log_i("Accel Self Test Results: %d\n", accel_result); gyro_result = gyro_6500_self_test(gyro, gyro_st, debug); if(debug) log_i("Gyro Self Test Results: %d\n", gyro_result); result = 0; if (!gyro_result) result |= 0x01; if (!accel_result) result |= 0x02; #ifdef AK89xx_SECONDARY compass_result = compass_self_test(); if(debug) log_i("Compass Self Test Results: %d\n", compass_result); if (!compass_result) result |= 0x04; #else result |= 0x04; #endif restore: if(debug) log_i("Exiting HWST\n"); /* Set to invalid values to ensure no I2C writes are skipped. */ st.chip_cfg.gyro_fsr = 0xFF; st.chip_cfg.accel_fsr = 0xFF; st.chip_cfg.lpf = 0xFF; st.chip_cfg.sample_rate = 0xFFFF; st.chip_cfg.sensors = 0xFF; st.chip_cfg.fifo_enable = 0xFF; st.chip_cfg.clk_src = INV_CLK_PLL; mpu_set_gyro_fsr(gyro_fsr); mpu_set_accel_fsr(accel_fsr); mpu_set_lpf(lpf); mpu_set_sample_rate(sample_rate); mpu_set_sensors(sensors_on); mpu_configure_fifo(fifo_sensors); if (dmp_was_on) mpu_set_dmp_state(1); return result; } #endif /* * \n This function must be called with the device either face-up or face-down * (z-axis is parallel to gravity). * @param[out] gyro Gyro biases in q16 format. * @param[out] accel Accel biases (if applicable) in q16 format. * @return Result mask (see above). */ int mpu_run_self_test(long *gyro, long *accel) { #ifdef MPU6050 const unsigned char tries = 2; long gyro_st[3], accel_st[3]; unsigned char accel_result, gyro_result; #ifdef AK89xx_SECONDARY unsigned char compass_result; #endif int ii; #endif int result; unsigned char accel_fsr, fifo_sensors, sensors_on; unsigned short gyro_fsr, sample_rate, lpf; unsigned char dmp_was_on; if (st.chip_cfg.dmp_on) { mpu_set_dmp_state(0); dmp_was_on = 1; } else dmp_was_on = 0; /* Get initial settings. */ mpu_get_gyro_fsr(&gyro_fsr); mpu_get_accel_fsr(&accel_fsr); mpu_get_lpf(&lpf); mpu_get_sample_rate(&sample_rate); sensors_on = st.chip_cfg.sensors; mpu_get_fifo_config(&fifo_sensors); /* For older chips, the self-test will be different. */ #if defined MPU6050 for (ii = 0; ii < tries; ii++) if (!get_st_biases(gyro, accel, 0)) break; if (ii == tries) { /* If we reach this point, we most likely encountered an I2C error. * We'll just report an error for all three sensors. */ result = 0; goto restore; } for (ii = 0; ii < tries; ii++) if (!get_st_biases(gyro_st, accel_st, 1)) break; if (ii == tries) { /* Again, probably an I2C error. */ result = 0; goto restore; } accel_result = accel_self_test(accel, accel_st); gyro_result = gyro_self_test(gyro, gyro_st); result = 0; if (!gyro_result) result |= 0x01; if (!accel_result) result |= 0x02; #ifdef AK89xx_SECONDARY compass_result = compass_self_test(); if (!compass_result) result |= 0x04; #else result |= 0x04; #endif restore: #elif defined MPU6500 /* For now, this function will return a "pass" result for all three sensors * for compatibility with current test applications. */ get_st_biases(gyro, accel, 0); result = 0x7; #endif /* Set to invalid values to ensure no I2C writes are skipped. */ st.chip_cfg.gyro_fsr = 0xFF; st.chip_cfg.accel_fsr = 0xFF; st.chip_cfg.lpf = 0xFF; st.chip_cfg.sample_rate = 0xFFFF; st.chip_cfg.sensors = 0xFF; st.chip_cfg.fifo_enable = 0xFF; st.chip_cfg.clk_src = INV_CLK_PLL; mpu_set_gyro_fsr(gyro_fsr); mpu_set_accel_fsr(accel_fsr); mpu_set_lpf(lpf); mpu_set_sample_rate(sample_rate); mpu_set_sensors(sensors_on); mpu_configure_fifo(fifo_sensors); if (dmp_was_on) mpu_set_dmp_state(1); return result; } /** * @brief Write to the DMP memory. * This function prevents I2C writes past the bank boundaries. The DMP memory * is only accessible when the chip is awake. * @param[in] mem_addr Memory location (bank << 8 | start address) * @param[in] length Number of bytes to write. * @param[in] data Bytes to write to memory. * @return 0 if successful. */ int mpu_write_mem(unsigned short mem_addr, unsigned short length, unsigned char *data) { unsigned char tmp[2]; if (!data) return -1; if (!st.chip_cfg.sensors) return -1; tmp[0] = (unsigned char)(mem_addr >> 8); tmp[1] = (unsigned char)(mem_addr & 0xFF); /* Check bank boundaries. */ if (tmp[1] + length > st.hw->bank_size) return -1; if (i2c_write(st.hw->addr, st.reg->bank_sel, 2, tmp)) return -1; if (i2c_write(st.hw->addr, st.reg->mem_r_w, length, data)) return -1; return 0; } /** * @brief Read from the DMP memory. * This function prevents I2C reads past the bank boundaries. The DMP memory * is only accessible when the chip is awake. * @param[in] mem_addr Memory location (bank << 8 | start address) * @param[in] length Number of bytes to read. * @param[out] data Bytes read from memory. * @return 0 if successful. */ int mpu_read_mem(unsigned short mem_addr, unsigned short length, unsigned char *data) { unsigned char tmp[2]; if (!data) return -1; if (!st.chip_cfg.sensors) return -1; tmp[0] = (unsigned char)(mem_addr >> 8); tmp[1] = (unsigned char)(mem_addr & 0xFF); /* Check bank boundaries. */ if (tmp[1] + length > st.hw->bank_size) return -1; if (i2c_write(st.hw->addr, st.reg->bank_sel, 2, tmp)) return -1; if (i2c_read(st.hw->addr, st.reg->mem_r_w, length, data)) return -1; return 0; } /** * @brief Load and verify DMP image. * @param[in] length Length of DMP image. * @param[in] firmware DMP code. * @param[in] start_addr Starting address of DMP code memory. * @param[in] sample_rate Fixed sampling rate used when DMP is enabled. * @return 0 if successful. */ int mpu_load_firmware(unsigned short length, const unsigned char *firmware, unsigned short start_addr, unsigned short sample_rate) { unsigned short ii; unsigned short this_write; /* Must divide evenly into st.hw->bank_size to avoid bank crossings. */ #define LOAD_CHUNK (16) unsigned char cur[LOAD_CHUNK], tmp[2]; if (st.chip_cfg.dmp_loaded) /* DMP should only be loaded once. */ return -1; if (!firmware) return -1; for (ii = 0; ii < length; ii += this_write) { this_write = min(LOAD_CHUNK, length - ii); if (mpu_write_mem(ii, this_write, (unsigned char*)&firmware[ii])) return -1; if (mpu_read_mem(ii, this_write, cur)) return -1; if (memcmp(firmware+ii, cur, this_write)) return -2; } /* Set program start address. */ tmp[0] = start_addr >> 8; tmp[1] = start_addr & 0xFF; if (i2c_write(st.hw->addr, st.reg->prgm_start_h, 2, tmp)) return -1; st.chip_cfg.dmp_loaded = 1; st.chip_cfg.dmp_sample_rate = sample_rate; return 0; } /** * @brief Enable/disable DMP support. * @param[in] enable 1 to turn on the DMP. * @return 0 if successful. */ int mpu_set_dmp_state(unsigned char enable) { unsigned char tmp; if (st.chip_cfg.dmp_on == enable) return 0; if (enable) { if (!st.chip_cfg.dmp_loaded) return -1; /* Disable data ready interrupt. */ set_int_enable(0); /* Disable bypass mode. */ mpu_set_bypass(0); /* Keep constant sample rate, FIFO rate controlled by DMP. */ mpu_set_sample_rate(st.chip_cfg.dmp_sample_rate); /* Remove FIFO elements. */ tmp = 0; i2c_write(st.hw->addr, 0x23, 1, &tmp); st.chip_cfg.dmp_on = 1; /* Enable DMP interrupt. */ set_int_enable(1); mpu_reset_fifo(); } else { /* Disable DMP interrupt. */ set_int_enable(0); /* Restore FIFO settings. */ tmp = st.chip_cfg.fifo_enable; i2c_write(st.hw->addr, 0x23, 1, &tmp); st.chip_cfg.dmp_on = 0; mpu_reset_fifo(); } return 0; } /** * @brief Get DMP state. * @param[out] enabled 1 if enabled. * @return 0 if successful. */ int mpu_get_dmp_state(unsigned char *enabled) { enabled[0] = st.chip_cfg.dmp_on; return 0; } #ifdef AK89xx_SECONDARY /* This initialization is similar to the one in ak8975.c. */ static int setup_compass(void) { unsigned char data[4], akm_addr; int result; mpu_set_bypass(0); /* Find compass. Possible addresses range from 0x0C to 0x0F. */ for (akm_addr = 0x0C; akm_addr <= 0x0F; akm_addr++) { //result = i2c_read(akm_addr, AKM_REG_WHOAMI, 1, data); result = MPU9250_AK8963_SPIx_Reads(akm_addr, AKM_REG_WHOAMI, 1, data); if (!result && (data[0] == AKM_WHOAMI)) break; } if (akm_addr > 0x0F) { /* TODO: Handle this case in all compass-related functions. */ log_e("Compass not found.\n"); return -1; } st.chip_cfg.compass_addr = akm_addr; data[0] = AKM_POWER_DOWN; if (MPU9250_AK8963_SPIx_Writes(st.chip_cfg.compass_addr, AKM_REG_CNTL, 1, data)) return -1; delay_ms(1); data[0] = AKM_FUSE_ROM_ACCESS; if (MPU9250_AK8963_SPIx_Writes(st.chip_cfg.compass_addr, AKM_REG_CNTL, 1, data)) return -1; delay_ms(1); /* Get sensitivity adjustment data from fuse ROM. */ if (MPU9250_AK8963_SPIx_Reads(st.chip_cfg.compass_addr, AKM_REG_ASAX, 3, data)) return -1; //bug?why plus 128? but must sub 128 from datasheet st.chip_cfg.mag_sens_adj[0] = (long)data[0] + 128; st.chip_cfg.mag_sens_adj[1] = (long)data[1] + 128; st.chip_cfg.mag_sens_adj[2] = (long)data[2] + 128; data[0] = AKM_POWER_DOWN; if (MPU9250_AK8963_SPIx_Writes(st.chip_cfg.compass_addr, AKM_REG_CNTL, 1, data)) return -1; delay_ms(1); /* Set up master mode, master clock, and ES bit. */ //modified by hetao.su //data[0] = 0x40; data[0] = 0x4D; if (i2c_write(st.hw->addr, st.reg->i2c_mst, 1, data)) return -1; /* Slave 0 reads from AKM data registers. */ data[0] = BIT_I2C_READ | st.chip_cfg.compass_addr; if (i2c_write(st.hw->addr, st.reg->s0_addr, 1, data)) return -1; /* Compass reads start at this register. */ data[0] = AKM_REG_ST1; if (i2c_write(st.hw->addr, st.reg->s0_reg, 1, data)) return -1; /* Enable slave 0, 8-byte reads. */ data[0] = BIT_SLAVE_EN | 8; if (i2c_write(st.hw->addr, st.reg->s0_ctrl, 1, data)) return -1; /* Slave 1 changes AKM measurement mode. */ data[0] = st.chip_cfg.compass_addr; if (i2c_write(st.hw->addr, st.reg->s1_addr, 1, data)) return -1; /* AKM measurement mode register. */ data[0] = AKM_REG_CNTL; if (i2c_write(st.hw->addr, st.reg->s1_reg, 1, data)) return -1; /* Enable slave 1, 1-byte writes. */ data[0] = BIT_SLAVE_EN | 1; if (i2c_write(st.hw->addr, st.reg->s1_ctrl, 1, data)) return -1; /* Set slave 1 data. */ data[0] = AKM_SINGLE_MEASUREMENT; if (i2c_write(st.hw->addr, st.reg->s1_do, 1, data)) return -1; /* Trigger slave 0 and slave 1 actions at each sample. */ data[0] = 0x03; if (i2c_write(st.hw->addr, st.reg->i2c_delay_ctrl, 1, data)) return -1; #ifdef MPU9150 /* For the MPU9150, the auxiliary I2C bus needs to be set to VDD. */ data[0] = BIT_I2C_MST_VDDIO; if (i2c_write(st.hw->addr, st.reg->yg_offs_tc, 1, data)) return -1; #endif return 0; } #endif /** * @brief Read raw compass data. * @param[out] data Raw data in hardware units. * @param[out] timestamp Timestamp in milliseconds. Null if not needed. * @return 0 if successful. */ int mpu_get_compass_reg(short *data, unsigned long *timestamp) { #ifdef AK89xx_SECONDARY unsigned char tmp[9]; if (!(st.chip_cfg.sensors & INV_XYZ_COMPASS)) return -1; #ifdef AK89xx_BYPASS if (MPU9250_AK8963_SPIx_Reads(st.chip_cfg.compass_addr, AKM_REG_ST1, 8, tmp)) return -1; tmp[8] = AKM_SINGLE_MEASUREMENT; if (MPU9250_AK8963_SPIx_Writes(st.chip_cfg.compass_addr, AKM_REG_CNTL, 1, tmp+8)) return -1; #else if (i2c_read(st.hw->addr, st.reg->raw_compass, 8, tmp)) return -1; #endif #if defined AK8975_SECONDARY /* AK8975 doesn't have the overrun error bit. */ if (!(tmp[0] & AKM_DATA_READY)) return -2; if ((tmp[7] & AKM_OVERFLOW) || (tmp[7] & AKM_DATA_ERROR)) return -3; #elif defined AK8963_SECONDARY /* AK8963 doesn't have the data read error bit. */ if (!(tmp[0] & AKM_DATA_READY) || (tmp[0] & AKM_DATA_OVERRUN)) return -2; if (tmp[7] & AKM_OVERFLOW) return -3; #endif data[0] = (tmp[2] << 8) | tmp[1]; data[1] = (tmp[4] << 8) | tmp[3]; data[2] = (tmp[6] << 8) | tmp[5]; data[0] = ((long)data[0] * st.chip_cfg.mag_sens_adj[0]) >> 8; data[1] = ((long)data[1] * st.chip_cfg.mag_sens_adj[1]) >> 8; data[2] = ((long)data[2] * st.chip_cfg.mag_sens_adj[2]) >> 8; if (timestamp) get_ms(timestamp); return 0; #else return -1; #endif } /** * @brief Get the compass full-scale range. * @param[out] fsr Current full-scale range. * @return 0 if successful. */ int mpu_get_compass_fsr(unsigned short *fsr) { #ifdef AK89xx_SECONDARY fsr[0] = st.hw->compass_fsr; return 0; #else return -1; #endif } /** * @brief Enters LP accel motion interrupt mode. * The behaviour of this feature is very different between the MPU6050 and the * MPU6500. Each chip's version of this feature is explained below. * * \n The hardware motion threshold can be between 32mg and 8160mg in 32mg * increments. * * \n Low-power accel mode supports the following frequencies: * \n 1.25Hz, 5Hz, 20Hz, 40Hz * * \n MPU6500: * \n Unlike the MPU6050 version, the hardware does not "lock in" a reference * sample. The hardware monitors the accel data and detects any large change * over a short period of time. * * \n The hardware motion threshold can be between 4mg and 1020mg in 4mg * increments. * * \n MPU6500 Low-power accel mode supports the following frequencies: * \n 1.25Hz, 2.5Hz, 5Hz, 10Hz, 20Hz, 40Hz, 80Hz, 160Hz, 320Hz, 640Hz * * \n\n NOTES: * \n The driver will round down @e thresh to the nearest supported value if * an unsupported threshold is selected. * \n To select a fractional wake-up frequency, round down the value passed to * @e lpa_freq. * \n The MPU6500 does not support a delay parameter. If this function is used * for the MPU6500, the value passed to @e time will be ignored. * \n To disable this mode, set @e lpa_freq to zero. The driver will restore * the previous configuration. * * @param[in] thresh Motion threshold in mg. * @param[in] time Duration in milliseconds that the accel data must * exceed @e thresh before motion is reported. * @param[in] lpa_freq Minimum sampling rate, or zero to disable. * @return 0 if successful. */ int mpu_lp_motion_interrupt(unsigned short thresh, unsigned char time, unsigned char lpa_freq) { #if defined MPU6500 unsigned char data[3]; #endif if (lpa_freq) { #if defined MPU6500 unsigned char thresh_hw; /* 1LSb = 4mg. */ if (thresh > 1020) thresh_hw = 255; else if (thresh < 4) thresh_hw = 1; else thresh_hw = thresh >> 2; #endif if (!time) /* Minimum duration must be 1ms. */ time = 1; #if defined MPU6500 if (lpa_freq > 640) /* At this point, the chip has not been re-configured, so the * function can safely exit. */ return -1; #endif if (!st.chip_cfg.int_motion_only) { /* Store current settings for later. */ if (st.chip_cfg.dmp_on) { mpu_set_dmp_state(0); st.chip_cfg.cache.dmp_on = 1; } else st.chip_cfg.cache.dmp_on = 0; mpu_get_gyro_fsr(&st.chip_cfg.cache.gyro_fsr); mpu_get_accel_fsr(&st.chip_cfg.cache.accel_fsr); mpu_get_lpf(&st.chip_cfg.cache.lpf); mpu_get_sample_rate(&st.chip_cfg.cache.sample_rate); st.chip_cfg.cache.sensors_on = st.chip_cfg.sensors; mpu_get_fifo_config(&st.chip_cfg.cache.fifo_sensors); } #if defined MPU6500 /* Disable hardware interrupts. */ set_int_enable(0); /* Enter full-power accel-only mode, no FIFO/DMP. */ data[0] = 0; data[1] = 0; data[2] = BIT_STBY_XYZG; if (i2c_write(st.hw->addr, st.reg->user_ctrl, 3, data)) goto lp_int_restore; /* Set motion threshold. */ data[0] = thresh_hw; if (i2c_write(st.hw->addr, st.reg->motion_thr, 1, data)) goto lp_int_restore; /* Set wake frequency. */ if (lpa_freq == 1) data[0] = INV_LPA_1_25HZ; else if (lpa_freq == 2) data[0] = INV_LPA_2_5HZ; else if (lpa_freq <= 5) data[0] = INV_LPA_5HZ; else if (lpa_freq <= 10) data[0] = INV_LPA_10HZ; else if (lpa_freq <= 20) data[0] = INV_LPA_20HZ; else if (lpa_freq <= 40) data[0] = INV_LPA_40HZ; else if (lpa_freq <= 80) data[0] = INV_LPA_80HZ; else if (lpa_freq <= 160) data[0] = INV_LPA_160HZ; else if (lpa_freq <= 320) data[0] = INV_LPA_320HZ; else data[0] = INV_LPA_640HZ; if (i2c_write(st.hw->addr, st.reg->lp_accel_odr, 1, data)) goto lp_int_restore; /* Enable motion interrupt (MPU6500 version). */ data[0] = BITS_WOM_EN; if (i2c_write(st.hw->addr, st.reg->accel_intel, 1, data)) goto lp_int_restore; /* Enable cycle mode. */ data[0] = BIT_LPA_CYCLE; if (i2c_write(st.hw->addr, st.reg->pwr_mgmt_1, 1, data)) goto lp_int_restore; /* Enable interrupt. */ data[0] = BIT_MOT_INT_EN; if (i2c_write(st.hw->addr, st.reg->int_enable, 1, data)) goto lp_int_restore; st.chip_cfg.int_motion_only = 1; return 0; #endif } else { /* Don't "restore" the previous state if no state has been saved. */ int ii; char *cache_ptr = (char*)&st.chip_cfg.cache; for (ii = 0; ii < sizeof(st.chip_cfg.cache); ii++) { if (cache_ptr[ii] != 0) goto lp_int_restore; } /* If we reach this point, motion interrupt mode hasn't been used yet. */ return -1; } lp_int_restore: /* Set to invalid values to ensure no I2C writes are skipped. */ st.chip_cfg.gyro_fsr = 0xFF; st.chip_cfg.accel_fsr = 0xFF; st.chip_cfg.lpf = 0xFF; st.chip_cfg.sample_rate = 0xFFFF; st.chip_cfg.sensors = 0xFF; st.chip_cfg.fifo_enable = 0xFF; st.chip_cfg.clk_src = INV_CLK_PLL; mpu_set_sensors(st.chip_cfg.cache.sensors_on); mpu_set_gyro_fsr(st.chip_cfg.cache.gyro_fsr); mpu_set_accel_fsr(st.chip_cfg.cache.accel_fsr); mpu_set_lpf(st.chip_cfg.cache.lpf); mpu_set_sample_rate(st.chip_cfg.cache.sample_rate); mpu_configure_fifo(st.chip_cfg.cache.fifo_sensors); if (st.chip_cfg.cache.dmp_on) mpu_set_dmp_state(1); #ifdef MPU6500 /* Disable motion interrupt (MPU6500 version). */ data[0] = 0; if (i2c_write(st.hw->addr, st.reg->accel_intel, 1, data)) goto lp_int_restore; #endif st.chip_cfg.int_motion_only = 0; return 0; } /** * @} */ ================================================ FILE: Libraries/eMPL/inv_mpu.h ================================================ /* $License: Copyright (C) 2011-2012 InvenSense Corporation, All Rights Reserved. See included License.txt for License information. $ */ /** * @addtogroup DRIVERS Sensor Driver Layer * @brief Hardware drivers to communicate with sensors via I2C. * * @{ * @file inv_mpu.h * @brief An I2C-based driver for Invensense gyroscopes. * @details This driver currently works for the following devices: * MPU6050 * MPU6500 * MPU9150 (or MPU6050 w/ AK8975 on the auxiliary bus) * MPU9250 (or MPU6500 w/ AK8963 on the auxiliary bus) */ #ifndef _INV_MPU_H_ #define _INV_MPU_H_ #define INV_X_GYRO (0x40) #define INV_Y_GYRO (0x20) #define INV_Z_GYRO (0x10) #define INV_XYZ_GYRO (INV_X_GYRO | INV_Y_GYRO | INV_Z_GYRO) #define INV_XYZ_ACCEL (0x08) #define INV_XYZ_COMPASS (0x01) struct int_param_s { #if defined EMPL_TARGET_MSP430 || defined MOTION_DRIVER_TARGET_MSP430 || STM32F40_41xxx void (*cb)(void); unsigned short pin; unsigned char lp_exit; unsigned char active_low; #elif defined EMPL_TARGET_UC3L0 unsigned long pin; void (*cb)(volatile void*); void *arg; #endif }; #define MPU_INT_STATUS_DATA_READY (0x0001) #define MPU_INT_STATUS_DMP (0x0002) #define MPU_INT_STATUS_PLL_READY (0x0004) #define MPU_INT_STATUS_I2C_MST (0x0008) #define MPU_INT_STATUS_FIFO_OVERFLOW (0x0010) #define MPU_INT_STATUS_ZMOT (0x0020) #define MPU_INT_STATUS_MOT (0x0040) #define MPU_INT_STATUS_FREE_FALL (0x0080) #define MPU_INT_STATUS_DMP_0 (0x0100) #define MPU_INT_STATUS_DMP_1 (0x0200) #define MPU_INT_STATUS_DMP_2 (0x0400) #define MPU_INT_STATUS_DMP_3 (0x0800) #define MPU_INT_STATUS_DMP_4 (0x1000) #define MPU_INT_STATUS_DMP_5 (0x2000) /* Set up APIs */ int mpu_init(struct int_param_s *int_param); int mpu_init_slave(void); int mpu_set_bypass(unsigned char bypass_on); /* Configuration APIs */ int mpu_lp_accel_mode(unsigned char rate); int mpu_lp_motion_interrupt(unsigned short thresh, unsigned char time, unsigned char lpa_freq); int mpu_set_int_level(unsigned char active_low); int mpu_set_int_latched(unsigned char enable); int mpu_set_dmp_state(unsigned char enable); int mpu_get_dmp_state(unsigned char *enabled); int mpu_get_lpf(unsigned short *lpf); int mpu_set_lpf(unsigned short lpf); int mpu_get_gyro_fsr(unsigned short *fsr); int mpu_set_gyro_fsr(unsigned short fsr); int mpu_get_accel_fsr(unsigned char *fsr); int mpu_set_accel_fsr(unsigned char fsr); int mpu_get_compass_fsr(unsigned short *fsr); int mpu_get_gyro_sens(float *sens); int mpu_get_accel_sens(unsigned short *sens); int mpu_get_sample_rate(unsigned short *rate); int mpu_set_sample_rate(unsigned short rate); int mpu_get_compass_sample_rate(unsigned short *rate); int mpu_set_compass_sample_rate(unsigned short rate); int mpu_get_fifo_config(unsigned char *sensors); int mpu_configure_fifo(unsigned char sensors); int mpu_get_power_state(unsigned char *power_on); int mpu_set_sensors(unsigned char sensors); int mpu_read_6500_accel_bias(long *accel_bias); int mpu_set_gyro_bias_reg(long * gyro_bias); int mpu_set_accel_bias_6500_reg(const long *accel_bias); int mpu_read_6050_accel_bias(long *accel_bias); int mpu_set_accel_bias_6050_reg(const long *accel_bias); /* Data getter/setter APIs */ int mpu_get_gyro_reg(short *data, unsigned long *timestamp); int mpu_get_accel_reg(short *data, unsigned long *timestamp); int mpu_get_compass_reg(short *data, unsigned long *timestamp); int mpu_get_temperature(long *data, unsigned long *timestamp); int mpu_get_int_status(short *status); int mpu_read_fifo(short *gyro, short *accel, unsigned long *timestamp, unsigned char *sensors, unsigned char *more); int mpu_read_fifo_stream(unsigned short length, unsigned char *data, unsigned char *more); int mpu_reset_fifo(void); int mpu_write_mem(unsigned short mem_addr, unsigned short length, unsigned char *data); int mpu_read_mem(unsigned short mem_addr, unsigned short length, unsigned char *data); int mpu_load_firmware(unsigned short length, const unsigned char *firmware, unsigned short start_addr, unsigned short sample_rate); int mpu_reg_dump(void); int mpu_read_reg(unsigned char reg, unsigned char *data); int mpu_run_self_test(long *gyro, long *accel); int mpu_run_6500_self_test(long *gyro, long *accel, unsigned char debug); int mpu_register_tap_cb(void (*func)(unsigned char, unsigned char)); #endif /* #ifndef _INV_MPU_H_ */ ================================================ FILE: Libraries/eMPL/inv_mpu_dmp_motion_driver.c ================================================ /* $License: Copyright (C) 2011-2012 InvenSense Corporation, All Rights Reserved. See included License.txt for License information. $ */ /** * @addtogroup DRIVERS Sensor Driver Layer * @brief Hardware drivers to communicate with sensors via I2C. * * @{ * @file inv_mpu_dmp_motion_driver.c * @brief DMP image and interface functions. * @details All functions are preceded by the dmp_ prefix to * differentiate among MPL and general driver function calls. */ #include #include #include #include #include #include "inv_mpu.h" #include "inv_mpu_dmp_motion_driver.h" #include "dmpKey.h" #include "dmpmap.h" /* The following functions must be defined for this platform: * i2c_write(unsigned char slave_addr, unsigned char reg_addr, * unsigned char length, unsigned char const *data) * i2c_read(unsigned char slave_addr, unsigned char reg_addr, * unsigned char length, unsigned char *data) * delay_ms(unsigned long num_ms) * get_ms(unsigned long *count) */ #if defined MOTION_DRIVER_TARGET_MSP430 #include "msp430.h" #include "msp430_clock.h" #define delay_ms msp430_delay_ms #define get_ms msp430_get_clock_ms #define log_i(...) do {} while (0) #define log_e(...) do {} while (0) #elif defined EMPL_TARGET_MSP430 #include "msp430.h" #include "msp430_clock.h" #include "log.h" #define delay_ms msp430_delay_ms #define get_ms msp430_get_clock_ms #define log_i MPL_LOGI #define log_e MPL_LOGE #elif defined EMPL_TARGET_UC3L0 /* Instead of using the standard TWI driver from the ASF library, we're using * a TWI driver that follows the slave address + register address convention. */ #include "delay.h" #include "sysclk.h" #include "log.h" #include "uc3l0_clock.h" /* delay_ms is a function already defined in ASF. */ #define get_ms uc3l0_get_clock_ms #define log_i MPL_LOGI #define log_e MPL_LOGE #elif defined STM32F40_41xxx #include "stm32f4_delay.h" #define get_ms Get_Ms #else #error Gyro driver is missing the system layer implementations. #endif /* These defines are copied from dmpDefaultMPU6050.c in the general MPL * releases. These defines may change for each DMP image, so be sure to modify * these values when switching to a new image. */ #define CFG_LP_QUAT (2712) #define END_ORIENT_TEMP (1866) #define CFG_27 (2742) #define CFG_20 (2224) #define CFG_23 (2745) #define CFG_FIFO_ON_EVENT (2690) #define END_PREDICTION_UPDATE (1761) #define CGNOTICE_INTR (2620) #define X_GRT_Y_TMP (1358) #define CFG_DR_INT (1029) #define CFG_AUTH (1035) #define UPDATE_PROP_ROT (1835) #define END_COMPARE_Y_X_TMP2 (1455) #define SKIP_X_GRT_Y_TMP (1359) #define SKIP_END_COMPARE (1435) #define FCFG_3 (1088) #define FCFG_2 (1066) #define FCFG_1 (1062) #define END_COMPARE_Y_X_TMP3 (1434) #define FCFG_7 (1073) #define FCFG_6 (1106) #define FLAT_STATE_END (1713) #define SWING_END_4 (1616) #define SWING_END_2 (1565) #define SWING_END_3 (1587) #define SWING_END_1 (1550) #define CFG_8 (2718) #define CFG_15 (2727) #define CFG_16 (2746) #define CFG_EXT_GYRO_BIAS (1189) #define END_COMPARE_Y_X_TMP (1407) #define DO_NOT_UPDATE_PROP_ROT (1839) #define CFG_7 (1205) #define FLAT_STATE_END_TEMP (1683) #define END_COMPARE_Y_X (1484) #define SKIP_SWING_END_1 (1551) #define SKIP_SWING_END_3 (1588) #define SKIP_SWING_END_2 (1566) #define TILTG75_START (1672) #define CFG_6 (2753) #define TILTL75_END (1669) #define END_ORIENT (1884) #define CFG_FLICK_IN (2573) #define TILTL75_START (1643) #define CFG_MOTION_BIAS (1208) #define X_GRT_Y (1408) #define TEMPLABEL (2324) #define CFG_ANDROID_ORIENT_INT (1853) #define CFG_GYRO_RAW_DATA (2722) #define X_GRT_Y_TMP2 (1379) #define D_0_22 (22+512) #define D_0_24 (24+512) #define D_0_36 (36) #define D_0_52 (52) #define D_0_96 (96) #define D_0_104 (104) #define D_0_108 (108) #define D_0_163 (163) #define D_0_188 (188) #define D_0_192 (192) #define D_0_224 (224) #define D_0_228 (228) #define D_0_232 (232) #define D_0_236 (236) #define D_1_2 (256 + 2) #define D_1_4 (256 + 4) #define D_1_8 (256 + 8) #define D_1_10 (256 + 10) #define D_1_24 (256 + 24) #define D_1_28 (256 + 28) #define D_1_36 (256 + 36) #define D_1_40 (256 + 40) #define D_1_44 (256 + 44) #define D_1_72 (256 + 72) #define D_1_74 (256 + 74) #define D_1_79 (256 + 79) #define D_1_88 (256 + 88) #define D_1_90 (256 + 90) #define D_1_92 (256 + 92) #define D_1_96 (256 + 96) #define D_1_98 (256 + 98) #define D_1_106 (256 + 106) #define D_1_108 (256 + 108) #define D_1_112 (256 + 112) #define D_1_128 (256 + 144) #define D_1_152 (256 + 12) #define D_1_160 (256 + 160) #define D_1_176 (256 + 176) #define D_1_178 (256 + 178) #define D_1_218 (256 + 218) #define D_1_232 (256 + 232) #define D_1_236 (256 + 236) #define D_1_240 (256 + 240) #define D_1_244 (256 + 244) #define D_1_250 (256 + 250) #define D_1_252 (256 + 252) #define D_2_12 (512 + 12) #define D_2_96 (512 + 96) #define D_2_108 (512 + 108) #define D_2_208 (512 + 208) #define D_2_224 (512 + 224) #define D_2_236 (512 + 236) #define D_2_244 (512 + 244) #define D_2_248 (512 + 248) #define D_2_252 (512 + 252) #define CPASS_BIAS_X (35 * 16 + 4) #define CPASS_BIAS_Y (35 * 16 + 8) #define CPASS_BIAS_Z (35 * 16 + 12) #define CPASS_MTX_00 (36 * 16) #define CPASS_MTX_01 (36 * 16 + 4) #define CPASS_MTX_02 (36 * 16 + 8) #define CPASS_MTX_10 (36 * 16 + 12) #define CPASS_MTX_11 (37 * 16) #define CPASS_MTX_12 (37 * 16 + 4) #define CPASS_MTX_20 (37 * 16 + 8) #define CPASS_MTX_21 (37 * 16 + 12) #define CPASS_MTX_22 (43 * 16 + 12) #define D_EXT_GYRO_BIAS_X (61 * 16) #define D_EXT_GYRO_BIAS_Y (61 * 16) + 4 #define D_EXT_GYRO_BIAS_Z (61 * 16) + 8 #define D_ACT0 (40 * 16) #define D_ACSX (40 * 16 + 4) #define D_ACSY (40 * 16 + 8) #define D_ACSZ (40 * 16 + 12) #define FLICK_MSG (45 * 16 + 4) #define FLICK_COUNTER (45 * 16 + 8) #define FLICK_LOWER (45 * 16 + 12) #define FLICK_UPPER (46 * 16 + 12) #define D_AUTH_OUT (992) #define D_AUTH_IN (996) #define D_AUTH_A (1000) #define D_AUTH_B (1004) #define D_PEDSTD_BP_B (768 + 0x1C) #define D_PEDSTD_HP_A (768 + 0x78) #define D_PEDSTD_HP_B (768 + 0x7C) #define D_PEDSTD_BP_A4 (768 + 0x40) #define D_PEDSTD_BP_A3 (768 + 0x44) #define D_PEDSTD_BP_A2 (768 + 0x48) #define D_PEDSTD_BP_A1 (768 + 0x4C) #define D_PEDSTD_INT_THRSH (768 + 0x68) #define D_PEDSTD_CLIP (768 + 0x6C) #define D_PEDSTD_SB (768 + 0x28) #define D_PEDSTD_SB_TIME (768 + 0x2C) #define D_PEDSTD_PEAKTHRSH (768 + 0x98) #define D_PEDSTD_TIML (768 + 0x2A) #define D_PEDSTD_TIMH (768 + 0x2E) #define D_PEDSTD_PEAK (768 + 0X94) #define D_PEDSTD_STEPCTR (768 + 0x60) #define D_PEDSTD_TIMECTR (964) #define D_PEDSTD_DECI (768 + 0xA0) #define D_HOST_NO_MOT (976) #define D_ACCEL_BIAS (660) #define D_ORIENT_GAP (76) #define D_TILT0_H (48) #define D_TILT0_L (50) #define D_TILT1_H (52) #define D_TILT1_L (54) #define D_TILT2_H (56) #define D_TILT2_L (58) #define D_TILT3_H (60) #define D_TILT3_L (62) #define DMP_CODE_SIZE (3062) static const unsigned char dmp_memory[DMP_CODE_SIZE] = { /* bank # 0 */ 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x02, 0x00, 0x03, 0x00, 0x00, 0x00, 0x65, 0x00, 0x54, 0xff, 0xef, 0x00, 0x00, 0xfa, 0x80, 0x00, 0x0b, 0x12, 0x82, 0x00, 0x01, 0x03, 0x0c, 0x30, 0xc3, 0x0e, 0x8c, 0x8c, 0xe9, 0x14, 0xd5, 0x40, 0x02, 0x13, 0x71, 0x0f, 0x8e, 0x38, 0x83, 0xf8, 0x83, 0x30, 0x00, 0xf8, 0x83, 0x25, 0x8e, 0xf8, 0x83, 0x30, 0x00, 0xf8, 0x83, 0xff, 0xff, 0xff, 0xff, 0x0f, 0xfe, 0xa9, 0xd6, 0x24, 0x00, 0x04, 0x00, 0x1a, 0x82, 0x79, 0xa1, 0x00, 0x00, 0x00, 0x3c, 0xff, 0xff, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x38, 0x83, 0x6f, 0xa2, 0x00, 0x3e, 0x03, 0x30, 0x40, 0x00, 0x00, 0x00, 0x02, 0xca, 0xe3, 0x09, 0x3e, 0x80, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x0c, 0x18, 0x6e, 0x00, 0x00, 0x06, 0x92, 0x0a, 0x16, 0xc0, 0xdf, 0xff, 0xff, 0x02, 0x56, 0xfd, 0x8c, 0xd3, 0x77, 0xff, 0xe1, 0xc4, 0x96, 0xe0, 0xc5, 0xbe, 0xaa, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x0b, 0x2b, 0x00, 0x00, 0x16, 0x57, 0x00, 0x00, 0x03, 0x59, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1d, 0xfa, 0x00, 0x02, 0x6c, 0x1d, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xff, 0xdf, 0xeb, 0x00, 0x3e, 0xb3, 0xb6, 0x00, 0x0d, 0x22, 0x78, 0x00, 0x00, 0x2f, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x42, 0xb5, 0x00, 0x00, 0x39, 0xa2, 0x00, 0x00, 0xb3, 0x65, 0xd9, 0x0e, 0x9f, 0xc9, 0x1d, 0xcf, 0x4c, 0x34, 0x30, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x00, 0x3b, 0xb6, 0x7a, 0xe8, 0x00, 0x64, 0x00, 0x00, 0x00, 0xc8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* bank # 1 */ 0x10, 0x00, 0x00, 0x00, 0x10, 0x00, 0xfa, 0x92, 0x10, 0x00, 0x22, 0x5e, 0x00, 0x0d, 0x22, 0x9f, 0x00, 0x01, 0x00, 0x00, 0x00, 0x32, 0x00, 0x00, 0xff, 0x46, 0x00, 0x00, 0x63, 0xd4, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x04, 0xd6, 0x00, 0x00, 0x04, 0xcc, 0x00, 0x00, 0x04, 0xcc, 0x00, 0x00, 0x00, 0x00, 0x10, 0x72, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x02, 0x00, 0x05, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x05, 0x00, 0x64, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x32, 0xf8, 0x98, 0x00, 0x00, 0xff, 0x65, 0x00, 0x00, 0x83, 0x0f, 0x00, 0x00, 0xff, 0x9b, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0xb2, 0x6a, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0xfb, 0x83, 0x00, 0x68, 0x00, 0x00, 0x00, 0xd9, 0xfc, 0x00, 0x7c, 0xf1, 0xff, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x65, 0x00, 0x00, 0x00, 0x64, 0x03, 0xe8, 0x00, 0x64, 0x00, 0x28, 0x00, 0x00, 0x00, 0x25, 0x00, 0x00, 0x00, 0x00, 0x16, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x2f, 0x00, 0x00, 0x00, 0x00, 0x01, 0xf4, 0x00, 0x00, 0x10, 0x00, /* bank # 2 */ 0x00, 0x28, 0x00, 0x00, 0xff, 0xff, 0x45, 0x81, 0xff, 0xff, 0xfa, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0x05, 0x00, 0x05, 0xba, 0xc6, 0x00, 0x47, 0x78, 0xa2, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x25, 0x4d, 0x00, 0x2f, 0x70, 0x6d, 0x00, 0x00, 0x05, 0xae, 0x00, 0x0c, 0x02, 0xd0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, 0x00, 0x0e, 0x00, 0x00, 0x0a, 0xc7, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x32, 0xff, 0xff, 0xff, 0x9c, 0x00, 0x00, 0x0b, 0x2b, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x64, 0xff, 0xe5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* bank # 3 */ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0x24, 0x26, 0xd3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x10, 0x00, 0x96, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0a, 0x4e, 0x68, 0xcd, 0xcf, 0x77, 0x09, 0x50, 0x16, 0x67, 0x59, 0xc6, 0x19, 0xce, 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17, 0xd7, 0x84, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc7, 0x93, 0x8f, 0x9d, 0x1e, 0x1b, 0x1c, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 0x18, 0x85, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x67, 0x7d, 0xdf, 0x7e, 0x72, 0x90, 0x2e, 0x55, 0x4c, 0xf6, 0xe6, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* bank # 4 */ 0xd8, 0xdc, 0xb4, 0xb8, 0xb0, 0xd8, 0xb9, 0xab, 0xf3, 0xf8, 0xfa, 0xb3, 0xb7, 0xbb, 0x8e, 0x9e, 0xae, 0xf1, 0x32, 0xf5, 0x1b, 0xf1, 0xb4, 0xb8, 0xb0, 0x80, 0x97, 0xf1, 0xa9, 0xdf, 0xdf, 0xdf, 0xaa, 0xdf, 0xdf, 0xdf, 0xf2, 0xaa, 0xc5, 0xcd, 0xc7, 0xa9, 0x0c, 0xc9, 0x2c, 0x97, 0xf1, 0xa9, 0x89, 0x26, 0x46, 0x66, 0xb2, 0x89, 0x99, 0xa9, 0x2d, 0x55, 0x7d, 0xb0, 0xb0, 0x8a, 0xa8, 0x96, 0x36, 0x56, 0x76, 0xf1, 0xba, 0xa3, 0xb4, 0xb2, 0x80, 0xc0, 0xb8, 0xa8, 0x97, 0x11, 0xb2, 0x83, 0x98, 0xba, 0xa3, 0xf0, 0x24, 0x08, 0x44, 0x10, 0x64, 0x18, 0xb2, 0xb9, 0xb4, 0x98, 0x83, 0xf1, 0xa3, 0x29, 0x55, 0x7d, 0xba, 0xb5, 0xb1, 0xa3, 0x83, 0x93, 0xf0, 0x00, 0x28, 0x50, 0xf5, 0xb2, 0xb6, 0xaa, 0x83, 0x93, 0x28, 0x54, 0x7c, 0xf1, 0xb9, 0xa3, 0x82, 0x93, 0x61, 0xba, 0xa2, 0xda, 0xde, 0xdf, 0xdb, 0x81, 0x9a, 0xb9, 0xae, 0xf5, 0x60, 0x68, 0x70, 0xf1, 0xda, 0xba, 0xa2, 0xdf, 0xd9, 0xba, 0xa2, 0xfa, 0xb9, 0xa3, 0x82, 0x92, 0xdb, 0x31, 0xba, 0xa2, 0xd9, 0xba, 0xa2, 0xf8, 0xdf, 0x85, 0xa4, 0xd0, 0xc1, 0xbb, 0xad, 0x83, 0xc2, 0xc5, 0xc7, 0xb8, 0xa2, 0xdf, 0xdf, 0xdf, 0xba, 0xa0, 0xdf, 0xdf, 0xdf, 0xd8, 0xd8, 0xf1, 0xb8, 0xaa, 0xb3, 0x8d, 0xb4, 0x98, 0x0d, 0x35, 0x5d, 0xb2, 0xb6, 0xba, 0xaf, 0x8c, 0x96, 0x19, 0x8f, 0x9f, 0xa7, 0x0e, 0x16, 0x1e, 0xb4, 0x9a, 0xb8, 0xaa, 0x87, 0x2c, 0x54, 0x7c, 0xba, 0xa4, 0xb0, 0x8a, 0xb6, 0x91, 0x32, 0x56, 0x76, 0xb2, 0x84, 0x94, 0xa4, 0xc8, 0x08, 0xcd, 0xd8, 0xb8, 0xb4, 0xb0, 0xf1, 0x99, 0x82, 0xa8, 0x2d, 0x55, 0x7d, 0x98, 0xa8, 0x0e, 0x16, 0x1e, 0xa2, 0x2c, 0x54, 0x7c, 0x92, 0xa4, 0xf0, 0x2c, 0x50, 0x78, /* bank # 5 */ 0xf1, 0x84, 0xa8, 0x98, 0xc4, 0xcd, 0xfc, 0xd8, 0x0d, 0xdb, 0xa8, 0xfc, 0x2d, 0xf3, 0xd9, 0xba, 0xa6, 0xf8, 0xda, 0xba, 0xa6, 0xde, 0xd8, 0xba, 0xb2, 0xb6, 0x86, 0x96, 0xa6, 0xd0, 0xf3, 0xc8, 0x41, 0xda, 0xa6, 0xc8, 0xf8, 0xd8, 0xb0, 0xb4, 0xb8, 0x82, 0xa8, 0x92, 0xf5, 0x2c, 0x54, 0x88, 0x98, 0xf1, 0x35, 0xd9, 0xf4, 0x18, 0xd8, 0xf1, 0xa2, 0xd0, 0xf8, 0xf9, 0xa8, 0x84, 0xd9, 0xc7, 0xdf, 0xf8, 0xf8, 0x83, 0xc5, 0xda, 0xdf, 0x69, 0xdf, 0x83, 0xc1, 0xd8, 0xf4, 0x01, 0x14, 0xf1, 0xa8, 0x82, 0x4e, 0xa8, 0x84, 0xf3, 0x11, 0xd1, 0x82, 0xf5, 0xd9, 0x92, 0x28, 0x97, 0x88, 0xf1, 0x09, 0xf4, 0x1c, 0x1c, 0xd8, 0x84, 0xa8, 0xf3, 0xc0, 0xf9, 0xd1, 0xd9, 0x97, 0x82, 0xf1, 0x29, 0xf4, 0x0d, 0xd8, 0xf3, 0xf9, 0xf9, 0xd1, 0xd9, 0x82, 0xf4, 0xc2, 0x03, 0xd8, 0xde, 0xdf, 0x1a, 0xd8, 0xf1, 0xa2, 0xfa, 0xf9, 0xa8, 0x84, 0x98, 0xd9, 0xc7, 0xdf, 0xf8, 0xf8, 0xf8, 0x83, 0xc7, 0xda, 0xdf, 0x69, 0xdf, 0xf8, 0x83, 0xc3, 0xd8, 0xf4, 0x01, 0x14, 0xf1, 0x98, 0xa8, 0x82, 0x2e, 0xa8, 0x84, 0xf3, 0x11, 0xd1, 0x82, 0xf5, 0xd9, 0x92, 0x50, 0x97, 0x88, 0xf1, 0x09, 0xf4, 0x1c, 0xd8, 0x84, 0xa8, 0xf3, 0xc0, 0xf8, 0xf9, 0xd1, 0xd9, 0x97, 0x82, 0xf1, 0x49, 0xf4, 0x0d, 0xd8, 0xf3, 0xf9, 0xf9, 0xd1, 0xd9, 0x82, 0xf4, 0xc4, 0x03, 0xd8, 0xde, 0xdf, 0xd8, 0xf1, 0xad, 0x88, 0x98, 0xcc, 0xa8, 0x09, 0xf9, 0xd9, 0x82, 0x92, 0xa8, 0xf5, 0x7c, 0xf1, 0x88, 0x3a, 0xcf, 0x94, 0x4a, 0x6e, 0x98, 0xdb, 0x69, 0x31, 0xda, 0xad, 0xf2, 0xde, 0xf9, 0xd8, 0x87, 0x95, 0xa8, 0xf2, 0x21, 0xd1, 0xda, 0xa5, 0xf9, 0xf4, 0x17, 0xd9, 0xf1, 0xae, 0x8e, 0xd0, 0xc0, 0xc3, 0xae, 0x82, /* bank # 6 */ 0xc6, 0x84, 0xc3, 0xa8, 0x85, 0x95, 0xc8, 0xa5, 0x88, 0xf2, 0xc0, 0xf1, 0xf4, 0x01, 0x0e, 0xf1, 0x8e, 0x9e, 0xa8, 0xc6, 0x3e, 0x56, 0xf5, 0x54, 0xf1, 0x88, 0x72, 0xf4, 0x01, 0x15, 0xf1, 0x98, 0x45, 0x85, 0x6e, 0xf5, 0x8e, 0x9e, 0x04, 0x88, 0xf1, 0x42, 0x98, 0x5a, 0x8e, 0x9e, 0x06, 0x88, 0x69, 0xf4, 0x01, 0x1c, 0xf1, 0x98, 0x1e, 0x11, 0x08, 0xd0, 0xf5, 0x04, 0xf1, 0x1e, 0x97, 0x02, 0x02, 0x98, 0x36, 0x25, 0xdb, 0xf9, 0xd9, 0x85, 0xa5, 0xf3, 0xc1, 0xda, 0x85, 0xa5, 0xf3, 0xdf, 0xd8, 0x85, 0x95, 0xa8, 0xf3, 0x09, 0xda, 0xa5, 0xfa, 0xd8, 0x82, 0x92, 0xa8, 0xf5, 0x78, 0xf1, 0x88, 0x1a, 0x84, 0x9f, 0x26, 0x88, 0x98, 0x21, 0xda, 0xf4, 0x1d, 0xf3, 0xd8, 0x87, 0x9f, 0x39, 0xd1, 0xaf, 0xd9, 0xdf, 0xdf, 0xfb, 0xf9, 0xf4, 0x0c, 0xf3, 0xd8, 0xfa, 0xd0, 0xf8, 0xda, 0xf9, 0xf9, 0xd0, 0xdf, 0xd9, 0xf9, 0xd8, 0xf4, 0x0b, 0xd8, 0xf3, 0x87, 0x9f, 0x39, 0xd1, 0xaf, 0xd9, 0xdf, 0xdf, 0xf4, 0x1d, 0xf3, 0xd8, 0xfa, 0xfc, 0xa8, 0x69, 0xf9, 0xf9, 0xaf, 0xd0, 0xda, 0xde, 0xfa, 0xd9, 0xf8, 0x8f, 0x9f, 0xa8, 0xf1, 0xcc, 0xf3, 0x98, 0xdb, 0x45, 0xd9, 0xaf, 0xdf, 0xd0, 0xf8, 0xd8, 0xf1, 0x8f, 0x9f, 0xa8, 0xca, 0xf3, 0x88, 0x09, 0xda, 0xaf, 0x8f, 0xcb, 0xf8, 0xd8, 0xf2, 0xad, 0x97, 0x8d, 0x0c, 0xd9, 0xa5, 0xdf, 0xf9, 0xba, 0xa6, 0xf3, 0xfa, 0xf4, 0x12, 0xf2, 0xd8, 0x95, 0x0d, 0xd1, 0xd9, 0xba, 0xa6, 0xf3, 0xfa, 0xda, 0xa5, 0xf2, 0xc1, 0xba, 0xa6, 0xf3, 0xdf, 0xd8, 0xf1, 0xba, 0xb2, 0xb6, 0x86, 0x96, 0xa6, 0xd0, 0xca, 0xf3, 0x49, 0xda, 0xa6, 0xcb, 0xf8, 0xd8, 0xb0, 0xb4, 0xb8, 0xd8, 0xad, 0x84, 0xf2, 0xc0, 0xdf, 0xf1, 0x8f, 0xcb, 0xc3, 0xa8, /* bank # 7 */ 0xb2, 0xb6, 0x86, 0x96, 0xc8, 0xc1, 0xcb, 0xc3, 0xf3, 0xb0, 0xb4, 0x88, 0x98, 0xa8, 0x21, 0xdb, 0x71, 0x8d, 0x9d, 0x71, 0x85, 0x95, 0x21, 0xd9, 0xad, 0xf2, 0xfa, 0xd8, 0x85, 0x97, 0xa8, 0x28, 0xd9, 0xf4, 0x08, 0xd8, 0xf2, 0x8d, 0x29, 0xda, 0xf4, 0x05, 0xd9, 0xf2, 0x85, 0xa4, 0xc2, 0xf2, 0xd8, 0xa8, 0x8d, 0x94, 0x01, 0xd1, 0xd9, 0xf4, 0x11, 0xf2, 0xd8, 0x87, 0x21, 0xd8, 0xf4, 0x0a, 0xd8, 0xf2, 0x84, 0x98, 0xa8, 0xc8, 0x01, 0xd1, 0xd9, 0xf4, 0x11, 0xd8, 0xf3, 0xa4, 0xc8, 0xbb, 0xaf, 0xd0, 0xf2, 0xde, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xd8, 0xf1, 0xb8, 0xf6, 0xb5, 0xb9, 0xb0, 0x8a, 0x95, 0xa3, 0xde, 0x3c, 0xa3, 0xd9, 0xf8, 0xd8, 0x5c, 0xa3, 0xd9, 0xf8, 0xd8, 0x7c, 0xa3, 0xd9, 0xf8, 0xd8, 0xf8, 0xf9, 0xd1, 0xa5, 0xd9, 0xdf, 0xda, 0xfa, 0xd8, 0xb1, 0x85, 0x30, 0xf7, 0xd9, 0xde, 0xd8, 0xf8, 0x30, 0xad, 0xda, 0xde, 0xd8, 0xf2, 0xb4, 0x8c, 0x99, 0xa3, 0x2d, 0x55, 0x7d, 0xa0, 0x83, 0xdf, 0xdf, 0xdf, 0xb5, 0x91, 0xa0, 0xf6, 0x29, 0xd9, 0xfb, 0xd8, 0xa0, 0xfc, 0x29, 0xd9, 0xfa, 0xd8, 0xa0, 0xd0, 0x51, 0xd9, 0xf8, 0xd8, 0xfc, 0x51, 0xd9, 0xf9, 0xd8, 0x79, 0xd9, 0xfb, 0xd8, 0xa0, 0xd0, 0xfc, 0x79, 0xd9, 0xfa, 0xd8, 0xa1, 0xf9, 0xf9, 0xf9, 0xf9, 0xf9, 0xa0, 0xda, 0xdf, 0xdf, 0xdf, 0xd8, 0xa1, 0xf8, 0xf8, 0xf8, 0xf8, 0xf8, 0xac, 0xde, 0xf8, 0xad, 0xde, 0x83, 0x93, 0xac, 0x2c, 0x54, 0x7c, 0xf1, 0xa8, 0xdf, 0xdf, 0xdf, 0xf6, 0x9d, 0x2c, 0xda, 0xa0, 0xdf, 0xd9, 0xfa, 0xdb, 0x2d, 0xf8, 0xd8, 0xa8, 0x50, 0xda, 0xa0, 0xd0, 0xde, 0xd9, 0xd0, 0xf8, 0xf8, 0xf8, 0xdb, 0x55, 0xf8, 0xd8, 0xa8, 0x78, 0xda, 0xa0, 0xd0, 0xdf, /* bank # 8 */ 0xd9, 0xd0, 0xfa, 0xf8, 0xf8, 0xf8, 0xf8, 0xdb, 0x7d, 0xf8, 0xd8, 0x9c, 0xa8, 0x8c, 0xf5, 0x30, 0xdb, 0x38, 0xd9, 0xd0, 0xde, 0xdf, 0xa0, 0xd0, 0xde, 0xdf, 0xd8, 0xa8, 0x48, 0xdb, 0x58, 0xd9, 0xdf, 0xd0, 0xde, 0xa0, 0xdf, 0xd0, 0xde, 0xd8, 0xa8, 0x68, 0xdb, 0x70, 0xd9, 0xdf, 0xdf, 0xa0, 0xdf, 0xdf, 0xd8, 0xf1, 0xa8, 0x88, 0x90, 0x2c, 0x54, 0x7c, 0x98, 0xa8, 0xd0, 0x5c, 0x38, 0xd1, 0xda, 0xf2, 0xae, 0x8c, 0xdf, 0xf9, 0xd8, 0xb0, 0x87, 0xa8, 0xc1, 0xc1, 0xb1, 0x88, 0xa8, 0xc6, 0xf9, 0xf9, 0xda, 0x36, 0xd8, 0xa8, 0xf9, 0xda, 0x36, 0xd8, 0xa8, 0xf9, 0xda, 0x36, 0xd8, 0xa8, 0xf9, 0xda, 0x36, 0xd8, 0xa8, 0xf9, 0xda, 0x36, 0xd8, 0xf7, 0x8d, 0x9d, 0xad, 0xf8, 0x18, 0xda, 0xf2, 0xae, 0xdf, 0xd8, 0xf7, 0xad, 0xfa, 0x30, 0xd9, 0xa4, 0xde, 0xf9, 0xd8, 0xf2, 0xae, 0xde, 0xfa, 0xf9, 0x83, 0xa7, 0xd9, 0xc3, 0xc5, 0xc7, 0xf1, 0x88, 0x9b, 0xa7, 0x7a, 0xad, 0xf7, 0xde, 0xdf, 0xa4, 0xf8, 0x84, 0x94, 0x08, 0xa7, 0x97, 0xf3, 0x00, 0xae, 0xf2, 0x98, 0x19, 0xa4, 0x88, 0xc6, 0xa3, 0x94, 0x88, 0xf6, 0x32, 0xdf, 0xf2, 0x83, 0x93, 0xdb, 0x09, 0xd9, 0xf2, 0xaa, 0xdf, 0xd8, 0xd8, 0xae, 0xf8, 0xf9, 0xd1, 0xda, 0xf3, 0xa4, 0xde, 0xa7, 0xf1, 0x88, 0x9b, 0x7a, 0xd8, 0xf3, 0x84, 0x94, 0xae, 0x19, 0xf9, 0xda, 0xaa, 0xf1, 0xdf, 0xd8, 0xa8, 0x81, 0xc0, 0xc3, 0xc5, 0xc7, 0xa3, 0x92, 0x83, 0xf6, 0x28, 0xad, 0xde, 0xd9, 0xf8, 0xd8, 0xa3, 0x50, 0xad, 0xd9, 0xf8, 0xd8, 0xa3, 0x78, 0xad, 0xd9, 0xf8, 0xd8, 0xf8, 0xf9, 0xd1, 0xa1, 0xda, 0xde, 0xc3, 0xc5, 0xc7, 0xd8, 0xa1, 0x81, 0x94, 0xf8, 0x18, 0xf2, 0xb0, 0x89, 0xac, 0xc3, 0xc5, 0xc7, 0xf1, 0xd8, 0xb8, /* bank # 9 */ 0xb4, 0xb0, 0x97, 0x86, 0xa8, 0x31, 0x9b, 0x06, 0x99, 0x07, 0xab, 0x97, 0x28, 0x88, 0x9b, 0xf0, 0x0c, 0x20, 0x14, 0x40, 0xb0, 0xb4, 0xb8, 0xf0, 0xa8, 0x8a, 0x9a, 0x28, 0x50, 0x78, 0xb7, 0x9b, 0xa8, 0x29, 0x51, 0x79, 0x24, 0x70, 0x59, 0x44, 0x69, 0x38, 0x64, 0x48, 0x31, 0xf1, 0xbb, 0xab, 0x88, 0x00, 0x2c, 0x54, 0x7c, 0xf0, 0xb3, 0x8b, 0xb8, 0xa8, 0x04, 0x28, 0x50, 0x78, 0xf1, 0xb0, 0x88, 0xb4, 0x97, 0x26, 0xa8, 0x59, 0x98, 0xbb, 0xab, 0xb3, 0x8b, 0x02, 0x26, 0x46, 0x66, 0xb0, 0xb8, 0xf0, 0x8a, 0x9c, 0xa8, 0x29, 0x51, 0x79, 0x8b, 0x29, 0x51, 0x79, 0x8a, 0x24, 0x70, 0x59, 0x8b, 0x20, 0x58, 0x71, 0x8a, 0x44, 0x69, 0x38, 0x8b, 0x39, 0x40, 0x68, 0x8a, 0x64, 0x48, 0x31, 0x8b, 0x30, 0x49, 0x60, 0x88, 0xf1, 0xac, 0x00, 0x2c, 0x54, 0x7c, 0xf0, 0x8c, 0xa8, 0x04, 0x28, 0x50, 0x78, 0xf1, 0x88, 0x97, 0x26, 0xa8, 0x59, 0x98, 0xac, 0x8c, 0x02, 0x26, 0x46, 0x66, 0xf0, 0x89, 0x9c, 0xa8, 0x29, 0x51, 0x79, 0x24, 0x70, 0x59, 0x44, 0x69, 0x38, 0x64, 0x48, 0x31, 0xa9, 0x88, 0x09, 0x20, 0x59, 0x70, 0xab, 0x11, 0x38, 0x40, 0x69, 0xa8, 0x19, 0x31, 0x48, 0x60, 0x8c, 0xa8, 0x3c, 0x41, 0x5c, 0x20, 0x7c, 0x00, 0xf1, 0x87, 0x98, 0x19, 0x86, 0xa8, 0x6e, 0x76, 0x7e, 0xa9, 0x99, 0x88, 0x2d, 0x55, 0x7d, 0xd8, 0xb1, 0xb5, 0xb9, 0xa3, 0xdf, 0xdf, 0xdf, 0xae, 0xd0, 0xdf, 0xaa, 0xd0, 0xde, 0xf2, 0xab, 0xf8, 0xf9, 0xd9, 0xb0, 0x87, 0xc4, 0xaa, 0xf1, 0xdf, 0xdf, 0xbb, 0xaf, 0xdf, 0xdf, 0xb9, 0xd8, 0xb1, 0xf1, 0xa3, 0x97, 0x8e, 0x60, 0xdf, 0xb0, 0x84, 0xf2, 0xc8, 0xf8, 0xf9, 0xd9, 0xde, 0xd8, 0x93, 0x85, 0xf1, 0x4a, 0xb1, 0x83, 0xa3, 0x08, 0xb5, 0x83, /* bank # 10 */ 0x9a, 0x08, 0x10, 0xb7, 0x9f, 0x10, 0xd8, 0xf1, 0xb0, 0xba, 0xae, 0xb0, 0x8a, 0xc2, 0xb2, 0xb6, 0x8e, 0x9e, 0xf1, 0xfb, 0xd9, 0xf4, 0x1d, 0xd8, 0xf9, 0xd9, 0x0c, 0xf1, 0xd8, 0xf8, 0xf8, 0xad, 0x61, 0xd9, 0xae, 0xfb, 0xd8, 0xf4, 0x0c, 0xf1, 0xd8, 0xf8, 0xf8, 0xad, 0x19, 0xd9, 0xae, 0xfb, 0xdf, 0xd8, 0xf4, 0x16, 0xf1, 0xd8, 0xf8, 0xad, 0x8d, 0x61, 0xd9, 0xf4, 0xf4, 0xac, 0xf5, 0x9c, 0x9c, 0x8d, 0xdf, 0x2b, 0xba, 0xb6, 0xae, 0xfa, 0xf8, 0xf4, 0x0b, 0xd8, 0xf1, 0xae, 0xd0, 0xf8, 0xad, 0x51, 0xda, 0xae, 0xfa, 0xf8, 0xf1, 0xd8, 0xb9, 0xb1, 0xb6, 0xa3, 0x83, 0x9c, 0x08, 0xb9, 0xb1, 0x83, 0x9a, 0xb5, 0xaa, 0xc0, 0xfd, 0x30, 0x83, 0xb7, 0x9f, 0x10, 0xb5, 0x8b, 0x93, 0xf2, 0x02, 0x02, 0xd1, 0xab, 0xda, 0xde, 0xd8, 0xf1, 0xb0, 0x80, 0xba, 0xab, 0xc0, 0xc3, 0xb2, 0x84, 0xc1, 0xc3, 0xd8, 0xb1, 0xb9, 0xf3, 0x8b, 0xa3, 0x91, 0xb6, 0x09, 0xb4, 0xd9, 0xab, 0xde, 0xb0, 0x87, 0x9c, 0xb9, 0xa3, 0xdd, 0xf1, 0xb3, 0x8b, 0x8b, 0x8b, 0x8b, 0x8b, 0xb0, 0x87, 0xa3, 0xa3, 0xa3, 0xa3, 0xb2, 0x8b, 0xb6, 0x9b, 0xf2, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xf1, 0xb0, 0x87, 0xb5, 0x9a, 0xa3, 0xf3, 0x9b, 0xa3, 0xa3, 0xdc, 0xba, 0xac, 0xdf, 0xb9, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xd8, 0xd8, 0xd8, 0xbb, 0xb3, 0xb7, 0xf1, 0xaa, 0xf9, 0xda, 0xff, 0xd9, 0x80, 0x9a, 0xaa, 0x28, 0xb4, 0x80, 0x98, 0xa7, 0x20, 0xb7, 0x97, 0x87, 0xa8, 0x66, 0x88, 0xf0, 0x79, 0x51, 0xf1, 0x90, 0x2c, 0x87, 0x0c, 0xa7, 0x81, 0x97, 0x62, 0x93, 0xf0, 0x71, 0x71, 0x60, 0x85, 0x94, 0x01, 0x29, /* bank # 11 */ 0x51, 0x79, 0x90, 0xa5, 0xf1, 0x28, 0x4c, 0x6c, 0x87, 0x0c, 0x95, 0x18, 0x85, 0x78, 0xa3, 0x83, 0x90, 0x28, 0x4c, 0x6c, 0x88, 0x6c, 0xd8, 0xf3, 0xa2, 0x82, 0x00, 0xf2, 0x10, 0xa8, 0x92, 0x19, 0x80, 0xa2, 0xf2, 0xd9, 0x26, 0xd8, 0xf1, 0x88, 0xa8, 0x4d, 0xd9, 0x48, 0xd8, 0x96, 0xa8, 0x39, 0x80, 0xd9, 0x3c, 0xd8, 0x95, 0x80, 0xa8, 0x39, 0xa6, 0x86, 0x98, 0xd9, 0x2c, 0xda, 0x87, 0xa7, 0x2c, 0xd8, 0xa8, 0x89, 0x95, 0x19, 0xa9, 0x80, 0xd9, 0x38, 0xd8, 0xa8, 0x89, 0x39, 0xa9, 0x80, 0xda, 0x3c, 0xd8, 0xa8, 0x2e, 0xa8, 0x39, 0x90, 0xd9, 0x0c, 0xd8, 0xa8, 0x95, 0x31, 0x98, 0xd9, 0x0c, 0xd8, 0xa8, 0x09, 0xd9, 0xff, 0xd8, 0x01, 0xda, 0xff, 0xd8, 0x95, 0x39, 0xa9, 0xda, 0x26, 0xff, 0xd8, 0x90, 0xa8, 0x0d, 0x89, 0x99, 0xa8, 0x10, 0x80, 0x98, 0x21, 0xda, 0x2e, 0xd8, 0x89, 0x99, 0xa8, 0x31, 0x80, 0xda, 0x2e, 0xd8, 0xa8, 0x86, 0x96, 0x31, 0x80, 0xda, 0x2e, 0xd8, 0xa8, 0x87, 0x31, 0x80, 0xda, 0x2e, 0xd8, 0xa8, 0x82, 0x92, 0xf3, 0x41, 0x80, 0xf1, 0xd9, 0x2e, 0xd8, 0xa8, 0x82, 0xf3, 0x19, 0x80, 0xf1, 0xd9, 0x2e, 0xd8, 0x82, 0xac, 0xf3, 0xc0, 0xa2, 0x80, 0x22, 0xf1, 0xa6, 0x2e, 0xa7, 0x2e, 0xa9, 0x22, 0x98, 0xa8, 0x29, 0xda, 0xac, 0xde, 0xff, 0xd8, 0xa2, 0xf2, 0x2a, 0xf1, 0xa9, 0x2e, 0x82, 0x92, 0xa8, 0xf2, 0x31, 0x80, 0xa6, 0x96, 0xf1, 0xd9, 0x00, 0xac, 0x8c, 0x9c, 0x0c, 0x30, 0xac, 0xde, 0xd0, 0xde, 0xff, 0xd8, 0x8c, 0x9c, 0xac, 0xd0, 0x10, 0xac, 0xde, 0x80, 0x92, 0xa2, 0xf2, 0x4c, 0x82, 0xa8, 0xf1, 0xca, 0xf2, 0x35, 0xf1, 0x96, 0x88, 0xa6, 0xd9, 0x00, 0xd8, 0xf1, 0xff }; static const unsigned short sStartAddress = 0x0400; /* END OF SECTION COPIED FROM dmpDefaultMPU6050.c */ #define INT_SRC_TAP (0x01) #define INT_SRC_ANDROID_ORIENT (0x08) #define DMP_FEATURE_SEND_ANY_GYRO (DMP_FEATURE_SEND_RAW_GYRO | \ DMP_FEATURE_SEND_CAL_GYRO) #define MAX_PACKET_LENGTH (32) #define DMP_SAMPLE_RATE (200) #define GYRO_SF (46850825LL * 200 / DMP_SAMPLE_RATE) //#define FIFO_CORRUPTION_CHECK #ifdef FIFO_CORRUPTION_CHECK #define QUAT_ERROR_THRESH (1L<<24) #define QUAT_MAG_SQ_NORMALIZED (1L<<28) #define QUAT_MAG_SQ_MIN (QUAT_MAG_SQ_NORMALIZED - QUAT_ERROR_THRESH) #define QUAT_MAG_SQ_MAX (QUAT_MAG_SQ_NORMALIZED + QUAT_ERROR_THRESH) #endif struct dmp_s { void (*tap_cb)(unsigned char count, unsigned char direction); void (*android_orient_cb)(unsigned char orientation); unsigned short orient; unsigned short feature_mask; unsigned short fifo_rate; unsigned char packet_length; }; static struct dmp_s dmp = { /*.tap_cb = */NULL, /*.android_orient_cb = */NULL, /*.orient = */0, /*.feature_mask = */0, /*.fifo_rate = */0, /*.packet_length = */0 }; /** * @brief Load the DMP with this image. * @return 0 if successful. */ int dmp_load_motion_driver_firmware(void) { return mpu_load_firmware(DMP_CODE_SIZE, dmp_memory, sStartAddress, DMP_SAMPLE_RATE); } /** * @brief Push gyro and accel orientation to the DMP. * The orientation is represented here as the output of * @e inv_orientation_matrix_to_scalar. * @param[in] orient Gyro and accel orientation in body frame. * @return 0 if successful. */ int dmp_set_orientation(unsigned short orient) { unsigned char gyro_regs[3], accel_regs[3]; const unsigned char gyro_axes[3] = {DINA4C, DINACD, DINA6C}; const unsigned char accel_axes[3] = {DINA0C, DINAC9, DINA2C}; const unsigned char gyro_sign[3] = {DINA36, DINA56, DINA76}; const unsigned char accel_sign[3] = {DINA26, DINA46, DINA66}; gyro_regs[0] = gyro_axes[orient & 3]; gyro_regs[1] = gyro_axes[(orient >> 3) & 3]; gyro_regs[2] = gyro_axes[(orient >> 6) & 3]; accel_regs[0] = accel_axes[orient & 3]; accel_regs[1] = accel_axes[(orient >> 3) & 3]; accel_regs[2] = accel_axes[(orient >> 6) & 3]; /* Chip-to-body, axes only. */ if (mpu_write_mem(FCFG_1, 3, gyro_regs)) return -1; if (mpu_write_mem(FCFG_2, 3, accel_regs)) return -1; memcpy(gyro_regs, gyro_sign, 3); memcpy(accel_regs, accel_sign, 3); if (orient & 4) { gyro_regs[0] |= 1; accel_regs[0] |= 1; } if (orient & 0x20) { gyro_regs[1] |= 1; accel_regs[1] |= 1; } if (orient & 0x100) { gyro_regs[2] |= 1; accel_regs[2] |= 1; } /* Chip-to-body, sign only. */ if (mpu_write_mem(FCFG_3, 3, gyro_regs)) return -1; if (mpu_write_mem(FCFG_7, 3, accel_regs)) return -1; dmp.orient = orient; return 0; } /** * @brief Push gyro biases to the DMP. * Because the gyro integration is handled in the DMP, any gyro biases * calculated by the MPL should be pushed down to DMP memory to remove * 3-axis quaternion drift. * \n NOTE: If the DMP-based gyro calibration is enabled, the DMP will * overwrite the biases written to this location once a new one is computed. * @param[in] bias Gyro biases in q16. * @return 0 if successful. */ int dmp_set_gyro_bias(long *bias) { long gyro_bias_body[3]; unsigned char regs[4]; gyro_bias_body[0] = bias[dmp.orient & 3]; if (dmp.orient & 4) gyro_bias_body[0] *= -1; gyro_bias_body[1] = bias[(dmp.orient >> 3) & 3]; if (dmp.orient & 0x20) gyro_bias_body[1] *= -1; gyro_bias_body[2] = bias[(dmp.orient >> 6) & 3]; if (dmp.orient & 0x100) gyro_bias_body[2] *= -1; #ifdef EMPL_NO_64BIT gyro_bias_body[0] = (long)(((float)gyro_bias_body[0] * GYRO_SF) / 1073741824.f); gyro_bias_body[1] = (long)(((float)gyro_bias_body[1] * GYRO_SF) / 1073741824.f); gyro_bias_body[2] = (long)(((float)gyro_bias_body[2] * GYRO_SF) / 1073741824.f); #else gyro_bias_body[0] = (long)(((long long)gyro_bias_body[0] * GYRO_SF) >> 30); gyro_bias_body[1] = (long)(((long long)gyro_bias_body[1] * GYRO_SF) >> 30); gyro_bias_body[2] = (long)(((long long)gyro_bias_body[2] * GYRO_SF) >> 30); #endif regs[0] = (unsigned char)((gyro_bias_body[0] >> 24) & 0xFF); regs[1] = (unsigned char)((gyro_bias_body[0] >> 16) & 0xFF); regs[2] = (unsigned char)((gyro_bias_body[0] >> 8) & 0xFF); regs[3] = (unsigned char)(gyro_bias_body[0] & 0xFF); if (mpu_write_mem(D_EXT_GYRO_BIAS_X, 4, regs)) return -1; regs[0] = (unsigned char)((gyro_bias_body[1] >> 24) & 0xFF); regs[1] = (unsigned char)((gyro_bias_body[1] >> 16) & 0xFF); regs[2] = (unsigned char)((gyro_bias_body[1] >> 8) & 0xFF); regs[3] = (unsigned char)(gyro_bias_body[1] & 0xFF); if (mpu_write_mem(D_EXT_GYRO_BIAS_Y, 4, regs)) return -1; regs[0] = (unsigned char)((gyro_bias_body[2] >> 24) & 0xFF); regs[1] = (unsigned char)((gyro_bias_body[2] >> 16) & 0xFF); regs[2] = (unsigned char)((gyro_bias_body[2] >> 8) & 0xFF); regs[3] = (unsigned char)(gyro_bias_body[2] & 0xFF); return mpu_write_mem(D_EXT_GYRO_BIAS_Z, 4, regs); } /** * @brief Push accel biases to the DMP. * These biases will be removed from the DMP 6-axis quaternion. * @param[in] bias Accel biases in q16. * @return 0 if successful. */ int dmp_set_accel_bias(long *bias) { long accel_bias_body[3]; unsigned char regs[12]; long long accel_sf; unsigned short accel_sens; mpu_get_accel_sens(&accel_sens); accel_sf = (long long)accel_sens << 15; __NOP(); accel_bias_body[0] = bias[dmp.orient & 3]; if (dmp.orient & 4) accel_bias_body[0] *= -1; accel_bias_body[1] = bias[(dmp.orient >> 3) & 3]; if (dmp.orient & 0x20) accel_bias_body[1] *= -1; accel_bias_body[2] = bias[(dmp.orient >> 6) & 3]; if (dmp.orient & 0x100) accel_bias_body[2] *= -1; #ifdef EMPL_NO_64BIT accel_bias_body[0] = (long)(((float)accel_bias_body[0] * accel_sf) / 1073741824.f); accel_bias_body[1] = (long)(((float)accel_bias_body[1] * accel_sf) / 1073741824.f); accel_bias_body[2] = (long)(((float)accel_bias_body[2] * accel_sf) / 1073741824.f); #else accel_bias_body[0] = (long)(((long long)accel_bias_body[0] * accel_sf) >> 30); accel_bias_body[1] = (long)(((long long)accel_bias_body[1] * accel_sf) >> 30); accel_bias_body[2] = (long)(((long long)accel_bias_body[2] * accel_sf) >> 30); #endif regs[0] = (unsigned char)((accel_bias_body[0] >> 24) & 0xFF); regs[1] = (unsigned char)((accel_bias_body[0] >> 16) & 0xFF); regs[2] = (unsigned char)((accel_bias_body[0] >> 8) & 0xFF); regs[3] = (unsigned char)(accel_bias_body[0] & 0xFF); regs[4] = (unsigned char)((accel_bias_body[1] >> 24) & 0xFF); regs[5] = (unsigned char)((accel_bias_body[1] >> 16) & 0xFF); regs[6] = (unsigned char)((accel_bias_body[1] >> 8) & 0xFF); regs[7] = (unsigned char)(accel_bias_body[1] & 0xFF); regs[8] = (unsigned char)((accel_bias_body[2] >> 24) & 0xFF); regs[9] = (unsigned char)((accel_bias_body[2] >> 16) & 0xFF); regs[10] = (unsigned char)((accel_bias_body[2] >> 8) & 0xFF); regs[11] = (unsigned char)(accel_bias_body[2] & 0xFF); return mpu_write_mem(D_ACCEL_BIAS, 12, regs); } /** * @brief Set DMP output rate. * Only used when DMP is on. * @param[in] rate Desired fifo rate (Hz). * @return 0 if successful. */ int dmp_set_fifo_rate(unsigned short rate) { const unsigned char regs_end[12] = {DINAFE, DINAF2, DINAAB, 0xc4, DINAAA, DINAF1, DINADF, DINADF, 0xBB, 0xAF, DINADF, DINADF}; unsigned short div; unsigned char tmp[8]; if (rate > DMP_SAMPLE_RATE) return -1; div = DMP_SAMPLE_RATE / rate - 1; tmp[0] = (unsigned char)((div >> 8) & 0xFF); tmp[1] = (unsigned char)(div & 0xFF); if (mpu_write_mem(D_0_22, 2, tmp)) return -1; if (mpu_write_mem(CFG_6, 12, (unsigned char*)regs_end)) return -1; dmp.fifo_rate = rate; return 0; } /** * @brief Get DMP output rate. * @param[out] rate Current fifo rate (Hz). * @return 0 if successful. */ int dmp_get_fifo_rate(unsigned short *rate) { rate[0] = dmp.fifo_rate; return 0; } /** * @brief Set tap threshold for a specific axis. * @param[in] axis 1, 2, and 4 for XYZ accel, respectively. * @param[in] thresh Tap threshold, in mg/ms. * @return 0 if successful. */ int dmp_set_tap_thresh(unsigned char axis, unsigned short thresh) { unsigned char tmp[4], accel_fsr; float scaled_thresh; unsigned short dmp_thresh, dmp_thresh_2; if (!(axis & TAP_XYZ) || thresh > 1600) return -1; scaled_thresh = (float)thresh / DMP_SAMPLE_RATE; mpu_get_accel_fsr(&accel_fsr); switch (accel_fsr) { case 2: dmp_thresh = (unsigned short)(scaled_thresh * 16384); /* dmp_thresh * 0.75 */ dmp_thresh_2 = (unsigned short)(scaled_thresh * 12288); break; case 4: dmp_thresh = (unsigned short)(scaled_thresh * 8192); /* dmp_thresh * 0.75 */ dmp_thresh_2 = (unsigned short)(scaled_thresh * 6144); break; case 8: dmp_thresh = (unsigned short)(scaled_thresh * 4096); /* dmp_thresh * 0.75 */ dmp_thresh_2 = (unsigned short)(scaled_thresh * 3072); break; case 16: dmp_thresh = (unsigned short)(scaled_thresh * 2048); /* dmp_thresh * 0.75 */ dmp_thresh_2 = (unsigned short)(scaled_thresh * 1536); break; default: return -1; } tmp[0] = (unsigned char)(dmp_thresh >> 8); tmp[1] = (unsigned char)(dmp_thresh & 0xFF); tmp[2] = (unsigned char)(dmp_thresh_2 >> 8); tmp[3] = (unsigned char)(dmp_thresh_2 & 0xFF); if (axis & TAP_X) { if (mpu_write_mem(DMP_TAP_THX, 2, tmp)) return -1; if (mpu_write_mem(D_1_36, 2, tmp+2)) return -1; } if (axis & TAP_Y) { if (mpu_write_mem(DMP_TAP_THY, 2, tmp)) return -1; if (mpu_write_mem(D_1_40, 2, tmp+2)) return -1; } if (axis & TAP_Z) { if (mpu_write_mem(DMP_TAP_THZ, 2, tmp)) return -1; if (mpu_write_mem(D_1_44, 2, tmp+2)) return -1; } return 0; } /** * @brief Set which axes will register a tap. * @param[in] axis 1, 2, and 4 for XYZ, respectively. * @return 0 if successful. */ int dmp_set_tap_axes(unsigned char axis) { unsigned char tmp = 0; if (axis & TAP_X) tmp |= 0x30; if (axis & TAP_Y) tmp |= 0x0C; if (axis & TAP_Z) tmp |= 0x03; return mpu_write_mem(D_1_72, 1, &tmp); } /** * @brief Set minimum number of taps needed for an interrupt. * @param[in] min_taps Minimum consecutive taps (1-4). * @return 0 if successful. */ int dmp_set_tap_count(unsigned char min_taps) { unsigned char tmp; if (min_taps < 1) min_taps = 1; else if (min_taps > 4) min_taps = 4; tmp = min_taps - 1; return mpu_write_mem(D_1_79, 1, &tmp); } /** * @brief Set length between valid taps. * @param[in] time Milliseconds between taps. * @return 0 if successful. */ int dmp_set_tap_time(unsigned short time) { unsigned short dmp_time; unsigned char tmp[2]; dmp_time = time / (1000 / DMP_SAMPLE_RATE); tmp[0] = (unsigned char)(dmp_time >> 8); tmp[1] = (unsigned char)(dmp_time & 0xFF); return mpu_write_mem(DMP_TAPW_MIN, 2, tmp); } /** * @brief Set max time between taps to register as a multi-tap. * @param[in] time Max milliseconds between taps. * @return 0 if successful. */ int dmp_set_tap_time_multi(unsigned short time) { unsigned short dmp_time; unsigned char tmp[2]; dmp_time = time / (1000 / DMP_SAMPLE_RATE); tmp[0] = (unsigned char)(dmp_time >> 8); tmp[1] = (unsigned char)(dmp_time & 0xFF); return mpu_write_mem(D_1_218, 2, tmp); } /** * @brief Set shake rejection threshold. * If the DMP detects a gyro sample larger than @e thresh, taps are rejected. * @param[in] sf Gyro scale factor. * @param[in] thresh Gyro threshold in dps. * @return 0 if successful. */ int dmp_set_shake_reject_thresh(long sf, unsigned short thresh) { unsigned char tmp[4]; long thresh_scaled = sf / 1000 * thresh; tmp[0] = (unsigned char)(((long)thresh_scaled >> 24) & 0xFF); tmp[1] = (unsigned char)(((long)thresh_scaled >> 16) & 0xFF); tmp[2] = (unsigned char)(((long)thresh_scaled >> 8) & 0xFF); tmp[3] = (unsigned char)((long)thresh_scaled & 0xFF); return mpu_write_mem(D_1_92, 4, tmp); } /** * @brief Set shake rejection time. * Sets the length of time that the gyro must be outside of the threshold set * by @e gyro_set_shake_reject_thresh before taps are rejected. A mandatory * 60 ms is added to this parameter. * @param[in] time Time in milliseconds. * @return 0 if successful. */ int dmp_set_shake_reject_time(unsigned short time) { unsigned char tmp[2]; time /= (1000 / DMP_SAMPLE_RATE); tmp[0] = time >> 8; tmp[1] = time & 0xFF; return mpu_write_mem(D_1_90,2,tmp); } /** * @brief Set shake rejection timeout. * Sets the length of time after a shake rejection that the gyro must stay * inside of the threshold before taps can be detected again. A mandatory * 60 ms is added to this parameter. * @param[in] time Time in milliseconds. * @return 0 if successful. */ int dmp_set_shake_reject_timeout(unsigned short time) { unsigned char tmp[2]; time /= (1000 / DMP_SAMPLE_RATE); tmp[0] = time >> 8; tmp[1] = time & 0xFF; return mpu_write_mem(D_1_88,2,tmp); } /** * @brief Get current step count. * @param[out] count Number of steps detected. * @return 0 if successful. */ int dmp_get_pedometer_step_count(unsigned long *count) { unsigned char tmp[4]; if (!count) return -1; if (mpu_read_mem(D_PEDSTD_STEPCTR, 4, tmp)) return -1; count[0] = ((unsigned long)tmp[0] << 24) | ((unsigned long)tmp[1] << 16) | ((unsigned long)tmp[2] << 8) | tmp[3]; return 0; } /** * @brief Overwrite current step count. * WARNING: This function writes to DMP memory and could potentially encounter * a race condition if called while the pedometer is enabled. * @param[in] count New step count. * @return 0 if successful. */ int dmp_set_pedometer_step_count(unsigned long count) { unsigned char tmp[4]; tmp[0] = (unsigned char)((count >> 24) & 0xFF); tmp[1] = (unsigned char)((count >> 16) & 0xFF); tmp[2] = (unsigned char)((count >> 8) & 0xFF); tmp[3] = (unsigned char)(count & 0xFF); return mpu_write_mem(D_PEDSTD_STEPCTR, 4, tmp); } /** * @brief Get duration of walking time. * @param[in] time Walk time in milliseconds. * @return 0 if successful. */ int dmp_get_pedometer_walk_time(unsigned long *time) { unsigned char tmp[4]; if (!time) return -1; if (mpu_read_mem(D_PEDSTD_TIMECTR, 4, tmp)) return -1; time[0] = (((unsigned long)tmp[0] << 24) | ((unsigned long)tmp[1] << 16) | ((unsigned long)tmp[2] << 8) | tmp[3]) * 20; return 0; } /** * @brief Overwrite current walk time. * WARNING: This function writes to DMP memory and could potentially encounter * a race condition if called while the pedometer is enabled. * @param[in] time New walk time in milliseconds. */ int dmp_set_pedometer_walk_time(unsigned long time) { unsigned char tmp[4]; time /= 20; tmp[0] = (unsigned char)((time >> 24) & 0xFF); tmp[1] = (unsigned char)((time >> 16) & 0xFF); tmp[2] = (unsigned char)((time >> 8) & 0xFF); tmp[3] = (unsigned char)(time & 0xFF); return mpu_write_mem(D_PEDSTD_TIMECTR, 4, tmp); } /** * @brief Enable DMP features. * The following \#define's are used in the input mask: * \n DMP_FEATURE_TAP * \n DMP_FEATURE_ANDROID_ORIENT * \n DMP_FEATURE_LP_QUAT * \n DMP_FEATURE_6X_LP_QUAT * \n DMP_FEATURE_GYRO_CAL * \n DMP_FEATURE_SEND_RAW_ACCEL * \n DMP_FEATURE_SEND_RAW_GYRO * \n NOTE: DMP_FEATURE_LP_QUAT and DMP_FEATURE_6X_LP_QUAT are mutually * exclusive. * \n NOTE: DMP_FEATURE_SEND_RAW_GYRO and DMP_FEATURE_SEND_CAL_GYRO are also * mutually exclusive. * @param[in] mask Mask of features to enable. * @return 0 if successful. */ int dmp_enable_feature(unsigned short mask) { unsigned char tmp[10]; /* TODO: All of these settings can probably be integrated into the default * DMP image. */ /* Set integration scale factor. */ tmp[0] = (unsigned char)((GYRO_SF >> 24) & 0xFF); tmp[1] = (unsigned char)((GYRO_SF >> 16) & 0xFF); tmp[2] = (unsigned char)((GYRO_SF >> 8) & 0xFF); tmp[3] = (unsigned char)(GYRO_SF & 0xFF); mpu_write_mem(D_0_104, 4, tmp); /* Send sensor data to the FIFO. */ tmp[0] = 0xA3; if (mask & DMP_FEATURE_SEND_RAW_ACCEL) { tmp[1] = 0xC0; tmp[2] = 0xC8; tmp[3] = 0xC2; } else { tmp[1] = 0xA3; tmp[2] = 0xA3; tmp[3] = 0xA3; } if (mask & DMP_FEATURE_SEND_ANY_GYRO) { tmp[4] = 0xC4; tmp[5] = 0xCC; tmp[6] = 0xC6; } else { tmp[4] = 0xA3; tmp[5] = 0xA3; tmp[6] = 0xA3; } tmp[7] = 0xA3; tmp[8] = 0xA3; tmp[9] = 0xA3; mpu_write_mem(CFG_15,10,tmp); /* Send gesture data to the FIFO. */ if (mask & (DMP_FEATURE_TAP | DMP_FEATURE_ANDROID_ORIENT)) tmp[0] = DINA20; else tmp[0] = 0xD8; mpu_write_mem(CFG_27,1,tmp); if (mask & DMP_FEATURE_GYRO_CAL) dmp_enable_gyro_cal(1); else dmp_enable_gyro_cal(0); if (mask & DMP_FEATURE_SEND_ANY_GYRO) { if (mask & DMP_FEATURE_SEND_CAL_GYRO) { tmp[0] = 0xB2; tmp[1] = 0x8B; tmp[2] = 0xB6; tmp[3] = 0x9B; } else { tmp[0] = DINAC0; tmp[1] = DINA80; tmp[2] = DINAC2; tmp[3] = DINA90; } mpu_write_mem(CFG_GYRO_RAW_DATA, 4, tmp); } if (mask & DMP_FEATURE_TAP) { /* Enable tap. */ tmp[0] = 0xF8; mpu_write_mem(CFG_20, 1, tmp); dmp_set_tap_thresh(TAP_XYZ, 250); dmp_set_tap_axes(TAP_XYZ); dmp_set_tap_count(1); dmp_set_tap_time(100); dmp_set_tap_time_multi(500); dmp_set_shake_reject_thresh(GYRO_SF, 200); dmp_set_shake_reject_time(40); dmp_set_shake_reject_timeout(10); } else { tmp[0] = 0xD8; mpu_write_mem(CFG_20, 1, tmp); } if (mask & DMP_FEATURE_ANDROID_ORIENT) { tmp[0] = 0xD9; } else tmp[0] = 0xD8; mpu_write_mem(CFG_ANDROID_ORIENT_INT, 1, tmp); if (mask & DMP_FEATURE_LP_QUAT) dmp_enable_lp_quat(1); else dmp_enable_lp_quat(0); if (mask & DMP_FEATURE_6X_LP_QUAT) dmp_enable_6x_lp_quat(1); else dmp_enable_6x_lp_quat(0); /* Pedometer is always enabled. */ dmp.feature_mask = mask | DMP_FEATURE_PEDOMETER; mpu_reset_fifo(); dmp.packet_length = 0; if (mask & DMP_FEATURE_SEND_RAW_ACCEL) dmp.packet_length += 6; if (mask & DMP_FEATURE_SEND_ANY_GYRO) dmp.packet_length += 6; if (mask & (DMP_FEATURE_LP_QUAT | DMP_FEATURE_6X_LP_QUAT)) dmp.packet_length += 16; if (mask & (DMP_FEATURE_TAP | DMP_FEATURE_ANDROID_ORIENT)) dmp.packet_length += 4; return 0; } /** * @brief Get list of currently enabled DMP features. * @param[out] Mask of enabled features. * @return 0 if successful. */ int dmp_get_enabled_features(unsigned short *mask) { mask[0] = dmp.feature_mask; return 0; } /** * @brief Calibrate the gyro data in the DMP. * After eight seconds of no motion, the DMP will compute gyro biases and * subtract them from the quaternion output. If @e dmp_enable_feature is * called with @e DMP_FEATURE_SEND_CAL_GYRO, the biases will also be * subtracted from the gyro output. * @param[in] enable 1 to enable gyro calibration. * @return 0 if successful. */ int dmp_enable_gyro_cal(unsigned char enable) { if (enable) { unsigned char regs[9] = {0xb8, 0xaa, 0xb3, 0x8d, 0xb4, 0x98, 0x0d, 0x35, 0x5d}; return mpu_write_mem(CFG_MOTION_BIAS, 9, regs); } else { unsigned char regs[9] = {0xb8, 0xaa, 0xaa, 0xaa, 0xb0, 0x88, 0xc3, 0xc5, 0xc7}; return mpu_write_mem(CFG_MOTION_BIAS, 9, regs); } } /** * @brief Generate 3-axis quaternions from the DMP. * In this driver, the 3-axis and 6-axis DMP quaternion features are mutually * exclusive. * @param[in] enable 1 to enable 3-axis quaternion. * @return 0 if successful. */ int dmp_enable_lp_quat(unsigned char enable) { unsigned char regs[4]; if (enable) { regs[0] = DINBC0; regs[1] = DINBC2; regs[2] = DINBC4; regs[3] = DINBC6; } else memset(regs, 0x8B, 4); mpu_write_mem(CFG_LP_QUAT, 4, regs); return mpu_reset_fifo(); } /** * @brief Generate 6-axis quaternions from the DMP. * In this driver, the 3-axis and 6-axis DMP quaternion features are mutually * exclusive. * @param[in] enable 1 to enable 6-axis quaternion. * @return 0 if successful. */ int dmp_enable_6x_lp_quat(unsigned char enable) { unsigned char regs[4]; if (enable) { regs[0] = DINA20; regs[1] = DINA28; regs[2] = DINA30; regs[3] = DINA38; } else memset(regs, 0xA3, 4); mpu_write_mem(CFG_8, 4, regs); return mpu_reset_fifo(); } /** * @brief Decode the four-byte gesture data and execute any callbacks. * @param[in] gesture Gesture data from DMP packet. * @return 0 if successful. */ static int decode_gesture(unsigned char *gesture) { unsigned char tap, android_orient; android_orient = gesture[3] & 0xC0; tap = 0x3F & gesture[3]; if (gesture[1] & INT_SRC_TAP) { unsigned char direction, count; direction = tap >> 3; count = (tap % 8) + 1; if (dmp.tap_cb) dmp.tap_cb(direction, count); } if (gesture[1] & INT_SRC_ANDROID_ORIENT) { if (dmp.android_orient_cb) dmp.android_orient_cb(android_orient >> 6); } return 0; } /** * @brief Specify when a DMP interrupt should occur. * A DMP interrupt can be configured to trigger on either of the two * conditions below: * \n a. One FIFO period has elapsed (set by @e mpu_set_sample_rate). * \n b. A tap event has been detected. * @param[in] mode DMP_INT_GESTURE or DMP_INT_CONTINUOUS. * @return 0 if successful. */ int dmp_set_interrupt_mode(unsigned char mode) { const unsigned char regs_continuous[11] = {0xd8, 0xb1, 0xb9, 0xf3, 0x8b, 0xa3, 0x91, 0xb6, 0x09, 0xb4, 0xd9}; const unsigned char regs_gesture[11] = {0xda, 0xb1, 0xb9, 0xf3, 0x8b, 0xa3, 0x91, 0xb6, 0xda, 0xb4, 0xda}; switch (mode) { case DMP_INT_CONTINUOUS: return mpu_write_mem(CFG_FIFO_ON_EVENT, 11, (unsigned char*)regs_continuous); case DMP_INT_GESTURE: return mpu_write_mem(CFG_FIFO_ON_EVENT, 11, (unsigned char*)regs_gesture); default: return -1; } } /** * @brief Get one packet from the FIFO. * If @e sensors does not contain a particular sensor, disregard the data * returned to that pointer. * \n @e sensors can contain a combination of the following flags: * \n INV_X_GYRO, INV_Y_GYRO, INV_Z_GYRO * \n INV_XYZ_GYRO * \n INV_XYZ_ACCEL * \n INV_WXYZ_QUAT * \n If the FIFO has no new data, @e sensors will be zero. * \n If the FIFO is disabled, @e sensors will be zero and this function will * return a non-zero error code. * @param[out] gyro Gyro data in hardware units. * @param[out] accel Accel data in hardware units. * @param[out] quat 3-axis quaternion data in hardware units. * @param[out] timestamp Timestamp in milliseconds. * @param[out] sensors Mask of sensors read from FIFO. * @param[out] more Number of remaining packets. * @return 0 if successful. */ int dmp_read_fifo(short *gyro, short *accel, long *quat, unsigned long *timestamp, short *sensors, unsigned char *more) { unsigned char fifo_data[MAX_PACKET_LENGTH]; unsigned char ii = 0; /* TODO: sensors[0] only changes when dmp_enable_feature is called. We can * cache this value and save some cycles. */ sensors[0] = 0; /* Get a packet. */ if (mpu_read_fifo_stream(dmp.packet_length, fifo_data, more)) return -1; /* Parse DMP packet. */ if (dmp.feature_mask & (DMP_FEATURE_LP_QUAT | DMP_FEATURE_6X_LP_QUAT)) { #ifdef FIFO_CORRUPTION_CHECK long quat_q14[4], quat_mag_sq; #endif quat[0] = ((long)fifo_data[0] << 24) | ((long)fifo_data[1] << 16) | ((long)fifo_data[2] << 8) | fifo_data[3]; quat[1] = ((long)fifo_data[4] << 24) | ((long)fifo_data[5] << 16) | ((long)fifo_data[6] << 8) | fifo_data[7]; quat[2] = ((long)fifo_data[8] << 24) | ((long)fifo_data[9] << 16) | ((long)fifo_data[10] << 8) | fifo_data[11]; quat[3] = ((long)fifo_data[12] << 24) | ((long)fifo_data[13] << 16) | ((long)fifo_data[14] << 8) | fifo_data[15]; ii += 16; #ifdef FIFO_CORRUPTION_CHECK /* We can detect a corrupted FIFO by monitoring the quaternion data and * ensuring that the magnitude is always normalized to one. This * shouldn't happen in normal operation, but if an I2C error occurs, * the FIFO reads might become misaligned. * * Let's start by scaling down the quaternion data to avoid long long * math. */ quat_q14[0] = quat[0] >> 16; quat_q14[1] = quat[1] >> 16; quat_q14[2] = quat[2] >> 16; quat_q14[3] = quat[3] >> 16; quat_mag_sq = quat_q14[0] * quat_q14[0] + quat_q14[1] * quat_q14[1] + quat_q14[2] * quat_q14[2] + quat_q14[3] * quat_q14[3]; if ((quat_mag_sq < QUAT_MAG_SQ_MIN) || (quat_mag_sq > QUAT_MAG_SQ_MAX)) { /* Quaternion is outside of the acceptable threshold. */ mpu_reset_fifo(); sensors[0] = 0; return -1; } sensors[0] |= INV_WXYZ_QUAT; #endif } if (dmp.feature_mask & DMP_FEATURE_SEND_RAW_ACCEL) { accel[0] = ((short)fifo_data[ii+0] << 8) | fifo_data[ii+1]; accel[1] = ((short)fifo_data[ii+2] << 8) | fifo_data[ii+3]; accel[2] = ((short)fifo_data[ii+4] << 8) | fifo_data[ii+5]; ii += 6; sensors[0] |= INV_XYZ_ACCEL; } if (dmp.feature_mask & DMP_FEATURE_SEND_ANY_GYRO) { gyro[0] = ((short)fifo_data[ii+0] << 8) | fifo_data[ii+1]; gyro[1] = ((short)fifo_data[ii+2] << 8) | fifo_data[ii+3]; gyro[2] = ((short)fifo_data[ii+4] << 8) | fifo_data[ii+5]; ii += 6; sensors[0] |= INV_XYZ_GYRO; } /* Gesture data is at the end of the DMP packet. Parse it and call * the gesture callbacks (if registered). */ if (dmp.feature_mask & (DMP_FEATURE_TAP | DMP_FEATURE_ANDROID_ORIENT)) decode_gesture(fifo_data + ii); get_ms(timestamp); return 0; } /** * @brief Register a function to be executed on a tap event. * The tap direction is represented by one of the following: * \n TAP_X_UP * \n TAP_X_DOWN * \n TAP_Y_UP * \n TAP_Y_DOWN * \n TAP_Z_UP * \n TAP_Z_DOWN * @param[in] func Callback function. * @return 0 if successful. */ int dmp_register_tap_cb(void (*func)(unsigned char, unsigned char)) { dmp.tap_cb = func; return 0; } /** * @brief Register a function to be executed on a android orientation event. * @param[in] func Callback function. * @return 0 if successful. */ int dmp_register_android_orient_cb(void (*func)(unsigned char)) { dmp.android_orient_cb = func; return 0; } /** * @} */ ================================================ FILE: Libraries/eMPL/inv_mpu_dmp_motion_driver.h ================================================ /* $License: Copyright (C) 2011-2012 InvenSense Corporation, All Rights Reserved. See included License.txt for License information. $ */ /** * @addtogroup DRIVERS Sensor Driver Layer * @brief Hardware drivers to communicate with sensors via I2C. * * @{ * @file inv_mpu_dmp_motion_driver.h * @brief DMP image and interface functions. * @details All functions are preceded by the dmp_ prefix to * differentiate among MPL and general driver function calls. */ #ifndef _INV_MPU_DMP_MOTION_DRIVER_H_ #define _INV_MPU_DMP_MOTION_DRIVER_H_ #define TAP_X (0x01) #define TAP_Y (0x02) #define TAP_Z (0x04) #define TAP_XYZ (0x07) #define TAP_X_UP (0x01) #define TAP_X_DOWN (0x02) #define TAP_Y_UP (0x03) #define TAP_Y_DOWN (0x04) #define TAP_Z_UP (0x05) #define TAP_Z_DOWN (0x06) #define ANDROID_ORIENT_PORTRAIT (0x00) #define ANDROID_ORIENT_LANDSCAPE (0x01) #define ANDROID_ORIENT_REVERSE_PORTRAIT (0x02) #define ANDROID_ORIENT_REVERSE_LANDSCAPE (0x03) #define DMP_INT_GESTURE (0x01) #define DMP_INT_CONTINUOUS (0x02) #define DMP_FEATURE_TAP (0x001) #define DMP_FEATURE_ANDROID_ORIENT (0x002) #define DMP_FEATURE_LP_QUAT (0x004) #define DMP_FEATURE_PEDOMETER (0x008) #define DMP_FEATURE_6X_LP_QUAT (0x010) #define DMP_FEATURE_GYRO_CAL (0x020) #define DMP_FEATURE_SEND_RAW_ACCEL (0x040) #define DMP_FEATURE_SEND_RAW_GYRO (0x080) #define DMP_FEATURE_SEND_CAL_GYRO (0x100) #define INV_WXYZ_QUAT (0x100) /* Set up functions. */ int dmp_load_motion_driver_firmware(void); int dmp_set_fifo_rate(unsigned short rate); int dmp_get_fifo_rate(unsigned short *rate); int dmp_enable_feature(unsigned short mask); int dmp_get_enabled_features(unsigned short *mask); int dmp_set_interrupt_mode(unsigned char mode); int dmp_set_orientation(unsigned short orient); int dmp_set_gyro_bias(long *bias); int dmp_set_accel_bias(long *bias); /* Tap functions. */ int dmp_register_tap_cb(void (*func)(unsigned char, unsigned char)); int dmp_set_tap_thresh(unsigned char axis, unsigned short thresh); int dmp_set_tap_axes(unsigned char axis); int dmp_set_tap_count(unsigned char min_taps); int dmp_set_tap_time(unsigned short time); int dmp_set_tap_time_multi(unsigned short time); int dmp_set_shake_reject_thresh(long sf, unsigned short thresh); int dmp_set_shake_reject_time(unsigned short time); int dmp_set_shake_reject_timeout(unsigned short time); /* Android orientation functions. */ int dmp_register_android_orient_cb(void (*func)(unsigned char)); /* LP quaternion functions. */ int dmp_enable_lp_quat(unsigned char enable); int dmp_enable_6x_lp_quat(unsigned char enable); /* Pedometer functions. */ int dmp_get_pedometer_step_count(unsigned long *count); int dmp_set_pedometer_step_count(unsigned long count); int dmp_get_pedometer_walk_time(unsigned long *time); int dmp_set_pedometer_walk_time(unsigned long time); /* DMP gyro calibration functions. */ int dmp_enable_gyro_cal(unsigned char enable); /* Read function. This function should be called whenever the MPU interrupt is * detected. */ int dmp_read_fifo(short *gyro, short *accel, long *quat, unsigned long *timestamp, short *sensors, unsigned char *more); #endif /* #ifndef _INV_MPU_DMP_MOTION_DRIVER_H_ */ ================================================ FILE: Math/inc/FastMath.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _FASTMATH_H_ #define _FASTMATH_H_ #include "Double.h" #define ROOT_HALF (0.70710678118654752440084436210485f) #define LOGA_COEF0 (-4.649062303464e-1f) #define LOGA_COEF1 (+1.360095468621e-2f) #define LOGB_COEF0 (-5.578873750242f) #define LOGDA_COEF0 (-6.4124943423745581147e1f) #define LOGDA_COEF1 (+1.6383943563021534222e1f) #define LOGDA_COEF2 (-7.8956112887491257267e-1f) #define LOGDB_COEF0 (-7.6949932108494879777e2f) #define LOGDB_COEF1 (+3.1203222091924532844e2f) #define LOGDB_COEF2 (-3.5667977739034646171e1f) #define LN2_DC1 (0.693359375f) #define LN2_DC2 (-2.121944400e-4f) #define LN2_DC3 (-5.46905827678e-14f) float FastLn(float x); ////////////////////////////////////////////////////////////////////////// ///Coefficients used for pow #define POWP_COEF1 (+8.33333286245e-2f) #define POWP_COEF2 (+1.25064850052e-2f) #define POWQ_COEF1 (+6.93147180556341e-1f) #define POWQ_COEF2 (+2.40226506144710e-1f) #define POWQ_COEF3 (+5.55040488130765e-2f) #define POWQ_COEF4 (+9.61620659583789e-3f) #define POWQ_COEF5 (+1.30525515942810e-3f) #define POW_BIGNUM (+2046.0f) #define POW_SMALLNUM (-2015.0f) #define LOG2E_MINUS1 (0.44269504088896340735992468100189f) // #define FLT_EPSILON 1.1920928955078125E-07F #define FLT_MAX 3.4028234663852886E+38F // float FastPow(float x,float y); ////////////////////////////////////////////////////////////////////////// // #define X_MAX (+9.099024257348e3f) #define INV_PI_2 ( 0.63661977236758134307553505349006f) #define PI_2_C1 ( 1.5703125f) #define PI_2_C2 ( 4.84466552734375e-4f) #define PI_2_C3 (-6.39757837755768678308360248557e-7f) #define TANP_COEF1 (-1.113614403566e-1f) #define TANP_COEF2 (+1.075154738488e-3f) #define TANQ_COEF0 (+1.000000000000f) #define TANQ_COEF1 (-4.446947720281e-1f) #define TANQ_COEF2 (+1.597339213300e-2f) float FastTan(float x); ////////////////////////////////////////////////////////////////////////// #define _2_PI 6.283185307179586476925286766559f #define RADTODEG(x) ((x) * 57.295779513082320876798154814105f) #define DEGTORAD(x) ((x) * 0.01745329251994329576923690768489f) //translate from the DSP instruction of a DSP Library. #ifndef PI #define PI (3.1415926535897932384626433832795f) #endif #define PI_2 (1.5707963267948966192313216916398f) #define PI_3 (1.0471975511965977461542144610932f) #define PI_4 (0.78539816339744830961566084581988f) #define PI_6 (0.52359877559829887307710723054658f) #define TWO_MINUS_ROOT3 (0.26794919243112270647255365849413f) #define SQRT3_MINUS_1 (0.73205080756887729352744634150587f) #define SQRT3 (1.7320508075688772935274463415059f) #define EPS_FLOAT (+3.452669830012e-4f) //Coefficients used for atan/atan2 #define ATANP_COEF0 (-1.44008344874f) #define ATANP_COEF1 (-7.20026848898e-1f) #define ATANQ_COEF0 (+4.32025038919f) #define ATANQ_COEF1 (+4.75222584599f) //Coefficients used for asin/acos #define ASINP_COEF1 (-2.7516555290596f) #define ASINP_COEF2 (+2.9058762374859f) #define ASINP_COEF3 (-5.9450144193246e-1f) #define ASINQ_COEF0 (-1.6509933202424e+1f) #define ASINQ_COEF1 (+2.4864728969164e+1f) #define ASINQ_COEF2 (-1.0333867072113e+1f) float FastAsin(float x); float FastAtan2(float y, float x); float FastSqrtI(float x); float FastSqrt(float x); float FastSin(float x); float FastCos(float x); void FastSinCos(float x, float *sinVal, float *cosVal); __inline float FastAbs(float x){ union { unsigned int i; float f;} y; y.f = x; y.i = y.i & 0x7FFFFFFF; return (float)y.f; } __inline double FastAbsD(double x){ union { unsigned __int64 i; double d;} y; y.d = x; y.i = y.i & 0x7FFFFFFFFFFFFFFFLL; return (double)y.d; } ////////////////////////////////////////////////////////////////////////// Double FastSqrtID(Double dx); Double FastSqrtD(Double dx); #endif ================================================ FILE: Math/src/FastMath.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "FastMath.h" //translate from ADI's dsp library. ////////////////////////////////////////////////////////////////////////// //Get fraction and integer parts of floating point float Modf(float x, float *i) { float y; float fract; y = x; if (x < (float)0.0){ y = -y; } if (y >= (float)16777216.0f){ *i = x; return (float)0.0f; } if (y < (float)1.0f){ *i = (float)0.0f; return x; } y = (float)((long)(y)); if (x < (float)0.0f){ y = -y; } fract = x - y; *i = y; return fract; } float FastPow(float x,float y) { float tmp; float znum, zden, result; float g, r, u1, u2, v, z; long m, p, negate, y_int, n; long mi, pi, iw1; float y1, y2, w1, w2, w; float *a1, *a2; float xtmp; long *lPtr = (long *)&xtmp; float *fPtr = &xtmp; static const long a1l[] = {0, /* 0.0 */ 0x3f800000, /* 1.0 */ 0x3f75257d, /* 0.9576032757759 */ 0x3f6ac0c6, /* 0.9170039892197 */ 0x3f60ccde, /* 0.8781260251999 */ 0x3f5744fc, /* 0.8408963680267 */ 0x3f4e248c, /* 0.8052451610565 */ 0x3f45672a, /* 0.7711054086685 */ 0x3f3d08a3, /* 0.7384130358696 */ 0x3f3504f3, /* 0.7071067690849 */ 0x3f2d583e, /* 0.6771277189255 */ 0x3f25fed6, /* 0.6484197378159 */ 0x3f1ef532, /* 0.6209288835526 */ 0x3f1837f0, /* 0.5946035385132 */ 0x3f11c3d3, /* 0.5693942904472 */ 0x3f0b95c1, /* 0.5452538132668 */ 0x3f05aac3, /* 0.5221368670464 */ 0x3f000000}; /* 0.5 */ static const long a2l[] = {0, /* 0.0 */ 0x31a92436, /* 4.922664054163e-9 */ 0x336c2a94, /* 5.498675648141e-8 */ 0x31a8fc24, /* 4.918108587049e-9 */ 0x331f580c, /* 3.710015050729e-8 */ 0x336a42a1, /* 5.454296925222e-8 */ 0x32c12342, /* 2.248419050943e-8 */ 0x32e75623, /* 2.693110978669e-8 */ 0x32cf9890}; /* 2.41673490109e-8 */ a1 = (float *)a1l; a2 = (float *)a2l; negate = 0; if (x == (float)0.0){ if (y == (float)0.0){ return (float)1.0; } else if (y > (float)0.0){ return (float)0.0; } else{ return (float)FLT_MAX; } } else if (x < (float)0.0){ y_int = (long)(y); if ((float)(y_int) != y){ return (float)0.0; } x = -x; negate = y_int & 0x1; } xtmp = x; m = (*lPtr >> 23); m = m - 126; *lPtr = (*lPtr & 0x807fffff) | (126 << 23); g = *fPtr; p = 1; if (g <= a1[9]){ p = 9; } if (g <= a1[p + 4]){ p = p + 4; } if (g <= a1[p + 2]){ p = p + 2; } p = p + 1; znum = g - a1[p]; znum = znum - a2[p >> 1]; zden = g + a1[p]; p = p - 1; z = znum / zden; z = z + z; v = z * z; r = POWP_COEF2 * v; r = r + POWP_COEF1; r = r * v; r = r * z; r = r + LOG2E_MINUS1 * r; u2 = LOG2E_MINUS1 * z; u2 = r + u2; u2 = u2 + z; u1 = (float)((m * 16) - p); u1 = u1 * 0.0625f; Modf(16.0f * y, &(y1)); y1 = y1 * 0.0625f; y2 = y - y1; w = u1 * y2; tmp = u2 * y; w = tmp + w; Modf(16.0f * w, &(w1)); w1 = w1 * 0.0625f; w2 = w - w1; w = u1 * y1; w = w + w1; Modf(16.0f * w, &(w1)); w1 = w1 * 0.0625f; tmp = w - w1; w2 = w2 + tmp; Modf(16.0f * w2, &(w)); w = w * 0.0625f; tmp = w1 + w; tmp = 16.0f * tmp; iw1 = (long)(tmp); w2 = w2 - w; if (iw1 > POW_BIGNUM){ result = (float)FLT_MAX; if (negate == 1){ result = -result; } return result; } if (w2 > 0){ w2 = w2 - 0.0625f; iw1++; } if (iw1 < POW_SMALLNUM){ return (float)0.0; } if (iw1 < 0){ mi = 0; } else{ mi = 1; } n = iw1 / 16; mi = mi + n; pi = (mi * 16) - iw1; z = POWQ_COEF5 * w2; z = z + POWQ_COEF4; z = z * w2; z = z + POWQ_COEF3; z = z * w2; z = z + POWQ_COEF2; z = z * w2; z = z + POWQ_COEF1; z = z * w2; z = z * a1[pi + 1]; z = a1[pi + 1] + z; fPtr = &z; lPtr = (long *)fPtr; n = (*lPtr >> 23) & 0xff; n = n - 127; mi = mi + n; mi = mi + 127; mi = mi & 0xff; *lPtr = *lPtr & (0x807fffff); *lPtr = *lPtr | mi << 23; result = *fPtr; if (negate){ result = -result; } return result; } // float FastTan(float x) { long n; float xn; float f, g; float x_int, x_fract; float result; float xnum, xden; if ((x > (float)X_MAX) || (x < (float)-X_MAX)){ return (float)0.0; } x_int = (float)((long)(x)); x_fract = x - x_int; g = (float)0.5; if (x <= (float)0.0){ g = -g; } n = (long)(x * (float)INV_PI_2 + g); xn = (float)(n); f = x_int - xn * PI_2_C1; f = f + x_fract; f = f - xn * PI_2_C2; f = f - xn * PI_2_C3; if (f < (float)0.0){ g = -f; } else{ g = f; } if (g < (float)EPS_FLOAT){ if (n & 0x0001){ result = -1.0f / f; } else{ result = f; } return result; } g = f * f; xnum = g * TANP_COEF2; xnum = xnum + TANP_COEF1; xnum = xnum * g; xnum = xnum * f; xnum = xnum + f; xden = g * TANQ_COEF2; xden = xden + TANQ_COEF1; xden = xden * g; xden = xden + TANQ_COEF0; if (n & 0x0001){ result = xnum; xnum = -xden; xden = result; } result = xnum / xden; return result; } // float FastLn(float x) { union { unsigned int i; float f;} e; float xn; float z; float w; float a; float b; float r; float result; float znum, zden; int exponent = (*((int*)&x) & 0x7F800000) >> 23; e.i = (*((int*)&x) & 0x3F800000); if(e.f > ROOT_HALF){ znum = e.f - 1.0f; zden = e.f * 0.5f + 0.5f; } else{ exponent -= 1; znum = e.f - 0.5f; zden = e.f * 0.5f + 0.5f; } xn = (float)exponent; z = znum / zden; w = z * z; a = (LOGDA_COEF2 * w + LOGDA_COEF1) * w + LOGDA_COEF0; b = ((w + LOGDB_COEF2) * w + LOGDB_COEF1) * w + LOGDB_COEF0; r = a / b * w * z + z; result = xn * LN2_DC1 + r; r = xn * LN2_DC2; result += r; r = xn * LN2_DC3; result += r; return result; } float FastAsin(float x) { float y, g; float num, den, result; long i; float sign = 1.0; y = x; if (y < (float)0.0){ y = -y; sign = -sign; } if (y > (float)0.5){ i = 1; if (y > (float)1.0){ result = 0.0; return result; } g = (1.0f - y) * 0.5f; y = -2.0f * FastSqrt(g); } else{ i = 0; if (y < (float)EPS_FLOAT){ result = y; if (sign < (float)0.0){ result = -result; } return result; } g = y * y; } num = ((ASINP_COEF3 * g + ASINP_COEF2) * g + ASINP_COEF1) * g; den = ((g + ASINQ_COEF2) * g + ASINQ_COEF1) * g + ASINQ_COEF0; result = num / den; result = result * y + y; if (i == 1){ result = result + (float)PI_2; } if (sign < (float)0.0){ result = -result; } return result; } float FastAtan2(float y, float x) { float f, g; float num, den; float result; int n; static const float a[4] = {0, (float)PI_6, (float)PI_2, (float)PI_3}; if (x == (float)0.0){ if (y == (float)0.0){ result = 0.0; return result; } result = (float)PI_2; if (y > (float)0.0){ return result; } if (y < (float)0.0){ result = -result; return result; } } n = 0; num = y; den = x; if (num < (float)0.0){ num = -num; } if (den < (float)0.0){ den = -den; } if (num > den){ f = den; den = num; num = f; n = 2; } f = num / den; if (f > (float)TWO_MINUS_ROOT3){ num = f * (float)SQRT3_MINUS_1 - 1.0f + f; den = (float)SQRT3 + f; f = num / den; n = n + 1; } g = f; if (g < (float)0.0){ g = -g; } if (g < (float)EPS_FLOAT){ result = f; } else{ g = f * f; num = (ATANP_COEF1 * g + ATANP_COEF0) * g; den = (g + ATANQ_COEF1) * g + ATANQ_COEF0; result = num / den; result = result * f + f; } if (n > 1){ result = -result; } result = result + a[n]; if (x < (float)0.0){ result = PI - result; } if (y < (float)0.0){ result = -result; } return result; } // Quake inverse square root float FastSqrtI(float x) { ////////////////////////////////////////////////////////////////////////// //less accuracy, more faster /* L2F l2f; float xhalf = 0.5f * x; l2f.f = x; l2f.i = 0x5f3759df - (l2f.i >> 1); x = l2f.f * (1.5f - xhalf * l2f.f * l2f.f); return x; */ ////////////////////////////////////////////////////////////////////////// union { unsigned int i; float f;} l2f; l2f.f = x; l2f.i = 0x5F1F1412 - (l2f.i >> 1); return l2f.f * (1.69000231f - 0.714158168f * x * l2f.f * l2f.f); } float FastSqrt(float x) { return x * FastSqrtI(x); } #define FAST_SIN_TABLE_SIZE 512 const float sinTable[FAST_SIN_TABLE_SIZE + 1] = { 0.00000000f, 0.01227154f, 0.02454123f, 0.03680722f, 0.04906767f, 0.06132074f, 0.07356456f, 0.08579731f, 0.09801714f, 0.11022221f, 0.12241068f, 0.13458071f, 0.14673047f, 0.15885814f, 0.17096189f, 0.18303989f, 0.19509032f, 0.20711138f, 0.21910124f, 0.23105811f, 0.24298018f, 0.25486566f, 0.26671276f, 0.27851969f, 0.29028468f, 0.30200595f, 0.31368174f, 0.32531029f, 0.33688985f, 0.34841868f, 0.35989504f, 0.37131719f, 0.38268343f, 0.39399204f, 0.40524131f, 0.41642956f, 0.42755509f, 0.43861624f, 0.44961133f, 0.46053871f, 0.47139674f, 0.48218377f, 0.49289819f, 0.50353838f, 0.51410274f, 0.52458968f, 0.53499762f, 0.54532499f, 0.55557023f, 0.56573181f, 0.57580819f, 0.58579786f, 0.59569930f, 0.60551104f, 0.61523159f, 0.62485949f, 0.63439328f, 0.64383154f, 0.65317284f, 0.66241578f, 0.67155895f, 0.68060100f, 0.68954054f, 0.69837625f, 0.70710678f, 0.71573083f, 0.72424708f, 0.73265427f, 0.74095113f, 0.74913639f, 0.75720885f, 0.76516727f, 0.77301045f, 0.78073723f, 0.78834643f, 0.79583690f, 0.80320753f, 0.81045720f, 0.81758481f, 0.82458930f, 0.83146961f, 0.83822471f, 0.84485357f, 0.85135519f, 0.85772861f, 0.86397286f, 0.87008699f, 0.87607009f, 0.88192126f, 0.88763962f, 0.89322430f, 0.89867447f, 0.90398929f, 0.90916798f, 0.91420976f, 0.91911385f, 0.92387953f, 0.92850608f, 0.93299280f, 0.93733901f, 0.94154407f, 0.94560733f, 0.94952818f, 0.95330604f, 0.95694034f, 0.96043052f, 0.96377607f, 0.96697647f, 0.97003125f, 0.97293995f, 0.97570213f, 0.97831737f, 0.98078528f, 0.98310549f, 0.98527764f, 0.98730142f, 0.98917651f, 0.99090264f, 0.99247953f, 0.99390697f, 0.99518473f, 0.99631261f, 0.99729046f, 0.99811811f, 0.99879546f, 0.99932238f, 0.99969882f, 0.99992470f, 1.00000000f, 0.99992470f, 0.99969882f, 0.99932238f, 0.99879546f, 0.99811811f, 0.99729046f, 0.99631261f, 0.99518473f, 0.99390697f, 0.99247953f, 0.99090264f, 0.98917651f, 0.98730142f, 0.98527764f, 0.98310549f, 0.98078528f, 0.97831737f, 0.97570213f, 0.97293995f, 0.97003125f, 0.96697647f, 0.96377607f, 0.96043052f, 0.95694034f, 0.95330604f, 0.94952818f, 0.94560733f, 0.94154407f, 0.93733901f, 0.93299280f, 0.92850608f, 0.92387953f, 0.91911385f, 0.91420976f, 0.90916798f, 0.90398929f, 0.89867447f, 0.89322430f, 0.88763962f, 0.88192126f, 0.87607009f, 0.87008699f, 0.86397286f, 0.85772861f, 0.85135519f, 0.84485357f, 0.83822471f, 0.83146961f, 0.82458930f, 0.81758481f, 0.81045720f, 0.80320753f, 0.79583690f, 0.78834643f, 0.78073723f, 0.77301045f, 0.76516727f, 0.75720885f, 0.74913639f, 0.74095113f, 0.73265427f, 0.72424708f, 0.71573083f, 0.70710678f, 0.69837625f, 0.68954054f, 0.68060100f, 0.67155895f, 0.66241578f, 0.65317284f, 0.64383154f, 0.63439328f, 0.62485949f, 0.61523159f, 0.60551104f, 0.59569930f, 0.58579786f, 0.57580819f, 0.56573181f, 0.55557023f, 0.54532499f, 0.53499762f, 0.52458968f, 0.51410274f, 0.50353838f, 0.49289819f, 0.48218377f, 0.47139674f, 0.46053871f, 0.44961133f, 0.43861624f, 0.42755509f, 0.41642956f, 0.40524131f, 0.39399204f, 0.38268343f, 0.37131719f, 0.35989504f, 0.34841868f, 0.33688985f, 0.32531029f, 0.31368174f, 0.30200595f, 0.29028468f, 0.27851969f, 0.26671276f, 0.25486566f, 0.24298018f, 0.23105811f, 0.21910124f, 0.20711138f, 0.19509032f, 0.18303989f, 0.17096189f, 0.15885814f, 0.14673047f, 0.13458071f, 0.12241068f, 0.11022221f, 0.09801714f, 0.08579731f, 0.07356456f, 0.06132074f, 0.04906767f, 0.03680722f, 0.02454123f, 0.01227154f, 0.00000000f, -0.01227154f, -0.02454123f, -0.03680722f, -0.04906767f, -0.06132074f, -0.07356456f, -0.08579731f, -0.09801714f, -0.11022221f, -0.12241068f, -0.13458071f, -0.14673047f, -0.15885814f, -0.17096189f, -0.18303989f, -0.19509032f, -0.20711138f, -0.21910124f, -0.23105811f, -0.24298018f, -0.25486566f, -0.26671276f, -0.27851969f, -0.29028468f, -0.30200595f, -0.31368174f, -0.32531029f, -0.33688985f, -0.34841868f, -0.35989504f, -0.37131719f, -0.38268343f, -0.39399204f, -0.40524131f, -0.41642956f, -0.42755509f, -0.43861624f, -0.44961133f, -0.46053871f, -0.47139674f, -0.48218377f, -0.49289819f, -0.50353838f, -0.51410274f, -0.52458968f, -0.53499762f, -0.54532499f, -0.55557023f, -0.56573181f, -0.57580819f, -0.58579786f, -0.59569930f, -0.60551104f, -0.61523159f, -0.62485949f, -0.63439328f, -0.64383154f, -0.65317284f, -0.66241578f, -0.67155895f, -0.68060100f, -0.68954054f, -0.69837625f, -0.70710678f, -0.71573083f, -0.72424708f, -0.73265427f, -0.74095113f, -0.74913639f, -0.75720885f, -0.76516727f, -0.77301045f, -0.78073723f, -0.78834643f, -0.79583690f, -0.80320753f, -0.81045720f, -0.81758481f, -0.82458930f, -0.83146961f, -0.83822471f, -0.84485357f, -0.85135519f, -0.85772861f, -0.86397286f, -0.87008699f, -0.87607009f, -0.88192126f, -0.88763962f, -0.89322430f, -0.89867447f, -0.90398929f, -0.90916798f, -0.91420976f, -0.91911385f, -0.92387953f, -0.92850608f, -0.93299280f, -0.93733901f, -0.94154407f, -0.94560733f, -0.94952818f, -0.95330604f, -0.95694034f, -0.96043052f, -0.96377607f, -0.96697647f, -0.97003125f, -0.97293995f, -0.97570213f, -0.97831737f, -0.98078528f, -0.98310549f, -0.98527764f, -0.98730142f, -0.98917651f, -0.99090264f, -0.99247953f, -0.99390697f, -0.99518473f, -0.99631261f, -0.99729046f, -0.99811811f, -0.99879546f, -0.99932238f, -0.99969882f, -0.99992470f, -1.00000000f, -0.99992470f, -0.99969882f, -0.99932238f, -0.99879546f, -0.99811811f, -0.99729046f, -0.99631261f, -0.99518473f, -0.99390697f, -0.99247953f, -0.99090264f, -0.98917651f, -0.98730142f, -0.98527764f, -0.98310549f, -0.98078528f, -0.97831737f, -0.97570213f, -0.97293995f, -0.97003125f, -0.96697647f, -0.96377607f, -0.96043052f, -0.95694034f, -0.95330604f, -0.94952818f, -0.94560733f, -0.94154407f, -0.93733901f, -0.93299280f, -0.92850608f, -0.92387953f, -0.91911385f, -0.91420976f, -0.90916798f, -0.90398929f, -0.89867447f, -0.89322430f, -0.88763962f, -0.88192126f, -0.87607009f, -0.87008699f, -0.86397286f, -0.85772861f, -0.85135519f, -0.84485357f, -0.83822471f, -0.83146961f, -0.82458930f, -0.81758481f, -0.81045720f, -0.80320753f, -0.79583690f, -0.78834643f, -0.78073723f, -0.77301045f, -0.76516727f, -0.75720885f, -0.74913639f, -0.74095113f, -0.73265427f, -0.72424708f, -0.71573083f, -0.70710678f, -0.69837625f, -0.68954054f, -0.68060100f, -0.67155895f, -0.66241578f, -0.65317284f, -0.64383154f, -0.63439328f, -0.62485949f, -0.61523159f, -0.60551104f, -0.59569930f, -0.58579786f, -0.57580819f, -0.56573181f, -0.55557023f, -0.54532499f, -0.53499762f, -0.52458968f, -0.51410274f, -0.50353838f, -0.49289819f, -0.48218377f, -0.47139674f, -0.46053871f, -0.44961133f, -0.43861624f, -0.42755509f, -0.41642956f, -0.40524131f, -0.39399204f, -0.38268343f, -0.37131719f, -0.35989504f, -0.34841868f, -0.33688985f, -0.32531029f, -0.31368174f, -0.30200595f, -0.29028468f, -0.27851969f, -0.26671276f, -0.25486566f, -0.24298018f, -0.23105811f, -0.21910124f, -0.20711138f, -0.19509032f, -0.18303989f, -0.17096189f, -0.15885814f, -0.14673047f, -0.13458071f, -0.12241068f, -0.11022221f, -0.09801714f, -0.08579731f, -0.07356456f, -0.06132074f, -0.04906767f, -0.03680722f, -0.02454123f, -0.01227154f, -0.00000000f }; void FastSinCos(float x, float *sinVal, float *cosVal) { float fract, in; // Temporary variables for input, output unsigned short indexS, indexC; // Index variable float f1, f2, d1, d2; // Two nearest output values int n; float findex, Dn, Df, temp; // input x is in radians //Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi, for cosine add 0.25 (pi/2) to read sine table in = x * 0.159154943092f; // Calculation of floor value of input n = (int) in; // Make negative values towards -infinity if(in < 0.0f){ n--; } // Map input value to [0 1] in = in - (float) n; // Calculation of index of the table findex = (float) FAST_SIN_TABLE_SIZE * in; indexS = ((unsigned short)findex) & 0x1ff; indexC = (indexS + (FAST_SIN_TABLE_SIZE / 4)) & 0x1ff; // fractional value calculation fract = findex - (float) indexS; // Read two nearest values of input value from the cos & sin tables f1 = sinTable[indexC+0]; f2 = sinTable[indexC+1]; d1 = -sinTable[indexS+0]; d2 = -sinTable[indexS+1]; Dn = 0.0122718463030f; // delta between the two points (fixed), in this case 2*pi/FAST_SIN_TABLE_SIZE Df = f2 - f1; // delta between the values of the functions temp = Dn*(d1 + d2) - 2*Df; temp = fract*temp + (3*Df - (d2 + 2*d1)*Dn); temp = fract*temp + d1*Dn; // Calculation of cosine value *cosVal = fract*temp + f1; // Read two nearest values of input value from the cos & sin tables f1 = sinTable[indexS+0]; f2 = sinTable[indexS+1]; d1 = sinTable[indexC+0]; d2 = sinTable[indexC+1]; Df = f2 - f1; // delta between the values of the functions temp = Dn*(d1 + d2) - 2*Df; temp = fract*temp + (3*Df - (d2 + 2*d1)*Dn); temp = fract*temp + d1*Dn; // Calculation of sine value *sinVal = fract*temp + f1; } float FastSin(float x) { float sinVal, fract, in; // Temporary variables for input, output unsigned short index; // Index variable float a, b; // Two nearest output values int n; float findex; // input x is in radians // Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi in = x * 0.159154943092f; // Calculation of floor value of input n = (int) in; // Make negative values towards -infinity if(x < 0.0f){ n--; } // Map input value to [0 1] in = in - (float) n; // Calculation of index of the table findex = (float) FAST_SIN_TABLE_SIZE * in; index = ((unsigned short)findex) & 0x1ff; // fractional value calculation fract = findex - (float) index; // Read two nearest values of input value from the sin table a = sinTable[index]; b = sinTable[index+1]; // Linear interpolation process sinVal = (1.0f-fract)*a + fract*b; // Return the output value return (sinVal); } float FastCos(float x) { float cosVal, fract, in; // Temporary variables for input, output unsigned short index; // Index variable float a, b; // Two nearest output values int n; float findex; // input x is in radians // Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi, add 0.25 (pi/2) to read sine table in = x * 0.159154943092f + 0.25f; // Calculation of floor value of input n = (int) in; // Make negative values towards -infinity if(in < 0.0f){ n--; } // Map input value to [0 1] in = in - (float) n; // Calculation of index of the table findex = (float) FAST_SIN_TABLE_SIZE * in; index = ((unsigned short)findex) & 0x1ff; // fractional value calculation fract = findex - (float) index; // Read two nearest values of input value from the cos table a = sinTable[index]; b = sinTable[index+1]; // Linear interpolation process cosVal = (1.0f-fract)*a + fract*b; // Return the output value return (cosVal); } Double FastSqrtID(Double dx) { Double dy; Double dhalfx = DoubleMul(doubleToDouble(0.5), dx); union { double d; unsigned __int64 i; } u; // u.d = DoubleTodouble(dx); u.i = 0x5fe6ec85e7de30daLL - (u.i >> 1); dy = doubleToDouble(u.d); dy = DoubleMul(dy, DoubleSub(doubleToDouble(1.5), DoubleMul(DoubleMul(dhalfx, dy), dy))); //return DoubleDiv(doubleToDouble(1.0), dx); return dy; } Double FastSqrtD(Double dx) { Double dy; Double dhalfx = DoubleMul(doubleToDouble(0.5), dx); union { double d; unsigned __int64 i; } u; // u.d = DoubleTodouble(dx); u.i = 0x5fe6ec85e7de30daLL - (u.i >> 1); dy = doubleToDouble(u.d); dy = DoubleMul(dy, DoubleSub(doubleToDouble(1.5), DoubleMul(DoubleMul(dhalfx, dy), dy))); return DoubleDiv(doubleToDouble(1.0), dx); } ================================================ FILE: Matrix/inc/DoubleMatrix.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _DOUBLEMATRIX_H_ #define _DOUBLEMATRIX_H_ #include "Double.h" #endif ================================================ FILE: Matrix/inc/Matrix.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _MATRIX_H_ #define _MATRIX_H_ #include "arm_math.h" void arm_mat_zero_f32(arm_matrix_instance_f32* s); arm_status mat_identity(float32_t *pData, uint16_t numRows, uint16_t numCols, float32_t value); arm_status arm_mat_identity_f32(arm_matrix_instance_f32* s, float32_t value); arm_status arm_mat_fill_f32(arm_matrix_instance_f32* s, float32_t *pData, uint32_t blockSize); arm_status arm_mat_chol_f32(arm_matrix_instance_f32* s); arm_status arm_mat_remainlower_f32(arm_matrix_instance_f32* s); void arm_mat_getsubmatrix_f32(arm_matrix_instance_f32* s, arm_matrix_instance_f32 *a, int row, int col); void arm_mat_setsubmatrix_f32(arm_matrix_instance_f32* a, arm_matrix_instance_f32 *s, int row, int col); void arm_mat_getcolumn_f32(arm_matrix_instance_f32* s, float32_t *x, uint32_t col); void arm_mat_setcolumn_f32(arm_matrix_instance_f32* s, float32_t *x, uint32_t col); void arm_mat_cumsum_f32(arm_matrix_instance_f32* s, float32_t *tmp, float32_t *x); int arm_mat_qr_decompositionT_f32(arm_matrix_instance_f32 *A, arm_matrix_instance_f32 *R); #endif ================================================ FILE: Matrix/src/DoubleMatrix.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "DoubleMatrix.h" #include "FastMath.h" ================================================ FILE: Matrix/src/Matrix.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "Matrix.h" #include "FastMath.h" arm_status mat_identity(float32_t *pData, uint16_t numRows, uint16_t numCols, float32_t value) { uint16_t pos = 0; float32_t *A = pData; if (numRows != numCols){ return ARM_MATH_LENGTH_ERROR; } do{ A[pos * numRows + pos] = value; pos++; } while (pos < numRows); return ARM_MATH_SUCCESS; } void arm_mat_zero_f32(arm_matrix_instance_f32* s) { uint16_t pos = 0; uint16_t blockSize = s->numRows * s->numCols; float32_t *A = s->pData; do{ A[pos] = 0.0f; pos++; } while (pos < blockSize); } arm_status arm_mat_identity_f32(arm_matrix_instance_f32* s, float32_t value) { uint16_t pos = 0; float32_t *A = s->pData; int n = s->numRows; if (n != s->numCols){ return ARM_MATH_LENGTH_ERROR; } do{ A[pos * n + pos] = value; pos++; } while (pos < n); return ARM_MATH_SUCCESS; } arm_status arm_mat_remainlower_f32(arm_matrix_instance_f32* s) { float32_t *A = s->pData; int nrows = s->numRows; int ncols = s->numCols; int k, p; float32_t *p_Uk0; // pointer to U[k][0] float32_t *p_Ukp; // pointer to U[k][p] if (nrows != ncols){ return ARM_MATH_SIZE_MISMATCH; } for (k = 0, p_Uk0 = A; k < nrows; p_Uk0 += ncols, k++){ for (p = k + 1; p < ncols; p++){ p_Ukp = p_Uk0 + p; *p_Ukp = 0.0f; } } return ARM_MATH_SUCCESS; } arm_status arm_mat_fill_f32(arm_matrix_instance_f32* s, float32_t *pData, uint32_t blockSize) { uint16_t pos = 0; float32_t *A = s->pData; if (s->numRows * s->numCols < blockSize){ return ARM_MATH_SIZE_MISMATCH; } do{ A[pos] = pData[pos]; pos++; } while (pos < blockSize); return ARM_MATH_SUCCESS; } //Returns the lower triangular matrix L in the //bottom of A so that L*L' = A. arm_status arm_mat_chol_f32(arm_matrix_instance_f32* s) { int i, k, p; float32_t *p_Lk0; // pointer to L[k][0] float32_t *p_Lkp; // pointer to L[k][p] float32_t *p_Lkk; // pointer to diagonal element on row k. float32_t *p_Li0; // pointer to L[i][0] float32_t reciprocal; float32_t *A = s->pData; int n = s->numRows; if (n != s->numCols){ return ARM_MATH_SIZE_MISMATCH; } for (k = 0, p_Lk0 = A; k < n; p_Lk0 += n, k++) { p_Lkk = p_Lk0 + k; for (p = 0, p_Lkp = p_Lk0; p < k; p_Lkp += 1, p++){ *p_Lkk -= *p_Lkp * *p_Lkp; } if (*p_Lkk <= 0.0f){ return ARM_MATH_SINGULAR; } arm_sqrt_f32(*p_Lkk, p_Lkk); reciprocal = 1.0f / *p_Lkk; p_Li0 = p_Lk0 + n; for (i = k + 1; i < n; p_Li0 += n, i++) { for (p = 0; p < k; p++){ *(p_Li0 + k) -= *(p_Li0 + p) * *(p_Lk0 + p); } *(p_Li0 + k) *= reciprocal; *(p_Lk0 + i) = *(p_Li0 + k); } } return ARM_MATH_SUCCESS; } void arm_mat_getsubmatrix_f32(arm_matrix_instance_f32* s, arm_matrix_instance_f32 *a, int row, int col) { int k; int mrows = s->numRows; int mcols = s->numCols; int ncols = a->numCols; float32_t *S = s->pData; float32_t *A = a->pData; for (A += row * ncols + col; mrows > 0; A += ncols, S+= mcols, mrows--){ for(k = 0; k < mcols; k++){ *(S + k) = *(A + k); } } } void arm_mat_setsubmatrix_f32(arm_matrix_instance_f32* a, arm_matrix_instance_f32 *s, int row, int col) { int mrows = s->numRows; int mcols = s->numCols; int ncols = a->numCols; int i,j; float32_t *S = s->pData; float32_t *A = a->pData; for(A += row * ncols + col, i = 0; i < mrows; A += ncols, i++){ for(j = 0; j < mcols; j++){ *(A + j) = *S++; } } } void arm_mat_getcolumn_f32(arm_matrix_instance_f32* s, float32_t *x, uint32_t col) { int nrows = s->numRows, ncols = s->numCols; float32_t *S = s->pData; int i = 0; for (S += col; i < nrows; S += ncols, i++) x[i] = *S; } void arm_mat_setcolumn_f32(arm_matrix_instance_f32* s, float32_t *x, uint32_t col) { int nrows = s->numRows, ncols = s->numCols; float32_t *S = s->pData; int i = 0; for (S += col; i < nrows; S += ncols, i++) *S = x[i]; } void arm_mat_cumsum_f32(arm_matrix_instance_f32* s, float32_t *tmp, float32_t *x) { int nrows = s->numRows, ncols = s->numCols; int i, j; //zero x; for(i = 0; i < nrows; i++){ x[i] = 0.0f; } for(i = 0; i < ncols; i++){ arm_mat_getcolumn_f32(s, tmp, i); for(j = 0; j < nrows; j++){ x[j] += tmp[j]; } } } int arm_mat_qr_decompositionT_f32(arm_matrix_instance_f32 *A, arm_matrix_instance_f32 *R) { int minor; int row, col; int m = A->numCols; int n = A->numRows; int min; float32_t xNormSqr; float32_t a; float32_t alpha; // clear R arm_fill_f32(0, R->pData, R->numRows * R->numCols); if(m < n){ min = m; } else{ min = n; } for (minor = 0; minor < min; minor++) { xNormSqr = 0.0f; for (row = minor; row < m; row++){ xNormSqr += A->pData[minor * m + row] * A->pData[minor * m + row]; } arm_sqrt_f32(xNormSqr, &a); if (A->pData[minor * m + minor] > 0.0f){ a = -a; } if (a != 0.0f) { R->pData[minor * R->numCols + minor] = a; A->pData[minor * m + minor] -= a; for (col = minor+1; col < n; col++) { alpha = 0.0f; for (row = minor; row < m; row++){ alpha -= A->pData[col * m + row] * A->pData[minor * m + row]; } alpha /= a * A->pData[minor * m + minor]; // subtract the column vector alpha * v from x. for (row = minor; row < m; row++){ A->pData[col * m + row] -= alpha * A->pData[minor * m + row]; } } } // rank deficient else{ return 0; } } // Form the matrix R of the QR-decomposition. // R is supposed to be m x n, but only calculate n x n // copy the upper triangle of A for (row = min-1; row >= 0; row--){ for (col = row+1; col < n; col++){ R->pData[row * R->numCols + col] = A->pData[col * m + row]; } } return 1; } ================================================ FILE: Project/JLinkLog.txt ================================================ T169C 000:523 SEGGER J-Link V4.96f Log File (0000ms, 0309ms total) T169C 000:523 DLL Compiled: Feb 4 2015 14:13:39 (0000ms, 0309ms total) T169C 000:523 Logging started @ 2015-03-05 22:36 (0000ms, 0309ms total) T169C 000:523 JLINK_SetWarnOutHandler(...) (0000ms, 0309ms total) T169C 000:523 JLINK_OpenEx(...) Firmware: J-Link ARM V8 compiled Nov 28 2014 13:44:46 Hardware: V8.00 S/N: 20150219 Feature(s): RDI,FlashDL,FlashBP,JFlash,GDBFULL returns O.K. (0304ms, 0613ms total) T169C 000:827 JLINK_SetErrorOutHandler(...) (0000ms, 0613ms total) T169C 000:827 JLINK_ExecCommand("ProjectFile = "G:\work\project\imu\stm32f4_mpu9250\Project\JLinkSettings.ini"", ...) returns 0x00 (0000ms, 0613ms total) T169C 000:827 JLINK_ExecCommand("Device = STM32F407VE", ...)Device "STM32F407VE" selected. returns 0x00 (0000ms, 0613ms total) T169C 000:827 JLINK_ExecCommand("DisableConnectionTimeout", ...) returns 0x01 (0000ms, 0613ms total) T169C 000:828 JLINK_GetHardwareVersion() returns 0x13880 (0000ms, 0614ms total) T169C 000:828 JLINK_GetDLLVersion() returns 49606 (0000ms, 0614ms total) T169C 000:828 JLINK_GetFirmwareString(...) (0000ms, 0614ms total) T169C 000:828 JLINK_GetDLLVersion() returns 49606 (0000ms, 0614ms total) T169C 000:828 JLINK_GetCompileDateTime() (0000ms, 0614ms total) T169C 000:828 JLINK_GetFirmwareString(...) (0000ms, 0614ms total) T169C 000:829 JLINK_GetHardwareVersion() returns 0x13880 (0000ms, 0614ms total) T169C 000:829 JLINK_TIF_Select(JLINKARM_TIF_JTAG) returns 0x00 (0010ms, 0624ms total) T169C 000:839 JLINK_SetSpeed(2000) (0001ms, 0625ms total) T169C 000:840 JLINK_GetIdData(...) >0x2F8 JTAG>TotalIRLen = 9, IRPrint = 0x0011 >0x30 JTAG> >0x210 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x2F8 JTAG>TotalIRLen = 9, IRPrint = 0x0011 >0x30 JTAG> >0x210 JTAG> >0x70 JTAG> >0x40 JTAG> >0x40 JTAG> >0x40 JTAG> >0x50 JTAG> >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x50 JTAG>Found Cortex-M4 r0p1, Little endian. -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000)FPUnit: 6 code (BP) slots and 2 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88) -- CPU_ReadMem(4 bytes @ 0xE00FF010) TPIU fitted. -- CPU_ReadMem(4 bytes @ 0xE00FF014)ETM fitted. -- CPU_ReadMem(4 bytes @ 0xE00FF018) ScanLen=9 NumDevices=2 aId[0]=0x4BA00477 aIrRead[0]=0 aScanLen[0]=0 aScanRead[0]=0 (0122ms, 0747ms total) T169C 000:962 JLINK_JTAG_GetDeviceID(DeviceIndex = 0) returns 0x4BA00477 (0000ms, 0747ms total) T169C 000:962 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 0) returns 0x00 (0000ms, 0747ms total) T169C 000:962 JLINK_JTAG_GetDeviceID(DeviceIndex = 1) returns 0x6413041 (0000ms, 0747ms total) T169C 000:962 JLINK_JTAG_GetDeviceInfo(DeviceIndex = 1) returns 0x00 (0000ms, 0747ms total) T169C 000:962 JLINK_GetDeviceFamily() returns 14 (0000ms, 0747ms total) T169C 000:962 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0003ms, 0750ms total) T169C 000:965 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0003ms, 0753ms total) T169C 000:968 JLINK_ReadMem (0xE00FF000, 0x0018 Bytes, ...) -- CPU is running -- CPU_ReadMem(24 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF 03 20 F0 FF 03 30 F0 FF 03 10 F0 FF ... returns 0x00 (0003ms, 0756ms total) T169C 000:971 JLINK_ReadMemU32(0xE000ED00, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000ED00) - Data: 41 C2 0F 41 returns 0x01 (0002ms, 0758ms total) T169C 000:973 JLINK_ReadMemU32(0xE000EF40, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF40) - Data: 21 00 11 10 returns 0x01 (0002ms, 0760ms total) T169C 000:975 JLINK_ReadMemU32(0xE000EF44, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EF44) - Data: 11 00 00 11 returns 0x01 (0003ms, 0763ms total) T169C 000:978 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 0763ms total) T169C 000:978 JLINK_Reset() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x50 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0069ms, 0832ms total) T169C 001:047 JLINK_ReadReg(R15 (PC)) returns 0x080002D4 (0002ms, 0834ms total) T169C 001:049 JLINK_ReadReg(XPSR) returns 0x01000000 (0000ms, 0834ms total) T169C 001:049 JLINK_Halt() returns 0x00 (0000ms, 0834ms total) T169C 001:049 JLINK_IsHalted() returns TRUE (0000ms, 0834ms total) T169C 001:049 JLINK_ReadMemU32(0xE000EDF0, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) - Data: 03 00 03 00 returns 0x01 (0003ms, 0837ms total) T169C 001:052 JLINK_WriteU32(0xE000EDF0, 0xA05F0003) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) returns 0x00 (0001ms, 0838ms total) T169C 001:053 JLINK_WriteU32(0xE000EDFC, 0x01000000) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) returns 0x00 (0002ms, 0840ms total) T169C 001:055 JLINK_GetHWStatus(...) returns 0x00 (0003ms, 0843ms total) T169C 001:058 JLINK_GetNumBPUnits(Type = 0xFFFFFF00) returns 0x06 (0000ms, 0843ms total) T169C 001:058 JLINK_GetNumBPUnits(Type = 0xF0) returns 0x2000 (0000ms, 0843ms total) T169C 001:058 JLINK_GetNumWPUnits() returns 0x04 (0000ms, 0843ms total) T169C 001:058 JLINK_GetSpeed() returns 0x7D0 (0000ms, 0843ms total) T169C 001:058 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0003ms, 0846ms total) T169C 001:061 JLINK_ReadMemU32(0xE000E004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000E004) - Data: 02 00 00 00 returns 0x01 (0002ms, 0848ms total) T169C 001:063 JLINK_WriteMem(0xE0001000, 0x001C Bytes, ...) - Data: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... -- CPU_WriteMem(28 bytes @ 0xE0001000) returns 0x1C (0003ms, 0851ms total) T169C 001:066 JLINK_ReadMem (0xE0001000, 0x001C Bytes, ...) -- CPU_ReadMem(28 bytes @ 0xE0001000) - Data: 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0002ms, 0853ms total) T169C 001:068 JLINK_ReadReg(R15 (PC)) returns 0x080002D4 (0000ms, 0853ms total) T169C 001:068 JLINK_ReadReg(XPSR) returns 0x01000000 (0000ms, 0853ms total) T169C 001:089 JLINK_ReadMem (0x08000000, 0x1000 Bytes, ...) -- CPU_ReadMem(4096 bytes @ 0x08000000) -- Updating C cache (4096 bytes @ 0x08000000) -- Read from C cache (4096 bytes @ 0x08000000) - Data: B0 4E 00 20 D5 02 00 08 DD 02 00 08 DF 02 00 08 ... returns 0x00 (0026ms, 0879ms total) T169C 001:115 JLINK_ReadMem (0x08001000, 0x1000 Bytes, ...) -- CPU_ReadMem(4096 bytes @ 0x08001000) -- Updating C cache (4096 bytes @ 0x08001000) -- Read from C cache (4096 bytes @ 0x08001000) - Data: F0 EE 00 0A 60 EE 20 AA 90 ED 02 0A F0 EE 00 0A ... returns 0x00 (0027ms, 0906ms total) T169C 001:142 JLINK_ReadMem (0x08002000, 0x1000 Bytes, ...) -- CPU_ReadMem(4096 bytes @ 0x08002000) -- Updating C cache (4096 bytes @ 0x08002000) -- Read from C cache (4096 bytes @ 0x08002000) - Data: C0 0A F1 EE 10 FA 02 D1 4F F0 FF 30 00 90 00 98 ... returns 0x00 (0026ms, 0932ms total) T169C 001:169 JLINK_ReadMem (0x08003000, 0x1000 Bytes, ...) -- CPU_ReadMem(4096 bytes @ 0x08003000) -- Updating C cache (4096 bytes @ 0x08003000) -- Read from C cache (4096 bytes @ 0x08003000) - Data: 03 F3 01 2D 02 D1 96 89 33 40 06 E0 02 2D 02 D1 ... returns 0x00 (0026ms, 0958ms total) T169C 001:195 JLINK_ReadMem (0x08004000, 0x1000 Bytes, ...) -- CPU_ReadMem(4096 bytes @ 0x08004000) -- Updating C cache (4096 bytes @ 0x08004000) -- Read from C cache (4096 bytes @ 0x08004000) - Data: 40 8A B0 EE 48 0A 16 AA 19 A9 1C A8 FC F7 3C FE ... returns 0x00 (0027ms, 0985ms total) T169C 001:222 JLINK_ReadMem (0x08005000, 0x1000 Bytes, ...) -- CPU_ReadMem(4096 bytes @ 0x08005000) -- Updating C cache (4096 bytes @ 0x08005000) -- Read from C cache (4096 bytes @ 0x08005000) - Data: 14 48 41 74 23 E0 13 48 80 7A 10 B9 4F F0 FF 30 ... returns 0x00 (0026ms, 1011ms total) T169C 001:249 JLINK_ReadMem (0x08006000, 0x0A04 Bytes, ...) -- CPU_ReadMem(2624 bytes @ 0x08006000) -- Updating C cache (2624 bytes @ 0x08006000) -- Read from C cache (2564 bytes @ 0x08006000) - Data: 79 51 F1 90 2C 87 0C A7 81 97 62 93 F0 71 71 60 ... returns 0x00 (0016ms, 1027ms total) T169C 001:317 JLINK_SetResetType(JLINKARM_RESET_TYPE_NORMAL) returns JLINKARM_RESET_TYPE_NORMAL (0000ms, 1027ms total) T169C 001:317 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) >0x80 JTAG> >0x40 JTAG> >0x30 JTAG> >0x40 JTAG> >0x50 JTAG> >0x40 JTAG> -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU_WriteMem(4 bytes @ 0xE0001028) -- CPU_WriteMem(4 bytes @ 0xE0001038) -- CPU_WriteMem(4 bytes @ 0xE0001048) -- CPU_WriteMem(4 bytes @ 0xE0001058) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0060ms, 1087ms total) T169C 001:377 JLINK_ReadReg(R15 (PC)) returns 0x080002D4 (0000ms, 1087ms total) T169C 001:377 JLINK_ReadReg(XPSR) returns 0x01000000 (0000ms, 1087ms total) T169C 001:377 JLINK_ReadMem (0x080002D2, 0x0002 Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x080002C0) -- Updating C cache (64 bytes @ 0x080002C0) -- Read from C cache (2 bytes @ 0x080002D2) - Data: 70 47 returns 0x00 (0003ms, 1090ms total) T169C 001:380 JLINK_ReadMem (0x080002D4, 0x003C Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x08000300) -- Updating C cache (64 bytes @ 0x08000300) -- Read from C cache (60 bytes @ 0x080002D4) - Data: 09 48 80 47 09 48 00 47 FE E7 FE E7 FE E7 FE E7 ... returns 0x00 (0003ms, 1093ms total) T169C 001:383 JLINK_ReadMem (0x080002CE, 0x0002 Bytes, ...) -- Read from C cache (2 bytes @ 0x080002CE) - Data: BD E8 returns 0x00 (0000ms, 1093ms total) T169C 001:383 JLINK_ReadMem (0x080002D0, 0x003C Bytes, ...) -- Read from C cache (60 bytes @ 0x080002D0) - Data: F0 0F 70 47 09 48 80 47 09 48 00 47 FE E7 FE E7 ... returns 0x00 (0000ms, 1093ms total) T2250 002:638 JLINK_SetBPEx(Addr = 0x08003D68, Type = 0xFFFFFFF2) returns 0x00000001 (0002ms, 1095ms total) T2250 002:640 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0015ms, 1110ms total) T2250 002:755 JLINK_IsHalted() returns TRUE (0007ms, 1117ms total) T2250 002:762 JLINK_Halt() returns 0x00 (0000ms, 1110ms total) T2250 002:762 JLINK_IsHalted() returns TRUE (0000ms, 1110ms total) T2250 002:762 JLINK_IsHalted() returns TRUE (0000ms, 1110ms total) T2250 002:762 JLINK_IsHalted() returns TRUE (0000ms, 1110ms total) T2250 002:762 JLINK_ReadReg(R15 (PC)) returns 0x08003D68 (0000ms, 1110ms total) T2250 002:762 JLINK_ReadReg(XPSR) returns 0x21000000 (0000ms, 1110ms total) T2250 002:762 JLINK_ClrBPEx(BPHandle = 0x00000001) returns 0x00 (0000ms, 1110ms total) T2250 002:762 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 03 00 00 00 returns 0x01 (0003ms, 1113ms total) T2250 002:765 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00 returns 0x01 (0002ms, 1115ms total) T2250 002:767 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00 returns 0x01 (0002ms, 1117ms total) T2250 002:769 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00 returns 0x01 (0003ms, 1120ms total) T2250 002:772 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00 returns 0x01 (0002ms, 1122ms total) T2250 002:774 JLINK_ReadReg(R0) returns 0x20000CB0 (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(R1) returns 0x20000EB0 (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(R2) returns 0x20000EB0 (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(R3) returns 0x20000EB0 (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(R5) returns 0x20000C4C (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(R9) returns 0x00000000 (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(R10) returns 0x08006940 (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(R12) returns 0x20000C8C (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(R13 (SP)) returns 0x20004EB0 (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(R14) returns 0x08000257 (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(R15 (PC)) returns 0x08003D68 (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(XPSR) returns 0x21000000 (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(MSP) returns 0x20004EB0 (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(PSP) returns 0x00000000 (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(CFBP) returns 0x04000000 (0000ms, 1122ms total) T2250 002:774 JLINK_ReadReg(FPSCR) returns 0x03000000 (0009ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 1131ms total) T2250 002:783 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 1131ms total) T169C 002:784 JLINK_ReadMem (0x20004E8C, 0x0001 Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x20004E80) -- Updating C cache (64 bytes @ 0x20004E80) -- Read from C cache (1 bytes @ 0x20004E8C) - Data: 00 returns 0x00 (0002ms, 1133ms total) T169C 002:786 JLINK_ReadMem (0x20004E88, 0x0002 Bytes, ...) -- Read from C cache (2 bytes @ 0x20004E88) - Data: 00 00 returns 0x00 (0000ms, 1133ms total) T169C 002:786 JLINK_ReadMem (0x20004E84, 0x0002 Bytes, ...) -- Read from C cache (2 bytes @ 0x20004E84) - Data: 00 00 returns 0x00 (0000ms, 1133ms total) T169C 002:786 JLINK_ReadMem (0x20004E34, 0x0002 Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x20004E00) -- Updating C cache (64 bytes @ 0x20004E00) -- Read from C cache (2 bytes @ 0x20004E34) - Data: 00 00 returns 0x00 (0002ms, 1135ms total) T169C 002:788 JLINK_ReadMem (0x20004E30, 0x0001 Bytes, ...) -- Read from C cache (1 bytes @ 0x20004E30) - Data: 00 returns 0x00 (0000ms, 1135ms total) T169C 002:788 JLINK_ReadMem (0x20004E1C, 0x0004 Bytes, ...) -- Read from C cache (4 bytes @ 0x20004E1C) - Data: 00 00 00 00 returns 0x00 (0000ms, 1135ms total) T169C 002:788 JLINK_ReadMem (0x20004DFC, 0x0004 Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x20004DC0) -- Updating C cache (64 bytes @ 0x20004DC0) -- Read from C cache (4 bytes @ 0x20004DFC) - Data: 00 00 00 00 returns 0x00 (0002ms, 1137ms total) T169C 002:790 JLINK_ReadMem (0x00000000, 0x0002 Bytes, ...) -- CPU_ReadMem(4 bytes @ 0x00000004) -- CPU_ReadMem(64 bytes @ 0x08000000) -- Updating C cache (64 bytes @ 0x08000000) -- Read from C cache (2 bytes @ 0x08000000) - Data: B0 4E returns 0x00 (0004ms, 1141ms total) T169C 002:795 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 4F 67 00 00 returns 0x01 (0002ms, 1143ms total) T169C 002:805 JLINK_ReadMem (0x08003C68, 0x003C Bytes, ...) -- CPU_ReadMem(128 bytes @ 0x08003C40) -- Updating C cache (128 bytes @ 0x08003C40) -- Read from C cache (60 bytes @ 0x08003C68) - Data: 01 F0 6E F9 10 B1 4F F0 FF 30 59 E7 16 F0 04 0F ... returns 0x00 (0003ms, 1146ms total) T169C 002:808 JLINK_ReadMem (0x08003CA4, 0x003C Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x08003CC0) -- Updating C cache (64 bytes @ 0x08003CC0) -- Read from C cache (60 bytes @ 0x08003CA4) - Data: 00 20 3F E7 00 00 48 43 00 00 80 46 00 00 40 46 ... returns 0x00 (0002ms, 1148ms total) T169C 002:810 JLINK_ReadMem (0x08003CE0, 0x003C Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x08003D00) -- Updating C cache (64 bytes @ 0x08003D00) -- Read from C cache (60 bytes @ 0x08003CE0) - Data: 8D F8 01 00 6A 46 02 21 4F F4 EF 70 01 F0 2C F9 ... returns 0x00 (0002ms, 1150ms total) T169C 002:812 JLINK_ReadMem (0x08003D1C, 0x003C Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x08003D40) -- Updating C cache (64 bytes @ 0x08003D40) -- Read from C cache (60 bytes @ 0x08003D1C) - Data: 00 20 00 2A 01 DD 00 20 1E E0 91 F9 00 20 00 2A ... returns 0x00 (0002ms, 1152ms total) T169C 002:814 JLINK_ReadMem (0x08003D58, 0x003C Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x08003D80) -- Updating C cache (64 bytes @ 0x08003D80) -- Read from C cache (60 bytes @ 0x08003D58) - Data: 02 20 00 2A 01 DA 06 20 00 E0 07 20 70 47 00 00 ... returns 0x00 (0002ms, 1154ms total) T169C 002:831 JLINK_ReadMem (0x08003EC2, 0x0002 Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x08003EC0) -- Updating C cache (64 bytes @ 0x08003EC0) -- Read from C cache (2 bytes @ 0x08003EC2) - Data: BD F9 returns 0x00 (0002ms, 1156ms total) T169C 002:833 JLINK_ReadMem (0x08003EC4, 0x003C Bytes, ...) -- Read from C cache (60 bytes @ 0x08003EC4) - Data: 8E 00 00 EE 10 0A B8 EE C0 0A DF ED 73 0A 20 EE ... returns 0x00 (0000ms, 1156ms total) T2250 003:134 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002008) (0003ms, 1159ms total) T2250 003:237 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 003:338 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 003:439 JLINK_IsHalted() returns FALSE (0002ms, 1161ms total) T2250 003:541 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 003:642 JLINK_IsHalted() returns FALSE (0003ms, 1162ms total) T2250 003:745 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 003:846 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 003:947 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 004:048 JLINK_IsHalted() returns FALSE (0002ms, 1161ms total) T2250 004:150 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 004:251 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 004:352 JLINK_IsHalted() returns FALSE (0002ms, 1161ms total) T2250 004:454 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 004:555 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 004:656 JLINK_IsHalted() returns FALSE (0002ms, 1161ms total) T2250 004:758 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 004:859 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 004:960 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 005:061 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 005:162 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 005:263 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 005:364 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 005:465 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 005:566 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 005:667 JLINK_IsHalted() returns FALSE (0003ms, 1162ms total) T2250 005:770 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 005:871 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 005:972 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 006:073 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 006:174 JLINK_IsHalted() returns FALSE (0002ms, 1161ms total) T2250 006:276 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 006:377 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 006:478 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 006:579 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 006:680 JLINK_IsHalted() returns FALSE (0002ms, 1161ms total) T2250 006:782 JLINK_IsHalted() returns FALSE (0002ms, 1161ms total) T2250 006:884 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 006:985 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 007:086 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 007:187 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 007:288 JLINK_IsHalted() returns FALSE (0002ms, 1161ms total) T2250 007:390 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 007:491 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 007:592 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 007:693 JLINK_IsHalted() returns FALSE (0002ms, 1161ms total) T2250 007:795 JLINK_IsHalted() returns FALSE (0001ms, 1160ms total) T2250 007:896 JLINK_IsHalted() returns FALSE (0002ms, 1161ms total) T2250 007:998 JLINK_Halt() returns 0x00 (0006ms, 1165ms total) T2250 008:004 JLINK_IsHalted() returns TRUE (0000ms, 1165ms total) T2250 008:004 JLINK_IsHalted() returns TRUE (0000ms, 1165ms total) T2250 008:004 JLINK_IsHalted() returns TRUE (0000ms, 1165ms total) T2250 008:004 JLINK_ReadReg(R15 (PC)) returns 0x08001AC8 (0000ms, 1165ms total) T2250 008:004 JLINK_ReadReg(XPSR) returns 0x61000000 (0000ms, 1165ms total) T2250 008:004 JLINK_ReadMemU32(0xE000ED30, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) - Data: 01 00 00 00 returns 0x01 (0002ms, 1167ms total) T2250 008:006 JLINK_ReadMemU32(0xE0001028, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00 returns 0x01 (0002ms, 1169ms total) T2250 008:008 JLINK_ReadMemU32(0xE0001038, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00 returns 0x01 (0002ms, 1171ms total) T2250 008:010 JLINK_ReadMemU32(0xE0001048, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00 returns 0x01 (0002ms, 1173ms total) T2250 008:012 JLINK_ReadMemU32(0xE0001058, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00 returns 0x01 (0001ms, 1174ms total) T2250 008:013 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(R1) returns 0x20000008 (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(R2) returns 0x20000008 (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(R3) returns 0x0000000D (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(R4) returns 0x2000003C (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(R6) returns 0x00000088 (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(R7) returns 0x00000150 (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(R8) returns 0x000012F4 (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(R9) returns 0x000012F4 (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(R10) returns 0x00000001 (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(R11) returns 0x00000088 (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(R12) returns 0x200008E4 (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(R13 (SP)) returns 0x20004DF0 (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(R14) returns 0x08003E81 (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(R15 (PC)) returns 0x08001AC8 (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(XPSR) returns 0x61000000 (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(MSP) returns 0x20004DF0 (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(PSP) returns 0x00000000 (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(CFBP) returns 0x04000000 (0000ms, 1174ms total) T2250 008:013 JLINK_ReadReg(FPSCR) returns 0x83000010 (0010ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS0) returns 0x02C96750 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS1) returns 0x4F000000 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS2) returns 0x3D5E8559 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS3) returns 0xBDA49392 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS4) returns 0x40929A9C (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS5) returns 0xBE685AF7 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS6) returns 0xBF7938F5 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS7) returns 0xC03A680D (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS8) returns 0x4099CF47 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS9) returns 0xBF800000 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS10) returns 0xBB0B4ED3 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS11) returns 0xC183ECFC (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS16) returns 0x3C23D70B (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS31) returns 0x00000000 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS7) returns 0xC03A680D (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS8) returns 0x4099CF47 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS9) returns 0xBF800000 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS10) returns 0xBB0B4ED3 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS11) returns 0xC183ECFC (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS15) returns 0x00000000 (0000ms, 1184ms total) T2250 008:023 JLINK_ReadReg(FPS16) returns 0x3C23D70B (0000ms, 1184ms total) T169C 008:025 JLINK_ReadMem (0x20004E8C, 0x0001 Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x20004E80) -- Updating C cache (64 bytes @ 0x20004E80) -- Read from C cache (1 bytes @ 0x20004E8C) - Data: 02 returns 0x00 (0001ms, 1185ms total) T169C 008:026 JLINK_ReadMem (0x20004E88, 0x0002 Bytes, ...) -- Read from C cache (2 bytes @ 0x20004E88) - Data: C8 00 returns 0x00 (0000ms, 1185ms total) T169C 008:026 JLINK_ReadMem (0x20004E84, 0x0002 Bytes, ...) -- Read from C cache (2 bytes @ 0x20004E84) - Data: D0 07 returns 0x00 (0000ms, 1185ms total) T169C 008:026 JLINK_ReadMem (0x20004E34, 0x0002 Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x20004E00) -- Updating C cache (64 bytes @ 0x20004E00) -- Read from C cache (2 bytes @ 0x20004E34) - Data: 78 00 returns 0x00 (0003ms, 1188ms total) T169C 008:029 JLINK_ReadMem (0x20004E30, 0x0001 Bytes, ...) -- Read from C cache (1 bytes @ 0x20004E30) - Data: 13 returns 0x00 (0000ms, 1188ms total) T169C 008:029 JLINK_ReadMem (0x20004E1C, 0x0004 Bytes, ...) -- Read from C cache (4 bytes @ 0x20004E1C) - Data: F4 12 00 00 returns 0x00 (0000ms, 1188ms total) T169C 008:029 JLINK_ReadMem (0x20004DFC, 0x0004 Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x20004DC0) -- Updating C cache (64 bytes @ 0x20004DC0) -- Read from C cache (4 bytes @ 0x20004DFC) - Data: F4 12 00 00 returns 0x00 (0003ms, 1191ms total) T169C 008:032 JLINK_ReadMem (0x00000000, 0x0002 Bytes, ...) -- CPU_ReadMem(4 bytes @ 0x00000004) -- CPU_ReadMem(64 bytes @ 0x08000000) -- Updating C cache (64 bytes @ 0x08000000) -- Read from C cache (2 bytes @ 0x08000000) - Data: B0 4E returns 0x00 (0005ms, 1196ms total) T169C 008:037 JLINK_ReadMemU32(0xE0001004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE0001004) - Data: 55 45 C5 22 returns 0x01 (0003ms, 1199ms total) T169C 008:043 JLINK_ReadMem (0x08001AC4, 0x003C Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x08001AC0) -- Updating C cache (64 bytes @ 0x08001AC0) -- Read from C cache (60 bytes @ 0x08001AC4) - Data: 02 49 08 78 00 21 01 4A 11 70 70 47 08 00 00 20 ... returns 0x00 (0003ms, 1202ms total) T169C 008:046 JLINK_ReadMem (0x080019C4, 0x003C Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x080019C0) -- Updating C cache (64 bytes @ 0x080019C0) -- Read from C cache (60 bytes @ 0x080019C4) - Data: F0 B5 0A 46 00 21 00 23 00 24 00 BF 3D E0 01 25 ... returns 0x00 (0002ms, 1204ms total) T169C 008:048 JLINK_ReadMem (0x08001A00, 0x003C Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x08001A00) -- Updating C cache (64 bytes @ 0x08001A00) -- Read from C cache (60 bytes @ 0x08001A00) - Data: 15 79 02 2D 16 D1 85 68 4F 00 03 26 BE 40 B5 43 ... returns 0x00 (0003ms, 1207ms total) T169C 008:051 JLINK_ReadMem (0x08001A3C, 0x003C Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x08001A40) -- Updating C cache (64 bytes @ 0x08001A40) -- Read from C cache (60 bytes @ 0x08001A3C) - Data: B5 43 C5 60 D5 79 4E 00 B5 40 C6 68 35 43 C5 60 ... returns 0x00 (0003ms, 1210ms total) T169C 008:054 JLINK_ReadMem (0x08001A78, 0x003C Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x08001A80) -- Updating C cache (64 bytes @ 0x08001A80) -- Read from C cache (60 bytes @ 0x08001A78) - Data: 00 F1 20 06 46 F8 27 50 CE 10 00 F1 20 05 55 F8 ... returns 0x00 (0003ms, 1213ms total) T169C 008:057 JLINK_ReadMem (0x08001AB4, 0x003C Bytes, ...) -- Read from C cache (60 bytes @ 0x08001AB4) - Data: 01 46 02 48 00 68 08 60 00 20 70 47 00 00 00 20 ... returns 0x00 (0000ms, 1213ms total) T169C 008:681 JLINK_Close() >0x80 JTAG> >0x08 JTAG> (0014ms, 1227ms total) T169C 008:681 (0014ms, 1227ms total) T169C 008:681 Closed (0014ms, 1227ms total) ================================================ FILE: Project/JLinkSettings.ini ================================================ [BREAKPOINTS] ForceImpTypeAny = 0 ShowInfoWin = 1 EnableFlashBP = 2 BPDuringExecution = 0 [CFI] CFISize = 0x00 CFIAddr = 0x00 [CPU] OverrideMemMap = 0 AllowSimulation = 1 ScriptFile="" [FLASH] CacheExcludeSize = 0x00 CacheExcludeAddr = 0x00 MinNumBytesFlashDL = 0 SkipProgOnCRCMatch = 1 VerifyDownload = 1 AllowCaching = 1 EnableFlashDL = 2 Override = 0 Device="UNSPECIFIED" [GENERAL] WorkRAMSize = 0x00 WorkRAMAddr = 0x00 RAMUsageLimit = 0x00 [SWO] SWOLogFile="" [MEM] RdOverrideOrMask = 0x00 RdOverrideAndMask = 0xFFFFFFFF RdOverrideAddr = 0xFFFFFFFF WrOverrideOrMask = 0x00 WrOverrideAndMask = 0xFFFFFFFF WrOverrideAddr = 0xFFFFFFFF ================================================ FILE: Project/stm32f4_dmp.uvopt ================================================ 1.0
### uVision Project, (C) Keil Software
*.c *.s*; *.src; *.a* *.obj *.lib *.txt; *.h; *.inc *.plm *.cpp 0 0 stm32f4_dmp 0x4 ARM-ADS 12000000 1 1 1 0 1 65535 0 0 0 79 66 8 .\stm32f4_dmp\ 1 1 1 0 1 1 0 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 0 1 255 0 Datasheet DATASHTS\ST\STM32F4xx\DM00037051.pdf 1 Reference Manual DATASHTS\ST\STM32F4xx\DM00031020.pdf 2 Technical Reference Manual datashts\arm\cortex_m4\r0p1\DDI0439C_CORTEX_M4_R0P1_TRM.PDF 3 Generic User Guide datashts\arm\cortex_m4\r0p1\DUI0553A_CORTEX_M4_DGUG.PDF 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 0 0 0 6 Segger\JL2CM3.dll 0 DLGTARM (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) 0 ARMDBGFLAGS 0 DLGUARM 0 JL2CM3 -U20150425 -O143 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06413041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL080000 0 UL2CM3 UL2CM3(-O207 -S0 -C0 -FO7 -FN1 -FC800 -FD20000000 -FF0STM32F4xx_1024 -FL0100000 -FS08000000 0 0 267 1
134218738
0 0 0 0 0 1 ..\Common\src\Memory.c 1 0 127 1
134238024
0 0 0 0 0 1 ..\Application\Src\main.c 0 1 a,0x0A 1 1 b,0x0A 2 1 c,0x0A 3 1 d,0x0A 1 6 0x20004874 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Application 1 0 0 0 1 1 1 0 0 21 0 1 17 0 ..\Application\Src\stm32f4_rcc.c stm32f4_rcc.c 0 0 1 2 1 0 0 0 0 18 93 0 ..\Application\Src\stm32f4_delay.c stm32f4_delay.c 0 0 1 3 1 0 0 11 0 337 402 0 ..\Application\Src\stm32f4_mpu9250.c stm32f4_mpu9250.c 0 0 1 4 1 0 0 78 0 214 291 0 ..\Application\Src\main.c main.c 0 0 1 5 1 0 0 16 0 40 26 0 ..\Application\src\stm32f4_serial.c stm32f4_serial.c 0 0 1 6 1 0 0 15 0 110 165 0 ..\Application\src\stm32f4_ms5611.c stm32f4_ms5611.c 0 0 1 7 1 0 0 2 0 29 77 0 ..\Application\src\stm32f4_ublox.c stm32f4_ublox.c 0 0 STM32F4xx_StdPeriph_Driver 0 0 0 0 2 8 1 0 0 0 0 0 0 0 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_gpio.c stm32f4xx_gpio.c 0 0 2 9 1 0 0 0 0 0 0 0 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rcc.c stm32f4xx_rcc.c 0 0 2 10 1 0 0 0 0 0 0 0 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_exti.c stm32f4xx_exti.c 0 0 2 11 1 0 0 0 0 0 0 0 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\misc.c misc.c 0 0 2 12 1 0 0 0 0 0 0 0 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_syscfg.c stm32f4xx_syscfg.c 0 0 2 13 1 0 0 0 0 1159 1169 0 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_spi.c stm32f4xx_spi.c 0 0 2 14 1 0 0 0 0 0 0 0 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_crc.c stm32f4xx_crc.c 0 0 2 15 1 0 0 0 0 0 0 0 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dma.c stm32f4xx_dma.c 0 0 2 16 1 0 0 0 0 0 0 0 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_flash.c stm32f4xx_flash.c 0 0 2 17 1 0 0 0 0 0 0 0 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_tim.c stm32f4xx_tim.c 0 0 2 18 1 0 0 0 0 0 0 0 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_usart.c stm32f4xx_usart.c 0 0 CMSIS 0 0 0 0 3 19 1 0 0 28 0 515 546 0 ..\Application\Src\system_stm32f4xx.c system_stm32f4xx.c 0 0 3 20 2 0 0 0 0 165 184 0 ..\Libraries\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f40_41xxx.s startup_stm32f40_41xxx.s 0 0 eMPL 0 0 0 0 4 21 1 0 0 0 0 2975 2982 0 ..\Libraries\eMPL\inv_mpu.c inv_mpu.c 0 0 4 22 1 0 0 0 0 0 0 0 ..\Libraries\eMPL\inv_mpu_dmp_motion_driver.c inv_mpu_dmp_motion_driver.c 0 0 Algorithm 1 0 0 0 5 23 1 0 0 29 0 20 40 0 ..\Algorithm\src\EKF.c EKF.c 0 0 5 24 1 0 0 29 0 16 40 0 ..\Algorithm\src\UKF.c UKF.c 0 0 5 25 1 0 0 19 0 162 244 0 ..\Algorithm\src\Quaternion.c Quaternion.c 0 0 5 26 1 0 0 11 0 1 24 0 ..\Algorithm\src\PID.c PID.c 0 0 5 27 1 0 0 15 0 223 257 0 ..\Algorithm\src\INS_EKF.c INS_EKF.c 0 0 5 28 1 0 0 21 0 21 49 0 ..\Algorithm\src\SRCKF.c SRCKF.c 0 0 5 29 1 0 0 29 0 16 40 0 ..\Algorithm\src\CKF.C CKF.C 0 0 5 30 5 0 0 0 0 0 0 0 ..\Algorithm\inc\Double.h Double.h 0 0 Matrix 1 0 0 0 6 31 1 0 0 1 0 1 28 0 ..\Matrix\src\Matrix.c Matrix.c 0 0 6 32 1 0 0 0 0 1 27 0 ..\Matrix\src\DoubleMatrix.c DoubleMatrix.c 0 0 DSP_Lib 1 0 0 0 7 33 4 0 0 0 0 0 0 0 ..\Libraries\CMSIS\DSP_Lib\Lib\arm_cortexM4lf_math.lib arm_cortexM4lf_math.lib 0 0 Drivers 1 0 0 0 8 34 1 0 0 53 0 2 21 0 ..\Drivers\src\stm32f4_spi.c stm32f4_spi.c 0 0 8 35 1 0 0 16 0 1 25 0 ..\Drivers\src\stm32f4_usart.c stm32f4_usart.c 0 0 8 36 1 0 0 0 0 0 0 0 ..\Drivers\src\stm32f4_exti.c stm32f4_exti.c 0 0 8 37 1 0 0 0 0 0 0 0 ..\Drivers\src\stm32f4_gpio.c stm32f4_gpio.c 0 0 Math 1 0 0 0 9 38 1 0 0 13 0 609 674 0 ..\Math\src\FastMath.c FastMath.c 0 0 miniIMU 1 0 0 0 10 39 1 0 0 40 0 135 161 0 ..\miniIMU\miniIMU.c miniIMU.c 0 0 10 40 1 0 0 0 0 1 1 0 ..\miniIMU\miniMatrix.c miniMatrix.c 0 0 FP_miniIMU 1 0 0 0 11 41 1 0 0 2 0 26 27 0 ..\miniIMU\FP\FP_Matrix.c FP_Matrix.c 0 0 11 42 1 0 0 8 0 46 30 0 ..\miniIMU\FP\FP_miniIMU.c FP_miniIMU.c 0 0 11 43 1 0 0 9 0 1 27 0 ..\miniIMU\FP\FP_Math.c FP_Math.c 0 0 miniAHRS 1 0 0 0 12 44 1 0 0 2 0 28 29 0 ..\miniAHRS\miniAHRS.c miniAHRS.c 0 0 Data 1 0 0 0 13 45 1 0 0 0 0 1 1 0 ..\Data\src\Fifo.c Fifo.c 0 0 13 46 1 0 0 18 0 1 44 0 ..\Data\src\Queue.c Queue.c 0 0 Gps 1 0 0 0 14 47 1 0 0 25 0 302 374 0 ..\Gps\src\Nema.c Nema.c 0 0 14 48 1 0 0 0 0 59 97 0 ..\Gps\src\Map.c Map.c 0 0 Common 1 0 0 0 15 49 1 0 0 16 0 137 191 0 ..\Common\src\Memory.c Memory.c 0 0 ================================================ FILE: Project/stm32f4_dmp.uvproj ================================================ 1.1
### uVision Project, (C) Keil Software
stm32f4_dmp 0x4 ARM-ADS STM32F407VG STMicroelectronics IRAM(0x20000000-0x2001FFFF) IRAM2(0x10000000-0x1000FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M4") FPU2 "Startup\ST\STM32F4xx\startup_stm32f40_41xxx.s" ("STM32F40/41xxx Startup Code") UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F4xx_1024 -FS08000000 -FL0100000) 6103 stm32f4xx.h -DSTM32F40_41xxx SFD\ST\STM32F4xx\STM32F40x.sfr 0 0 ST\STM32F4xx\ ST\STM32F4xx\ 0 0 0 0 1 .\stm32f4_dmp\ stm32f4_dmp 1 0 0 1 1 .\stm32f4_dmp\ 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 C:\Keil\ARM\ARMCC\bin\fromelf.exe --bin -o .\stm32f4_dmp\stm32f4_dmp.bin .\stm32f4_dmp\stm32f4_dmp.axf 0 0 0 0 0 0 0 0 1 0 0 0 0 3 1 SARMCM3.DLL -MPU -REMAP DCM.DLL -pCM4 SARMCM3.DLL -MPU TCM.DLL -pCM4 1 0 0 0 16 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 0 0 6 Segger\JL2CM3.dll 1 0 0 1 1 4096 1 BIN\UL2CM3.DLL 0 0 1 1 1 1 1 1 1 0 1 1 0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 "Cortex-M4" 0 0 0 1 1 0 0 2 1 0 8 0 0 0 3 3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0x0 0x0 0 0x0 0x0 0 0x0 0x0 0 0x0 0x0 0 0x0 0x0 0 0x0 0x0 0 0x20000000 0x20000 1 0x8000000 0x100000 0 0x0 0x0 1 0x0 0x0 1 0x0 0x0 1 0x0 0x0 1 0x8000000 0x100000 1 0x0 0x0 0 0x0 0x0 0 0x0 0x0 0 0x0 0x0 0 0x20000000 0x20000 0 0x10000000 0x10000 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 USE_STDPERIPH_DRIVER STM32F40_41xxx ARM_MATH_CM4 __FPU_PRESENT MPU9250 ..\Libraries\CMSIS\Include;..\Libraries\CMSIS\ST\STM32F4xx\Include;..\Libraries\STM32F4xx_StdPeriph_Driver\inc;..\Drivers\inc;..\Application\inc;..\Libraries\eMPL;..\Matrix\inc;..\Algorithm\inc;..\Math\inc;..\miniIMU;..\miniIMU\FP;..\miniAHRS;..\Data\inc;..\Gps\inc;..\Common\inc 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0x08000000 0x20000000 .\stm32f4_vcp\stm32f4_vcp.sct Application stm32f4_rcc.c 1 ..\Application\Src\stm32f4_rcc.c stm32f4_delay.c 1 ..\Application\Src\stm32f4_delay.c stm32f4_mpu9250.c 1 ..\Application\Src\stm32f4_mpu9250.c main.c 1 ..\Application\Src\main.c stm32f4_serial.c 1 ..\Application\src\stm32f4_serial.c stm32f4_ms5611.c 1 ..\Application\src\stm32f4_ms5611.c stm32f4_ublox.c 1 ..\Application\src\stm32f4_ublox.c STM32F4xx_StdPeriph_Driver stm32f4xx_gpio.c 1 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_gpio.c stm32f4xx_rcc.c 1 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rcc.c stm32f4xx_exti.c 1 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_exti.c misc.c 1 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\misc.c stm32f4xx_syscfg.c 1 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_syscfg.c stm32f4xx_spi.c 1 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_spi.c stm32f4xx_crc.c 1 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_crc.c stm32f4xx_dma.c 1 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dma.c stm32f4xx_flash.c 1 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_flash.c stm32f4xx_tim.c 1 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_tim.c stm32f4xx_usart.c 1 ..\Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_usart.c CMSIS system_stm32f4xx.c 1 ..\Application\Src\system_stm32f4xx.c startup_stm32f40_41xxx.s 2 ..\Libraries\CMSIS\Device\ST\STM32F4xx\Source\Templates\arm\startup_stm32f40_41xxx.s eMPL inv_mpu.c 1 ..\Libraries\eMPL\inv_mpu.c inv_mpu_dmp_motion_driver.c 1 ..\Libraries\eMPL\inv_mpu_dmp_motion_driver.c Algorithm EKF.c 1 ..\Algorithm\src\EKF.c UKF.c 1 ..\Algorithm\src\UKF.c Quaternion.c 1 ..\Algorithm\src\Quaternion.c PID.c 1 ..\Algorithm\src\PID.c INS_EKF.c 1 ..\Algorithm\src\INS_EKF.c SRCKF.c 1 ..\Algorithm\src\SRCKF.c CKF.C 1 ..\Algorithm\src\CKF.C Double.h 5 ..\Algorithm\inc\Double.h Matrix Matrix.c 1 ..\Matrix\src\Matrix.c DoubleMatrix.c 1 ..\Matrix\src\DoubleMatrix.c DSP_Lib arm_cortexM4lf_math.lib 4 ..\Libraries\CMSIS\DSP_Lib\Lib\arm_cortexM4lf_math.lib Drivers stm32f4_spi.c 1 ..\Drivers\src\stm32f4_spi.c stm32f4_usart.c 1 ..\Drivers\src\stm32f4_usart.c stm32f4_exti.c 1 ..\Drivers\src\stm32f4_exti.c stm32f4_gpio.c 1 ..\Drivers\src\stm32f4_gpio.c Math FastMath.c 1 ..\Math\src\FastMath.c miniIMU miniIMU.c 1 ..\miniIMU\miniIMU.c miniMatrix.c 1 ..\miniIMU\miniMatrix.c FP_miniIMU FP_Matrix.c 1 ..\miniIMU\FP\FP_Matrix.c FP_miniIMU.c 1 ..\miniIMU\FP\FP_miniIMU.c FP_Math.c 1 ..\miniIMU\FP\FP_Math.c miniAHRS miniAHRS.c 1 ..\miniAHRS\miniAHRS.c Data Fifo.c 1 ..\Data\src\Fifo.c Queue.c 1 ..\Data\src\Queue.c Gps Nema.c 1 ..\Gps\src\Nema.c Map.c 1 ..\Gps\src\Map.c Common Memory.c 1 ..\Common\src\Memory.c ================================================ FILE: README.md ================================================ # stm32f4_mpu9250 Access the data of 3-axis magnetometer and DMP from MPU9250 with SPI interface All data fusion (including the data of dmp output, such as the accelerometer data, gyroscope, 6-axis quaternion and internal magnetometer data) via a 7-state, 13-mesurement EKF(Extended Kalman filter) / Unscented Kalman Filter(UKF) / Cubature Kalman Filters (CKF) Algorithm / Square-Root Cubature Kalman Filters (SRCKF) Algorithm. 1.kalman feature: prediction state: q0 q1 q2 q3 wx wy wz mesurement:q0 q1 q2 q3(q0~q3 from dmp ouput) ax ay az wx wy wz mx my mz 2.Add a miniIMU for doctor's miniQuadrotor add a new fixed-point ekf algorithm for doctor's miniQuadrotor please check the miniIMU directory at the root and look the usage.txt for using! 3.Add a win32 application for serial port communication calibraion for accelerometer, gyroscope, magnetometer please check the "Calibration App" directory at the root 4.Add a miniAHRS for 9-axis fusion, such as ax ay az wx wy wz mx my mz form accelerometer,gyroscope,magnetometer 7-state ekf algorithm: quaternion and 3-axis gyroscope bais 3-mesurement for accelerometer 3-mesurement for magnetometer 5.Add a GPS/ins implement via ekf fusion algorithm 16-state ekf algorithm: 4 quaternion, 3D postion, 3D velocity, 3-axis gyroscope bais and 3-axis accelerometer bais 9-mesurement for magnetometer, 3D postion and 3D velocity from gps and barometer 6.Other stuff add ms5611 spi driver using 4-order Runge_Kutta to slove the quaternion differential equation. 7.Add a 9-axis sensor fusion with square-root cubature Kalman filter for testing 7-state srckf algorithm: quaternion and 3-axis gyroscope bais 6-mesurement for accelerometer, magnetometer ouput 8.add ublox-m8n uart4 driver 9.Emulated double precision Double single routine ================================================ FILE: miniAHRS/miniAHRS.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "FastMath.h" #include "Quaternion.h" #include "miniAHRS.h" #include "miniMatrix.h" ////////////////////////////////////////////////////////////////////////// // //all parameters below need to be tune #define EKF_PQ_INITIAL 0.001f #define EKF_PWB_INITIAL 0.001f #define EKF_QQ_INITIAL 0.05f #define EKF_QWB_INITIAL 0.0000005f #define EKF_RA_INITIAL 0.005346f #define EKF_RM_INITIAL 0.005346f ////////////////////////////////////////////////////////////////////////// // #define UPDATE_P_COMPLICATED #ifdef UPDATE_P_COMPLICATED static float I[EKF_STATE_DIM * EKF_STATE_DIM] = { 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, }; #endif static float P[EKF_STATE_DIM * EKF_STATE_DIM] = { EKF_PQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_PQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_PQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_PQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_PWB_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_PWB_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_PWB_INITIAL, }; static float Q[EKF_STATE_DIM * EKF_STATE_DIM] = { EKF_QQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_QQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_QQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_QQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_QWB_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_QWB_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_QWB_INITIAL, }; static float R[EKF_MEASUREMENT_DIM * EKF_MEASUREMENT_DIM] = { EKF_RA_INITIAL, 0, 0, 0, 0, 0, 0, EKF_RA_INITIAL, 0, 0, 0, 0, 0, 0, EKF_RA_INITIAL, 0, 0, 0, 0, 0, 0, EKF_RM_INITIAL, 0, 0, 0, 0, 0, 0, EKF_RM_INITIAL, 0, 0, 0, 0, 0, 0, EKF_RM_INITIAL, }; static float F[EKF_STATE_DIM * EKF_STATE_DIM] = { 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, }; static float H[EKF_MEASUREMENT_DIM * EKF_STATE_DIM] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; //state static float X[EKF_STATE_DIM]; static float KY[EKF_STATE_DIM]; //measurement static float Y[EKF_MEASUREMENT_DIM]; // static float CBn[9]; // static float PX[EKF_STATE_DIM * EKF_STATE_DIM]; static float PXX[EKF_STATE_DIM * EKF_STATE_DIM]; static float PXY[EKF_STATE_DIM * EKF_MEASUREMENT_DIM]; static float K[EKF_STATE_DIM * EKF_MEASUREMENT_DIM]; static float S[EKF_MEASUREMENT_DIM * EKF_MEASUREMENT_DIM]; static void Calcultate_RotationMatrix(float *accel, float *mag, float *R) { // local variables float norm, fmodx, fmody; // place the un-normalized gravity and geomagnetic vectors into // the rotation matrix z and x axes R[2] = accel[0]; R[5] = accel[1]; R[8] = accel[2]; R[0] = mag[0]; R[3] = mag[1]; R[6] = mag[2]; // set y vector to vector product of z and x vectors R[1] = R[5] * R[6] - R[8] * R[3]; R[4] = R[8] * R[0] - R[2] * R[6]; R[7] = R[2] * R[3] - R[5] * R[0]; // set x vector to vector product of y and z vectors R[0] = R[4] * R[8] - R[7] * R[5]; R[3] = R[7] * R[2] - R[1] * R[8]; R[6] = R[1] * R[5] - R[4] * R[2]; // calculate the vector moduli invert norm = FastSqrtI(accel[0] * accel[0] + accel[1] * accel[1] + accel[2] * accel[2]); fmodx = FastSqrtI(R[0] * R[0] + R[3] * R[3] + R[6] * R[6]); fmody = FastSqrtI(R[1] * R[1] + R[4] * R[4] + R[7] * R[7]); // normalize the rotation matrix // normalize x axis R[0] *= fmodx; R[3] *= fmodx; R[6] *= fmodx; // normalize y axis R[1] *= fmody; R[4] *= fmody; R[7] *= fmody; // normalize z axis R[2] *= norm; R[5] *= norm; R[8] *= norm; } void EKF_AHRSInit(float *accel, float *mag) { //3x3 rotation matrix float R[9]; Calcultate_RotationMatrix(accel, mag, R); Quaternion_FromRotationMatrix(R, X); } void EKF_AHRSUpdate(float *gyro, float *accel, float *mag, float dt) { float norm; float halfdx, halfdy, halfdz; float neghalfdx, neghalfdy, neghalfdz; float halfdtq0, neghalfdtq0, halfdtq1, neghalfdtq1, halfdtq2, neghalfdtq2, halfdtq3, neghalfdtq3; float halfdt = 0.5f * dt; ////////////////////////////////////////////////////////////////////////// float _2q0,_2q1,_2q2,_2q3; float q0q0, q0q1, q0q2, q0q3, q1q1, q1q2, q1q3, q2q2, q2q3, q3q3; float q0, q1, q2, q3; float _2mx, _2my, _2mz; float hx, hy, hz; float bx, bz; // float SI[EKF_MEASUREMENT_DIM * EKF_MEASUREMENT_DIM] = {0}; ////////////////////////////////////////////////////////////////////////// halfdx = halfdt * (gyro[0] - X[4]); halfdy = halfdt * (gyro[1] - X[5]); halfdz = halfdt * (gyro[2] - X[6]); neghalfdx = -halfdx; neghalfdy = -halfdy; neghalfdz = -halfdz; // q0 = X[0]; q1 = X[1]; q2 = X[2]; q3 = X[3]; ////////////////////////////////////////////////////////////////////////// //Extended Kalman Filter: Prediction Step //state time propagation //Update Quaternion with the new gyroscope measurements X[0] = q0 - halfdx * q1 - halfdy * q2 - halfdz * q3; X[1] = q1 + halfdx * q0 - halfdy * q3 + halfdz * q2; X[2] = q2 + halfdx * q3 + halfdy * q0 - halfdz * q1; X[3] = q3 - halfdx * q2 + halfdy * q1 + halfdz * q0; //normalize quaternion norm = FastSqrtI(X[0] * X[0] + X[1] * X[1] + X[2] * X[2] + X[3] * X[3]); X[0] *= norm; X[1] *= norm; X[2] *= norm; X[3] *= norm; //populate F jacobian halfdtq0 = halfdt * q0; halfdtq1 = halfdt * q1; halfdtq2 = halfdt * q2; halfdtq3 = halfdt * q3; neghalfdtq0 = -halfdtq0; neghalfdtq1 = -halfdtq1; neghalfdtq2 = -halfdtq2; neghalfdtq3 = -halfdtq3; /* F[0] = 1.0f; */ F[1] = neghalfdx; F[2] = neghalfdy; F[3] = neghalfdz; F[4] = halfdtq1; F[5] = halfdtq2; F[6] = halfdtq3; F[7] = halfdx; /* F[8] = 1.0f; */ F[9] = halfdz; F[10] = neghalfdy; F[11] = neghalfdtq0; F[12] = halfdtq3; F[13] = neghalfdtq2; F[14] = halfdy; F[15] = neghalfdz; /* F[16] = 1.0f; */ F[17] = halfdx; F[18] = neghalfdtq3; F[19] = neghalfdtq0; F[20] = halfdtq1; F[21] = halfdz; F[22] = halfdy; F[23] = neghalfdx; /* F[24] = 1.0f; */ F[25] = halfdtq2; F[26] = neghalfdtq1; F[27] = neghalfdtq0; //covariance time propagation //P = F*P*F' + Q; Matrix_Multiply(F, EKF_STATE_DIM, EKF_STATE_DIM, P, EKF_STATE_DIM, PX); Matrix_Multiply_With_Transpose(PX, EKF_STATE_DIM, EKF_STATE_DIM, F, EKF_STATE_DIM, P); Maxtrix_Add(P, EKF_STATE_DIM, EKF_STATE_DIM, Q, P); ////////////////////////////////////////////////////////////////////////// //measurement update //normalize accel and magnetic norm = FastSqrtI(accel[0] * accel[0] + accel[1] * accel[1] + accel[2] * accel[2]); accel[0] *= norm; accel[1] *= norm; accel[2] *= norm; norm = FastSqrtI(mag[0] * mag[0] + mag[1] * mag[1] + mag[2] * mag[2]); mag[0] *= norm; mag[1] *= norm; mag[2] *= norm; //Reference field calculation //auxiliary variables to avoid repeated arithmetic _2q0 = 2.0f * X[0]; _2q1 = 2.0f * X[1]; _2q2 = 2.0f * X[2]; _2q3 = 2.0f * X[3]; // q0q0 = X[0] * X[0]; q0q1 = X[0] * X[1]; q0q2 = X[0] * X[2]; q0q3 = X[0] * X[3]; q1q1 = X[1] * X[1]; q1q2 = X[1] * X[2]; q1q3 = X[1] * X[3]; q2q2 = X[2] * X[2]; q2q3 = X[2] * X[3]; q3q3 = X[3] * X[3]; _2mx = 2.0f * mag[0]; _2my = 2.0f * mag[1]; _2mz = 2.0f * mag[2]; hx = _2mx * (0.5f - q2q2 - q3q3) + _2my * (q1q2 - q0q3) + _2mz *(q1q3 + q0q2); hy = _2mx * (q1q2 + q0q3) + _2my * (0.5f - q1q1 - q3q3) + _2mz * (q2q3 - q0q1); hz = _2mx * (q1q3 - q0q2) + _2my * (q2q3 + q0q1) + _2mz *(0.5f - q1q1 - q2q2); bx = FastSqrt(hx * hx + hy * hy); bz = hz; // Y[0] = -2.0f * (q1q3 - q0q2); Y[1] = -2.0f * (q2q3 + q0q1); Y[2] = 1.0f - 2.0f * (q0q0 + q3q3); Y[3] = bx * (1.0f - 2.0f * (q2q2 + q3q3)) + bz * ( 2.0f * (q1q3 - q0q2)); Y[4] = bx * (2.0f * (q1q2 - q0q3)) + bz * (2.0f * (q2q3 + q0q1)); Y[5] = bx * (2.0f * (q1q3 + q0q2)) + bz * (1.0f - 2.0f * (q1q1 + q2q2)); Y[0] = accel[0] - Y[0]; Y[1] = accel[1] - Y[1]; Y[2] = accel[2] - Y[2]; Y[3] = mag[0] - Y[3]; Y[4] = mag[1] - Y[4]; Y[5] = mag[2] - Y[5]; //populate H jacobian H[0] = _2q2; H[1] = -_2q3; H[2] = _2q0; H[3] = -_2q1; H[7] = -_2q1; H[8] = -_2q0; H[9] = -_2q3; H[10] = -_2q2; H[14] = -_2q0; H[15] = _2q1; H[16] = _2q2; H[17] = -_2q3; H[21] = bx * _2q0 - bz * _2q2; H[22] = bx * _2q1 + bz * _2q3; H[23] = -bx * _2q2 - bz * _2q0; H[24] = bz * _2q1 - bx * _2q3; H[28] = bz * _2q1 - bx * _2q3; H[29] = bx * _2q2 + bz * _2q0; H[30] = bx * _2q1 + bz * _2q3; H[31] = bz * _2q2 - bx * _2q0; H[35] = bx * _2q2 + bz * _2q0; H[36] = bx * _2q3 - bz * _2q1; H[37] = bx * _2q0 - bz * _2q2; H[38] = bx * _2q1 + bz * _2q3; //kalman gain calculation //K = P * H' / (R + H * P * H') //acceleration of gravity Matrix_Multiply_With_Transpose(P, EKF_STATE_DIM, EKF_STATE_DIM, H, EKF_MEASUREMENT_DIM, PXY); Matrix_Multiply(H, EKF_MEASUREMENT_DIM, EKF_STATE_DIM, PXY, EKF_MEASUREMENT_DIM, S); Maxtrix_Add(S, EKF_MEASUREMENT_DIM, EKF_MEASUREMENT_DIM, R, S); Matrix_Inverse(S, EKF_MEASUREMENT_DIM, SI); Matrix_Multiply(PXY, EKF_STATE_DIM, EKF_MEASUREMENT_DIM, SI, EKF_MEASUREMENT_DIM, K); //update state vector //X = X + K * Y; Matrix_Multiply(K, EKF_STATE_DIM, EKF_MEASUREMENT_DIM, Y, 1, KY); Maxtrix_Add(X, EKF_STATE_DIM, 1, KY, X); //normalize quaternion norm = FastSqrtI(X[0] * X[0] + X[1] * X[1] + X[2] * X[2] + X[3] * X[3]); X[0] *= norm; X[1] *= norm; X[2] *= norm; X[3] *= norm; //covariance estimate update //P = (I - K * H) * P //P = P - K * H * P //or //P=(I - K*H)*P*(I - K*H)' + K*R*K' #ifndef UPDATE_P_COMPLICATED Matrix_Multiply(K, EKF_STATE_DIM, EKF_MEASUREMENT_DIM, H, EKF_STATE_DIM, PX); Matrix_Multiply(PX, EKF_STATE_DIM, EKF_STATE_DIM, P, EKF_STATE_DIM, PXX); Maxtrix_Add(P, EKF_STATE_DIM, EKF_STATE_DIM, PXX, P); #else Matrix_Multiply(K, EKF_STATE_DIM, EKF_MEASUREMENT_DIM, H, EKF_STATE_DIM, PX); Maxtrix_Sub(I, EKF_STATE_DIM, EKF_STATE_DIM, PX, PX); Matrix_Multiply(PX, EKF_STATE_DIM, EKF_STATE_DIM, P, EKF_STATE_DIM, PXX); Matrix_Multiply_With_Transpose(PXX, EKF_STATE_DIM, EKF_STATE_DIM, PX, EKF_STATE_DIM, P); Matrix_Multiply(K, EKF_STATE_DIM, EKF_MEASUREMENT_DIM, R, EKF_MEASUREMENT_DIM, PXY); Matrix_Multiply_With_Transpose(PXY, EKF_STATE_DIM, EKF_MEASUREMENT_DIM, K, EKF_STATE_DIM, PX); Maxtrix_Add(P, EKF_STATE_DIM, EKF_STATE_DIM, PX, P); #endif } void EKF_AHRSGetQ(float* Q) { Q[0] = X[0]; Q[1] = X[1]; Q[2] = X[2]; Q[3] = X[3]; } void EKF_AHRSGetAngle(float* rpy) { float q0q0 = X[0] * X[0]; //x-y-z CBn[0] = 2.0f * (q0q0 + X[1] * X[1]) - 1.0f; CBn[1] = 2.0f * (X[1] * X[2] + X[0] * X[3]); CBn[2] = 2.0f * (X[1] * X[3] - X[0] * X[2]); //CBn[3] = 2.0f * (X[1] * X[2] - X[0] * X[3]); //CBn[4] = 2.0f * (q0q0 + X[2] * X[2]) - 1.0f; CBn[5] = 2.0f * (X[2] * X[3] + X[0] * X[1]); //CBn[6] = 2.0f * (X[1] * X[3] + X[0] * X[2]); //CBn[7] = 2.0f * (X[2] * X[3] - X[0] * X[1]); CBn[8] = 2.0f * (q0q0 + X[3] * X[3]) - 1.0f; //roll rpy[0] = FastAtan2(CBn[5], CBn[8]); if (rpy[0] == EKF_PI) rpy[0] = -EKF_PI; //pitch if (CBn[2] >= 1.0f) rpy[1] = -EKF_HALFPI; else if (CBn[2] <= -1.0f) rpy[1] = EKF_HALFPI; else rpy[1] = FastAsin(-CBn[2]); //yaw rpy[2] = FastAtan2(CBn[1], CBn[0]); if (rpy[2] < 0.0f){ rpy[2] += EKF_TWOPI; } if (rpy[2] >= EKF_TWOPI){ rpy[2] = 0.0f; } rpy[0] = EKF_TODEG(rpy[0]); rpy[1] = EKF_TODEG(rpy[1]); rpy[2] = EKF_TODEG(rpy[2]); } ================================================ FILE: miniAHRS/miniAHRS.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef MINIAHRS_H_ #define MINIAHRS_H_ ////////////////////////////////////////////////////////////////////////// // #define EKF_STATE_DIM 7 //q0 q1 q2 q3 wxb wyb wzb #define EKF_MEASUREMENT_DIM 6 //ax ay az and mx my mz #define EKF_HALFPI 1.5707963267948966192313216916398f #define EKF_PI 3.1415926535897932384626433832795f #define EKF_TWOPI 6.283185307179586476925286766559f #define EKF_TODEG(x) ((x) * 57.2957796f) void EKF_AHRSInit(float *accel, float *mag); void EKF_AHRSUpdate(float *gyro, float *accel, float *mag, float dt); void EKF_AHRSGetAngle(float* rpy); void EKF_AHRSGetQ(float* Q); #endif ================================================ FILE: miniIMU/FP/FP_Math.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "FP_Math.h" typedef union { long i; float f; }L2F; ////////////////////////////////////////////////////////////////////////// //S16.16 Q16 FT_Q16(float f) { L2F l2f; int ival; int exponent; l2f.f = f; ival= (l2f.i & 0x07fffff) | 0x800000; exponent = 150 - ((l2f.i >> 23) & 0xff); if (exponent < 0) ival = ival << (-exponent - 16); else ival = ival >> (exponent - 16); if (l2f.i & 0x80000000){ ival = -ival; } return ival; } #ifdef OPTIMIZE_SDIV //translate from arm-gcc build-in toolchain //cortex-m3's instruction assembly optimization //div signed 32bit << 16 / signed 32bit = signed 32bit __asm Q16 FP_SDIV(Q16 num, Q16 den) { //num r0, den r1, mod r2, cnt r3, quo r4, sign r12 //set sign and ensure numerator and denominator are positive cmp r1, #0; //exceptioin if den == zero beq div0; // eor r12, r0, r1; //sign = num ^ den rsbmi r1, r1, #0; //den = -den if den < 0 subs r2, r1, #1; //mod = den - 1 beq div1; //return if den == 1 movs r3, r0; //num = -num if num < 0 rsbmi r0, r0, #0; //skip if deniminator >= numerator movs r3, r0, lsr #16; //return if den >= num << 16 bne cont; cmp r1, r0, lsl #16; bhs numLeDen; cont //test if denominator is a power of two tst r1, r2; //if(den & (den - 1) == 0) beq powerOf2; //den is power of 2 stmfd sp!, {r4};// push r4 (quo) onto the stack //count leading zeros clz r2, r1; clz r3, r0; sub r2, r2, r3; rsb r3, r2, #31; and r3, r3, #30; rsb r2, r3, #32; mov r2, r0, lsr r2; mov r0, r0, lsl r3; rsb r3, r3, #32 + 16 mov r4, #0 rsb r1, r1, #0; //negate den for divide loop inner_loop adds r0, r0, r0; //start: num = mod:num / den adcs r2, r1, r2, lsl #1; subcc r2, r2, r1; adc r4, r4, r4; subs r3, r3, #1; bne inner_loop // negate quotient if signed cmp r12, #0; //negate quotient if sign < 0 mov r0, r4 rsbmi r0, r0, #0; ldmfd sp!, {r4}; // pop r4 (quo) off the stack bx lr; //return //divide by zero handler div0 mov r0, #0 bx lr; //return //divide by one handler div1 cmp r12, #0 mov r0, r0, lsl #16//mov r0, r0, asl #16 rsbmi r0, r0, #0 bx lr; //return //numerator less than or equal to denominator handler numLeDen mov r0, #0; //quotient = 0 if num < den moveq r0, r12, asr #31; //negate quotient if sign < 0 orreq r0, r0, #1; //quotient = 1 if num == den bx lr; //return //power of two handler powerOf2 clz r3, r1; rsb r3, r3, #31; rsb r2, r3, #32 mov r1, r0, lsr #16; //den:num = num << 16 mov r0, r0, lsl #16 mov r0, r0, lsr r3; //num = num >> cnt | den << mod //orr r0, r0, r1, lsl r2 lsl r1, r1, r2; orr r0, r0, r1 cmp r12, #0 rsbmi r0, r0, #0; //negate quotient if sign < 0" bx lr } #else //udiv64_32 __asm uint32_t UDIV64(uint32_t a, uint32_t b, uint32_t c) { adds r0, r0, r0; adc r1, r1, r1; mov r3, #31; loop cmp r1, r2; subcs r1, r1, r2; adcs r0, r0, r0; adc r1, r1, r1; sub r3, r3, #1; cmp r3, #0; bne loop cmp r1, r2; subcs r1, r1, r2; adcs r0, r0, r0; bx lr; } //div 32bit << 16 / 32bit Q16 FP_SDIV(Q16 a, Q16 b) { int q; //different signs int sign = (a^b) < 0; uint32_t l,h; a = a < 0 ? -a : a; b = b < 0 ? -b : b; l = (a << 16); h = (a >> 16); q = UDIV64(l, h, b); if (sign){ q = -q; } return q; } #endif static const uint8_t ISQRT_LUT[256] ={ 150,149,148,147,146,145,144,143,142,141,140,139,138,137,136,135, 134,133,132,131,131,130,129,128,127,126,125,124,124,123,122,121, 120,119,119,118,117,116,115,114,114,113,112,111,110,110,109,108, 107,107,106,105,104,104,103,102,101,101,100, 99, 98, 98, 97, 96, 95, 95, 94, 93, 93, 92, 91, 91, 90, 89, 88, 88, 87, 86, 86, 85, 84, 84, 83, 82, 82, 81, 80, 80, 79, 79, 78, 77, 77, 76, 75, 75, 74, 74, 73, 72, 72, 71, 70, 70, 69, 69, 68, 67, 67, 66, 66, 65, 65, 64, 63, 63, 62, 62, 61, 61, 60, 59, 59, 58, 58, 57, 57, 56, 56, 55, 54, 54, 53, 53, 52, 52, 51, 51, 50, 50, 49, 49, 48, 48, 47, 47, 46, 46, 45, 45, 44, 44, 43, 43, 42, 42, 41, 41, 40, 40, 39, 39, 38, 38, 37, 37, 36, 36, 35, 35, 34, 34, 33, 33, 33, 32, 32, 31, 31, 30, 30, 29, 29, 28, 28, 28, 27, 27, 26, 26, 25, 25, 25, 24, 24, 23, 23, 22, 22, 22, 21, 21, 20, 20, 19, 19, 19, 18, 18, 17, 17, 17, 16, 16, 15, 15, 15, 14, 14, 13, 13, 13, 12, 12, 11, 11, 11, 10, 10, 9, 9, 9, 8, 8, 8, 7, 7, 6, 6, 6, 5, 5, 5, 4, 4, 3, 3, 3, 2, 2, 2, 1, 1, 1, 0, 0 }; uint32_t FP_SqrtC(uint32_t mant, int expn, uint32_t iter) { uint32_t m2 = mant / 2; //Half mantissa temporary uint32_t est; //Inverse square root estimate //look up the initial guess from mantissa MSBs est = (uint32_t)(ISQRT_LUT[(mant >> 23) & 0xff] + 362) << 22; //iterate newton step: est = est*(3 - mant*est*est)/2 switch (iter) { default: case 2: est = FP_ISQRT_UPDATE(est, m2); //fall through case 1: est = FP_ISQRT_UPDATE(est, m2); case 0: ; //no action } //adjust estimate by 1/sqrt(2) if exponent is odd if (expn & 1) { est = (uint32_t)FP_UMUL_FRAC(est, 0xb504f334UL, 31); } return est; } __asm uint8_t CLZ(uint32_t value) { mov r1, r0; clz r0, r1 bx lr; //return } Q16 FP_Sqrt(Q16 xval, uint32_t frac) { const uint8_t iter[] = {0, 1, 2, 2}; //result bits to #iter LUT uint32_t est; //estimated value uint32_t mant; //floating-point mantissa int expn; //floating-point exponent int nz; //handle illegal values if (xval < 0 || frac > 31) { return -1; } //handle the trivial case if (xval == 0) { return 0; } //convert fixed-point number to floating-point with 32-bit mantissa nz = CLZ(xval); mant = xval << nz; expn = 31 - nz - frac; //call inverse square root core function est = FP_SqrtC(mant, expn, iter[((expn >> 1) + frac) >> 3]); //multiply estimation by mant to produce the square root est = FP_UMUL_FRAC(est, mant, 31); //the square root of the exponent expn >>= 1; //convert back to fixed-point return est >> (31 - expn - frac); } Q16 FP_SqrtI(Q16 xval, int32_t frac) { uint32_t est; //estimated value uint32_t mant; //floating-point mantissa int expn; //floating-point exponent int nz; //handle illegal values if (xval <= 0 || frac > 31) { return -1; } //convert fixed-point number to floating-point with 32-bit mantissa nz = CLZ(xval); mant = xval << nz; expn = 31 - nz - frac; //call inverse square root core function est = FP_SqrtC(mant, expn, 2); //the square root of the exponent expn = -expn >> 1; //convert back to fixed-point return est >> (31 - expn - frac); } ////////////////////////////////////////////////////////////////////////// //translate from google's skia fixed-point dsp Library. // const int ATAN_TABLE[] = { 0x20000000, 0x12E4051D, 0x9FB385B, 0x51111D4, 0x28B0D43, 0x145D7E1, 0xA2F61E, 0x517C55, 0x28BE53, 0x145F2E, 0xA2F98, 0x517CC, 0x28BE6, 0x145F3, 0xA2F9, 0x517C, 0x28BE, 0x145F, 0xA2F, 0x517, 0x28B, 0x145, 0xA2, 0x51, 0x28, 0x14, 0xA, 0x5, 0x2, 0x1 }; __asm Q16 FP_ScaleBack(Q16 a, Q16 s) { smull r3, r4, r0, r1; mov r0, r4; bx lr; //return } Q16 FP_FastAsin(Q16 a) { int x, y, z; int x1, y1, z1, t, tan; int sign = a >> 31; const int* tanPtr = ATAN_TABLE; if(a < 0){ z = -a; } else{ z = a; } if (z >= Q16_One){ return (Q16_HALFPI ^ (~sign)) - sign; } x = 0x18bde0bb; //gain parameter 0.607252935 y = 0; z *= 0x28be; z1 = 0; t = 0; do { x1 = y >> t; y1 = x >> t; tan = *tanPtr++; if (y < z) { x -= x1; y += y1; z1 -= tan; } else { x += x1; y -= y1; z1 += tan; } } while (++t < 16); // 30 //scale back into the scalar space (0x100000000/0x28be = #0x6488d) z = FP_ScaleBack(z1, 0x6488d); z = (z ^ (~sign)) - sign; return z; } Q16 FP_FastAtan2(Q16 y, Q16 x) { int xsign, rsign; int pi, result; int z, t; int x1, y1, tan; const int* tanPtr = ATAN_TABLE; if ((x | y) == 0){ return 0; } xsign = x >> 31; if(x < 0){ x = -x; } z = 0; t = 0; do { x1 = y >> t; y1 = x >> t; tan = *tanPtr++; if (y < 0) { x -= x1; y += y1; z -= tan; } else{ x += x1; y -= y1; z += tan; } } while (++t < 16); // 30 //cortex-m3's instruction assembly optimization //scale back into the scalar space (0x100000000/0x28be = #0x6488d) result = FP_ScaleBack(z, 0x6488d); if (xsign) { rsign = result >> 31; if (y == 0){ rsign = 0; } pi = (Q16_PI ^ (~rsign)) - rsign; result = pi - result; } return result; } ================================================ FILE: miniIMU/FP/FP_Math.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _FP_FASTMATH_H_ #define _FP_FASTMATH_H_ #define FIXED_POINT #define PRECISION 16 #define OPTIMIZE_SDIV typedef int Q16; typedef int int32_t; typedef unsigned int uint32_t; typedef unsigned char uint8_t; typedef unsigned short uint16_t; typedef signed __int64 int64_t; typedef unsigned __int64 uint64_t; #define Q16_One 65536 ////////////////////////////////////////////////////////////////////////// //S16.16 #define FP_ADDS(a, b) ((a) + (b)) #define FP_SUBS(a, b) ((a) - (b)) #define FP_SMUL_FRAC(a, b, frac) \ ((int32_t)((int64_t)(a)*(int64_t)(b) >> (frac))) #define FP_UMUL_FRAC(a, b, frac) \ ((uint32_t)((uint64_t)(a)*(uint64_t)(b) >> (frac))) #define FP_SMUL(a, b) \ ((int32_t)((int64_t)(a)*(int64_t)(b) >> 16)) #define FP_UMUL(a, b) \ ((uint32_t)((uint64_t)(a)*(uint64_t)(b) >> 16)) Q16 FP_SDIV(Q16 a, Q16 b); ////////////////////////////////////////////////////////////////////////// #define FP_ISQRT_UPDATE(est, mant2) \ (((est) + ((est) >> 1)) - \ FP_UMUL_FRAC(FP_UMUL_FRAC(mant2, est, 31), \ FP_UMUL_FRAC(est, est, 31), 31)) Q16 FT_Q16(float f); Q16 FP_Sqrt(Q16 xval, uint32_t frac); Q16 FP_SqrtI(Q16 xval, int32_t frac); __inline float Q16_FT(Q16 x) { return ((float)x) / 65536.0f; } ////////////////////////////////////////////////////////////////////////// //translate from google's skia fixed-point dsp Library. // #define TO_FLOAT_DEGREE(x) (((float)(x)) * 0.000874264215087890625f) #define Q16_TWOPI 411775 #define Q16_PI 205887 #define Q16_HALFPI 102944 Q16 FP_FastAsin(Q16 a); Q16 FP_FastAtan2(Q16 y, Q16 x); #endif ================================================ FILE: miniIMU/FP/FP_Matrix.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "FP_Matrix.h" ////////////////////////////////////////////////////////////////////////// // void FP_Matrix_Copy(Q16 *pSrc, int numRows, int numCols, Q16 *pDst) { Q16 *pIn = pSrc; Q16 *pOut = pDst; unsigned int numSamples = numRows * numCols; unsigned int blkCnt = numSamples >> 2u; //cortex-m3's speed optimization while(blkCnt > 0u){ (*pOut++) = (*pIn++); (*pOut++) = (*pIn++); (*pOut++) = (*pIn++); (*pOut++) = (*pIn++); blkCnt--; } blkCnt = numSamples & 0x03u; while(blkCnt > 0u){ (*pOut++) = (*pIn++); blkCnt--; } } int FP_Maxtrix_Add(Q16 *pSrcA, unsigned short numRows, unsigned short numCols, Q16 *pSrcB, Q16 *pDst) { Q16 *pIn1 = pSrcA; Q16 *pIn2 = pSrcB; Q16 *pOut = pDst; Q16 inA1, inA2, inB1, inB2, out1, out2; unsigned int numSamples; unsigned int blkCnt; numSamples = (unsigned int) numRows * numCols; blkCnt = numSamples >> 2u; while(blkCnt > 0u){ //C(m,n) = A(m,n) + B(m,n) inA1 = pIn1[0]; inB1 = pIn2[0]; inA2 = pIn1[1]; out1 = FP_ADDS(inA1, inB1); inB2 = pIn2[1]; inA1 = pIn1[2]; out2 = FP_ADDS(inA2, inB2); inB1 = pIn2[2]; pOut[0] = out1; pOut[1] = out2; inA2 = pIn1[3]; inB2 = pIn2[3]; out1 = FP_ADDS(inA1, inB1); out2 = FP_ADDS(inA2, inB2); pOut[2] = out1; pOut[3] = out2; pIn1 += 4u; pIn2 += 4u; pOut += 4u; blkCnt--; } blkCnt = numSamples & 0x03u; while(blkCnt > 0u){ //C(m,n) = A(m,n) + B(m,n) *pOut++ = FP_ADDS((*pIn1++), (*pIn2++)); blkCnt--; } return 0; } int FP_Maxtrix_Sub(Q16 *pSrcA, unsigned short numRows, unsigned short numCols, Q16 *pSrcB, Q16 *pDst) { Q16 *pIn1 = pSrcA; Q16 *pIn2 = pSrcB; Q16 *pOut = pDst; Q16 inA1, inA2, inB1, inB2, out1, out2; unsigned int numSamples; unsigned int blkCnt; numSamples = (unsigned int) numRows * numCols; blkCnt = numSamples >> 2u; while(blkCnt > 0u){ //C(m,n) = A(m,n) - B(m,n) inA1 = pIn1[0]; inB1 = pIn2[0]; inA2 = pIn1[1]; out1 = FP_SUBS(inA1, inB1); inB2 = pIn2[1]; inA1 = pIn1[2]; out2 = FP_SUBS(inA2, inB2); inB1 = pIn2[2]; pOut[0] = out1; pOut[1] = out2; inA2 = pIn1[3]; inB2 = pIn2[3]; out1 = FP_SUBS(inA1, inB1); out2 = FP_SUBS(inA2, inB2); pOut[2] = out1; pOut[3] = out2; pIn1 += 4u; pIn2 += 4u; pOut += 4u; blkCnt--; } blkCnt = numSamples & 0x03u; while(blkCnt > 0u){ //C(m,n) = A(m,n) - B(m,n) *pOut++ = FP_SUBS((*pIn1++), (*pIn2++)); blkCnt--; } return 0; } int FP_Matrix_Multiply(Q16 *A, int nrows, int ncols, Q16 *B, int mcols, Q16 *C) { Q16 *pB; Q16 *p_B; int i,j,k; for (i = 0; i < nrows; A += ncols, i++){ for (p_B = B, j = 0; j < mcols; C++, p_B++, j++) { pB = p_B; *C = 0; for (k = 0; k < ncols; pB += mcols, k++){ //*C += *(A+k) * *pB; *C = FP_ADDS(*C, FP_SMUL(*(A+k),*pB)); } } } return 0; } void FP_Matrix_Multiply_With_Transpose(Q16 *A, int nrows, int ncols, Q16 *B, int mrows, Q16 *C) { int i,j,k; Q16 *pA; Q16 *pB; for (i = 0; i < nrows; A += ncols, i++){ for (pB = B, j = 0; j < mrows; C++, j++){ *C = 0; for (pA = A, /* ,*C = 0 */k = 0; k < ncols; k++){ //*C += *pA++ * *pB++; *C = FP_ADDS(*C, FP_SMUL(*pA++, *pB++)); } } } } int FP_Matrix_Inverse(Q16* pSrc, unsigned short n, Q16* pDst) { Q16 *pIn = pSrc; // input data matrix pointer Q16 *pOut = pDst; // output data matrix pointer Q16 *pInT1, *pInT2; // Temporary input data matrix pointer Q16 *pOutT1, *pOutT2; // Temporary output data matrix pointer Q16 *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; // Temporary input and output data matrix pointer Q16 maxC; // maximum value in the column Q16 Xchg, in = 0, in1; // Temporary input values unsigned int i, rowCnt, flag = 0u, j, loopCnt, k, l; // loop counters int status; // status of matrix inverse // Working pointer for destination matrix pOutT1 = pOut; // Loop over the number of rows rowCnt = n; // Making the destination matrix as identity matrix while(rowCnt > 0u){ // Writing all zeroes in lower triangle of the destination matrix j = n - rowCnt; while(j > 0u){ *pOutT1++ = 0; j--; } // Writing all ones in the diagonal of the destination matrix *pOutT1++ = Q16_One; // Writing all zeroes in upper triangle of the destination matrix // j = rowCnt - 1u; while(j > 0u){ *pOutT1++ = 0; j--; } // Decrement the loop counter rowCnt--; } // Loop over the number of columns of the input matrix. // All the elements in each column are processed by the row operations loopCnt = n; // Index modifier to navigate through the columns l = 0u; while(loopCnt > 0u){ // Check if the pivot element is zero.. // If it is zero then interchange the row with non zero row below. // If there is no non zero element to replace in the rows below, // then the matrix is Singular. // Working pointer for the input matrix that points // to the pivot element of the particular row pInT1 = pIn + (l * n); // Working pointer for the destination matrix that points // to the pivot element of the particular row pOutT1 = pOut + (l * n); // Temporary variable to hold the pivot value in = *pInT1; // Grab the most significant value from column l maxC = 0; for (i = l; i < n; i++){ maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC); pInT1 += n; } // Update the status if the matrix is singular if(maxC == 0){ return -1; } // Restore pInT1 pInT1 = pIn; // Destination pointer modifier k = 1u; // Check if the pivot element is the most significant of the column if( (in > 0 ? in : -in) != maxC){ // Loop over the number rows present below i = n - (l + 1u); while(i > 0u){ // Update the input and destination pointers pInT2 = pInT1 + (n * l); pOutT2 = pOutT1 + (n * k); // Look for the most significant element to // replace in the rows below if((*pInT2 > 0 ? *pInT2: -*pInT2) == maxC){ // Loop over number of columns // to the right of the pilot element j = n - l; while(j > 0u){ // Exchange the row elements of the input matrix Xchg = *pInT2; *pInT2++ = *pInT1; *pInT1++ = Xchg; // Decrement the loop counter j--; } // Loop over number of columns of the destination matrix j = n; while(j > 0u){ // Exchange the row elements of the destination matrix Xchg = *pOutT2; *pOutT2++ = *pOutT1; *pOutT1++ = Xchg; // Decrement the loop counter j--; } // Flag to indicate whether exchange is done or not flag = 1u; // Break after exchange is done break; } // Update the destination pointer modifier k++; // Decrement the loop counter i--; } } // Update the status if the matrix is singular if((flag != 1u) && (in == 0)){ return -1; } // Points to the pivot row of input and destination matrices pPivotRowIn = pIn + (l * n); pPivotRowDst = pOut + (l * n); // Temporary pointers to the pivot row pointers pInT1 = pPivotRowIn; pInT2 = pPivotRowDst; // Pivot element of the row in = *pPivotRowIn; // Loop over number of columns // to the right of the pilot element j = (n - l); while(j > 0u){ // Divide each element of the row of the input matrix // by the pivot element in1 = *pInT1; //*pInT1++ = in1 / in; *pInT1++ = FP_SDIV(in1, in); // Decrement the loop counter j--; } // Loop over number of columns of the destination matrix j = n; while(j > 0u){ // Divide each element of the row of the destination matrix // by the pivot element in1 = *pInT2; //*pInT2++ = in1 / in; *pInT2++ = FP_SDIV(in1, in); // Decrement the loop counter j--; } // Replace the rows with the sum of that row and a multiple of row i // so that each new element in column i above row i is zero.*/ // Temporary pointers for input and destination matrices pInT1 = pIn; pInT2 = pOut; // index used to check for pivot element i = 0u; // Loop over number of rows // to be replaced by the sum of that row and a multiple of row i k = n; while(k > 0u){ // Check for the pivot element if(i == l){ // If the processing element is the pivot element, // only the columns to the right are to be processed pInT1 += n - l; pInT2 += n; } else{ // Element of the reference row in = *pInT1; // Working pointers for input and destination pivot rows pPRT_in = pPivotRowIn; pPRT_pDst = pPivotRowDst; // Loop over the number of columns to the right of the pivot element, // to replace the elements in the input matrix j = (n - l); while(j > 0u){ // Replace the element by the sum of that row // and a multiple of the reference row in1 = *pInT1; //*pInT1++ = in1 - (in * *pPRT_in++); *pInT1++ = FP_SUBS(in1, FP_SMUL(in, *pPRT_in++)); // Decrement the loop counter j--; } // Loop over the number of columns to // replace the elements in the destination matrix j = n; while(j > 0u){ // Replace the element by the sum of that row // and a multiple of the reference row in1 = *pInT2; //*pInT2++ = in1 - (in * *pPRT_pDst++); *pInT2++ = FP_SUBS(in1, FP_SMUL(in, *pPRT_pDst++)); // Decrement the loop counter j--; } } // Increment the temporary input pointer pInT1 = pInT1 + l; // Decrement the loop counter k--; // Increment the pivot index i++; } // Increment the input pointer pIn++; // Decrement the loop counter loopCnt--; // Increment the index modifier l++; } // Set status as SUCCESS status = 0; if((flag != 1u) && (in == 0)){ status = -1; } // Return to application return (status); } ================================================ FILE: miniIMU/FP/FP_Matrix.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _FP_MAXTRIX_H_ #define _FP_MAXTRIX_H_ #include "FP_Math.h" ////////////////////////////////////////////////////////////////////////// // void FP_Matrix_Copy(Q16 *pSrc, int numRows, int numCols, Q16 *pDst); int FP_Maxtrix_Add(Q16 *pSrcA, unsigned short numRows, unsigned short numCols, Q16 *pSrcB, Q16 *pDst); int FP_Maxtrix_Sub(Q16 *pSrcA, unsigned short numRows, unsigned short numCols, Q16 *pSrcB, Q16 *pDst); int FP_Matrix_Multiply(Q16 *A, int nrows, int ncols, Q16 *B, int mcols, Q16 *C); void FP_Matrix_Multiply_With_Transpose(Q16 *A, int nrows, int ncols, Q16 *B, int mrows, Q16 *C); int FP_Matrix_Inverse(Q16* pSrc, unsigned short n, Q16* pDst); #endif ================================================ FILE: miniIMU/FP/FP_miniIMU.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "FP_miniIMU.h" #include "FP_Math.h" #include "FP_Matrix.h" #include "FastMath.h" ////////////////////////////////////////////////////////////////////////// //S16.16 //precision 1 / 2^16 = 0.0000152587890625 //all parameters below need to be tune #define FP_EKF_PQ_INITIAL 66//0.001 #define FP_EKF_QQ_INITIAL 66//0.001 #define FP_EKF_RA_INITIAL 1638//0.025 #if FP_EKF_STATE_DIM == 7 #define FP_EKF_PWB_INITIAL 66//0.001f #define FP_EKF_QWB_INITIAL 7//0.0001f #endif ////////////////////////////////////////////////////////////////////////// // static Q16 I[FP_EKF_STATE_DIM * FP_EKF_STATE_DIM] = { #if EKF_STATE_DIM == 4 Q16_One, 0, 0, 0, 0, Q16_One, 0, 0, 0, 0, Q16_One, 0, 0, 0, 0, Q16_One, #else //EKF_STATE_DIM == 7 Q16_One, 0, 0, 0, 0, 0, 0, 0, Q16_One, 0, 0, 0, 0, 0, 0, 0, Q16_One, 0, 0, 0, 0, 0, 0, 0, Q16_One, 0, 0, 0, 0, 0, 0, 0, Q16_One, 0, 0, 0, 0, 0, 0, 0, Q16_One, 0, 0, 0, 0, 0, 0, 0, Q16_One, #endif }; static Q16 P[FP_EKF_STATE_DIM * FP_EKF_STATE_DIM] = { #if FP_EKF_STATE_DIM == 4 FP_EKF_PQ_INITIAL, 0, 0, 0, 0, FP_EKF_PQ_INITIAL, 0, 0, 0, 0, FP_EKF_PQ_INITIAL, 0, 0, 0, 0, FP_EKF_PQ_INITIAL, #else //FP_EKF_STATE_DIM == 7 FP_EKF_PQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, FP_EKF_PQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, FP_EKF_PQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, FP_EKF_PQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, FP_EKF_PWB_INITIAL, 0, 0, 0, 0, 0, 0, 0, FP_EKF_PWB_INITIAL, 0, 0, 0, 0, 0, 0, 0, FP_EKF_PWB_INITIAL, #endif }; static Q16 Q[FP_EKF_STATE_DIM * FP_EKF_STATE_DIM] = { #if FP_EKF_STATE_DIM == 4 FP_EKF_QQ_INITIAL, 0, 0, 0, 0, FP_EKF_QQ_INITIAL, 0, 0, 0, 0, FP_EKF_QQ_INITIAL, 0, 0, 0, 0, FP_EKF_QQ_INITIAL, #else //FP_EKF_STATE_DIM == 7 FP_EKF_QQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, FP_EKF_QQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, FP_EKF_QQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, FP_EKF_QQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, FP_EKF_QWB_INITIAL, 0, 0, 0, 0, 0, 0, 0, FP_EKF_QWB_INITIAL, 0, 0, 0, 0, 0, 0, 0, FP_EKF_QWB_INITIAL, #endif }; static Q16 R[FP_EKF_MEASUREMENT_DIM * FP_EKF_MEASUREMENT_DIM] = { FP_EKF_RA_INITIAL, 0, 0, 0, FP_EKF_RA_INITIAL, 0, 0, 0, FP_EKF_RA_INITIAL, }; static Q16 F[FP_EKF_STATE_DIM * FP_EKF_STATE_DIM] = { #if FP_EKF_STATE_DIM == 4 Q16_One, 0, 0, 0, 0, Q16_One, 0, 0, 0, 0, Q16_One, 0, 0, 0, 0, Q16_One, #else //FP_EKF_STATE_DIM == 7 Q16_One, 0, 0, 0, 0, 0, 0, 0, Q16_One, 0, 0, 0, 0, 0, 0, 0, Q16_One, 0, 0, 0, 0, 0, 0, 0, Q16_One, 0, 0, 0, 0, 0, 0, 0, Q16_One, 0, 0, 0, 0, 0, 0, 0, Q16_One, 0, 0, 0, 0, 0, 0, 0, Q16_One, #endif }; static Q16 H[FP_EKF_MEASUREMENT_DIM * FP_EKF_STATE_DIM] = { #if FP_EKF_STATE_DIM == 4 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, #else //FP_EKF_STATE_DIM == 7 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, #endif }; //state static Q16 X[FP_EKF_STATE_DIM]; static Q16 KY[FP_EKF_STATE_DIM]; //measurement static Q16 Y[FP_EKF_MEASUREMENT_DIM]; // static Q16 CBn[9]; // static Q16 PX[FP_EKF_STATE_DIM * FP_EKF_STATE_DIM]; static Q16 PXX[FP_EKF_STATE_DIM * FP_EKF_STATE_DIM]; static Q16 PHT[FP_EKF_STATE_DIM * FP_EKF_MEASUREMENT_DIM]; static Q16 K[FP_EKF_STATE_DIM * FP_EKF_MEASUREMENT_DIM]; static Q16 S[FP_EKF_MEASUREMENT_DIM * FP_EKF_MEASUREMENT_DIM]; void FP_EKF_IMUInit(float *accel, float *gyro) { //NED coordinate system unit vector float nedVector[3] = {0, 0 , -1.0f}; float accelVector[3] = {0, 0 , 0}; float norm; float crossVector[3]; float sinwi, cosw, sinhalfw, coshalfw; float q[4]; //unit accel norm = FastSqrtI(accel[0] * accel[0] + accel[1] * accel[1] + accel[2] * accel[2]); accelVector[0] = accel[0] * norm; accelVector[1] = accel[1] * norm; accelVector[2] = accel[2] * norm; //cross product between accel and reference crossVector[0] = accelVector[1] * nedVector[2] - accelVector[2] * nedVector[1]; crossVector[1] = accelVector[2] * nedVector[0] - accelVector[0] * nedVector[2]; crossVector[2] = accelVector[0] * nedVector[1] - accelVector[1] * nedVector[0]; sinwi = FastSqrtI(crossVector[0] * crossVector[0] + crossVector[1] * crossVector[1] + crossVector[2] * crossVector[2]); crossVector[0] *= sinwi; crossVector[1] *= sinwi; crossVector[2] *= sinwi; //the angle between accel and reference is the dot product of the two vectors cosw = accelVector[0] * nedVector[0] + accelVector[1] * nedVector[1] + accelVector[2] * nedVector[2]; coshalfw = FastSqrt(0.5f + 0.5f * cosw); sinhalfw = FastSqrt(0.5f - 0.5f * cosw); q[0] = coshalfw; q[1] = crossVector[0] * sinhalfw; q[2] = crossVector[1] * sinhalfw; q[3] = crossVector[2] * sinhalfw; X[0] = FT_Q16(q[0]); X[1] = FT_Q16(q[1]); X[2] = FT_Q16(q[2]); X[3] = FT_Q16(q[3]); } void FP_EKF_IMUUpdate(float *gyro, float *accel, float dt) { Q16 halfdx, halfdy, halfdz; Q16 neghalfdx, neghalfdy, neghalfdz; #if FP_EKF_STATE_DIM == 7 Q16 halfdtq0, neghalfdtq0, halfdtq1, neghalfdtq1, halfdtq2, neghalfdtq2, halfdtq3, neghalfdtq3; #endif Q16 halfdt = FP_SMUL(32768, FT_Q16(dt)); ////////////////////////////////////////////////////////////////////////// Q16 _2q0,_2q1,_2q2,_2q3; Q16 q0, q1, q2, q3; Q16 SI[FP_EKF_MEASUREMENT_DIM * FP_EKF_MEASUREMENT_DIM] = {0}; ////////////////////////////////////////////////////////////////////////// int __al, __ah; Q16 gx = FT_Q16(gyro[0]); Q16 gy = FT_Q16(gyro[1]); Q16 gz = FT_Q16(gyro[2]); // ////////////////////////////////////////////////////////////////////////// float norm; Q16 qNorm; #if FP_EKF_STATE_DIM == 4 halfdx = FP_SMUL(halfdt, gx); halfdy = FP_SMUL(halfdt, gy); halfdz = FP_SMUL(halfdt, gz); #else //EKF_STATE_DIM == 7 halfdx = FP_SMUL(halfdt, FP_SUBS(gx, X[4])); halfdy = FP_SMUL(halfdt, FP_SUBS(gy, X[5])); halfdz = FP_SMUL(halfdt, FP_SUBS(gz, X[6])); #endif neghalfdx = -halfdx; neghalfdy = -halfdy; neghalfdz = -halfdz; // q0 = X[0]; q1 = X[1]; q2 = X[2]; q3 = X[3]; #if FP_EKF_STATE_DIM == 4 /* F[0] = Q16_One; */ F[1] = neghalfdx; F[2] = neghalfdy; F[3] = neghalfdz; F[4] = halfdx; /* F[5] = Q16_One; */ F[6] = neghalfdz; F[7] = halfdy; F[8] = halfdy; F[9] = halfdz; /* F[10] = Q16_One; */ F[11] = neghalfdx; F[12] = halfdz; F[13] = neghalfdy; F[14] = halfdx; /* F[15] = Q16_One; */ #else halfdtq0 = FP_SMUL(halfdt, q0); neghalfdtq0 = -halfdtq0; halfdtq1 = FP_SMUL(halfdt, q1); neghalfdtq1 = -halfdtq1; halfdtq2 = FP_SMUL(halfdt, q2); neghalfdtq2 = -halfdtq2; halfdtq3 = FP_SMUL(halfdt, q3); neghalfdtq3 = -halfdtq3; /* F[0] = Q16_One; */ F[1] = neghalfdx; F[2] = neghalfdy; F[3] = neghalfdz; F[4] = halfdtq1; F[5] = halfdtq2; F[6] = halfdtq3; F[7] = halfdx; /* F[8] = Q16_One; */ F[9] = halfdz; F[10] = neghalfdy; F[11] = neghalfdtq0; F[12] = halfdtq3; F[13] = neghalfdtq2; F[14] = halfdy; F[15] = neghalfdz; /* F[16] = Q16_One; */ F[17] = halfdx; F[18] = neghalfdtq3; F[19] = neghalfdtq0; F[20] = halfdtq1; F[21] = halfdz; F[22] = halfdy; F[23] = neghalfdx; /* F[24] = Q16_One; */ F[25] = halfdtq2; F[26] = neghalfdtq1; F[27] = neghalfdtq0; #endif ////////////////////////////////////////////////////////////////////////// //Extended Kalman Filter: Prediction Step //state time propagation //Update Quaternion with the new gyroscope measurements //X[0] = q0 - halfdx * q1 - halfdy * q2 - halfdz * q3; //X[1] = q1 + halfdx * q0 - halfdy * q3 + halfdz * q2; //X[2] = q2 + halfdx * q3 + halfdy * q0 - halfdz * q1; //X[3] = q3 - halfdx * q2 + halfdy * q1 + halfdz * q0; //cortex-m3's instruction assembly optimization __asm{ smull __al, __ah, neghalfdx, q1; smlal __al, __ah, neghalfdy, q2; smlal __al, __ah, neghalfdz, q3; lsls __ah, __ah, #16; orr X[0], __ah, __al, lsr #16; adds X[0], q0, X[0]; smull __al, __ah, halfdx, q0; smlal __al, __ah, neghalfdy, q3; smlal __al, __ah, halfdz, q2; lsls __ah, __ah, #16; orr X[1], __ah, __al, lsr #16; adds X[1], q1, X[1]; smull __al, __ah, halfdx, q3; smlal __al, __ah, halfdy, q0; smlal __al, __ah, neghalfdz, q1; lsls __ah, __ah, #16; orr X[2], __ah, __al, lsr #16; adds X[2], q2, X[2]; smull __al, __ah, neghalfdx, q2; smlal __al, __ah, halfdy, q1; smlal __al, __ah, halfdz, q0; lsls __ah, __ah, #16; orr X[3], __ah, __al, lsr #16; adds X[3], q3, X[3]; } //covariance time propagation //P = F*P*F' + Q; FP_Matrix_Multiply(F, FP_EKF_STATE_DIM, FP_EKF_STATE_DIM, P, FP_EKF_STATE_DIM, PX); FP_Matrix_Multiply_With_Transpose(PX, FP_EKF_STATE_DIM, FP_EKF_STATE_DIM, F, FP_EKF_STATE_DIM, P); FP_Maxtrix_Add(P, FP_EKF_STATE_DIM, FP_EKF_STATE_DIM, Q, P); ////////////////////////////////////////////////////////////////////////// //measurement update //kalman gain calculation //K = P * H' / (R + H * P * H') _2q0 = X[0] << 1; _2q1 = X[1] << 1; _2q2 = X[2] << 1; _2q3 = X[3] << 1; #if FP_EKF_STATE_DIM == 4 H[0] = _2q2; H[1] = -_2q3; H[2] = _2q0; H[3] = -_2q1; H[4] = -_2q1; H[5] = -_2q0; H[6] = -_2q3; H[7] = -_2q2; H[8] = -_2q0; H[9] = _2q1; H[10] = _2q2; H[11] = -_2q3; #else //FP_EKF_STATE_DIM == 7 H[0] = _2q2; H[1] = -_2q3; H[2] = _2q0; H[3] = -_2q1; H[8] = -_2q1; H[9] = -_2q0; H[10] = -_2q3; H[11] = -_2q2; H[14] = -_2q0; H[15] = _2q1; H[16] = _2q2; H[17] = -_2q3; #endif FP_Matrix_Multiply_With_Transpose(P, FP_EKF_STATE_DIM, FP_EKF_STATE_DIM, H, FP_EKF_MEASUREMENT_DIM, PHT); FP_Matrix_Multiply(H, FP_EKF_MEASUREMENT_DIM, FP_EKF_STATE_DIM, PHT, FP_EKF_MEASUREMENT_DIM, S); FP_Maxtrix_Add(S, FP_EKF_MEASUREMENT_DIM, FP_EKF_MEASUREMENT_DIM, R, S); FP_Matrix_Inverse(S, FP_EKF_MEASUREMENT_DIM, SI); FP_Matrix_Multiply(PHT, FP_EKF_STATE_DIM, FP_EKF_MEASUREMENT_DIM, SI, FP_EKF_MEASUREMENT_DIM, K); //state measurement update //X = X + K * Y; //Y[0] = -2.0f * (X[1] * X[3] - X[0] * X[2]); //Y[1] = -2.0f * (X[2] * X[3] + X[0] * X[1]); //Y[2] = 1.0f - 2.0f * (X[0] * X[0] + X[3] * X[3]); Y[0] = FP_SUBS(FP_SMUL(X[0], X[2]), FP_SMUL(X[1], X[3])) << 1; Y[1] = FP_ADDS(FP_SMUL(-X[2], X[3]), FP_SMUL(-X[0], X[1])) << 1; Y[2] = FP_SUBS(Q16_One, FP_ADDS(FP_SMUL(X[0], X[0]), FP_SMUL(X[3], X[3])) << 1); //normalize accel norm = FastSqrtI(accel[0] * accel[0] + accel[1] * accel[1] + accel[2] * accel[2]); accel[0] *= norm; accel[1] *= norm; accel[2] *= norm; Y[0] = FP_SUBS(FT_Q16(accel[0]), Y[0]); Y[1] = FP_SUBS(FT_Q16(accel[1]), Y[1]); Y[2] = FP_SUBS(FT_Q16(accel[2]), Y[2]); FP_Matrix_Multiply(K, FP_EKF_STATE_DIM, FP_EKF_MEASUREMENT_DIM, Y, 1, KY); FP_Maxtrix_Add(X, FP_EKF_STATE_DIM, 1, X, KY); //normalize quaternion //norm = FastSqrtI(X[0] * X[0] + X[1] * X[1] + X[2] * X[2] + X[3] * X[3]); //X[0] *= norm; //X[1] *= norm; //X[2] *= norm; //X[3] *= norm; //cortex-m3's instruction assembly optimization __asm{ smull __al, __ah, X[0], X[0]; smlal __al, __ah, X[1], X[1]; smlal __al, __ah, X[2], X[2]; smlal __al, __ah, X[3], X[3]; lsls __ah, __ah, #16; orr qNorm, __ah, __al, lsr #16; } qNorm = FP_SqrtI(qNorm, PRECISION); X[0] = FP_SMUL(X[0], qNorm); X[1] = FP_SMUL(X[1], qNorm); X[2] = FP_SMUL(X[2], qNorm); X[3] = FP_SMUL(X[3], qNorm); //covariance measurement update //P = (I - K * H) * P FP_Matrix_Multiply(K, FP_EKF_STATE_DIM, FP_EKF_MEASUREMENT_DIM, H, FP_EKF_STATE_DIM, PX); FP_Maxtrix_Sub(I, FP_EKF_STATE_DIM, FP_EKF_STATE_DIM, PX, PX); FP_Matrix_Multiply(PX, FP_EKF_STATE_DIM, FP_EKF_STATE_DIM, P, FP_EKF_STATE_DIM, PXX); FP_Matrix_Copy(PXX, FP_EKF_STATE_DIM, FP_EKF_STATE_DIM, P); } void FP_EKF_IMUGetAngle(float* rpy) { Q16 q0q0 = FP_SMUL(X[0], X[0]); Q16 fpRPY[3]; CBn[0] = FP_SUBS(((q0q0 + FP_SMUL(X[1], X[1])) << 1), Q16_One); CBn[1] = (FP_SMUL(X[1], X[2]) + FP_SMUL(X[0], X[3])) << 1; CBn[2] = (FP_SMUL(X[1], X[3]) - FP_SMUL(X[0], X[2])) << 1; //CBn[3] = 2.0f * (X[1] * X[2] - X[0] * X[3]); //CBn[4] = 2.0f * (q0q0 + X[2] * X[2]) - 1.0f; CBn[5] = (FP_SMUL(X[2], X[3]) + FP_SMUL(X[0], X[1])) << 1; //CBn[6] = 2.0f * (X[1] * X[3] + X[0] * X[2]); //CBn[7] = 2.0f * (X[2] * X[3] - X[0] * X[1]); CBn[8] = FP_SUBS(((q0q0 + FP_SMUL(X[3], X[3])) << 1), Q16_One); //roll fpRPY[0] = FP_FastAtan2(CBn[5], CBn[8]); if(fpRPY[0] == Q16_PI){ fpRPY[0] = -Q16_PI; } //pitch if (CBn[2] >= Q16_One){ fpRPY[1] = -Q16_HALFPI; } else if (fpRPY[2] <= -Q16_One){ fpRPY[1] = Q16_HALFPI; } else{ fpRPY[1] = FP_FastAsin(-CBn[2]); } //yaw fpRPY[2] = FP_FastAtan2(CBn[1], CBn[0]); if (fpRPY[2] < 0){ fpRPY[2] = FP_ADDS(fpRPY[2], Q16_TWOPI); } if (fpRPY[2] >= Q16_TWOPI){ fpRPY[2] = 0; } rpy[0] = TO_FLOAT_DEGREE(fpRPY[0]); rpy[1] = TO_FLOAT_DEGREE(fpRPY[1]); rpy[2] = TO_FLOAT_DEGREE(fpRPY[2]); } ================================================ FILE: miniIMU/FP/FP_miniIMU.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _FP_MINIIMU_H_ #define _FP_MINIIMU_H_ ////////////////////////////////////////////////////////////////////////// //S16.16 //#define FP_EKF_STATE_DIM 4 //q0 q1 q2 q3 #define FP_EKF_STATE_DIM 7 //q0 q1 q2 q3 wxb wyb wzb #define FP_EKF_MEASUREMENT_DIM 3 //ax ay az void FP_EKF_IMUInit(float *accel, float *gyro); void FP_EKF_IMUUpdate(float *gyro, float *accel, float dt); void FP_EKF_IMUGetAngle(float* rpy); #endif ================================================ FILE: miniIMU/Usage.txt ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ ////////////////////////////////////////////////////////////////////////// //setp 1: Decide how many states do you want to use. Look into the filename of "miniIMU.h" either uncomment #define EKF_STATE_DIM 4 or uncomment #define EKF_STATE_DIM 7 on your own, by default is "define EKF_STATE_DIM 7" ////////////////////////////////////////////////////////////////////////// //setp 2: // using the struct as below,In the main loop of the program ...... if EKF is not initialization EKF_IMUInit(accel, gyro); else EKF_IMUUpdate(gyro, accel, dt); ...... EKF_IMUGetAngle(rpy); Enjoy it! ================================================ FILE: miniIMU/miniIMU.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #include "FastMath.h" #include "miniIMU.h" #include "miniMatrix.h" ////////////////////////////////////////////////////////////////////////// // //all parameters below need to be tune #define EKF_PQ_INITIAL 0.001f #define EKF_QQ_INITIAL 0.05f #define EKF_RA_INITIAL 0.005346f #if EKF_STATE_DIM == 7 #define EKF_PWB_INITIAL 0.001f #define EKF_QWB_INITIAL 0.0000005f #endif ////////////////////////////////////////////////////////////////////////// // //#define UPDATE_P_COMPLICATED #ifdef UPDATE_P_COMPLICATED static float I[EKF_STATE_DIM * EKF_STATE_DIM] = { #if EKF_STATE_DIM == 4 1.0f, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 1.0f, #else //EKF_STATE_DIM == 7 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, #endif }; #endif static float P[EKF_STATE_DIM * EKF_STATE_DIM] = { #if EKF_STATE_DIM == 4 EKF_PQ_INITIAL, 0, 0, 0, 0, EKF_PQ_INITIAL, 0, 0, 0, 0, EKF_PQ_INITIAL, 0, 0, 0, 0, EKF_PQ_INITIAL, #else //EKF_STATE_DIM == 7 EKF_PQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_PQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_PQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_PQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_PWB_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_PWB_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_PWB_INITIAL, #endif }; static float Q[EKF_STATE_DIM * EKF_STATE_DIM] = { #if EKF_STATE_DIM == 4 EKF_QQ_INITIAL, 0, 0, 0, 0, EKF_QQ_INITIAL, 0, 0, 0, 0, EKF_QQ_INITIAL, 0, 0, 0, 0, EKF_QQ_INITIAL, #else //EKF_STATE_DIM == 7 EKF_QQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_QQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_QQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_QQ_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_QWB_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_QWB_INITIAL, 0, 0, 0, 0, 0, 0, 0, EKF_QWB_INITIAL, #endif }; static float R[EKF_MEASUREMENT_DIM * EKF_MEASUREMENT_DIM] = { EKF_RA_INITIAL, 0, 0, 0, EKF_RA_INITIAL, 0, 0, 0, EKF_RA_INITIAL, }; static float F[EKF_STATE_DIM * EKF_STATE_DIM] = { #if EKF_STATE_DIM == 4 0.0f, 0, 0, 0, 0, 0.0f, 0, 0, 0, 0, 0.0f, 0, 0, 0, 0, 0.0f, #else //EKF_STATE_DIM == 7 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, 0, 0, 0, 0, 0, 0, 0, 1.0f, #endif }; static float H[EKF_MEASUREMENT_DIM * EKF_STATE_DIM] = { #if EKF_STATE_DIM == 4 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, #else //EKF_STATE_DIM == 7 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, #endif }; //state static float X[EKF_STATE_DIM]; static float KY[EKF_STATE_DIM]; //measurement static float Y[EKF_MEASUREMENT_DIM]; // static float CBn[9]; // static float PX[EKF_STATE_DIM * EKF_STATE_DIM]; static float PXX[EKF_STATE_DIM * EKF_STATE_DIM]; static float PXY[EKF_STATE_DIM * EKF_MEASUREMENT_DIM]; static float K[EKF_STATE_DIM * EKF_MEASUREMENT_DIM]; static float S[EKF_MEASUREMENT_DIM * EKF_MEASUREMENT_DIM]; void EKF_IMUInit(float *accel, float *gyro) { //NED coordinate system unit vector float nedVector[3] = {0, 0 , -1.0f}; float accelVector[3] = {0, 0 , 0}; float norm; float crossVector[3]; float sinwi, cosw, sinhalfw, coshalfw; //unit accel norm = FastSqrtI(accel[0] * accel[0] + accel[1] * accel[1] + accel[2] * accel[2]); accelVector[0] = accel[0] * norm; accelVector[1] = accel[1] * norm; accelVector[2] = accel[2] * norm; //cross product between accel and reference crossVector[0] = accelVector[1] * nedVector[2] - accelVector[2] * nedVector[1]; crossVector[1] = accelVector[2] * nedVector[0] - accelVector[0] * nedVector[2]; crossVector[2] = accelVector[0] * nedVector[1] - accelVector[1] * nedVector[0]; sinwi = FastSqrtI(crossVector[0] * crossVector[0] + crossVector[1] * crossVector[1] + crossVector[2] * crossVector[2]); crossVector[0] *= sinwi; crossVector[1] *= sinwi; crossVector[2] *= sinwi; //the angle between accel and reference is the dot product of the two vectors cosw = accelVector[0] * nedVector[0] + accelVector[1] * nedVector[1] + accelVector[2] * nedVector[2]; coshalfw = FastSqrt((1.0f + cosw) * 0.5f); sinhalfw = FastSqrt((1.0f - cosw) * 0.5f); X[0] = coshalfw; X[1] = crossVector[0] * sinhalfw; X[2] = crossVector[1] * sinhalfw; X[3] = crossVector[2] * sinhalfw; norm = FastSqrtI(X[0] * X[0] + X[1] * X[1] + X[2] * X[2] + X[3] * X[3]); X[0] *= norm; X[1] *= norm; X[2] *= norm; X[3] *= norm; } void EKF_IMUUpdate(float *gyro, float *accel, float dt) { float norm; float halfdx, halfdy, halfdz; float neghalfdx, neghalfdy, neghalfdz; #if EKF_STATE_DIM == 7 float halfdtq0, neghalfdtq0, halfdtq1, neghalfdtq1, halfdtq2, neghalfdtq2, halfdtq3, neghalfdtq3; #endif float halfdt = 0.5f * dt; ////////////////////////////////////////////////////////////////////////// float _2q0,_2q1,_2q2,_2q3; float q0, q1, q2, q3; // float SI[EKF_MEASUREMENT_DIM * EKF_MEASUREMENT_DIM] = {0}; ////////////////////////////////////////////////////////////////////////// #if EKF_STATE_DIM == 4 halfdx = halfdt * gyro[0]; halfdy = halfdt * gyro[1]; halfdz = halfdt * gyro[2]; #else //EKF_STATE_DIM == 7 halfdx = halfdt * (gyro[0] - X[4]); halfdy = halfdt * (gyro[1] - X[5]); halfdz = halfdt * (gyro[2] - X[6]); #endif neghalfdx = -halfdx; neghalfdy = -halfdy; neghalfdz = -halfdz; // q0 = X[0]; q1 = X[1]; q2 = X[2]; q3 = X[3]; ////////////////////////////////////////////////////////////////////////// //Extended Kalman Filter: Prediction Step //state time propagation //Update Quaternion with the new gyroscope measurements X[0] = q0 - halfdx * q1 - halfdy * q2 - halfdz * q3; X[1] = q1 + halfdx * q0 - halfdy * q3 + halfdz * q2; X[2] = q2 + halfdx * q3 + halfdy * q0 - halfdz * q1; X[3] = q3 - halfdx * q2 + halfdy * q1 + halfdz * q0; #if EKF_STATE_DIM == 4 /* F[0] = 1.0f; */ F[1] = neghalfdx; F[2] = neghalfdy; F[3] = neghalfdz; F[4] = halfdx; /* F[5] = 1.0f; */ F[6] = neghalfdz; F[7] = halfdy; F[8] = halfdy; F[9] = halfdz; /* F[10] = 1.0f; */ F[11] = neghalfdx; F[12] = halfdz; F[13] = neghalfdy; F[14] = halfdx; /* F[15] = 1.0f; */ #else halfdtq0 = halfdt * q0; neghalfdtq0 = -halfdtq0; halfdtq1 = halfdt * q1; neghalfdtq1 = -halfdtq1; halfdtq2 = halfdt * q2; neghalfdtq2 = -halfdtq2; halfdtq3 = halfdt * q3; neghalfdtq3 = -halfdtq3; /* F[0] = 1.0f; */ F[1] = neghalfdx; F[2] = neghalfdy; F[3] = neghalfdz; F[4] = halfdtq1; F[5] = halfdtq2; F[6] = halfdtq3; F[7] = halfdx; /* F[8] = 1.0f; */ F[9] = halfdz; F[10] = neghalfdy; F[11] = neghalfdtq0; F[12] = halfdtq3; F[13] = neghalfdtq2; F[14] = halfdy; F[15] = neghalfdz; /* F[16] = 1.0f; */ F[17] = halfdx; F[18] = neghalfdtq3; F[19] = neghalfdtq0; F[20] = halfdtq1; F[21] = halfdz; F[22] = halfdy; F[23] = neghalfdx; /* F[24] = 1.0f; */ F[25] = halfdtq2; F[26] = neghalfdtq1; F[27] = neghalfdtq0; #endif //covariance time propagation //P = F*P*F' + Q; Matrix_Multiply(F, EKF_STATE_DIM, EKF_STATE_DIM, P, EKF_STATE_DIM, PX); Matrix_Multiply_With_Transpose(PX, EKF_STATE_DIM, EKF_STATE_DIM, F, EKF_STATE_DIM, P); Maxtrix_Add(P, EKF_STATE_DIM, EKF_STATE_DIM, Q, P); ////////////////////////////////////////////////////////////////////////// //measurement update //kalman gain calculation //K = P * H' / (R + H * P * H') _2q0 = 2.0f * X[0]; _2q1 = 2.0f * X[1]; _2q2 = 2.0f * X[2]; _2q3 = 2.0f * X[3]; #if EKF_STATE_DIM == 4 H[0] = _2q2; H[1] = -_2q3; H[2] = _2q0; H[3] = -_2q1; H[4] = -_2q1; H[5] = -_2q0; H[6] = -_2q3; H[7] = -_2q2; H[8] = -_2q0; H[9] = _2q1; H[10] = _2q2; H[11] = -_2q3; #else //EKF_STATE_DIM == 7 H[0] = _2q2; H[1] = -_2q3; H[2] = _2q0; H[3] = -_2q1; H[8] = -_2q1; H[9] = -_2q0; H[10] = -_2q3; H[11] = -_2q2; H[14] = -_2q0; H[15] = _2q1; H[16] = _2q2; H[17] = -_2q3; #endif Matrix_Multiply_With_Transpose(P, EKF_STATE_DIM, EKF_STATE_DIM, H, EKF_MEASUREMENT_DIM, PXY); Matrix_Multiply(H, EKF_MEASUREMENT_DIM, EKF_STATE_DIM, PXY, EKF_MEASUREMENT_DIM, S); Maxtrix_Add(S, EKF_MEASUREMENT_DIM, EKF_MEASUREMENT_DIM, R, S); Matrix_Inverse(S, EKF_MEASUREMENT_DIM, SI); Matrix_Multiply(PXY, EKF_STATE_DIM, EKF_MEASUREMENT_DIM, SI, EKF_MEASUREMENT_DIM, K); //state measurement update //X = X + K * Y; Y[0] = -2.0f * (X[1] * X[3] - X[0] * X[2]); Y[1] = -2.0f * (X[2] * X[3] + X[0] * X[1]); Y[2] = 1.0f - 2.0f * (X[0] * X[0] + X[3] * X[3]); //normalize accel norm = FastSqrtI(accel[0] * accel[0] + accel[1] * accel[1] + accel[2] * accel[2]); accel[0] *= norm; accel[1] *= norm; accel[2] *= norm; Y[0] = accel[0] - Y[0]; Y[1] = accel[1] - Y[1]; Y[2] = accel[2] - Y[2]; // Update State Vector Matrix_Multiply(K, EKF_STATE_DIM, EKF_MEASUREMENT_DIM, Y, 1, KY); Maxtrix_Add(X, EKF_STATE_DIM, 1, KY, X); //normalize quaternion norm = FastSqrtI(X[0] * X[0] + X[1] * X[1] + X[2] * X[2] + X[3] * X[3]); X[0] *= norm; X[1] *= norm; X[2] *= norm; X[3] *= norm; //covariance measurement update //P = (I - K * H) * P //P = P - K * H * P //or //P=(I - K*H)*P*(I - K*H)' + K*R*K' #ifndef UPDATE_P_COMPLICATED Matrix_Multiply(K, EKF_STATE_DIM, EKF_MEASUREMENT_DIM, H, EKF_STATE_DIM, PX); Matrix_Multiply(PX, EKF_STATE_DIM, EKF_STATE_DIM, P, EKF_STATE_DIM, PXX); Maxtrix_Add(P, EKF_STATE_DIM, EKF_STATE_DIM, PXX, P); #else Matrix_Multiply(K, EKF_STATE_DIM, EKF_MEASUREMENT_DIM, H, EKF_STATE_DIM, PX); Maxtrix_Sub(I, EKF_STATE_DIM, EKF_STATE_DIM, PX, PX); Matrix_Multiply(PX, EKF_STATE_DIM, EKF_STATE_DIM, P, EKF_STATE_DIM, PXX); Matrix_Multiply_With_Transpose(PXX, EKF_STATE_DIM, EKF_STATE_DIM, PX, EKF_STATE_DIM, P); Matrix_Multiply(K, EKF_STATE_DIM, EKF_MEASUREMENT_DIM, R, EKF_MEASUREMENT_DIM, PXY); Matrix_Multiply_With_Transpose(PXY, EKF_STATE_DIM, EKF_MEASUREMENT_DIM, K, EKF_STATE_DIM, PX); Maxtrix_Add(P, EKF_STATE_DIM, EKF_STATE_DIM, PX, P); #endif } void EKF_IMUGetAngle(float* rpy) { float q0q0 = X[0] * X[0]; //x-y-z ned CBn[0] = 2.0f * (q0q0 + X[1] * X[1]) - 1.0f; CBn[1] = 2.0f * (X[1] * X[2] + X[0] * X[3]); CBn[2] = 2.0f * (X[1] * X[3] - X[0] * X[2]); //CBn[3] = 2.0f * (X[1] * X[2] - X[0] * X[3]); //CBn[4] = 2.0f * (q0q0 + X[2] * X[2]) - 1.0f; CBn[5] = 2.0f * (X[2] * X[3] + X[0] * X[1]); //CBn[6] = 2.0f * (X[1] * X[3] + X[0] * X[2]); //CBn[7] = 2.0f * (X[2] * X[3] - X[0] * X[1]); CBn[8] = 2.0f * (q0q0 + X[3] * X[3]) - 1.0f; //roll rpy[0] = FastAtan2(CBn[5], CBn[8]); if (rpy[0] == EKF_PI) rpy[0] = -EKF_PI; //pitch if (CBn[2] >= 1.0f) rpy[1] = -EKF_HALFPI; else if (CBn[2] <= -1.0f) rpy[1] = EKF_HALFPI; else rpy[1] = FastAsin(-CBn[2]); //yaw rpy[2] = FastAtan2(CBn[1], CBn[0]); if (rpy[2] < 0.0f){ rpy[2] += EKF_TWOPI; } if (rpy[2] >= EKF_TWOPI){ rpy[2] = 0.0f; } rpy[0] = EKF_TODEG(rpy[0]); rpy[1] = EKF_TODEG(rpy[1]); rpy[2] = EKF_TODEG(rpy[2]); } void EKF_IMUGetQ(float* Q) { Q[0] = X[0]; Q[1] = X[1]; Q[2] = X[2]; Q[3] = X[3]; } ================================================ FILE: miniIMU/miniIMU.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef MINIIMU_H_ #define MINIIMU_H_ ////////////////////////////////////////////////////////////////////////// // //#define EKF_STATE_DIM 4 //q0 q1 q2 q3 #define EKF_STATE_DIM 7 //q0 q1 q2 q3 wxb wyb wzb #define EKF_MEASUREMENT_DIM 3 //ax ay az #define EKF_HALFPI 1.5707963267948966192313216916398f #define EKF_PI 3.1415926535897932384626433832795f #define EKF_TWOPI 6.283185307179586476925286766559f #define EKF_TODEG(x) ((x) * 57.2957796f) void EKF_IMUInit(float *accel, float *gyro); void EKF_IMUUpdate(float *gyro, float *accel, float dt); void EKF_IMUGetAngle(float* rpy); void EKF_IMUGetQ(float *Q); #endif ================================================ FILE: miniIMU/miniMatrix.c ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _MINIMAXTRIX_H_ #define _MINIMAXTRIX_H_ #include "miniMatrix.h" ////////////////////////////////////////////////////////////////////////// // void Matrix_Zero(float *A, unsigned short numRows, unsigned short numCols) { float *pIn = A; unsigned int numSamples = numRows * numCols; unsigned int blkCnt = numSamples >> 2u; //cortex-m3's speed optimization while(blkCnt > 0u){ (*pIn++) = 0.0f; (*pIn++) = 0.0f; (*pIn++) = 0.0f; (*pIn++) = 0.0f; blkCnt--; } blkCnt = numSamples & 0x03u; while(blkCnt > 0u){ (*pIn++) = 0.0f; blkCnt--; } } void Matrix_Copy(float *pSrc, unsigned short numRows, unsigned short numCols, float *pDst) { unsigned int numSamples; // total number of elements in the matrix unsigned int blkCnt; // loop counters float in1, in2, in3, in4; // Total number of samples in the input matrix numSamples = (unsigned int) numRows * numCols; // Loop unrolling blkCnt = numSamples >> 2u; // First part of the processing with loop unrolling. Compute 4 outputs at a time. // a second loop below computes the remaining 1 to 3 samples. while(blkCnt > 0u){ // C = A // Copy and then store the results in the destination buffer in1 = *pSrc++; in2 = *pSrc++; in3 = *pSrc++; in4 = *pSrc++; *pDst++ = in1; *pDst++ = in2; *pDst++ = in3; *pDst++ = in4; // Decrement the loop counter blkCnt--; } // If the numSamples is not a multiple of 4, compute any remaining output samples here. // No loop unrolling is used. blkCnt = numSamples & 0x3u; while(blkCnt > 0u){ // C = A // Copy and then store the results in the destination buffer *pDst++ = *pSrc++; // Decrement the loop counter blkCnt--; } } int Maxtrix_Add(float *pSrcA, unsigned short numRows, unsigned short numCols, float *pSrcB, float *pDst) { float *pIn1 = pSrcA; // input data matrix pointer A float *pIn2 = pSrcB; // input data matrix pointer B float *pOut = pDst; // output data matrix pointer float inA1, inA2, inB1, inB2, out1, out2; // temporary variables unsigned int numSamples; // total number of elements in the matrix unsigned int blkCnt; // loop counters int status; // status of matrix addition // Total number of samples in the input matrix numSamples = (unsigned int) numRows * numCols; // Loop unrolling blkCnt = numSamples >> 2u; // First part of the processing with loop unrolling. Compute 4 outputs at a time. // a second loop below computes the remaining 1 to 3 samples. while(blkCnt > 0u){ // C(m,n) = A(m,n) + B(m,n) // Add and then store the results in the destination buffer. // Read values from source A inA1 = pIn1[0]; // Read values from source B inB1 = pIn2[0]; // Read values from source A inA2 = pIn1[1]; // out = sourceA + sourceB out1 = inA1 + inB1; // Read values from source B inB2 = pIn2[1]; // Read values from source A inA1 = pIn1[2]; // out = sourceA + sourceB out2 = inA2 + inB2; // Read values from source B inB1 = pIn2[2]; // Store result in destination pOut[0] = out1; pOut[1] = out2; // Read values from source A inA2 = pIn1[3]; // Read values from source B inB2 = pIn2[3]; // out = sourceA + sourceB out1 = inA1 + inB1; // out = sourceA + sourceB out2 = inA2 + inB2; // Store result in destination pOut[2] = out1; // Store result in destination pOut[3] = out2; // update pointers to process next sampels pIn1 += 4u; pIn2 += 4u; pOut += 4u; // Decrement the loop counter blkCnt--; } // If the numSamples is not a multiple of 4, compute any remaining output samples here. // No loop unrolling is used. blkCnt = numSamples & 0x3u; while(blkCnt > 0u){ // C(m,n) = A(m,n) + B(m,n) // Add and then store the results in the destination buffer. *pOut++ = (*pIn1++) + (*pIn2++); // Decrement the loop counter blkCnt--; } // set status as SUCCESS status = 0; // Return to application return (status); } int Maxtrix_Sub(float *pSrcA, unsigned short numRows, unsigned short numCols, float *pSrcB, float *pDst) { float *pIn1 = pSrcA; // input data matrix pointer A float *pIn2 = pSrcB; // input data matrix pointer B float *pOut = pDst; // output data matrix pointer float inA1, inA2, inB1, inB2, out1, out2; // temporary variables unsigned int numSamples; // total number of elements in the matrix unsigned int blkCnt; // loop counters int status; // status of matrix subtraction // Total number of samples in the input matrix numSamples = (unsigned int) numRows * numCols; // Run the below code for Cortex-M4 and Cortex-M3 // Loop Unrolling blkCnt = numSamples >> 2u; // First part of the processing with loop unrolling. Compute 4 outputs at a time. // a second loop below computes the remaining 1 to 3 samples. while(blkCnt > 0u){ // C(m,n) = A(m,n) - B(m,n) // Subtract and then store the results in the destination buffer. // Read values from source A inA1 = pIn1[0]; // Read values from source B inB1 = pIn2[0]; // Read values from source A inA2 = pIn1[1]; // out = sourceA - sourceB out1 = inA1 - inB1; // Read values from source B inB2 = pIn2[1]; // Read values from source A inA1 = pIn1[2]; // out = sourceA - sourceB out2 = inA2 - inB2; // Read values from source B inB1 = pIn2[2]; // Store result in destination pOut[0] = out1; pOut[1] = out2; // Read values from source A inA2 = pIn1[3]; // Read values from source B inB2 = pIn2[3]; // out = sourceA - sourceB out1 = inA1 - inB1; // out = sourceA - sourceB out2 = inA2 - inB2; // Store result in destination pOut[2] = out1; // Store result in destination pOut[3] = out2; // update pointers to process next sampels pIn1 += 4u; pIn2 += 4u; pOut += 4u; // Decrement the loop counter blkCnt--; } // If the numSamples is not a multiple of 4, compute any remaining output samples here. // No loop unrolling is used. blkCnt = numSamples & 0x3u; while(blkCnt > 0u){ // C(m,n) = A(m,n) - B(m,n) // Subtract and then store the results in the destination buffer. *pOut++ = (*pIn1++) - (*pIn2++); // Decrement the loop counter blkCnt--; } // Set status as ARM_MATH_SUCCESS status = 0; // Return to application return (status); } int Matrix_Multiply(float* pSrcA, unsigned short numRowsA, unsigned short numColsA, float* pSrcB, unsigned short numColsB, float* pDst) { float *pIn1 = pSrcA; // input data matrix pointer A float *pIn2 = pSrcB; // input data matrix pointer B float *pInA = pSrcA; // input data matrix pointer A float *pOut = pDst; // output data matrix pointer float *px; // Temporary output data matrix pointer float sum; // Accumulator // Run the below code for Cortex-M4 and Cortex-M3 float in1, in2, in3, in4; unsigned short col, i = 0u, j, row = numRowsA, colCnt; // loop counters int status; // status of matrix multiplication // The following loop performs the dot-product of each row in pSrcA with each column in pSrcB // row loop do{ // Output pointer is set to starting address of the row being processed px = pOut + i; // For every row wise process, the column loop counter is to be initiated col = numColsB; // For every row wise process, the pIn2 pointer is set // to the starting address of the pSrcB data pIn2 = pSrcB; j = 0u; // column loop do{ // Set the variable sum, that acts as accumulator, to zero sum = 0.0f; // Initiate the pointer pIn1 to point to the starting address of the column being processed pIn1 = pInA; // Apply loop unrolling and compute 4 MACs simultaneously. colCnt = numColsA >> 2u; // matrix multiplication while(colCnt > 0u){ // c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) in3 = *pIn2; pIn2 += numColsB; in1 = pIn1[0]; in2 = pIn1[1]; sum += in1 * in3; in4 = *pIn2; pIn2 += numColsB; sum += in2 * in4; in3 = *pIn2; pIn2 += numColsB; in1 = pIn1[2]; in2 = pIn1[3]; sum += in1 * in3; in4 = *pIn2; pIn2 += numColsB; sum += in2 * in4; pIn1 += 4u; // Decrement the loop count colCnt--; } // If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here. // No loop unrolling is used. colCnt = numColsA & 0x3u; while(colCnt > 0u){ // c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) sum += *pIn1++ * (*pIn2); pIn2 += numColsB; // Decrement the loop counter colCnt--; } // Store the result in the destination buffer *px++ = sum; // Update the pointer pIn2 to point to the starting address of the next column j++; pIn2 = pSrcB + j; // Decrement the column loop counter col--; } while(col > 0u); // Update the pointer pInA to point to the starting address of the next row i = i + numColsB; pInA = pInA + numColsA; // Decrement the row loop counter row--; } while(row > 0u); // Set status as ARM_MATH_SUCCESS status = 0; // Return to application return (status); } void Matrix_Multiply_With_Transpose(float *A, unsigned short nrows, unsigned short ncols, float *B, unsigned short mrows, float *C) { int i,j,k; float *pA; float *pB; for (i = 0; i < nrows; A += ncols, i++){ for (pB = B, j = 0; j < mrows; C++, j++){ for (pA = A, *C = 0.0, k = 0; k < ncols; k++){ *C += *pA++ * *pB++; } } } } void Maxtrix_Transpose(float *pSrc, unsigned short nRows, unsigned short nCols, float *pDst) { float *pIn = pSrc; float *pOut = pDst; float *px; unsigned short blkCnt, i = 0u, row = nRows; do{ blkCnt = nCols >> 2; px = pOut + i; while(blkCnt > 0u){ *px = *pIn++; px += nRows; *px = *pIn++; px += nRows; *px = *pIn++; px += nRows; *px = *pIn++; px += nRows; blkCnt--; } blkCnt = nCols & 0x03u; while(blkCnt > 0u){ *px = *pIn++; px += nRows; blkCnt--; } i++; row--; } while(row > 0u); } int Matrix_Inverse(float * pSrc, unsigned short n, float* pDst) { float *pIn = pSrc; // input data matrix pointer float *pOut = pDst; // output data matrix pointer float *pInT1, *pInT2; // Temporary input data matrix pointer float *pOutT1, *pOutT2; // Temporary output data matrix pointer float *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; // Temporary input and output data matrix pointer float maxC; // maximum value in the column float Xchg, in = 0.0f, in1; // Temporary input values unsigned int i, rowCnt, flag = 0u, j, loopCnt, k, l; // loop counters int status; // status of matrix inverse // Working pointer for destination matrix pOutT1 = pOut; // Loop over the number of rows rowCnt = n; // Making the destination matrix as identity matrix while(rowCnt > 0u){ // Writing all zeroes in lower triangle of the destination matrix j = n - rowCnt; while(j > 0u){ *pOutT1++ = 0.0f; j--; } // Writing all ones in the diagonal of the destination matrix *pOutT1++ = 1.0f; // Writing all zeroes in upper triangle of the destination matrix j = rowCnt - 1u; while(j > 0u){ *pOutT1++ = 0.0f; j--; } // Decrement the loop counter rowCnt--; } // Loop over the number of columns of the input matrix. // All the elements in each column are processed by the row operations loopCnt = n; // Index modifier to navigate through the columns l = 0u; while(loopCnt > 0u){ // Check if the pivot element is zero.. // If it is zero then interchange the row with non zero row below. // If there is no non zero element to replace in the rows below, // then the matrix is Singular. // Working pointer for the input matrix that points // to the pivot element of the particular row pInT1 = pIn + (l * n); // Working pointer for the destination matrix that points // to the pivot element of the particular row pOutT1 = pOut + (l * n); // Temporary variable to hold the pivot value in = *pInT1; // Grab the most significant value from column l maxC = 0; for (i = l; i < n; i++){ maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC); pInT1 += n; } // Update the status if the matrix is singular if(maxC == 0.0f){ return -1; } // Restore pInT1 pInT1 = pIn; // Destination pointer modifier k = 1u; // Check if the pivot element is the most significant of the column if( (in > 0.0f ? in : -in) != maxC){ // Loop over the number rows present below i = n - (l + 1u); while(i > 0u){ // Update the input and destination pointers pInT2 = pInT1 + (n * l); pOutT2 = pOutT1 + (n * k); // Look for the most significant element to // replace in the rows below if((*pInT2 > 0.0f ? *pInT2: -*pInT2) == maxC){ // Loop over number of columns // to the right of the pilot element j = n - l; while(j > 0u){ // Exchange the row elements of the input matrix Xchg = *pInT2; *pInT2++ = *pInT1; *pInT1++ = Xchg; // Decrement the loop counter j--; } // Loop over number of columns of the destination matrix j = n; while(j > 0u){ // Exchange the row elements of the destination matrix Xchg = *pOutT2; *pOutT2++ = *pOutT1; *pOutT1++ = Xchg; // Decrement the loop counter j--; } // Flag to indicate whether exchange is done or not flag = 1u; // Break after exchange is done break; } // Update the destination pointer modifier k++; // Decrement the loop counter i--; } } // Update the status if the matrix is singular if((flag != 1u) && (in == 0.0f)){ return -1; } // Points to the pivot row of input and destination matrices pPivotRowIn = pIn + (l * n); pPivotRowDst = pOut + (l * n); // Temporary pointers to the pivot row pointers pInT1 = pPivotRowIn; pInT2 = pPivotRowDst; // Pivot element of the row in = *pPivotRowIn; // Loop over number of columns // to the right of the pilot element j = (n - l); while(j > 0u){ // Divide each element of the row of the input matrix // by the pivot element in1 = *pInT1; *pInT1++ = in1 / in; // Decrement the loop counter j--; } // Loop over number of columns of the destination matrix j = n; while(j > 0u){ // Divide each element of the row of the destination matrix // by the pivot element in1 = *pInT2; *pInT2++ = in1 / in; // Decrement the loop counter j--; } // Replace the rows with the sum of that row and a multiple of row i // so that each new element in column i above row i is zero.*/ // Temporary pointers for input and destination matrices pInT1 = pIn; pInT2 = pOut; // index used to check for pivot element i = 0u; // Loop over number of rows // to be replaced by the sum of that row and a multiple of row i k = n; while(k > 0u){ // Check for the pivot element if(i == l){ // If the processing element is the pivot element, // only the columns to the right are to be processed pInT1 += n - l; pInT2 += n; } else{ // Element of the reference row in = *pInT1; // Working pointers for input and destination pivot rows pPRT_in = pPivotRowIn; pPRT_pDst = pPivotRowDst; // Loop over the number of columns to the right of the pivot element, // to replace the elements in the input matrix j = (n - l); while(j > 0u){ // Replace the element by the sum of that row // and a multiple of the reference row in1 = *pInT1; *pInT1++ = in1 - (in * *pPRT_in++); // Decrement the loop counter j--; } // Loop over the number of columns to // replace the elements in the destination matrix j = n; while(j > 0u){ // Replace the element by the sum of that row // and a multiple of the reference row in1 = *pInT2; *pInT2++ = in1 - (in * *pPRT_pDst++); // Decrement the loop counter j--; } } // Increment the temporary input pointer pInT1 = pInT1 + l; // Decrement the loop counter k--; // Increment the pivot index i++; } // Increment the input pointer pIn++; // Decrement the loop counter loopCnt--; // Increment the index modifier l++; } // Set status as SUCCESS status = 0; if((flag != 1u) && (in == 0.0f)){ status = -1; } // Return to application return (status); } #endif ================================================ FILE: miniIMU/miniMatrix.h ================================================ /* The MIT License (MIT) Copyright (c) 2015-? suhetao Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _MAXTRIX_H_ #define _MAXTRIX_H_ #include "FastMath.h" ////////////////////////////////////////////////////////////////////////// // void Matrix_Zero(float *A, unsigned short numRows, unsigned short numCols); void Matrix_Copy(float *pSrc, unsigned short numRows, unsigned short numCols, float *pDst); int Maxtrix_Add(float *pSrcA, unsigned short numRows, unsigned short numCols, float *pSrcB, float *pDst); int Maxtrix_Sub(float *pSrcA, unsigned short numRows, unsigned short numCols, float *pSrcB, float *pDst); int Matrix_Multiply(float* pSrcA, unsigned short numRowsA, unsigned short numColsA, float* pSrcB, unsigned short numColsB, float* pDst); void Matrix_Multiply_With_Transpose(float *A, unsigned short nrows, unsigned short ncols, float *B, unsigned short mrows, float *C); void Maxtrix_Transpose(float *pSrc, unsigned short nRows, unsigned short nCols, float *pDst); int Matrix_Inverse(float* pDst, unsigned short n, float * pSrc); #endif