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Directory structure:
gitextract_n515nfga/
├── .gitignore
├── chapter-acknowledge.tex
├── chapter-bibliography.tex
├── chapter-copyright.tex
├── chapter-instr-close.tex
├── chapter-instr-glance-16bit-arithmetic.tex
├── chapter-instr-glance-16bit-load.tex
├── chapter-instr-glance-8bit-arithmetic.tex
├── chapter-instr-glance-8bit-load.tex
├── chapter-instr-glance-alphabetical.tex
├── chapter-instr-glance-bit.tex
├── chapter-instr-glance-block.tex
├── chapter-instr-glance-call-return.tex
├── chapter-instr-glance-exchange.tex
├── chapter-instr-glance-general.tex
├── chapter-instr-glance-input.tex
├── chapter-instr-glance-jump.tex
├── chapter-instr-glance-next.tex
├── chapter-instr-glance-output.tex
├── chapter-instr-glance-rotate-shift.tex
├── chapter-instr-glance-stack.tex
├── chapter-instr-glance.tex
├── chapter-instr-sorted-mnemonic.tex
├── chapter-instr-sorted-opcode.tex
├── chapter-introduction.tex
├── chapter-license.tex
├── chapter-next-copper.tex
├── chapter-next-dma.tex
├── chapter-next-interrupts.tex
├── chapter-next-keyboard.tex
├── chapter-next-layer2.tex
├── chapter-next-memory.tex
├── chapter-next-palette.tex
├── chapter-next-ports.tex
├── chapter-next-sound.tex
├── chapter-next-sprites.tex
├── chapter-next-tilemap.tex
├── chapter-next-ula.tex
├── chapter-next.tex
├── chapter-title.tex
├── chapter-toc.tex
├── chapter-z80.tex
├── defines-dma.tex
├── defines-instr-close.tex
├── defines.tex
├── instructions.tex
├── ports.tex
├── readme.md
├── samples/
│ ├── copper/
│ │ ├── .vscode/
│ │ │ ├── launch.json
│ │ │ └── tasks.json
│ │ ├── build/
│ │ │ └── .gitignore
│ │ └── main.asm
│ ├── im1/
│ │ ├── .vscode/
│ │ │ ├── launch.json
│ │ │ └── tasks.json
│ │ ├── build/
│ │ │ └── .gitignore
│ │ └── main.asm
│ ├── im2/
│ │ ├── .vscode/
│ │ │ ├── launch.json
│ │ │ └── tasks.json
│ │ ├── build/
│ │ │ └── .gitignore
│ │ └── main.asm
│ ├── im2hw/
│ │ ├── .vscode/
│ │ │ ├── launch.json
│ │ │ └── tasks.json
│ │ ├── build/
│ │ │ └── .gitignore
│ │ └── main.asm
│ ├── im2safe/
│ │ ├── .vscode/
│ │ │ ├── launch.json
│ │ │ └── tasks.json
│ │ ├── build/
│ │ │ └── .gitignore
│ │ └── main.asm
│ ├── layer2-256x192/
│ │ ├── .vscode/
│ │ │ ├── launch.json
│ │ │ └── tasks.json
│ │ ├── build/
│ │ │ └── .gitignore
│ │ └── main.asm
│ ├── layer2-320x256/
│ │ ├── .vscode/
│ │ │ ├── launch.json
│ │ │ └── tasks.json
│ │ ├── build/
│ │ │ └── .gitignore
│ │ └── main.asm
│ ├── layer2-640x256/
│ │ ├── .vscode/
│ │ │ ├── launch.json
│ │ │ └── tasks.json
│ │ ├── build/
│ │ │ └── .gitignore
│ │ └── main.asm
│ ├── sound/
│ │ ├── .vscode/
│ │ │ ├── launch.json
│ │ │ └── tasks.json
│ │ ├── build/
│ │ │ └── .gitignore
│ │ └── main.asm
│ ├── sprites/
│ │ ├── .vscode/
│ │ │ ├── launch.json
│ │ │ └── tasks.json
│ │ ├── build/
│ │ │ └── .gitignore
│ │ ├── main.asm
│ │ └── sprites.spr
│ └── tilemap/
│ ├── .vscode/
│ │ ├── launch.json
│ │ └── tasks.json
│ ├── build/
│ │ └── .gitignore
│ ├── main.asm
│ ├── tiles.pal
│ └── tiles.spr
├── setup.tex
├── tables.tex
└── zx-next-dev-guide.tex
================================================
FILE CONTENTS
================================================
================================================
FILE: .gitignore
================================================
## Ignored project files and folders
Tools
## Core latex/pdflatex auxiliary files:
*.ptc
*.aux
*.lof
*.log
*.lot
*.fls
*.out
*.toc
*.fmt
*.fot
*.cb
*.cb2
.*.lb
## Intermediate documents:
*.dvi
*.xdv
*-converted-to.*
# these rules might exclude image files for figures etc.
*.ps
*.eps
*.pdf
## Generated if empty string is given at "Please type another file name for output:"
.pdf
## Bibliography auxiliary files (bibtex/biblatex/biber):
*.bbl
*.bcf
*.blg
*-blx.aux
*-blx.bib
*.run.xml
## Build tool auxiliary files:
*.fdb_latexmk
*.synctex
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*.synctex.gz(busy)
*.pdfsync
## Build tool directories for auxiliary files
# latexrun
latex.out/
## Auxiliary and intermediate files from other packages:
# algorithms
*.alg
*.loa
# achemso
acs-*.bib
# amsthm
*.thm
# beamer
*.nav
*.pre
*.snm
*.vrb
# changes
*.soc
# comment
*.cut
# cprotect
*.cpt
# elsarticle (documentclass of Elsevier journals)
*.spl
# endnotes
*.ent
# fixme
*.lox
# feynmf/feynmp
*.mf
*.mp
*.t[1-9]
*.t[1-9][0-9]
*.tfm
#(r)(e)ledmac/(r)(e)ledpar
*.end
*.?end
*.[1-9]
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*.[1-9][0-9][0-9]
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*.eledsec[1-9][0-9]R
*.eledsec[1-9][0-9][0-9]
*.eledsec[1-9][0-9][0-9]R
# glossaries
*.acn
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*.glsdefs
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*.lzs
# uncomment this for glossaries-extra (will ignore makeindex's style files!)
# *.ist
# gnuplottex
*-gnuplottex-*
# gregoriotex
*.gaux
*.gtex
# htlatex
*.4ct
*.4tc
*.idv
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*.trc
*.xref
# hyperref
*.brf
# knitr
*-concordance.tex
# TODO Uncomment the next line if you use knitr and want to ignore its generated tikz files
# *.tikz
*-tikzDictionary
# listings
*.lol
# luatexja-ruby
*.ltjruby
# makeidx
*.idx
*.ilg
*.ind
# minitoc
*.maf
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*.mtc
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*.slt[0-9]*
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# minted
_minted*
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*.mw
# nomencl
*.nlg
*.nlo
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# pax
*.pax
# pdfpcnotes
*.pdfpc
# sagetex
*.sagetex.sage
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*.sagetex.scmd
# scrwfile
*.wrt
# sympy
*.sout
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sympy-plots-for-*.tex/
# pdfcomment
*.upa
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# pythontex
*.pytxcode
pythontex-files-*/
# tcolorbox
*.listing
# thmtools
*.loe
# TikZ & PGF
*.dpth
*.md5
*.auxlock
# todonotes
*.tdo
# vhistory
*.hst
*.ver
# easy-todo
*.lod
# xcolor
*.xcp
# xmpincl
*.xmpi
# xindy
*.xdy
# xypic precompiled matrices and outlines
*.xyc
*.xyd
# endfloat
*.ttt
*.fff
# Latexian
TSWLatexianTemp*
## Editors:
# WinEdt
*.bak
*.sav
# Texpad
.texpadtmp
# LyX
*.lyx~
# Kile
*.backup
# gummi
.*.swp
# KBibTeX
*~[0-9]*
# TeXnicCenter
*.tps
# auto folder when using emacs and auctex
./auto/*
*.el
# expex forward references with \gathertags
*-tags.tex
# standalone packages
*.sta
# Makeindex log files
*.lpz
# xwatermark package
*.xwm
# REVTeX puts footnotes in the bibliography by default, unless the nofootinbib
# option is specified. Footnotes are the stored in a file with suffix Notes.bib.
# Uncomment the next line to have this generated file ignored.
#*Notes.bib
## Auto generated files for companion code
.tmp
================================================
FILE: chapter-acknowledge.tex
================================================
\begingroup
\WorkInProgressFullScreen
\textbf{Acknowlegements}
A lot of work has gone into this book. But I also learned a lot. Not just about Z80 and Next, also \LaTeX~which basics I learned in secondary school and then all but forgotten. In this regard, I'd like to thank Jan Wilmans and Sean Young for creating the original Z80 Undocumented that I took as a basis for this book. I also need to thank countless kind folks on \url{https://tex.stackexchange.com/}, those who asked questions and those who answered them; I found solutions to most issues I encountered there (and I was one very frequent visitor at times :) I'm very grateful to all members of {\tt z80-hardcore} Spectrum Next Discord channel who pointed out errors and shortcomings of the book but especially Peter Ped Helcmanovsky and Alvin Albrecht (aka Allen Albright) for help in fact-checking and pull request contributions. And last but not least, my family for being patient with my frequent long after-hours. Oh, also special shoutout to Bibi, our small JRT companion with the biggest heart :)
\vspace*{\fill}
\WorkInProgressFullScreen
\endgroup
================================================
FILE: chapter-bibliography.tex
================================================
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\begin{thebibliography}{}
\bibitem{mrison} Mark Rison Z80 page for !CPC. \\
{\tt \small http://www.acorn.co.uk/$\sim$mrison/en/cpc/tech.html}
\bibitem{yaze} YAZE (Yet Another Z80 Emulator). This is a CPM emulator by Frank Cringle. It emulates almost every undocumented flag, very good emulator. Also includes a very good instruction exerciser and is released under the GPL. \\
{\tt \small ftp://ftp.ping.de/pub/misc/emulators/yaze-1.10.tar.gz} \\
Note: the instruction exerciser zexdoc/zexall does not test I/O instructions and not all normal instructions (for instance LD A,(IX+n) is tested, but not with different values of n, just n=1, values above 128 (LD A,(IX-n) are not tested) but it still gives a pretty good idea of how well a simulated Z80 works.
\bibitem{thomas} Z80 Family Official Support Page by Thomas Scherrer. Very good -- your one-stop Z80 page. \\
{\tt \small http://www.geocities.com/SiliconValley/Peaks/3938/z80\_home.htm}
\bibitem{speccy_faq} Spectrum FAQ technical information. \\
{\tt \small http://www.worldofspectrum.org/faq/}
\bibitem{gerton} Gerton Lunter's Spectrum emulator (Z80). In the package there is a file TECHINFO.DOC, which contains a lot of interesting information. Note that the current version can only be unpacked in Windows. \\
{\tt \small ftp://ftp.void.jump.org/pub/sinclair/emulators/pc/dos/z80-400.zip}
\bibitem{mostek} Mostek Z80 Programming Manual -- a very good reference to the Z80.
\bibitem{datasheet} Z80 Product Specification, from MSX2 Hardware Information. \\
{\tt \small http://www.hardwareinfo.msx2.com/pdf/Zilog/z80.pdf}
\bibitem{zx_next} ZX Spectrum Next information. \\
{\tt \small \url{https://wiki.specnext.dev/}}
\end{thebibliography}
\pagebreak
\IntentionallyEmpty
\pagebreak
================================================
FILE: chapter-copyright.tex
================================================
\begingroup
{\WorkInProgressFullScreen}
\vspace*{\fill} % render at the bottom of the page
{\Large\textbf{\BookTitle}}
\vspace*{0.1cm}
{\large\AuthorNameSurname}
\LatestRevisionName{}
REVISIONS\\
\LatestRevisionDate{}\\
\RevisionTwoDate{}\\
\RevisionOneDate{}
\vspace*{0.2cm}
Copyright {\copyright} \LatestYear{} \AuthorNameSurname{}\\ % note this should become 2021-\LatestYear (aka 2021-2022) for releases after 2021...
Copyright {\copyright} 2005 Jan Wilmans\\
Copyright {\copyright} 1997, 1998, 2001, 2003, 2005 Sean Young
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.1 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled ``GNU Free Documentation License''.
\endgroup
================================================
FILE: chapter-instr-close.tex
================================================
\chapter{Instructions up Close}
\label{instruction_details}
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\input{defines-instr-close.tex}
The following pages describe all instructions in detail. Alphabetical order is used as much as possible, but some deviations were made to better fit to pages. Each instruction includes:
\begin{itemize}
\setlength\itemsep{1pt}
\item Mnemonic
\item Symbolic operation for quick info on what instruction does
\item All variants (where applicable)
\item Description with further details
\item Effects on flags
\item Timing table with machine cycles, T states and time required for execution on different CPU speeds
\end{itemize}
Where possible, multiple variants of same instruction are grouped together and where multiple timings are possible, timing table is sorted from quickest to slowest.
\pagebreak
\thispagestyle{plain} % use toc style without headers for this explanation page, it better matches chapter start page
\subsubsection{Flags}
\newcommand{\DetailsFlagTableList}[1]{
\vspace*{-2ex}
\setlist{leftmargin=1em,after=\vspace{-2ex}}
\begin{itemize}
\setlength\itemsep{-4pt}
#1
\end{itemize}
}
\newcommand{\DetailsFlagTableParagraph}{\vspace{1ex}}
{
\renewcommand{\arraystretch}{1.5}
\begin{tabularx}{\linewidth}{cX}
\FlagSF{} &
\textbf{Sign Flag} is set to twos-complement of the most-significant bit (bit 7) of the result of an instruction. If the result is positive (bit 7 is {\tt 0}), \FlagSF{} is set, and if the result is negative (bit 7 is {\tt 1}), \FlagSF{} is reset. This leaves bits 0-6 to represent the value. Positive numbers range from {\tt 0} to {\tt 127} and negative from {\tt -1} to {\tt -128}.
\\
\FlagZF{} &
\textbf{Zero Flag} depends on whether the result of an instruction is {\tt 0}. \FlagZF{} is set if the result if {\tt 0} and reset otherwise.
\\
\FlagHF{} &
\textbf{Half Carry Flag} represents a carry or borrow status between bits 3 and 4 of an 8-bit arithmetic operation (bits 11 and 12 for 16-bit operations). Set if:
\DetailsFlagTableList{
\item A carry from bit 3 to bit 4 occurs during addition (bit 11 to 12 for 16-bit operations)
\item A borrow from bit 4 occurs during subtraction (from bit 12 for 16-bit operations)
}
\\
\FlagPV{} &
\textbf{Parity/Overflow Flag} value depends on the type of the operation.
\DetailsFlagTableParagraph
For arithmetic operations, \FlagPV{} indicates an overflow. The flag is set when the sign of the result is different from the sign of the operands:
\DetailsFlagTableList{
\item all operands are positive but the result is negative or
\item all operands are negative but the result is positive
}
\DetailsFlagTableParagraph
For logical and rotate operations, \FlagPV{} indicates the parity of the result. The number of set bits in the result are counted. If the total is an even value, \FlagPV{} is set. If the total is odd, \FlagPV{} is reset.
\\
\FlagNF{} &
\textbf{Add/Subtract Flag} is used primarily for {\tt DAA} instruction to distinguish between add and subtract operations. But other instructions may also affect it as described in the following pages.
\\
\textbf{CF} &
\textbf{Carry Flag} represents a carry or borrow status for arithmetic operations. \textbf{CF} is set if add instruction generates a carry, or subtract generates a borrow.
\DetailsFlagTableParagraph
For rotate and shift instructions, \textbf{CF} is used:
\DetailsFlagTableList{
\item as a link between least-significat and most significant bit for {\tt RLA}, {\tt RL}, {\tt RRA} and {\tt RR}
\item contains the value shifted out of bit 7 for {\tt RLC}, {\tt RLCA} and {\tt SLA}
\item contains the value shifted out of bit 0 for {\tt RRC}, {\tt RRCA}, {\tt SRA} and {\tt SRL}
}
\DetailsFlagTableParagraph
Finally, some instructions directly affect the value of \textbf{CF}:
\DetailsFlagTableList{
\item reset with {\tt AND}, {\tt OR} and {\tt XOR}
\item set with {\tt SCF}
\item completed with {\tt CCF}
}
\\
\end{tabularx}
}
\subsubsection{Effects}
\begin{tabular}{cl}
{\tt 0} & Flag is set to {\tt 0} \\
{\tt 1} & Flag is set to {\tt 1} \\
{\tt \FS} & Flag is modified according to operation \\
{\tt \FN} & Flag is not affected \\
{\tt \FU} & Effect on flag is unpredictable \\
{\tt \FX} & Special case, see notes below effects table \\
\DetailParityOverflow{v} & P/V flag is used as overflow \\
\DetailParityOverflow{p} & P/V flag is used as parity \\
\DetailParityOverflow{} & P/V is undefined or indicates other result \\
\end{tabular}
\subsubsection{Abbreviations}
\begin{tabularx}{\textwidth}{lX}
{\tt r} &
8-bit register {\tt A}-{\tt L} \\
{\tt n} &
8-bit immediate value \\
{\tt rr} &
16-bit register pair {\tt AF}, {\tt BC}, {\tt DE}, {\tt HL}, {\tt IX}, {\tt IY}, {\tt SP} (note in some cases particular register pairs may use different timing from the rest; if so, those will be explicitly indicated in their own line; {\tt rr} may still be used, though in those cases it will cover the remaining registers only) \\
{\tt nn} &
16-bit immediate value \\
{\tt s} &
Placeholder for argument when multiple variants are possible \\
{\tt d} &
If instruction takes 2 operands, {\tt d} indicates destination and {\tt s} source \\
\UNDOC & Indicates undocumented instruction \\
\ZXN & Indicates ZX Spectrum Next extended instruction \\
\end{tabularx}
\pagebreak
\IntentionallyEmpty
\pagebreak
\begin{basedescript}{
% setup basedescript styling for labels
\desclabelstyle{\multilinelabel}
\desclabelwidth{3cm}}
% setup spacing between items
\setlength\itemsep{1.5em}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{ADC}{d,s}
{\IH{AD}d with \IH{C}arry}
{\SymADC{d}{s}}
\begin{DetailVariants}[p{1.9cm}p{1.9cm}Xp{2.8cm}p{2.4cm}]
\textnormal{8 bit} & \textnormal{8 bit} & \textnormal{8 bit} & \textnormal{8 bit} & \textnormal{16 bit} \\
ADC A,A & ADC A,E & ADC A,(HL) & ADC A,IXH\UNDOC & ADC HL,BC \\
ADC A,B & ADC A,H & ADC A,(IX+d) & ADC A,IXL\UNDOC & ADC HL,DE \\
ADC A,C & ADC A,L & ADC A,(IY+d) & ADC A,IYH\UNDOC & ADC HL,HL \\
ADC A,D & ADC A,n & & ADC A,IYL\UNDOC & ADC HL,SP \\
\end{DetailVariants}
Adds source operand {\tt s} or contents of the memory location addressed by {\tt s} and value of carry flag to destination {\tt d}. Result is then stored to destination {\tt d}.
\begin{DetailEffects}[v]
\FlagsADCr[8-bit]
\FlagsADCrr[16-bit]
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign}
\DetailFlagZF{\DetailFlagResultZero}
\DetailFlagHF{\DetailFlagResultHalfCarry}*
\DetailFlagPV{\DetailFlagResultOverflow}*
\DetailFlagCF{\DetailFlagResultCarry}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[A,r]{1}{4}
\DetailTime[A,n]{2}{7}
\DetailTime[A,(HL)]{2}{7}
\DetailTime[HL,rr]{4}{15}
\DetailTime[A,(IX+d)]{5}{19}
\DetailTime[A,(IY+d)]{5}{19}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{ADD}{d,s}
{\IH{ADD}}
{\SymADD{d}{s}}
\begin{DetailVariants}[p{1.9cm}Xp{2.3cm}p{2.3cm}p{2.4cm}]
\textnormal{8-bit} & \textnormal{8-bit} & \textnormal{16-bit} & \textnormal{16-bit} & \textnormal{ZX Next} \\
ADD A,A & ADD A,(HL) & ADD IX,BC & ADD HL,BC & ADD BC,A\ZXN \\
ADD A,B & ADD A,(IX+d) & ADD IX,DE & ADD HL,DE & ADD DE,A\ZXN \\
ADD A,C & ADD A,(IY+d) & ADD IX,IX & ADD HL,HL & ADD HL,A\ZXN \\
ADD A,D & ADD A,IXH\UNDOC & ADD IX,SP & ADD HL,SP & ADD BE,nn\ZXN \\
ADD A,E & ADD A,IXL\UNDOC & ADD IY,BC & & ADD DE,nn\ZXN \\
ADD A,H & ADD A,IYH\UNDOC & ADD IY,DE & & ADD HL,nn\ZXN \\
ADD A,L & ADD A,IYL\UNDOC & ADD IY,IY \\
ADD A,n & & ADD IY,SP \\
\end{DetailVariants}
Similar to {\tt ADC} except carry flag is not used in calculation: adds operand {\tt s} or contents of the memory location addressed by {\tt s} to destination {\tt d}. Result is then stored to destination {\tt d}.
ZX Next Extended instructions for adding {\tt A} to 16-bit register pair, zero extend {\tt A} to 16-bits.
\begin{DetailEffects}[v]
\FlagsADDr[8-bit]
\FlagsADDrr[16-bit]
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF[8-bit only, set if:]{\DetailFlagResultSign}
\DetailFlagZF[8-bit only, set if:]{\DetailFlagResultZero}
\DetailFlagHF{\DetailFlagResultHalfCarry*}*
\DetailFlagPV[8-bit only, set if:]{\DetailFlagResultOverflow}*
\DetailFlagCF{\DetailFlagResultCarry*}
\end{DetailEffectsFlags}
\begin{DetailEffects}
\FlagsADDrra[\tt ADD rr,A\ZXN]
\FlagsADDrrnn[\tt ADD rr,nn\ZXN]
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime[A,r]{1}{4}
\DetailTime[A,n]{2}{7}
\DetailTime[A,(HL)]{2}{7}
\DetailTime[rr,A\ZXN]{2}{8}
\DetailTime[HL,rr]{3}{11}
\DetailTime[IX,rr]{4}{15}
\DetailTime[IY,rr]{4}{15}
\DetailTime[rr,nn\ZXN]{4}{16}
\DetailTime[A,(IX+d)]{5}{19}
\DetailTime[A,(IY+d)]{5}{19}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{AND}{s}
{bitwise \IH{AND}}
{\SymAND{s}}
\begin{DetailVariants}[4]
AND A\\
AND B\\
AND C\\
AND D
\columnbreak
AND E\\
AND H\\
AND L\\
AND n
\columnbreak
AND (HL)\\
AND (IX+d)\\
AND (IY+d)
\columnbreak
AND IXH\UNDOC\\
AND IXL\UNDOC\\
AND IYH\UNDOC\\
AND IYL\UNDOC
\end{DetailVariants}
\begin{tabularx}{\linewidth}{@{}Xl}
Performs bitwise AND between accumulator {\tt A} and the given operand. The result is then stored back to the accumulator. Individual bits are AND'ed as shown on the right:
&
\begin{tabular}[t]{cc|c}
{\tt A} & {\tt s} & Result \\
\hline
{\tt 0} & {\tt 0} & {\tt 0} \\
{\tt 0} & {\tt 1} & {\tt 0} \\
{\tt 1} & {\tt 0} & {\tt 0} \\
{\tt 1} & {\tt 1} & {\tt 1} \\
\end{tabular}
\\
\end{tabularx}
\begin{DetailEffects}[p]
\FlagsANDr
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign}
\DetailFlagZF{\DetailFlagResultZero}
\DetailFlagPV{\DetailFlagResultParity}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[r]{1}{4}
\DetailTime[n]{2}{7}
\DetailTime[(HL)]{2}{7}
\DetailTime[(IX+d)]{5}{19}
\DetailTime[(IY+d)]{5}{19}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{BIT}{b,s}
{test \IH{BIT}}
{\SymBIT{s}}
\begin{DetailVariants}
BIT b,A\\
BIT b,B\\
BIT b,C\\
BIT b,D
\columnbreak
BIT b,E\\
BIT b,H\\
BIT b,L
\columnbreak
BIT b,(HL)\\
BIT b,(IX+d)\\
BIT b,(IY+d)
\end{DetailVariants}
Tests specified bit {\tt b} ({\tt 0-7}) of the given register {\tt s} or contents of memory addressed by {\tt s} and sets zero flag according to result; if bit was 1, \FlagZF{} is 0 and vice versa.
\begin{DetailEffects}
\FlagsBITr
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagZF{bit {\tt b} of the given source argument is {\tt 0}}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[b,r]{2}{8}
\DetailTime[b,(HL)]{3}{12}
\DetailTime[b,(IX+d)]{5}{20}
\DetailTime[b,(IY+d)]{5}{20}
\end{DetailTiming}
\end{DetailItem}
% these instructions should be here in alphabetical order, but I want them to be placed on the same page spread so reader can check the differences easily
\DetailItemsSeePageReference{BRLC, BSLA, BSRA, BSRF, BSRL}{See pages \DetailItemPageRef{BRLC} and \DetailItemPageRef{BSRL}}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{CALL}{nn}
{\IH{CALL} subroutine}
{\SymCALL{nn}}
Pushes program counter {\tt PC} to stack and calls subroutine at the given location {\tt nn} by changing {\tt PC} to point to address {\tt nn}.
\begin{DetailEffects}
\FlagsCALLnn
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{5}{17}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{CALL c,nn}{}
{\IH{CALL} subroutine conditionally}
{\SymCALLc{nn}}
\vspace{1ex} % we need some vertical space to achieve same separation as multicols
\begin{tabular}{@{}llcll}
{\tt CALL C,nn} & calls if \FlagCF{} is set & &
{\tt CALL M,nn} & calls if \FlagSF{} is set\\
{\tt CALL NC,nn} & calls if \FlagCF{} is reset & &
{\tt CALL P,nn} & calls if \FlagSF{} is reset\\
{\tt CALL Z,nn} & calls if \FlagZF{} is set & &
{\tt CALL PE,nn} & calls if \FlagPV{} is set\\
{\tt CALL NZ,nn} & calls if \FlagZF{} is reset & &
{\tt CALL PO,nn} & calls if \FlagPV{} is reset\\
\end{tabular}
If the given condition is met, {\tt CALL nn} is performed, as described above.
\begin{DetailEffects}
\FlagsCALLccnn
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime[c\normalfont{=false}]{3}{10}
\DetailTime[c\normalfont{=true}]{5}{17}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{BRLC}{DE,B\ZXN}
{\IH{B}arrel \IH{R}otate \IH{L}eft \IH{C}ircular}
{\SymBRLC}
Rotates value in register pair {\tt DE} left for the amount given in bits 3-0 (low nibble) of register {\tt B}. To rotate right, use formula: {\tt B=16-places}. The result is stored in {\tt DE}.
\begin{DetailEffects}
\FlagsBRLC
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{2}{8}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{BSLA}{DE,B\ZXN}
{\IH{B}arrel \IH{S}hift \IH{L}eft \IH{A}rithmetic}
{\SymBSLA}
Performs shift left of the value in register pair {\tt DE} for the amount given in lower 5 bits of register {\tt B}. The result is stored in {\tt DE}.
\begin{DetailEffects}
\FlagsBSLA
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{2}{8}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{BSRA}{DE,B\ZXN}
{\IH{B}arrel \IH{S}hift \IH{R}ight \IH{A}rithmetic}
{\SymBSRA}
Performs arithmetical shift right of the value in register pair {\tt DE} for the amount given in lower 5 bits of register {\tt B}. The result is stored in {\tt DE}.
\begin{DetailEffects}
\FlagsBSRA
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{2}{8}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{BSRF}{DE,B\ZXN}
{\IH{B}arrel \IH{S}hift \IH{R}ight \IH{F}ill-one}
{\SymBSRF}
Performs fill-one-way shift right of the value in register pair {\tt DE} for the amount given in lower 5 bits of register {\tt B}. The result is stored in {\tt DE}.
\begin{DetailEffects}
\FlagsBSRF
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{2}{8}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{BSRL}{DE,B\ZXN}
{\IH{B}arrel \IH{S}hift \IH{R}ight \IH{L}ogical}
{\SymBSRL}
Performs logical shift right of the value in register pair {\tt DE} for the amount given in lower 5 bits of register {\tt B}. The result is stored in {\tt DE}.
\begin{DetailEffects}
\FlagsBSRL
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{2}{8}
\end{DetailTiming}
\end{DetailItem}
% CALL instructions should be here in alphabetical order, but I placed them before B*** above so they can be in the same page spread
\DetailItemSeePageReference{CALL}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{CCF}{}
{\IH{C}omplement \IH{C}arry \IH{F}lag}
{\SymCCF}
Complements (inverts) carry flag \FlagCF{}; if \FlagCF{} was {\tt 0} it's now {\tt 1} and vice versa. Previous value of \FlagCF{} is copied to \FlagHF{}.
\begin{DetailEffects}
\FlagsCCF
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagHF[]{Documentation says original value of \FlagCF{} is copied to \FlagHF{}, however under my tests \FlagHF{} remained unchanged}
\DetailFlagCF[]{if \FlagCF{} was {\tt 0} it's now {\tt 1} and vice versa}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{1}{4}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{CP}{s}
{\IH{C}om\IH{P}are}
{\SymCP{s}}
\begin{DetailVariants}[4]
CP A\\
CP B\\
CP C\\
CP D
\columnbreak
CP E\\
CP H\\
CP L\\
CP n
\columnbreak
CP (HL)\\
CP (IX+d)\\
CP (IY+d)
\columnbreak
CP IXH\UNDOC\\
CP IXL\UNDOC\\
CP IYH\UNDOC\\
CP IYL\UNDOC
\end{DetailVariants}
Operand {\tt s} or content of the memory location addressed by {\tt s} is subtracted from accumulator {\tt A}. Status flags are updated according to the result, but the result is then discarded (value of {\tt A} is not changed).
\begin{DetailEffects}[v]
\FlagsCPr
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagHF{\DetailFlagResultHalfBorrow}*
\DetailFlagPV{
\DetailFlagsList{
\item {\tt A} and {\tt s} positive and {\tt A-s} result negative
\item {\tt A} and {\tt s} negative and {\tt A-s} result positve
}
\DetailFlagResultOverflowListBottomSpacing % we don't want additional space below the table, otherwise next item would have larger gap
}
\end{DetailEffectsFlags}
Other flags are set like this when {\tt A} is greater than, equal or less than {\tt s}:
\begin{DetailEffects}[v][]
\Flags[A$>$s]{0}{0}{\FS}{\FS}{1}{0}
\Flags[A$=$s]{0}{1}{\FS}{\FS}{1}{0}
\Flags[A$<$s]{1}{0}{\FS}{\FS}{1}{1}
\end{DetailEffects}
With this in mind, we can derive the programs for common comparisons:
\newcommand{\CPExampleTitle}[1]{{\tt #1}\vspace{-1.5ex}}
%-----------------------------------------------------------------------------------------------------
\begin{multicols}{2}
\CPExampleTitle{A=s}
\begin{tcblisting}{right skip=1em}
CP s
JP Z, true ; A=s?
false: ; A!=s
true: ; A=s
\end{tcblisting}
\CPExampleTitle{A$\neq$s}
\begin{tcblisting}{}
CP s
JP NZ, true ; A!=s?
false: ; A=s
true: ; A!=s
\end{tcblisting}
\end{multicols}
%-----------------------------------------------------------------------------------------------------
\begin{multicols}{2}
\CPExampleTitle{A$\leqslant$s}
\begin{tcblisting}{right skip=1em}
CP s
JP M, true ; A<s?
JP Z, true ; A=s?
false: ; A>s
true: ; A<=s
\end{tcblisting}
\columnbreak
\CPExampleTitle{A<s}
\begin{tcblisting}{}
CP s
JP M, true ; A<s?
false: ; A>=s
true: ; A<s
\end{tcblisting}
\end{multicols}
%-----------------------------------------------------------------------------------------------------
\begin{multicols}{2}
\CPExampleTitle{A$\geqslant$s}
\begin{tcblisting}{right skip=1em}
CP s
JP M, false ; A<s?
true: ; A>=s
false: ; A<s
\end{tcblisting}
\columnbreak
\CPExampleTitle{A>s}
\begin{tcblisting}{}
CP s
JP M, false ; A<s?
JP Z, false ; A=s?
true: ; A>s
false: ; A<=s
\end{tcblisting}
\end{multicols}
\DetailNote[-1ex]{
Note: the examples use two labels to emphasize both results. But only one is needed. Furthermore, depending on the actual needs, the programs can also use no label at all. For example, we can use {\tt RET} instead of {\tt JP} when used within a subroutine, and the desired outcome is to return if the condition is not met:
}
%-----------------------------------------------------------------------------------------------------
\begin{multicols}{2}
\CPExampleTitle{A=s}
\begin{tcblisting}{right skip=1em}
CP s
RET NZ ; A!=s?
; A=s
\end{tcblisting}
\CPExampleTitle{A$\neq$s}
\begin{tcblisting}{}
CP s
RET Z ; A=s?
; A!=s
\end{tcblisting}
\end{multicols}
%-----------------------------------------------------------------------------------------------------
\begin{multicols}{2}
\CPExampleTitle{A$\leqslant$s}
\begin{tcblisting}{right skip=1em}
CP s
JP M, true ; A<s?
JP Z, true ; A=s?
RET ; A>s
true: ; A<=s
\end{tcblisting}
\columnbreak
\CPExampleTitle{A<s}
\begin{tcblisting}{}
CP s
RET P ; A>=s?
; A<s
\end{tcblisting}
\end{multicols}
%-----------------------------------------------------------------------------------------------------
\begin{multicols}{2}
\CPExampleTitle{A$\geqslant$s}
\begin{tcblisting}{right skip=1em}
CP s
RET M ; A<s?
; A>=s
\end{tcblisting}
\CPExampleTitle{A>s}
\begin{tcblisting}{}
CP s
RET M ; A<s?
RET Z ; A=s?
; A>s
\end{tcblisting}
\end{multicols}
\DetailNote[-1ex]{
Note: some of the comparisons are reversed. And {\tt A$\leqslant$s} still requires a label because the condition is true if either \FlagSF{} or \FlagZF{} is set.
}
\DetailNote{
Note: I opted to use \FlagSF{} for some of the comparisons. It makes more sense to me this way. But you can just as well use \FlagCF{} instead. As evident from the table on the previous page, both flags are updated the same way, so you could use {\tt JP C} or {\tt RET C} instead of {\tt M} and {\tt JP NZ} or {\tt RET NZ} instead of {\tt P}. This is due to {\tt CP} performing a subtraction {\tt A-s} internally. So when {\tt s} is greater than {\tt A}, the result of the subtraction is negative, meaning the sign flag is set. At the same time a borrow is needed, so the carry is set too. I thought it's worth mentioning since you may find examples using the carry flag elsewhere and wonder why.
}
\vspace{2ex} % some vertical gap between notes and timings
\begin{DetailTiming}
\DetailTime[r]{1}{4}
\DetailTime[n]{2}{7}
\DetailTime[(HL)]{2}{7}
\DetailTime[(IX+d)]{5}{19}
\DetailTime[(IY+d)]{5}{19}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{CPD}{}
{\IH{C}om\IH{P}are and \IH{D}ecrement}
{\SymCPD}
Subtracts contents of memory location addressed by {\tt HL} register pair from accumulator {\tt A}. Result is then discarded. Afterwards both {\tt HL} and {\tt BC} are decremented.
\begin{DetailEffects}
\FlagsCPD
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{{\tt A<(HL)} before {\tt HL} is decremented}
\DetailFlagZF{{\tt A=(HL)} before {\tt HL} is decremented}
\DetailFlagPV{{\tt BC$\neq$0} after execution}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{4}{16}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{CPDR}{}
{\IH{C}om\IH{P}are and \IH{D}ecrement \IH{R}epeated}
{\SymCPDR}
Repeats {\tt CPD} until either {\tt A=(HL)} or {\tt BC=0}. If {\tt BC} is set to {\tt 0} before instruction execution, it loops through 64KB if no match is found. See {\tt CPIR} for example.
\begin{DetailEffects}
\FlagsCPDR
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{{\tt A<(HL)} before {\tt HL} is decremented}
\DetailFlagZF{{\tt A=(HL)} before {\tt HL} is decremented}
\DetailFlagPV{{\tt BC$\neq$0} after execution}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTimeRegular[{\tt BC}=0 or {\tt A}={\tt (HL)}]{4}{16}
\DetailTimeRegular[{\tt BC}$\neq$0 and {\tt A}$\neq${\tt (HL)}]{5}{21}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{CPI}{}
{\IH{C}om\IH{P}are and \IH{I}ncrement}
{\SymCPI}
Subtracts contents of memory location addressed by {\tt HL} register pair from accumulator {\tt A}. Result is then discarded. Afterwards {\tt HL} is incremented and {\tt BC} decremented.
\begin{DetailEffects}
\FlagsCPI
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{{\tt A<(HL)} before {\tt HL} is decremented}
\DetailFlagZF{{\tt A=(HL)} before {\tt HL} is decremented}
\DetailFlagPV{{\tt BC$\neq$0} after execution}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{4}{16}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{CPIR}{}
{\IH{C}om\IH{P}are and \IH{D}ecrement \IH{R}epeated}
{\SymCPIR}
Repeats {\tt CPI} until either {\tt A=(HL)} or {\tt BC=0}. If {\tt BC} is set to {\tt 0} before instruction execution, it loops through 64KB if no match is found.
Example, searching for {\tt \$AB} in memory from \MemAddr{0000}-\MemAddr{999}:
\begin{multicols}{2}
{\tt CPIR} = finding first occurrence:
\begin{tcblisting}{right skip=1em}
LD HL, &0000
LD BC, &0999
LD A, &AB
CPIR
\end{tcblisting}
{\tt CPDR} = finding last occurrence:
\begin{tcblisting}{}
LD HL, &0999
LD BC, &0999
LD A, &AB
CPDR
\end{tcblisting}
\end{multicols}
\begin{DetailEffects}
\FlagsCPIR
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{{\tt A<(HL)} before {\tt HL} is decremented}
\DetailFlagZF{{\tt A=(HL)} before {\tt HL} is decremented}
\DetailFlagPV{{\tt BC$\neq$0} after execution}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTimeRegular[{\tt BC}=0 or {\tt A}={\tt (HL)}]{4}{16}
\DetailTimeRegular[{\tt BC}$\neq$0 and {\tt A}$\neq${\tt (HL)}]{5}{21}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
% by moving CPL to next page, we can have DAA fit the whole of the page. Otherwise last part (timing) doesn't fit the same page (it's still in the same spread, but this way it's nicer)
\DetailItemsSeePageReference{CPL}{See next page}
\begin{DetailItem}{DAA}{}
{\IH{D}ecimal \IH{A}djust \IH{A}ccumulator}
{}
Updates accumulator {\tt A} for BCD correction after arithmetic operations using the following algorithm:
\begin{enumerate}
\item The least significant 4 bits of accumulator {\tt A} (low nibble) are checked first. If they contain invalid BCD number (greater than 9), or \FlagHF{} is set, the value of {\tt A} is adjusted based on the value of \FlagNF{}: if it's reset, {\tt \$06} is added to {\tt A}, if set, {\tt \$06} is removed from {\tt A}.
\item Then 4 most significant bits of accumulator {\tt A} (high nibble) are checked in a similar fashion. If they contain invalid BCD number, or \textbf{CF} is set, the value of {\tt A} is adjusted: if \FlagNF{} is not set, {\tt \$60} is added to {\tt A}, if \FlagNF{} is set, {\tt \$60} is removed from {\tt A}.
\item Finally flags are changed accordingly, as described below.
\end{enumerate}
% Symbolically, the algorithm could be expressed as:
% {
% \tt \small
% if (A$\wedge$\$0F>\$09)$\vee$(HF=1):\\
% \hspace*{1em}if NF=0:~A$\leftarrow$A+\$06~else:~A$\leftarrow$A-\$06\\
% if (A$\wedge$\$F0>\$90)$\vee$(CF=1):\\
% \hspace*{1em}if NF=0:~A$\leftarrow$A+\$60~else:~A$\leftarrow$A-\$60\\
% }
\begin{DetailEffects}[p]
\FlagsDAA
\end{DetailEffects}
\newcommand{\DAAIn}[1]{#1}
\newcommand{\DAAOut}[1]{\RArrow{6pt}#1}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign[A] after operation}
\DetailFlagZF{\DetailFlagResultZero[A] after operation}*
\DetailFlagHF[depends on:]{
input values of \FlagNF{}, \FlagHF{} and bits 0-3 of {\tt A}:
{
\tt
\begin{tabular}{ccc|c}
\DAAIn{NF} & \DAAIn{HF} & \DAAIn{A\textsubscript{{[}3-0{]}}} & \DAAOut{HF} \notet\noteb \\
\hline
0 & * & 0-9 & 0 \notet \\
0 & * & A-F & 1 \notet \\
1 & 0 & * & 0 \notet \\
1 & 1 & 0-5 & 1 \notet \\
1 & 1 & 6-F & 0 \notet\noteb \\
\end{tabular}
}
}*
\DetailFlagPV{\DetailFlagResultParity[A] after operation}
\end{DetailEffectsFlags}
\vspace*{-1ex} % using separate DetailEffectsFlags allows us to control vertical spacing between CF and PV
\begin{DetailEffectsFlags}
\DetailFlagCF[depends on:]{
input values of \textbf{CF} and both nibbles of {\tt A}:
{
\tt
\begin{tabular}{ccc|c}
\DAAIn{CF} & \DAAIn{A\textsubscript{{[}7-4{]}}} & \DAAIn{A\textsubscript{{[}3-0{]}}} & \DAAOut{CF} \notet\noteb \\
\hline
0 & 0-9 & 0-9 & 0 \notet \\
0 & 0-8 & A-F & 0 \notet \\
0 & 9-F & A-F & 1 \notet \\
0 & A-F & 0-9 & 1 \notet \\
1 & * & * & 1 \notet\noteb \\
\end{tabular}
}
}*
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{1}{4}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{CPL}{}
{\IH{C}om\IH{PL}ement accumulator}
{\SymCPL}
Complements (inverts) all bits of the accumulator {\tt A} and stores the result back to {\tt A}.
\begin{DetailEffects}
\FlagsCPL
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{1}{4}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{DEC}{s}
{\IH{DEC}rement}
{\SymDEC{s}}
\begin{DetailVariants}
\textnormal{8-bit}\\
DEC A\\
DEC B\\
DEC C\\
DEC D\\
DEC E\\
DEC H\\
DEC L
\columnbreak
\textnormal{8-bit}\\
DEC (HL)\\
DEC (IX+d)\\
DEC (IY+d)\\
DEC IXH\UNDOC\\
DEC IXL\UNDOC\\
DEC IYH\UNDOC\\
DEC IYL\UNDOC
\columnbreak
\textnormal{16-bit}\\
DEC BC\\
DEC DE\\
DEC HL\\
DEC IX\\
DEC IY\\
DEC SP
\end{DetailVariants}
Decrements the operand {\tt s} or memory addressed by {\tt s} by 1.
\begin{DetailEffects}[v]
\FlagsDECr[8-bit]
\FlagsDECrr[16-bit (no effect)]
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF[8-bit only, set if:]{\DetailFlagResultSign}
\DetailFlagZF[8-bit only, set if:]{\DetailFlagResultZero}
\DetailFlagHF[8-bit only, set if:]{\DetailFlagResultHalfBorrow}
\DetailFlagPV[8-bit only, set if:]{value was {\tt \$80} before decrementing}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[r]{1}{4}
\DetailTime[rr]{1}{6}
\DetailTime[IX]{2}{10}
\DetailTime[IY]{2}{10}
\DetailTime[(HL)]{3}{11}
\DetailTime[(IX+d)]{6}{23}
\DetailTime[(IY+d)]{6}{23}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{DI}{}
{\IH{D}isable \IH{I}nterrupts}
{\SymDI}
Disables all maskable interrupts (mode 1 and 2). Interrupts are disabled after execution of the instruction following {\tt DI}. See sections \XRef{z80_interrupts} and \XRef{zx_next_interrupts} for more details on interrupts.
\begin{DetailEffects}
\FlagsDI
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{1}{4}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{DJNZ}{e}
{\IH{D}ecrement {\tt B} and \IH{J}ump if \IH{N}ot \IH{Z}ero}
{\SymDJNZ{e}}
Decrements {\tt B} register and jumps to the given relative address if {\tt B$\neq$0}. Given offset is added to the value of {\tt PC} after parsing {\tt DJNZ} instruction, so effective offset it {\tt -126} to {\tt +129}. Assembler automatically subtracts {\tt 2} from offset value {\tt e} to generate opcode.
\begin{DetailEffects}
\FlagsDJNZ
\end{DetailEffects}
\begin{DetailTiming}
\DetailTimeRegular[{\tt B}=0]{2}{8}
\DetailTimeRegular[{\tt B}$\neq$0]{3}{13}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{EI}{}
{\IH{E}nable \IH{I}nterrupts}
{\SymEI}
Enables maskable interrupts (mode 1 and 2). Interrupts are enabled after execution of the instruction following {\tt EI}; typically {\tt RETI} or {\tt RETN}. See sections \XRef{z80_interrupts} and \XRef{zx_next_interrupts} for more details on interrupts.
\begin{DetailEffects}
\FlagsEI
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{1}{4}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{EX}{d,s}
{\IH{EX}change register pair}
{\SymEX{d}{s}}
\begin{DetailVariants}
EX AF,AF'\\
EX DE,HL\\
\columnbreak
EX (SP),HL\\
EX (SP),IX\\
EX (SP),IY
\end{DetailVariants}
Exchanges contents of two register pairs or register pair and last value pushed to stack. For example:
\begin{tabular}{llcl}
\multicolumn{2}{c}{BEFORE} & & AFTER \\[5pt]
Reg & \multicolumn{3}{l}{Value} \\[5pt]
{\tt HL} &
\MemAddr{ABCD} &
\multirow{5}{*}{$\rightarrow$ {\tt EX (SP),HL} $\rightarrow$} &
\MemAddr{3412}\\
{\tt SP} & \MemAddr{0B00} & & \MemAddr{0B00}\\[5pt]
Mem & Value \\[5pt]
\MemAddr{0B00} & {\tt \$12} & & {\tt \$CD}\\
\MemAddr{0B01} & {\tt \$34} & & {\tt \$AB}\\
\end{tabular}\\[5pt] % some spacing between table and effects
\begin{DetailEffects}
\FlagsEXaf[{\tt EX AF,AF'}]
\FlagsEXrr[Other variants no effect]
\DetailFlagsComments{
\item {\tt EX AF,AF'} sets flags directly from the value of {\tt F'}
}
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime[rr,rr]{1}{4}
\DetailTime[(SP),HL]{5}{19}
\DetailTime[(SP),IX]{6}{23}
\DetailTime[(SP),IY]{6}{23}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{EXX}{}
{\IH{EX}change alternate registers}
{\SymEXX}
Exchanges contents of registers {\tt BC}, {\tt DE} and {\tt HL} with shadow registers {\tt BC'}, {\tt DE'} and {\tt HL'}. The most frequent use is in interrupt handlers as an alternative to using the stack for saving and restoring register values. If using outside interrupt handlers, interrupts must be disabled before using this instruction.
\begin{DetailEffects}
\FlagsEXX
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{1}{4}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{HALT}{}
{\IH{HALT}}
{}
Suspends CPU and executes {\tt NOP}s (to continue memory refresh cycles) until the next interrupt or reset. This effectively creates a delay. You can chain {\tt HALT}s. But make sure that there will be an interrupt, otherwise {\tt HALT} will run forever.
\begin{DetailEffects}
\FlagsHALT
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{1}{4}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{IM}{n}
{\IH{I}nterrupt \IH{M}ode}
{}
\begin{DetailVariants}[2]
IM 0\\
IM 1\\
IM 2
\columnbreak
~
\end{DetailVariants}
Sets the interrupt mode. All 3 interrupts are maskable, meaning they can be disabled using {\tt DI} instruction. See sections \XRef{z80_interrupts} and \XRef{zx_next_interrupts} for details and example.
\begin{DetailEffects}
\FlagsIM
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{2}{8}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{IN}{r,(s)}
{\IH{IN}put from port}
{\SymIN{r}{s}}
\begin{DetailVariants}
IN A,(n)\\
IN A,(C)\\
IN B,(C)\\
IN C,(C)\\
IN D,(C)\\
IN E,(C)\\
IN H,(C)\\
IN L,(C)\\
IN (C)\UNDOC\\
IN F,(C)\UNDOC
\end{DetailVariants}
Reads peripheral device addressed by {\tt BC} or combination of {\tt A} and immediate value and stores result in given register. The address is provided as follows:
\begin{tabular}{ccc}
& \multicolumn{2}{c}{Address Bits} \\
Variant & {\tt 15-8} & {\tt 7-0} \\
\hline
{\tt IN A,(n)} & {\tt A} & {\tt n} \\
{\tt IN r,(C)} & {\tt B} & {\tt C} \\
\end{tabular}
\vspace{1ex} % some spacing before next text for less cluttered layout
So these two have the same result (though, as mentioned in section \XRef{zx_next_keyboard}, variant on the right is slightly faster, 18 vs 22 T states):
\begin{multicols}{2}
\begin{tcblisting}{right skip=1em}
LD BC, &DFFE
IN A, (C)
\end{tcblisting}
\columnbreak
\begin{tcblisting}{}
LD A, &DF
IN A, (&FE)
\end{tcblisting}
\end{multicols}
\begin{DetailEffects}[p]
\FlagsINrc[\tt IN r,(C)]
\FlagsINan[{\tt IN A,(n)} no effect]
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF[{\tt \small IN r,(C)}, set if:]{input data is negative (bit 7 is set)}
\DetailFlagZF[{\tt \small IN r,(C)}, set if:]{input data is {\tt 0}}
\DetailFlagPV[{\tt \small IN r,(C)}, set if:]{input data has even number of bits set}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[r,(n)]{3}{11}
\DetailTime[r,(C)]{3}{12}
\end{DetailTiming}
\DetailNote{Note: {\tt IN (C)} (or its alternative form {\tt IN F,(C)}) performs an input, but does not store the result, only sets the flags.}
\DetailNote[]{Note: some assemblers also allow {\tt (BC)} to be used instead of {\tt (C)}.}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{INC}{s}
{\IH{INC}rement}
{\SymINC{s}}
\begin{DetailVariants}
\textnormal{8-bit}\\
INC A\\
INC B\\
INC C\\
INC D\\
INC E\\
INC H\\
INC L
\textnormal{8-bit}\\
INC (HL)\\
INC (IX+d)\\
INC (IY+d)\\
INC IXH\UNDOC\\
INC IXL\UNDOC\\
INC IYH\UNDOC\\
INC IYL\UNDOC
\textnormal{16-bit}\\
INC BC\\
INC DE\\
INC HL\\
INC IX\\
INC IY\\
INC SP
\end{DetailVariants}
Increments the operand {\tt s} or memory addressed by {\tt s} by 1.
\begin{DetailEffects}[v]
\FlagsINCr[8-bit]
\FlagsINCrr[16-bit (no effect)]
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF[8-bit only, set if:]{\DetailFlagResultSign}
\DetailFlagZF[8-bit only, set if:]{\DetailFlagResultZero}
\DetailFlagHF[8-bit only, set if:]{\DetailFlagResultHalfCarry}
\DetailFlagPV[8-bit only, set if:]{value was {\tt \$7F} before incrementing}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[r]{1}{6}
\DetailTime[rr]{1}{6}
\DetailTime[IX]{2}{10}
\DetailTime[IY]{2}{10}
\DetailTime[(HL)]{3}{11}
\DetailTime[(IX+d)]{6}{23}
\DetailTime[(IY+d)]{6}{23}
\end{DetailTiming}
\end{DetailItem}
% with an empty page, we can achieve nice spreads for upcoming related instructions...
\pagebreak
\IntentionallyEmpty
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{IND}{}
{\IH{IN}put and \IH{D}ecrement}
{\SymIND}
Reads peripheral device addressed by {\tt BC} and stores the result in memory addressed by {\tt HL} register pair. Then decrements {\tt HL} and {\tt B}.
\begin{DetailEffects}
\FlagsIND
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\DetailFlagZF{{\tt B} becomes zero after decrementing}
\DetailFlagHF[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\DetailFlagPV[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{4}{16}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{INDR}{}
{\IH{IN}put and \IH{D}ecrement \IH{R}epeated}
{\SymINDR}
Repeats {\tt IND} until {\tt B=0}.
\begin{DetailEffects}
\FlagsINDR
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\DetailFlagHF[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\DetailFlagPV[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTimeRegular[{\tt B}=0]{4}{16}
\DetailTimeRegular[{\tt B}$\neq$0]{5}{21}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{INI}{}
{\IH{IN}put and \IH{I}ncrement}
{\SymINI}
Reads peripheral device addressed by {\tt BC} and stores the result in memory addressed by {\tt HL} register pair. Then increments {\tt HL} and decrements {\tt B}.
\begin{DetailEffects}
\FlagsINI
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\DetailFlagZF{{\tt B} becomes zero after decrementing}
\DetailFlagHF[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\DetailFlagPV[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{4}{16}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{INIR}{}
{\IH{IN}put and \IH{I}ncrement \IH{R}epeated}
{\SymINIR}
Repeats {\tt INI} until {\tt B=0}.
\begin{DetailEffects}
\FlagsINIR
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\DetailFlagHF[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\DetailFlagPV[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTimeRegular[{\tt B}=0]{4}{16}
\DetailTimeRegular[{\tt B}$\neq$0]{5}{21}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{JP}{nn}
{\IH{J}um\IH{P}}
{\SymJP{nn}}
\begin{DetailVariants}
JP nn\\
JP (HL)
\columnbreak
JP (IX)\\
JP (IY)
\end{DetailVariants}
Unconditionally jumps (changes program counter {\tt PC} to point) to the given absolute address or the memory location addressed by register pair. Unconditional jumps are the fastest way of changing program counter, even faster than {\tt JR}, but they take more bytes.
\begin{DetailEffects}
\FlagsJPnn
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime[(HL)]{1}{4}
\DetailTime[(IX)]{2}{8}
\DetailTime[(IY)]{2}{8}
\DetailTime[nn]{3}{10}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{JP c,nn}{}
{\IH{J}um\IH{P} conditionally}
{\SymJPc{nn}}
\vspace{1ex} % we need some vertical space to achieve same separation as with multicols
\begin{tabular}{@{}llcll}
{\tt JP C,nn} & jumps if \FlagCF{} is set & &
{\tt JP M,nn} & jumps if \FlagSF{} is set\\
{\tt JP NC,nn} & jumps if \FlagCF{} is reset & &
{\tt JP P,nn} & jumps if \FlagSF{} is reset\\
{\tt JP Z,nn} & jumps if \FlagZF{} is set & &
{\tt JP PE,nn} & jumps if \FlagPV{} is set\\
{\tt JP NZ,nn} & jumps if \FlagZF{} is reset & &
{\tt JP PO,nn} & jumps if \FlagPV{} is reset\\
\end{tabular}
Conditionally jumps to the given absolute address. See {\tt CP} on page \DetailItemPageRef{CP} for more details on comparisons.
\begin{DetailEffects}
\FlagsJPccnn
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{3}{10}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{JP (C)}{\DetailItemZXN}
{\IH{J}um\IH{P}}
{\SymJPC}
Sets bottom 14 bits of current program counter {\tt PC}\See{*} to value read from I/O port: {\tt PC[13-0] = (IN (C) << 6)}. Can be used to execute code block read from a disk stream.
\DetailNote[]{\See{*}``Current {\tt PC}'' is the address of the next instruction after {\tt JP (C)}; {\tt PC} was already advanced after fetching {\tt JP (C)} instruction from memory. If {\tt JP (C)} instruction is located at the very end of 16K memory block (\MemAddr{..FE} or \MemAddr{..FF} address), then the new {\tt PC} value will land into the following 16K block.}
\begin{DetailEffects}
\FlagsJPc
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{3}{13}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{JR}{e}
{\IH{J}ump \IH{R}elative}
{\SymJR{e}}
Unconditionally performs relative jump. Offset {\tt e} is added to the value of program counter {\tt PC} as signed value to allow jumps forward and backward. Offset is added to {\tt PC} after {\tt JR} instruction is read (aka {\tt PC+2}), so offset is in the range of {\tt -126} to {\tt 129}. Assembler automatically subtracts {\tt 2} from offset value {\tt e} to generate opcode.
\begin{DetailEffects}
\FlagsJRn
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{3}{12}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{JR c,n}{}
{\IH{J}ump \IH{R}elative conditionally}
{\SymJRc{c}{n}}
\vspace{1ex} % we need some vertical space to achieve same separation as with multicols
\begin{tabular}{@{}llcll}
{\tt JR C,e} & jumps if \FlagCF{} is set & &
{\tt JR Z,e} & jumps if \FlagZF{} is set\\
{\tt JR NC,e} & jumps if \FlagCF{} is reset & &
{\tt JR NZ,e} & jumps if \FlagZF{} is reset\\
\end{tabular}
Conditionally performs relative jump. Note: in contrast to {\tt JP}, {\tt JR} only supports above 4 conditions. See {\tt CP} on page \DetailItemPageRef{CP} for more details on conditions.
\begin{DetailEffects}
\FlagsJRccn
\end{DetailEffects}
\begin{DetailTiming}
\DetailTimeRegular[{\tt c}=false]{2}{7}
\DetailTimeRegular[{\tt c}=true]{3}{12}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{LD}{d,s}
{\IH{L}oa\IH{D}}
{\SymLD{d}{s}}
Loads source {\tt s} into destination {\tt d}. The following combinations are allowed (source {\tt s} is represented horizontally, destination {\tt d} vertically):
{
\fontsize{10pt}{10pt} % 9pt results in slightly wider table than the rest of the text, but the larger the font, more readable it is, so I prefer it this way (originally \scripsize was used which makes the table slightly slimer than the rest of the text)
\setlength{\tabcolsep}{1pt}
% note: OO and ii were chosen simply because the difference is noticable in the table below...
% note: OQ and ik are the same, but darker backgrounds
\newcommand{\OO}{$\bullet$}
\newcommand{\OQ}{\cellcolor{PrintableLightMidGray}$\bullet$}
\newcommand{\ii}{\cellcolor{PrintableLightGray}}
\newcommand{\ik}{\cellcolor{PrintableMidGray}}
\newcommand{\Small}[1]{\FontSize{8.5pt}{#1}}
\newcommand{\Mini}[1]{\FontSize{7.5pt}{#1}}
\newcolumntype{A}{>{\centering\arraybackslash}p{2.6ex}} % A...
\newcolumntype{B}{>{\centering\arraybackslash}p{2.8ex}} % BC...
\newcolumntype{D}{>{\centering\arraybackslash}p{3.7ex}} % (BC)...
\newcolumntype{E}{>{\centering\arraybackslash}p{5.0ex}} % (IX+d)...
\newcolumntype{?}{!{\vrule width 0.6pt}} % wider vertical line
\begin{changemargin}{-3.2cm}{0cm} % let the table extend below the title to allow more width, for more comfortable reading
\begin{tabular}{@{}|c?A|A|A|A|A|A|A?A|A?c|c|c|c?B|B|B|B|B|B?D|D|D?E|E?A|B|D|}
\arrayrulecolor{gray}
\hline
& {\tt A} & {\tt B} & {\tt C} & {\tt D} & {\tt E} & {\tt H} & {\tt L} & {\tt I} & {\tt R}
& {\tt IXH} & {\tt IXL} & {\tt IYH} & {\tt IYL}
& {\tt BC} & {\tt DE} & {\tt HL} & {\tt SP} & {\tt IX} & {\tt IY}
& {\tt \Small{(BC)}} & {\tt \Small{(DE)}} & {\tt \Small{(HL)}}
& {\tt \Mini{(IX+d)}} & {\tt \Mini{(IY+d)}}
& {\tt n} & {\tt nn} & {\tt \Small{(nn)}} \\
\hline
{\tt A} &\OO&\OO&\OO&\OO&\OO&\OO&\OO&\OO&\OO&\OO&\OO&\OO&\OO&\ii&\ii&\ii&\ii&\ii&\ii&\OO&\OO&\OO&\OO&\OO&\OO&\ii&\OO \\ \hline
{\tt B} &\OQ&\OQ&\OQ&\OQ&\OQ&\OQ&\OQ&\ik&\ik&\OQ&\OQ&\OQ&\OQ&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\OQ&\OQ&\OQ&\OQ&\ik&\ik \\ \hline
{\tt C} &\OO&\OO&\OO&\OO&\OO&\OO&\OO&\ii&\ii&\OO&\OO&\OO&\OO&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\OO&\OO&\OO&\OO&\ii&\ii \\ \hline
{\tt D} &\OQ&\OQ&\OQ&\OQ&\OQ&\OQ&\OQ&\ik&\ik&\OQ&\OQ&\OQ&\OQ&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\OQ&\OQ&\OQ&\OQ&\ik&\ik \\ \hline
{\tt E} &\OO&\OO&\OO&\OO&\OO&\OO&\OO&\ii&\ii&\OO&\OO&\OO&\OO&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\OO&\OO&\OO&\OO&\ii&\ii \\ \hline
{\tt H} &\OQ&\OQ&\OQ&\OQ&\OQ&\OQ&\OQ&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\OQ&\OQ&\OQ&\OQ&\ik&\ik \\ \hline
{\tt L} &\OO&\OO&\OO&\OO&\OO&\OO&\OO&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\OO&\OO&\OO&\OO&\ii&\ii \\ \hline
{\tt I} &\OQ&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik \\ \hline
{\tt R} &\OO&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii \\ \hline
{\tt IXH} &\OQ&\OQ&\OQ&\OQ&\OQ&\ik&\ik&\ik&\ik&\OQ&\OQ&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\OQ&\ik&\ik \\ \hline
{\tt IXL} &\OO&\OO&\OO&\OO&\OO&\ii&\ii&\ii&\ii&\OO&\OO&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\OO&\ii&\ii \\ \hline
{\tt IYH} &\OQ&\OQ&\OQ&\OQ&\OQ&\ik&\ik&\ik&\ik&\ik&\ik&\OQ&\OQ&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\OQ&\ik&\ik \\ \hline
{\tt IYL} &\OO&\OO&\OO&\OO&\OO&\ii&\ii&\ii&\ii&\ii&\ii&\OO&\OO&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\OO&\ii&\ii \\ \hline
{\tt BC} &\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\OQ&\OQ \\ \hline
{\tt DE} &\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\OO&\OO \\ \hline
{\tt HL} &\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\OQ&\OQ \\ \hline
{\tt SP} &\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\OO&\ii&\OO&\OO&\ii&\ii&\ii&\ii&\ii&\ii&\OO&\OO \\ \hline
{\tt IX} &\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\OQ&\OQ \\ \hline
{\tt IY} &\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\OO&\OO \\ \hline
{\tt (BC)} &\OQ&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik \\ \hline
{\tt (DE)} &\OO&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii \\ \hline
{\tt (HL)} &\OQ&\OQ&\OQ&\OQ&\OQ&\OQ&\OQ&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\OQ&\ik&\ik \\ \hline
{\tt \Mini{(IX+d)}} &\OO&\OO&\OO&\OO&\OO&\OO&\OO&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\OO&\ii&\ii \\ \hline
{\tt \Mini{(IY+d)}} &\OQ&\OQ&\OQ&\OQ&\OQ&\OQ&\OQ&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\ik&\OQ&\ik&\ik \\ \hline
{\tt (nn)} &\OO&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\OO&\OO&\OO&\OO&\OO&\OO&\ii&\ii&\ii&\ii&\ii&\ii&\ii&\ii \\ \hline
\end{tabular}
\end{changemargin}
}
% while moving effects and timing tables to next page presents a gap below variants, it's nonetheless more readable to keep it all together
\pagebreak
\begin{DetailEffects}
\FlagsLDair[{\tt LD A,I} and {\tt LD A,R}]
\FlagsLDr[Other variants]
\end{DetailEffects}
\begin{DetailTiming}[Timing 8-bit]
\DetailTime[r,r]{1}{4}
\DetailTime[r,n]{2}{7}
\DetailTime[(rr),A]{2}{7}
\DetailTime[A,(rr)]{2}{7}
\DetailTime[r,(HL)]{2}{7}
\DetailTime[(HL),r]{2}{7}
\DetailTime[A,I]{2}{9}
\DetailTime[A,R]{2}{9}
\DetailTime[I,A]{2}{9}
\DetailTime[R,A]{2}{9}
\DetailTime[(HL),n]{3}{10}
\DetailTime[A,(nn)]{4}{13}
\DetailTime[(nn),A]{4}{13}
\DetailTime[r,(IX+d)]{5}{19}
\DetailTime[r,(IY+d)]{5}{19}
\DetailTime[(IX+d),r]{5}{19}
\DetailTime[(IX+d),n]{5}{19}
\DetailTime[(IY+d),r]{5}{19}
\DetailTime[(IY+d),n]{5}{19}
\end{DetailTiming}
\begin{DetailTiming}[Timing 16-bit]
\DetailTime[SP,HL]{1}{6}
\DetailTime[SP,IX]{2}{10}
\DetailTime[SP,IY]{2}{10}
\DetailTime[rr,nn]{3}{10}
\DetailTime[IX,nn]{4}{14}
\DetailTime[IY,nn]{4}{14}
\DetailTime[(HL),nn]{5}{16}
\DetailTime[(nn),HL]{5}{16}
\DetailTime[(IX),nn]{6}{20}
\DetailTime[(IY),nn]{6}{20}
\DetailTime[rr,(nn)]{6}{20}
\DetailTime[(nn),rr]{6}{20}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
% note: LDx instructions are not listed alphabetically, instead all "single" operation instructions are listed together on one page spread, while their "repeat" variants on the following page spread. I thought this would result in nicer direct comparison of the variants. Plus it fits better on the pages without excess empty space
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{LDD}{}
{\IH{L}oa\IH{D} and \IH{D}ecrement}
{\SymLDD}
Loads contents of memory location addressed by {\tt HL} to memory location addressed by {\tt DE}. Then decrements {\tt DE}, {\tt HL} and {\tt BC} register pairs.
\begin{DetailEffects}
\FlagsLDD
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagPV{{\tt BC$\neq$0} after execution}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{4}{16}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{LDDX}{\DetailItemZXN}
{\IH{L}oa\IH{D} and \IH{D}ecrement e\IH{X}tended}
{\SymLDDX}
Works similar to {\tt LDD} except:
\begin{DetailCompactList}
\item Byte is only copied if it's different from the accumulator {\tt A}
\item {\tt DE} is incremented instead of decremented
\item Doesn't change flags
\end{DetailCompactList}
\begin{DetailEffects}
\FlagsLDDX
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{4}{16}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{LDI}{}
{\IH{L}oa\IH{D} and \IH{I}ncrement}
{\SymLDI}
Same as {\tt LDD}, except it increments {\tt DE} and {\tt HL}.
\begin{DetailEffects}
\FlagsLDI
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagPV{{\tt BC$\neq$0} after execution}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{4}{16}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{LDIX}{\DetailItemZXN}
{\IH{L}oa\IH{D} and \IH{I}ncrement e\IH{X}tended}
{\SymLDIX}
Works similar to {\tt LDI} except:
\begin{DetailCompactList}
\item Byte is only copied if it's different from the accumulator {\tt A}
\item Doesn't change flags
\end{DetailCompactList}
\begin{DetailEffects}
\FlagsLDIX
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{4}{16}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
% this item is not in alphabetical order, should be after LDPIRX, but we have empty space here and following set of instructions belong together so want to keep them on the same page
\begin{DetailItem}{LDWS}{\DetailItemZXN}
{\IH{L}oa\IH{D} \IH{W}asp \IH{S}pecial}
{\SymLDWS}
Copies the byte pointed to by {\tt HL} to the address pointed to by {\tt DE}. Then increments {\tt L} and {\tt D}. Used for vertically copying bytes to Layer 2 display. Flags are identical to what the {\tt INC D} instrution would produce.
\begin{DetailEffects}[v]
\FlagsLDWS
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign[D]}
\DetailFlagZF{\DetailFlagResultZero}
\DetailFlagHF{\DetailFlagResultHalfCarry}
\DetailFlagPV{{\tt D} was {\tt \$7F} before incrementing}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{4}{14}
\end{DetailTiming}
\DetailNote{Note: the source data are read from a single 256B (aligned) block of memory, because only {\tt L} is incremented, not the whole {\tt HL} pair.}
\end{DetailItem}
\pagebreak
% note: LDxR instructions are not listed alphabetically, instead all "single" operation instructions are listed together on one page spread, while their "repeat" variants on the following page spread. I thought this would result in nicer direct comparison of the variants. Plus it fits better on the pages without excess empty space
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{LDDR}{}
{\IH{L}oa\IH{D} and \IH{D}ecrement \IH{R}epeated}
{\SymLDDR}
Repeats {\tt LDD} until {\tt BC=0}. {\tt LDDR} can be used for block transfer. See {\tt LDIR} on page \DetailItemPageRef{LDIR} for an example and comparison of both instructions.
\begin{DetailEffects}
\FlagsLDDR
\end{DetailEffects}
\begin{DetailTiming}
\DetailTimeRegular[{\tt BC}=0]{4}{16}
\DetailTimeRegular[{\tt BC}$\neq$0]{5}{21}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{LDDRX}{\DetailItemZXN}
{\IH{L}oa\IH{D} and \IH{D}ecrement \IH{R}epeated e\IH{X}tended}
{\SymLDDRX}
Works similar to {\tt LDDR} except the differences noted at {\tt LDDX} above.
\begin{DetailEffects}
\FlagsLDDRX
\end{DetailEffects}
\begin{DetailTiming}
\DetailTimeRegular[{\tt BC}=0]{4}{16}
\DetailTimeRegular[{\tt BC}$\neq$0]{5}{21}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{LDIR}{}
{\IH{L}oa\IH{D} and \IH{I}ncrement \IH{R}epeated}
{\SymLDIR}
Repeats {\tt LDI} until {\tt BC=0}. Example of copying 100 bytes from {\tt source} to {\tt destination} with {\tt LDIR} and {\tt LDDR}:
\begin{multicols}{2}
{\tt LDIR} = copy forward
\begin{tcblisting}{right skip=1em}
LD HL, source
LD DE, destination
LD BC, 100
LDIR
\end{tcblisting}
\columnbreak
{\tt LDDR} = copy backwards
\begin{tcblisting}{}
LD HL, source+99
LD DE, destination+99
LD BC, 100
LDDR
\end{tcblisting}
\end{multicols}
\begin{DetailEffects}
\FlagsLDIR
\end{DetailEffects}
\begin{DetailTiming}
\DetailTimeRegular[{\tt BC}=0]{4}{16}
\DetailTimeRegular[{\tt BC}$\neq$0]{5}{21}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{LDIRX}{\DetailItemZXN}
{\IH{L}oa\IH{D} and \IH{I}ncrement \IH{R}epeated e\IH{X}tended}
{\SymLDIRX}
Works similar to {\tt LDIR} except the differences noted at {\tt LDIX} on previous page.
\begin{DetailEffects}
\FlagsLDIRX
\end{DetailEffects}
\begin{DetailTiming}
\DetailTimeRegular[{\tt BC}=0]{4}{16}
\DetailTimeRegular[{\tt BC}$\neq$0]{5}{21}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{LDPIRX}{\DetailItemZXN}
{\IH{L}oa\IH{D} \IH{P}attern fill and \IH{I}ncrement \IH{R}epeated e\IH{X}tended}
{\SymLDPIRX}
Similar to {\tt LDIRX} except the source byte address is not just {\tt HL}, but is obtained by using the top 13 bits of {\tt HL} and lower 3 bits of {\tt DE}. Furthermore {\tt HL} is not incremented during the loop; it serves as the base address of the aligned 8-byte lookup table. {\tt DE} works as destination and also wrapping index 0..7 into the table. This instruction is intended for ``pattern fill'' functionality.
\begin{DetailEffects}
\FlagsLDPIRX
\end{DetailEffects}
\begin{DetailTiming}
\DetailTimeRegular[{\tt BC}=0]{4}{16}
\DetailTimeRegular[{\tt BC}$\neq$0]{5}{21}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{MUL}{D,E\ZXN}
{\IH{MUL}tiply}
{\SymMUL}
Multiplies {\tt D} by {\tt E}, storing 16-bit result into {\tt DE}.
\begin{DetailEffects}
\FlagsMULde
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{2}{8}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{NEG}{}
{\IH{NEG}ate}
{\SymNEG}
Negates contents of the accumulator {\tt A} and stores result back to {\tt A}. You can also think of the operation as subtracting the value of {\tt A} from {\tt 0} ({\tt A$\leftarrow$0-A}). This way it might be easier to understand effects on flags.
\begin{DetailEffects}[p]
\FlagsNEG
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign}
\DetailFlagZF{\DetailFlagResultZero}
\DetailFlagHF{\DetailFlagResultHalfBorrow}
\DetailFlagPV{{\tt A} was {\tt \$80} before operation}
\DetailFlagCF{{\tt A} was not {\tt \$00} before operation}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{2}{8}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{NEXTREG}{n,s\ZXN}
{set \IH{NEXT} \IH{REG}ister value}
{\SymNEXTREG{s}}
\begin{DetailVariants}
NEXTREG n,A\\
NEXTREG n,n'
\end{DetailVariants}
% note: we only show page number on second port xref since both are declared on the same page, but if this changes in the future, we should update this text accordingly
Directly sets the Next Feature Control Registers without going through ports \PortTextXRef[]{243B} and \PortTextXRef[]{253B} (page \PortPage{243B}). See section \XRef{zx_next_tbblue_registers} for registers list.
\begin{DetailEffects}
\FlagsNEXTREGna
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime[r,A]{4}{17}
\DetailTime[r,n]{5}{20}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{NOP}{}
{\IH{N}o \IH{OP}eration}
{}
Does nothing for 4 cycles.
\begin{DetailEffects}
\FlagsNOP
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{1}{4}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{OR}{s}
{bitwise \IH{OR}}
{\SymOR{s}}
\begin{DetailVariants}[4]
OR A\\
OR B\\
OR C\\
OR D
\columnbreak
OR E\\
OR H\\
OR L\\
OR n
\columnbreak
OR (HL)\\
OR (IX+d)\\
OR (IY+d)
\columnbreak
OR IXH\UNDOC\\
OR IXL\UNDOC\\
OR IYH\UNDOC\\
OR IYL\UNDOC
\end{DetailVariants}
\begin{tabularx}{\linewidth}{@{}Xl}
Performs bitwise or between the accumulator {\tt A} and operand {\tt s} or contents of memory addressed by {\tt s}. Then stores the result back to {\tt A}. Individual bits are OR'ed as shown on the right:
&
\begin{tabular}[t]{cc|c}
{\tt A} & {\tt s} & Result \\
\hline
{\tt 0} & {\tt 0} & {\tt 0} \\
{\tt 0} & {\tt 1} & {\tt 1} \\
{\tt 1} & {\tt 0} & {\tt 1} \\
{\tt 1} & {\tt 1} & {\tt 1} \\
\end{tabular}
\\
\end{tabularx}
\begin{DetailEffects}[p]
\FlagsORr
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign}
\DetailFlagZF{\DetailFlagResultZero}
\DetailFlagPV{\DetailFlagResultParity}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[r]{1}{4}
\DetailTime[n]{2}{7}
\DetailTime[(HL)]{2}{7}
\DetailTime[(IX+d)]{5}{19}
\DetailTime[(IY+d)]{5}{19}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
% █▄─▄█▄─▀█▄─▄█─▄▄▄▄█─▄─▄─█▄─▄▄▀█▄─██─▄█─▄▄▄─█─▄─▄─█▄─▄█─▄▄─█▄─▀█▄─▄█
% ██─███─█▄▀─██▄▄▄▄─███─████─▄─▄██─██─██─███▀███─████─██─██─██─█▄▀─██
% ▀▄▄▄▀▄▄▄▀▀▄▄▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▀▄▄▀▀▄▄▄▄▀▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▄▀▄▄▄▄▀▄▄▄▀▀▄▄▀
%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{OTDR}{}
{\IH{O}u\IH{T}put and \IH{D}ec\IH{R}ement}
{\SymOTDR}
Repeats {\tt OUTD} (see page \DetailItemPageRef{OUTD}) until {\tt B=0}. Similar to {\tt OTIR} except {\tt HL} is decremented instead of incremented.
\begin{DetailEffects}
\FlagsOTDR
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\DetailFlagHF[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\DetailFlagPV[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTimeRegular[{\tt B}=0]{4}{16}
\DetailTimeRegular[{\tt B}$\neq$0]{5}{21}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
% █▄─▄█▄─▀█▄─▄█─▄▄▄▄█─▄─▄─█▄─▄▄▀█▄─██─▄█─▄▄▄─█─▄─▄─█▄─▄█─▄▄─█▄─▀█▄─▄█
% ██─███─█▄▀─██▄▄▄▄─███─████─▄─▄██─██─██─███▀███─████─██─██─██─█▄▀─██
% ▀▄▄▄▀▄▄▄▀▀▄▄▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▀▄▄▀▀▄▄▄▄▀▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▄▀▄▄▄▄▀▄▄▄▀▀▄▄▀
%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{OTIR}{}
{\IH{O}u\IH{T}put and \IH{I}nc\IH{R}ement}
{\SymOTIR}
Repeats {\tt OUTI} (see page \DetailItemPageRef{OUTI}) until {\tt B=0}. Similar to {\tt OTDR} except {\tt HL} is incremented instead of decremented.
\begin{DetailEffects}
\FlagsOTIR
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\DetailFlagHF[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\DetailFlagPV[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTimeRegular[{\tt B}=0]{4}{16}
\DetailTimeRegular[{\tt B}$\neq$0]{5}{21}
\end{DetailTiming}
\end{DetailItem}
% we want to keep OUTI and OUTD on the same page spread as their block repeat variants above
\DetailItemSeePageReference{OUT}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
% █▄─▄█▄─▀█▄─▄█─▄▄▄▄█─▄─▄─█▄─▄▄▀█▄─██─▄█─▄▄▄─█─▄─▄─█▄─▄█─▄▄─█▄─▀█▄─▄█
% ██─███─█▄▀─██▄▄▄▄─███─████─▄─▄██─██─██─███▀███─████─██─██─██─█▄▀─██
% ▀▄▄▄▀▄▄▄▀▀▄▄▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▀▄▄▀▀▄▄▄▄▀▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▄▀▄▄▄▄▀▄▄▄▀▀▄▄▀
%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{OUTD}{}
{\IH{OUT}put and \IH{D}ecrement}
{\SymOUTD}
Outputs the value from contents of memory addressed by {\tt HL} to port on address {\tt BC}. Then decrements both, {\tt HL} and {\tt B}.
\begin{DetailEffects}
\FlagsOUTD
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\DetailFlagZF{{\tt B=0} after decrement}
\DetailFlagHF[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\DetailFlagPV[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{4}{16}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
% █▄─▄█▄─▀█▄─▄█─▄▄▄▄█─▄─▄─█▄─▄▄▀█▄─██─▄█─▄▄▄─█─▄─▄─█▄─▄█─▄▄─█▄─▀█▄─▄█
% ██─███─█▄▀─██▄▄▄▄─███─████─▄─▄██─██─██─███▀███─████─██─██─██─█▄▀─██
% ▀▄▄▄▀▄▄▄▀▀▄▄▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▀▄▄▀▀▄▄▄▄▀▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▄▀▄▄▄▄▀▄▄▄▀▀▄▄▀
%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{OUTI}{}
{\IH{OUT}put and \IH{I}ncrement}
{\SymOUTI}
Similar to {\tt OUTD} except {\tt HL} is incremented.
\begin{DetailEffects}
\FlagsOUTI
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\DetailFlagZF{{\tt B=0} after decrement}
\DetailFlagHF[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\DetailFlagPV[]{destroyed on Next, Z80 see \XRef{z80_undocumented_instructions_io_block}}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{4}{16}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
% █▄─▄█▄─▀█▄─▄█─▄▄▄▄█─▄─▄─█▄─▄▄▀█▄─██─▄█─▄▄▄─█─▄─▄─█▄─▄█─▄▄─█▄─▀█▄─▄█
% ██─███─█▄▀─██▄▄▄▄─███─████─▄─▄██─██─██─███▀███─████─██─██─██─█▄▀─██
% ▀▄▄▄▀▄▄▄▀▀▄▄▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▀▄▄▀▀▄▄▄▄▀▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▄▀▄▄▄▄▀▄▄▄▀▀▄▄▀
%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{OUT}{(d),s}
{\IH{OUT}put to port}
{\SymOUT{d}{s}}
\begin{DetailVariants}
OUT (n),A
\columnbreak
OUT (C),A\\
OUT (C),B\\
OUT (C),C\\
OUT (C),D
\columnbreak
OUT (C),E\\
OUT (C),H\\
OUT (C),L\\
OUT (C),0\UNDOC
\end{DetailVariants}
Writes the value of operand {\tt s} to the port at address {\tt d}. Port addresses are always 16-bit values defined like this:
\begin{tabular}{ccc}
& \multicolumn{2}{c}{Address Bits} \\
Variant & {\tt 15-8} & {\tt 7-0} \\
\hline
{\tt OUT (n),A} & {\tt A} & {\tt n} \\
{\tt OUT (C),r} & {\tt B} & {\tt C} \\
\end{tabular}
\vspace{1ex} % some spacing before next text for less cluttered layout
\begin{DetailEffects}
\FlagsOUTcr
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime[(n),A]{3}{11}
\DetailTime[(C),r]{3}{12}
\end{DetailTiming}
\DetailNote{Note: on the Next FPGA {\tt OUT (C),0} variant outputs {\tt 0} to the port at address {\tt BC}, but some Z80 chips may output different value like {\tt \$FF}, so it is not recommended to use {\tt OUT (C),0} if you want to reuse your code on original ZX Spectrum also.}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
% █▄─▄█▄─▀█▄─▄█─▄▄▄▄█─▄─▄─█▄─▄▄▀█▄─██─▄█─▄▄▄─█─▄─▄─█▄─▄█─▄▄─█▄─▀█▄─▄█
% ██─███─█▄▀─██▄▄▄▄─███─████─▄─▄██─██─██─███▀███─████─██─██─██─█▄▀─██
% ▀▄▄▄▀▄▄▄▀▀▄▄▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▀▄▄▀▀▄▄▄▄▀▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▄▀▄▄▄▄▀▄▄▄▀▀▄▄▀
%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{OUTINB}{\DetailItemZXN}
{\IH{OUT}put and \IH{I}ncrement with \IH{N}o \IH{B}}
{\SymOUTINB}
Similar to {\tt OUTI} except it doesn't decrement {\tt B}.
\begin{DetailEffects}
\FlagsOUTINB
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{4}{16}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
% █▄─▄█▄─▀█▄─▄█─▄▄▄▄█─▄─▄─█▄─▄▄▀█▄─██─▄█─▄▄▄─█─▄─▄─█▄─▄█─▄▄─█▄─▀█▄─▄█
% ██─███─█▄▀─██▄▄▄▄─███─████─▄─▄██─██─██─███▀███─████─██─██─██─█▄▀─██
% ▀▄▄▄▀▄▄▄▀▀▄▄▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▀▄▄▀▀▄▄▄▄▀▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▄▀▄▄▄▄▀▄▄▄▀▀▄▄▀
%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{PIXELAD}{\DetailItemZXN}
{\IH{PIXEL} \IH{AD}dress}
{\SymPIXELAD}
Takes {\tt E} and {\tt D} as the (x,y) coordinates of a point and calculates the address of the byte containing this pixel in the pixel area of standard ULA screen 0. Result is stored in {\tt HL}.
\begin{DetailEffects}
\FlagsPIXELAD
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{2}{8}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
% █▄─▄█▄─▀█▄─▄█─▄▄▄▄█─▄─▄─█▄─▄▄▀█▄─██─▄█─▄▄▄─█─▄─▄─█▄─▄█─▄▄─█▄─▀█▄─▄█
% ██─███─█▄▀─██▄▄▄▄─███─████─▄─▄██─██─██─███▀███─████─██─██─██─█▄▀─██
% ▀▄▄▄▀▄▄▄▀▀▄▄▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▀▄▄▀▀▄▄▄▄▀▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▄▀▄▄▄▄▀▄▄▄▀▀▄▄▀
%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{PIXELDN}{\DetailItemZXN}
{\IH{PIXEL} \IH{D}ow\IH{N}}
{\SymPIXELDN}
Updates the address in {\tt HL} (likely from prior {\tt PIXELAD} or {\tt PIXELDN}) to move down by one line of pixels of standard ULA screen 0.
\begin{DetailEffects}
\FlagsPIXELDN
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{2}{8}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
% █▄─▄█▄─▀█▄─▄█─▄▄▄▄█─▄─▄─█▄─▄▄▀█▄─██─▄█─▄▄▄─█─▄─▄─█▄─▄█─▄▄─█▄─▀█▄─▄█
% ██─███─█▄▀─██▄▄▄▄─███─████─▄─▄██─██─██─███▀███─████─██─██─██─█▄▀─██
% ▀▄▄▄▀▄▄▄▀▀▄▄▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▀▄▄▀▀▄▄▄▄▀▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▄▀▄▄▄▄▀▄▄▄▀▀▄▄▀
%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{POP}{rr}
{\IH{POP} from stack}
{\SymPOP{rr}}
\begin{DetailVariants}
POP AF\\
POP BC\\
POP DE\\
POP HL
\columnbreak
POP IX\\
POP IY
\columnbreak
~
\end{DetailVariants}
Copies 2 bytes from stack pointer {\tt SP} into contents of the given register pair {\tt ss} and increments {\tt SP} by {\tt 2}.
\begin{DetailEffects}
\FlagsPOPaf[{\tt POP AF}]
\FlagsPOPrr[Other variants no effect]
\DetailFlagsComments{
\item {\tt POP AF} flags set directly to low 8-bits of the value from {\tt SP}
}
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime[rr]{3}{10}
\DetailTime[IX]{4}{14}
\DetailTime[IY]{4}{14}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
% █▄─▄█▄─▀█▄─▄█─▄▄▄▄█─▄─▄─█▄─▄▄▀█▄─██─▄█─▄▄▄─█─▄─▄─█▄─▄█─▄▄─█▄─▀█▄─▄█
% ██─███─█▄▀─██▄▄▄▄─███─████─▄─▄██─██─██─███▀███─████─██─██─██─█▄▀─██
% ▀▄▄▄▀▄▄▄▀▀▄▄▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▀▄▄▀▀▄▄▄▄▀▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▄▀▄▄▄▄▀▄▄▄▀▀▄▄▀
%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{PUSH}{ss}
{\IH{PUSH} on stack}
{\SymPUSH{ss}}
\begin{DetailVariants}
PUSH AF\\
PUSH BC\\
PUSH DE\\
PUSH HL
\columnbreak
PUSH IX\\
PUSH IY\\
\columnbreak
PUSH nn\ZXN
\end{DetailVariants}
Copies contents of a register pair to the top of the stack pointer {\tt SP}, then decrements {\tt SP} by {\tt 2}. Next extended {\tt PUSH nn} also allows pushing immediate 16-bit value.
\begin{DetailEffects}
\FlagsPUSHrr
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime[rr]{3}{11}
\DetailTime[IX]{4}{15}
\DetailTime[IY]{4}{15}
\DetailTime[nn]{6}{23}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
% █▄─▄█▄─▀█▄─▄█─▄▄▄▄█─▄─▄─█▄─▄▄▀█▄─██─▄█─▄▄▄─█─▄─▄─█▄─▄█─▄▄─█▄─▀█▄─▄█
% ██─███─█▄▀─██▄▄▄▄─███─████─▄─▄██─██─██─███▀███─████─██─██─██─█▄▀─██
% ▀▄▄▄▀▄▄▄▀▀▄▄▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▀▄▄▀▀▄▄▄▄▀▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▄▀▄▄▄▄▀▄▄▄▀▀▄▄▀
%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{RES}{b,s}
{\IH{RES}et bit}
{\SymRES{s}}
% we use tabularx instead of multicols because some columns need to be wider to accomodate instructions. And then tabularx instead of tabular to fit whole width
\begin{DetailVariants}
RES b,A\\
RES b,B\\
RES b,C\\
RES b,D\\
RES b,E\\
RES b,H\\
RES b,L\\
RES b,(HL)\\
RES b,(IX+d)\\
RES b,(IY+d)
\columnbreak
RES b,(IX+d),A\UNDOC\\
RES b,(IX+d),B\UNDOC\\
RES b,(IX+d),C\UNDOC\\
RES b,(IX+d),D\UNDOC\\
RES b,(IX+d),E\UNDOC\\
RES b,(IX+d),H\UNDOC\\
RES b,(IX+d),L\UNDOC
\columnbreak
RES b,(IY+d),A\UNDOC\\
RES b,(IY+d),B\UNDOC\\
RES b,(IY+d),C\UNDOC\\
RES b,(IY+d),D\UNDOC\\
RES b,(IY+d),E\UNDOC\\
RES b,(IY+d),H\UNDOC\\
RES b,(IY+d),L\UNDOC
\end{DetailVariants}
Resets bit {\tt b} ({\tt 0-7}) of the given register {\tt s} or memory location addressed by operand {\tt s}.
\begin{DetailEffects}
\FlagsRESr
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime[r]{2}{8}
\DetailTime[(HL)]{4}{15}
\DetailTime[(IX+d)]{6}{23}
\DetailTime[(IY+d)]{6}{23}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
% █▄─▄█▄─▀█▄─▄█─▄▄▄▄█─▄─▄─█▄─▄▄▀█▄─██─▄█─▄▄▄─█─▄─▄─█▄─▄█─▄▄─█▄─▀█▄─▄█
% ██─███─█▄▀─██▄▄▄▄─███─████─▄─▄██─██─██─███▀███─████─██─██─██─█▄▀─██
% ▀▄▄▄▀▄▄▄▀▀▄▄▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▀▄▄▀▀▄▄▄▄▀▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▄▀▄▄▄▄▀▄▄▄▀▀▄▄▀
%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{RET}{}
{\IH{RET}urn from subroutine}
{\SymRET}
Returns from subroutine. The contents of program counter {\tt PC} is {\tt POP}-ed from stack so next instruction will be loaded from there.
\begin{DetailEffects}
\FlagsRET
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{3}{10}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
% █▄─▄█▄─▀█▄─▄█─▄▄▄▄█─▄─▄─█▄─▄▄▀█▄─██─▄█─▄▄▄─█─▄─▄─█▄─▄█─▄▄─█▄─▀█▄─▄█
% ██─███─█▄▀─██▄▄▄▄─███─████─▄─▄██─██─██─███▀███─████─██─██─██─█▄▀─██
% ▀▄▄▄▀▄▄▄▀▀▄▄▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▀▄▄▀▀▄▄▄▄▀▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▄▀▄▄▄▄▀▄▄▄▀▀▄▄▀
%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{RET c}{}
{\IH{RET}urn from subroutine conditionally}
{\SymRETc{c}}
\vspace{1ex} % we need some vertical space to achieve same separation as multicols
\begin{tabular}{@{}llcll}
{\tt RET C,nn} & returns if \FlagCF{} is set & &
{\tt RET M,nn} & returns if \FlagSF{} is set\\
{\tt RET NC,nn} & returns if \FlagCF{} is reset & &
{\tt RET P,nn} & returns if \FlagSF{} is reset\\
{\tt RET Z,nn} & returns if \FlagZF{} is set & &
{\tt RET PE,nn} & returns if \FlagPV{} is set\\
{\tt RET NZ,nn} & returns if \FlagZF{} is reset & &
{\tt RET PO,nn} & returns if \FlagPV{} is reset\\
\end{tabular}
If given condition is met, {\tt RET} is performed, as described above.
\begin{DetailEffects}
\FlagsRETcc
\end{DetailEffects}
\begin{DetailTiming}
\DetailTimeRegular[{\tt c}=false]{1}{5}
\DetailTimeRegular[{\tt c}=true]{3}{11}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{RETI}{}
{\IH{RET}urn from \IH{I}nterrupt}
{\SymRETI}
Returns from maskable interrupt; restores stack pointer {\tt SP} and signals to I/O device that interrupt routine is completed.
Note that {\tt RETI} doesn't re-enable interrupts that were disabled when interrupt routine started - {\tt EI} should be called before {\tt RETI} to do that.
\begin{DetailEffects}
\FlagsRETI
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{4}{14}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{RETN}{}
{\IH{RET}urn from \IH{N}on-maskable interrupt}
{\SymRETN}
Returns from non-maskable interrupt; restores stack pointer {\tt SP} and copies state of {\tt IFF2} back to {\tt IFF1} so that maskable interrupts are re-enabled.
\begin{DetailEffects}
\FlagsRETN
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{4}{14}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
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% ▀▄▄▄▀▄▄▄▀▀▄▄▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▀▄▄▀▀▄▄▄▄▀▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▄▀▄▄▄▄▀▄▄▄▀▀▄▄▀
%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{RL}{s}
{\IH{R}otate \IH{L}eft}
{\SymRL{s}}
\begin{DetailVariants}
RL A\\
RL B\\
RL C\\
RL D\\
RL E\\
RL H\\
RL L\\
RL (HL)\\
RL (IX+d)\\
RL (IY+d)
\columnbreak
RL (IX+d),A\UNDOC\\
RL (IX+d),B\UNDOC\\
RL (IX+d),C\UNDOC\\
RL (IX+d),D\UNDOC\\
RL (IX+d),E\UNDOC\\
RL (IX+d),H\UNDOC\\
RL (IX+d),L\UNDOC
\columnbreak
RL (IY+d),A\UNDOC\\
RL (IY+d),B\UNDOC\\
RL (IY+d),C\UNDOC\\
RL (IY+d),D\UNDOC\\
RL (IY+d),E\UNDOC\\
RL (IY+d),H\UNDOC\\
RL (IY+d),L\UNDOC
\end{DetailVariants}
Performs 9-bit left rotation of the value of the operand {\tt s} or memory addressed by {\tt s} through the carry flag \FlagCF{} so that contents of \FlagCF{} are moved to bit {\tt 0} and bit {\tt 7} to \FlagCF{}. Result is then stored back to {\tt s}.
\begin{DetailEffects}[p]
\FlagsRLr
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign}
\DetailFlagZF{\DetailFlagResultZero}
\DetailFlagPV{\DetailFlagResultParity}
\DetailFlagCF[set to:]{bit {\tt 7} of the original value}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[r]{2}{8}
\DetailTime[(HL)]{4}{15}
\DetailTime[(IX+d)]{6}{23}
\DetailTime[(IY+d)]{6}{23}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{RLA}{}
{\IH{R}otate \IH{L}eft \IH{A}ccumulator}
{\SymRL{A}}
Performs {\tt RL A}, but twice faster and preserves \FlagSF{}, \FlagZF{} and \FlagPV{}.
\begin{DetailEffects}
\FlagsRLA
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagCF[set to:]{bit {\tt 7} of the original value}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{1}{4}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{RLC}{s}
{\IH{R}otate \IH{L}eft \IH{C}ircular}
{\SymRLC{s}}
\begin{DetailVariants}
RLC A\\
RLC B\\
RLC C\\
RLC D\\
RLC E\\
RLC H\\
RLC L\\
RLC (HL)\\
RLC (IX+d)\\
RLC (IY+d)
\columnbreak
RLC (IX+d),A\UNDOC\\
RLC (IX+d),B\UNDOC\\
RLC (IX+d),C\UNDOC\\
RLC (IX+d),D\UNDOC\\
RLC (IX+d),E\UNDOC\\
RLC (IX+d),H\UNDOC\\
RLC (IX+d),L\UNDOC
\columnbreak
RLC (IY+d),A\UNDOC\\
RLC (IY+d),B\UNDOC\\
RLC (IY+d),C\UNDOC\\
RLC (IY+d),D\UNDOC\\
RLC (IY+d),E\UNDOC\\
RLC (IY+d),H\UNDOC\\
RLC (IY+d),L\UNDOC
\end{DetailVariants}
Performs 8-bit rotation to the left. Bit {\tt 7} is moved to carry flag \FlagCF{} as well as to bit {\tt 0}. Result is then stored back to {\tt s}.
Note: undocumented variants work slightly differently:
\begin{multicols}{2}
\DetailSymbolVariants{RLC r,(IX+d)}{\SymRLCu{r}{IX}}
\DetailSymbolVariants{RLC r,(IY+d)}{\SymRLCu{r}{IY}}
\end{multicols}
\begin{DetailEffects}[p]
\FlagsRLCr
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign}
\DetailFlagZF{\DetailFlagResultZero}
\DetailFlagPV{\DetailFlagResultParity}
\DetailFlagCF[set to:]{bit {\tt 7} of the original value}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[r]{2}{8}
\DetailTime[(HL)]{4}{15}
\DetailTime[(IX+d)]{6}{23}
\DetailTime[(IY+d)]{6}{23}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{RLCA}{}
{\IH{R}otate \IH{L}eft \IH{C}ircular \IH{A}ccumulator}
{\SymRLC{A}}
Performs {\tt RLC A}, but twice faster and preserves \FlagSF{}, \FlagZF{} and \FlagPV{}.
\begin{DetailEffects}
\FlagsRLCA
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagCF[set to:]{bit {\tt 7} of the original value}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{1}{4}
\end{DetailTiming}
\end{DetailItem}
% RLD and RRD are similar instructions, so while RLD would alphabetically fit here, moving it on the same page spread with RRD allows direct comparison between the two
\DetailItemSeePageReference{RLD}
% % these instructions were moved before backwards so they can be all together on the same page spread for better direct comparison
% \DetailItemsSeePageReference{RR, RRA, RRC, RRCA}{See pages \DetailItemPageRef{RR} and \DetailItemPageRef{RRCA}}
% \pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{RR}{s}
{\IH{R}otate \IH{R}ight}
{\SymRR{s}}
\begin{DetailVariants}
RR A\\
RR B\\
RR C\\
RR D\\
RR E\\
RR H\\
RR L\\
RR (HL)\\
RR (IX+d)\\
RR (IY+d)
\columnbreak
RR (IX+d),A\UNDOC\\
RR (IX+d),B\UNDOC\\
RR (IX+d),C\UNDOC\\
RR (IX+d),D\UNDOC\\
RR (IX+d),E\UNDOC\\
RR (IX+d),H\UNDOC\\
RR (IX+d),L\UNDOC
\columnbreak
RR (IY+d),A\UNDOC\\
RR (IY+d),B\UNDOC\\
RR (IY+d),C\UNDOC\\
RR (IY+d),D\UNDOC\\
RR (IY+d),E\UNDOC\\
RR (IY+d),H\UNDOC\\
RR (IY+d),L\UNDOC
\end{DetailVariants}
Performs 9-bit right rotation of the contents of the operand {\tt s} or memory addressed by {\tt s} through carry flag \FlagCF{} so that contents of \FlagCF{} are moved to bit {\tt 7} and bit {\tt 0} to \FlagCF{}. Result is then stored back to {\tt s}.
\begin{DetailEffects}[p]
\FlagsRRr
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign}
\DetailFlagZF{\DetailFlagResultZero}
\DetailFlagPV{\DetailFlagResultParity}
\DetailFlagCF[set to:]{bit {\tt 0} of the original value}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[r]{2}{8}
\DetailTime[(HL)]{4}{15}
\DetailTime[(IX+d)]{6}{23}
\DetailTime[(IY+d)]{6}{23}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{RRA}{}
{\IH{R}otate \IH{R}ight \IH{A}ccumulator}
{\SymRR{A}}
Performs {\tt RR A}, but twice faster and preserves \FlagSF{}, \FlagZF{} and \FlagPV{}.
\begin{DetailEffects}
\FlagsRRA
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagCF[set to:]{bit {\tt 0} of the original value}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{1}{4}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{RRC}{s}
{\IH{R}otate \IH{R}ight \IH{C}ircular}
{\SymRRC{s}}
\begin{DetailVariants}
RRC A\\
RRC B\\
RRC C\\
RRC D\\
RRC E\\
RRC H\\
RRC L\\
RRC (HL)\\
RRC (IX+d)\\
RRC (IY+d)
\columnbreak
RRC (IX+d),A\UNDOC\\
RRC (IX+d),B\UNDOC\\
RRC (IX+d),C\UNDOC\\
RRC (IX+d),D\UNDOC\\
RRC (IX+d),E\UNDOC\\
RRC (IX+d),H\UNDOC\\
RRC (IX+d),L\UNDOC
\columnbreak
RRC (IY+d),A\UNDOC\\
RRC (IY+d),B\UNDOC\\
RRC (IY+d),C\UNDOC\\
RRC (IY+d),D\UNDOC\\
RRC (IY+d),E\UNDOC\\
RRC (IY+d),H\UNDOC\\
RRC (IY+d),L\UNDOC
\end{DetailVariants}
Performs 8-bit rotation of the source {\tt s} to the right. Bit {\tt 0} is moved to \FlagCF{} as well as to bit {\tt 7}. Result is then stored back to {\tt s}.
\begin{DetailEffects}[p]
\FlagsRRCr
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign}
\DetailFlagZF{\DetailFlagResultZero}
\DetailFlagPV{\DetailFlagResultParity}
\DetailFlagCF[set to:]{bit {\tt 0} of the original value}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[r]{2}{8}
\DetailTime[(HL)]{4}{15}
\DetailTime[(IX+d)]{6}{23}
\DetailTime[(IY+d)]{6}{23}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
% while RRCA should alphabetically be before RLD, I opted for this changed order so that both RLD and RRD are rendered at the top of their pages - easier to compare both this way
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
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% ██─███─█▄▀─██▄▄▄▄─███─████─▄─▄██─██─██─███▀███─████─██─██─██─█▄▀─██
% ▀▄▄▄▀▄▄▄▀▀▄▄▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▀▄▄▀▀▄▄▄▄▀▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▄▀▄▄▄▄▀▄▄▄▀▀▄▄▀
%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{RLD}{}
{\IH{R}otate \IH{L}eft bcd \IH{D}igit}
{\SymRLD}
Performs leftward 12-bit rotation of 4-bit nibbles where 2 least significant nibbles are stored in memory location addressed by {\tt HL} and most significant digit as lower 4 bits of the accumulator {\tt A}.
If used with BCD numbers: as the shift happens by 1 digit to the left, this effectively results in multiplication with {\tt 10}. {\tt A} acts as a sort of decimal carry in the operation. Example of multiplying multi-digit BCD number by 10:
\begin{tabular}{m{8cm}p{0.1cm}m{4.3cm}}
{ % tcblisting must be enclosed within {} inside tabular otherwise latex compiler gets confused
\begin{tcblisting}{}
MultiplyBy10: ; number=0123
LD HL, number+digits-1
LD B, digits ; number of repeats
XOR A ; reset "carry"
lp: RLD ; multiply by 10
DEC HL ; prev 2 digits
DJNZ lp ; number=1230, A=0
number:
DB &01, &23
digits = &-number ;(2)
\end{tcblisting}
}
& &
\newcommand{\HLindicator}[2]{
\path (progress-#1-2.south west) --
node[xshift=#2, yshift=1.4ex, rotate=90]{$\lbrace$}
node[xshift=#2 + 0.1ex, yshift=0.2ex, indicator]{(HL)} (progress-#1-2.south)
}
\newcommand{\ByteIndicator}[1]{
\draw
(progress-#1-2.south west) ++(8pt,13pt)
|- ++(5pt,-3pt) -| ++(5pt,3pt)
++(1pt,0)
|- ++(5pt,-3pt) -| ++(5pt,3pt);
}
\begin{tikzpicture}[
value/.style={font=\ttfamily},
leading/.style={value, inner xsep=8pt, xshift=2pt},
indicator/.style={inner sep=0, font=\ttfamily\scriptsize},
line/.style={inner sep=6pt, font=\ttfamily\tiny}]
\node (title) {Progression};
\matrix (progress) [
below=0em of title,
matrix of nodes,
column 1/.style={line},
column 2/.style={value},
column 3/.style={value},
column 4/.style={leading}] {
line & number & A & B \\
\hline
2-4 & 0123 & 0 & 2 \\[-1.3ex]
$\downarrow$ & ~~~~~ & & \\[0.8em]
5-7 & 0130 & 2 & 1 \\[-1.3ex]
$\circlearrowright$ & ~~~~~ & & \\[0.8em]
5-7 & 1230 & 0 & 0 \\[-1.3ex]
$\circlearrowright$ & ~~~~~ & & \\
};
\ByteIndicator{3};
\ByteIndicator{5};
\ByteIndicator{7};
\HLindicator{3}{3.15ex};
\HLindicator{5}{0.8ex};
\HLindicator{7}{-1.45ex};
\end{tikzpicture}
\end{tabular}
\begin{DetailEffects}[p]
\FlagsRLD
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{5}{18}
\end{DetailTiming}
\DetailNote{Note: instruction doesn't assume any format of the data; it simply rotates nibbles. So while it's most frequently associated with BCD numbers, it can be used for shifting hexadecimal values or any other content.}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{RRCA}{}
{\IH{R}otate \IH{R}ight \IH{C}ircular \IH{A}ccumulator}
{\SymRRC{A}}
Performs {\tt RRC A}, but twice faster and preserves \FlagSF{}, \FlagZF{} and \FlagPV{}.
\begin{DetailEffects}
\FlagsRRCA
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagCF[set to:]{bit {\tt 0} of the original value}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{1}{4}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{RRD}{}
{\IH{R}otate \IH{R}ight bcd \IH{D}igit}
{\SymRRD}
Similar to {\tt RLD} except rotation is to the right. If used with BCD values, this operation effectively divides 3-digit BCD number by {\tt 10} and stores remainder in {\tt A}. Taking the example from {\tt RLD}, we can easily convert it to division by 10 simply by using {\tt RRD}. Note however we also need to change the order - we start from MSB now (which is exactly how division would be performed by hand):
\begin{tabular}{m{8cm}p{0.1cm}m{4.3cm}}
{ % tcblisting must be enclosed within {} inside tabular otherwise latex compiler gets confused
\begin{tcblisting}{}
DivideBy10:
LD HL, number ; number=0123
LD B, digits ; number of repeats
XOR A ; reset "carry"
lp: RRD ; divide by 10
INC HL ; next 2 digits
DJNZ lp ; number=0012, A=3
number:
DB &01, &23
digits = &-number ;(2)
\end{tcblisting}
}
& &
\newcommand{\HLindicator}[2]{
\path (progress-#1-2.south west) --
node[xshift=#2, yshift=1.4ex, rotate=90]{$\lbrace$}
node[xshift=#2 + 0.1ex, yshift=0.2ex, indicator]{(HL)} (progress-#1-2.south)
}
\newcommand{\ByteIndicator}[1]{
\draw
(progress-#1-2.south west) ++(8pt,13pt)
|- ++(5pt,-3pt) -| ++(5pt,3pt)
++(1pt,0)
|- ++(5pt,-3pt) -| ++(5pt,3pt);
}
\begin{tikzpicture}[
value/.style={font=\ttfamily},
leading/.style={value, inner xsep=8pt, xshift=2pt},
indicator/.style={inner sep=0, font=\ttfamily\scriptsize},
line/.style={inner sep=6pt, font=\ttfamily\tiny}]
\node (title) {Progression};
\matrix (progress) [
below=0em of title,
matrix of nodes,
column 1/.style={line},
column 2/.style={value},
column 3/.style={value},
column 4/.style={leading}] {
line & number & A & B \\
\hline
2-4 & 0123 & 0 & 2 \\[-1.3ex]
$\downarrow$ & ~~~~~ & & \\[1em]
5-7 & 0023 & 1 & 1 \\[-1.3ex]
$\circlearrowright$ & ~~~~~ & & \\[1em]
5-7 & 0012 & 3 & 0 \\[-1.3ex]
$\circlearrowright$ & ~~~~~ & \\[1em]
};
\ByteIndicator{3};
\ByteIndicator{5};
\ByteIndicator{7};
\HLindicator{3}{0.8ex};
\HLindicator{5}{3.15ex};
\HLindicator{7}{5.6ex};
\end{tikzpicture}
\end{tabular}
\begin{DetailEffects}[p]
\FlagsRRD
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{5}{18}
\end{DetailTiming}
\DetailNote{Note: similar to {\tt RLD}, this instruction also doesn't assume any format of the data; it simply rotates nibbles. So while it's most frequently associated with BCD numbers, it can be used for shifting hexadecimal values or any other content.}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{RST}{n}
{\IH{R}e\IH{ST}art}
{\SymRST{n}}
\begin{DetailVariants}
RST \$00\\
RST \$08\\
RST \$10\\
RST \$18
\columnbreak
RST \$20\\
RST \$28\\
RST \$30\\
RST \$38
\end{DetailVariants}
Restarts at the zero page address {\tt s}. Only above addresses are possible, all in page {\tt 0} of the memory, therefore the most significant byte of the program counter {\tt PC} is loaded with {\tt \$00}. The instruction may be used as a fast response to an interrupt.
\begin{DetailEffects}
\FlagsRSTn
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{3}{11}
\end{DetailTiming}
\end{DetailItem}
% SBC should be listed here alphabetically, but we move it backwards so we can have both SBC and SUB on the same page spread for easier comparison
\DetailItemSeePageReference{SBC}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{SCF}{}
{\IH{S}et \IH{C}arry \IH{F}lag}
{\SymSCF}
Sets carry flag \FlagCF{}.
\begin{DetailEffects}
\FlagsSCF
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{1}{4}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{SET}{b,s}
{\IH{SET} bit}
{\SymSET{s}}
\begin{DetailVariants}
SET b,A\\
SET b,B\\
SET b,C\\
SET b,D\\
SET b,E\\
SET b,H\\
SET b,L\\
SET b,(HL)\\
SET b,(IX+d)\\
SET b,(IY+d)
\columnbreak
SET b,(IX+d),A\UNDOC\\
SET b,(IX+d),B\UNDOC\\
SET b,(IX+d),C\UNDOC\\
SET b,(IX+d),D\UNDOC\\
SET b,(IX+d),E\UNDOC\\
SET b,(IX+d),H\UNDOC\\
SET b,(IX+d),L\UNDOC
\columnbreak
SET b,(IY+d),A\UNDOC\\
SET b,(IY+d),B\UNDOC\\
SET b,(IY+d),C\UNDOC\\
SET b,(IY+d),D\UNDOC\\
SET b,(IY+d),E\UNDOC\\
SET b,(IY+d),H\UNDOC\\
SET b,(IY+d),L\UNDOC
\end{DetailVariants}
Sets bit {\tt b} ({\tt 0-7}) of operand {\tt s} or memory location addressed by {\tt s}.
Note: undocumented variants work slightly differently:
\begin{multicols}{2}
\DetailSymbolVariants{SET b,(IX+d),r}{\SymSETu{r}{IX}}
\DetailSymbolVariants{SET b,(IY+d),r}{\SymSETu{r}{IY}}
\end{multicols}
\begin{DetailEffects}
\FlagsSETr
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime[r]{2}{8}
\DetailTime[(HL)]{4}{15}
\DetailTime[(IX+d)]{6}{23}
\DetailTime[(IY+d)]{6}{23}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{SETAE}{\DetailItemZXN}
{\IH{SET} \IH{A}ccumulator from \IH{E}}
{\SymSETAE}
Takes the bit number to set from {\tt E} (only the low 3 bits) and sets the value of the accumulator {\tt A} to the value of that bit, but counted from top to bottom ({\tt E=0} will produce {\tt A$\leftarrow$\$80}, {\tt E=7} will produce {\tt A$\leftarrow$\$01} and so on). This works as pixel mask for ULA bitmap modes, when {\tt E} represents x-coordinate {\tt 0-255}.
\begin{DetailEffects}
\FlagsSETAE
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{2}{8}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{SLA}{s}
{\IH{S}hift \IH{L}eft \IH{A}rithmetic}
{\SymSLA{s}}
\begin{DetailVariants}
SLA A\\
SLA B\\
SLA C\\
SLA D\\
SLA E\\
SLA H\\
SLA L\\
SLA (HL)\\
SLA (IX+d)\\
SLA (IY+d)
\columnbreak
SLA (IX+d),A\UNDOC\\
SLA (IX+d),B\UNDOC\\
SLA (IX+d),C\UNDOC\\
SLA (IX+d),D\UNDOC\\
SLA (IX+d),E\UNDOC\\
SLA (IX+d),H\UNDOC\\
SLA (IX+d),L\UNDOC
\columnbreak
SLA (IY+d),A\UNDOC\\
SLA (IY+d),B\UNDOC\\
SLA (IY+d),C\UNDOC\\
SLA (IY+d),D\UNDOC\\
SLA (IY+d),E\UNDOC\\
SLA (IY+d),H\UNDOC\\
SLA (IY+d),L\UNDOC
\end{DetailVariants}
Performs arithmetic shift left of the operand {\tt s} or memory location addressed by {\tt s}. Bit {\tt 0} is forced to {\tt 0} and bit {\tt 7} is moved to \FlagCF{}.
\begin{DetailEffects}[p]
\FlagsSLAr
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign}
\DetailFlagZF{\DetailFlagResultZero}
\DetailFlagPV{\DetailFlagResultParity}
\DetailFlagCF[set to:]{bit 7 of the original value}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[r]{2}{8}
\DetailTime[(HL)]{4}{15}
\DetailTime[(IX+d)]{6}{23}
\DetailTime[(IY+d)]{6}{23}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{SLL}{}
{\IH{S}hift \IH{L}eft \IH{L}ogical}
{}
This mnemonic has no associated opcode on Next. There is no difference between logical and arithmetic shift left, use {\tt SLA} for both. Some assemblers will allow {\tt SLL} as equivalent, but unfortunately, some will assemble it as {\tt SLI}, so it's best avoiding.
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItemMultiline}
{SLI}{s\UNDOC}{\IH{S}hift \IH{L}eft and \IH{I}ncrement}
{SL1}{s\UNDOC}{\IH{S}hift \IH{L}eft and add \IH{1}}
{\SymSLI{s}}
\begin{DetailVariants}
SLI A\\
SLI B\\
SLI C\\
SLI D\\
SLI E\\
SLI H\\
SLI L\\
SLA (HL)\\
SLA (IX+d)\\
SLA (IY+d)
\columnbreak
SLI (IX+d),A\UNDOC\\
SLI (IX+d),B\UNDOC\\
SLI (IX+d),C\UNDOC\\
SLI (IX+d),D\UNDOC\\
SLI (IX+d),E\UNDOC\\
SLI (IX+d),H\UNDOC\\
SLI (IX+d),L\UNDOC
\columnbreak
SLI (IY+d),A\UNDOC\\
SLI (IY+d),B\UNDOC\\
SLI (IY+d),C\UNDOC\\
SLI (IY+d),D\UNDOC\\
SLI (IY+d),E\UNDOC\\
SLI (IY+d),H\UNDOC\\
SLI (IY+d),L\UNDOC
\end{DetailVariants}
Undocumented instruction. Similar to {\tt SLA} except {\tt 1} is moved to bit {\tt 0}.
\begin{DetailEffects}[p]
\FlagsSLIr
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign}
\DetailFlagZF{\DetailFlagResultZero}
\DetailFlagPV{\DetailFlagResultParity}
\DetailFlagCF[set to:]{bit 7 of the original value}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[r]{2}{8}
\DetailTime[(HL)]{4}{15}
\DetailTime[(IX+d)]{6}{23}
\DetailTime[(IY+d)]{6}{23}
\end{DetailTiming}
\DetailNote{Note: most assemblers will accept both variants: {\tt SLI} or {\tt SL1}, but some may only accept one or the other, while some may expect {\tt SLL} instead.}
\end{DetailItemMultiline}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{SRA}{s}
{\IH{S}hift \IH{R}ight \IH{A}rithmetic}
{\SymSRA{s}}
% we're using non-standard layout here so that we can fit SRA and SRL to the same page
\begin{DetailVariants}[p{1.3cm}p{3.5cm}XX]
SRA A & SRA (HL) & SRA (IX+d),A\UNDOC & SRA (IY+d),A\UNDOC \\
SRA B & SRA (IX+d) & SRA (IX+d),B\UNDOC & SRA (IY+d),B\UNDOC \\
SRA C & SRA (IY+d) & SRA (IX+d),C\UNDOC & SRA (IY+d),C\UNDOC \\
SRA D & & SRA (IX+d),D\UNDOC & SRA (IY+d),D\UNDOC \\
SRA E & & SRA (IX+d),E\UNDOC & SRA (IY+d),E\UNDOC \\
SRA H & & SRA (IX+d),H\UNDOC & SRA (IY+d),H\UNDOC \\
SRA L & & SRA (IX+d),L\UNDOC & SRA (IY+d),L\UNDOC \\
\end{DetailVariants}
Performs arithmetic shift right of the operand {\tt s} or memory location addressed by {\tt s}. Bit {\tt 0} is moved to \FlagCF{} while bit {\tt 7} remains unchanged (on the assumption that it's the sign bit).
\begin{DetailEffects}[p]
\FlagsSRAr
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign}
\DetailFlagZF{\DetailFlagResultZero}
\DetailFlagPV{\DetailFlagResultParity}
\DetailFlagCF[set to:]{bit 0 of the original value}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[r]{2}{8}
\DetailTime[(HL)]{4}{15}
\DetailTime[(IX+d)]{6}{23}
\DetailTime[(IY+d)]{6}{23}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{SRL}{s}
{\IH{S}hift \IH{R}ight \IH{L}ogical}
{\SymSRL{s}}
% we're using non-standard layout here so that we can fit SRA and SRL to the same page
\begin{DetailVariants}[p{1.3cm}p{3.5cm}XX]
SRL A & SRL (HL) & SRL (IX+d),A\UNDOC & SRL (IY+d),A\UNDOC \\
SRL B & SRL (IX+d) & SRL (IX+d),B\UNDOC & SRL (IY+d),B\UNDOC \\
SRL C & SRL (IY+d) & SRL (IX+d),C\UNDOC & SRL (IY+d),C\UNDOC \\
SRL D & & SRL (IX+d),D\UNDOC & SRL (IY+d),D\UNDOC \\
SRL E & & SRL (IX+d),E\UNDOC & SRL (IY+d),E\UNDOC \\
SRL H & & SRL (IX+d),H\UNDOC & SRL (IY+d),H\UNDOC \\
SRL L & & SRL (IX+d),L\UNDOC & SRL (IY+d),L\UNDOC \\
\end{DetailVariants}
Performs logical shift right of the operand {\tt s} or memory location addressed by {\tt s}. Bit {\tt 0} is moved to \FlagCF{} while {\tt 0} is moved to bit {\tt 7}.
\begin{DetailEffects}[p]
\FlagsSRLr
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign}
\DetailFlagZF{\DetailFlagResultZero}
\DetailFlagPV{\DetailFlagResultParity}
\DetailFlagCF[set to:]{bit 0 of the original value}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[r]{2}{8}
\DetailTime[(HL)]{4}{15}
\DetailTime[(IX+d)]{6}{23}
\DetailTime[(IY+d)]{6}{23}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{SBC}{d,s}
{\IH{S}u\IH{B}tract with \IH{C}arry}
{\SymSBC{d}{s}}
\begin{DetailVariants}
\textnormal{8 bit}\\
SBC A,A\\
SBC A,B\\
SBC A,C\\
SBC A,D\\
SBC A,E\\
SBC A,H\\
SBC A,L\\
SBC A,n
\columnbreak
\textnormal{8 bit}\\
SBC A,IXH\UNDOC\\
SBC A,IXL\UNDOC\\
SBC A,IYH\UNDOC\\
SBC A,IYL\UNDOC\\
SBC A,(HL)\\
SBC A,(IX+d)\\
SBC A,(IY+d)
\columnbreak
\textnormal{16 bit}\\
SBC HL,BC\\
SBC HL,DE\\
SBC HL,HL\\
SBC HL,SP
\end{DetailVariants}
Subtracts source operand {\tt s} or contents of the memory location addressed by {\tt s} and carry flag \FlagCF{} from destination {\tt d}. Result is then stored to destination {\tt d}.
\begin{DetailEffects}[v]
\FlagsSBCr[8-bit]
\FlagsSBCrr[16-bit]
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign}
\DetailFlagZF{\DetailFlagResultZero}
\DetailFlagHF{\DetailFlagResultHalfBorrow*}*
\DetailFlagPV{\DetailFlagResultOverflow}*
\DetailFlagCF{\DetailFlagResultBorrow*}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[r]{1}{4}
\DetailTime[n]{2}{7}
\DetailTime[(HL)]{2}{7}
\DetailTime[HL,rr]{4}{15}
\DetailTime[(IX+d)]{5}{19}
\DetailTime[(IY+d)]{5}{19}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{SUB}{s}
{\IH{SUB}tract}
{\SymSUB{s}}
\begin{DetailVariants}
SUB A\\
SUB B\\
SUB C\\
SUB D\\
SUB E\\
SUB H\\
SUB L
\columnbreak
SUB n\\
SUB (HL)\\
SUB (IX+d)\\
SUB (IY+d)
\columnbreak
SUB IXH\UNDOC\\
SUB IXL\UNDOC\\
SUB IYH\UNDOC\\
SUB IYL\UNDOC
\end{DetailVariants}
Subtracts 8-bit immediate value, operand {\tt s} or memory location addressed by {\tt s} from accumulator {\tt A}. Then stores result back to {\tt A}.
\begin{DetailEffects}[v]
\FlagsSUBr
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign}
\DetailFlagZF{\DetailFlagResultZero}
\DetailFlagHF{\DetailFlagResultHalfBorrow*}*
\DetailFlagPV{\DetailFlagResultOverflow}*
\DetailFlagCF{\DetailFlagResultBorrow*}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[r]{1}{4}
\DetailTime[n]{2}{7}
\DetailTime[(HL)]{2}{7}
\DetailTime[(IX+d)]{5}{19}
\DetailTime[(IY+d)]{5}{19}
\end{DetailTiming}
\end{DetailItem}
\pagebreak
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{SWAPNIB}{\DetailItemZXN}
{\IH{SWAP} \IH{NIB}bles}
{\SymSWAPNIB}
Swaps the high and low nibbles of the accumulator {\tt A}.
\begin{DetailEffects}
\FlagsSWAPNIB
\end{DetailEffects}
\begin{DetailTiming}
\DetailTime{2}{8}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
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%----------------------------------------------------------------------------------------------------------------------
\begin{DetailItem}{TEST}{n\ZXN}
{\IH{TEST}}
{\SymTEST}
Similar to {\tt CP} (page \DetailItemPageRef{CP}), but performs an {\tt AND} instead of a subtraction. Again, {\tt AND} is performed between the accumulator {\tt A} and value {\tt n}. Status flags are updated according to the result, but the result is then discarded (value of {\tt A} is not changed).
\begin{DetailEffects}[p]
\FlagsTESTn
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign}
\DetailFlagZF{\DetailFlagResultZero ~(no bits matched)}
\DetailFlagPV{\DetailFlagResultParity}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime{3}{11}
\end{DetailTiming}
\end{DetailItem}
%----------------------------------------------------------------------------------------------------------------------
% ███████████████████████████████████████████████████████████████████
% █▄─▄█▄─▀█▄─▄█─▄▄▄▄█─▄─▄─█▄─▄▄▀█▄─██─▄█─▄▄▄─█─▄─▄─█▄─▄█─▄▄─█▄─▀█▄─▄█
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% ▀▄▄▄▀▄▄▄▀▀▄▄▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▀▄▄▀▀▄▄▄▄▀▀▄▄▄▄▄▀▀▄▄▄▀▀▄▄▄▀▄▄▄▄▀▄▄▄▀▀▄▄▀
%----------------------------------------------------------------------------------------------------------------------
\pagebreak
\begin{DetailItem}{XOR}{s}
{bitwise e\IH{X}clusive \IH{OR}}
{\SymXOR{s}}
\begin{DetailVariants}
XOR A\\
XOR B\\
XOR C\\
XOR D\\
XOR E\\
XOR H\\
XOR L\\
XOR n
\columnbreak
XOR (HL)\\
XOR (IX+d)\\
XOR (IY+d)
\columnbreak
XOR IXH\UNDOC\\
XOR IXL\UNDOC\\
XOR IYH\UNDOC\\
XOR IYL\UNDOC
\end{DetailVariants}
\begin{tabularx}{\linewidth}{@{}Xl}
Performs exclusive or between accumulator {\tt A} and operand {\tt s} or memory location addressed by {\tt s}. Result is then stored back to {\tt A}. Individual bits are XOR'ed as shown on the right:
&
\begin{tabular}[t]{cc|c}
{\tt A} & {\tt s} & Result \\
\hline
{\tt 0} & {\tt 0} & {\tt 0} \\
{\tt 0} & {\tt 1} & {\tt 1} \\
{\tt 1} & {\tt 0} & {\tt 1} \\
{\tt 1} & {\tt 1} & {\tt 0} \\
\end{tabular}
\\
\end{tabularx}
\begin{DetailEffects}[p]
\FlagsXORr
\end{DetailEffects}
\begin{DetailEffectsFlags}
\DetailFlagSF{\DetailFlagResultSign}
\DetailFlagZF{\DetailFlagResultZero}
\DetailFlagPV{\DetailFlagResultParity}
\end{DetailEffectsFlags}
\begin{DetailTiming}
\DetailTime[r]{1}{4}
\DetailTime[n]{2}{7}
\DetailTime[(HL)]{2}{7}
\DetailTime[(IX+d)]{5}{19}
\DetailTime[(IY+d)]{5}{19}
\end{DetailTiming}
\end{DetailItem}
\end{basedescript}
================================================
FILE: chapter-instr-glance-16bit-arithmetic.tex
================================================
\section{16-Bit Arithmetic}
\vspace*{0.7ex} % ensure this table starts at the same height as the one on the odd page
\begin{minipage}{\textwidth}
\begin{instrtable}
\begin{instruction}{ADC HL,rr}
\Symbol{\SymADC{HL}{rr}}
\FlagsADCrr
\OpCode{11}{101}{101}
\Hex{ED}{2}
\Cycles{4}{15}
\Comment{
\tt
\multirow{4}{*}{
\begin{tabular}{ll}
rr & \OCT{rr} \\
\hline
BC & 00 \\
DE & 01 \\
HL & 10 \\
SP & 11 \\
\end{tabular}
}
}
\SkipToOpCode
\OpCode{01}{\OCT{rr}1}{010}
\Hex{..}{}
\end{instruction}
\begin{instruction}{SBC HL,rr}
\Symbol{\SymSBC{HL}{rr}}
\FlagsSBCrr
\OpCode{11}{101}{101}
\Hex{ED}{2}
\Cycles{4}{15}
\SkipToOpCode
\OpCode{01}{\OCT{rr}0}{010}
\Hex{..}{}
\end{instruction}
\begin{instruction}{ADD HL,rr}
\Symbol{\SymADD{HL}{rr}}
\FlagsADDrr
\OpCode{00}{\OCT{rr}1}{001}
\Hex{..}{1}
\Cycles{3}{11}
\end{instruction}
\begin{instruction}{ADD IX,pp}
\Symbol{\SymADD{IX}{pp}}
\FlagsADDrr
\OpCode{11}{011}{101}
\Hex{DD}{2}
\Cycles{4}{15}
\Comment{
\multirow{4}{*}{
\tt
\begin{tabular}{ll}
pp & \OCT{pp} \\
\hline
BC & 00 \\
DE & 01 \\
IX & 10 \\
SP & 11 \\
\end{tabular}
}
}
\SkipToOpCode
\OpCode{00}{\OCT{pp}1}{001}
\Hex{..}{}
\end{instruction}
\begin{instruction}{ADD IY,qq}
\Symbol{\SymADD{IY}{qq}}
\FlagsADDrr
\OpCode{11}{111}{101}
\Hex{FD}{2}
\Cycles{4}{15}
\SkipToOpCode
\OpCode{00}{\OCT{qq}1}{001}
\Hex{..}{}
\end{instruction}
\begin{instruction}{INC rr}
\Symbol{\SymINC{rr}}
\FlagsINCrr
\OpCode{00}{\OCT{rr}0}{011}
\Hex{..}{1}
\Cycles{1}{6}
\end{instruction}
\begin{instruction}{INC IX}
\Symbol{\SymINC{IX}}
\FlagsINCrr
\OpCode{11}{011}{101}
\Hex{DD}{2}
\Cycles{2}{10}
\Comment{
\multirow{4}{*}{
\tt
\begin{tabular}{ll}
qq & \OCT{qq} \\
\hline
BC & 00 \\
DE & 01 \\
IY & 10 \\
SP & 11 \\
\end{tabular}
}
}
\SkipToOpCode
\OpCode{00}{100}{011}
\Hex{23}{}
\end{instruction}
\begin{instruction}{INC IY}
\Symbol{\SymINC{IY}}
\FlagsINCrr
\OpCode{11}{111}{101}
\Hex{FD}{2}
\Cycles{2}{10}
\SkipToOpCode
\OpCode{00}{100}{011}
\Hex{23}{}
\end{instruction}
\begin{instruction}{DEC rr}
\Symbol{\SymDEC{rr}}
\FlagsDECrr
\OpCode{00}{\OCT{rr}1}{011}
\Hex{..}{1}
\Cycles{1}{6}
\end{instruction}
\begin{instruction}{DEC IX}
\Symbol{\SymDEC{IX}}
\FlagsDECrr
\OpCode{11}{011}{101}
\Hex{DD}{2}
\Cycles{2}{10}
\SkipToOpCode
\OpCode{00}{101}{011}
\Hex{2B}{}
\end{instruction}
\begin{lastinstruction}{DEC IY}
\Symbol{\SymDEC{IY}}
\FlagsDECrr
\OpCode{11}{111}{101}
\Hex{FD}{2}
\Cycles{2}{10}
\SkipToOpCode
\OpCode{00}{101}{011}
\Hex{2B}{}
\end{lastinstruction}
\end{instrtable}
\begin{notestable}
\NoteItem{\See{1}Flag is set by carry from bit 15}
\NoteItem{\See{2}Flag is set by carry from bit 11 (half carry in high byte)}
\end{notestable}
\end{minipage}
================================================
FILE: chapter-instr-glance-16bit-load.tex
================================================
\section{16-Bit Load}
\begin{instrtable}
\begin{instruction}{LD rr,nm}
\Symbol{\SymLD{rr}{nm}}
\FlagsLDrr
\OpCode{00}{\OCT{rr}0}{001}
\Hex{..}{3}
\Cycles{3}{10}
\Comment{
\tt
\multirow{4}{*}{
\begin{tabular}{ll}
rr & \OCT{rr} \\
\hline
BC & 00 \\
DE & 01 \\
HL & 10 \\
SP & 11 \\
\end{tabular}
}
}
\SkipToOpCode
\OpRange{m}
\Hex{..}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD IX,nm}
\Symbol{\SymLD{IX}{nm}}
\FlagsLDrr
\OpCode{11}{011}{101}
\Hex{DD}{4}
\Cycles{4}{14}
\SkipToOpCode
\OpCode{00}{100}{001}
\Hex{21}{}
\SkipToOpCode
\OpRange{m}
\Hex{..}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD IY,nm}
\Symbol{\SymLD{IX}{nm}}
\FlagsLDrr
\OpCode{11}{111}{101}
\Hex{FD}{4}
\Cycles{4}{14}
\SkipToOpCode
\OpCode{00}{100}{001}
\Hex{21}{}
\SkipToOpCode
\OpRange{m}
\Hex{..}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD HL,(nm)}
\Symbol{\SymLD{H}{(nm+1)}}
\FlagsLDrr
\OpCode{00}{101}{010}
\Hex{2A}{3}
\Cycles{5}{16}
\SkipToSymbol
\Symbol{\SymLD{L}{(nm)}}
\FromSymbolToOpCode
\OpRange{m}
\Hex{..}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD rr,(nm)}
\Symbol{\SymLD{rr\High}{(nm+1)}}
\FlagsLDrr
\OpCode{11}{101}{101}
\Hex{ED}{4}
\Cycles{6}{20}
\SkipToSymbol
\Symbol{\SymLD{rr\Low}{(nm)}}
\FromSymbolToOpCode
\OpCode{01}{\OCT{rr}1}{011}
\Hex{..}{}
\SkipToOpCode
\OpRange{m}
\Hex{..}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD IX,(nm)}
\Symbol{\SymLD{IX\High}{(nm+1)}}
\FlagsLDrr
\OpCode{11}{011}{101}
\Hex{DD}{4}
\Cycles{6}{20}
\SkipToSymbol
\Symbol{\SymLD{IX\Low}{(nm)}}
\FromSymbolToOpCode
\OpCode{00}{101}{010}
\Hex{2A}{}
\SkipToOpCode
\OpRange{m}
\Hex{..}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD IY,(nm)}
\Symbol{\SymLD{IY\High}{(nm+1)}}
\FlagsLDrr
\OpCode{11}{111}{101}
\Hex{FD}{4}
\Cycles{6}{20}
\SkipToSymbol
\Symbol{\SymLD{IY\Low}{(nn)}}
\FromSymbolToOpCode
\OpCode{00}{101}{010}
\Hex{2A}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD (nm),HL}
\Symbol{\SymLD{(nn+1)}{H}}
\FlagsLDrr
\OpCode{00}{100}{010}
\Hex{22}{3}
\Cycles{5}{16}
\SkipToSymbol
\Symbol{\SymLD{(nm)}{L}}
\FromSymbolToOpCode
\OpRange{m}
\Hex{..}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD (nm),rr}
\Symbol{\SymLD{(nm+1)}{rr\High}}
\FlagsLDrr
\OpCode{11}{101}{101}
\Hex{ED}{4}
\Cycles{6}{20}
\SkipToSymbol
\Symbol{\SymLD{(nm)}{rr\Low}}
\FromSymbolToOpCode
\OpCode{01}{\OCT{rr}0}{011}
\Hex{..}{}
\SkipToOpCode
\OpRange{m}
\Hex{..}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD (nm),IX}
\Symbol{\SymLD{(nm+1)}{IX\High}}
\FlagsLDrr
\OpCode{11}{011}{101}
\Hex{DD}{4}
\Cycles{6}{20}
\SkipToSymbol
\Symbol{\SymLD{(nm)}{IX\Low}}
\FromSymbolToOpCode
\OpCode{00}{100}{010}
\Hex{22}{}
\SkipToOpCode
\OpRange{m}
\Hex{..}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD (nm),IY}
\Symbol{\SymLD{(nm+1)}{IY\High}}
\FlagsLDrr
\OpCode{11}{111}{101}
\Hex{FD}{4}
\Cycles{6}{20}
\SkipToSymbol
\Symbol{\SymLD{(nm)}{IY\Low}}
\FromSymbolToOpCode
\OpCode{00}{100}{010}
\Hex{22}{}
\SkipToOpCode
\OpRange{m}
\Hex{..}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD SP,HL}
\Symbol{\SymLD{SP}{HL}}
\FlagsLDrr
\OpCode{11}{111}{001}
\Hex{F9}{1}
\Cycles{1}{6}
\end{instruction}
\begin{instruction}{LD SP,IX}
\Symbol{\SymLD{SP}{IX}}
\FlagsLDrr
\OpCode{11}{011}{101}
\Hex{DD}{2}
\Cycles{2}{10}
\SkipToOpCode
\OpCode{11}{111}{001}
\Hex{F9}{}
\end{instruction}
\begin{lastinstruction}{LD SP,IY}
\Symbol{\SymLD{SP}{IY}}
\FlagsLDrr
\OpCode{11}{111}{101}
\Hex{FD}{2}
\Cycles{2}{10}
\SkipToOpCode
\OpCode{11}{111}{001}
\Hex{F9}{}
\end{lastinstruction}
\end{instrtable}
================================================
FILE: chapter-instr-glance-8bit-arithmetic.tex
================================================
\section{8-Bit Arithmetic and Logical}
\begin{minipage}{\textwidth}
\begin{instrtable}
\begin{instruction}{ADD A,r}
\Symbol{\SymADD{A}{r}}
\FlagsADDr
\OpCode{10}{\fbox{000}}{\OCT{r}}
\Hex{..}{1}
\Cycles{1}{4}
\Comment{
\tt
\multirow{6}{*}{
\begin{tabular}{ll}
r & \OCT{r} \\
\hline
B & 000 \\
C & 001 \\
D & 010 \\
E & 011 \\
H & 100 \\
L & 101 \\
A & 111 \\
\end{tabular}
}
}
\end{instruction}
\begin{instruction}{ADD A,p}
\Symbol{\SymADD{A}{p}}
\FlagsADDr
\OpCode{11}{011}{101}
\Hex{DD}{2}
\Cycles{2}{8}
\SkipToOpCode
\OpCode{10}{\fbox{000}}{\OCT{p}}
\Hex{..}{}
\Cycles{}{}
\end{instruction}
\begin{instruction}{ADD A,q}
\Symbol{\SymADD{A}{q}}
\FlagsADDr
\OpCode{11}{111}{101}
\Hex{FD}{2}
\Cycles{2}{8}
\SkipToOpCode
\OpCode{10}{\fbox{000}}{\OCT{q}}
\Hex{..}{}
\end{instruction}
\begin{instruction}{ADD A,n}
\Symbol{\SymADD{A}{n}}
\FlagsADDr
\OpCode{11}{\fbox{000}}{110}
\Hex{C6}{2}
\Cycles{2}{7}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{ADD A,(HL)}
\Symbol{\SymADD{A}{(HL)}}
\FlagsADDr
\OpCode{10}{\fbox{000}}{110}
\Hex{86}{1}
\Cycles{2}{7}
\Comment{
\multirow{8}{*}{
\tt
\begin{tabular}{ll}
p & \OCT{p} \\
\hline
B & 000 \\
C & 001 \\
D & 010 \\
E & 011 \\
IX\High & 100 \\
IX\Low & 101 \\
A & 111 \\
\end{tabular}
}
}
\end{instruction}
\begin{instruction}{ADD A,(IX+d)}
\Symbol{\SymADD{A}{(IX+d)}}
\FlagsADDr
\OpCode{11}{011}{101}
\Hex{DD}{3}
\Cycles{5}{19}
\SkipToOpCode
\OpCode{10}{\fbox{000}}{110}
\Hex{86}{}
\SkipToOpCode
\OpRange{d}
\Hex{..}{}
\end{instruction}
\begin{instruction}{ADD A,(IY+d)}
\Symbol{\SymADD{A}{(IY+d)}}
\FlagsADDr
\OpCode{11}{111}{101}
\Hex{FD}{3}
\Cycles{5}{19}
\SkipToOpCode
\OpCode{10}{\fbox{000}}{110}
\Hex{86}{}
\SkipToOpCode
\OpRange{d}
\Hex{..}{}
\end{instruction}
\StartWithOpCode\OpCode{}{$\uparrow$}{}\\
\begin{instruction}{ADC A,s\See{2}}
\Symbol{\SymADC{A}{s}}
\FlagsADCr
\OpCode{..}{\fbox{001}}{...}
\Hex{}{}
\Cycles{}{}
\Comment{
\multirow{8}{*}{
\tt
\begin{tabular}{ll}
q & \OCT{q} \\
\hline
B & 000 \\
C & 001 \\
D & 010 \\
E & 011 \\
IY\High & 100 \\
IY\Low & 101 \\
A & 111 \\
\end{tabular}
}
}
\end{instruction}
\begin{instruction}{SUB s\See{2}}
\Symbol{\SymSUB{s}}
\FlagsSUBr
\OpCode{..}{\fbox{010}}{...}
\end{instruction}
\begin{instruction}{SBC A,s\See{2}}
\Symbol{\SymSBC{A}{s}}
\FlagsSBCr
\OpCode{..}{\fbox{011}}{...}
\end{instruction}
\begin{instruction}{AND s\See{2}}
\Symbol{\SymAND{s}}
\FlagsANDr
\OpCode{..}{\fbox{100}}{...}
\end{instruction}
\begin{instruction}{XOR s\See{2}}
\Symbol{\SymXOR{s}}
\FlagsXORr
\OpCode{..}{\fbox{101}}{...}
\end{instruction}
\begin{instruction}{OR s\See{2}}
\Symbol{\SymOR{s}}
\FlagsORr
\OpCode{..}{\fbox{110}}{...}
\end{instruction}
\begin{instruction}{CP s\See{1,2}}
\Symbol{\SymCP{s}}
\FlagsCPr
\OpCode{..}{\fbox{111}}{...}
\end{instruction}
\Empty{}
\begin{instruction}{INC r}
\Symbol{\SymINC{r}}
\FlagsINCr
\OpCode{00}{\OCT{r}}{\fbox{100}}
\Hex{..}{1}
\Cycles{1}{4}
\end{instruction}
\begin{instruction}{INC p}
\Symbol{\SymINC{p}}
\FlagsINCr
\OpCode{11}{011}{101}
\Hex{DD}{2}
\Cycles{2}{8}
\SkipToOpCode
\OpCode{00}{\OCT{p}}{\fbox{100}}
\Hex{..}{}
\end{instruction}
\begin{instruction}{INC q}
\Symbol{\SymINC{q}}
\FlagsINCr
\OpCode{11}{111}{101}
\Hex{FD}{2}
\Hex{2}{8}
\SkipToOpCode
\OpCode{00}{\OCT{q}}{\fbox{100}}
\Hex{..}{}
\end{instruction}
\begin{instruction}{INC (HL)}
\Symbol{\SymINC{(HL)}}
\FlagsINCr
\OpCode{00}{110}{\fbox{100}}
\Hex{34}{1}
\Cycles{3}{11}
\end{instruction}
\begin{instruction}{INC (IX+d)}
\Symbol{\SymINC{(IX+d)}}
\FlagsINCr
\OpCode{11}{011}{101}
\Hex{DD}{3}
\Cycles{6}{23}
\SkipToOpCode
\OpCode{00}{110}{\fbox{100}}
\Hex{34}{}
\SkipToOpCode
\OpRange{d}
\end{instruction}
\begin{instruction}{INC (IY+d)}
\Symbol{\SymINC{(IY+d)}}
\FlagsINCr
\OpCode{11}{111}{101}
\Hex{FD}{3}
\Cycles{6}{23}
\SkipToOpCode
\OpCode{00}{110}{\fbox{100}}
\Hex{34}{}
\SkipToOpCode
\OpRange{d}
\end{instruction}
\StartWithOpCode\OpCode{}{}{$\uparrow$} \\
\begin{lastinstruction}{DEC m\See{3}}
\Symbol{\SymDEC{m}}
\FlagsDECr
\OpCode{..}{...}{\fbox{101}}
\end{lastinstruction}
\end{instrtable}
\begin{notestable}
\NoteItem{\See{1}YF and XF flags are copied from the operand {\tt s}, not the result {\tt A-s}}
\NoteItem{\See{2}{\tt s} is any of {\tt r}, {\tt p}, {\tt q}, {\tt n}, {\tt (HL)}, {\tt (IX+d)}, {\tt (IY+d)} as shown for {\tt ADD}. Replace \fbox{{\tt 000}} in the {\tt ADD} set above. Ts also the same}
\NoteItem{\See{3}{\tt m} is any of {\tt r}, {\tt p}, {\tt q}, {\tt n}, {\tt (HL)}, {\tt (IX+d)}, {\tt (IY+d)} as shown for {\tt INC}. Replace \fbox{{\tt 100}} with \fbox{{\tt 101}} in opcode. Ts also the same}
\NoteItem{\See{4}PV set if value was {\tt \$7F} before incrementing}
\NoteItem{\See{5}PV set if value was {\tt \$80} before decrementing}
\end{notestable}
\end{minipage}
================================================
FILE: chapter-instr-glance-8bit-load.tex
================================================
\section{8-Bit Load}
\begin{instrtable}
\begin{instruction}{LD r,r'}
\Symbol{\SymLD{r}{r'}}
\FlagsLDr
\OpCode{01}{\OCT{r}}{\OCTS{r}}
\Hex{..}{1}
\Cycles{1}{4}
\Comment{
\tt
\multirow{6}{*}{
\begin{tabular}{ll}
r & \OCT{r} \\
r' & \OCTS{r} \\
\hline
B & 000 \\
C & 001 \\
D & 010 \\
E & 011 \\
H & 100 \\
L & 101 \\
A & 111 \\
\end{tabular}
}
}
\end{instruction}
\begin{instruction}{LD p,p'}
\Symbol{\SymLD{p}{p'}}
\FlagsLDr
\OpCode{11}{011}{101}
\Hex{DD}{2}
\Cycles{2}{8}
\SkipToOpCode
\OpCode{01}{\OCT{p}}{\OCTS{p}}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD q,q'}
\Symbol{\SymLD{q}{q'}}
\FlagsLDr
\OpCode{11}{111}{101}
\Hex{FD}{2}
\Cycles{2}{8}
\SkipToOpCode
\OpCode{01}{\OCT{q}}{\OCTS{q}}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD r,n}
\Symbol{\SymLD{r}{n}}
\FlagsLDr
\OpCode{00}{\OCT{r}}{110}
\Hex{..}{2}
\Cycles{2}{7}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD p,n}
\Symbol{\SymLD{p}{n}}
\FlagsLDr
\OpCode{11}{011}{101}
\Hex{DD}{3}
\Cycles{3}{11}
\Comment{
\multirow{6}{*}{
\tt
\begin{tabular}{ll}
p & \OCT{p} \\
p' & \OCTS{p} \\
\hline
B & 000 \\
C & 001 \\
D & 010 \\
E & 011 \\
IX\High & 100 \\
IX\Low & 101 \\
A & 111 \\
\end{tabular}
}
}
\SkipToOpCode
\OpCode{00}{\OCT{p}}{110}
\Hex{..}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD q,n}
\Symbol{\SymLD{q}{n}}
\FlagsLDr
\OpCode{11}{111}{101}
\Hex{FD}{3}
\Cycles{3}{11}
\SkipToOpCode
\OpCode{00}{\OCT{q}}{110}
\Hex{..}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD r,(HL)}
\Symbol{\SymLD{r}{(HL)}}
\FlagsLDr
\OpCode{01}{\OCT{r}}{110}
\Hex{..}{1}
\Cycles{2}{7}
\end{instruction}
\begin{instruction}{LD r,(IX+d)}
\Symbol{\SymLD{r}{(IX+d)}}
\FlagsLDr
\OpCode{11}{011}{101}
\Hex{DD}{3}
\Cycles{5}{19}
\Comment{
\multirow{6}{*}{
\tt
\begin{tabular}{ll}
q & \OCT{q} \\
q' & \OCTS{q} \\
\hline
B & 000 \\
C & 001 \\
D & 010 \\
E & 011 \\
IY\High & 100 \\
IY\Low & 101\\
A & 111 \\
\end{tabular}
}
}
\SkipToOpCode
\OpCode{01}{\OCT{r}}{110}
\Hex{..}{}
\SkipToOpCode
\OpRange{d}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD r,(IY+d)}
\Symbol{\SymLD{r}{(IY+d)}}
\FlagsLDr
\OpCode{11}{111}{101}
\Hex{FD}{3}
\Cycles{5}{19}
\SkipToOpCode
\OpCode{01}{\OCT{r}}{110}
\Hex{..}{}
\SkipToOpCode
\OpRange{d}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD (HL),r}
\Symbol{\SymLD{(HL)}{r}}
\FlagsLDr
\OpCode{01}{110}{\OCT{r}}
\Hex{..}{1}
\Cycles{2}{7}
\end{instruction}
\begin{instruction}{LD (IX+d),r}
\Symbol{\SymLD{(IX+d)}{r}}
\FlagsLDr
\OpCode{11}{011}{101}
\Hex{DD}{3}
\Cycles{5}{19}
\SkipToOpCode
\OpCode{01}{110}{\OCT{r}}
\Hex{..}{}
\SkipToOpCode
\OpRange{d}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD (IY+d),r}
\Symbol{\SymLD{(IY+d)}{r}}
\FlagsLDr
\OpCode{11}{111}{101}
\Hex{FD}{3}
\Cycles{5}{19}
\SkipToOpCode
\OpCode{01}{110}{\OCT{r}}
\Hex{..}{}
\SkipToOpCode
\OpRange{d}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD (HL),n}
\Symbol{\SymLD{(HL)}{n}}
\FlagsLDr
\OpCode{00}{110}{110}
\Hex{36}{2}
\Cycles{3}{10}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD (IX+d),n}
\Symbol{\SymLD{(IX+d)}{n}}
\FlagsLDr
\OpCode{11}{011}{101}
\Hex{DD}{4}
\Cycles{5}{19}
\SkipToOpCode
\OpCode{00}{110}{110}
\Hex{36}{}
\SkipToOpCode
\OpRange{d}
\Hex{..}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD (IY+d),n}
\Symbol{\SymLD{(IY+d)}{n}}
\FlagsLDr
\OpCode{11}{111}{101}
\Hex{FD}{4}
\Cycles{5}{19}
\SkipToOpCode
\OpCode{00}{110}{110}
\Hex{36}{}
\SkipToOpCode
\OpRange{d}
\Hex{..}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD A,(BC)}
\Symbol{\SymLD{A}{(BC)}}
\FlagsLDr
\OpCode{00}{001}{010}
\Hex{0A}{1}
\Cycles{2}{7}
\end{instruction}
\begin{instruction}{LD A,(DE)}
\Symbol{\SymLD{A}{(DE)}}
\FlagsLDr
\OpCode{00}{011}{01}
\Hex{1A}{1}
\Cycles{2}{7}
\end{instruction}
\begin{lastinstruction}{LD A,(nm)}
\Symbol{\SymLD{A}{(nm)}}
\FlagsLDr
\OpCode{00}{111}{010}
\Hex{3A}{3}
\Cycles{4}{13}
\SkipToOpCode
\OpRange{m}
\Hex{..}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{lastinstruction}
\end{instrtable}
\InstrTableContinue
\pagebreak
\vspace*{0.38cm} % ensure this table starts at the same height as the one on the odd page
\begin{instrtable}
\begin{instruction}{LD (BC),A}
\Symbol{\SymLD{(BC)}{A}}
\FlagsLDr
\OpCode{00}{000}{010}
\Hex{02}{1}
\Cycles{2}{7}
\end{instruction}
\begin{instruction}{LD (DE),A}
\Symbol{\SymLD{(DE)}{A}}
\FlagsLDr
\OpCode{00}{010}{010}
\Hex{12}{1}
\Cycles{2}{7}
\end{instruction}
\begin{instruction}{LD (nm),A}
\Symbol{\SymLD{(nm)}{A}}
\FlagsLDr
\OpCode{00}{110}{010}
\Hex{32}{3}
\Cycles{4}{13}
\SkipToOpCode
\OpRange{m}
\Hex{..}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{LD A,I}
\Symbol{\SymLD{A}{I}}
\FlagsLDair
\OpCode{11}{101}{101}
\Hex{ED}{2}
\Cycles{2}{9}
\SkipToOpCode
\OpCode{01}{010}{111}
\Hex{57}{}
\end{instruction}
\begin{instruction}{LD A,R}
\Symbol{\SymLD{A}{R}}
\FlagsLDair
\OpCode{11}{101}{101}
\Hex{ED}{2}
\Cycles{2}{9}
\SkipToOpCode
\OpCode{01}{011}{111}
\Hex{5F}{}
\end{instruction}
\begin{instruction}{LD I,A}
\Symbol{\SymLD{I}{A}}
\FlagsLDr
\OpCode{11}{101}{101}
\Hex{ED}{2}
\Cycles{2}{9}
\SkipToOpCode
\OpCode{01}{000}{111}
\Hex{47}{}
\end{instruction}
\begin{lastinstruction}{LD R,A}
\Symbol{\SymLD{R}{A}}
\FlagsLDr
\OpCode{11}{101}{101}
\Hex{ED}{2}
\Cycles{2}{9}
\SkipToOpCode
\OpCode{01}{001}{111}
\Hex{4F}{}
\end{lastinstruction}
\end{instrtable}
================================================
FILE: chapter-instr-glance-alphabetical.tex
================================================
% Alphabetical section only really makes sense for printed book; online PDF can be searched to get to specific instructions. TBH, the whole "in a glance" chapter only truly comes to life on paper, for online version, details chapter is more suitable, combined with sorted by mnemonic if actual machine codes are needed. But for now I'm only stripping alphabetical section out...
\ifdefined\isPDF
\else
\section{Alphabetical}
\renewcommand{\FlagsSee}[1]{} % we don't want to display any footnotes in alphabetical list; it would result in too many notes as instructions are not grouped by their resemblance
% note we don't need `lastinstruction` here because we don't use bottom hline; however it's still useful in cases where last instruction in the table would otherwise cause vertical gap before next table
\begin{instrtablesimple}
\begin{instruction}{ADC A,r}
\Symbol{\SymADC{A}{r}}
\FlagsADCr
\OpCode{10}{001}{\OCT{r}}
\Hex{..}{1}
\Cycles{1}{4}
\end{instruction}
\begin{instruction}{ADC A,n}
\Symbol{\SymADC{A}{n}}
\FlagsADCr
\OpCode{11}{001}{110}
\Hex{CE}{2}
\Cycles{2}{7}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{ADC A,(HL)}
\Symbol{\SymADC{A}{(HL)}}
\FlagsADCr
\OpCode{10}{001}{110}
\Hex{8E}{1}
\Cycles{2}{7}
\end{instruction}
\begin{instruction}{ADC A,(IX+d)}
\Symbol{\SymADC{A}{(IX+d)}}
\FlagsADCr
\OpCode{11}{011}{101}
\Hex{DD}{3}
\Cycles{5}{19}
\SkipToOpCode
\OpCode{10}{001}{110}
\Hex{8E}{}
\SkipToOpCode
\OpRange{d}
\Hex{..}{}
\end{instruction}
\begin{instruction}{ADC A,(IY+d)}
\Symbol{\SymADC{A}{(IY+d)}}
\FlagsADCr
\OpCode{11}{111}{101}
\Hex{FD}{3}
\Cycles{5}{19}
\SkipToOpCode
\OpCode{10}{001}{110}
\Hex{8E}{}
\SkipToOpCode
\OpRange{d}
\Hex{..}{}
\end{instruction}
\begin{instruction}{ADC HL,rr}
\Symbol{\SymADC{HL}{rr}}
\FlagsADCrr
\OpCode{11}{101}{101}
\Hex{ED}{2}
\Cycles{4}{15}
\SkipToOpCode
\OpCode{01}{\OCT{rr}1}{010}
\Hex{..}{}
\end{instruction}
\EmptySeparator
%-------------------------------------------
\begin{instruction}{ADD A,r}
\Symbol{\SymADD{A}{r}}
\FlagsADDr
\OpCode{10}{000}{\OCT{r}}
\Hex{..}{1}
\Cycles{1}{4}
\end{instruction}
\begin{instruction}{ADD A,n}
\Symbol{\SymADD{A}{n}}
\FlagsADDr
\OpCode{11}{000}{110}
\Hex{C6}{2}
\Cycles{2}{7}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{ADD A,(HL)}
\Symbol{\SymADD{A}{(HL)}}
\FlagsADDr
\OpCode{10}{000}{110}
\Hex{86}{1}
\Cycles{2}{7}
\end{instruction}
\begin{instruction}{ADD A,(IX+d)}
\Symbol{\SymADD{A}{(IX+d)}}
\FlagsADDr
\OpCode{11}{011}{101}
\Hex{DD}{3}
\Cycles{5}{19}
\SkipToOpCode
\OpCode{10}{000}{110}
\Hex{86}{}
\SkipToOpCode
\OpRange{d}
\Hex{..}{}
\end{instruction}
\begin{instruction}{ADD A,(IY+d)}
\Symbol{\SymADD{A}{(IY+d)}}
\FlagsADDr
\OpCode{11}{111}{101}
\Hex{FD}{3}
\Cycles{5}{19}
\SkipToOpCode
\OpCode{10}{000}{110}
\Hex{86}{}
\SkipToOpCode
\OpRange{d}
\Hex{..}{}
\end{instruction}
\begin{instruction}{ADD HL,rr}
\Symbol{\SymADD{HL}{rr}}
\FlagsADDrr
\OpCode{00}{\OCT{rr}1}{001}
\Hex{..}{1}
\Cycles{3}{11}
\end{instruction}
\begin{instruction}{ADD IX,rr}
\Symbol{\SymADD{IX}{rr}}
\FlagsADDrr
\OpCode{11}{011}{101}
\Hex{DD}{2}
\Cycles{4}{15}
\SkipToOpCode
\OpCode{00}{\OCT{rr}1}{001}
\Hex{..}{}
\end{instruction}
\begin{instruction}{ADD IY,rr}
\Symbol{\SymADD{IY}{rr}}
\FlagsADDrr
\OpCode{11}{111}{101}
\Hex{FD}{2}
\Cycles{4}{15}
\SkipToOpCode
\OpCode{00}{\OCT{rr}1}{001}
\Hex{..}{}
\end{instruction}
\begin{instruction}{ADD rr,A\ZXNS}
\Symbol{\SymADD{rr}{A}}
\FlagsADDrra
\OpCode{11}{101}{101}
\Hex{ED}{2}
\Cycles{2}{8}
\SkipToOpCode
\OpCode{00}{110}{0\OCT{rr}}
\Hex{..}{}
\end{instruction}
\begin{instruction}{ADD rr,nm\ZXNS}
\Symbol{\SymADD{rr}{nm}}
\FlagsADDrrnn
\OpCode{11}{101}{101}
\Hex{ED}{2}
\Cycles{4}{16}
\SkipToOpCode
\OpCode{00}{110}{1\OCT{rr}}
\Hex{..}{}
\SkipToOpCode
\OpRange{m}
\Hex{..}{}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\EmptySeparator
%-------------------------------------------
\begin{instruction}{AND A,r}
\Symbol{\SymAND{r}}
\FlagsANDr
\OpCode{10}{100}{\OCT{r}}
\Hex{..}{1}
\Cycles{1}{4}
\end{instruction}
\begin{instruction}{AND A,n}
\Symbol{\SymAND{n}}
\FlagsANDr
\OpCode{11}{100}{110}
\Hex{E6}{2}
\Cycles{2}{7}
\SkipToOpCode
\OpRange{n}
\Hex{..}{}
\end{instruction}
\begin{instruction}{AND A,(HL)}
\Symbol{\SymAND{(HL)}}
\FlagsANDr
\OpCode{10}{100}{110}
\Hex{A6}{}
\Cycles{2}{7}
\end{instruction}
\begin{instruction}{AND A,(IX+d)}
\Symbol{\SymAND{(IX+d)}}
\FlagsANDr
\OpCode{11}{011}{101}
\Hex{DD}{3}
\Cycles{5}{19}
\SkipToOpCode
\OpCode{10}{100}{110}
\Hex{A6}{}
\SkipToOpCode
\OpRange{d}
\Hex{..}{}
\end{instruction}
\begin{instruction}{AND A,(IY+d)}
\Symbol{\SymAND{(IY+d)}}
\FlagsANDr
\OpCode{11}{111}{101}
\Hex{FD}{3}
\Cycles{5}{19}
\SkipToOpCode
\OpCode{10}{100}{110}
\Hex{A6}{}
\SkipToOpCode
\OpRange{d}
\Hex{..}{}
\end{instruction}
\end{instrtablesimple}
\vspace*{3ex} % ensure this table starts at the same height as the one on the odd page
\begin{instrtablesimple}
\begin{instruction}{BIT b,r}
\Symbol{\SymBIT{r}}
\FlagsBITr
\OpCode{11}{001}{011}
\Hex{CB}{2}
\Cycles{2}{8}
\SkipToOpCode
\OpCode{01}{\OCT{b}}{\OCT{r}}
\Hex{..}{}
\end{instruction}
\begin{instruction}{BIT b,(HL)}
\Symbol{\SymBIT{(HL)}}
\FlagsBITr
\OpCode{11}{001}{011}
\Hex{CB}{2}
\Cycles{3}{12}
\SkipToOpCode
\OpCode{01}{\OCT{b}}{110}
\Hex{..}{}
\end{instruction}
\begin{instruction}{BIT b,(IX+d)}
\Symbol{\SymBIT{(IX+d)}}
\FlagsBITr
\OpCode{11}{011}{101}
\Hex{DD}{4}
\Cycles{5}{20}
\SkipToOpCode
\OpCode{11}{001}{011}
\Hex{CB}{}
\SkipToOpCode
\OpRange{d}
\Hex{..}{}
\SkipToOpCode
\OpCode{01}{\OCT{b}}{110}
\Hex{..}{}
\end{instruction}
\begin{instruction}{BIT b,(IY+d)}
\Symbol{\SymBIT{(IY+d)}}
\FlagsBITr
\OpCode{11}{111}{101}
\Hex{FD}{4}
\Cycles{5}{20}
\SkipToOpCode
\OpCode{11}{001}{011}
\Hex{CB}{}
\SkipToOpCode
\OpRange{d}
\Hex{..}{}
\SkipToOpCode
\OpCode{01}{\OCT{b}}{110}
\Hex{..}{}
\end{instruction}
\EmptySeparator
%-------------------------------------------
\begin{instruction}{BRLC DE,B\ZXNS}
\Symbol{\SymBRLC[0]}
\FlagsBRLC
\OpCode{11}{101}{101}
\Hex{ED}{2}
\Cycles{2}{8}
\SkipToSymbol
\Symbol{\SymBRLC[1]}
\FromSymbolToOpCode
\OpCode{00}{101}{100}
\Hex{2C}{}
\end{instruction}
\begin{instruction}{BSLA DE,B\ZXNS}
\Symbol{\SymBSLA[0]}
\FlagsBSLA
\OpCode{11}{101}{101}
\Hex{ED}{2}
\Cycles{2}{8}
\SkipToOpCode
\OpCode{00}{101}{000}
\Hex{28}{}
\end{instruction}
\begin{instruction}{BSRA DE,B\ZXNS}
\SymbolS{\SymBSRA[0]}
\FlagsBSRA
\OpCode{11}{101}{101}
\Hex{ED}{2}
\Cycles{2}{8}
\SkipToSymbol
\SymbolP{\SymBSRA[1]}
\FromSymbolToOpCode
\OpCode{00}{101}{001}
\Hex{29}{}
\end{instruction}
\begin{instruction}{BSRL DE,B\ZXNS}
\SymbolS{\SymBSRL[0]}
\FlagsBSRL
\OpCode{11}{101}{101}
\Hex{ED}{2}
\Cycles{2}{8}
\SkipToSymbol
\SymbolP{\SymBSRL[1]}
\FromSymbolToOpCode
\OpCode{00}{101}{010}
\Hex{2A}{}
\end{instruction}
\begin{instruction}{BSRF DE,B\ZXNS}
\SymbolS{\SymBSRF[0]}
\FlagsBSRF
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%-------------------------------------------
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%-------------------------------------------
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%-------------------------------------------
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%-------------------------------------------
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%-------------------------------------------
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%-------------------------------------------
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%-------------------------------------------
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gitextract_n515nfga/ ├── .gitignore ├── chapter-acknowledge.tex ├── chapter-bibliography.tex ├── chapter-copyright.tex ├── chapter-instr-close.tex ├── chapter-instr-glance-16bit-arithmetic.tex ├── chapter-instr-glance-16bit-load.tex ├── chapter-instr-glance-8bit-arithmetic.tex ├── chapter-instr-glance-8bit-load.tex ├── chapter-instr-glance-alphabetical.tex ├── chapter-instr-glance-bit.tex ├── chapter-instr-glance-block.tex ├── chapter-instr-glance-call-return.tex ├── chapter-instr-glance-exchange.tex ├── chapter-instr-glance-general.tex ├── chapter-instr-glance-input.tex ├── chapter-instr-glance-jump.tex ├── chapter-instr-glance-next.tex ├── chapter-instr-glance-output.tex ├── chapter-instr-glance-rotate-shift.tex ├── chapter-instr-glance-stack.tex ├── chapter-instr-glance.tex ├── chapter-instr-sorted-mnemonic.tex ├── chapter-instr-sorted-opcode.tex ├── chapter-introduction.tex ├── chapter-license.tex ├── chapter-next-copper.tex ├── chapter-next-dma.tex ├── chapter-next-interrupts.tex ├── chapter-next-keyboard.tex ├── chapter-next-layer2.tex ├── chapter-next-memory.tex ├── chapter-next-palette.tex ├── chapter-next-ports.tex ├── chapter-next-sound.tex ├── chapter-next-sprites.tex ├── chapter-next-tilemap.tex ├── chapter-next-ula.tex ├── chapter-next.tex ├── chapter-title.tex ├── chapter-toc.tex ├── chapter-z80.tex ├── defines-dma.tex ├── defines-instr-close.tex ├── defines.tex ├── instructions.tex ├── ports.tex ├── readme.md ├── samples/ │ ├── copper/ │ │ ├── .vscode/ │ │ │ ├── launch.json │ │ │ └── tasks.json │ │ ├── build/ │ │ │ └── .gitignore │ │ └── main.asm │ ├── im1/ │ │ ├── .vscode/ │ │ │ ├── launch.json │ │ │ └── tasks.json │ │ ├── build/ │ │ │ └── .gitignore │ │ └── main.asm │ ├── im2/ │ │ ├── .vscode/ │ │ │ ├── launch.json │ │ │ └── tasks.json │ │ ├── build/ │ │ │ └── .gitignore │ │ └── main.asm │ ├── im2hw/ │ │ ├── .vscode/ │ │ │ ├── launch.json │ │ │ └── tasks.json │ │ ├── build/ │ │ │ └── .gitignore │ │ └── main.asm │ ├── im2safe/ │ │ ├── .vscode/ │ │ │ ├── launch.json │ │ │ └── tasks.json │ │ ├── build/ │ │ │ └── .gitignore │ │ └── main.asm │ ├── layer2-256x192/ │ │ ├── .vscode/ │ │ │ ├── launch.json │ │ │ └── tasks.json │ │ ├── build/ │ │ │ └── .gitignore │ │ └── main.asm │ ├── layer2-320x256/ │ │ ├── .vscode/ │ │ │ ├── launch.json │ │ │ └── tasks.json │ │ ├── build/ │ │ │ └── .gitignore │ │ └── main.asm │ ├── layer2-640x256/ │ │ ├── .vscode/ │ │ │ ├── launch.json │ │ │ └── tasks.json │ │ ├── build/ │ │ │ └── .gitignore │ │ └── main.asm │ ├── sound/ │ │ ├── .vscode/ │ │ │ ├── launch.json │ │ │ └── tasks.json │ │ ├── build/ │ │ │ └── .gitignore │ │ └── main.asm │ ├── sprites/ │ │ ├── .vscode/ │ │ │ ├── launch.json │ │ │ └── tasks.json │ │ ├── build/ │ │ │ └── .gitignore │ │ ├── main.asm │ │ └── sprites.spr │ └── tilemap/ │ ├── .vscode/ │ │ ├── launch.json │ │ └── tasks.json │ ├── build/ │ │ └── .gitignore │ ├── main.asm │ ├── tiles.pal │ └── tiles.spr ├── setup.tex ├── tables.tex └── zx-next-dev-guide.tex
Condensed preview — 98 files, each showing path, character count, and a content snippet. Download the .json file or copy for the full structured content (1,191K chars).
[
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"path": ".gitignore",
"chars": 3357,
"preview": "## Ignored project files and folders\r\nTools\r\n\r\n## Core latex/pdflatex auxiliary files:\r\n*.ptc\r\n*.aux\r\n*.lof\r\n*.log\r\n*.lo"
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"path": "chapter-acknowledge.tex",
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"preview": "\\begingroup\r\n\r\n\t\\WorkInProgressFullScreen\r\n\r\n\r\n\t\\textbf{Acknowlegements}\r\n\r\n\tA lot of work has gone into this book. But "
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"preview": "\r\n% ████████████████████████████████████████████████████████████████████████████\r\n% █░░░░░░░░░░░░░░███░░░░░░░░░░█░░░░░░░"
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"path": "chapter-copyright.tex",
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"preview": "\\begingroup\r\n\t{\\WorkInProgressFullScreen}\r\n\r\n\t\\vspace*{\\fill} % render at the bottom of the page\r\n\r\n\t{\\Large\\textbf{\\Boo"
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"path": "chapter-instr-close.tex",
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"preview": "\\chapter{Instructions up Close}\r\n\\label{instruction_details}\r\n\r\n% ██████████████████████████████████████████████████████"
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"path": "chapter-instr-glance-16bit-arithmetic.tex",
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"preview": "\\section{16-Bit Arithmetic}\r\n\r\n\\vspace*{0.7ex} % ensure this table starts at the same height as the one on the odd page\r"
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"preview": "\\section{16-Bit Load}\r\n\r\n\\begin{instrtable}\r\n\r\n\t\\begin{instruction}{LD rr,nm} \r\n\t\t\\Symbol{\\SymLD{rr}{nm}}\r\n\t\t\t\\FlagsLDrr"
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"preview": "\\section{8-Bit Arithmetic and Logical}\r\n\r\n\\begin{minipage}{\\textwidth}\r\n\r\n\\begin{instrtable}\r\n\r\n\t\\begin{instruction}{ADD"
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"preview": "\\section{8-Bit Load}\r\n\r\n\\begin{instrtable}\t\r\n\r\n\t\\begin{instruction}{LD r,r'}\r\n\t\t\\Symbol{\\SymLD{r}{r'}}\r\n\t\t\t\\FlagsLDr\r\n\t\t"
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"preview": "% Alphabetical section only really makes sense for printed book; online PDF can be searched to get to specific instructi"
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"preview": "\\section{Bit Set, Reset and Test}\r\n\r\n\\begin{minipage}{\\textwidth}\r\n\r\n\\begin{instrtable}\r\n\r\n\t\\begin{instruction}{BIT b,r}"
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"preview": "\\section{Call and Return}\r\n\r\n\\vspace*{0.7ex} % ensure this table starts at the same height as the one on the odd page\r\n\\"
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"preview": "\\section{Exchange}\r\n\r\n\\begin{minipage}{\\textwidth}\r\n\t\r\n\\begin{instrtable}\t\r\n\r\n\t\\begin{instruction}{EX AF,AF'} \r\n\t\t\\Symbo"
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"preview": "\\section{General-Purpose Arithmetic and CPU Control}\r\n\r\n\\begin{minipage}{\\textwidth}\r\n\r\n\\begin{instrtable}\r\n\r\n\t\\begin{in"
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"preview": "\\section{Jump}\r\n\r\n\\begin{minipage}{\\textwidth}\r\n\t\r\n\\begin{instrtable}\r\n\r\n\t\\begin{instruction}{JP nm} \r\n\t\t\\Symbol{\\SymJP{"
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"preview": "\\section{ZX Spectrum Next Extended}\r\n\\label{zx_next_instructions_table}\r\n\r\n\\begin{minipage}{\\textwidth}\r\n\r\n\\begin{instrt"
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"preview": "\\section{Output}\r\n\r\n\\begin{minipage}{\\textwidth}\r\n\r\n\\begin{instrtable}\r\n\r\n\t\\begin{instruction}{OUT (n),A} \r\n\t\t\\Symbol{\\S"
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"preview": "\\section{Rotate and Shift}\r\n\r\n\\vspace*{0.7ex} % ensure this table starts at the same height as the one on the odd page\r\n"
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"preview": "\\section{Stack}\r\n\r\n\\begin{minipage}{\\textwidth}\r\n\t\r\n\\begin{instrtable}\r\n\r\n\t\\begin{instruction}{POP pp} \r\n\t\t\\Symbol{\\SymP"
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"preview": "\\chapter{Instructions at a Glance}\r\n\r\n% ████████████████████████████████████████████████████████████████████████████████"
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"preview": "\\chapter{Instructions Sorted by Mnemonic}\r\n\r\n% █████████████████████████████████████████████████████████████████████████"
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"preview": "\\chapter{Instructions Sorted by Opcode}\r\n\r\n% ███████████████████████████████████████████████████████████████████████████"
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"preview": "\\chapter{GNU Free Documentation License}\r\n\\label{gfdl}\r\n\r\n\r\n% ██████████████████████████████████████████\r\n% █░░░░░░█████"
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"path": "chapter-next-copper.tex",
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"preview": "\\section{Copper}\r\n\\label{zx_next_copper}\r\n\r\n% ──────────────────────────────────────────────────────────────────────────"
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"path": "chapter-next-dma.tex",
"chars": 52027,
"preview": "\\section{DMA}\r\n\\label{zx_next_dma}\r\n\r\n% ──────────────────────────────────────────────────────\r\n% ─████████████───██████"
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"path": "chapter-next-interrupts.tex",
"chars": 29441,
"preview": "\\section{Interrupts on Next}\r\n\\label{zx_next_interrupts}\r\n\r\n% ──────────────────────────────────────────────────────────"
},
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"path": "chapter-next-keyboard.tex",
"chars": 5408,
"preview": "\\section{Keyboard}\r\n\\label{zx_next_keyboard}\r\n\r\n% ───────────────────────────────────────────────────────────────────\r\n%"
},
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"path": "chapter-next-layer2.tex",
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"preview": "\\section{Layer 2}\r\n\\label{zx_next_layer2}\r\n\r\n% ───────────────────────────────\r\n% ─██████─────────██████████████─\r\n% ─██"
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"path": "chapter-next-memory.tex",
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"preview": "\\section{Memory Map and Paging}\r\n\\label{zx_next_memorypaging}\r\n\r\n% ─────────────────────────────────────────────────────"
},
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"path": "chapter-next-palette.tex",
"chars": 13137,
"preview": "\\section{Palette}\r\n\\label{zx_next_palette}\r\n\r\nNext greatly enhances ZX Spectrum video capabilities by offering several n"
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"path": "chapter-next-ports.tex",
"chars": 21514,
"preview": "\\section{Ports and Registers}\r\n\\label{zx_next_ports}\r\n\r\n% ──────────────────────────────────────────────────────────────"
},
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"path": "chapter-next-sound.tex",
"chars": 13037,
"preview": "\\section{Sound}\r\n\\label{zx_next_sound}\r\n\r\n% ────────────────────────────────────────────────────────────────────────────"
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"preview": "\\section{Sprites}\r\n\\label{zx_next_sprites}\r\n\r\n% ────────────────────────────────────────────────────────────────────────"
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"path": "chapter-next-tilemap.tex",
"chars": 17141,
"preview": "\\section{Tilemap}\r\n\\label{zx_next_tilemap}\r\n\r\n% ────────────────────────────────────────────────────────────────────────"
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"path": "chapter-next-ula.tex",
"chars": 13993,
"preview": "\\section{ULA Layer}\r\n\\label{zx_next_ula}\r\n\r\n% ──────────────────────────────────────────────\r\n% ─██████──██████─██████──"
},
{
"path": "chapter-next.tex",
"chars": 3219,
"preview": "\\chapter{ZX Spectrum Next}\r\n\r\n% █████████████████████████████████████████████████████████████████████████\r\n% █░░░░░░████"
},
{
"path": "chapter-title.tex",
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"preview": "% ████████████████████████████████████████████████████████████████████████\r\n% █░░░░░░░░░░░░░░█░░░░░░░░░░█░░░░░░░░░░░░░░█"
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{
"path": "chapter-toc.tex",
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"preview": "% ██████████████████████████████████████████████\r\n% █░░░░░░░░░░░░░░█░░░░░░░░░░░░░░█░░░░░░░░░░░░░░█\r\n% █░░▄▀▄▀▄▀▄▀▄▀░░█░░"
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"path": "chapter-z80.tex",
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"preview": "\\chapter{Zilog Z80}\r\n\r\n% ██████████████████████████████████████████████████\r\n% █░░░░░░░░░░░░░░░░░░█░░░░░░░░░░░░░░█░░░░░░"
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{
"path": "defines-dma.tex",
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{
"path": "defines-instr-close.tex",
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"preview": "% ───────────────────────────────────────────────────────────────────────────────────────\r\n% ─████████████───███████████"
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{
"path": "defines.tex",
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"preview": "\\newcommand*{\\isPDF}{1}\r\n\\newcommand*{\\isWIP}{1}\r\n\r\n\r\n% ░█▀▀█ ▒█▀▀█ ▒█▀▀▀█ ▒█░▒█ ▀▀█▀▀ \r\n% ▒█▄▄█ ▒█▀▀▄ ▒█░░▒█ ▒█░▒█ ░▒█░"
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{
"path": "instructions.tex",
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"preview": "% ──────────────────────────────────────────────────────────\r\n% ─██████████████─████████──████████─██████──────────█████"
},
{
"path": "ports.tex",
"chars": 9713,
"preview": "% ────────────────────────────────────────────────────────────────────────────────\n% ─██████████████─██████████████─████"
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"path": "readme.md",
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"preview": "# ZX Spectrum Next Assembly Developer Guide\r\n\r\nZX Spectrum Next is the successor of the Sinclair Spectrum line from the "
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{
"path": "samples/copper/.vscode/launch.json",
"chars": 2857,
"preview": "{\r\n\t// Use IntelliSense to learn about possible attributes.\r\n\t// Hover to view descriptions of existing attributes.\r\n\t//"
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{
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},
{
"path": "samples/copper/build/.gitignore",
"chars": 73,
"preview": "# Ignore everything in this directory\r\n*\r\n# Except this file\r\n!.gitignore"
},
{
"path": "samples/copper/main.asm",
"chars": 12462,
"preview": ";;--------------------------------------------------------------------\r\n;; sjasmplus setup\r\n;;--------------------------"
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{
"path": "samples/im1/.vscode/launch.json",
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"preview": "{\r\n\t// Use IntelliSense to learn about possible attributes.\r\n\t// Hover to view descriptions of existing attributes.\r\n\t//"
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"path": "samples/im1/.vscode/tasks.json",
"chars": 1090,
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{
"path": "samples/im1/build/.gitignore",
"chars": 73,
"preview": "# Ignore everything in this directory\r\n*\r\n# Except this file\r\n!.gitignore"
},
{
"path": "samples/im1/main.asm",
"chars": 4300,
"preview": ";;--------------------------------------------------------------------\r\n;; sjasmplus setup\r\n;;--------------------------"
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{
"path": "samples/im2/.vscode/launch.json",
"chars": 2857,
"preview": "{\r\n\t// Use IntelliSense to learn about possible attributes.\r\n\t// Hover to view descriptions of existing attributes.\r\n\t//"
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{
"path": "samples/im2/build/.gitignore",
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"preview": "# Ignore everything in this directory\r\n*\r\n# Except this file\r\n!.gitignore"
},
{
"path": "samples/im2/main.asm",
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"preview": ";;--------------------------------------------------------------------\r\n;; sjasmplus setup\r\n;;--------------------------"
},
{
"path": "samples/im2hw/.vscode/launch.json",
"chars": 2857,
"preview": "{\r\n\t// Use IntelliSense to learn about possible attributes.\r\n\t// Hover to view descriptions of existing attributes.\r\n\t//"
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},
{
"path": "samples/im2hw/build/.gitignore",
"chars": 73,
"preview": "# Ignore everything in this directory\r\n*\r\n# Except this file\r\n!.gitignore"
},
{
"path": "samples/im2hw/main.asm",
"chars": 6466,
"preview": ";;--------------------------------------------------------------------\r\n;; sjasmplus setup\r\n;;--------------------------"
},
{
"path": "samples/im2safe/.vscode/launch.json",
"chars": 2857,
"preview": "{\r\n\t// Use IntelliSense to learn about possible attributes.\r\n\t// Hover to view descriptions of existing attributes.\r\n\t//"
},
{
"path": "samples/im2safe/.vscode/tasks.json",
"chars": 1090,
"preview": "{\n\t\"version\": \"2.0.0\",\n\t\"tasks\": [\n\t\t{\n\t\t\t\"label\": \"Build\",\n\t\t\t\"type\": \"shell\",\n\t\t\t\"command\": \"${workspaceRoot}/../Tools"
},
{
"path": "samples/im2safe/build/.gitignore",
"chars": 73,
"preview": "# Ignore everything in this directory\r\n*\r\n# Except this file\r\n!.gitignore"
},
{
"path": "samples/im2safe/main.asm",
"chars": 5404,
"preview": ";;--------------------------------------------------------------------\r\n;; sjasmplus setup\r\n;;--------------------------"
},
{
"path": "samples/layer2-256x192/.vscode/launch.json",
"chars": 2857,
"preview": "{\r\n\t// Use IntelliSense to learn about possible attributes.\r\n\t// Hover to view descriptions of existing attributes.\r\n\t//"
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{
"path": "samples/layer2-256x192/.vscode/tasks.json",
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},
{
"path": "samples/layer2-256x192/build/.gitignore",
"chars": 73,
"preview": "# Ignore everything in this directory\r\n*\r\n# Except this file\r\n!.gitignore"
},
{
"path": "samples/layer2-256x192/main.asm",
"chars": 3263,
"preview": ";;--------------------------------------------------------------------\r\n;; sjasmplus setup\r\n;;--------------------------"
},
{
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"path": "samples/layer2-320x256/.vscode/tasks.json",
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},
{
"path": "samples/layer2-320x256/build/.gitignore",
"chars": 73,
"preview": "# Ignore everything in this directory\r\n*\r\n# Except this file\r\n!.gitignore"
},
{
"path": "samples/layer2-320x256/main.asm",
"chars": 3519,
"preview": ";;--------------------------------------------------------------------\r\n;; sjasmplus setup\r\n;;--------------------------"
},
{
"path": "samples/layer2-640x256/.vscode/launch.json",
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"preview": "{\r\n\t// Use IntelliSense to learn about possible attributes.\r\n\t// Hover to view descriptions of existing attributes.\r\n\t//"
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"path": "samples/layer2-640x256/.vscode/tasks.json",
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{
"path": "samples/layer2-640x256/build/.gitignore",
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"preview": "# Ignore everything in this directory\r\n*\r\n# Except this file\r\n!.gitignore"
},
{
"path": "samples/layer2-640x256/main.asm",
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"preview": ";;--------------------------------------------------------------------\r\n;; sjasmplus setup\r\n;;--------------------------"
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{
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},
{
"path": "samples/sound/build/.gitignore",
"chars": 73,
"preview": "# Ignore everything in this directory\r\n*\r\n# Except this file\r\n!.gitignore"
},
{
"path": "samples/sound/main.asm",
"chars": 4815,
"preview": ";;--------------------------------------------------------------------\r\n;; sjasmplus setup\r\n;;--------------------------"
},
{
"path": "samples/sprites/.vscode/launch.json",
"chars": 2857,
"preview": "{\r\n\t// Use IntelliSense to learn about possible attributes.\r\n\t// Hover to view descriptions of existing attributes.\r\n\t//"
},
{
"path": "samples/sprites/.vscode/tasks.json",
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},
{
"path": "samples/sprites/build/.gitignore",
"chars": 73,
"preview": "# Ignore everything in this directory\r\n*\r\n# Except this file\r\n!.gitignore"
},
{
"path": "samples/sprites/main.asm",
"chars": 5677,
"preview": ";;--------------------------------------------------------------------\r\n;; sjasmplus setup\r\n;;--------------------------"
},
{
"path": "samples/tilemap/.vscode/launch.json",
"chars": 2857,
"preview": "{\r\n\t// Use IntelliSense to learn about possible attributes.\r\n\t// Hover to view descriptions of existing attributes.\r\n\t//"
},
{
"path": "samples/tilemap/.vscode/tasks.json",
"chars": 1090,
"preview": "{\n\t\"version\": \"2.0.0\",\n\t\"tasks\": [\n\t\t{\n\t\t\t\"label\": \"Build\",\n\t\t\t\"type\": \"shell\",\n\t\t\t\"command\": \"${workspaceRoot}/../Tools"
},
{
"path": "samples/tilemap/build/.gitignore",
"chars": 73,
"preview": "# Ignore everything in this directory\r\n*\r\n# Except this file\r\n!.gitignore"
},
{
"path": "samples/tilemap/main.asm",
"chars": 5346,
"preview": ";;--------------------------------------------------------------------\r\n;; sjasmplus setup\r\n;;--------------------------"
},
{
"path": "samples/tilemap/tiles.spr",
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"preview": "DDDDA\"\"3C\"\"#C333DDDD\"3A\"\"#C\"33C3UUUUUUUPUU\u0005UUUUUUUUUPU\u0005UUUUUUUUUUUUUUgUUWwwUXvwUUuUVwweUxWUUUUUUUUUUgxUXwguWwwWgwUXwwuUX"
},
{
"path": "setup.tex",
"chars": 8488,
"preview": "% this must be included **after** defines.tex!\r\n\r\n% ▒█▀▀█ ░█▀▀█ ▒█▀▀█ ▒█░▄▀ ░█▀▀█ ▒█▀▀█ ▒█▀▀▀ ▒█▀▀▀█ \r\n% ▒█▄▄█ ▒█▄▄█ ▒█░"
},
{
"path": "tables.tex",
"chars": 19274,
"preview": "% ──────────────────────────────────────────────────────────────────────────────────────────────────────────────────────"
},
{
"path": "zx-next-dev-guide.tex",
"chars": 4351,
"preview": "\\documentclass[12pt,twoside,openright,a4paper]{book}\n\n\\usepackage{fancyhdr}\n\\usepackage{a4wide}\n\\usepackage{etoc}\n\\usepa"
}
]
// ... and 2 more files (download for full content)
About this extraction
This page contains the full source code of the tomaz/zx-next-dev-guide GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 98 files (913.9 KB), approximately 351.4k tokens. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.
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