[
{
"path": ".clang-format",
"content": "AccessModifierOffset: '-4'\nAllowShortFunctionsOnASingleLine: InlineOnly\nAllowShortIfStatementsOnASingleLine: Never\nBinPackArguments: 'false'\nBinPackParameters: 'false'\nBreakBeforeBraces: Allman\nBreakConstructorInitializers: AfterColon\nColumnLimit: '100'\nIndentWidth: '4'\nPackConstructorInitializers: CurrentLine\nPointerAlignment: Left\n"
},
{
"path": ".clang-tidy",
"content": "Checks: > \n clang-diagnostic-*,\n clang-analyzer-*,\n modernize-*,\n bugprone-*,\n concurrency-*,\n cppcoreguidelines-*,\n performance-*,\n portability-*,\n readability-*,\n -modernize-use-trailing-return-type,\n -readability-braces-around-statements,\n -readability-identifier-length,\n -readability-function-cognitive-complexity\nWarningsAsErrors: ''\nHeaderFilterRegex: ''\nAnalyzeTemporaryDtors: false\nFormatStyle: file\n"
},
{
"path": ".github/workflows/CI.yml",
"content": "name: Continuous Integration\n\non:\n push:\n branches: [ \"master\" ]\n pull_request:\n branches: [ \"master\" ]\n\nenv:\n # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.)\n BUILD_TYPE: Release\n\njobs:\n # Compile and test project on Linux based builds\n build-gcc:\n # The CMake configure and build commands are platform agnostic and should work equally well on Windows or Mac.\n # You can convert this to a matrix build if you need cross-platform coverage.\n # See: https://docs.github.com/en/free-pro-team@latest/actions/learn-github-actions/managing-complex-workflows#using-a-build-matrix\n runs-on: ubuntu-latest\n\n steps:\n - uses: actions/checkout@v4\n\n - name: Configure CMake\n # Configure CMake in a 'build' subdirectory. `CMAKE_BUILD_TYPE` is only required if you are using a single-configuration generator such as make.\n # See https://cmake.org/cmake/help/latest/variable/CMAKE_BUILD_TYPE.html?highlight=cmake_build_type\n run: cmake --preset ci-unix\n\n - name: Build\n run: cmake --build ${{github.workspace}}/build --config ${{env.BUILD_TYPE}} -j4\n\n - name: Test\n working-directory: ${{github.workspace}}/build\n # Execute tests defined by the CMake configuration. \n # See https://cmake.org/cmake/help/latest/manual/ctest.1.html for more detail\n run: ctest -C ${{env.BUILD_TYPE}}\n \n # Compile and test project on Linux based builds using clang\n build-clang:\n # The CMake configure and build commands are platform agnostic and should work equally well on Windows or Mac.\n # You can convert this to a matrix build if you need cross-platform coverage.\n # See: https://docs.github.com/en/free-pro-team@latest/actions/learn-github-actions/managing-complex-workflows#using-a-build-matrix\n runs-on: ubuntu-latest\n env:\n CC: clang\n CXX: clang++\n\n steps:\n - uses: actions/checkout@v4\n\n - name: Configure CMake\n # Configure CMake in a 'build' subdirectory. `CMAKE_BUILD_TYPE` is only required if you are using a single-configuration generator such as make.\n # See https://cmake.org/cmake/help/latest/variable/CMAKE_BUILD_TYPE.html?highlight=cmake_build_type\n run: cmake --preset ci-unix\n\n - name: Build\n run: cmake --build ${{github.workspace}}/build --config ${{env.BUILD_TYPE}} -j4\n\n - name: Test\n working-directory: ${{github.workspace}}/build\n # Execute tests defined by the CMake configuration. \n # See https://cmake.org/cmake/help/latest/manual/ctest.1.html for more detail\n run: ctest -C ${{env.BUILD_TYPE}}\n\n # Compile and test project on Windows based builds\n build-msvc:\n runs-on: windows-latest\n\n steps:\n - uses: actions/checkout@v4\n\n - name: Configure CMake\n # Configure CMake in a 'build' subdirectory.\n run: cmake --preset ci-msvc\n\n - name: Build\n run: cmake --build ${{github.workspace}}/build --config ${{env.BUILD_TYPE}} -j4\n\n - name: Test\n working-directory: ${{github.workspace}}/build\n # Execute tests defined by the CMake configuration. \n # See https://cmake.org/cmake/help/latest/manual/ctest.1.html for more detail\n run: ctest -C ${{env.BUILD_TYPE}}\n"
},
{
"path": ".gitignore",
"content": "# Prerequisites\n*.d\n\n# Compiled Object files\n*.slo\n*.lo\n*.o\n*.obj\n\n# Precompiled Headers\n*.gch\n*.pch\n\n# Compiled Dynamic libraries\n*.so\n*.dylib\n*.dll\n\n# Fortran module files\n*.mod\n*.smod\n\n# Compiled Static libraries\n*.lai\n*.la\n*.a\n*.lib\n\n# Executables\n*.exe\n*.app\n\n# Common project files\n.DS_Store\n.project\n.cproject\ncompile_commands.json\n.clangd/\n.vscode\n.idea\n\nbuild*/\nbin/\n*.swp\n.~*\ncmake-build-debug\ncmake-build-release\n.cache\n"
},
{
"path": "CMakeLists.txt",
"content": "# Copyright (c) 2022, Fraunhofer IESE\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions are\n# met:\n#\n# 1. Redistributions of source code must retain the above copyright notice,\n# this list of conditions and the following disclaimer.\n#\n# 2. Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in the\n# documentation and/or other materials provided with the distribution.\n#\n# 3. Neither the name of the copyright holder nor the names of its\n# contributors may be used to endorse or promote products derived from\n# this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\n# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER\n# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n# Author:\n# Thomas Psota\n# Marco Mörz\n\n#########################################\n### DRAMPower ###\n#########################################\ncmake_minimum_required(VERSION 3.22.0)\n\n# TODO change for release\nset(DRAMPOWER_VERSION_MAJOR 6)\nset(DRAMPOWER_VERSION_MINOR 0)\nset(DRAMPOWER_VERSION_PATCH 0)\nset(DRAMPOWER_VERSION_STRING \"${DRAMPOWER_VERSION_MAJOR}.${DRAMPOWER_VERSION_MINOR}.${DRAMPOWER_VERSION_PATCH}\")\nadd_compile_definitions(DRAMPOWER_VERSION_STRING=\"${DRAMPOWER_VERSION_STRING}\")\n\nset(PROJECT_NAME \"DRAMPower ${DRAMPOWER_VERSION_STRING}\")\nset(PROJECT_SHORTNAME \"DRAMPower\")\n\nproject(${PROJECT_NAME} VERSION ${DRAMPOWER_VERSION_MAJOR}.${DRAMPOWER_VERSION_MINOR}.${DRAMPOWER_VERSION_PATCH} LANGUAGES CXX)\n\nif(POLICY CMP0135)\n cmake_policy(SET CMP0135 NEW)\nendif()\n\n### CMake settings ###\nlist(APPEND CMAKE_MODULE_PATH \"${CMAKE_CURRENT_LIST_DIR}/cmake\")\ninclude(build_source_group)\ninclude(diagnostics_print)\ninclude(enable_clang_format)\ninclude(enable_clang_tidy)\ninclude(enable_cppcheck)\n\nif (PROJECT_IS_TOP_LEVEL)\n set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin)\n set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib)\n set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib)\nendif()\n\n# set_property(GLOBAL PROPERTY USE_FOLDERS ON)\nset(CMAKE_EXPORT_COMPILE_COMMANDS ON)\n\n### Project settings ###\nmessage(STATUS \"CMAKE_SOURCE_DIR: ${CMAKE_SOURCE_DIR}\")\nmessage(STATUS \"CMAKE_BINARY_DIR: ${CMAKE_BINARY_DIR}\")\nmessage(STATUS \"\" )\n\n### Build options ###\noption(DRAMPOWER_BUILD_CLI \"Build DRAMPower Command Line Tool\" ${PROJECT_IS_TOP_LEVEL})\noption(DRAMPOWER_BUILD_BENCHMARKS \"Build DRAMPower Command Line Tool\" OFF)\noption(DRAMPOWER_BUILD_TESTS \"Build DRAMPower unit tests\" OFF)\n\n### Compiler optimization settings ###\nif(PROJECT_IS_TOP_LEVEL)\n option(OPTIMIZE_FOR_NATIVE \"Build with -march=native (overrides CPU_TYPE if enabled)\" ON)\n set(CPU_TYPE \"\" CACHE STRING \"CPU type for -march=CPU_TYPE and -mtune=CPU_TYPE compile options\")\n # Set CPU_TYPE to native if OPTIMIZE_FOR_NATIVE is enabled\n if(OPTIMIZE_FOR_NATIVE)\n if(CPU_TYPE)\n message(NOTICE \"OPTIMIZE_FOR_NATIVE is enabled. Overriding CPU_TYPE from \\\"${CPU_TYPE}\\\" to \\\"native\\\".\")\n endif()\n set(CPU_TYPE \"native\")\n endif()\n\n # add CPU_TYPE to cmake cxx flags\n if(CPU_TYPE)\n set(CMAKE_CXX_FLAGS \"${CMAKE_CXX_FLAGS} -march=${CPU_TYPE} -mtune=${CPU_TYPE}\")\n endif()\nendif()\n\n# Use sane defaults for FetchContent:\n# In case we are the top-level project, get everything by default\n# In case we are included in another project, the user might want to provide their own system dependencies\noption(DRAMPOWER_USE_FETCH_CONTENT \"Enable the FetchContent module\" ${PROJECT_IS_TOP_LEVEL})\noption(DRAMPOWER_USE_FETCH_CONTENT_INTERNAL \"Enable FetchContent to provide internal dependencies\" ${DRAMPOWER_USE_FETCH_CONTENT})\noption(DRAMPOWER_USE_FETCH_CONTENT_CLI11 \"Enable FetchContent to provide CLI11\" ${DRAMPOWER_USE_FETCH_CONTENT})\noption(DRAMPOWER_USE_FETCH_CONTENT_SPDLOG \"Enable FetchContent to provide spdlog\" ${DRAMPOWER_USE_FETCH_CONTENT})\noption(DRAMPOWER_USE_FETCH_CONTENT_NLOHMANN_JSON \"Enable FetchContent to provide nlohmann json\" ${DRAMPOWER_USE_FETCH_CONTENT})\n\n### DRAMPower directories ###\nset(DRAMPOWER_SOURCE_DIR \"${CMAKE_CURRENT_SOURCE_DIR}/src\")\nset(DRAMPOWER_LIBRARY_DIR \"${CMAKE_CURRENT_SOURCE_DIR}/lib\")\nset(DRAMPOWER_TESTS_DIR \"${CMAKE_CURRENT_SOURCE_DIR}/tests\")\n\n###############################################\n### Library Settings ###\n###############################################\n\n### Detect OS threading library ###\nfind_package(Threads)\n\nif (DRAMPOWER_USE_FETCH_CONTENT)\n include(FetchContent)\n\n # nlohmann_json for DRAMUtils\n if (DRAMPOWER_USE_FETCH_CONTENT_NLOHMANN_JSON)\n FetchContent_Declare(nlohmann_json\n URL \"https://github.com/nlohmann/json/releases/download/v3.11.3/json.tar.xz\"\n OVERRIDE_FIND_PACKAGE\n )\n\n FetchContent_MakeAvailable(nlohmann_json)\n endif()\n\n # DRAMUtils\n if (DRAMPOWER_USE_FETCH_CONTENT_INTERNAL)\n FetchContent_Declare(\n DRAMUtils\n URL \"https://github.com/tukl-msd/DRAMUtils/archive/refs/tags/v1.12.1.tar.gz\"\n OVERRIDE_FIND_PACKAGE\n )\n\n FetchContent_MakeAvailable(DRAMUtils)\n endif()\n\n # cli11\n if (DRAMPOWER_USE_FETCH_CONTENT_CLI11 AND DRAMPOWER_BUILD_CLI)\n add_subdirectory(${DRAMPOWER_LIBRARY_DIR}/cli11)\n endif()\n\n # spdlog\n if (DRAMPOWER_USE_FETCH_CONTENT_SPDLOG AND (DRAMPOWER_BUILD_CLI OR DRAMPOWER_BUILD_BENCHMARKS))\n add_subdirectory(${DRAMPOWER_LIBRARY_DIR}/spdlog)\n endif()\nendif()\n\n###############################################\n### Source Directory ###\n###############################################\n\nadd_subdirectory(src/DRAMPower)\n\nif(DRAMPOWER_BUILD_CLI OR DRAMPOWER_BUILD_BENCHMARKS)\n add_subdirectory(src/cli)\nendif()\n\n###############################################\n### Test Directory ###\n###############################################\n\nif(DRAMPOWER_BUILD_TESTS)\n enable_testing()\n add_subdirectory(tests)\nendif()\n\n###############################################\n### Benchmark Directory ###\n###############################################\n\nif(DRAMPOWER_BUILD_BENCHMARKS)\n add_subdirectory(benches)\nendif()\n\n###############################################\n### Utility Projects ###\n###############################################\n\nif(${DRAMPOWER_UTILITY_PROJECTS})\n enable_clang_format()\n enable_clang_tidy()\n enable_cppcheck()\nendif()\n"
},
{
"path": "CMakePresets.json",
"content": "{\n\t\"version\": 3,\n\t\"cmakeMinimumRequired\": {\n\t\t\"major\": 3,\n\t\t\"minor\": 14,\n\t\t\"patch\": 0\n\t},\n\t\"configurePresets\": [\n\t\t{\n\t\t\t\"name\": \"cmake-pedantic\",\n\t\t\t\"hidden\": true,\n\t\t\t\"warnings\": {\n\t\t\t\t\"dev\": true,\n\t\t\t\t\"deprecated\": true,\n\t\t\t\t\"unusedCli\": true,\n\t\t\t\t\"systemVars\": false\n\t\t\t}\n\t\t},\n\t\t{\n\t\t\t\"name\": \"dev-mode\",\n\t\t\t\"hidden\": true,\n\t\t\t\"binaryDir\": \"${sourceDir}/build\",\n\t\t\t\"inherits\": \"cmake-pedantic\",\n\t\t\t\"cacheVariables\": {\n\t\t\t\t\"DRAMPOWER_BUILD_TESTS\": \"ON\",\n\t\t\t\t\"CMAKE_BUILD_PARALLEL_LEVEL\": \"\",\n\t\t\t\t\"DRAMPOWER_BUILD_CLI\": \"ON\",\n\t\t\t\t\"DRAMPOWER_BUILD_BENCHMARKS\": \"ON\"\n\t\t\t}\n\t\t},\n\t\t{\n\t\t\t\"name\": \"ci-common\",\n\t\t\t\"inherits\": [\n\t\t\t\t\"dev-mode\"\n\t\t\t],\n\t\t\t\"cacheVariables\": {\n\t\t\t\t\"CMAKE_BUILD_TYPE\": \"Release\"\n\t\t\t}\n\t\t},\n\t\t{\n\t\t\t\"name\": \"ci-unix\",\n\t\t\t\"generator\": \"Unix Makefiles\",\n\t\t\t\"inherits\": [\n\t\t\t\t\"ci-common\"\n\t\t\t]\n\t\t},\n\t\t{\n\t\t\t\"name\": \"ci-msvc\",\n\t\t\t\"generator\": \"Visual Studio 17 2022\",\n\t\t\t\"inherits\": [\n\t\t\t\t\"ci-common\"\n\t\t\t],\n\t\t\t\"cacheVariables\": {\n\t\t\t\t\"CMAKE_CXX_FLAGS\": \"/DWIN32 /D_WINDOWS /W3 /GR /EHsc /MP\"\n\t\t\t}\n\t\t},\n\t\t{\n\t\t\t\"name\": \"dev-unix\",\n\t\t\t\"generator\": \"Ninja\",\n\t\t\t\"binaryDir\": \"${sourceDir}/build\",\n\t\t\t\"inherits\": [\n\t\t\t\t\"dev-mode\"\n\t\t\t],\n\t\t\t\"cacheVariables\": {\n\t\t\t\t\"CMAKE_BUILD_TYPE\": \"Debug\",\n\t\t\t\t\"CMAKE_CXX_FLAGS\": \"-Wall -Wextra -Wpedantic\"\n\t\t\t}\n\t\t},\n\t\t{\n\t\t\t\"name\": \"dev-msvc\",\n\t\t\t\"generator\": \"Visual Studio 17 2022\",\n\t\t\t\"inherits\": [\n\t\t\t\t\"dev-mode\"\n\t\t\t],\n\t\t\t\"cacheVariables\": {\n\t\t\t\t\"CMAKE_CXX_FLAGS\": \"/DWIN32 /D_WINDOWS /W3 /GR /EHsc /MP\"\n\t\t\t}\n\t\t}\n\t]\n}"
},
{
"path": "LICENSE.txt",
"content": "Copyright (c) 2022, Technische Universität Kaiserslautern, Fraunhofer IESE\nAll rights reserved.\n\nThis software is released under the BSD 3-Clause License. \nBy using this software, the user implicitly agrees to the licensing terms.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are\nmet:\n\n1. Redistributions of source code must retain the above copyright notice,\n this list of conditions and the following disclaimer.\n\n2. Redistributions in binary form must reproduce the above copyright\n notice, this list of conditions and the following disclaimer in the\n documentation and/or other materials provided with the distribution.\n\n3. Neither the name of the copyright holder nor the names of its\n contributors may be used to endorse or promote products derived from\n this software without specific prior written permission.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n\"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\nTO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\nPURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER\nOR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\nEXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\nPROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\nPROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\nLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\nNEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\nSOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n"
},
{
"path": "README.md",
"content": "![\"DRAMPower](\"docs/images/logo_drampower_5_0.png\")
\n\n# DRAM Power Model (DRAMPower 6.0.0)\n\n- [Releases](#releases)\n- [Installation of the DRAMPower library](#installation-of-the-drampower-library)\n- [Installation of the DRAMPower Command Line application](#installation-of-the-drampower-command-line-application)\n- [Project structure](#project-structure)\n- [Dependencies](#dependencies)\n- [Usage of the DRAMPower library](#usage-of-the-drampower-library)\n- [Usage of the DRAMPower Command Line application](#usage-of-the-drampower-command-line-application)\n- [Memory Specifications](#memory-specifications)\n- [Variation-aware Power And Energy Estimation](#variation-aware-power-and-energy-estimation)\n- [Authors & Acknowledgment](#authors--acknowledgment)\n- [Contact Information](#contact-information)\n\n## Releases\nThe last official release can be found here: https://github.com/tukl-msd/DRAMPower/releases/tag/v6.0.0\n\nThe master branch of the repository should be regarded as the bleeding-edge version, which has all the latest features, but also all the latest bugs. Use at your own discretion.\n\n## Installation of the DRAMPower library\nCMake is required for the building of DRAMPower. If DRAMPower is the top level project DRAMPower fetches the required dependencies.\nIf DRAMPower is not the top level project, the dependencies have to be fetched manually, provided by the top level project or the DRAMPower library can fetch the dependencies. Fetching content is enabled by the following cmake flag:\n\n```console\n$ -D DRAMPOWER_USE_FETCH_CONTENT=Y\n```\n\nBy default DRAMPower fetches all dependencies if `DRAMPOWER_USE_FETCH_CONTENT` is enabled. If you want to disable the fetching of a specific dependency, you can set the respective flag to N. The following flags are available:\n- `DRAMPOWER_USE_FETCH_CONTENT_INTERNAL` Fetches the internal dependencies of DRAMPower (DRAMUtils)\n- `DRAMPOWER_USE_FETCH_CONTENT_SPDLOG` Fetches the spdlog library used by the command line application\n- `DRAMPOWER_USE_FETCH_CONTENT_CLI11` Fetches the CLI11 library used by the command line application\n- `DRAMPOWER_USE_FETCH_CONTENT_NLOHMANN_JSON` Fetches the nlohmann_json library used by DRAMUtils\n\nThe following cmake flags show an example of how to disable the fetching of the spdlog and CLI11 libraries:\n```console\n$ -D DRAMPOWER_USE_FETCH_CONTENT=Y -D DRAMPOWER_USE_FETCH_CONTENT_SPDLOG=N -D DRAMPOWER_USE_FETCH_CONTENT_CLI11=N\n```\n\nFor building DRAMPower clone the repository, or download the zip file of the release you would like to use and use CMake to generate the build files, e.g.\n\n```console\n$ cd DRAMPower\n$ cmake -S . -B build\n$ cmake --build build --parallel\n```\n\nOptionally, test cases can be built by toggling the `DRAMPOWER_BUILD_TESTS` flag with CMake.\n\n## Installation of the DRAMPower Command Line application\nThe command line application is automatically build if DRAMPower is the top level project (see [Installation of the DRAMPower library](#installation-of-the-drampower-library)).\nAlternatively, the `DRAMPOWER_BUILD_CLI` flag can be set to Y to force the build of the command line tool.\nClone the repository, or download the zip file of the release you would like to use and use CMake to generate the build files. The following commands force the build of the command line application:\n\n```console\n$ cd DRAMPower\n$ cmake -S . -B build -D DRAMPOWER_BUILD_CLI=Y\n$ cmake --build build\n```\n\n## Project structure\nThe project is structured in a library part, a (optional) test part and an (optional) Command Line application.\nIntegration of DRAMPower in other projects can be easily achieved by including it as a git submodule or by using the CMake FetchContent directive.\n\nThis repository contains the following sub-directoires\n\n DRAMPower # top directory\n └── cmake # cmake scripts used by configuration step\n ├── lib # contains bundled dependencies of the project\n ├── src # top level directory containing the actual sources\n ├── DRAMPower # source code of the actual DRAMPower library\n └── cli # the optional Command Line tool\n └── tests # test cases used by the project\n\n## Dependencies\nDRAMPower comes bundled with all necessary libraries and no installation of further system packages is required. DRAMPower uses the following libraries:\n - [DRAMUtils](https://github.com/tukl-msd/DRAMUtils)\n\nThe DRAMPower cli tool uses the following libraries:\n - DRAMPower\n - [DRAMUtils](https://github.com/tukl-msd/DRAMUtils)\n - [spdlog](https://github.com/gabime/spdlog/releases/tag/v1.9.2)\n - [CLI11 (CLI11 2.2 Copyright (c) 2017-2024 University of Cincinnati, developed by Henry Schreiner under NSF AWARD 1414736. All rights reserved.)](https://github.com/CLIUtils/CLI11/releases/tag/v2.4.2)\n\n## Usage of the DRAMPower library\n\nThe project is [FetchContent](https://cmake.org/cmake/help/latest/module/FetchContent.html) ready and can be easily included in any other CMake based project.\n\n```cmake\ninclude(FetchContent)\n\nFetchContent_Declare(\ndrampower\nGIT_REPOSITORY https://github.com/tukl-msd/DRAMPower\nGIT_TAG master)\nFetchContent_MakeAvailable(drampower)\n```\n\nThe library target DRAMPower is then available to the rest of the project and can be consumed by any other target, e.g.\n\n```cmake\nadd_executable(drampower_app ${SOURCE_FILES})\ntarget_link_libraries(drampower_app PRIVATE DRAMPower::DRAMPower)\n```\n\nAll constructs inside DRAMPower are exposed through the DRAMPower namespace.\nTherefore all the following examples will refer to them with the implied usage of their namespace.\n\n```cpp\nusing namespace DRAMPower;\n```\n\nTo use the actual DRAM calculations, first a memspec has to be supplied. Some example memspecs are supplied in the [tests directory](https://github.com/tukl-msd/DRAMPower/tree/master/tests/tests_drampower/resources). The values in the memspecs are in SI units.\nAn example snippet to initialize a DDR4 based DRAM spec can look like this (only the DRAMPower related includes are shown):\n\n```cpp\n#include \n#include \n#include \n\n// optional for simulation with toggling rates\n#include \n\n// Use DRAMUtils library to parse the memspec\nauto memspec = DRAMUtils::parse_memspec_from_file(\n std::filesystem::path(\"tests/tests_drampower/resources/ddr4.json\")\n);\nif (!memspec) {\n throw std::runtime_error(\"Could not parse memspec\");\n}\n// Make the DRAMPower specific memspec from the parsed memspec and initialize the DRAM\n// The next line can throw std::bad_variant_access if the memspec is not a DDR4 memspec\n// or an exception derived from std::exception if the json object is not valid\nDDR4 dram(MemSpecDDR4::from_memspec(*memspec));\n// Optionally use toggle rates if no data is available for the traces\n// dram.setToggleRate(DRAMUtils::Config::ToggleRateDefinition{\n// 0.5, // togglingRateRead 0.0 to 1.0\n// 0.5, // togglingRateWrite 0.0 to 1.0\n// 0.5, // dutyCycleRead 0.0 to 1.0\n// 0.5, // dutyCycleWrite 0.0 to 1.0\n// TogglingRateIdlePattern::H, // idlePatternRead H, L, Z\n// TogglingRateIdlePattern::H // idlePatternWrite H, L, Z\n// });\n```\n\nThe created DRAM simulator then has to be fed with commands, e.g.\n\n```cpp\n#include \n\n#define SZ_BITS(x) sizeof(x)*8\n\nuint8_t rd_data[] = {\n 0, 0, 0, 0, 0, 0, 0, 1,\n};\n\nstd::vector testPattern = {\n // {timestamp, commandtype, {bank_id, bank_group_id, rank_id, row_id}\n { 0, CmdType::ACT, {0, 0, 0, 0}},\n // {timestamp, commandtype, {bank_id, bank_group_id, rank_id, row_id, column_id}, data, data_size}\n { 15, CmdType::RD , {0, 0, 0, 0, 16}, rd_data, SZ_BITS(rd_data)},\n // optional for simulation with toggling rates (dram.setToggleRate() was called)\n // { 15, CmdType::RD , {0, 0, 0, 0, 16}, nullptr, 64}, \n { 35, CmdType::PRE, {0, 0, 0, 0}},\n { 45, CmdType::END_OF_SIMULATION },\n};\n\nfor (const auto& command : testPattern) {\n dram.doCoreInterfaceCommand(command);\n};\n```\n\nThe bank stats and energy calculations can then be accessed through their respective methods.\nIn the example energy_core holds the individual bank energy measures. total_energy_core holds the accumulated energy measures accessable through the energy type (e.g E_act, E_pre, E_RD, E_bg_act, E_bg_pre). total_core, total_interface and total_all hold the total energy measures for the core, interface and the sum of both as double values.\nAll values are returned in their respective SI units.\n\n```cpp\nauto stats = dram.getStats();\n\nstats.bank[0].counter.act; // 1;\nstats.bank[0].counter.reads; // 1;\nstats.bank[0].counter.pre; // 1;\nstats.rank_total[0].cycles.act; // 35;\nstats.rank_total[0].cycles.pre; // 10;\nstats.bank[0].cycles.act; // 35;\nstats.bank[0].cycles.pre; // 10;\n\n// Core energy\nauto energy_core = dram.calcCoreEnergy(dram.getLastCommandTime());\n// Interface energy\nauto energy_interface = dram.calcInterfaceEnergy(dram.getLastCommandTime());\n// Total energy with core and interface energy\n\n// Accummulated bank energy\n// Note: total_core_detailed.E_bg_act holds holds the accumulated backgound activation energy plus the shared background activation energy \nauto total_energy_core = energy_core.total_energy();\n\nenergy_core.bank_energy[0].E_act; // 1.7949519230769228e-10 J\ntotal_energy_core.E_act; // 1.7949519230769228e-10 J\n\nenergy_core.E_bg_act_shared; // 1.1832692307692309e-09 J\n\nenergy_core.bank_energy[0].E_bg_act; // 5.8052884615384527e-12 J\ntotal_energy_core.E_bg_act; // 1.1890745192307694e-09 J (5.8052884615384527e-12 J + 1.1832692307692309e-09 J)\n\ntotal_energy_core.E_pre; // 2.076923076923077e-10 J\nenergy_core.bank_energy[0].E_pre; // 2.076923076923077e-10 J\n\ntotal_energy_core.E_bg_pre; // 3.1153846153846144e-10 J\nenergy_core.bank_energy[0].E_bg_pre; // 1.9471153846153847e-11 J\n\ntotal_energy_core.E_RD; // 4.3569230769230762e-10 J\nenergy_core.bank_energy[0].E_RD; // 4.3569230769230762e-10 J\n\ndouble total_core = core_energy.total(); // 2.3234927884615384e-09 J\ndouble total_interface = interface_energy.total(); // 1.1102233846153846e-10 J\ndouble total_all = dram.getTotalEnergy(dram.getLastCommandTime()); // 2.4345151269230767e-09 J\n```\n\n## Usage of the DRAMPower Command Line application\n\nThe Command Line application can be built directly by setting the DRAMPOWER_BUILD_CLI flag with CMake (see [Installation Command Line application](#installation-command-line-application)).\nThe Command Line application can be used to calculate energy consumption of a DRAM memory using a command trace. The output can be printed to the console or written as a JSON file. The application needs the following arguments:\n\n- -m, --memspec (required): The path to the memory specification file (JSON format)\n- -c, --config (required): Configuration file for the Command Line application (JSON format)\n- -t, --trace (required): The path to the command trace file (CSV format) (see [tests directory](https://github.com/tukl-msd/DRAMPower/tree/master/tests/tests_drampower/resources))\n- -j, --json (optional): The path to the output JSON file (default: print to console) (the output JSON file must exist and will be overwritten)\n\nThe configuration file has the following format:\n\n```json\n{\n \"useToggleRate\": false, // true or false\n \"toggleRateConfig\": {\n \"togglingRateRead\": 0.5, // 0.0 to 1.0\n \"togglingRateWrite\": 0.5, // 0.0 to 1.0\n \"dutyCycleRead\": 0.5, // 0.0 to 1.0\n \"dutyCycleWrite\": 0.5, // 0.0 to 1.0\n \"idlePatternRead\": \"H\", // \"H\", \"L\" or \"Z\"\n \"idlePatternWrite\": \"H\" // \"H\", \"L\" or \"Z\"\n }\n}\n```\n\nThe Command Line application can be used as follows (in the following example the executable drampower_cli is located in the DRAMPower/build/bin directory):\n\n```console\n$ cd build/bin\n$ touch output.json\n$ touch config.json\n$ # The configuration file config.json must be filled with a valid configuration (see above)\n$ ./drampower_cli -c config.json -m ../../tests/tests_drampower/resources/ddr4.json -t ../../tests/tests_drampower/resources/ddr4.csv\n$ ./drampower_cli -c config.json -m ../../tests/tests_drampower/resources/ddr4.json -t ../../tests/tests_drampower/resources/ddr4.csv -j output.json\n```\n## Memory Specifications\n\nNote: The timing specifications in the JSONs are in clock cycles (cc). The current specifications for Reading and Writing do not include the I/O consumption. They are computed and included seperately. The IDD measures associated with different power supply sources of equal measure (VDD2, VDDCA and VDDQ). The current measures for dual-rank DIMMs reflect only the measures for the active rank. The default state of the idle rank is assumed to be the same as the complete memory state, for background power estimation. Accordingly, in all dual-rank memory specifications, IDD2P0 has been subtracted from the active currents and all background currents have been halved. They are also accounted for seperately by the power model. Stacking multiple Wide IO DRAM dies can also be captured by the nbrOfRanks parameter.\n\n## Variation-aware Power And Energy Estimation\n\n15 of the included datasheets reflect the impact of process-variations on DRAM currents for a selection of DDR3 memories manufactured at 50nm process technology. These memories include:\n(1) MICRON_128MB_DDR3-1066_8bit - revision G\n(2) MICRON_128MB_DDR3-1066_16bit - revision G\n(3) MICRON_128MB_DDR3-1600_8bit - revision G\n(4) MICRON_256MB_DDR3-1066_8bit - revision D\n(5) MICRON_256MB_DDR3-1600_16bit - revision D\n\nThe original vendor-provided datasheet current specifications are given in XMLs\nwithout suffixes such as _mu, _2s and _3s. XMLs including suffixes indicate that the\ncurrent measures are either: (1) typical (mu), or (2) include +2 sigma variation (2s),\nor (3) include +3 sigma variation (3s). These measures are derived based on the\nMonte-Carlo analysis performed on our SPICE-based DRAM cross-section.\n\nTo include these XMLs in your simulations, simply use them as the target memory.\n\n## Authors & Acknowledgment\n\nThe tool is based on the DRAM power model developed jointly by the Computer Engineering Research Group at TU Delft and the Electronic Systems Group at TU Eindhoven\nand verified by the Microelectronic System Design Research Group at TU Kaiserslautern with equivalent circuit-level simulations. This tool has been developed by\nKarthik Chandrasekar with Yonghui Li under the supervision of Dr. Benny Akesson and Prof. Kees Goossens. The IO and Termination Power measures have been employed\nfrom Micron's DRAM Power Calculator. If you decide to use DRAMPower in your research, please cite one of the following references:\n\n**To cite the DRAMPower Tool:**\n```\n[1] DRAMPower: Open-source DRAM Power & Energy Estimation Tool\nKarthik Chandrasekar, Christian Weis, Yonghui Li, Sven Goossens, Matthias Jung, Omar Naji, Benny Akesson, Norbert Wehn, and Kees Goossens\nURL: http://www.drampower.info\n```\n\n**To cite the DRAM power model:**\n```\n[2] \"Improved Power Modeling of DDR SDRAMs\"\nKarthik Chandrasekar, Benny Akesson, and Kees Goossens\nIn Proc. 14th Euromicro Conference on Digital System Design (DSD), 2011\n```\n\n**To cite the 3D-DRAM power model:**\n```\n[3] \"System and Circuit Level Power Modeling of Energy-Efficient 3D-Stacked Wide I/O DRAMs\"\nKarthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, and Kees Goossens\nIn Proc. Design, Automation and Test in Europe (DATE), 2013\n```\n\n**To cite variation-aware DRAM power estimation:**\n```\n[4] \"Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach\"\nKarthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, and Kees Goossens\nIn Proc. Design Automation Conference (DAC), 2013\n```\n\n## Contact Information\n\nFurther questions about the tool and the power model can be directed to:\n\nMatthias Jung (matthias.jung@iese.fraunhofer.de)\n\nFeel free to ask for updates to the tool's features and please do report any bugs\nand errors you encounter. This will encourage us to continuously improve the tool.\n\n## Disclaimer\n\nThe tool does not check the timing accuracy of the user's memory command trace\nand the use of commands and memory modes. It is expected that the user employs\na valid trace generated using a DRAM memory controller or simulator, which\nsatisfies all memory timing constraints and other requirements. The user DOES\nNOT get ANY WARRANTIES when using this tool. This software is released under the\nBSD 3-Clause License. By using this software, the user implicitly agrees to the\nlicensing terms.\n"
},
{
"path": "benches/CMakeLists.txt",
"content": "# Copyright (c) 2024, RPTU Kaiserslautern-Landau\n# All rights reserved.\n#\n# Redistribution and use in source and binary forms, with or without\n# modification, are permitted provided that the following conditions are\n# met:\n#\n# 1. Redistributions of source code must retain the above copyright notice,\n# this list of conditions and the following disclaimer.\n#\n# 2. Redistributions in binary form must reproduce the above copyright\n# notice, this list of conditions and the following disclaimer in the\n# documentation and/or other materials provided with the distribution.\n#\n# 3. Neither the name of the copyright holder nor the names of its\n# contributors may be used to endorse or promote products derived from\n# this software without specific prior written permission.\n#\n# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n# \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\n# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER\n# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n#\n# Authors:\n# Derek Christ\n# Marco Mörz\n\n###############################################\n### benches_drampower ###\n###############################################\n\noption(DRAMPOWER_USE_FETCH_CONTENT_GOOGLE_BENCHMARK \"Enable FetchContent to provide Google Benchmark\" ${DRAMPOWER_USE_FETCH_CONTENT})\n\nif(DRAMPOWER_USE_FETCH_CONTENT)\n if(DRAMPOWER_USE_FETCH_CONTENT_GOOGLE_BENCHMARK AND DRAMPOWER_BUILD_BENCHMARKS)\n set(BENCHMARK_ENABLE_TESTING OFF)\n\n FetchContent_Declare(\n benchmark\n URL \"https://github.com/google/benchmark/archive/refs/tags/v1.8.3.tar.gz\"\n OVERRIDE_FIND_PACKAGE\n )\n\n FetchContent_MakeAvailable(benchmark)\n endif()\nendif()\n\nfind_package(benchmark REQUIRED)\n\nadd_executable(benches_drampower\n main.cpp\n simulation.cpp\n)\ntarget_link_libraries(benches_drampower\n PRIVATE\n DRAMPower::DRAMPower\n DRAMPower::cli_lib\n DRAMUtils::DRAMUtils\n benchmark::benchmark\n)\n\ntarget_compile_definitions(benches_drampower PUBLIC DRAMPOWER_BENCHMARK_CONFIGS_DIR=\"${CMAKE_SOURCE_DIR}/tests/tests_drampower/resources\")\n"
},
{
"path": "benches/main.cpp",
"content": "/*\n * Copyright (c) 2023, RPTU Kaiserslautern-Landau\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are\n * met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n *\n * 3. Neither the name of the copyright holder nor the names of its\n * contributors may be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\n * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER\n * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n * Authors:\n * Derek Christ\n * Marco Mörz\n */\n\n#include \n\nint main(int argc, char** argv)\n{\n ::benchmark::Initialize(&argc, argv);\n ::benchmark::RunSpecifiedBenchmarks();\n return 0;\n}\n"
},
{
"path": "benches/simulation.cpp",
"content": "/*\n * Copyright (c) 2023, RPTU Kaiserslautern-Landau\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are\n * met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n *\n * 3. Neither the name of the copyright holder nor the names of its\n * contributors may be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\n * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER\n * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n * Authors:\n * Derek Christ\n * Marco Mörz\n */\n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n#include \n\nclass LPDDR4_Bench : public benchmark::Fixture\n{\npublic:\n\n using Command = DRAMPower::Command;\n using CmdType = DRAMPower::CmdType;\n using CommandList_t = std::vector>>;\n using BaseDDR_t = DRAMPower::dram_base;\n\n void SetUp(::benchmark::State&) {\n std::string memspecFile{DRAMPOWER_BENCHMARK_CONFIGS_DIR\"/lpddr4.json\"};\n std::string commandFile{DRAMPOWER_BENCHMARK_CONFIGS_DIR\"/lpddr4.csv\"};\n \n // Get dram\n // auto ddr = DRAMPower::CLI::getMemory(memspecFile, std::nullopt);\n auto memspeccontainer = DRAMUtils::parse_memspec_from_file(memspecFile);\n if(!memspeccontainer)\n {\n throw std::runtime_error(\"Failed to parse memspec from file\");\n }\n memspec = std::make_unique(DRAMPower::MemSpecLPDDR4::from_memspec(*memspeccontainer));\n\n // Parse command list\n if (!DRAMPower::DRAMPowerCLI::parse_command_list(commandFile, commandlist))\n {\n throw std::runtime_error(\"Failed to parse command list\");\n }\n }\n\n void TearDown(::benchmark::State&) {\n commandlist.clear();\n }\n std::unique_ptr memspec;\n CommandList_t commandlist;\n};\n\nBENCHMARK_DEFINE_F(LPDDR4_Bench, lpddr4PowerSimulation)(benchmark::State& state)\n{\n auto rdbuf = std::cout.rdbuf(nullptr);\n for (auto _ : state)\n {\n std::unique_ptr ddr = std::make_unique(*memspec);\n DRAMPower::DRAMPowerCLI::runCommands(ddr, commandlist);\n }\n std::cout.rdbuf(rdbuf);\n}\n\nBENCHMARK_REGISTER_F(LPDDR4_Bench, lpddr4PowerSimulation)->Unit(benchmark::kMicrosecond)->Iterations(10);\n\nBENCHMARK_DEFINE_F(LPDDR4_Bench, lpddr4PowerSimulationToggling)(benchmark::State& state)\n{\n auto rdbuf = std::cout.rdbuf(nullptr);\n for (auto _ : state)\n {\n auto trd = DRAMUtils::Config::ToggleRateDefinition{\n 0.5, // togglingRateRead\n 0.5, // togglingRateWrite\n 0.5, // dutyCycleRead\n 0.5, // dutyCycleWrite\n DRAMUtils::Config::TogglingRateIdlePattern::L, // idlePatternRead\n DRAMUtils::Config::TogglingRateIdlePattern::L // idlePatternWrite\n };\n std::unique_ptr ddr = std::make_unique(*memspec, DRAMPower::config::SimConfig{trd});\n DRAMPower::DRAMPowerCLI::runCommands(ddr, commandlist);\n }\n std::cout.rdbuf(rdbuf);\n}\n\nBENCHMARK_REGISTER_F(LPDDR4_Bench, lpddr4PowerSimulationToggling)->Unit(benchmark::kMicrosecond)->Iterations(10);"
},
{
"path": "cmake/build_source_group.cmake",
"content": "###############################################\n### build_source_group ###\n###############################################\n###\n### Builds a source group from a set of files\n### for nicer display in IDEs\n###\n\nfunction( build_source_group )\n\tfile(GLOB_RECURSE files ${CMAKE_CURRENT_SOURCE_DIR}/*.* )\n\tlist(REMOVE_ITEM files \"CMakeLists.txt\")\n\tsource_group(TREE ${CMAKE_CURRENT_SOURCE_DIR} PREFIX \"[src]\" FILES ${files})\nendfunction()"
},
{
"path": "cmake/diagnostics_print.cmake",
"content": "###############################################\n### diagnostics_print ###\n###############################################\n###\n### Prints different diagnostics and infos\n### about the specified target\n###\n\nfunction( diagnostics_print target_name )\t\n\tmessage(STATUS \"${target_name} settings:\")\n\tmessage(STATUS \"==============\\n\")\n\n\tmessage(STATUS \"Source Files:\")\n\tget_target_property(SOURCE_FILES ${target_name} SOURCES)\n\tif(SOURCE_FILES)\n\t\tmessage(STATUS \"${SOURCE_FILES}\")\n\tendif()\n\t\n\tmessage(STATUS \"\\nInclude Directories:\")\n\tget_target_property(HEADER_DIR ${target_name} INCLUDE_DIRECTORIES)\n\tif(HEADER_DIR)\n\t\tmessage(STATUS \"${HEADER_DIR}\")\n\tendif()\n\t\n\tmessage(STATUS \"\\nLink Libraries:\")\n\tget_target_property(LINKED_LIBS ${target_name} LINK_LIBRARIES)\n\tif(LINKED_LIBS)\n\t\tmessage(STATUS \"${LINKED_LIBS}\")\n\tendif()\n\t\t\n\tmessage(STATUS \"\\n\")\nendfunction()"
},
{
"path": "cmake/enable_clang_format.cmake",
"content": "###############################################\n### enable_clang_format ###\n###############################################\n###\n### Enables a clang-format target, if\n### clang-format is installed, automatically\n### formatting all sources in the tree\n###\n\nfunction( enable_clang_format )\n\t\nendfunction()"
},
{
"path": "cmake/enable_clang_tidy.cmake",
"content": "###############################################\n### enable_clang_tidy ###\n###############################################\n###\n### Enables a clang-tidy target, if\n### clang-tidy is installed, to run static\n### code analysis on all sources\n###\n\nfunction( enable_clang_tidy )\n file(GLOB_RECURSE SOURCE_FILES src/*.c src/*.cpp src/*.cxx src/*.cc )\n file(GLOB_RECURSE HEADER_FILES src/*.h src/*.hpp src/*.hxx src/*.hh )\n\t\t\n\tfind_program(UTIL_TIDY_PATH clang-tidy)\n\tif(UTIL_TIDY_PATH)\n\t\tmessage(STATUS \"Using clang-tidy static-analysis: yes\")\n\t\tadd_custom_target(clang-tidy\n\t\t\tCOMMAND ${UTIL_TIDY_PATH} ${SOURCE_FILES} ${HEADER_FILES} -p=./ )\n\telse()\n\t\tmessage(STATUS \"Using clang-tidy static-analysis: no\")\n\tendif()\nendfunction()\n"
},
{
"path": "cmake/enable_cppcheck.cmake",
"content": "###############################################\n### enable_cppcheck ###\n###############################################\n###\n### Enables a cppcheck target, if\n### cppcheck is installed, to run static\n### analysis on all sources\n###\n\nfunction( enable_cppcheck )\n file(GLOB_RECURSE SOURCE_FILES src/*.c src/*.cpp src/*.cxx src/*.cc )\n file(GLOB_RECURSE HEADER_FILES src/*.h src/*.hpp src/*.hxx src/*.hh )\n\t\n\tfind_program(UTIL_CPPCHECK_PATH cppcheck)\n\tif(UTIL_CPPCHECK_PATH)\n\t\tmessage(STATUS \"Using cppcheck static-analysis: yes \")\n\t\tadd_custom_target(\n\t\t\t\tcppcheck\n\t\t\t\tCOMMAND ${UTIL_CPPCHECK_PATH}\n\t\t\t\t--enable=warning,performance,portability,information,missingInclude\n\t\t\t\t--language=c++\n\t\t\t\t--std=c++11\n\t\t\t\t--template=gcc\n\t\t\t\t--verbose\n\t\t\t\t--quiet\n\t\t\t\t${SOURCE_FILES} ${HEADER_FILES}\n\t\t)\n\telse()\n\t\tmessage(STATUS \"Using cppcheck static-analysis: no \")\n\tendif()\nendfunction()\n"
},
{
"path": "lib/cli11/CMakeLists.txt",
"content": "########################################\n### CLI11 ###\n########################################\n\n\nFetchContent_Declare(cli11\n URL \"https://github.com/CLIUtils/CLI11/archive/refs/tags/v2.4.2.tar.gz\"\n OVERRIDE_FIND_PACKAGE\n)\n\nFetchContent_MakeAvailable(cli11)"
},
{
"path": "lib/spdlog/CMakeLists.txt",
"content": "########################################\n### spdlog ###\n########################################\n\n\nFetchContent_Declare(spdlog\n URL \"https://github.com/gabime/spdlog/archive/refs/tags/v1.9.2.tar.gz\"\n OVERRIDE_FIND_PACKAGE\n)\n\nFetchContent_MakeAvailable(spdlog)"
},
{
"path": "src/DRAMPower/CMakeLists.txt",
"content": "########################################\n### DRAMPower ###\n########################################\n\nfind_package(DRAMUtils REQUIRED)\n\nadd_library(DRAMPower\n DRAMPower/command/Command.cpp\n DRAMPower/command/Pattern.cpp\n DRAMPower/data/energy.cpp\n DRAMPower/dram/Interface.cpp\n DRAMPower/dram/Rank.cpp\n DRAMPower/memspec/MemSpecDDR4.cpp\n DRAMPower/memspec/MemSpecDDR5.cpp\n DRAMPower/memspec/MemSpecLPDDR4.cpp\n DRAMPower/memspec/MemSpecLPDDR5.cpp\n DRAMPower/standards/ddr4/core_calculation_DDR4.cpp\n DRAMPower/standards/ddr4/DDR4.cpp\n DRAMPower/standards/ddr4/DDR4Core.cpp\n DRAMPower/standards/ddr4/DDR4Interface.cpp\n DRAMPower/standards/ddr4/interface_calculation_DDR4.cpp\n DRAMPower/standards/ddr5/core_calculation_DDR5.cpp\n DRAMPower/standards/ddr5/DDR5.cpp\n DRAMPower/standards/ddr5/DDR5Core.cpp\n DRAMPower/standards/ddr5/DDR5Interface.cpp\n DRAMPower/standards/ddr5/interface_calculation_DDR5.cpp\n DRAMPower/standards/lpddr4/core_calculation_LPDDR4.cpp\n DRAMPower/standards/lpddr4/LPDDR4.cpp\n DRAMPower/standards/lpddr4/LPDDR4Core.cpp\n DRAMPower/standards/lpddr4/LPDDR4Interface.cpp\n DRAMPower/standards/lpddr4/interface_calculation_LPDDR4.cpp\n DRAMPower/standards/lpddr5/core_calculation_LPDDR5.cpp\n DRAMPower/standards/lpddr5/LPDDR5.cpp\n DRAMPower/standards/lpddr5/LPDDR5Core.cpp\n DRAMPower/standards/lpddr5/LPDDR5Interface.cpp\n DRAMPower/standards/lpddr5/interface_calculation_LPDDR5.cpp\n DRAMPower/util/extensions.cpp\n)\n\ntarget_sources(DRAMPower\nPUBLIC\n FILE_SET api\nTYPE HEADERS\nFILES\n DRAMPower/Types.h\n DRAMPower/Exceptions.h\n\n DRAMPower/dram/dram_base.h\n\n DRAMPower/simconfig/simconfig.h\n\n DRAMPower/command/Command.h\n DRAMPower/data/energy.h\n DRAMPower/data/stats.h\n\n DRAMPower/util/extension_manager.h\n DRAMPower/util/extensions.h\n \n DRAMPower/memspec/MemSpec.h\n\n DRAMPower/memspec/MemSpecDDR4.h\n DRAMPower/standards/ddr4/DDR4.h\n DRAMPower/standards/ddr4/DDR4Core.h\n DRAMPower/standards/ddr4/DDR4Interface.h\n DRAMPower/standards/ddr4/core_calculation_DDR4.h\n DRAMPower/standards/ddr4/interface_calculation_DDR4.h\n DRAMPower/standards/ddr4/types.h\n \n DRAMPower/memspec/MemSpecDDR5.h\n DRAMPower/standards/ddr5/DDR5.h\n DRAMPower/standards/ddr5/DDR5Core.h\n DRAMPower/standards/ddr5/DDR5Interface.h\n DRAMPower/standards/ddr5/core_calculation_DDR5.h\n DRAMPower/standards/ddr5/interface_calculation_DDR5.h\n DRAMPower/standards/ddr5/types.h\n \n DRAMPower/memspec/MemSpecLPDDR4.h\n DRAMPower/standards/lpddr4/LPDDR4.h\n DRAMPower/standards/lpddr4/LPDDR4Core.h\n DRAMPower/standards/lpddr4/LPDDR4Interface.h\n DRAMPower/standards/lpddr4/core_calculation_LPDDR4.h\n DRAMPower/standards/lpddr4/interface_calculation_LPDDR4.h\n DRAMPower/standards/lpddr4/types.h\n \n DRAMPower/memspec/MemSpecLPDDR5.h\n DRAMPower/standards/lpddr5/LPDDR5.h\n DRAMPower/standards/lpddr5/LPDDR5Core.h\n DRAMPower/standards/lpddr5/LPDDR5Interface.h\n DRAMPower/standards/lpddr5/core_calculation_LPDDR5.h\n DRAMPower/standards/lpddr5/interface_calculation_LPDDR5.h\n DRAMPower/standards/lpddr5/types.h\n \n DRAMPower/util/Serialize.h\n DRAMPower/util/Deserialize.h\n)\n\ntarget_include_directories(DRAMPower PUBLIC ${CMAKE_CURRENT_SOURCE_DIR})\n\ntarget_compile_features(DRAMPower PUBLIC cxx_std_17)\nset_target_properties(DRAMPower PROPERTIES CXX_EXTENSIONS OFF)\nset_target_properties(DRAMPower PROPERTIES CXX_STANDARD_REQUIRED ON)\n\ntarget_link_libraries(DRAMPower\nPUBLIC \n DRAMUtils::DRAMUtils\n)\n\n# Add test functions\nif(DRAMPOWER_BUILD_TESTS)\n target_compile_definitions(DRAMPower PUBLIC DRAMPOWER_TESTING)\nendif()\n\nadd_library(DRAMPower::DRAMPower ALIAS DRAMPower)\n\ninstall(TARGETS DRAMPower FILE_SET api)\n"
},
{
"path": "src/DRAMPower/DRAMPower/Exceptions.h",
"content": "#ifndef DRAMPOWER_EXCEPTIONS_H\n#define DRAMPOWER_EXCEPTIONS_H\n\n#include \n#include \n\n\nnamespace DRAMPower {\n\nclass Exception : public std::exception {\n// protected constructors\nprotected:\n\n// public constructors\npublic:\n // Constructors with message\n explicit Exception(const std::string &message) : m_message(message) {}\n explicit Exception(std::string &&message) : m_message(std::move(message)) {}\n \n // Exception without message should not be allowed\n Exception() = delete;\n \n // Copy and move constructors and assignment operators\n Exception(const Exception &other) = default;\n Exception &operator=(const Exception &other) = default;\n Exception(Exception &&other) = default;\n Exception &operator=(Exception &&other) = default;\n\n // Destructor\n virtual ~Exception() noexcept = default;\n\n// Public member functions\npublic:\n const char *what() const noexcept override {\n return m_message.c_str();\n }\n\n// Private member variables\nprivate:\n std::string m_message;\n};\n\n} // namespace DRAMPower\n\n#endif /* DRAMPOWER_EXCEPTIONS_H */\n"
},
{
"path": "src/DRAMPower/DRAMPower/Types.h",
"content": "#ifndef DRAMPOWER_TYPES_H\n#define DRAMPOWER_TYPES_H\n\n#include \n\n#include \n\nnamespace DRAMPower {\n\nusing timestamp_t = uint64_t;\nusing interval_t = util::interval_counter;\n\n}\n\n#endif /* DRAMPOWER_TYPES_H */\n"
},
{
"path": "src/DRAMPower/DRAMPower/command/CmdType.h",
"content": "#ifndef DRAMPOWER_COMMAND_CMDTYPE_H\n#define DRAMPOWER_COMMAND_CMDTYPE_H\n\n#include \n#include \n\nnamespace DRAMPower\n{\n\n// Taken from DRAM 4.0\n//\t\t\t\t\t\t\t\t\t\t\t\tDRAMSys \n//\t\t\t\t\t\t\t\t\t\t\t\t\\\t\\__> DRAMPower\n//\t\t\t\t\t\t\t\t\t\t\t\t \\ \\_v\n//\t\t\t\t\t\t\t\t\t\t\t\t \\_______> DRAMCommon\t\nenum class CmdType {\n\tNOP = 0, \t\t\t// 0\n\tRD, \t\t\t\t// 1\n\tWR, \t\t\t\t// 2\n\tRDA, \t\t\t\t// 3\n\tWRA, \t\t\t\t// 4\n\tACT, \t\t\t\t// 5\n\tPRE, \t\t\t\t// 6\n\tREFB, \t\t\t\t// 7\n\tREFP2B,\t\t\t\t\t// 8\n\tPRESB, \t\t\t\t// 9\n\tREFSB, \t\t\t\t// 10\n\tPREA, \t\t\t\t// 11\n\tREFA, \t\t\t\t// 12\n\tPDEA, \t\t\t\t// 13\n\tPDEP, \t\t\t\t// 14\n\tPDXA, \t\t\t\t// 15\n\tPDXP, \t\t\t\t// 16\n\tSREFEN, \t\t\t\t// 17\n\tSREFEX, \t\t\t\t// 18\n\tDSMEN,\t\t\t\t\t// 19\n\tDSMEX,\t\t\t\t\t// 20\n\tEND_OF_SIMULATION,\t\t// 21\n\tCOUNT,\t\t\t\t\t// 22\n};\n\nnamespace CmdTypeUtil\n{\n\tconstexpr bool needs_data(CmdType cmd)\n\t{\n\t\tswitch (cmd)\n\t\t{\n\t\tcase CmdType::RD:\n\t\tcase CmdType::RDA:\n\t\tcase CmdType::WR:\n\t\tcase CmdType::WRA:\n\t\t\treturn true;\n\t\tdefault:\n\t\t\treturn false;\n\t\t};\n\t};\n\n\tconstexpr CmdType from_string(const std::string_view& str)\n\t{\n\t\tif (str == \"NOP\")\n\t\t\treturn CmdType::NOP;\n\t\tif (str == \"ACT\")\n\t\t\treturn CmdType::ACT;\n\t\tif (str == \"PRE\")\n\t\t\treturn CmdType::PRE;\n\t\tif (str == \"PREA\")\n\t\t\treturn CmdType::PREA;\n\t\tif (str == \"PRESB\")\n\t\t\treturn CmdType::PRESB;\n\t\tif (str == \"REFA\")\n\t\t\treturn CmdType::REFA;\n\t\tif (str == \"REFB\")\n\t\t\treturn CmdType::REFB;\n\t\tif (str == \"REFSB\")\n\t\t\treturn CmdType::REFSB;\n\t\tif (str == \"REFP2B\")\n\t\t\treturn CmdType::REFP2B;\n\t\tif (str == \"RD\")\n\t\t\treturn CmdType::RD;\n\t\tif (str == \"RDA\")\n\t\t\treturn CmdType::RDA;\n\t\tif (str == \"WR\")\n\t\t\treturn CmdType::WR;\n\t\tif (str == \"WRA\")\n\t\t\treturn CmdType::WRA;\n\t\tif (str == \"PDEA\")\n\t\t\treturn CmdType::PDEA;\n\t\tif (str == \"PDEP\")\n\t\t\treturn CmdType::PDEP;\n\t\tif (str == \"PDXA\")\n\t\t\treturn CmdType::PDXA;\n\t\tif (str == \"PDXP\")\n\t\t\treturn CmdType::PDXP;\n\t\tif (str == \"SREFEN\")\n\t\t\treturn CmdType::SREFEN;\n\t\tif (str == \"SREFEX\")\n\t\t\treturn CmdType::SREFEX;\n\t\tif (str == \"DSMEN\")\n\t\t\treturn CmdType::DSMEN;\n\t\tif (str == \"DSMEX\")\n\t\t\treturn CmdType::DSMEX;\n\t\tif (str == \"END\")\n\t\t\treturn CmdType::END_OF_SIMULATION;\n\t\treturn CmdType::NOP;\n\t};\n\n\tconstexpr const char * to_string(CmdType cmd)\n\t{\n\t\tswitch (cmd)\n\t\t{\n\t\tcase CmdType::NOP:\n\t\t\treturn \"NOP\";\n\t\tcase CmdType::ACT:\n\t\t\treturn \"ACT\";\n\t\tcase CmdType::PRE:\n\t\t\treturn \"PRE\";\n\t\tcase CmdType::PREA:\n\t\t\treturn \"PREA\";\n\t\tcase CmdType::REFA:\n\t\t\treturn \"REFA\";\n\t\tcase CmdType::REFB:\n\t\t\treturn \"REFB\";\n\t\tcase CmdType::RD:\n\t\t\treturn \"RD\";\n\t\tcase CmdType::RDA:\n\t\t\treturn \"RDA\";\n\t\tcase CmdType::WR:\n\t\t\treturn \"WR\";\n\t\tcase CmdType::WRA:\n\t\t\treturn \"WRA\";\n\t\tcase CmdType::REFSB:\n\t\t\treturn \"REFSB\";\n\t\tcase CmdType::REFP2B:\n\t\t\treturn \"REFP2B\";\n\t\tcase CmdType::PRESB:\n\t\t\treturn \"PRESB\";\n\t\tcase CmdType::PDEA:\n\t\t\treturn \"PDEA\";\n\t\tcase CmdType::PDEP:\n\t\t\treturn \"PDEP\";\n\t\tcase CmdType::PDXA:\n\t\t\treturn \"PDXA\";\n\t\tcase CmdType::PDXP:\n\t\t\treturn \"PDXP\";\n\t\tcase CmdType::SREFEN:\n\t\t\treturn \"SREFEN\";\n\t\tcase CmdType::SREFEX:\n\t\t\treturn \"SREFEX\";\n\t\tcase CmdType::DSMEN:\n\t\t\treturn \"DSMEN\";\n\t\tcase CmdType::DSMEX:\n\t\t\treturn \"DSMEX\";\n\t\tcase CmdType::END_OF_SIMULATION:\n\t\t\treturn \"END_OF_SIMULATION\";\n\t\tdefault:\n\t\t\treturn \"to_string()\";\n\t\t}\n\t}\n\n\tinline std::ostream& operator<<(std::ostream& os, CmdType cmd) {\n\t\treturn os << to_string(cmd);\n\t}\n}\n}\n#endif /* DRAMPOWER_COMMAND_CMDTYPE_H */\n"
},
{
"path": "src/DRAMPower/DRAMPower/command/Command.cpp",
"content": "#include \"Command.h\"\n\nnamespace DRAMPower {\n\n TargetCoordinate::TargetCoordinate(std::size_t bank_id, std::size_t bank_group_id, std::size_t rank_id)\n : bank(bank_id), bankGroup(bank_group_id), rank(rank_id)\n {};\n\n TargetCoordinate::TargetCoordinate(std::size_t bank_id, std::size_t bank_group_id, std::size_t rank_id, std::size_t row_id)\n : bank(bank_id), bankGroup(bank_group_id), rank(rank_id), row(row_id)\n {};\n\n TargetCoordinate::TargetCoordinate(std::size_t bank_id, std::size_t bank_group_id, std::size_t rank_id, std::size_t row_id, std::size_t column_id)\n : bank(bank_id), bankGroup(bank_group_id), rank(rank_id), row(row_id), column(column_id)\n {};\n\n Command::Command(timestamp_t timestamp, CmdType type, TargetCoordinate targetCoord, const uint8_t * data, std::size_t sz_bits)\n : timestamp(timestamp)\n , type(type)\n , targetCoordinate(targetCoord)\n , data(data)\n , sz_bits(sz_bits)\n {};\n\n} // namespace DRAMPower"
},
{
"path": "src/DRAMPower/DRAMPower/command/Command.h",
"content": "#ifndef DRAMPOWER_COMMAND_COMMAND_H\n#define DRAMPOWER_COMMAND_COMMAND_H\n\n#include \n#include \n\n#include \n\nnamespace DRAMPower {\n\nstruct TargetCoordinate {\n std::size_t bank = 0;\n std::size_t bankGroup = 0;\n std::size_t rank = 0;\n\tstd::size_t row = 0;\n\tstd::size_t column = 0;\n\n\tTargetCoordinate() = default;\n\tTargetCoordinate(std::size_t bank_id, std::size_t bank_group_id, std::size_t rank_id);\n\tTargetCoordinate(std::size_t bank_id, std::size_t bank_group_id, std::size_t rank_id, std::size_t row_id);\n\tTargetCoordinate(std::size_t bank_id, std::size_t bank_group_id, std::size_t rank_id, std::size_t row_id, std::size_t column_id);\n};\n\nclass Command {\npublic:\n Command() = default;\n\tCommand(timestamp_t timestamp, CmdType type, TargetCoordinate targetCoord = {}, const uint8_t * data = nullptr, std::size_t sz_bits = 0);\n\npublic:\n timestamp_t timestamp = 0;\n CmdType type;\n TargetCoordinate targetCoordinate;\n\n\n const uint8_t * data = 0x00;\n\tstd::size_t sz_bits;\n //uint64_t burstLength;\npublic:\n};\n\n}\n\n#endif /* DRAMPOWER_COMMAND_COMMAND_H */\n"
},
{
"path": "src/DRAMPower/DRAMPower/command/Pattern.cpp",
"content": "#include \"Pattern.h\"\n#include \n#include \n#include \n\nnamespace DRAMPower {\n\n PatternEncoderOverrides::PatternEncoderOverrides(std::initializer_list _settings)\n {\n for (const auto &setting : _settings)\n {\n this->settings.emplace(setting.descriptor, setting.bitSpec);\n }\n }\n\n void PatternEncoderOverrides::updateSettings(std::initializer_list _settings)\n {\n // Update settings if descriptor is already present\n for (const auto &setting : _settings)\n {\n this->settings[setting.descriptor] = setting.bitSpec;\n }\n }\n\n std::unordered_map PatternEncoderOverrides::getSettings()\n {\n return this->settings;\n }\n \n const std::unordered_map& PatternEncoderOverrides::getSettings() const {\n return this->settings;\n }\n\n PatternEncoderBitSpec PatternEncoderOverrides::getSetting(pattern_descriptor::t descriptor)\n {\n if (this->settings.find(descriptor) != this->settings.end())\n {\n return this->settings.at(descriptor);\n }\n return PatternEncoderBitSpec::INVALID;\n }\n\n bool PatternEncoderOverrides::hasSetting(pattern_descriptor::t descriptor)\n {\n return this->settings.find(descriptor) != this->settings.end();\n }\n\n bool PatternEncoderOverrides::removeSetting(pattern_descriptor::t descriptor)\n {\n return this->settings.erase(descriptor) > 0;\n }\n\n PatternEncoder::PatternEncoder(PatternEncoderOverrides settings)\n : settings(settings) \n {}\n\n inline bool PatternEncoder::applyBitSpec(\n PatternEncoderOverrides &spec,\n pattern_descriptor::t descriptor,\n bool LAST_BIT,\n bool default_bit\n )\n {\n auto setting = spec.getSetting(descriptor);\n switch (setting)\n {\n case PatternEncoderBitSpec::L:\n return false;\n case PatternEncoderBitSpec::H:\n return true;\n case PatternEncoderBitSpec::LAST_BIT:\n return LAST_BIT;\n case PatternEncoderBitSpec::INVALID:\n return default_bit;\n default:\n assert(false);\n break;\n }\n return false;\n }\n\n uint64_t PatternEncoder::encode(const Command& cmd, const std::vector& pattern, const uint64_t lastpattern)\n {\n return encode(cmd.targetCoordinate, pattern, lastpattern);\n }\n\n uint64_t PatternEncoder::encode(const TargetCoordinate& targetCoordinate, const std::vector& pattern, const uint64_t lastpattern)\n {\n using namespace pattern_descriptor;\n\n std::bitset<64> bitset(0);\n std::bitset<32> bank_bits(targetCoordinate.bank);\n std::bitset<32> row_bits(targetCoordinate.row);\n std::bitset<32> column_bits(targetCoordinate.column);\n std::bitset<32> bank_group_bits(targetCoordinate.bankGroup);\n\n std::size_t n = pattern.size() - 1;\n uint64_t opcodeshifter = 1;\n uint16_t opcodecount = 0;\n\n assert(n < 64);\n\n for (const auto descriptor : pattern) {\n // assert(n >= 0); // std::size_t is unsigned\n\n switch (descriptor) {\n case H:\n bitset[n] = true;\n break;\n case L:\n bitset[n] = false;\n break;\n\n // Command bits\n case BL:\n case CID0:\n case CID1:\n case CID2:\n case CID3:\n bitset[n] = applyBitSpec(settings, descriptor, ((lastpattern >> n) & 1) == 1, true);\n break;\n case V:\n case X:\n case AP:\n bitset[n] = applyBitSpec(settings, descriptor, ((lastpattern >> n) & 1) == 1, false);\n break;\n\n // Target Coordinate bits\n\n // Bank bits\n case BA0:\n bitset[n] = bank_bits[0];\n break;\n case BA1:\n bitset[n] = bank_bits[1];\n break;\n case BA2:\n bitset[n] = bank_bits[2];\n break;\n case BA3:\n bitset[n] = bank_bits[3];\n break;\n case BA4:\n bitset[n] = bank_bits[4];\n break;\n case BA5:\n bitset[n] = bank_bits[5];\n break;\n case BA6:\n bitset[n] = bank_bits[6];\n break;\n case BA7:\n bitset[n] = bank_bits[7];\n break;\n case BA8:\n bitset[n] = bank_bits[8];\n break;\n\n // BG bits\n case BG0:\n bitset[n] = bank_group_bits[0];\n break;\n case BG1:\n bitset[n] = bank_group_bits[1];\n break;\n case BG2:\n bitset[n] = bank_group_bits[2];\n break;\n\n case C0:\n bitset[n] = applyBitSpec(settings, descriptor, ((lastpattern >> n) & 1) == 1, column_bits[0]);\n break;\n case C1:\n bitset[n] = applyBitSpec(settings, descriptor, ((lastpattern >> n) & 1) == 1, column_bits[1]);\n break;\n case C2:\n bitset[n] = applyBitSpec(settings, descriptor, ((lastpattern >> n) & 1) == 1, column_bits[2]);\n break;\n case C3:\n bitset[n] = applyBitSpec(settings, descriptor, ((lastpattern >> n) & 1) == 1, column_bits[3]);\n break;\n case C4:\n bitset[n] = applyBitSpec(settings, descriptor, ((lastpattern >> n) & 1) == 1, column_bits[4]);\n break;\n case C5:\n bitset[n] = column_bits[5];\n break;\n case C6:\n bitset[n] = column_bits[6];\n break;\n case C7:\n bitset[n] = column_bits[7];\n break;\n case C8:\n bitset[n] = column_bits[8];\n break;\n case C9:\n bitset[n] = column_bits[9];\n break;\n case C10:\n bitset[n] = applyBitSpec(settings, descriptor, ((lastpattern >> n) & 1) == 1, column_bits[10]);\n break;\n case C11:\n bitset[n] = column_bits[C11];\n break;\n case C12:\n bitset[n] = column_bits[C12];\n break;\n case C13:\n bitset[n] = column_bits[C13];\n break;\n case C14:\n bitset[n] = column_bits[C14];\n break;\n case C15:\n bitset[n] = column_bits[C15];\n break;\n case C16:\n bitset[n] = column_bits[C16];\n break;\n // Row bits\n case R0:\n bitset[n] = row_bits[0];\n break;\n case R1:\n bitset[n] = row_bits[1];\n break;\n case R2:\n bitset[n] = row_bits[2];\n break;\n case R3:\n bitset[n] = row_bits[3];\n break;\n case R4:\n bitset[n] = row_bits[4];\n break;\n case R5:\n bitset[n] = row_bits[5];\n break;\n case R6:\n bitset[n] = row_bits[6];\n break;\n case R7:\n bitset[n] = row_bits[7];\n break;\n case R8:\n bitset[n] = row_bits[8];\n break;\n case R9:\n bitset[n] = row_bits[9];\n break;\n case R10:\n bitset[n] = row_bits[10];\n break;\n case R11:\n bitset[n] = row_bits[11];\n break;\n case R12:\n bitset[n] = row_bits[12];\n break;\n case R13:\n bitset[n] = row_bits[13];\n break;\n case R14:\n bitset[n] = row_bits[14];\n break;\n case R15:\n bitset[n] = row_bits[15];\n break;\n case R16:\n bitset[n] = row_bits[16];\n break;\n case R17:\n bitset[n] = row_bits[17];\n break;\n case OPCODE:\n // Example: opcode 0x31 results in pattern 0b0011'0001\n assert(m_opcodeLength > opcodecount);\n bitset[n] = m_opcode & opcodeshifter;\n opcodeshifter <<= 1;\n ++opcodecount;\n break;\n \n default:\n break;\n }\n\n --n;\n }\n\n return bitset.to_ullong();\n }\n\n void PatternEncoder::setOpcode(uint64_t opcode, uint16_t opcodeLength) {\n m_opcode = opcode;\n m_opcodeLength = opcodeLength;\n }\n\n uint64_t PatternEncoder::getOpcode() const {\n return m_opcode;\n }\n\n uint16_t PatternEncoder::getOpcodeLength() const {\n return m_opcodeLength;\n }\n\n void PatternEncoder::serialize(std::ostream& stream) const {\n stream.write(reinterpret_cast(&m_opcode), sizeof(m_opcode));\n stream.write(reinterpret_cast(&m_opcodeLength), sizeof(m_opcodeLength));\n // settings\n const std::size_t settingsSize = settings.getSettings().size();\n stream.write(reinterpret_cast(&settingsSize), sizeof(settingsSize));\n for (const auto& [descriptor, bitSpec] : settings.getSettings()) {\n stream.write(reinterpret_cast(&descriptor), sizeof(descriptor));\n stream.write(reinterpret_cast(&bitSpec), sizeof(bitSpec));\n }\n }\n\n void PatternEncoder::deserialize(std::istream& stream) {\n stream.read(reinterpret_cast(&m_opcode), sizeof(m_opcode));\n stream.read(reinterpret_cast(&m_opcodeLength), sizeof(m_opcodeLength));\n // settings\n std::size_t settingsSize = 0;\n stream.read(reinterpret_cast(&settingsSize), sizeof(settingsSize));\n settings = PatternEncoderOverrides{};\n for (std::size_t i = 0; i < settingsSize; ++i) {\n pattern_descriptor::t descriptor;\n PatternEncoderBitSpec bitSpec;\n stream.read(reinterpret_cast(&descriptor), sizeof(descriptor));\n stream.read(reinterpret_cast(&bitSpec), sizeof(bitSpec));\n settings.updateSettings({{descriptor, bitSpec}});\n }\n }\n\n} // namespace DRAMPower"
},
{
"path": "src/DRAMPower/DRAMPower/command/Pattern.h",
"content": "#ifndef DRAMPOWER_COMMAND_PATTERN_H\n#define DRAMPOWER_COMMAND_PATTERN_H\n\n#include \n#include \n#include \n\n#include \n#include \n\nnamespace DRAMPower {\nnamespace pattern_descriptor {\n enum t {\n H, L,\n V, X,\n A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17,\n BG0, BG1, BG2, BA0, BA1, BA2, BA3, BA4, BA5, BA6, BA7, BA8,\n C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16,\n R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23,\n CID0, CID1, CID2, CID3,\n AP,\n BL,\n OPCODE, // Example: opcode 0x03 pattern: {H, L, OPCODE, OPCODE, OPCODE, OPCODE} result in 0b100011\n };\n}\n\nenum class PatternEncoderBitSpec\n{\n L = 0,\n H = 1,\n LAST_BIT = 2,\n INVALID = -1\n};\n\n// struct for initializer list in PatternEncoderSettings\nstruct PatternEncoderSettingsEntry {\n pattern_descriptor::t descriptor;\n PatternEncoderBitSpec bitSpec;\n};\n\n// class to store pattern descriptor overrides\nclass PatternEncoderOverrides\n{\n\nprivate:\n std::unordered_map settings;\npublic:\n // Constructor with initializer list for settings\n PatternEncoderOverrides() = default;\n PatternEncoderOverrides(std::initializer_list _settings);\n\npublic:\n void updateSettings(std::initializer_list _settings);\n std::unordered_map getSettings();\n PatternEncoderBitSpec getSetting(pattern_descriptor::t descriptor);\n const std::unordered_map& getSettings() const;\n bool hasSetting(pattern_descriptor::t descriptor);\n bool removeSetting(pattern_descriptor::t descriptor);\n};\n\nclass PatternEncoder : public util::Serialize, public util::Deserialize // Currently LPDDR4\n{\npublic:\n PatternEncoderOverrides settings;\n PatternEncoder(PatternEncoderOverrides settings);\nprivate:\n inline bool applyBitSpec(\n PatternEncoderOverrides &spec,\n pattern_descriptor::t descriptor,\n bool LAST_BIT,\n bool default_bit\n );\n\npublic:\n void setOpcode(uint64_t opcode, uint16_t opcodeLength);\n uint64_t getOpcode() const;\n uint16_t getOpcodeLength() const;\n\n// Overrides\npublic:\n void serialize(std::ostream& stream) const override;\n void deserialize(std::istream& stream) override;\n\npublic:\n uint64_t encode(const Command& cmd, const std::vector& pattern, const uint64_t lastpattern);\n uint64_t encode(const TargetCoordinate& coordinate, const std::vector& pattern, const uint64_t lastpattern);\n\n// Private member variables\nprivate:\n uint64_t m_opcode = 0;\n uint16_t m_opcodeLength = 0;\n};\n\n} // namespace DRAMPower\n\n#endif /* DRAMPOWER_COMMAND_PATTERN_H */\n"
},
{
"path": "src/DRAMPower/DRAMPower/data/energy.cpp",
"content": "#include \"energy.h\"\n\nusing namespace DRAMPower;\n\ndouble energy_info_t::total() const\n{\n auto total = E_act\n + E_pre\n + E_bg_act\n + E_bg_pre\n\n + E_RD\n + E_WR\n + E_RDA\n + E_WRA\n //+ E_pre_RDA\n //+ E_pre_WRA\n\n + E_ref_AB\n + E_ref_PB\n + E_ref_SB\n + E_ref_2B;\n\n return total;\n};\n\nvoid energy_info_t::to_json(json_t &j) const\n{\n j = nlohmann::json{\n {\"ACT\", E_act},\n {\"PRE\", E_pre},\n {\"BG_ACT\", E_bg_act},\n {\"BG_PRE\", E_bg_pre},\n {\"RD\", E_RD},\n {\"WR\", E_WR},\n {\"RDA\", E_RDA},\n {\"WRA\", E_WRA},\n {\"PRE_RDA\", E_pre_RDA},\n {\"PRE_WRA\", E_pre_WRA},\n {\"REF_AB\", E_ref_AB},\n {\"REF_PB\", E_ref_PB},\n {\"REF_SB\", E_ref_SB},\n {\"REF_2B\", E_ref_2B}\n };\n\n}\n\nenergy_info_t& energy_info_t::operator+=(const DRAMPower::energy_info_t& other)\n{\n this->E_act += other.E_act;\n this->E_pre += other.E_pre;\n this->E_bg_act += other.E_bg_act;\n this->E_bg_pre += other.E_bg_pre;\n\n this->E_RD += other.E_RD;\n this->E_WR += other.E_WR;\n this->E_RDA += other.E_RDA;\n this->E_WRA += other.E_WRA;\n this->E_pre_RDA += other.E_pre_RDA;\n this->E_pre_WRA += other.E_pre_WRA;\n\n this->E_ref_AB += other.E_ref_AB;\n this->E_ref_PB += other.E_ref_PB;\n this->E_ref_SB += other.E_ref_SB;\n this->E_ref_2B += other.E_ref_2B;\n\n return *this;\n}\n\ndouble DRAMPower::energy_t::total() const\n{\n double total = 0.0;\n\n energy_info_t bank_energy_total;\n for (const auto& bank_e : this->bank_energy)\n bank_energy_total += bank_e;\n\n total += bank_energy_total.total() + E_bg_act_shared + E_PDNA + E_PDNP + E_sref + E_dsm + E_refab;\n\n return total;\n}\n\nvoid DRAMPower::interface_energy_info_t::to_json(json_t &j) const\n{\n j = nlohmann::json{};\n j[\"controller\"][\"dynamicEnergy\"] = controller.dynamicEnergy;\n j[\"controller\"][\"staticEnergy\"] = controller.staticEnergy;\n j[\"dram\"][\"dynamicEnergy\"] = dram.dynamicEnergy;\n j[\"dram\"][\"staticEnergy\"] = dram.staticEnergy;\n}\n\nvoid DRAMPower::energy_t::to_json(json_t &j) const\n{\n j = nlohmann::json{\n {\"E_bg_act_shared\", E_bg_act_shared},\n {\"E_PDNA\", E_PDNA},\n {\"E_PDNP\", E_PDNP},\n {\"E_sref\", E_sref},\n {\"E_dsm\", E_dsm},\n {\"E_refab\", E_refab}\n };\n // Bank energy\n auto energy_arr = nlohmann::json::array();\n for (const energy_info_t& energy : bank_energy)\n {\n json_t bank_energy_json;\n energy.to_json(bank_energy_json);\n energy_arr.push_back(bank_energy_json);\n }\n j[this->get_Bank_energy_keyword()] = energy_arr;\n}\n\nenergy_info_t DRAMPower::energy_t::aggregated_bank_energy() const\n{\n energy_info_t total;\n\n for (const auto& bank_e : this->bank_energy)\n total += bank_e;\n\n total.E_bg_act += this->E_bg_act_shared;\n\n return total;\n}\n"
},
{
"path": "src/DRAMPower/DRAMPower/data/energy.h",
"content": "#ifndef DRAMPOWER_CALCULATION_ENERGY_H\n#define DRAMPOWER_CALCULATION_ENERGY_H\n\n#pragma once\n\n#include \n#include \n\n#include \n\nnamespace DRAMPower {\n\nstruct energy_info_t\n{\n\tdouble E_act = 0.0;\n\tdouble E_pre = 0.0;\n\tdouble E_bg_act = 0.0;\n\tdouble E_bg_pre = 0.0;\n\n\tdouble E_RD = 0.0;\n\tdouble E_WR = 0.0;\n\tdouble E_RDA = 0.0;\n\tdouble E_WRA = 0.0;\n\tdouble E_pre_RDA = 0.0;\n\tdouble E_pre_WRA = 0.0;\n\n double E_ref_AB = 0.0;\n\tdouble E_ref_PB = 0.0;\n\tdouble E_ref_SB = 0.0;\n\tdouble E_ref_2B = 0.0;\n\n\tdouble total() const;\n\tvoid to_json(json_t &j) const;\n\tenergy_info_t& operator+=(const energy_info_t & other);\n\t// Operator << for std::cout\n\tfriend std::ostream & operator<<(std::ostream & os, const energy_info_t & ei)\n\t{\n\t\tos << \"ACT: \" << ei.E_act << \" \";\n\t\tos << \"PRE: \" << ei.E_pre << \" \";\n\t\tos << \"BG_ACT: \" << ei.E_bg_act << \" \";\n\t\tos << \"BG_PRE: \" << ei.E_bg_pre << \" \";\n\t\tos << \"RD: \" << ei.E_RD << \" \";\n\t\tos << \"WR: \" << ei.E_WR << \" \";\n\t\tos << \"RDA: \" << ei.E_RDA << \" \";\n\t\tos << \"WRA: \" << ei.E_WRA << \" \";\n\t\tos << \"PRE_RDA: \" << ei.E_pre_RDA << \" \";\n\t\tos << \"PRE_WRA: \" << ei.E_pre_WRA << \" \";\n\t\tos << \"REF_AB: \" << ei.E_ref_AB << \" \";\n\t\tos << \"REF_PB: \" << ei.E_ref_PB << \" \";\n\t\tos << \"REF_SB: \" << ei.E_ref_SB << \" \";\n\t\tos << \"REF_2B: \" << ei.E_ref_2B << \" \";\n\n\t\treturn os;\n\t}\n};\n\nstruct energy_t\n{\n\tstd::vector bank_energy;\n\tenergy_info_t aggregated_bank_energy() const;\n\tvoid to_json(json_t &j) const;\n\tconstexpr inline const char * get_Bank_energy_keyword() const\n\t{\n\t\treturn \"BankEnergy\";\n\t}\n\n\n\n\tdouble E_bg_act_shared = 0.0;\n\tdouble E_PDNA = 0.0;\n\tdouble E_PDNP = 0.0;\n\tdouble E_sref = 0.0;\n\tdouble E_dsm = 0.0;\n\tdouble E_refab = 0.0;\n\n\tenergy_t(std::size_t num_banks) : bank_energy(num_banks) {};\n\t// get fields of os stream output\n\tfriend std::ostream & operator<<(std::ostream & os, const energy_t & e)\n\t{\n\t\tos << \"E_bg_act_shared: \" << e.E_bg_act_shared << \" \";\n\t\tos << \"E_PDNA: \" << e.E_PDNA << \" \";\n\t\tos << \"E_PDNP: \" << e.E_PDNP << \" \";\n\t\tos << \"E_sref: \" << e.E_sref << \" \";\n\t\tos << \"E_dsm: \" << e.E_dsm << \" \";\n\t\tos << \"E_refab: \" << e.E_refab << \" \";\n\n \treturn os;\n\t}\n\tdouble total() const;\n};\n\nstruct interface_energy_t\n{\n\tdouble dynamicEnergy = 0.0;\n\tdouble staticEnergy = 0.0;\n\n\tinterface_energy_t &operator+=(const interface_energy_t &rhs) {\n\t\tdynamicEnergy += rhs.dynamicEnergy;\n\t\tstaticEnergy += rhs.staticEnergy;\n\t\treturn *this;\n\t}\n\n\tfriend interface_energy_t operator+(interface_energy_t lhs, const interface_energy_t &rhs) {\n\t\tlhs += rhs;\n\t\treturn lhs;\n\t}\n};\n\n\n\nstruct interface_energy_info_t\n{\n\tinterface_energy_t controller;\n\tinterface_energy_t dram;\n\n double total() const {\n return controller.dynamicEnergy + controller.staticEnergy + dram.dynamicEnergy + dram.staticEnergy;\n }\n\n interface_energy_info_t &operator+=(const interface_energy_info_t &rhs) {\n controller += rhs.controller;\n dram += rhs.dram;\n return *this;\n }\n\n\tfriend interface_energy_info_t operator+(interface_energy_info_t lhs,\n const interface_energy_info_t &rhs) {\n lhs += rhs;\n return lhs;\n }\n\n friend std::ostream & operator<<(std::ostream & os, const interface_energy_info_t & e)\n\t{\n\t\tos << \"Controller: dynamicEnergy: \" << e.controller.dynamicEnergy << \" \";\n os << \"staticEnergy: \" << e.controller.staticEnergy << std::endl;\n os << \"DRAM: dynamicEnergy: \" << e.dram.dynamicEnergy << \" \";\n os << \"staticEnergy: \" << e.dram.staticEnergy << std::endl;\n os << \"Total: \" << e.total();\n \treturn os;\n\t}\n\tvoid to_json(json_t &j) const;\n};\n\n};\n\n#endif /* DRAMPOWER_CALCULATION_ENERGY_H */\n"
},
{
"path": "src/DRAMPower/DRAMPower/data/stats.h",
"content": "#ifndef DRAMPOWER_DATA_STATS_H\n#define DRAMPOWER_DATA_STATS_H\n\n#include \n#include \n#include \n#include \n\n#include \n\nnamespace DRAMPower\n{\n\tstruct CycleStats : public util::Serialize, public util::Deserialize\n\t{\n\t\tstruct command_stats_t : public util::Serialize, public util::Deserialize {\n\t\t\tuint64_t act = 0;\n\t\t\tuint64_t pre = 0;\n\t\t\tuint64_t preSameBank = 0;\n\t\t\tuint64_t reads = 0;\n\t\t\tuint64_t writes = 0;\n\t\t\tuint64_t refAllBank = 0;\n\t\t\tuint64_t refPerBank = 0;\n\t\t\tuint64_t refPerTwoBanks = 0;\n\t\t\tuint64_t refSameBank = 0;\n\t\t\tuint64_t readAuto = 0;\n\t\t\tuint64_t writeAuto = 0;\n\n\t\t\tvoid serialize(std::ostream& stream) const override {\n\t\t\t\tstream.write(reinterpret_cast(&act), sizeof(act));\n\t\t\t\tstream.write(reinterpret_cast(&pre), sizeof(pre));\n\t\t\t\tstream.write(reinterpret_cast(&preSameBank), sizeof(preSameBank));\n\t\t\t\tstream.write(reinterpret_cast(&reads), sizeof(reads));\n\t\t\t\tstream.write(reinterpret_cast(&writes), sizeof(writes));\n\t\t\t\tstream.write(reinterpret_cast(&refAllBank), sizeof(refAllBank));\n\t\t\t\tstream.write(reinterpret_cast(&refPerBank), sizeof(refPerBank));\n\t\t\t\tstream.write(reinterpret_cast(&refPerTwoBanks), sizeof(refPerTwoBanks));\n\t\t\t\tstream.write(reinterpret_cast(&refSameBank), sizeof(refSameBank));\n\t\t\t\tstream.write(reinterpret_cast(&readAuto), sizeof(readAuto));\n\t\t\t\tstream.write(reinterpret_cast(&writeAuto), sizeof(writeAuto));\n\t\t\t}\n\t\t\tvoid deserialize(std::istream& stream) override {\n\t\t\t\tstream.read(reinterpret_cast(&act), sizeof(act));\n\t\t\t\tstream.read(reinterpret_cast(&pre), sizeof(pre));\n\t\t\t\tstream.read(reinterpret_cast(&preSameBank), sizeof(preSameBank));\n\t\t\t\tstream.read(reinterpret_cast(&reads), sizeof(reads));\n\t\t\t\tstream.read(reinterpret_cast(&writes), sizeof(writes));\n\t\t\t\tstream.read(reinterpret_cast(&refAllBank), sizeof(refAllBank));\n\t\t\t\tstream.read(reinterpret_cast(&refPerBank), sizeof(refPerBank));\n\t\t\t\tstream.read(reinterpret_cast(&refPerTwoBanks), sizeof(refPerTwoBanks));\n\t\t\t\tstream.read(reinterpret_cast(&refSameBank), sizeof(refSameBank));\n\t\t\t\tstream.read(reinterpret_cast(&readAuto), sizeof(readAuto));\n\t\t\t\tstream.read(reinterpret_cast(&writeAuto), sizeof(writeAuto));\n\t\t\t}\n\n\t\t\t// operator ==\n\t\t\tbool operator==(const command_stats_t& rhs) const {\n\t\t\t\treturn act == rhs.act &&\n\t\t\t\t\tpre == rhs.pre &&\n\t\t\t\t\tpreSameBank == rhs.preSameBank &&\n\t\t\t\t\treads == rhs.reads &&\n\t\t\t\t\twrites == rhs.writes &&\n\t\t\t\t\trefAllBank == rhs.refAllBank &&\n\t\t\t\t\trefPerBank == rhs.refPerBank &&\n\t\t\t\t\trefPerTwoBanks == rhs.refPerTwoBanks &&\n\t\t\t\t\trefSameBank == rhs.refSameBank &&\n\t\t\t\t\treadAuto == rhs.readAuto &&\n\t\t\t\t\twriteAuto == rhs.writeAuto;\n\t\t\t}\n\t\t} counter;\n\n\t\tstruct cycles_t : public util::Serialize, public util::Deserialize {\n\t\t\tuint64_t act = 0;\n\t\t\tuint64_t pre = 0;\n\t\t\tuint64_t powerDownAct = 0;\n\t\t\tuint64_t powerDownPre = 0;\n\t\t\tuint64_t selfRefresh = 0;\n\t\t\tuint64_t deepSleepMode = 0;\n\t\t\tuint64_t activeTime() const { return act; };\n\t\t\t//uint64_t prechargeTime;\n\n\t\t\tvoid serialize(std::ostream& stream) const override {\n\t\t\t\tstream.write(reinterpret_cast(&act), sizeof(act));\n\t\t\t\tstream.write(reinterpret_cast(&pre), sizeof(pre));\n\t\t\t\tstream.write(reinterpret_cast(&powerDownAct), sizeof(powerDownAct));\n\t\t\t\tstream.write(reinterpret_cast(&powerDownPre), sizeof(powerDownPre));\n\t\t\t\tstream.write(reinterpret_cast(&selfRefresh), sizeof(selfRefresh));\n\t\t\t\tstream.write(reinterpret_cast(&deepSleepMode), sizeof(deepSleepMode));\n\t\t\t}\n\t\t\tvoid deserialize(std::istream& stream) override {\n\t\t\t\tstream.read(reinterpret_cast(&act), sizeof(act));\n\t\t\t\tstream.read(reinterpret_cast(&pre), sizeof(pre));\n\t\t\t\tstream.read(reinterpret_cast(&powerDownAct), sizeof(powerDownAct));\n\t\t\t\tstream.read(reinterpret_cast(&powerDownPre), sizeof(powerDownPre));\n\t\t\t\tstream.read(reinterpret_cast(&selfRefresh), sizeof(selfRefresh));\n\t\t\t\tstream.read(reinterpret_cast(&deepSleepMode), sizeof(deepSleepMode));\n\t\t\t}\n\n\t\t\t// operator ==\n\t\t\tbool operator==(const cycles_t& rhs) const {\n\t\t\t\treturn act == rhs.act &&\n\t\t\t\t\tpre == rhs.pre &&\n\t\t\t\t\tpowerDownAct == rhs.powerDownAct &&\n\t\t\t\t\tpowerDownPre == rhs.powerDownPre &&\n\t\t\t\t\tselfRefresh == rhs.selfRefresh &&\n\t\t\t\t\tdeepSleepMode == rhs.deepSleepMode;\n\t\t\t}\n\t\t} cycles;\n\n\t\tstruct prepos_t : public util::Serialize, public util::Deserialize {\n\t\t\tuint64_t readMerged = 0;\n\t\t\tuint64_t readMergedTime = 0;\n\t\t\tuint64_t writeMerged = 0;\n\t\t\tuint64_t writeMergedTime = 0;\n\t\t\tuint64_t readSeamless = 0;\n\t\t\tuint64_t writeSeamless = 0;\n\n\t\t\tvoid serialize(std::ostream& stream) const override {\n\t\t\t\tstream.write(reinterpret_cast(&readMerged), sizeof(readMerged));\n\t\t\t\tstream.write(reinterpret_cast(&readMergedTime), sizeof(readMergedTime));\n\t\t\t\tstream.write(reinterpret_cast(&writeMerged), sizeof(writeMerged));\n\t\t\t\tstream.write(reinterpret_cast(&writeMergedTime), sizeof(writeMergedTime));\n\t\t\t\tstream.write(reinterpret_cast(&readSeamless), sizeof(readSeamless));\n\t\t\t\tstream.write(reinterpret_cast(&writeSeamless), sizeof(writeSeamless));\n\t\t\t}\n\t\t\tvoid deserialize(std::istream& stream) override {\n\t\t\t\tstream.read(reinterpret_cast(&readMerged), sizeof(readMerged));\n\t\t\t\tstream.read(reinterpret_cast(&readMergedTime), sizeof(readMergedTime));\n\t\t\t\tstream.read(reinterpret_cast(&writeMerged), sizeof(writeMerged));\n\t\t\t\tstream.read(reinterpret_cast(&writeMergedTime), sizeof(writeMergedTime));\n\t\t\t\tstream.read(reinterpret_cast(&readSeamless), sizeof(readSeamless));\n\t\t\t\tstream.read(reinterpret_cast(&writeSeamless), sizeof(writeSeamless));\n\t\t\t}\n\n\t\t\t// operator ==\n\t\t\tbool operator==(const prepos_t& rhs) const {\n\t\t\t\treturn readMerged == rhs.readMerged &&\n\t\t\t\t\treadMergedTime == rhs.readMergedTime &&\n\t\t\t\t\twriteMerged == rhs.writeMerged &&\n\t\t\t\t\twriteMergedTime == rhs.writeMergedTime &&\n\t\t\t\t\treadSeamless == rhs.readSeamless &&\n\t\t\t\t\twriteSeamless == rhs.writeSeamless;\n\t\t\t}\n\t\t} prepos;\n\n\t\tvoid serialize(std::ostream& stream) const override {\n\t\t\tcounter.serialize(stream);\n\t\t\tcycles.serialize(stream);\n\t\t\tprepos.serialize(stream);\n\t\t}\n\t\tvoid deserialize(std::istream& stream) override {\n\t\t\tcounter.deserialize(stream);\n\t\t\tcycles.deserialize(stream);\n\t\t\tprepos.deserialize(stream);\n\t\t}\n\n\t\t// operator ==\n\t\tbool operator==(const CycleStats& rhs) const {\n\t\t\treturn counter == rhs.counter &&\n\t\t\t\tcycles == rhs.cycles &&\n\t\t\t\tprepos == rhs.prepos;\n\t\t}\n\t};\n\n struct TogglingStats\n {\n util::bus_stats_t read;\n util::bus_stats_t write;\n };\n\n\tstruct SimulationStats\n\t{\n\t\tutil::bus_stats_t commandBus;\n\t\tutil::bus_stats_t readBus;\n\t\tutil::bus_stats_t writeBus;\n\t\tutil::bus_stats_t clockStats;\n\t\tutil::bus_stats_t wClockStats;\n\n\t\tutil::bus_stats_t readDBI;\n\t\tutil::bus_stats_t writeDBI;\n\n TogglingStats togglingStats;\n\n\t\tutil::bus_stats_t readDQSStats;\n\t\tutil::bus_stats_t writeDQSStats;\n\n\t\tstd::vector bank;\n\t\tstd::vector rank_total;\n\n\t\t// Operator ==\n\t\tbool operator==(const SimulationStats& other) const {\n\t\t\t// Compare banks\n\t\t\tbool banksEqual = true;\n\t\t\tif (bank.size() != other.bank.size()) {\n\t\t\t\tbanksEqual = false;\n\t\t\t} else {\n\t\t\t\tfor (size_t i = 0; i < bank.size(); ++i) {\n\t\t\t\t\tif (!(bank[i] == other.bank[i])) {\n\t\t\t\t\t\tbanksEqual = false;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tbool rank_totalEqual = true;\n\t\t\tif (rank_total.size() != other.rank_total.size()) {\n\t\t\t\trank_totalEqual = false;\n\t\t\t} else {\n\t\t\t\tfor (size_t i = 0; i < rank_total.size(); ++i) {\n\t\t\t\t\tif (!(rank_total[i] == other.rank_total[i])) {\n\t\t\t\t\t\trank_totalEqual = false;\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\treturn commandBus == other.commandBus &&\n\t\t\t\treadBus == other.readBus &&\n\t\t\t\twriteBus == other.writeBus &&\n\t\t\t\tclockStats == other.clockStats &&\n\t\t\t\twClockStats == other.wClockStats &&\n\t\t\t\treadDBI == other.readDBI &&\n\t\t\t\twriteDBI == other.writeDBI &&\n\t\t\t\ttogglingStats.read == other.togglingStats.read &&\n\t\t\t\ttogglingStats.write == other.togglingStats.write &&\n\t\t\t\treadDQSStats == other.readDQSStats &&\n\t\t\t\twriteDQSStats == other.writeDQSStats &&\n\t\t\t\tbanksEqual &&\n\t\t\t\trank_totalEqual;\n\t\t}\n\t};\n};\n\n\n#endif /* DRAMPOWER_DATA_STATS_H */\n"
},
{
"path": "src/DRAMPower/DRAMPower/dram/Bank.h",
"content": "#ifndef DRAMPOWER_DDR_BANK_H\n#define DRAMPOWER_DDR_BANK_H\n\n#include \n#include \n#include \n#include \n\n#include \n\nnamespace DRAMPower {\n\nstruct Bank : public util::Serialize, public util::Deserialize {\npublic:\n enum class BankState {\n BANK_PRECHARGED = 0,\n BANK_ACTIVE = 1,\n };\npublic:\n CycleStats::command_stats_t counter;\n\n struct {\n interval_t act;\n interval_t powerDownAct;\n interval_t powerDownPre;\n } cycles;\n\n BankState bankState;\npublic:\n timestamp_t latestPre = 0;\n timestamp_t refreshEndTime = 0;\n\n void serialize(std::ostream& stream) const override {\n stream.write(reinterpret_cast(&bankState), sizeof(bankState));\n stream.write(reinterpret_cast(&latestPre), sizeof(latestPre));\n stream.write(reinterpret_cast(&refreshEndTime), sizeof(refreshEndTime));\n cycles.act.serialize(stream);\n cycles.powerDownAct.serialize(stream);\n cycles.powerDownPre.serialize(stream);\n counter.serialize(stream);\n }\n void deserialize(std::istream& stream) override {\n stream.read(reinterpret_cast(&bankState), sizeof(bankState));\n stream.read(reinterpret_cast(&latestPre), sizeof(latestPre));\n stream.read(reinterpret_cast(&refreshEndTime), sizeof(refreshEndTime));\n cycles.act.deserialize(stream);\n cycles.powerDownAct.deserialize(stream);\n cycles.powerDownPre.deserialize(stream);\n counter.deserialize(stream);\n }\n};\n\n}\n\n#endif /* DRAMPOWER_DDR_BANK_H */\n"
},
{
"path": "src/DRAMPower/DRAMPower/dram/Interface.cpp",
"content": "#include \"Interface.h\"\n\nnamespace DRAMPower {\n\nusing namespace DRAMUtils::Config;\n\nvoid TogglingHandle::TogglingHandleLastBurst::serialize(std::ostream &stream) const\n{\n stream.write(reinterpret_cast(&last_length), sizeof(last_length));\n stream.write(reinterpret_cast(&last_load), sizeof(last_load));\n stream.write(reinterpret_cast(&handled), sizeof(handled));\n}\n\nvoid TogglingHandle::TogglingHandleLastBurst::deserialize(std::istream &stream) {\n stream.read(reinterpret_cast(&last_length), sizeof(last_length));\n stream.read(reinterpret_cast(&last_load), sizeof(last_load));\n stream.read(reinterpret_cast(&handled), sizeof(handled));\n}\n\nTogglingHandle::TogglingHandle(const uint64_t width, const uint64_t datarate, const double toggling_rate, const double duty_cycle, const bool enabled)\n : width(width)\n , datarate(datarate)\n , toggling_rate(toggling_rate)\n , duty_cycle(duty_cycle)\n , enableflag(enabled)\n{\n assert(width > 0); // Check bounds\n assert(datarate > 0); // Check bounds\n assert(duty_cycle >= 0 && duty_cycle <= 1); // Check bounds\n assert(toggling_rate >= 0 && toggling_rate <= 1); // Check bounds\n}\n\nTogglingHandle::TogglingHandle(const uint64_t width, const uint64_t datarate, const double toggling_rate, const double duty_cycle, DRAMUtils::Config::TogglingRateIdlePattern idlepattern, const bool enabled)\n : width(width)\n , datarate(datarate)\n , toggling_rate(toggling_rate)\n , duty_cycle(duty_cycle)\n , enableflag(enabled)\n , idlepattern(idlepattern)\n{\n assert(width > 0); // Check bounds\n assert(datarate > 0); // Check bounds\n assert(duty_cycle >= 0 && duty_cycle <= 1); // Check bounds\n assert(toggling_rate >= 0 && toggling_rate <= 1); // Check bounds\n}\n\nvoid TogglingHandle::disable(timestamp_t timestamp)\n{\n timestamp_t virtualtimestamp = timestamp * this->datarate;\n if(!this->enableflag) {\n return;\n }\n if (this->last_burst) {\n if(virtualtimestamp >= this->last_burst.last_length + this->last_burst.last_load) {\n this->count += this->last_burst.last_length;\n } else {\n // Partial burst is lost\n this->count += virtualtimestamp - this->last_burst.last_load;\n }\n this->last_burst.handled = true;\n }\n this->disable_timestamp = virtualtimestamp;\n this->enableflag = false;\n}\n\nvoid TogglingHandle::enable(timestamp_t timestamp)\n{\n if (this->enableflag) {\n return;\n }\n this->disable_time += timestamp * this->datarate - this->disable_timestamp;\n this->enableflag = true;\n}\n\nbool TogglingHandle::isEnabled() const\n{\n return this->enableflag;\n}\n\ndouble TogglingHandle::getTogglingRate() const\n{\n return this->toggling_rate;\n}\n\ndouble TogglingHandle::getDutyCycle() const\n{\n return this->duty_cycle;\n}\nuint64_t TogglingHandle::getWidth() const\n{\n return this->width;\n}\nvoid TogglingHandle::setWidth(const uint64_t width)\n{\n this->width = width;\n}\nuint64_t TogglingHandle::getDatarate() const\n{\n return this->datarate;\n}\nvoid TogglingHandle::setDataRate(const uint64_t datarate)\n{\n this->datarate = datarate;\n}\n\nvoid TogglingHandle::setTogglingRateAndDutyCycle(const double toggling_rate, const double duty_cycle, const TogglingRateIdlePattern idlepattern)\n{\n this->toggling_rate = toggling_rate;\n this->duty_cycle = duty_cycle;\n this->idlepattern = idlepattern;\n}\nuint64_t TogglingHandle::getCount() const\n{\n return this->count;\n}\n\n// Returns timestamp of last burst\ntimestamp_t TogglingHandle::get_lastburst_timestamp(bool relative_to_clock) const\n{\n timestamp_t lastburst = this->last_burst.last_load + this->last_burst.last_length;\n if (relative_to_clock) {\n auto remainder = lastburst % this->datarate;\n if (remainder != 0) {\n lastburst += this->datarate - remainder;\n }\n return lastburst / this->datarate;\n }\n return lastburst;\n}\n\nvoid TogglingHandle::incCountBurstLength(timestamp_t timestamp, uint64_t burstlength)\n{\n // Convert to bus timings\n timestamp_t virtual_timestamp = timestamp * this->datarate;\n assert(virtual_timestamp / this->datarate == timestamp); // No overflow\n assert(\n (this->last_burst && (virtual_timestamp >= (this->last_burst.last_length + this->last_burst.last_load)))\n || !this->last_burst\n );\n // Add last burst\n if (!this->last_burst.handled) {\n // Add last burst to count\n this->count += this->last_burst.last_length;\n }\n // Store burst in last_length and last_load if enabled\n if (this->enableflag) {\n // Set last_length and last_load to new burst_length\n this->last_burst = TogglingHandleLastBurst {\n burstlength, // last_length\n virtual_timestamp, // last_load\n false // handled\n };\n } else {\n // Clear last_burst\n this->last_burst.handled = true;\n }\n}\nvoid TogglingHandle::incCountBitLength(timestamp_t timestamp, uint64_t bitlength)\n{\n assert(bitlength % this->width == 0);\n this->incCountBurstLength(timestamp, bitlength / this->width);\n}\nutil::bus_stats_t TogglingHandle::get_stats(timestamp_t timestamp) const\n{\n // Convert to bus timings\n timestamp_t virtual_timestamp = timestamp * this->datarate;\n assert(virtual_timestamp / this->datarate == timestamp); // No overflow\n\n util::bus_stats_t stats;\n\n uint64_t count = this->count;\n timestamp_t disable_time = this->disable_time;\n if(this->enableflag) {\n // Check if last burst is finished\n if ((this->last_burst)\n && (virtual_timestamp < this->last_burst.last_length + this->last_burst.last_load)\n ) {\n // last burst not finished\n count += virtual_timestamp - this->last_burst.last_load;\n } else if (this->last_burst) {\n // last burst finished\n count += this->last_burst.last_length;\n }\n } else {\n disable_time += virtual_timestamp - this->disable_timestamp;\n }\n // Compute toggles\n stats.ones = count * this->duty_cycle;\n stats.zeroes = count * (1 - this->duty_cycle);\n stats.ones_to_zeroes = count * this->toggling_rate / 2; // Round down\n // Compute idle\n switch (this->idlepattern) {\n case TogglingRateIdlePattern::L:\n stats.zeroes += virtual_timestamp - disable_time - count;\n break;\n case TogglingRateIdlePattern::H:\n stats.ones += virtual_timestamp - disable_time - count;\n break;\n case TogglingRateIdlePattern::Invalid:\n assert(false); // Fallback to Z\n case TogglingRateIdlePattern::Z:\n // Nothing to do in high impedance mode\n break;\n }\n // Scale by bus width\n stats.ones *= this->width;\n stats.zeroes *= this->width;\n stats.ones_to_zeroes *= this->width;\n // Compute zeroes_to_ones and bit changes\n stats.zeroes_to_ones = stats.ones_to_zeroes;\n stats.bit_changes = stats.ones_to_zeroes + stats.zeroes_to_ones;\n return stats;\n}\n\nvoid TogglingHandle::serialize(std::ostream &stream) const {\n stream.write(reinterpret_cast(&width), sizeof(width));\n stream.write(reinterpret_cast(&datarate), sizeof(datarate));\n stream.write(reinterpret_cast(&toggling_rate), sizeof(toggling_rate));\n stream.write(reinterpret_cast(&duty_cycle), sizeof(duty_cycle));\n last_burst.serialize(stream);\n stream.write(reinterpret_cast(&enableflag), sizeof(enableflag));\n stream.write(reinterpret_cast(&count), sizeof(count));\n stream.write(reinterpret_cast(&disable_timestamp), sizeof(disable_timestamp));\n stream.write(reinterpret_cast(&disable_time), sizeof(disable_time));\n stream.write(reinterpret_cast(&idlepattern), sizeof(idlepattern));\n}\n\nvoid TogglingHandle::deserialize(std::istream &stream) {\n stream.read(reinterpret_cast(&width), sizeof(width));\n stream.read(reinterpret_cast(&datarate), sizeof(datarate));\n stream.read(reinterpret_cast(&toggling_rate), sizeof(toggling_rate));\n stream.read(reinterpret_cast(&duty_cycle), sizeof(duty_cycle));\n last_burst.deserialize(stream);\n stream.read(reinterpret_cast(&enableflag), sizeof(enableflag));\n stream.read(reinterpret_cast(&count), sizeof(count));\n stream.read(reinterpret_cast(&disable_timestamp), sizeof(disable_timestamp));\n stream.read(reinterpret_cast(&disable_time), sizeof(disable_time));\n stream.read(reinterpret_cast(&idlepattern), sizeof(idlepattern));\n}\n\n} // namespace DRAMPower"
},
{
"path": "src/DRAMPower/DRAMPower/dram/Interface.h",
"content": "#ifndef DRAMPOWER_DDR_INTERFACE_H\n#define DRAMPOWER_DDR_INTERFACE_H\n\n#pragma once \n\n#include \n#include \n#include \n#include \n\n#include \n\n#include \n#include \n\n\nnamespace DRAMPower {\n\nclass TogglingHandle : public util::Serialize, public util::Deserialize\n{\n\nstruct TogglingHandleLastBurst : public util::Serialize, public util::Deserialize {\n uint64_t last_length = 0;\n timestamp_t last_load = 0;\n bool handled = true;\n TogglingHandleLastBurst() = default;\n TogglingHandleLastBurst(uint64_t last_length, timestamp_t last_load, bool handled)\n : last_length(last_length), last_load(last_load), handled(handled) {}\n operator bool() const { return !this->handled; }\n void serialize(std::ostream &stream) const override;\n void deserialize(std::istream &stream) override;\n};\n\nprivate:\n uint64_t width = 0;\n uint64_t datarate = 1;\n double toggling_rate = 0; // [0, 1] allowed\n double duty_cycle = 0.0; // [0, 1] allowed\n TogglingHandleLastBurst last_burst;\n bool enableflag = false; // default disabled if default constructor is used\n uint64_t count = 0;\n timestamp_t disable_timestamp = 0;\n timestamp_t disable_time = 0;\n DRAMUtils::Config::TogglingRateIdlePattern idlepattern = DRAMUtils::Config::TogglingRateIdlePattern::Z;\n\npublic:\nTogglingHandle(const uint64_t width, const uint64_t datarate, const double toggling_rate, const double duty_cycle, const bool enabled = true);\nTogglingHandle(const uint64_t width, const uint64_t datarate, const double toggling_rate, const double duty_cycle, DRAMUtils::Config::TogglingRateIdlePattern idlepattern, const bool enabled = true);\n\n TogglingHandle() = default;\npublic:\n// Getters and Setters\n double getTogglingRate() const;\n double getDutyCycle() const;\n bool isEnabled() const;\n uint64_t getWidth() const;\n uint64_t getDatarate() const;\n timestamp_t get_lastburst_timestamp(bool relative_to_clock = true) const;\n \n void setTogglingRateAndDutyCycle(const double toggling_rate, const double duty_cycle, const DRAMUtils::Config::TogglingRateIdlePattern idlepattern);\n void disable(timestamp_t timestamp);\n void enable(timestamp_t timestamp);\n void setWidth(const uint64_t width);\n void setDataRate(const uint64_t datarate);\n uint64_t getCount() const;\npublic:\n void incCountBurstLength(timestamp_t timestamp, uint64_t burstlength);\n void incCountBitLength(timestamp_t timestamp, uint64_t bitlength);\n util::bus_stats_t get_stats(timestamp_t timestamp) const;\n\n// Overrides\n void serialize(std::ostream &stream) const override;\n void deserialize(std::istream &stream) override;\n\n};\n\nstruct interface_stats_t \n{\n util::bus_stats_t command_bus;\n util::bus_stats_t read_bus;\n util::bus_stats_t write_bus;\n};\n\n} // namespace DRAMPower\n\n#endif /* DRAMPOWER_DDR_INTERFACE_H */\n"
},
{
"path": "src/DRAMPower/DRAMPower/dram/Rank.cpp",
"content": "#include \"Rank.h\"\n\n#include \n\nnamespace DRAMPower {\n\nRank::Rank(std::size_t numBanks)\n : banks(numBanks)\n{};\n\nbool Rank::isActive(timestamp_t timestamp) {\n if ( timestamp < this->endRefreshTime ) {\n std::cout << \"[WARN] Rank::isActive() -> timestamp (\" << timestamp <<\") < \" << \"endRefreshTime (\" << this->endRefreshTime << \")\" << std::endl;\n }\n return countActiveBanks() > 0 || timestamp < this->endRefreshTime;\n}\n\nstd::size_t Rank::countActiveBanks() const {\n return (unsigned)std::count_if(banks.begin(), banks.end(),\n [](const auto& bank) {\n return (bank.bankState == Bank::BankState::BANK_ACTIVE);\n });\n}\n\nvoid Rank::serialize(std::ostream& stream) const {\n stream.write(reinterpret_cast(&memState), sizeof(memState));\n stream.write(reinterpret_cast(&endRefreshTime), sizeof(endRefreshTime));\n commandCounter.serialize(stream);\n\n stream.write(reinterpret_cast(&counter.selfRefresh), sizeof(counter.selfRefresh));\n stream.write(reinterpret_cast(&counter.deepSleepMode), sizeof(counter.deepSleepMode));\n stream.write(reinterpret_cast(&endRefreshTime), sizeof(endRefreshTime));\n cycles.pre.serialize(stream);\n cycles.act.serialize(stream);\n cycles.ref.serialize(stream);\n cycles.sref.serialize(stream);\n cycles.powerDownAct.serialize(stream);\n cycles.powerDownPre.serialize(stream);\n cycles.deepSleepMode.serialize(stream);\n\n for (const auto& bank : banks) {\n bank.serialize(stream);\n }\n};\n\nvoid Rank::deserialize(std::istream& stream) {\n stream.read(reinterpret_cast(&memState), sizeof(memState));\n stream.read(reinterpret_cast(&endRefreshTime), sizeof(endRefreshTime));\n commandCounter.deserialize(stream);\n\n stream.read(reinterpret_cast(&counter.selfRefresh), sizeof(counter.selfRefresh));\n stream.read(reinterpret_cast(&counter.deepSleepMode), sizeof(counter.deepSleepMode));\n stream.read(reinterpret_cast(&endRefreshTime), sizeof(endRefreshTime));\n cycles.pre.deserialize(stream);\n cycles.act.deserialize(stream);\n cycles.ref.deserialize(stream);\n cycles.sref.deserialize(stream);\n cycles.powerDownAct.deserialize(stream);\n cycles.powerDownPre.deserialize(stream);\n cycles.deepSleepMode.deserialize(stream);\n\n for (auto & bank : banks) {\n bank.deserialize(stream);\n }\n};\n\n\nvoid RankInterface::serialize(std::ostream& stream) const {\n stream.write(reinterpret_cast(&seamlessPrePostambleCounter_read), sizeof(seamlessPrePostambleCounter_read));\n stream.write(reinterpret_cast(&seamlessPrePostambleCounter_write), sizeof(seamlessPrePostambleCounter_write));\n stream.write(reinterpret_cast(&mergedPrePostambleCounter_read), sizeof(mergedPrePostambleCounter_read));\n stream.write(reinterpret_cast(&mergedPrePostambleCounter_write), sizeof(mergedPrePostambleCounter_write));\n stream.write(reinterpret_cast(&mergedPrePostambleTime_read), sizeof(mergedPrePostambleTime_read));\n stream.write(reinterpret_cast(&mergedPrePostambleTime_write), sizeof(mergedPrePostambleTime_write));\n stream.write(reinterpret_cast(&lastReadEnd), sizeof(lastReadEnd));\n stream.write(reinterpret_cast(&lastWriteEnd), sizeof(lastWriteEnd));\n}\nvoid RankInterface::deserialize(std::istream& stream) {\n stream.read(reinterpret_cast(&seamlessPrePostambleCounter_read), sizeof(seamlessPrePostambleCounter_read));\n stream.read(reinterpret_cast(&seamlessPrePostambleCounter_write), sizeof(seamlessPrePostambleCounter_write));\n stream.read(reinterpret_cast(&mergedPrePostambleCounter_read), sizeof(mergedPrePostambleCounter_read));\n stream.read(reinterpret_cast(&mergedPrePostambleCounter_write), sizeof(mergedPrePostambleCounter_write));\n stream.read(reinterpret_cast(&mergedPrePostambleTime_read), sizeof(mergedPrePostambleTime_read));\n stream.read(reinterpret_cast(&mergedPrePostambleTime_write), sizeof(mergedPrePostambleTime_write));\n stream.read(reinterpret_cast(&lastReadEnd), sizeof(lastReadEnd));\n stream.read(reinterpret_cast(&lastWriteEnd), sizeof(lastWriteEnd));\n}\n\n} // namespace DRAMPower"
},
{
"path": "src/DRAMPower/DRAMPower/dram/Rank.h",
"content": "#ifndef DRAMPOWER_DDR_RANK_H\n#define DRAMPOWER_DDR_RANK_H\n\n#include \n#include \n#include \n#include \n\n#include \n#include \n\n#include \n\nnamespace DRAMPower {\n\n// Power-Down and Self-refresh related memory states\nenum class MemState {\n\tNOT_IN_PD = 0,\n\tPDN_ACT,\n\tPDN_PRE,\n\tSREF,\n\tDSM,\n};\n\n\nstruct Rank : public util::Serialize, public util::Deserialize {\n\n// Type aliases\n\tusing commandCounter_t = util::CommandCounter;\n\npublic:\n// Variables\n\tMemState memState = MemState::NOT_IN_PD;\n\tcommandCounter_t commandCounter;\n\tstruct {\n\t\tinterval_t pre; // useful ???\n\t\tinterval_t act;\n\t\tinterval_t ref;\n\t\tinterval_t sref;\n\t\tinterval_t powerDownAct;\n\t\tinterval_t powerDownPre;\n\t\tinterval_t deepSleepMode;\n\t} cycles;\n\tstruct {\n\t\tuint64_t selfRefresh = 0;\n\t\tuint64_t deepSleepMode = 0;\n\t} counter = { 0 };\n\ttimestamp_t endRefreshTime = 0;\n\tstd::vector banks;\n\npublic:\n// Constructors\n\tRank(std::size_t numBanks);\n\n// Functions\npublic:\n\tbool isActive(timestamp_t timestamp);\n\tstd::size_t countActiveBanks() const;\n// Overrides\n\tvoid serialize(std::ostream& stream) const override;\n\tvoid deserialize(std::istream& stream) override;\n};\n\nstruct RankInterface : public util::Serialize, public util::Deserialize {\n\tuint64_t \tseamlessPrePostambleCounter_read\t= 0;\n\tuint64_t \tseamlessPrePostambleCounter_write\t= 0;\n\tuint64_t\tmergedPrePostambleCounter_read\t\t= 0;\n\tuint64_t\tmergedPrePostambleCounter_write\t\t= 0;\n\ttimestamp_t\tmergedPrePostambleTime_read\t\t\t= 0;\n\ttimestamp_t\tmergedPrePostambleTime_write\t\t= 0;\n\ttimestamp_t lastReadEnd = 0;\n\ttimestamp_t lastWriteEnd = 0;\n\n// Overrides\n\tvoid serialize(std::ostream& stream) const override;\n\tvoid deserialize(std::istream& stream) override;\n};\n\n} // namespace DRAMPower\n\n#endif /* DRAMPOWER_DDR_RANK_H */\n"
},
{
"path": "src/DRAMPower/DRAMPower/dram/dram_base.h",
"content": "#ifndef DRAMPOWER_DRAM_DRAM_BASE_H\n#define DRAMPOWER_DRAM_DRAM_BASE_H\n\n#include \n\n#include \n#include \n#include \n#include \n\n#include \n#include \n#include \n#include \n#include \n#include \n\n#include \n\n#include \n#include \n\nnamespace DRAMPower {\n\nusing namespace DRAMUtils::Config;\n\ntemplate \nclass dram_base : public util::Serialize, public util::Deserialize\n{\n// Public type definitions\npublic:\n using commandEnum_t = CommandEnum;\n using commandCount_t = std::vector;\n // ExtensionManager\n using extension_manager_t = util::extension_manager::ExtensionManager<\n extensions::Base\n >;\n\n// Public constructors and assignment operators\npublic:\n dram_base(const dram_base&) = default; // copy constructor\n dram_base& operator=(const dram_base&) = default; // copy assignment operator\n dram_base(dram_base&&) = default; // Move constructor\n dram_base& operator=(dram_base&&) = default; // Move assignment operator\n virtual ~dram_base() = 0;\n// Protected constructors\nprotected:\n dram_base() = default;\n\n// Public member functions\npublic:\n // ExtensionManager\n extension_manager_t& getExtensionManager() { return m_extensionManager; }\n const extension_manager_t& getExtensionManager() const { return m_extensionManager; }\n\n void doCoreCommand(const Command& command) {\n doCoreCommandImpl(command);\n }\n \n void doInterfaceCommand(const Command& command) {\n doInterfaceCommandImpl(command);\n }\n\n void doCommand(const Command& command) {\n doCoreCommandImpl(command);\n doInterfaceCommandImpl(command);\n }\n\n // deprecated\n void doCoreInterfaceCommand(const Command& command) {\n doCommand(command);\n }\n\n timestamp_t getLastCommandTime() const {\n return getLastCommandTime_impl();\n }\n\n double getTotalEnergy(timestamp_t timestamp) {\n return calcCoreEnergy(timestamp).total() + calcInterfaceEnergy(timestamp).total();\n };\n\n SimulationStats getStats() {\n return getWindowStats(getLastCommandTime());\n }\n\n void serialize(std::ostream& stream) const override {\n // Serialize the extension manager\n m_extensionManager.serialize(stream);\n serialize_impl(stream);\n }\n\n void deserialize(std::istream& stream) override {\n // Deserialize the extension manager\n m_extensionManager.deserialize(stream);\n deserialize_impl(stream);\n }\n\n// Public virtual methods\npublic:\n virtual energy_t calcCoreEnergyStats(const SimulationStats& stats) const = 0;\n energy_t calcCoreEnergy(timestamp_t timestamp) {\n return calcCoreEnergyStats(getWindowStats(timestamp));\n }\n virtual interface_energy_info_t calcInterfaceEnergyStats(const SimulationStats& stats) const = 0;\n interface_energy_info_t calcInterfaceEnergy(timestamp_t timestamp) {\n return calcInterfaceEnergyStats(getWindowStats(timestamp));\n }\n virtual SimulationStats getWindowStats(timestamp_t timestamp) = 0;\n virtual util::CLIArchitectureConfig getCLIArchitectureConfig() = 0;\n virtual bool isSerializable() const = 0;\n\n// Private virtual methods\nprivate:\n virtual void doCoreCommandImpl(const Command& command) = 0;\n virtual void doInterfaceCommandImpl(const Command& command) = 0;\n virtual timestamp_t getLastCommandTime_impl() const = 0;\n virtual void serialize_impl(std::ostream& stream) const = 0;\n virtual void deserialize_impl(std::istream& stream) = 0;\n\n// Private member variables\nprivate:\n extension_manager_t m_extensionManager;\n};\n\ntemplate \ndram_base::~dram_base() = default;\n\n}\n\n#endif /* DRAMPOWER_DDR_DRAM_BASE_H */\n"
},
{
"path": "src/DRAMPower/DRAMPower/memspec/MemSpec.h",
"content": "/*\n * Copyright (c) 2015-2020, University of Kaiserslautern\n * Copyright (c) 2012-2021, Fraunhofer IESE\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are\n * met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n *\n * 3. Neither the name of the copyright holder nor the names of its\n * contributors may be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\n * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER\n * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n * Authors:\n * Janik Schlemminger\n * Matthias Jung\n * Lukas Steiner\n * Luiza Correa\n */\n\n#ifndef DRAMPOWER_MEMSPEC_MEMSPEC_H\n#define DRAMPOWER_MEMSPEC_MEMSPEC_H\n\n#include \n\n#include \n#include \n#include \n\n#include \n#include \n\n\nnamespace DRAMPower {\n\ntemplate \nclass MemSpec\n{\n T rawmemspec;\npublic:\n uint64_t numberOfBanks;\n\tuint64_t numberOfRows;\n\tuint64_t numberOfColumns;\n\tuint64_t numberOfDevices; // Number of devices per rank\n\tuint64_t burstLength;\n\tuint64_t dataRate;\n\tuint64_t bitWidth;\n\n /* MEMSPEC specific parameters\n unsigned numberOfBankGroups;\n unsigned numberOfDevicesOnDIMM;\n unsigned numberOfRanks;\n unsigned banksPerRank;\n unsigned groupsPerRank;\n unsigned banksPerGroup;\n unsigned numberOfChannels;\n */\n\n std::string memoryId;\n std::string memoryType;\n\n\n uint64_t prechargeOffsetRD;\n uint64_t prechargeOffsetWR;\n MemSpec() = delete;\n virtual ~MemSpec() = default;\n\n\t// MemSpec() = default;\n MemSpec(const T &memspec) : rawmemspec(memspec)\n {\n numberOfBanks = memspec.memarchitecturespec.nbrOfBanks;\n numberOfRows = memspec.memarchitecturespec.nbrOfRows;\n numberOfColumns = memspec.memarchitecturespec.nbrOfColumns;\n numberOfDevices = memspec.memarchitecturespec.nbrOfDevices;\n if (numberOfDevices < 1)\n {\n numberOfDevices = 1;\n }\n burstLength = memspec.memarchitecturespec.burstLength;\n dataRate = memspec.memarchitecturespec.dataRate;\n bitWidth = memspec.memarchitecturespec.width;\n memoryId = memspec.memoryId;\n memoryType = memspec.id;\n }\n\n};\n\n} // namespace DRAMPower\n\n#endif /* DRAMPOWER_MEMSPEC_MEMSPEC_H */\n"
},
{
"path": "src/DRAMPower/DRAMPower/memspec/MemSpecDDR4.cpp",
"content": "/*\n * Copyright (c) 2019, University of Kaiserslautern\n * Copyright (c) 2012-2021, Fraunhofer IESE\n * All rights reserved.\n *\n * Redistribution and use in source and binary forms, with or without\n * modification, are permitted provided that the following conditions are\n * met:\n *\n * 1. Redistributions of source code must retain the above copyright notice,\n * this list of conditions and the following disclaimer.\n *\n * 2. Redistributions in binary form must reproduce the above copyright\n * notice, this list of conditions and the following disclaimer in the\n * documentation and/or other materials provided with the distribution.\n *\n * 3. Neither the name of the copyright holder nor the names of its\n * contributors may be used to endorse or promote products derived from\n * this software without specific prior written permission.\n *\n * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\n * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER\n * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n *\n * Authors:\n * Lukas Steiner\n * Luiza Correa\n */\n\n#include \"MemSpecDDR4.h\"\nusing namespace DRAMPower;\n\n\nMemSpecDDR4::MemSpecDDR4(const DRAMUtils::MemSpec::MemSpecDDR4 &memspec)\n : MemSpec(memspec)\n{\n\n numberOfBankGroups = memspec.memarchitecturespec.nbrOfBankGroups;\n numberOfRanks = memspec.memarchitecturespec.nbrOfRanks;\n\n memTimingSpec.tCK = memspec.memtimingspec.tCK;\n memTimingSpec.tRAS = memspec.memtimingspec.RAS;\n memTimingSpec.tRCD = memspec.memtimingspec.RCD;\n memTimingSpec.tRTP = memspec.memtimingspec.RTP;\n memTimingSpec.tWL = memspec.memtimingspec.WL;\n memTimingSpec.tWR = memspec.memtimingspec.WR;\n memTimingSpec.tRP = memspec.memtimingspec.RP;\n memTimingSpec.tAL = memspec.memtimingspec.AL;\n\n\n auto VDD = VoltageDomain::VDD;\n auto VPP = VoltageDomain::VPP;\n\n memPowerSpec.push_back(MemPowerSpec());\n\n memPowerSpec[VDD].vXX = memspec.mempowerspec.vdd;\n memPowerSpec[VDD].iXX0 = memspec.mempowerspec.idd0;\n memPowerSpec[VDD].iXX2N = memspec.mempowerspec.idd2n;\n memPowerSpec[VDD].iXX3N = memspec.mempowerspec.idd3n;\n memPowerSpec[VDD].iXX4R = memspec.mempowerspec.idd4r;\n memPowerSpec[VDD].iXX4W = memspec.mempowerspec.idd4w;\n memPowerSpec[VDD].iXX6N = memspec.mempowerspec.idd6n;\n memPowerSpec[VDD].iXX2P = memspec.mempowerspec.idd2p;\n memPowerSpec[VDD].iXX3P = memspec.mempowerspec.idd3p;\n\n memPowerSpec.push_back(MemPowerSpec());\n\n memPowerSpec[VPP].vXX = memspec.mempowerspec.vpp;\n memPowerSpec[VPP].iXX0 = memspec.mempowerspec.ipp0;\n memPowerSpec[VPP].iXX2N = memspec.mempowerspec.ipp2n;\n memPowerSpec[VPP].iXX3N = memspec.mempowerspec.ipp3n;\n memPowerSpec[VPP].iXX4R = memspec.mempowerspec.ipp4r;\n memPowerSpec[VPP].iXX4W = memspec.mempowerspec.ipp4w;\n memPowerSpec[VPP].iXX6N = memspec.mempowerspec.ipp6n;\n memPowerSpec[VPP].iXX2P = memspec.mempowerspec.ipp2p;\n memPowerSpec[VPP].iXX3P = memspec.mempowerspec.ipp3p;\n\n vddq = memspec.mempowerspec.vddq;\n\n if (DRAMUtils::MemSpec::RefModeTypeDDR4::REF_MODE_2 == memspec.memarchitecturespec.RefMode) {\n memPowerSpec[VDD].iXX5X = memspec.mempowerspec.idd5F2;\n memPowerSpec[VPP].iXX5X = memspec.mempowerspec.ipp5F2;\n memTimingSpec.tRFC = memspec.memtimingspec.RFC2;\n } else if (DRAMUtils::MemSpec::RefModeTypeDDR4::REF_MODE_4 == memspec.memarchitecturespec.RefMode) {\n memPowerSpec[VDD].iXX5X = memspec.mempowerspec.idd5F4;\n memPowerSpec[VPP].iXX5X = memspec.mempowerspec.ipp5F4;\n memTimingSpec.tRFC = memspec.memtimingspec.RFC4;\n } else {\n // RefModeTypeDDR4::REF_MODE_1 || RefModeTypeDDR4::INVALID\n memPowerSpec[VDD].iXX5X = memspec.mempowerspec.idd5B;\n memPowerSpec[VPP].iXX5X = memspec.mempowerspec.ipp5B;\n memTimingSpec.tRFC = memspec.memtimingspec.RFC1;\n }\n memPowerSpec[VDD].iBeta = memspec.mempowerspec.iBeta_vdd.value_or(memspec.mempowerspec.idd0);\n memPowerSpec[VPP].iBeta = memspec.mempowerspec.iBeta_vpp.value_or(memspec.mempowerspec.ipp0);\n\n if(memspec.bankwisespec.has_value())\n {\n bwParams.bwPowerFactRho = memspec.bankwisespec.value().factRho.value_or(1);\n }\n else\n {\n bwParams.bwPowerFactRho = 1;\n }\n\n memTimingSpec.tBurst = burstLength/dataRate;\n prechargeOffsetRD = memTimingSpec.tAL + memTimingSpec.tRTP;\n prechargeOffsetWR = memTimingSpec.tBurst + memTimingSpec.tWL + memTimingSpec.tWR;\n\n parseImpedanceSpec(memspec);\n parsePrePostamble(memspec);\n}\n\nvoid MemSpecDDR4::parseImpedanceSpec(const DRAMUtils::MemSpec::MemSpecDDR4 &memspec) {\n memImpedanceSpec = memspec.memimpedancespec;\n}\n\nvoid MemSpecDDR4::parsePrePostamble(const DRAMUtils::MemSpec::MemSpecDDR4 &memspec)\n{\n prePostamble.read_zeroes = memspec.prepostamble.read_zeroes;\n prePostamble.write_zeroes = memspec.prepostamble.write_zeroes;\n prePostamble.read_ones = memspec.prepostamble.read_ones;\n prePostamble.write_ones = memspec.prepostamble.write_ones;\n prePostamble.read_zeroes_to_ones = memspec.prepostamble.read_zeroes_to_ones;\n prePostamble.write_zeroes_to_ones = memspec.prepostamble.write_zeroes_to_ones;\n prePostamble.write_ones_to_zeroes = memspec.prepostamble.write_ones_to_zeroes;\n prePostamble.read_ones_to_zeroes = memspec.prepostamble.read_ones_to_zeroes;\n prePostamble.readMinTccd = memspec.prepostamble.readMinTccd;\n prePostamble.writeMinTccd = memspec.prepostamble.writeMinTccd;;\n}\n\nMemSpecDDR4 MemSpecDDR4::from_memspec(const DRAMUtils::MemSpec::MemSpecVariant& memSpec)\n{\n return std::get(memSpec.getVariant());\n}\n\n"
},
{
"path": "src/DRAMPower/DRAMPower/memspec/MemSpecDDR4.h",
"content": "/*\n* Copyright (c) 2019, University of Kaiserslautern\n* Copyright (c) 2012-2021, Fraunhofer IESE\n* All rights reserved.\n*\n* Redistribution and use in source and binary forms, with or without\n* modification, are permitted provided that the following conditions are\n* met:\n*\n* 1. Redistributions of source code must retain the above copyright notice,\n* this list of conditions and the following disclaimer.\n*\n* 2. Redistributions in binary form must reproduce the above copyright\n* notice, this list of conditions and the following disclaimer in the\n* documentation and/or other materials provided with the distribution.\n*\n* 3. Neither the name of the copyright holder nor the names of its\n* contributors may be used to endorse or promote products derived from\n* this software without specific prior written permission.\n*\n* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n* \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\n* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\n* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER\n* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\n* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\n* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n*\n* Authors:\n* Lukas Steiner\n* Luiza Correa\n*/\n\n#ifndef DRAMPOWER_MEMSPEC_MEMSPECDDR4_H\n#define DRAMPOWER_MEMSPEC_MEMSPECDDR4_H\n\n#include \"MemSpec.h\"\n\n#include \n\n#include \n\n\nnamespace DRAMPower {\n\nclass MemSpecDDR4 final : public MemSpec\n{\npublic:\n\tusing MemImpedanceSpec = DRAMUtils::MemSpec::MemImpedanceSpecTypeDDR4;\n\n enum VoltageDomain {\n VDD = 0,\n VPP = 1,\n };\n\npublic:\n MemSpecDDR4() = delete;\n \n\tMemSpecDDR4(const DRAMUtils::MemSpec::MemSpecDDR4 &memspec);\n\n\tMemSpecDDR4(json_t &data) = delete;\n\tMemSpecDDR4(const json_t &data) = delete;\n\n // Copy constructor and assignment operator\n MemSpecDDR4(const MemSpecDDR4&) = default;\n\tMemSpecDDR4& operator=(const MemSpecDDR4&) = default;\n\n // Move constructor and assignment operator\n MemSpecDDR4(MemSpecDDR4&&) = default;\n\tMemSpecDDR4& operator=(MemSpecDDR4&&) = default;\n\n\tuint64_t numberOfBankGroups;\n\tuint64_t numberOfRanks;\n\n\tdouble vddq;\n\n\t// Memspec Variables:\n\tstruct MemTimingSpec \n\t{\n\t\tdouble fck;\n\t\tdouble tCK;\n\t\tuint64_t tRAS;\n\t\tuint64_t tRCD;\n\t\tuint64_t tRL;\n\t\tuint64_t tRTP;\n\t\tuint64_t tWL;\n\t\tuint64_t tWR;\n\t\tuint64_t tRFC;\n\t\tuint64_t tRP;\n\t\tuint64_t tAL;\n uint64_t tBurst;\n\t};\n\n\t// Currents and Voltages:\n\tstruct MemPowerSpec \n\t{\n\t\tdouble iXX0;\n\t\tdouble iXX2N;\n\t\tdouble iXX3N;\n\t\tdouble iXX4R;\n\t\tdouble iXX4W;\n\t\tdouble iXX5X;\n\t\tdouble iXX6N;\n\t\tdouble vXX;\n\t\tdouble iXX2P;\n\t\tdouble iXX3P;\n double iBeta;\n\t};\n\n\tstruct BankWiseParams \n\t{\n // ACT Standby power factor\n double bwPowerFactRho;\n\t};\n\n\t// Pre and Postamble\n\t// Total number of zero cycles relative to tCK (one cycle = tCK) for example, if tCK = 1ns, and read_zeroes = 2.5, then the total time is 2.5ns\n\tstruct PrePostamble\n\t{\n\t\t// Total number of zero/one cycles per DQs differential pair\n\t\t// relative to tCK (one cycle = tCK)\n\t\t// for example, if tCK = 1ns, and read_zeroes = 2.5, then the total time is 2.5ns\n\t\tdouble read_zeroes;\n\t\tdouble write_zeroes;\n\t\tdouble read_ones;\n\t\tdouble write_ones;\n\n\t\t// Total number of zero to one and one to zero transitions per DQs differential pair\n\t\tuint64_t read_zeroes_to_ones;\n\t\tuint64_t write_zeroes_to_ones;\n\t\tuint64_t write_ones_to_zeroes;\n\t\tuint64_t read_ones_to_zeroes;\n\n\t\t// Minimum time interval between two consecutive read/write commands to prevent merging or seamless transition.\n\t\tuint64_t readMinTccd;\n\t\tuint64_t writeMinTccd;\n\t};\n\n uint64_t refreshMode;\n\tMemTimingSpec memTimingSpec;\n\tstd::vector memPowerSpec;\n\tMemImpedanceSpec memImpedanceSpec;\n\tPrePostamble prePostamble;\n\tBankWiseParams bwParams;\nprivate:\n\tvoid parseImpedanceSpec(const DRAMUtils::MemSpec::MemSpecDDR4 &memspec);\n\tvoid parsePrePostamble(const DRAMUtils::MemSpec::MemSpecDDR4 &memspec);\npublic:\n static MemSpecDDR4 from_memspec(const DRAMUtils::MemSpec::MemSpecVariant&);\n \n};\n\n}\n#endif /* DRAMPOWER_MEMSPEC_MEMSPECDDR4_H */\n"
},
{
"path": "src/DRAMPower/DRAMPower/memspec/MemSpecDDR5.cpp",
"content": "#include \"MemSpecDDR5.h\"\nusing namespace DRAMPower;\n\n\nMemSpecDDR5::MemSpecDDR5(const DRAMUtils::MemSpec::MemSpecDDR5 &memspec)\n : MemSpec(memspec)\n{\n numberOfBankGroups = memspec.memarchitecturespec.nbrOfBankGroups;\n numberOfRanks = memspec.memarchitecturespec.nbrOfRanks;\n banksPerGroup = numberOfBanks / numberOfBankGroups;\n\n memTimingSpec.tCK = memspec.memtimingspec.tCK;\n memTimingSpec.tRAS = memspec.memtimingspec.RAS;\n memTimingSpec.tRCD = memspec.memtimingspec.RCD;\n memTimingSpec.tRTP = memspec.memtimingspec.RTP;\n memTimingSpec.tWL = memspec.memtimingspec.WL;\n memTimingSpec.tWR = memspec.memtimingspec.WR;\n memTimingSpec.tRP = memspec.memtimingspec.RP;\n memTimingSpec.tRFCsb = memspec.memtimingspec.RFCsb_slr;\n\n auto VDD = VoltageDomain::VDD;\n auto VPP = VoltageDomain::VPP;\n\n memPowerSpec.push_back(MemPowerSpec());\n memPowerSpec[VDD].vXX = memspec.mempowerspec.vdd;\n memPowerSpec[VDD].iXX0 = memspec.mempowerspec.idd0;\n memPowerSpec[VDD].iXX2N = memspec.mempowerspec.idd2n;\n memPowerSpec[VDD].iXX3N = memspec.mempowerspec.idd3n;\n memPowerSpec[VDD].iXX4R = memspec.mempowerspec.idd4r;\n memPowerSpec[VDD].iXX4W = memspec.mempowerspec.idd4w;\n memPowerSpec[VDD].iXX5C = memspec.mempowerspec.idd5c;\n memPowerSpec[VDD].iXX6N = memspec.mempowerspec.idd6n;\n memPowerSpec[VDD].iXX2P = memspec.mempowerspec.idd2p;\n memPowerSpec[VDD].iXX3P = memspec.mempowerspec.idd3p;\n\n memPowerSpec.push_back(MemPowerSpec());\n\n memPowerSpec[VPP].vXX = memspec.mempowerspec.vpp;\n memPowerSpec[VPP].iXX0 = memspec.mempowerspec.ipp0;\n memPowerSpec[VPP].iXX2N = memspec.mempowerspec.ipp2n;\n memPowerSpec[VPP].iXX3N = memspec.mempowerspec.ipp3n;\n memPowerSpec[VPP].iXX4R = memspec.mempowerspec.ipp4r;\n memPowerSpec[VPP].iXX4W = memspec.mempowerspec.ipp4w;\n memPowerSpec[VPP].iXX5C = memspec.mempowerspec.ipp5c;\n memPowerSpec[VPP].iXX6N = memspec.mempowerspec.ipp6n;\n memPowerSpec[VPP].iXX2P = memspec.mempowerspec.ipp2p;\n memPowerSpec[VPP].iXX3P = memspec.mempowerspec.ipp3p;\n\n vddq = memspec.mempowerspec.vddq;\n\n\n if (DRAMUtils::MemSpec::RefModeTypeDDR5::REF_MODE_2 == memspec.memarchitecturespec.RefMode) {\n memPowerSpec[VDD].iXX5X = memspec.mempowerspec.idd5f;\n memPowerSpec[VPP].iXX5X = memspec.mempowerspec.ipp5f;\n memTimingSpec.tRFC = memspec.memtimingspec.RFC2_slr;\n } else {\n // RefModeTypeDDR5::REF_MODE_1 || RefModeTypeDDR5::INVALID\n memPowerSpec[VDD].iXX5X = memspec.mempowerspec.idd5b;\n memPowerSpec[VPP].iXX5X = memspec.mempowerspec.ipp5b;\n memTimingSpec.tRFC = memspec.memtimingspec.RFC1_slr;\n }\n\n memPowerSpec[VDD].iBeta = memspec.mempowerspec.iBeta_vdd.value_or(memspec.mempowerspec.idd0);\n memPowerSpec[VPP].iBeta = memspec.mempowerspec.iBeta_vpp.value_or(memspec.mempowerspec.ipp0);\n\n\n if (memspec.bankwisespec.has_value())\n {\n bwParams.bwPowerFactRho = memspec.bankwisespec.value().factRho.value_or(1);\n }\n else\n {\n bwParams.bwPowerFactRho = 1;\n }\n\n memTimingSpec.tBurst = burstLength/dataRate;\n prechargeOffsetRD = memTimingSpec.tRTP;\n prechargeOffsetWR = memTimingSpec.tBurst + memTimingSpec.tWL + memTimingSpec.tWR;\n\n parseImpedanceSpec(memspec);\n parseDataRateSpec(memspec);\n}\n\nvoid MemSpecDDR5::parseImpedanceSpec(const DRAMUtils::MemSpec::MemSpecDDR5 &memspec) {\n memImpedanceSpec = memspec.memimpedancespec;\n}\n\nvoid MemSpecDDR5::parseDataRateSpec(const DRAMUtils::MemSpec::MemSpecDDR5 &memspec) {\n if (!memspec.dataratespec.has_value()) {\n dataRateSpec = {2, 2, 2};\n return;\n }\n\n dataRateSpec.commandBusRate = memspec.dataratespec.value().ca_bus_rate;\n dataRateSpec.dataBusRate = memspec.dataratespec.value().dq_bus_rate;\n dataRateSpec.dqsBusRate = memspec.dataratespec.value().dqs_bus_rate;\n}\n\nMemSpecDDR5 MemSpecDDR5::from_memspec(const DRAMUtils::MemSpec::MemSpecVariant& memSpec)\n{\n return std::get(memSpec.getVariant());\n}\n"
},
{
"path": "src/DRAMPower/DRAMPower/memspec/MemSpecDDR5.h",
"content": "#ifndef DRAMPOWER_MEMSPEC_MEMSPECDDR5_H\n#define DRAMPOWER_MEMSPEC_MEMSPECDDR5_H\n\n#include \"MemSpec.h\"\n\n#include \n\n\nnamespace DRAMPower {\n\nclass MemSpecDDR5 final : public MemSpec {\n public:\n\t using MemImpedanceSpec = DRAMUtils::MemSpec::MemImpedanceSpecTypeDDR5;\n\n enum VoltageDomain {\n VDD = 0,\n VPP = 1,\n };\n\n public:\n MemSpecDDR5() = delete;\n\n MemSpecDDR5(const DRAMUtils::MemSpec::MemSpecDDR5 &memspec);\n\n MemSpecDDR5(json_t &data) = delete;\n MemSpecDDR5(const json_t &data) = delete;\n\n // Copy constructor and assignment operator\n MemSpecDDR5(const MemSpecDDR5&) = default;\n MemSpecDDR5& operator=(const MemSpecDDR5&) = default;\n\n // Move constructor and assignment operator\n MemSpecDDR5(MemSpecDDR5&&) = default;\n MemSpecDDR5& operator=(MemSpecDDR5&&) = default;\n\n uint64_t numberOfBankGroups;\n uint64_t banksPerGroup;\n uint64_t numberOfRanks;\n\n double vddq;\n\n // Memspec Variables:\n struct MemTimingSpec\n {\n double fck;\n double tCK;\n uint64_t tRAS;\n uint64_t tRCD;\n uint64_t tRL;\n uint64_t tRTP;\n uint64_t tWL;\n uint64_t tWR;\n uint64_t tRFC;\n uint64_t tRFCsb;\n uint64_t tRP;\n uint64_t tBurst;\n };\n\n // Currents and Voltages:\n struct MemPowerSpec\n {\n double vXX;\n double iXX0;\n double iXX2N;\n double iXX3N;\n double iXX2P;\n double iXX3P;\n double iXX4R;\n double iXX4W;\n double iXX5X;\n double iXX5C;\n double iXX6N;\n double iBeta;\n };\n\n struct DataRateSpec {\n uint64_t commandBusRate;\n uint64_t dataBusRate;\n uint64_t dqsBusRate;\n };\n\n struct BankWiseParams\n {\n // ACT Standby power factor\n double bwPowerFactRho;\n };\n\n MemTimingSpec memTimingSpec;\n MemImpedanceSpec memImpedanceSpec;\n DataRateSpec dataRateSpec;\n std::vector memPowerSpec;\n BankWiseParams bwParams;\n\n private:\n void parseImpedanceSpec(const DRAMUtils::MemSpec::MemSpecDDR5 &memspec);\n void parseDataRateSpec(const DRAMUtils::MemSpec::MemSpecDDR5 &memspec);\n public:\n static MemSpecDDR5 from_memspec(const DRAMUtils::MemSpec::MemSpecVariant&);\n };\n\n}\n\n#endif /* DRAMPOWER_MEMSPEC_MEMSPECDDR5_H */\n"
},
{
"path": "src/DRAMPower/DRAMPower/memspec/MemSpecLPDDR4.cpp",
"content": "#include \"MemSpecLPDDR4.h\"\nusing namespace DRAMPower;\n\n\nMemSpecLPDDR4::MemSpecLPDDR4(const DRAMUtils::MemSpec::MemSpecLPDDR4 &memspec)\n : MemSpec(memspec), memImpedanceSpec{}\n{\n numberOfBankGroups = memspec.memarchitecturespec.nbrOfBankGroups;\n numberOfRanks = memspec.memarchitecturespec.nbrOfRanks;\n banksPerGroup = numberOfBanks / numberOfBankGroups;\n\n memTimingSpec.tCK = memspec.memtimingspec.tCK;\n memTimingSpec.tRAS = memspec.memtimingspec.RAS;\n memTimingSpec.tRCD = memspec.memtimingspec.RCD;\n memTimingSpec.tRL = memspec.memtimingspec.RL;\n memTimingSpec.tRTP = memspec.memtimingspec.RTP;\n memTimingSpec.tWL = memspec.memtimingspec.WL;\n memTimingSpec.tWR = memspec.memtimingspec.WR;\n memTimingSpec.tRP = memspec.memtimingspec.RPpb;\n memTimingSpec.tRFCPB = memspec.memtimingspec.RFCpb;\n memTimingSpec.tRFC = memspec.memtimingspec.RFCab;\n memTimingSpec.tREFI = memspec.memtimingspec.REFI;\n\n auto VDD1 = VoltageDomain::VDD1;\n auto VDD2 = VoltageDomain::VDD2;\n\n memPowerSpec.push_back(MemPowerSpec());\n memPowerSpec.push_back(MemPowerSpec());\n\n memPowerSpec[VDD1].vDDX = memspec.mempowerspec.vdd1;\n memPowerSpec[VDD1].iDD0X = memspec.mempowerspec.idd01;\n memPowerSpec[VDD1].iDD2NX = memspec.mempowerspec.idd2n1;\n memPowerSpec[VDD1].iDD3NX = memspec.mempowerspec.idd3n1;\n memPowerSpec[VDD1].iDD4RX = memspec.mempowerspec.idd4r1;\n memPowerSpec[VDD1].iDD4WX = memspec.mempowerspec.idd4w1;\n memPowerSpec[VDD1].iDD5X = memspec.mempowerspec.idd51;\n memPowerSpec[VDD1].iDD5PBX = memspec.mempowerspec.idd5pb1;\n memPowerSpec[VDD1].iDD6X = memspec.mempowerspec.idd61;\n memPowerSpec[VDD1].iDD2PX = memspec.mempowerspec.idd2p1;\n memPowerSpec[VDD1].iDD3PX = memspec.mempowerspec.idd3p1;\n\n memPowerSpec[VDD2].vDDX = memspec.mempowerspec.vdd2;\n memPowerSpec[VDD2].iDD0X = memspec.mempowerspec.idd02;\n memPowerSpec[VDD2].iDD2NX = memspec.mempowerspec.idd2n2;\n memPowerSpec[VDD2].iDD3NX = memspec.mempowerspec.idd3n2;\n memPowerSpec[VDD2].iDD4RX = memspec.mempowerspec.idd4r2;\n memPowerSpec[VDD2].iDD4WX = memspec.mempowerspec.idd4w2;\n memPowerSpec[VDD2].iDD5X = memspec.mempowerspec.idd52;\n memPowerSpec[VDD2].iDD5PBX = memspec.mempowerspec.idd5pb2;\n memPowerSpec[VDD2].iDD6X = memspec.mempowerspec.idd62;\n memPowerSpec[VDD2].iDD2PX = memspec.mempowerspec.idd2p2;\n memPowerSpec[VDD2].iDD3PX = memspec.mempowerspec.idd3p2;\n\n vddq = memspec.mempowerspec.vddq;\n\n memPowerSpec[VDD1].iBeta = memspec.mempowerspec.iBeta_vdd1.value_or(memspec.mempowerspec.idd01);\n memPowerSpec[VDD2].iBeta = memspec.mempowerspec.iBeta_vdd2.value_or(memspec.mempowerspec.idd02);\n\n\n if(memspec.bankwisespec.has_value())\n {\n bwParams.bwPowerFactRho = memspec.bankwisespec.value().factRho.value_or(1);\n bwParams.bwPowerFactSigma = memspec.bankwisespec.value().factSigma.value_or(1);\n bwParams.flgPASR = memspec.bankwisespec.value().hasPASR.value_or(false);\n if (memspec.bankwisespec.value().pasrMode.has_value())\n {\n if(memspec.bankwisespec.value().pasrMode.value() == DRAMUtils::MemSpec::pasrModesType::Invalid)\n {\n // pasrMode invalid\n bwParams.pasrMode = 0;\n }\n else\n {\n // pasrMode valid\n bwParams.pasrMode = static_cast(memspec.bankwisespec.value().pasrMode.value());\n }\n }\n else\n {\n bwParams.pasrMode = 0;\n }\n }\n else\n {\n bwParams.bwPowerFactRho = 1;\n bwParams.bwPowerFactSigma = 1;\n bwParams.flgPASR = false;\n bwParams.pasrMode = 0;\n }\n\n if (bwParams.flgPASR) {\n\n ///////////////////////////////////////////////////////////\n // Activate banks for self refresh based on the PASR mode\n // ACTIVE - X\n // NOT ACTIVE - 0\n ///////////////////////////////////////////////////////////\n switch(bwParams.pasrMode) {\n\n case(BankWiseParams::pasrModes::PASR_0): {\n // PASR MODE 0\n // FULL ARRAY\n // |X X X X |\n // |X X X X |\n bwParams.activeBanks.resize(numberOfBanks);\n std::iota(bwParams.activeBanks.begin(), bwParams.activeBanks.end(), 0);\n break;\n }\n case(BankWiseParams::pasrModes::PASR_1): {\n // PASR MODE 1\n // (1/2) ARRAY\n // |X X X X |\n // |0 0 0 0 |\n bwParams.activeBanks.resize(numberOfBanks - 4);\n std::iota(bwParams.activeBanks.begin(), bwParams.activeBanks.end(), 0);\n break;\n }\n case(BankWiseParams::pasrModes::PASR_2): {\n // PASR MODE 2\n // (1/4) ARRAY\n // |X X 0 0 |\n // |0 0 0 0 |\n bwParams.activeBanks.resize(numberOfBanks - 6);\n std::iota(bwParams.activeBanks.begin(), bwParams.activeBanks.end(), 0);\n break;\n }\n case(BankWiseParams::pasrModes::PASR_3): {\n // PASR MODE 3\n // (1/8) ARRAY\n // |X 0 0 0 |\n // |0 0 0 0 |\n bwParams.activeBanks.resize(numberOfBanks - 7);\n std::iota(bwParams.activeBanks.begin(), bwParams.activeBanks.end(), 0);\n break;\n }\n case(BankWiseParams::pasrModes::PASR_4): {\n // PASR MODE 4\n // (3/4) ARRAY\n // |0 0 X X |\n // |X X X X |\n bwParams.activeBanks.resize(numberOfBanks - 2);\n std::iota(bwParams.activeBanks.begin(), bwParams.activeBanks.end(), 2);\n break;\n }\n case(BankWiseParams::pasrModes::PASR_5): {\n // PASR MODE 5\n // (1/2) ARRAY\n // |0 0 0 0 |\n // |X X X X |\n bwParams.activeBanks.resize(numberOfBanks - 4);\n std::iota(bwParams.activeBanks.begin(), bwParams.activeBanks.end(), 4);\n break;\n }\n case(BankWiseParams::pasrModes::PASR_6): {\n // PASR MODE 6\n // (1/4) ARRAY\n // |0 0 0 0 |\n // |0 0 X X |\n bwParams.activeBanks.resize(numberOfBanks - 6);\n std::iota(bwParams.activeBanks.begin(), bwParams.activeBanks.end(), 6);\n break;\n }\n case(BankWiseParams::pasrModes::PASR_7): {\n // PASR MODE 7\n // (1/8) ARRAY\n // |0 0 0 0 |\n // |0 0 0 X |\n bwParams.activeBanks.resize(numberOfBanks - 7);\n std::iota(bwParams.activeBanks.begin(), bwParams.activeBanks.end(), 7);\n break;\n }\n default: {\n // PASR MODE 0\n // FULL ARRAY\n // |X X X X |\n // |X X X X |\n bwParams.activeBanks.resize(numberOfBanks);\n std::iota(bwParams.activeBanks.begin(), bwParams.activeBanks.end(), 0);\n break;\n }\n } //end switch\n } // end IF flgPASR\n\n //Source: JESD209-4 (LPDDR4); Table 21\n if(burstLength == 16){\n prechargeOffsetRD = memTimingSpec.tRTP;\n }else{\n prechargeOffsetRD = 8 + memTimingSpec.tRTP;\n }\n prechargeOffsetWR = memTimingSpec.tWL + burstLength/2 + memTimingSpec.tWR + 1;\n parseImpedanceSpec(memspec);\n}\n\nbool MemSpecLPDDR4::BankWiseParams::isBankActiveInPasr(const unsigned bankIdx) const\n{\n return (std::find(activeBanks.begin(), activeBanks.end(), bankIdx)\n != activeBanks.end());\n}\n\nvoid MemSpecLPDDR4::parseImpedanceSpec(const DRAMUtils::MemSpec::MemSpecLPDDR4 &memspec) {\n memImpedanceSpec = memspec.memimpedancespec;\n}\n\nMemSpecLPDDR4 MemSpecLPDDR4::from_memspec(const DRAMUtils::MemSpec::MemSpecVariant& memSpec)\n{\n return std::get(memSpec.getVariant());\n}\n"
},
{
"path": "src/DRAMPower/DRAMPower/memspec/MemSpecLPDDR4.h",
"content": "#ifndef DRAMPOWER_MEMSPEC_MEMSPECLPDDR4_H\n#define DRAMPOWER_MEMSPEC_MEMSPECLPDDR4_H\n\n#include \"MemSpec.h\"\n\n#include \n\n\nnamespace DRAMPower {\n\nclass MemSpecLPDDR4 final : public MemSpec\n{\npublic:\n\tusing MemImpedanceSpec = DRAMUtils::MemSpec::MemImpedanceSpecTypeLPDDR4;\n\n enum VoltageDomain {\n VDD1 = 0,\n VDD2 = 1,\n };\n\npublic:\n\tMemSpecLPDDR4() = delete;\n\t\n\tMemSpecLPDDR4(const DRAMUtils::MemSpec::MemSpecLPDDR4 &memspec);\n\t\n\tMemSpecLPDDR4(json_t &data) = delete;\n\tMemSpecLPDDR4(const json_t &data) = delete;\n\n // Copy constructor and assignment operator\n MemSpecLPDDR4(const MemSpecLPDDR4&) = default;\n\tMemSpecLPDDR4& operator=(const MemSpecLPDDR4&) = default;\n\n // Move constructor and assignment operator\n MemSpecLPDDR4(MemSpecLPDDR4&&) = default;\n MemSpecLPDDR4& operator=(MemSpecLPDDR4&&) = default;\n\n\t~MemSpecLPDDR4() = default;\n\n uint64_t numberOfBankGroups;\n uint64_t banksPerGroup;\n uint64_t numberOfRanks;\n\n\tdouble vddq;\n\n\tstruct MemTimingSpec\n\t{\n\t\tdouble fck;\n\t\tdouble tCK;\n\t\tuint64_t tRAS;\n\t\tuint64_t tRCD;\n\t\tuint64_t tRL;\n\t\tuint64_t tRTP;\n\t\tuint64_t tWL;\n\t\tuint64_t tWR;\n\t\tuint64_t tREFI;\n\t\tuint64_t tRFC;\n\t\tuint64_t tRFCPB;\n\t\tuint64_t tRP;\n\t};\n\n\t// Currents and Voltages:\n\tstruct MemPowerSpec\n\t{\n double vDDX;\n double iDD0X;\n double iDD2NX;\n double iDD3NX;\n double iDD2PX;\n double iDD3PX;\n double iDD4RX;\n double iDD4WX;\n double iDD5X;\n double iDD5PBX;\n double iDD6X;\n double iBeta;\n\n\t};\n\n\tstruct BankWiseParams\n\t{\n\t\t// Set of possible PASR modes\n\t\tenum pasrModes {\n\t\t\tPASR_0,\n\t\t\tPASR_1,\n\t\t\tPASR_2,\n\t\t\tPASR_3,\n\t\t\tPASR_4,\n\t\t\tPASR_5,\n\t\t\tPASR_6,\n\t\t\tPASR_7\n\t\t};\n\n\t\t// List of active banks under the specified PASR mode\n\t\tstd::vector activeBanks;\n\t\t// ACT Standby power factor\n\t\tdouble bwPowerFactRho;\n\t\t// Self-Refresh power factor\n\t\tdouble bwPowerFactSigma;\n\t\t// Whether PASR is enabled ( true : enabled )\n\t\tbool flgPASR;\n\t\t// PASR mode utilized (int 0-7)\n\t\tuint64_t pasrMode;\n\t\t// Whether bank is active in PASR\n\t\tbool isBankActiveInPasr(const unsigned bankIdx) const;\n\n\t};\n\n\tMemTimingSpec memTimingSpec;\n\tMemImpedanceSpec memImpedanceSpec;\n\tstd::vector memPowerSpec;\n\tBankWiseParams bwParams;\n\nprivate:\n void parseImpedanceSpec(const DRAMUtils::MemSpec::MemSpecLPDDR4 &memspec);\n\npublic:\n static MemSpecLPDDR4 from_memspec(const DRAMUtils::MemSpec::MemSpecVariant&);\n};\n\n}\n\n#endif /* DRAMPOWER_MEMSPEC_MEMSPECLPDDR4_H */\n"
},
{
"path": "src/DRAMPower/DRAMPower/memspec/MemSpecLPDDR5.cpp",
"content": "#include \"DRAMPower/memspec/MemSpecLPDDR5.h\"\n\nusing namespace DRAMPower;\n\n\nMemSpecLPDDR5::MemSpecLPDDR5(const DRAMUtils::MemSpec::MemSpecLPDDR5 &memspec)\n : MemSpec(memspec)\n{\n numberOfBankGroups = memspec.memarchitecturespec.nbrOfBankGroups;\n numberOfRanks = memspec.memarchitecturespec.nbrOfRanks;\n banksPerGroup = numberOfBanks / numberOfBankGroups;\n\n memTimingSpec.tCK = memspec.memtimingspec.tCK;\n memTimingSpec.WCKtoCK = memspec.memtimingspec.WCK2CK;\n memTimingSpec.tWCK = memTimingSpec.tCK / memTimingSpec.WCKtoCK;\n memTimingSpec.tRAS = memspec.memtimingspec.RAS;\n memTimingSpec.tRCD = memspec.memtimingspec.RCD_S;\n memTimingSpec.tRBTP = memspec.memtimingspec.RBTP;\n memTimingSpec.tWL = memspec.memtimingspec.WL;\n memTimingSpec.tWR = memspec.memtimingspec.WR;\n memTimingSpec.tRP = memspec.memtimingspec.RPpb;\n memTimingSpec.tRFCPB = memspec.memtimingspec.RFCpb;\n memTimingSpec.tRFC = memspec.memtimingspec.RFCab;\n memTimingSpec.tREFI = memspec.memtimingspec.REFI;\n\n auto VDD1 = VoltageDomain::VDD1;\n auto VDD2H = VoltageDomain::VDD2H;\n auto VDD2L = VoltageDomain::VDD2L;\n\n memPowerSpec.push_back(MemPowerSpec()); // VDD1\n memPowerSpec.push_back(MemPowerSpec()); // VDD2H\n memPowerSpec.push_back(MemPowerSpec()); // VDD2L\n\n memPowerSpec[VDD1].vDDX = memspec.mempowerspec.vdd1;\n memPowerSpec[VDD1].iDD0X = memspec.mempowerspec.idd01;\n memPowerSpec[VDD1].iDD2NX = memspec.mempowerspec.idd2n1;\n memPowerSpec[VDD1].iDD3NX = memspec.mempowerspec.idd3n1;\n memPowerSpec[VDD1].iDD4RX = memspec.mempowerspec.idd4r1;\n memPowerSpec[VDD1].iDD4WX = memspec.mempowerspec.idd4w1;\n memPowerSpec[VDD1].iDD5X = memspec.mempowerspec.idd51;\n memPowerSpec[VDD1].iDD5PBX = memspec.mempowerspec.idd5pb1;\n memPowerSpec[VDD1].iDD6X = memspec.mempowerspec.idd61;\n memPowerSpec[VDD1].iDD6DSX = memspec.mempowerspec.idd6ds1;\n memPowerSpec[VDD1].iDD2PX = memspec.mempowerspec.idd2p1;\n memPowerSpec[VDD1].iDD3PX = memspec.mempowerspec.idd3p1;\n\n memPowerSpec[VDD2H].vDDX = memspec.mempowerspec.vdd2h;\n memPowerSpec[VDD2H].iDD0X = memspec.mempowerspec.idd02h;\n memPowerSpec[VDD2H].iDD2NX = memspec.mempowerspec.idd2n2h;\n memPowerSpec[VDD2H].iDD3NX = memspec.mempowerspec.idd3n2h;\n memPowerSpec[VDD2H].iDD4RX = memspec.mempowerspec.idd4r2h;\n memPowerSpec[VDD2H].iDD4WX = memspec.mempowerspec.idd4w2h;\n memPowerSpec[VDD2H].iDD5X = memspec.mempowerspec.idd52h;\n memPowerSpec[VDD2H].iDD5PBX = memspec.mempowerspec.idd5pb2h;\n memPowerSpec[VDD2H].iDD6X = memspec.mempowerspec.idd62h;\n memPowerSpec[VDD2H].iDD6DSX = memspec.mempowerspec.idd6ds2h;\n memPowerSpec[VDD2H].iDD2PX = memspec.mempowerspec.idd2p2h;\n memPowerSpec[VDD2H].iDD3PX = memspec.mempowerspec.idd3p2h;\n\n memPowerSpec[VDD2L].vDDX = memspec.mempowerspec.vdd2l;\n memPowerSpec[VDD2L].iDD0X = memspec.mempowerspec.idd02l;\n memPowerSpec[VDD2L].iDD2NX = memspec.mempowerspec.idd2n2l;\n memPowerSpec[VDD2L].iDD3NX = memspec.mempowerspec.idd3n2l;\n memPowerSpec[VDD2L].iDD4RX = memspec.mempowerspec.idd4r2l;\n memPowerSpec[VDD2L].iDD4WX = memspec.mempowerspec.idd4w2l;\n memPowerSpec[VDD2L].iDD5X = memspec.mempowerspec.idd52l;\n memPowerSpec[VDD2L].iDD5PBX = memspec.mempowerspec.idd5pb2l;\n memPowerSpec[VDD2L].iDD6X = memspec.mempowerspec.idd62l;\n memPowerSpec[VDD2L].iDD6DSX = memspec.mempowerspec.idd6ds2l;\n memPowerSpec[VDD2L].iDD2PX = memspec.mempowerspec.idd2p2l;\n memPowerSpec[VDD2L].iDD3PX = memspec.mempowerspec.idd3p2l;\n\n vddq = memspec.mempowerspec.vddq;\n\n memPowerSpec[VDD1].iBeta = memspec.mempowerspec.iBeta_vdd1.value_or(memspec.mempowerspec.idd01);\n memPowerSpec[VDD2H].iBeta = memspec.mempowerspec.iBeta_vdd2h.value_or(memspec.mempowerspec.idd02h);\n memPowerSpec[VDD2L].iBeta = memspec.mempowerspec.iBeta_vdd2l.value_or(memspec.mempowerspec.idd02l);\n\n if (memspec.bankwisespec.has_value()) {\n bwParams.bwPowerFactRho = memspec.bankwisespec.value().factRho.value_or(1);\n }\n else {\n bwParams.bwPowerFactRho = 1;\n }\n\n\n auto BankArchError = [this]() {\n std::cout << \"Invalid bank architecture selected\" << std::endl;\n std::cout << \"Selected values:\" << std::endl;\n std::cout << \" - Number of banks: \" << numberOfBanks << std::endl;\n std::cout << \" - Number of bank groups: \" << numberOfBankGroups << std::endl;\n std::cout << \"Valid values are 16|1 (16B mode), 16|4 (BG mode) or 8|1 (8B mode)\" << std::endl;\n std::cout << std::endl << \"Assuming 16B architecture.\" << std::endl;\n bank_arch = BankArchitectureMode::M16B;\n numberOfBanks = 16;\n numberOfBankGroups = 1;\n };\n\n if (numberOfBanks == 16) {\n if (numberOfBankGroups == 1 || numberOfBankGroups == 0) {\n bank_arch = BankArchitectureMode::M16B;\n } else if (numberOfBankGroups == 4) {\n bank_arch = BankArchitectureMode::MBG;\n } else {\n BankArchError();\n }\n } else if (numberOfBanks == 8) {\n if (numberOfBankGroups > 1) {\n BankArchError();\n } else {\n bank_arch = BankArchitectureMode::M8B;\n }\n } else {\n BankArchError();\n }\n\n // Source: LPDDR5 standard; table 312\n memTimingSpec.tBurst = burstLength/(dataRate * memTimingSpec.WCKtoCK);\n\n // Source: LPDDR5 standard; figure 96\n prechargeOffsetRD = memTimingSpec.tBurst + memTimingSpec.tRBTP;\n\n // Source: LPDDR5 standard; figure 97\n prechargeOffsetWR = memTimingSpec.tWL + memTimingSpec.tBurst + 1 + memTimingSpec.tWR;\n\n wckAlwaysOnMode = memspec.memarchitecturespec.WCKalwaysOn;\n\n parseImpedanceSpec(memspec);\n}\n\nvoid MemSpecLPDDR5::parseImpedanceSpec(const DRAMUtils::MemSpec::MemSpecLPDDR5 &memspec) {\n\n memImpedanceSpec = memspec.memimpedancespec;\n}\n\nMemSpecLPDDR5 MemSpecLPDDR5::from_memspec(const DRAMUtils::MemSpec::MemSpecVariant& memSpec)\n{\n return std::get(memSpec.getVariant());\n}\n"
},
{
"path": "src/DRAMPower/DRAMPower/memspec/MemSpecLPDDR5.h",
"content": "#ifndef DRAMPOWER_MEMSPEC_MEMSPECLPDDR5_H\n#define DRAMPOWER_MEMSPEC_MEMSPECLPDDR5_H\n\n#include \"MemSpec.h\"\n#include \n\nnamespace DRAMPower {\n\n class MemSpecLPDDR5 final : public MemSpec {\n public:\n using MemImpedanceSpec = DRAMUtils::MemSpec::MemImpedanceSpecTypeLPDDR5;\n enum VoltageDomain {\n VDD1 = 0,\n VDD2H,\n VDD2L,\n };\n\n enum BankArchitectureMode {\n MBG, // 4 banks, 4 bank groups\n M16B, // 16 banks, no bank groups\n M8B // 8 banks, no bank groups\n };\n\n public:\n MemSpecLPDDR5() = delete;\n\n MemSpecLPDDR5(const DRAMUtils::MemSpec::MemSpecLPDDR5 &memspec);\n\t\n MemSpecLPDDR5(json_t &data) = delete;\n MemSpecLPDDR5(const json_t &data) = delete;\n\n // Copy constructor and assignment operator\n MemSpecLPDDR5(const MemSpecLPDDR5&) = default;\n MemSpecLPDDR5& operator=(const MemSpecLPDDR5&) = default;\n\n // Move constructor and assignment operator\n MemSpecLPDDR5(MemSpecLPDDR5&&) = default;\n MemSpecLPDDR5& operator=(MemSpecLPDDR5&&) = default;\n\n\t ~MemSpecLPDDR5() = default;\n\n uint64_t numberOfBankGroups;\n uint64_t banksPerGroup;\n uint64_t numberOfRanks;\n std::size_t perTwoBankOffset = 8;\n BankArchitectureMode bank_arch;\n bool wckAlwaysOnMode;\n\n double vddq;\n\n // Memspec Variables:\n struct MemTimingSpec\n {\n double fck;\n double tCK;\n double tWCK;\n uint64_t WCKtoCK;\n uint64_t tRAS;\n uint64_t tRCD;\n uint64_t tRL;\n uint64_t tWL;\n uint64_t tWR;\n uint64_t tRFC;\n uint64_t tRFCPB;\n uint64_t tREFI;\n uint64_t tRP;\n uint64_t tRBTP;\n uint64_t tBurst;\n };\n\n // Currents and Voltages:\n struct MemPowerSpec\n {\n double vDDX;\n double iDD0X;\n double iDD2NX;\n double iDD3NX;\n double iDD2PX;\n double iDD3PX;\n double iDD4RX;\n double iDD4WX;\n double iDD5X;\n double iDD5PBX;\n double iDD6X;\n double iDD6DSX;\n double iBeta;\n };\n\n struct BankWiseParams {\n // ACT Standby power factor\n double bwPowerFactRho;\n };\n\n MemTimingSpec memTimingSpec;\n MemImpedanceSpec memImpedanceSpec;\n std::vector memPowerSpec;\n BankWiseParams bwParams;\n\n private:\n void parseImpedanceSpec(const DRAMUtils::MemSpec::MemSpecLPDDR5 &memspec);\n\n public:\n static MemSpecLPDDR5 from_memspec(const DRAMUtils::MemSpec::MemSpecVariant&);\n };\n\n} // namespace DRAMPower\n\n#endif /* DRAMPOWER_MEMSPEC_MEMSPECLPDDR5_H */\n"
},
{
"path": "src/DRAMPower/DRAMPower/simconfig/simconfig.h",
"content": "#ifndef DRAMPOWER_SIMCONFIG_SIMCONFIG_H\n#define DRAMPOWER_SIMCONFIG_SIMCONFIG_H\n\n#include \"DRAMUtils/util/json_utils.h\"\n#include \"DRAMUtils/config/toggling_rate.h\"\n\nnamespace DRAMPower::config {\n\nstruct SimConfig {\n// Public type definitions\npublic:\n using ToggleRateDefinition_t = DRAMUtils::Config::ToggleRateDefinition;\n\n// Public Constructors\npublic:\n SimConfig() = default;\n\n// Public members\npublic:\n std::optional toggleRateDefinition;\n};\nNLOHMANN_JSONIFY_ALL_THINGS(SimConfig, toggleRateDefinition);\n\n} // DRAMPower::config\n\n#endif /* DRAMPOWER_SIMCONFIG_SIMCONFIG_H */\n"
},
{
"path": "src/DRAMPower/DRAMPower/standards/ddr4/DDR4.cpp",
"content": "#include \"DDR4.h\"\n#include \"DRAMPower/Types.h\"\n#include \"DRAMPower/data/stats.h\"\n#include \"DRAMPower/memspec/MemSpecDDR4.h\"\n#include \"DRAMPower/standards/ddr4/DDR4Interface.h\"\n#include \"DRAMPower/standards/ddr4/core_calculation_DDR4.h\"\n#include \"DRAMPower/standards/ddr4/interface_calculation_DDR4.h\"\n#include \"DRAMPower/util/cli_architecture_config.h\"\n\n#include \n#include