[ { "path": "LICENSE", "content": "This work is licensed under the Creative Commons Attribution-ShareAlike 3.0 Unported License.\nTo view a copy of this license, visit http://creativecommons.org/licenses/by-sa/3.0/ or send\na letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA.\n" }, { "path": "README.md", "content": "# USB PD Tester\nThe USB PD Tester is a monitoring and triggering device designed for USB Power Delivery. It allows you to test a wide range of USB Type-C PD power supplies and their corresponding cables. This tool not only displays the capabilities of the power supply on an OLED but also enables you to select one of the available fixed or programmable voltages for output on the screw terminal. With this, it can also be used to power your projects with various selectable voltages and high currents, serving as a versatile variable power supply.\n\nThe USB PD Tester is built around the inexpensive (30 cents at the time of writing) and user-friendly CH32X035 RISC-V microcontroller, which comes with integrated USB 2.0, USB PD 2.0/3.0, and USB Type-C hardware support.\n\n- Project video (Youtube): https://youtu.be/wqLiRnbcISo\n\n![USB_PD_Tester_pic1.jpg](https://raw.githubusercontent.com/wagiminator/CH32X035-USB-PD-Tester/main/documentation/USB_PD_Tester_pic1.jpg)\n\n# USB Power Delivery\nUSB Power Delivery (USB PD) is a protocol that extends the capabilities of standard USB connections, allowing for faster charging and power delivery between devices. USB PD operates through negotiation between the source and sink devices. They exchange information through PDOs, determining the optimal power level for charging or powering the sink device. PPS enhances flexibility by allowing dynamic adjustments, and CC1 and CC2 are the communication channels involved in the negotiation process:\n- Source: The source is a device that provides power, such as a charger or power bank. It can negotiate with the connected device to determine the optimal power level. Here the USB PD power supply to be tested acts as the source.\n- Sink: The sink is a device that consumes power, like a smartphone or laptop. It communicates with the source to negotiate the power it needs for charging or other operations. Here the USB PD Tester acts as the sink.\n- PDO (Power Delivery Object): A PDO is a data structure exchanged between the source and sink during negotiation. It contains information about the available voltage and current levels. The devices negotiate and agree on a mutually supported PDO for power delivery.\n- PPS (Programmable Power Supply): PPS is a feature in USB PD that allows dynamic adjustment of the voltage and current levels during operation. It enables more flexible power delivery based on the specific needs of the connected device.\n- CC1 and CC2 (Configuration Channel 1 and 2): These are the communication channels used by USB Type-C connectors for negotiating power delivery. CC1 and CC2 lines carry information about the capabilities of the devices and facilitate negotiation.\n\n# Hardware\n## Schematic\n![USB_PD_Tester_wiring.png](https://raw.githubusercontent.com/wagiminator/CH32X035-USB-PD-Tester/main/documentation/USB_PD_Tester_wiring.png)\n\n## CH32X035 F7P6 32-bit RISC-V USB Microcontroller\nCH32X035F7P6 is a low-cost microcontroller that utilizes the QingKe 32-bit RISC-V4C core, supporting the RV32IMAC instruction set along with self-extending instructions. This microcontroller comes with a built-in USB PHY, supporting USB2.0 full-speed device functions and a USB PD PHY with source and sink capabilities. It features a programmable protocol I/O controller (PIOC), an operational amplifier (OPA) with programmable gain (PGA), an analog comparator (CMP), a 12-bit analog-to-digital converter (ADC), an 11-channel touch-key controller, 3 groups of USART, I2C, SPI, multiple timers, and various other peripheral resources. The device can operate at clock frequencies of up to 48MHz and is compatible with a supply voltage range of 2.0V to 5.5V. The CH32X035F7P6 includes 48KB of flash, 20KB of SRAM, and an embedded USB bootloader.\n\n## 78L05 Voltage Regulator\nThe 78L05 is a simple and inexpensive voltage regulator that can convert input voltages up to 30V to an output voltage of 5V with an output current of up to 100mA and a dropout voltage of 1.7V. The 78L05 supplies all elements of the circuit with up to 5V.\n\n## SSD1306 OLED Display Module\nA low-cost SSD1306 4-pin I2C 128x64 pixels 0.96-inch OLED module is used as the display device. Make sure to acquire one with the correct pinout!\n\n![USB_PD_Tester_pic2.jpg](https://raw.githubusercontent.com/wagiminator/CH32X035-USB-PD-Tester/main/documentation/USB_PD_Tester_pic2.jpg)\n\n# Software\n## USB Bootloader\n### Installing Drivers for the Bootloader\nOn Linux you do not need to install a driver. However, by default Linux will not expose enough permission to upload your code with the USB bootloader. In order to fix this, open a terminal and run the following commands:\n\n```\necho 'SUBSYSTEM==\"usb\", ATTR{idVendor}==\"4348\", ATTR{idProduct}==\"55e0\", MODE=\"666\"' | sudo tee /etc/udev/rules.d/99-ch55x.rules\necho 'SUBSYSTEM==\"usb\", ATTR{idVendor}==\"1a86\", ATTR{idProduct}==\"55e0\", MODE=\"666\"' | sudo tee -a /etc/udev/rules.d/99-ch55x.rules\nsudo udevadm\n```\n\nFor Windows you can use the [Zadig](https://zadig.akeo.ie/) tool to install the correct driver. Here, click \"Options\" -> \"List All Devices\" and select the USB module. Then install the libusb-win32 driver. To do this, the board must be connected and the microcontroller must be in bootloader mode.\n\n### Entering Bootloader Mode\nThe bootloader must be started manually for new uploads. To do this, the board must first be disconnected from the USB port. Now press the BOOT button and keep it pressed while reconnecting the board to the USB port of your PC. The chip now starts in bootloader mode, the BOOT button can be released and new firmware can be uploaded via USB within the next couple of seconds.\n\n## Compiling and Uploading Firmware using the Makefile\n### Linux\nInstall the toolchain (GCC compiler, Python3, and chprog):\n```\nsudo apt install build-essential libnewlib-dev gcc-riscv64-unknown-elf\nsudo apt install python3 python3-pip\npip install chprog\n```\n\nOpen a terminal and navigate to the folder with the *makefile*. Press the BOOT button and keep it pressed while connecting the board to the USB port of your PC. Run the following command to compile and upload:\n```\nmake flash\n```\n\n### Other Operating Systems\nFollow the instructions on [CNLohr's ch32v003fun page](https://github.com/cnlohr/ch32v003fun/wiki/Installation) to set up the toolchain on your respective operating system (for Windows, use WSL). Also, install [Python3](https://www.pythontutorial.net/getting-started/install-python/) and [chprog](https://pypi.org/project/chprog/). Compile and upload with \"make flash\". Note that I only have Debian-based Linux and have not tested it on other operating systems.\n\n## Compiling and Uploading Firmware using PlatformIO\n- Install [PlatformIO](https://platformio.org) and [platform-ch32v](https://github.com/Community-PIO-CH32V/platform-ch32v). Follow [these instructions](https://pio-ch32v.readthedocs.io/en/latest/installation.html) to do so. Linux/Mac users may also need to install [pyenv](https://realpython.com/intro-to-pyenv).\n- Click on \"Open Project\" and select the firmware folder with the *platformio.ini* file.\n- Press the BOOT button and keep it pressed while connecting the board to the USB port of your PC. Then click \"Upload\".\n\n## Uploading pre-compiled Firmware Binary\nWCH offers the free but closed-source software [WCHISPTool](https://www.wch.cn/downloads/WCHISPTool_Setup_exe.html) to upload firmware with Windows via the USB bootloader. Press the BOOT button and keep it pressed while connecting the board to the USB port of your PC. Release the BOOT button, open the *pd_tester.hex* file in the *bin* folder with WCHISPTool and upload it to the microcontroller.\n\nIf [Python3](https://www.pythontutorial.net/getting-started/install-python/) is installed, you can also use the platform-independent open-source command-line tool [chprog](https://pypi.org/project/chprog/) for uploading:\n```\nchprog bin/pd_tester.bin\n```\n\n# Building Instructions\n1. Take the Gerber files (the *zip* file inside the *hardware* folder) and upload them to a PCB (printed circuit board) manufacturer of your choice (e.g., [JLCPCB](https://jlcpcb.com/)). They will use these files to create the circuit board for your device and send it to you.\n2. Once you have the PCB, you can start soldering the components onto it. Use the BOM (bill of materials) and schematic as a guide to make sure everything is connected correctly. You can find the corresponding files in the *hardware* folder. Remove the plastic part from the pin header of the OLED, trim the pins, and solder the OLED module flush onto the PCB. Do not solder the screw terminal yet.\n3. Print the casing with your 3D printer. You can find the corresponding *stl* files in the *3dprint* folder.\n4. Insert the button extensions into the corresponding holes on the top part of the casing. Insert the circuit board and secure it with 4 self-tightening M2x5mm screws.\n5. Now solder the screw terminal onto the circuit board.\n6. Close the casing with the back panel.\n7. Upload the firmware by following the instructions in the previous section (see above).\n\n![USB_PD_Tester_pic3.jpg](https://raw.githubusercontent.com/wagiminator/CH32X035-USB-PD-Tester/main/documentation/USB_PD_Tester_pic3.jpg)\n\n# Operating Instructions\n1. Connect the USB PD Tester to a USB Type-C PD power supply using a USB-C cable. The available PDOs and their corresponding capabilities are displayed on the OLED.\n2. Utilize the UP and DOWN buttons to choose the desired PDO. A left-angle bracket on the right side serves as the selection indicator. Programmable PDOs, indicated by numbers within square brackets, allow precise adjustments of the output voltage in 20mV steps within the specified range.\n3. Press the SLCT button to activate the chosen PDO. An asterisk on the left side of the PDO confirms the activation.\n4. The selected voltage is now accessible on the screw terminal for further use.\n\n![USB_PD_Tester_pic4.jpg](https://raw.githubusercontent.com/wagiminator/CH32X035-USB-PD-Tester/main/documentation/USB_PD_Tester_pic4.jpg)\n![USB_PD_Tester_pic5.jpg](https://raw.githubusercontent.com/wagiminator/CH32X035-USB-PD-Tester/main/documentation/USB_PD_Tester_pic5.jpg)\n\n# References, Links and Notes\n- [EasyEDA Design Files](https://oshwlab.com/wagiminator)\n- [MCU Templates](https://github.com/wagiminator/MCU-Templates)\n- [MCU Flash Tools](https://github.com/wagiminator/MCU-Flash-Tools)\n- [CH32X035 Datasheets](http://www.wch-ic.com/products/CH32X035.html)\n- [SSD1306 Datasheet](https://cdn-shop.adafruit.com/datasheets/SSD1306.pdf)\n- [78L05 Datasheet](https://datasheet.lcsc.com/lcsc/2209271730_HX-hengjiaxing-78L05_C5181466.pdf)\n- [ATtiny814 USB PD Adapter](https://github.com/wagiminator/ATtiny814-USB-PD-Adapter)\n- [ATtiny412 USB PD Inverter](https://github.com/wagiminator/ATtiny412-USB-PD-Inverter)\n- [TI Primer on USB PD](https://www.ti.com/lit/wp/slyy109b/slyy109b.pdf)\n- [CH32X035 F7P6 on Aliexpress](https://aliexpress.com/item/1005006199310724.html)\n- [128x64 OLED on Aliexpress](https://aliexpress.com/wholesale?SearchText=128+64+0.96+oled)\n\n![USB_PD_Tester_pic6.jpg](https://raw.githubusercontent.com/wagiminator/CH32X035-USB-PD-Tester/main/documentation/USB_PD_Tester_pic6.jpg)\n\n# License\n![license.png](https://i.creativecommons.org/l/by-sa/3.0/88x31.png)\n\nThis work is licensed under Creative Commons Attribution-ShareAlike 3.0 Unported License. \n(http://creativecommons.org/licenses/by-sa/3.0/)\n" }, { "path": "software/pd_tester/bin/pd_tester.hex", "content": ":040000006F108024D9\r\n:10000400000000000000000036020000360200007C\r\n:1000140000000000360200000000000000000000A4\r\n:10002400360200003602000000000000000000005C\r\n:10003400360200000000000036020000000000004C\r\n:100044003602000036020000360200000000000004\r\n:1000540036020000360200003602000036020000BC\r\n:1000640036020000360200003602000036020000AC\r\n:10007400360200003602000036020000360200009C\r\n:10008400360200003602000036020000360200008C\r\n:10009400360200003602000036020000360200007C\r\n:1000A400360200003602000036020000360200006C\r\n:1000B400360200003602000036020000360200005C\r\n:1000C400360200001E08000036020000360200005E\r\n:0C00D40036020000360200003602000078\r\n:1000E000B7F700E09C4737F700E03E951C47898F43\r\n:1000F000E3CE07FE828079714ECE5EC6B70910FF4F\r\n:10010000B70B00F122D426D252CC56CA5AC862C4C8\r\n:1001100066C206D64AD0AA84A14A37140140FD1B04\r\n:10012000370C0003B70C0004FD19370B4000370AE9\r\n:1001300030000327048093978401E18733777701A8\r\n:1001400063DA0708336797012320E48003270480DC\r\n:100150000945FD1A33773701336767012320E480AF\r\n:10016000413703270480860493FAFA0F3377370167\r\n:10017000336747012320E48093F4F40FE39B0AFAEA\r\n:1001800003270480B70700F1FD177D8FB707000430\r\n:100190005D8F2320E480832704800945B3F737016E\r\n:1001A000B3E767012320F480253F83270480B25002\r\n:1001B0009254B3F93701B3E9490123203481225421\r\n:1001C0000259F249624AD24A424BB24B224C924CFB\r\n:1001D000456182803367870185BF411122C437148E\r\n:1001E000014003270480B70700F126C29384F7FF7C\r\n:1001F000658FB707000306C65D8F2320E48009459D\r\n:10020000C53503270480B70710FFFD177D8FB7079B\r\n:1002100040005D8F2320E4800945D9358327048081\r\n:1002200037070004B240E58FD98F2320F4802244A1\r\n:1002300092444101828001A09387C18603C7470190\r\n:1002400083C65701158F1377F70F6368A700DC4744\r\n:100250000A053E950355E5FF8280198D1947330540\r\n:10026000E5029C4B3E950355A5FF82809387C1868E\r\n:1002700003C7470183C65701158F1377F70F6368CC\r\n:10028000A700DC470A053E950355E5FF8280198DDE\r\n:1002900019473305E5029C4B3E950355C5FF828007\r\n:1002A0009387C18603C7470183C65701158F13770C\r\n:1002B000F70F6368A700DC470A053E950355C5FFA5\r\n:1002C0008280198D19473305E5029C4B3E950355F5\r\n:1002D000E5FF8280B77702401307200A2396E700E4\r\n:1002E0002397E7009387C186A3840700238507002F\r\n:1002F00023840700238A0700A38A070023A007009E\r\n:1003000023A207001387418323810702D8C7A38153\r\n:1003100007021387C1802382070298CB0547238BEE\r\n:10032000E70023800702238DE700A38DE700056720\r\n:1003300013078738239EE700239FE7008280B77763\r\n:10034000024003D70700118B21C303D7E700420700\r\n:100350004183136707012397E700B777024013072C\r\n:10036000F0042391E7004205A38207004181239313\r\n:10037000A700A384070003C747001377F70F13678D\r\n:1003800037002382E700828003D7C70042074183FA\r\n:10039000136707012396E700C9B7797122D426D2E3\r\n:1003A0004AD04ECE52CC56CA9387C18606D65AC87A\r\n:1003B0005EC6239F07000569238007029304F00FA0\r\n:1003C0001384C1861309892D93894183138A8181FE\r\n:1003D000834B040293FBFB0F63960B00FD1493F415\r\n:1003E000F40F91ECB25022540259F249624AD24AB7\r\n:1003F000424BB24B3335900092544561828037B501\r\n:10040000030013050598E939B777024003D7C70001\r\n:10041000420741831377E7F1420741832396E700C0\r\n:1004200003D7C70042074183136707042396E700F9\r\n:1004300083D6C70003D7E700C2064207418313777C\r\n:10044000E7F1420741832397E70003D7E700C18222\r\n:1004500042074183136707042397E70083D7E70028\r\n:100460000947858B99E313F7160083578401854666\r\n:100470008507C207C183231CF4001C406393D70483\r\n:100480006318F70823050400834794009546850701\r\n:1004900093F7F70FA304F4008347940093F7F70F43\r\n:1004A00063F1F602A304040089471CC0B77602403A\r\n:1004B00083D70600C207C183ED9BC207C183239087\r\n:1004C000F6001440854763FBD70249E78347840061\r\n:1004D0001547850793F7F70F2304F400834784003B\r\n:1004E00093F7F70F637CF700230404002320040034\r\n:1004F000B7E700E03707020023A2E718032B040048\r\n:100500001C402547636FF7088A07CA979C43828778\r\n:100510008947A3040400631CF7028347A40095469F\r\n:10052000850793F7F70F2305F4008347A40093F79B\r\n:10053000F70FE3F8F6F82305040018C0B776024079\r\n:1005400083D70600C207C18393E747008DBF230509\r\n:10055000040085BF2304040055B7B7E700E0370760\r\n:10056000020023A2E718BD3385471CC01DA85840D0\r\n:100570001C406308F7023777024093077007231186\r\n:10058000F7008347470093F7C70F93E7270023023D\r\n:10059000F700B7E700E0A38807423707020023A26D\r\n:1005A000E710232264012DB58347340293F7F70F38\r\n:1005B000EDDBA3010402B7E700E0370702000328E0\r\n:1005C000C400144823A2E718A30A0400B70800F0E7\r\n:1005D000370300C0294E9305200319461305400632\r\n:1005E0008347440193F7F70F63EAFB00B7E700E0A6\r\n:1005F0003707020023A2E710914785BF13972B000E\r\n:10060000B307EA009C43B3FE170163986E060347E5\r\n:10061000540193DE170193FEFE0F1377F70F330794\r\n:10062000C702B38EAE0236972311D7010347540198\r\n:1006300093DE870093FEFE0F1377F70F3307C70291\r\n:1006400093F7F707B38EAE0236972310D70103470F\r\n:100650005401B387B7021377F70F3307C7023697F2\r\n:100660002312F70083475401850793F7F70FA30A76\r\n:10067000F400850B93FBFB0FA5B793FEF73FA9830F\r\n:1006800093F7F73FB38ECE034297B387B702231099\r\n:10069000D7012311F700F1BF58401C406300F70C4D\r\n:1006A0008347A401834624020565130725009D8A1C\r\n:1006B000A606D98E21671307F7E1F98E0347640177\r\n:1006C00093F6F6F313F6F70F0D8B1A07D98E03473F\r\n:1006D0004401034854019395C7011377F70F13782A\r\n:1006E000F80F330707416355C7088357C4015147C3\r\n:1006F000C207C183B3D7E7021307F5FFF98FA60737\r\n:1007000003475401CD8F834544011377F70F329788\r\n:1007100093F5F50F0D8F19467D173307C702138622\r\n:10072000C180329703574700130620033357C7028F\r\n:10073000370600031377F707518F370600FD1306BE\r\n:1007400006F8F18FD98F138781842311F700C183B5\r\n:100750002310D7002312F7001945D53683474402EA\r\n:1007600093F7F70FE38F07E2230204029547F5BBE7\r\n:100770001307F6FF0A074E9703570700A9473706E6\r\n:1007800000033357F7021377F73F9317A700518FF2\r\n:100790005D8FB367B70045BF8347340293F7F70F08\r\n:1007A000E38107E0A3010402A5471CC0231C040049\r\n:1007B000CDBB85472300F4020347A4018347B4015E\r\n:1007C0001377F70F93F7F70F631CF7000357C40174\r\n:1007D0008357E4014207C2074183C183E303F7DC87\r\n:1007E0008347A401094593F7F70FA30DF40083573E\r\n:1007F000C401C207C183231FF400230004028347FE\r\n:100800002402034764019D8BA6070D8B1A0793E70B\r\n:100810007700D98F2394F1841D36A947B9B35D7150\r\n:100820003ED0B77702403AD203C7970086C696C437\r\n:100830009AC29EC022DE26DC2ADA2ED832D636D4E0\r\n:1008400042CE46CC4ACA72C876C67AC47EC21377F4\r\n:10085000070235CB03C7970085460D8B631BD70472\r\n:1008600083D7A7009546C207C18363F4F60403D477\r\n:1008700081841389818493160401C1869384C1867F\r\n:1008800063CE060E1D66618E9376F4016310061228\r\n:100890008D476383F60E99476388F6106390E60EE2\r\n:1008A0002382D40283C72402850793F7F70F23819D\r\n:1008B000F402377702408347970093F7F70F93E7E7\r\n:1008C0000702A304F700B777024003C79700620747\r\n:1008D0006187635D070403D7C700854642074183EC\r\n:1008E0003D9B420741832396E70003D7E700420779\r\n:1008F00041833D9B420741832397E700130770071D\r\n:100900002391E70003C747001377C70F136727003A\r\n:100910002382E7001387C186A301D70203C797008C\r\n:10092000136707F81377F70FA384E70037770240C0\r\n:100930008347970093F7070491CB8347970093F77A\r\n:10094000F70F93E70704A304F70069327254B64027\r\n:10095000A64216438643E2545255C2553256A25619\r\n:10096000125782577248E2485249424EB24E224FC5\r\n:10097000924F6161730020309D479CC01305005A5F\r\n:10098000EFF00FF6A381040203C7640193579400AC\r\n:100990009D8BA6070D8B1A0793E71700D98F094582\r\n:1009A0002310F900693A31B7A147C1BFE398E6FCCB\r\n:1009B0000D4798C01357C4001D8B238AE4001357BA\r\n:1009C00064000D8B238BE40093878184014771467B\r\n:1009D000938681818507E303C7FA03C51700B385B2\r\n:1009E000E60005072380A500F5B7411122C437149E\r\n:1009F000014083270480370700F17D17F98F3707FF\r\n:100A0000000306C6D98F2320F4800945EFF04FED8F\r\n:100A100083270480370710FF7D17F98F37073000D1\r\n:100A2000D98F2320F4802244B2401305800741016E\r\n:100A30006FF06FEC411122C426C206C69D47AA84FE\r\n:100A4000014463E3B7002E8423849180A3848180D2\r\n:100A5000693F0145EFF02FEA130404FB1375F40F0F\r\n:100A6000EFF06FE913F5F400EFF0EFE813D5440071\r\n:100A700013650501EFF02FE82244B2409244410192\r\n:100A80006FF0AFF5411122C44AC006C626C2214408\r\n:100A90001309F00F7D141374F40F63182401B2408E\r\n:100AA00022449244024941018280A285014559377E\r\n:100AB0002D3F13050004EFF00FE493040008FD142C\r\n:100AC000014593F4F40FEFF00FE3F5F8EFF0EFF0DA\r\n:100AD000A285014585377DBF011501114205418180\r\n:100AE0004EC603C7818022CC131425002A944204E9\r\n:100AF00006CE26CA4AC89307A00741809389818001\r\n:100B000063F9E70083C591800145850593F5F50FED\r\n:100B10001537E13D13050004EFF0EFDD93045400B9\r\n:100B20000145C2040569EFF00FDDC1801309093AE0\r\n:100B3000A287CA97050403C5070042044180EFF06D\r\n:100B40008FDBE39784FEEFF04FE983C70900F240A3\r\n:100B5000624499072380F900D2444249B2490561B1\r\n:100B60008280AA8793F707061375F50791C3ADB77F\r\n:100B7000A9476319F50083C59180850593F5F50FA5\r\n:100B800001454DBDB5476315F50083C59180CDBFC7\r\n:100B90008280014863DC0500B305B040E205E185D1\r\n:100BA000635605003305A0401308D00293080002E5\r\n:100BB000635806003306C04062066186930800034E\r\n:100BC000D1478146254E63D3C70A8280BE86B3775C\r\n:100BD000B50213F7F70F6370FE0813077703335559\r\n:100BE000B50200101377F70F3303D4009387160074\r\n:100BF0002306E3FE93F7F70F71F9630C0800130760\r\n:100C000000036388E800A2978906238607FF93F70D\r\n:100C1000F60F3E8763C4C704630D08009306000304\r\n:100C20006399D80014108507369793F7F70F2306BA\r\n:100C300007FF1384F7FF64001374F40F2694034531\r\n:100C400004000537A2877D14E39BF4FEB2502254C2\r\n:100C50009254456182801307070351B7141085072A\r\n:100C6000369793F7F70F230617FF65B7797106D606\r\n:100C700022D426D2A9BF411122C4370400208345C3\r\n:100C8000140026C2AA84FD1593F5F50F13058007FD\r\n:100C900006C64D331305000281351387C18683468E\r\n:100CA00047019307140093F6F60F63F49602054785\r\n:100CB0002380E70083C5070013058007FD1593F522\r\n:100CC000F50F8D3B2244B24092441305C00341010D\r\n:100CD00021B581E403474701E1BF23809700D9BFD5\r\n:100CE000411126C2B70400209384040083C5040088\r\n:100CF00022C42A84FD1593F5F50F014506C61D3B58\r\n:100D000013050002D13B9305F4FF014593F5F50F60\r\n:100D10002380840005332244B24092441305A0028C\r\n:100D200041015DBB1D7126DAA40022DC4ED652D4EF\r\n:100D300056D25AD05ECE62CC06DE4AD82E84B2C4D9\r\n:100D4000B6C6BAC8BECAC2CCC6CE26C69309500221\r\n:100D5000130A0003A54A294B930B3007130C3006E6\r\n:100D60000345040009EDF2506254D2544259B2597D\r\n:100D7000225A925A025BF24B624C256182806306D2\r\n:100D800035010504F93B2689A1A883471400638C2B\r\n:100D9000370109040147639647018347040005476B\r\n:100DA0000504014639A8130550023D33834724004A\r\n:100DB0000D04CDB7B30766030504B6973E96834787\r\n:100DC000F4FF938607FDE3F7DAFE19C33306C0404C\r\n:100DD000639D770113894400844003C5040019E131\r\n:100DE000CA84BDBF8504B53BCDBF6398870103C5E9\r\n:100DF000040013894400B533E5B7B5D7130750078E\r\n:100E00006389E70213074006638DE7001307800735\r\n:100E10006387E702130720068945638DE7007D1489\r\n:100E20009DB76206138944006186D9558840953381\r\n:100E300045BFA9456206138944006186C5BFC14507\r\n:100E4000D5BF4111B70700204AC003C9170026C209\r\n:100E5000AA844A8522C406C6EFF00FBE13842180FF\r\n:100E6000636895024A85EFF02FBD2310A4009945D1\r\n:100E70007945C936035604002244B24092440249DF\r\n:100E80008565056593850530130525B6410159BD76\r\n:100E90004A85EFF0AFBD63E6A4004A85EFF00FBDD1\r\n:100EA000E9B723109400E1B7797126D256CAB70486\r\n:100EB000004022D44AD04ECE52CC06D60544D93674\r\n:100EC000938AC18605698569FD14056A83C74A014D\r\n:100ED00093F7F70F63F48702B707002003C51700E5\r\n:100EE000593BB70700202254B25092540259F2499C\r\n:100EF000624AD24A03C507004561DDB383C74A0190\r\n:100F000003C75A01998F93F7F70F63EA870203A784\r\n:100F1000CA00B30794008A07BA9783D627002285B0\r\n:100F200036C6EFF0EFB7B2462A8722869305CA305D\r\n:100F3000130529B60504FD331374F40F41BF228550\r\n:100F4000EFF08FAF2AC62285EFF04FB2B2462A8764\r\n:100F5000228693850932E9BFB717014003A70780AE\r\n:100F6000B70610FFFD167971758FB706400006D6DB\r\n:100F700022D426D24AD04ECE52CC56CA5AC85EC6C9\r\n:100F800062C466C26AC0558F23A0E78003A70780AA\r\n:100F9000B70600F1FD16758FB7060004558F13864E\r\n:100FA000078023A0E780930700025CCA37A52400CE\r\n:100FB000930700045CCA130505F0EFF06F92353417\r\n:100FC000014505690144EFF00F9381441309095865\r\n:100FD000AD49B307990003C507008504EFF0AF9151\r\n:100FE000E39934FFEFF06F9F713C05698565938548\r\n:100FF0004533130529B63D33B7170240984FB7065E\r\n:101000000200B71401401367170198CFD84BCA8A62\r\n:10101000558FD8CB83A744C0B7060044370701409B\r\n:10102000A207A183D58F23A2F4C01C4F93E70730FA\r\n:101030001CCF93878184C20737770240C18323186E\r\n:10104000F700F977A1072310F700F157A304F70081\r\n:10105000EFF0AFB401E9856593854534130529B6F2\r\n:10106000D13101A0913583A70480B706F1FFFD16A9\r\n:10107000C19B93E7870023A0F480854723A8F480D1\r\n:1010800083A70480B70B002093F7F7F093E70708D6\r\n:1010900023A0F480894723A8F48083A70480938940\r\n:1010A000C186856CF58FB7060800D58F23A0F48024\r\n:1010B000C14723A8F480056DB714014083A784803D\r\n:1010C000858B85CF83A78480898B99EB03C51B0013\r\n:1010D00005051375F50F453683A78480898BEDDFF1\r\n:1010E00083A78480C18B8DC7EFF02FAB37550700E6\r\n:1010F00013050530EFE0DFFED1B703C51B007D15FA\r\n:101100001375F50F8D3E83A78480858BEDDF5DBF62\r\n:1011100083C7490103C7590103C91B00998F93F77E\r\n:10112000F70F63E7270303A7C90093172900238D4F\r\n:101130002901BA9783D7E7FF239EF900EFF0EFA5C7\r\n:1011400019C14A85713E83A78480C18BEDDF69BFD9\r\n:10115000EFF05F934A869385CC3413852AB6D9364F\r\n:101160004A85EFF06F8D2A8693054D3613852AB692\r\n:10117000553E4A85EFF08F8F85652A8693858537A2\r\n:1011800013852AB645364A85EFF08F9185652A8604\r\n:101190009385C53813852AB6713603D52180138B04\r\n:1011A0002180453183A78480C18BEDDF375A07004A\r\n:1011B00013050A30EFE0DFF2130CF00F130A0A30C8\r\n:1011C00083A784801387048003550B00C18B91EFA4\r\n:1011D000238D2901239EA900EFF02F9C09C5B70795\r\n:1011E000002023802701C931B9BF1C47858B95E7B3\r\n:1011F000510542054181B1317D141374F40F63161A\r\n:1012000084010944EFF06F9965BF83A78480858BC3\r\n:10121000EDFB5285EFE0DFECC5B71C47898B95E30A\r\n:1012200031154205418131397D141374F40FE30AFD\r\n:1012300084FD83A78480898BE9F75285EFE05FEA1C\r\n:10124000E5B7130420037DBF8567938787F597F182\r\n:10125000FF1F9381215B174100201301A1DA7D4517\r\n:10126000731005BC13058008732005308D457390FD\r\n:101270004580130540004D8D731055307390173421\r\n:10128000B70700200567938707001307C7589386A1\r\n:10129000818063E8D702938781801387418963E85F\r\n:1012A000E702B7270240094798C3B717024023A2B5\r\n:1012B000070037F700E0954614C3714798CF7300D5\r\n:1012C000203010431107910723AEC7FED9B791070D\r\n:1012D00023AE07FEE9B700005A050000A205000092\r\n:1012E0006E050000A805000098060000A205000099\r\n:1012F000A2050000A205000098070000B207000048\r\n:101300003E2536646D56203C0000000020282564F0\r\n:10131000292536646D56202535646D412000000076\r\n:10132000205B25645D2536646D562D2535646D562C\r\n:1013300020000000436F6E6E656374696E672E2E29\r\n:101340002E0000004641494C4544000053656C6541\r\n:10135000637420766F6C74616765206F66205B250F\r\n:10136000645D0A006D696E20766F6C746167653A22\r\n:101370002537646D560000006D617820766F6C74BF\r\n:101380006167653A2537646D560000006D6178200D\r\n:1013900063757272656E743A2537646D41000000A2\r\n:1013A000000000000000005F0000000700070014BC\r\n:1013B0007F147F14242A7F2A12231308646236497B\r\n:1013C0005522500004030000001C2241000041226D\r\n:1013D0001C0014083E081408083E0808008060003D\r\n:1013E00000080808080800606000002010080402D7\r\n:1013F0003E5149453E44427F404042615149462268\r\n:10140000414949361814127F102F494949313E4944\r\n:101410004949320301710907364949493626494984\r\n:10142000493E0036360000008068000000081422A3\r\n:1014300000141414141400221408000201510906A7\r\n:101440003E415D555E7C1211127C7F494949363E12\r\n:10145000414141227F4141221C7F494949417F0945\r\n:101460000909013E4149493A7F0808087F41417F07\r\n:1014700041412040413F017F081422417F404040CC\r\n:10148000407F020C027F7F0408107F3E4141413EB5\r\n:101490007F090909063E4141C1BE7F091929462637\r\n:1014A0004949493201017F01013F4040403F1F202F\r\n:1014B00040201F3F4038403F631408146307087002\r\n:1014C00008076151494543007F414100020408106B\r\n:1014D000200041417F000804020408404040404091\r\n:1014E000000609090620545454787F44444438388F\r\n:1014F00044444428384444447F385454541808FE23\r\n:1015000009010218A4A4A4787F0404047800447D8F\r\n:1015100040000080847D00417F10284400417F40CE\r\n:10152000007C047C04787C04040478384444443807\r\n:10153000FC2424241818242424FC7C08040408080F\r\n:1015400054545420043F4440203C4040403C1C2024\r\n:1015500040201C3C4030403C44281028441CA0A0A3\r\n:10156000A07C4464544C4408083641410000FF000C\r\n:101570000041413608080804081008FFFFFFFFFF7C\r\n:0C158000A83F8D142000DA12A1C8AF00B3\r\n:08158C000101881300000000BA\r\n:00000001FF\r\n" }, { "path": "software/pd_tester/config.h", "content": "// ===================================================================================\n// User Configurations\n// ===================================================================================\n\n#pragma once\n\n// Pin definitions\n#define PIN_KEY_UP PA0 // pin connected to UP button (active low)\n#define PIN_KEY_DOWN PA1 // pin connected to DOWN button (active low)\n#define PIN_KEY_SLCT PA4 // pin connected to SELECT button (active low)\n#define PIN_SCL PA5 // I2C SCL connected to OLED\n#define PIN_SDA PA6 // I2C SDA connected to OLED\n#define PIN_LED PB1 // pin connected to LED (active low)\n\n// If using PC18 and/or PC19 for OLED, disable SWJ\n#define DISABLE_SWJ 0 // 0: normal SWJ pins, 1: OLED pins\n\n// MCU supply voltage\n#define USB_VDD 0 // 0: 3.3V, 1: 5V\n" }, { "path": "software/pd_tester/ld/ch32x035.ld", "content": "ENTRY( jump_reset )\n\nMEMORY\n{\n FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 62K\n RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K\n}\n\nSECTIONS\n{\n .init :\n { \n _sinit = .;\n . = ALIGN(4);\n KEEP(*(SORT_NONE(.init.jump)))\n KEEP(*(SORT_NONE(.init.data)))\n . = ALIGN(4);\n _einit = .;\n } >FLASH AT>FLASH\n\n .vector :\n {\n . = ALIGN(4);\n *(.vector);\n . = ALIGN(4);\n } >FLASH AT>FLASH\n\n .text :\n {\n . = ALIGN(4);\n *(.text)\n *(.text.*)\n *(.rodata)\n *(.rodata*)\n *(.glue_7)\n *(.glue_7t)\n *(.gnu.linkonce.t.*)\n . = ALIGN(4);\n } >FLASH AT>FLASH \n\n .fini :\n {\n KEEP(*(SORT_NONE(.fini)))\n . = ALIGN(4);\n } >FLASH AT>FLASH\n\n PROVIDE(_etext = .);\n PROVIDE(_eitcm = .); \n\n .preinit_array :\n {\n PROVIDE_HIDDEN(__preinit_array_start = .);\n KEEP(*(.preinit_array))\n PROVIDE_HIDDEN(__preinit_array_end = .);\n } >FLASH AT>FLASH \n \n .init_array :\n {\n PROVIDE_HIDDEN(__init_array_start = .);\n KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*)SORT_BY_INIT_PRIORITY(.ctors.*)))\n KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors))\n PROVIDE_HIDDEN(__init_array_end = .);\n } >FLASH AT>FLASH \n \n .fini_array :\n {\n PROVIDE_HIDDEN(__fini_array_start = .);\n KEEP(*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))\n KEEP(*(.fini_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .dtors))\n PROVIDE_HIDDEN(__fini_array_end = .);\n } >FLASH AT>FLASH \n \n .ctors :\n {\n KEEP(*crtbegin.o(.ctors))\n KEEP(*crtbegin?.o(.ctors))\n KEEP(*(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors))\n KEEP(*(SORT(.ctors.*)))\n KEEP(*(.ctors))\n } >FLASH AT>FLASH \n \n .dtors :\n {\n KEEP(*crtbegin.o(.dtors))\n KEEP(*crtbegin?.o(.dtors))\n KEEP(*(EXCLUDE_FILE(*crtend.o *crtend?.o) .dtors))\n KEEP(*(SORT(.dtors.*)))\n KEEP(*(.dtors))\n } >FLASH AT>FLASH \n\n .dalign :\n {\n . = ALIGN(4);\n PROVIDE(_data_vma = .);\n } >RAM AT>FLASH \n\n .dlalign :\n {\n . = ALIGN(4); \n PROVIDE(_data_lma = .);\n } >FLASH AT>FLASH\n\n .data :\n {\n . = ALIGN(4);\n *(.gnu.linkonce.r.*)\n *(.data .data.*)\n *(.gnu.linkonce.d.*)\n . = ALIGN(8);\n PROVIDE(__global_pointer$ = . + 0x800);\n *(.sdata .sdata.*)\n *(.sdata2*)\n *(.gnu.linkonce.s.*)\n . = ALIGN(8);\n *(.srodata.cst16)\n *(.srodata.cst8)\n *(.srodata.cst4)\n *(.srodata.cst2)\n *(.srodata .srodata.*)\n . = ALIGN(4);\n PROVIDE(_edata = .);\n } >RAM AT>FLASH\n\n .bss :\n {\n . = ALIGN(4);\n PROVIDE(_sbss = .);\n *(.sbss*)\n *(.gnu.linkonce.sb.*)\n *(.bss*)\n *(.gnu.linkonce.b.*) \n *(COMMON*)\n . = ALIGN(4);\n PROVIDE(_ebss = .);\n } >RAM AT>FLASH\n\n PROVIDE(_end = _ebss);\n PROVIDE(end = . );\n PROVIDE(_eusrstack = ORIGIN(RAM) + LENGTH(RAM));\t\n}\n" }, { "path": "software/pd_tester/makefile", "content": "# ===================================================================================\n# Project Makefile\n# ===================================================================================\n# Project: USB PD Tester for CH32X035\n# Author: Stefan Wagner\n# Year: 2024\n# URL: https://github.com/wagiminator \n# ===================================================================================\n# Install toolchain:\n# sudo apt install build-essential libnewlib-dev gcc-riscv64-unknown-elf\n# sudo apt install python3 python3-pip\n# pip install chprog\n#\n# Provide access permission to USB bootloader:\n# echo 'SUBSYSTEM==\"usb\", ATTR{idVendor}==\"4348\", ATTR{idProduct}==\"55e0\", MODE=\"666\"' | sudo tee /etc/udev/rules.d/99-ch55x.rules\n# echo 'SUBSYSTEM==\"usb\", ATTR{idVendor}==\"1a86\", ATTR{idProduct}==\"55e0\", MODE=\"666\"' | sudo tee -a /etc/udev/rules.d/99-ch55x.rules\n# sudo udevadm control --reload-rules\n#\n# Set the device to bootloader mode and type \"make flash\" in the command line.\n# ===================================================================================\n\n# Files and Folders\nTARGET = pd_tester\nINCLUDE = include\nSOURCE = src\nBIN = bin\n\n# Microcontroller Settings\nF_CPU = 48000000\nLDSCRIPT = ld/ch32x035.ld\nCPUARCH = -march=rv32imac -mabi=ilp32\n\n# Toolchain\nPREFIX = riscv64-unknown-elf\nCC = $(PREFIX)-gcc\nOBJCOPY = $(PREFIX)-objcopy\nOBJDUMP = $(PREFIX)-objdump\nOBJSIZE = $(PREFIX)-size\nNEWLIB = /usr/include/newlib\nISPTOOL = chprog $(BIN)/$(TARGET).bin\nCLEAN = rm -f *.lst *.obj *.cof *.list *.map *.eep.hex *.o *.d\n\n# Compiler Flags\nCFLAGS = -g -Os -flto -ffunction-sections -fdata-sections -fno-builtin -nostdlib\nCFLAGS += $(CPUARCH) -DF_CPU=$(F_CPU) -I$(NEWLIB) -I$(INCLUDE) -I$(SOURCE) -I. -Wall\nLDFLAGS = -T$(LDSCRIPT) -lgcc -Wl,--gc-sections,--build-id=none\nCFILES = $(wildcard ./*.c) $(wildcard $(SOURCE)/*.c) $(wildcard $(SOURCE)/*.S)\n\n# Symbolic Targets\nhelp:\n\t@echo \"Use the following commands:\"\n\t@echo \"make all compile and build $(TARGET).elf/.bin/.hex/.asm\"\n\t@echo \"make hex compile and build $(TARGET).hex\"\n\t@echo \"make asm compile and disassemble to $(TARGET).asm\"\n\t@echo \"make bin compile and build $(TARGET).bin\"\n\t@echo \"make flash compile and upload to MCU\"\n\t@echo \"make clean remove all build files\"\n\n$(BIN)/$(TARGET).elf: $(CFILES)\n\t@echo \"Building $(BIN)/$(TARGET).elf ...\"\n\t@mkdir -p $(BIN)\n\t@$(CC) -o $@ $^ $(CFLAGS) $(LDFLAGS)\n\n$(BIN)/$(TARGET).lst: $(BIN)/$(TARGET).elf\n\t@echo \"Building $(BIN)/$(TARGET).lst ...\"\n\t@$(OBJDUMP) -S $^ > $(BIN)/$(TARGET).lst\n\n$(BIN)/$(TARGET).map: $(BIN)/$(TARGET).elf\n\t@echo \"Building $(BIN)/$(TARGET).map ...\"\n\t@$(OBJDUMP) -t $^ > $(BIN)/$(TARGET).map\n\n$(BIN)/$(TARGET).bin: $(BIN)/$(TARGET).elf\n\t@echo \"Building $(BIN)/$(TARGET).bin ...\"\n\t@$(OBJCOPY) -O binary $< $(BIN)/$(TARGET).bin\n\n$(BIN)/$(TARGET).hex: $(BIN)/$(TARGET).elf\n\t@echo \"Building $(BIN)/$(TARGET).hex ...\"\n\t@$(OBJCOPY) -O ihex $< $(BIN)/$(TARGET).hex\n\n$(BIN)/$(TARGET).asm: $(BIN)/$(TARGET).elf\n\t@echo \"Disassembling to $(BIN)/$(TARGET).asm ...\"\n\t@$(OBJDUMP) -d $(BIN)/$(TARGET).elf > $(BIN)/$(TARGET).asm\n\nall:\t$(BIN)/$(TARGET).lst $(BIN)/$(TARGET).map $(BIN)/$(TARGET).bin $(BIN)/$(TARGET).hex $(BIN)/$(TARGET).asm size\n\nelf:\t$(BIN)/$(TARGET).elf removetemp size\n\nbin:\t$(BIN)/$(TARGET).bin removetemp size removeelf\n\nhex:\t$(BIN)/$(TARGET).hex removetemp size removeelf\n\nasm:\t$(BIN)/$(TARGET).asm removetemp size removeelf\n\nflash:\t$(BIN)/$(TARGET).bin size removeelf\n\t@echo \"Uploading to MCU ...\"\n\t@$(ISPTOOL)\n\nclean:\n\t@echo \"Cleaning all up ...\"\n\t@$(CLEAN)\n\t@rm -f $(BIN)/$(TARGET).elf $(BIN)/$(TARGET).lst $(BIN)/$(TARGET).map $(BIN)/$(TARGET).bin $(BIN)/$(TARGET).hex $(BIN)/$(TARGET).asm\n\nsize:\n\t@echo \"------------------\"\n\t@echo \"FLASH: $(shell $(OBJSIZE) -d $(BIN)/$(TARGET).elf | awk '/[0-9]/ {print $$1 + $$2}') bytes\"\n\t@echo \"SRAM: $(shell $(OBJSIZE) -d $(BIN)/$(TARGET).elf | awk '/[0-9]/ {print $$2 + $$3}') bytes\"\n\t@echo \"------------------\"\n\nremovetemp:\n\t@echo \"Removing temporary files ...\"\n\t@$(CLEAN)\n\nremoveelf:\n\t@echo \"Removing $(BIN)/$(TARGET).elf ...\"\n\t@rm -f $(BIN)/$(TARGET).elf\n" }, { "path": "software/pd_tester/platformio.ini", "content": "; ===================================================================================\n; PlatformIO Project Configuration File\n; ===================================================================================\n; Project: USB PD Tester for CH32X035\n; Author: Stefan Wagner\n; Year: 2024\n; URL: https://github.com/wagiminator\n; ===================================================================================\n; Install PlatformIO and CH32V:\n; https://pio-ch32v.readthedocs.io/en/latest/\n; https://github.com/Community-PIO-CH32V/platform-ch32v\n; ===================================================================================\n\n[env:CH32X035]\nplatform = https://github.com/Community-PIO-CH32V/platform-ch32v.git\nboard = genericCH32X035F7P6\n\nbuild_flags = -I. -D F_CPU=48000000\nboard_build.ldscript = $PROJECT_DIR/ld/ch32x035.ld\nboard_build.use_lto = yes\n\nupload_protocol = minichlink\nupload_command = pip install chprog && chprog $SOURCE\n" }, { "path": "software/pd_tester/src/ch32x035.h", "content": "// ===================================================================================\n// Header file for CH32X035/X034/X033 * v0.6 *\n// ===================================================================================\n// This contains a copy of ch32x035.h and core_riscv.h and other misc functions.\n// NOTE: This file includes modifications by Stefan Wagner.\n/********************************** (C) COPYRIGHT *******************************\n * File Name : ch32x035.h\n * Author : WCH\n * Version : V1.0.0\n * Date : 2023/04/06\n * Description : CH32X035 Device Peripheral Access Layer Header File.\n *********************************************************************************\n * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.\n * Attention: This software (modified or not) and binary are used for\n * microcontroller manufactured by Nanjing Qinheng Microelectronics.\n *******************************************************************************/\n \n#pragma once\n\n/* MCU definitions */\n#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */\n#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */\n\n#ifdef __ASSEMBLER__\n#define HSI_VALUE (48000000) /* Value of the internal oscillator in Hz */\n#else\n\n#define HSI_VALUE ((uint32_t)48000000) /* Value of the internal oscillator in Hz */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n#include \n\n/* Interrupt Number Definition, according to the selected device */\ntypedef enum IRQn\n{\n /****** RISC-V Processor Exceptions Numbers ***************************************/\n NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */\n EXC_IRQn = 3, /* 3 Exception Interrupt */\n Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */\n Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */\n Break_Point_IRQn = 9, /* 9 Break Point Interrupt */\n SysTicK_IRQn = 12, /* 12 System timer Interrupt */\n Software_IRQn = 14, /* 14 software Interrupt */\n\n /****** RISC-V specific Interrupt Numbers *****************************************/\n WWDG_IRQn = 16, /* Window WatchDog Interrupt */\n PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */\n FLASH_IRQn = 18, /* FLASH global Interrupt */\n EXTI7_0_IRQn = 20, /* External Line[7:0] Interrupts */\n AWU_IRQn = 21, /* AWU global Interrupt */\n DMA1_Channel1_IRQn = 22, /* DMA1 Channel 1 global Interrupt */\n DMA1_Channel2_IRQn = 23, /* DMA1 Channel 2 global Interrupt */\n DMA1_Channel3_IRQn = 24, /* DMA1 Channel 3 global Interrupt */\n DMA1_Channel4_IRQn = 25, /* DMA1 Channel 4 global Interrupt */\n DMA1_Channel5_IRQn = 26, /* DMA1 Channel 5 global Interrupt */\n DMA1_Channel6_IRQn = 27, /* DMA1 Channel 6 global Interrupt */\n DMA1_Channel7_IRQn = 28, /* DMA1 Channel 7 global Interrupt */\n ADC1_IRQn = 29, /* ADC1 global Interrupt */\n I2C1_EV_IRQn = 30, /* I2C1 Event Interrupt */\n I2C1_ER_IRQn = 31, /* I2C1 Error Interrupt */\n USART1_IRQn = 32, /* USART1 global Interrupt */\n SPI1_IRQn = 33, /* SPI1 global Interrupt */\n TIM1_BRK_IRQn = 34, /* TIM1 Break Interrupt */\n TIM1_UP_IRQn = 35, /* TIM1 Update Interrupt */\n TIM1_TRG_COM_IRQn = 36, /* TIM1 Trigger and Commutation Interrupt */\n TIM1_CC_IRQn = 37, /* TIM1 Capture Compare Interrupt */\n TIM2_UP_IRQn = 38, /* TIM2 Update Interrupt */\n USART2_IRQn = 39, /* USART2 global Interrupt */\n EXTI15_8_IRQn = 40, /* External Line[15:8] Interrupts */\n EXTI25_16_IRQn = 41, /* External Line[25:16] Interrupts */\n USART3_IRQn = 42, /* USART3 global Interrupt */\n USART4_IRQn = 43, /* USART4 global Interrupt */\n DMA1_Channel8_IRQn = 44, /* DMA1 Channel 8 global Interrupt */\n USBFS_IRQn = 45, /* USBFS Host/Device global Interrupt */\n USBFSWakeUp_IRQn = 46, /* USBFS Host/Device WakeUp Interrupt */\n PIOC_IRQn = 47, /* PIOC global Interrupt */\n OPA_IRQn = 48, /* OPA global Interrupt */\n USBPD_IRQn = 49, /* USBPD global Interrupt */\n USBPDWakeUp_IRQn = 50, /* USBPD WakeUp Interrupt */\n TIM2_CC_IRQn = 51, /* TIM2 Capture Compare Interrupt */\n TIM2_TRG_COM_IRQn = 52, /* TIM2 Trigger and Commutation Interrupt */\n TIM2_BRK_IRQn = 53, /* TIM2 Break Interrupt */\n TIM3_IRQn = 54, /* TIM3 global Interrupt */\n} IRQn_Type;\n\n#define HardFault_IRQn EXC_IRQn\n\n/* IO definitions */\n#ifdef __cplusplus\n #define __I volatile /*!< defines 'read only' permissions */\n#else\n #define __I volatile const /*!< defines 'read only' permissions */\n#endif\n#define __O volatile /*!< defines 'write only' permissions */\n#define __IO volatile /*!< defines 'read / write' permissions */\n\n/* define compiler specific symbols */\n#define __ASM __asm /*!< asm keyword for GNU Compiler */\n#define __INLINE inline /*!< inline keyword for GNU Compiler */\n\n#define RV_STATIC_INLINE static inline\n\ntypedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus;\ntypedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\ntypedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\n\n/* Analog to Digital Converter */\ntypedef struct\n{\n __IO uint32_t STATR;\n __IO uint32_t CTLR1;\n __IO uint32_t CTLR2;\n __IO uint32_t SAMPTR1;\n __IO uint32_t SAMPTR2;\n __IO uint32_t IOFR1;\n __IO uint32_t IOFR2;\n __IO uint32_t IOFR3;\n __IO uint32_t IOFR4;\n __IO uint32_t WDHTR;\n __IO uint32_t WDLTR;\n __IO uint32_t RSQR1;\n __IO uint32_t RSQR2;\n __IO uint32_t RSQR3;\n __IO uint32_t ISQR;\n __IO uint32_t IDATAR1;\n __IO uint32_t IDATAR2;\n __IO uint32_t IDATAR3;\n __IO uint32_t IDATAR4;\n __IO uint32_t RDATAR;\n __IO uint32_t CTLR3;\n __IO uint32_t WDTR1;\n __IO uint32_t WDTR2;\n __IO uint32_t WDTR3;\n} ADC_TypeDef;\n\n/* DMA Channel Controller */\ntypedef struct\n{\n __IO uint32_t CFGR;\n __IO uint32_t CNTR;\n __IO uint32_t PADDR;\n __IO uint32_t MADDR;\n} DMA_Channel_TypeDef;\n\n/* DMA Controller */\ntypedef struct\n{\n __IO uint32_t INTFR;\n __IO uint32_t INTFCR;\n} DMA_TypeDef;\n\n/* External Interrupt/Event Controller */\ntypedef struct\n{\n __IO uint32_t INTENR;\n __IO uint32_t EVENR;\n __IO uint32_t RTENR;\n __IO uint32_t FTENR;\n __IO uint32_t SWIEVR;\n __IO uint32_t INTFR;\n} EXTI_TypeDef;\n\n/* FLASH Registers */\ntypedef struct\n{\n __IO uint32_t ACTLR;\n __IO uint32_t KEYR;\n __IO uint32_t OBKEYR;\n __IO uint32_t STATR;\n __IO uint32_t CTLR;\n __IO uint32_t ADDR;\n uint32_t RESERVED;\n __IO uint32_t OBR;\n __IO uint32_t WPR;\n __IO uint32_t MODEKEYR;\n __IO uint32_t BOOT_MODEKEYR;\n} FLASH_TypeDef;\n\n/* Option Bytes Registers */\ntypedef struct\n{\n __IO uint16_t RDPR;\n __IO uint16_t USER;\n __IO uint16_t Data0;\n __IO uint16_t Data1;\n __IO uint16_t WRPR0;\n __IO uint16_t WRPR1;\n __IO uint16_t WRPR2;\n __IO uint16_t WRPR3;\n} OB_TypeDef;\n\n/* General Purpose I/O */\ntypedef struct\n{\n __IO uint32_t CFGLR;\n __IO uint32_t CFGHR;\n __IO uint32_t INDR;\n __IO uint32_t OUTDR;\n __IO uint32_t BSHR;\n __IO uint32_t BCR;\n __IO uint32_t LCKR;\n __IO uint32_t CFGXR;\n __IO uint32_t BSXR;\n} GPIO_TypeDef;\n\n/* Alternate Function I/O */\ntypedef struct\n{\n uint32_t RESERVED0;\n __IO uint32_t PCFR1;\n __IO uint32_t EXTICR[2];\n uint32_t RESERVED1;\n uint32_t RESERVED2;\n __IO uint32_t CTLR;\n} AFIO_TypeDef;\n\n/* Inter Integrated Circuit Interface */\ntypedef struct\n{\n __IO uint16_t CTLR1;\n uint16_t RESERVED0;\n __IO uint16_t CTLR2;\n uint16_t RESERVED1;\n __IO uint16_t OADDR1;\n uint16_t RESERVED2;\n __IO uint16_t OADDR2;\n uint16_t RESERVED3;\n __IO uint16_t DATAR;\n uint16_t RESERVED4;\n __IO uint16_t STAR1;\n uint16_t RESERVED5;\n __IO uint16_t STAR2;\n uint16_t RESERVED6;\n __IO uint16_t CKCFGR;\n uint16_t RESERVED7;\n} I2C_TypeDef;\n\n/* Independent WatchDog */\ntypedef struct\n{\n __IO uint32_t CTLR;\n __IO uint32_t PSCR;\n __IO uint32_t RLDR;\n __IO uint32_t STATR;\n} IWDG_TypeDef;\n\n/* Power Control */\ntypedef struct\n{\n __IO uint32_t CTLR;\n __IO uint32_t CSR;\n} PWR_TypeDef;\n\n/* Reset and Clock Control */\ntypedef struct\n{\n __IO uint32_t CTLR;\n __IO uint32_t CFGR0;\n __IO uint32_t RESERVED0;\n __IO uint32_t APB2PRSTR;\n __IO uint32_t APB1PRSTR;\n __IO uint32_t AHBPCENR;\n __IO uint32_t APB2PCENR;\n __IO uint32_t APB1PCENR;\n __IO uint32_t RESERVED1;\n __IO uint32_t RSTSCKR;\n __IO uint32_t AHBRSTR;\n} RCC_TypeDef;\n\n/* Serial Peripheral Interface */\ntypedef struct\n{\n __IO uint16_t CTLR1;\n uint16_t RESERVED0;\n __IO uint16_t CTLR2;\n uint16_t RESERVED1;\n __IO uint16_t STATR;\n uint16_t RESERVED2;\n __IO uint16_t DATAR;\n uint16_t RESERVED3;\n __IO uint16_t CRCR;\n uint16_t RESERVED4;\n __IO uint16_t RCRCR;\n uint16_t RESERVED5;\n __IO uint16_t TCRCR;\n uint16_t RESERVED6;\n uint32_t RESERVED7;\n uint32_t RESERVED8;\n __IO uint16_t HSCR;\n uint16_t RESERVED9;\n} SPI_TypeDef;\n\n/* TIM */\ntypedef struct\n{\n __IO uint16_t CTLR1;\n uint16_t RESERVED0;\n __IO uint16_t CTLR2;\n uint16_t RESERVED1;\n __IO uint16_t SMCFGR;\n uint16_t RESERVED2;\n __IO uint16_t DMAINTENR;\n uint16_t RESERVED3;\n __IO uint16_t INTFR;\n uint16_t RESERVED4;\n __IO uint16_t SWEVGR;\n uint16_t RESERVED5;\n __IO uint16_t CHCTLR1;\n uint16_t RESERVED6;\n __IO uint16_t CHCTLR2;\n uint16_t RESERVED7;\n __IO uint16_t CCER;\n uint16_t RESERVED8;\n __IO uint16_t CNT;\n uint16_t RESERVED9;\n __IO uint16_t PSC;\n uint16_t RESERVED10;\n __IO uint16_t ATRLR;\n uint16_t RESERVED11;\n __IO uint16_t RPTCR;\n uint16_t RESERVED12;\n __IO uint16_t CH1CVR;\n uint16_t RESERVED13;\n __IO uint16_t CH2CVR;\n uint16_t RESERVED14;\n __IO uint16_t CH3CVR;\n uint16_t RESERVED15;\n __IO uint16_t CH4CVR;\n uint16_t RESERVED16;\n __IO uint16_t BDTR;\n uint16_t RESERVED17;\n __IO uint16_t DMACFGR;\n uint16_t RESERVED18;\n __IO uint16_t DMAADR;\n uint16_t RESERVED19;\n __IO uint16_t SPEC;\n uint16_t RESERVED20;\n} TIM_TypeDef;\n\n/* Universal Synchronous Asynchronous Receiver Transmitter */\ntypedef struct\n{\n __IO uint16_t STATR;\n uint16_t RESERVED0;\n __IO uint16_t DATAR;\n uint16_t RESERVED1;\n __IO uint16_t BRR;\n uint16_t RESERVED2;\n __IO uint16_t CTLR1;\n uint16_t RESERVED3;\n __IO uint16_t CTLR2;\n uint16_t RESERVED4;\n __IO uint16_t CTLR3;\n uint16_t RESERVED5;\n __IO uint16_t GPR;\n uint16_t RESERVED6;\n} USART_TypeDef;\n\n/* Window WatchDog */\ntypedef struct\n{\n __IO uint32_t CTLR;\n __IO uint32_t CFGR;\n __IO uint32_t STATR;\n} WWDG_TypeDef;\n\n/* OPA Registers */\ntypedef struct\n{\n __IO uint16_t CFGR1;\n __IO uint16_t CFGR2;\n __IO uint32_t CTLR1;\n __IO uint32_t CTLR2;\n __IO uint32_t OPAKEY;\n __IO uint32_t CMPKEY;\n __IO uint32_t POLLKEY;\n} OPA_TypeDef;\n\n/* AWU Registers */\ntypedef struct\n{\n __IO uint32_t CSR;\n __IO uint32_t WR;\n __IO uint32_t PSC;\n} AWU_TypeDef;\n\n/* USBPD Registers */\ntypedef struct\n{\n union {\n __IO uint32_t USBPD_CONFIG;\n struct {\n __IO uint16_t CONFIG;\n __IO uint16_t BMC_CLK_CNT;\n };\n };\n union {\n __IO uint32_t USBPD_CONTROL;\n struct {\n union {\n __IO uint16_t R16_CONTROL;\n struct {\n __IO uint8_t CONTROL;\n __IO uint8_t TX_SEL;\n };\n };\n __IO uint16_t BMC_TX_SZ;\n };\n };\n union {\n __IO uint32_t USBPD_STATUS;\n struct {\n union {\n __IO uint16_t R16_STATUS;\n struct {\n __IO uint8_t DATA_BUF;\n __IO uint8_t STATUS;\n };\n };\n __IO uint16_t BMC_BYTE_CNT;\n };\n };\n union {\n __IO uint32_t USBPD_PORT;\n struct {\n __IO uint16_t PORT_CC1;\n __IO uint16_t PORT_CC2;\n };\n };\n union {\n __IO uint32_t USBPD_DMA;\n struct {\n __IO uint16_t DMA;\n __IO uint16_t RESERVED;\n };\n };\n} USBPD_TypeDef;\n\n/* USBFS Registers */\ntypedef struct\n{\n __IO uint8_t BASE_CTRL;\n __IO uint8_t UDEV_CTRL;\n __IO uint8_t INT_EN;\n __IO uint8_t DEV_ADDR;\n uint8_t RESERVED0;\n __IO uint8_t MIS_ST;\n __IO uint8_t INT_FG;\n __IO uint8_t INT_ST;\n __IO uint16_t RX_LEN;\n uint16_t RESERVED1;\n __IO uint8_t UEP4_1_MOD;\n __IO uint8_t UEP2_3_MOD;\n __IO uint8_t UEP567_MOD;\n uint8_t RESERVED2;\n __IO uint32_t UEP0_DMA;\n __IO uint32_t UEP1_DMA;\n __IO uint32_t UEP2_DMA;\n __IO uint32_t UEP3_DMA;\n union {\n __IO uint32_t UEP0_CTRL;\n struct {\n __IO uint16_t UEP0_TX_LEN;\n __IO uint16_t UEP0_CTRL_H;\n };\n };\n union {\n __IO uint32_t UEP1_CTRL;\n struct {\n __IO uint16_t UEP1_TX_LEN;\n __IO uint16_t UEP1_CTRL_H;\n };\n };\n union {\n __IO uint32_t UEP2_CTRL;\n struct {\n __IO uint16_t UEP2_TX_LEN;\n __IO uint16_t UEP2_CTRL_H;\n };\n };\n union {\n __IO uint32_t UEP3_CTRL;\n struct {\n __IO uint16_t UEP3_TX_LEN;\n __IO uint16_t UEP3_CTRL_H;\n };\n };\n union {\n __IO uint32_t UEP4_CTRL;\n struct {\n __IO uint16_t UEP4_TX_LEN;\n __IO uint16_t UEP4_CTRL_H;\n };\n };\n uint32_t RESERVED3;\n uint32_t RESERVED4;\n uint32_t RESERVED5;\n uint32_t RESERVED6;\n uint32_t RESERVED7;\n uint32_t RESERVED8;\n uint32_t RESERVED9;\n uint32_t RESERVED10;\n __IO uint32_t UEP5_DMA;\n __IO uint32_t UEP6_DMA;\n __IO uint32_t UEP7_DMA;\n uint32_t RESERVED11;\n union {\n __IO uint32_t UEP5_CTRL;\n struct {\n __IO uint16_t UEP5_TX_LEN;\n __IO uint16_t UEP5_CTRL_H;\n };\n };\n union {\n __IO uint32_t UEP6_CTRL;\n struct {\n __IO uint16_t UEP6_TX_LEN;\n __IO uint16_t UEP6_CTRL_H;\n };\n };\n union {\n __IO uint32_t UEP7_CTRL;\n struct {\n __IO uint16_t UEP7_TX_LEN;\n __IO uint16_t UEP7_CTRL_H;\n };\n };\n __IO uint32_t UEPX_MOD;\n} USBFSD_TypeDef;\n\ntypedef struct\n{\n __IO uint8_t BASE_CTRL;\n __IO uint8_t HOST_CTRL;\n __IO uint8_t INT_EN;\n __IO uint8_t DEV_ADDR;\n uint8_t RESERVED0;\n __IO uint8_t MIS_ST;\n __IO uint8_t INT_FG;\n __IO uint8_t INT_ST;\n __IO uint16_t RX_LEN;\n uint16_t RESERVED1;\n uint8_t RESERVED2;\n __IO uint8_t HOST_EP_MOD;\n uint16_t RESERVED3;\n uint32_t RESERVED4;\n uint32_t RESERVED5;\n __IO uint16_t HOST_RX_DMA;\n uint16_t RESERVED6;\n __IO uint16_t HOST_TX_DMA;\n uint16_t RESERVED7;\n uint32_t RESERVED8;\n uint16_t RESERVED9;\n __IO uint8_t HOST_SETUP;\n uint8_t RESERVED10;\n __IO uint8_t HOST_EP_PID;\n uint8_t RESERVED11;\n __IO uint8_t HOST_RX_CTRL;\n uint8_t RESERVED12;\n __IO uint8_t HOST_TX_LEN;\n uint8_t RESERVED13;\n __IO uint8_t HOST_TX_CTRL;\n uint8_t RESERVED14;\n} USBFSH_TypeDef;\n\n/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */\ntypedef struct{\n __I uint32_t ISR[8];\n __I uint32_t IPR[8];\n __IO uint32_t ITHRESDR;\n __IO uint32_t RESERVED;\n __IO uint32_t CFGR;\n __I uint32_t GISR;\n __IO uint8_t VTFIDR[4];\n uint8_t RESERVED0[12];\n __IO uint32_t VTFADDR[4];\n uint8_t RESERVED1[0x90];\n __O uint32_t IENR[8];\n uint8_t RESERVED2[0x60];\n __O uint32_t IRER[8];\n uint8_t RESERVED3[0x60];\n __O uint32_t IPSR[8];\n uint8_t RESERVED4[0x60];\n __O uint32_t IPRR[8];\n uint8_t RESERVED5[0x60];\n __IO uint32_t IACTR[8];\n uint8_t RESERVED6[0xE0];\n __IO uint8_t IPRIOR[256];\n uint8_t RESERVED7[0x810];\n __IO uint32_t SCTLR;\n} PFIC_Type;\n\n/* memory mapped structure for SysTick */\ntypedef struct\n{\n __IO uint32_t CTLR;\n __IO uint32_t SR;\n union {\n __IO uint64_t CNT;\n struct {\n __IO uint32_t CNTL;\n __IO uint32_t CNTH;\n };\n };\n union {\n __IO uint64_t CMP;\n struct {\n __IO uint32_t CMPL;\n __IO uint32_t CMPH;\n };\n };\n} SysTick_Type;\n\n/* PIOC Registers */\ntypedef struct\n{\n uint32_t RESERVED00;\n union {\n __IO uint32_t PIOC_SFR;\n struct {\n __IO uint8_t INDIR_ADDR;\n __IO uint8_t TMR0_COUNT;\n __IO uint8_t TMR0_CTRL;\n __IO uint8_t TMR0_INIT;\n };\n };\n union {\n __IO uint32_t PORT_CFG;\n struct {\n __IO uint8_t BIT_CYCLE;\n __IO uint8_t INDIR_ADDR2;\n __IO uint8_t PORT_DIR;\n __IO uint8_t PORT_IO;\n };\n };\n uint32_t RESERVED0C;\n uint32_t RESERVED10;\n uint32_t RESERVED14;\n uint32_t RESERVED18;\n union {\n __IO uint32_t DATA_CTRL;\n struct {\n __IO uint8_t SYS_CFG;\n __IO uint8_t CTRL_RD;\n __IO uint8_t CTRL_WR;\n __IO uint8_t DATA_EXCH;\n };\n };\n union {\n __IO uint32_t DATA_REG0_3;\n struct {\n __IO uint8_t DATA_REG0;\n __IO uint8_t DATA_REG1;\n __IO uint8_t DATA_REG2;\n __IO uint8_t DATA_REG3;\n };\n __IO uint16_t DATA_REG0_1;\n };\n union {\n __IO uint32_t DATA_REG4_7;\n struct {\n __IO uint8_t DATA_REG4;\n __IO uint8_t DATA_REG5;\n __IO uint8_t DATA_REG6;\n __IO uint8_t DATA_REG7;\n };\n };\n union {\n __IO uint32_t DATA_REG8_11;\n struct {\n __IO uint8_t DATA_REG8;\n __IO uint8_t DATA_REG9;\n __IO uint8_t DATA_REG10;\n __IO uint8_t DATA_REG11;\n };\n };\n union {\n __IO uint32_t DATA_REG12_15;\n struct {\n __IO uint8_t DATA_REG12;\n __IO uint8_t DATA_REG13;\n __IO uint8_t DATA_REG14;\n __IO uint8_t DATA_REG15;\n };\n };\n union {\n __IO uint32_t DATA_REG16_19;\n struct {\n __IO uint8_t DATA_REG16;\n __IO uint8_t DATA_REG17;\n __IO uint8_t DATA_REG18;\n __IO uint8_t DATA_REG19;\n };\n };\n union {\n __IO uint32_t DATA_REG20_23;\n struct {\n __IO uint8_t DATA_REG20;\n __IO uint8_t DATA_REG21;\n __IO uint8_t DATA_REG22;\n __IO uint8_t DATA_REG23;\n };\n };\n union {\n __IO uint32_t DATA_REG24_27;\n struct {\n __IO uint8_t DATA_REG24;\n __IO uint8_t DATA_REG25;\n __IO uint8_t DATA_REG26;\n __IO uint8_t DATA_REG27;\n };\n };\n union {\n __IO uint32_t DATA_REG28_31;\n struct {\n __IO uint8_t DATA_REG28;\n __IO uint8_t DATA_REG29;\n __IO uint8_t DATA_REG30;\n __IO uint8_t DATA_REG31;\n };\n };\n} PIOC_TypeDef;\n\n#endif\n\n#ifdef __ASSEMBLER__\n#define FLASH_BASE (0x08000000) /* FLASH base address in the alias region */\n#define SRAM_BASE (0x20000000) /* SRAM base address in the alias region */\n#define PERIPH_BASE (0x40000000) /* Peripheral base address in the alias region */\n#define OB_BASE (0x1FFFF800)\n#define PFIC_BASE (0xE000E000)\n#define STK_BASE (0xE000F000)\n#else\n#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */\n#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */\n#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */\n#define OB_BASE ((uint32_t)0x1FFFF800)\n#define PFIC_BASE ((uint32_t)0xE000E000)\n#define STK_BASE ((uint32_t)0xE000F000)\n#endif\n\n#define APB1PERIPH_BASE (PERIPH_BASE)\n#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)\n#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)\n\n#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)\n#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)\n#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)\n#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)\n#define USART2_BASE (APB1PERIPH_BASE + 0x4400)\n#define USART3_BASE (APB1PERIPH_BASE + 0x4800)\n#define USART4_BASE (APB1PERIPH_BASE + 0x4C00)\n#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)\n#define PWR_BASE (APB1PERIPH_BASE + 0x7000)\n\n#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)\n#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)\n#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)\n#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)\n#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)\n#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)\n#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)\n#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)\n#define USART1_BASE (APB2PERIPH_BASE + 0x3800)\n\n#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)\n#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)\n#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)\n#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)\n#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)\n#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)\n#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)\n#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)\n#define DMA1_Channel8_BASE (AHBPERIPH_BASE + 0x0094)\n#define RCC_BASE (AHBPERIPH_BASE + 0x1000)\n#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)\n#define USBFS_BASE (AHBPERIPH_BASE + 0x3400)\n#define OPA_BASE (AHBPERIPH_BASE + 0x6000)\n#define AWU_BASE (AHBPERIPH_BASE + 0x6400)\n#define PIOC_BASE (AHBPERIPH_BASE + 0x6C00)\n#define USBPD_BASE (AHBPERIPH_BASE + 0x7000)\n\n#define PIOC_SRAM_BASE (SRAM_BASE+0x4000)\n#define PIOC_SFR_BASE PIOC_BASE\n\n/* Peripheral declaration */\n#define TIM2 ((TIM_TypeDef *)TIM2_BASE)\n#define TIM3 ((TIM_TypeDef *)TIM3_BASE)\n#define WWDG ((WWDG_TypeDef *)WWDG_BASE)\n#define IWDG ((IWDG_TypeDef *)IWDG_BASE)\n#define USART2 ((USART_TypeDef *)USART2_BASE)\n#define USART3 ((USART_TypeDef *)USART3_BASE)\n#define USART4 ((USART_TypeDef *)USART4_BASE)\n#define I2C1 ((I2C_TypeDef *)I2C1_BASE)\n#define PWR ((PWR_TypeDef *)PWR_BASE)\n\n#define AFIO ((AFIO_TypeDef *)AFIO_BASE)\n#define EXTI ((EXTI_TypeDef *)EXTI_BASE)\n#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)\n#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)\n#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)\n#define ADC1 ((ADC_TypeDef *)ADC1_BASE)\n#define TKey1 ((ADC_TypeDef *)ADC1_BASE)\n#define TIM1 ((TIM_TypeDef *)TIM1_BASE)\n#define SPI1 ((SPI_TypeDef *)SPI1_BASE)\n#define USART1 ((USART_TypeDef *)USART1_BASE)\n\n#define DMA1 ((DMA_TypeDef *)DMA1_BASE)\n#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)\n#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)\n#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)\n#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)\n#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)\n#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)\n#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)\n#define DMA1_Channel8 ((DMA_Channel_TypeDef *)DMA1_Channel8_BASE)\n#define RCC ((RCC_TypeDef *)RCC_BASE)\n#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)\n#define USBFSD ((USBFSD_TypeDef *)USBFS_BASE)\n#define USBFSH ((USBFSH_TypeDef *)USBFS_BASE)\n#define OPA ((OPA_TypeDef *)OPA_BASE)\n#define AWU ((AWU_TypeDef *)AWU_BASE)\n#define PIOC ((PIOC_TypeDef *)PIOC_BASE)\n#define USBPD ((USBPD_TypeDef *)USBPD_BASE)\n\n#define OB ((OB_TypeDef *)OB_BASE)\n\n/* Core declaration */\n#define PFIC ((PFIC_Type *)PFIC_BASE)\n#define NVIC PFIC\n#define SysTick ((SysTick_Type *)STK_BASE)\n#define STK SysTick\n\n/* PIOC declaration */\n#define PIOC ((PIOC_TypeDef *)PIOC_BASE)\n\n\n/******************************************************************************/\n/* Peripheral Registers Bits Definition */\n/******************************************************************************/\n\n/******************************************************************************/\n/* Analog to Digital Converter */\n/******************************************************************************/\n\n/******************** Bit definition for ADC_STATR register ********************/\n#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */\n#define ADC_EOC ((uint8_t)0x02) /* End of conversion */\n#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */\n#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */\n#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */\n\n/******************* Bit definition for ADC_CTLR1 register ********************/\n#define ADC_AWDCH ((uint32_t)0x0000000F) /* AWDCH[3:0] bits (Analog watchdog channel select bits) */\n#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */\n#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */\n#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */\n#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */\n\n#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */\n#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */\n#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */\n#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */\n#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */\n#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */\n#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */\n#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */\n\n#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */\n#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */\n#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */\n#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */\n\n#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */\n#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */\n#define ADC_TKENABLE ((uint32_t)0x01000000) /* TKEN mode enable */\n\n/******************* Bit definition for ADC_CTLR2 register ********************/\n#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */\n#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */\n#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */\n#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */\n\n#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */\n#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */\n#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */\n#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */\n\n#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */\n\n#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */\n#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */\n#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */\n#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */\n\n#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */\n#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */\n#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */\n\n/****************** Bit definition for ADC_SAMPTR1 register *******************/\n#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */\n#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */\n#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */\n#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */\n\n#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */\n#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */\n#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */\n#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */\n\n#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */\n#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */\n#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */\n#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */\n\n#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */\n#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */\n#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */\n#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */\n\n#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */\n#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */\n#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */\n#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */\n\n#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */\n#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */\n#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */\n#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */\n\n#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */\n#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */\n#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */\n#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */\n\n#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */\n#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */\n#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */\n#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */\n\n/****************** Bit definition for ADC_SAMPTR2 register *******************/\n#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */\n#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */\n#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */\n#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */\n\n#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */\n#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */\n#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */\n#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */\n\n#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */\n#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */\n#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */\n#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */\n\n#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */\n#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */\n#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */\n#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */\n\n#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */\n#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */\n#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */\n#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */\n\n#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */\n#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */\n#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */\n#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */\n\n#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */\n#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */\n#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */\n#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */\n\n#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */\n#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */\n#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */\n#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */\n\n#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */\n#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */\n#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */\n#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */\n\n#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */\n#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */\n#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */\n#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */\n\n/****************** Bit definition for ADC_IOFR1 register *******************/\n#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */\n\n/****************** Bit definition for ADC_IOFR2 register *******************/\n#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */\n\n/****************** Bit definition for ADC_IOFR3 register *******************/\n#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */\n\n/****************** Bit definition for ADC_IOFR4 register *******************/\n#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */\n\n/******************* Bit definition for ADC_WDHTR register ********************/\n#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */\n\n/******************* Bit definition for ADC_WDLTR register ********************/\n#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */\n\n/******************* Bit definition for ADC_RSQR1 register *******************/\n#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */\n#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */\n#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */\n#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */\n#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */\n#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */\n\n#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */\n#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */\n#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */\n#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */\n#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */\n#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */\n\n#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */\n#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */\n#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */\n#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */\n#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */\n#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */\n\n#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */\n#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */\n#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */\n#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */\n#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */\n#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */\n\n#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */\n#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */\n#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */\n#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */\n#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */\n\n/******************* Bit definition for ADC_RSQR2 register *******************/\n#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */\n#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */\n#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */\n#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */\n#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */\n#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */\n\n#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */\n#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */\n#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */\n#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */\n#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */\n#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */\n\n#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */\n#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */\n#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */\n#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */\n#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */\n#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */\n\n#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */\n#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */\n#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */\n#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */\n#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */\n#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */\n\n#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */\n#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */\n#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */\n#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */\n#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */\n#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */\n\n#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */\n#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */\n#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */\n#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */\n#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */\n#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */\n\n/******************* Bit definition for ADC_RSQR3 register *******************/\n#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */\n#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */\n#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */\n#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */\n#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */\n#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */\n\n#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */\n#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */\n#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */\n#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */\n#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */\n#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */\n\n#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */\n#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */\n#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */\n#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */\n#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */\n#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */\n\n#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */\n#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */\n#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */\n#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */\n#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */\n#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */\n\n#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */\n#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */\n#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */\n#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */\n#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */\n#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */\n\n#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */\n#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */\n#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */\n#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */\n#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */\n#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */\n\n/******************* Bit definition for ADC_ISQR register *******************/\n#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */\n#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */\n#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */\n#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */\n#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */\n#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */\n\n#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */\n#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */\n#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */\n#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */\n#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */\n#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */\n\n#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */\n#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */\n#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */\n#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */\n#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */\n#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */\n\n#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */\n#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */\n#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */\n#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */\n#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */\n#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */\n\n#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */\n#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */\n#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */\n\n/******************* Bit definition for ADC_IDATAR1 register *******************/\n#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */\n\n/******************* Bit definition for ADC_IDATAR2 register *******************/\n#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */\n\n/******************* Bit definition for ADC_IDATAR3 register *******************/\n#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */\n\n/******************* Bit definition for ADC_IDATAR4 register *******************/\n#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */\n\n/******************** Bit definition for ADC_RDATAR register ********************/\n#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */\n\n/******************** Bit definition for ADC_CTLR3 register ********************/\n#define ADC_CTLR3_CLK_DIV ((uint32_t)0x0000000F) /* CLK_DIVL[3:0] bits */\n#define ADC_CTLR3_CLK_DIV_0 ((uint32_t)0x00000001) /* Bit 0 */\n#define ADC_CTLR3_CLK_DIV_1 ((uint32_t)0x00000002) /* Bit 1 */\n#define ADC_CTLR3_CLK_DIV_2 ((uint32_t)0x00000004) /* Bit 2 */\n#define ADC_CTLR3_CLK_DIV_3 ((uint32_t)0x00000008) /* Bit 3 */\n\n#define ADC_CTLR3_AWD_SCAN ((uint32_t)0x00000200) /* Analog watchdog Scan enable */\n#define ADC_CTLR3_AWD0_RST_EN ((uint32_t)0x00001000) /* Watchdog0 Reset Enable */\n#define ADC_CTLR3_AWD1_RST_EN ((uint32_t)0x00002000) /* Watchdog1 Reset Enable */\n#define ADC_CTLR3_AWD2_RST_EN ((uint32_t)0x00004000) /* Watchdog2 Reset Enable */\n#define ADC_CTLR3_AWD3_RST_EN ((uint32_t)0x00008000) /* Watchdog3 Reset Enable */\n\n/******************** Bit definition for ADC_WDTR1 register ********************/\n#define ADC_WDTR1_LTR1 ((uint32_t)0x00000FFF) /* Analog watchdog1 low threshold */\n#define ADC_WDTR1_HTR1 ((uint32_t)0x00FFF000) /* Analog watchdog1 high threshold */\n\n/******************** Bit definition for ADC_WDTR2 register ********************/\n#define ADC_WDTR2_LTR2 ((uint32_t)0x00000FFF) /* Analog watchdog2 low threshold */\n#define ADC_WDTR2_HTR2 ((uint32_t)0x00FFF000) /* Analog watchdog2 high threshold */\n\n/******************** Bit definition for ADC_WDTR3 register ********************/\n#define ADC_WDTR3_LTR3 ((uint32_t)0x00000FFF) /* Analog watchdog3 low threshold */\n#define ADC_WDTR3_HTR3 ((uint32_t)0x00FFF000) /* Analog watchdog3 high threshold */\n\n/******************************************************************************/\n/* DMA Controller */\n/******************************************************************************/\n\n/******************* Bit definition for DMA_INTFR register ********************/\n#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */\n#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */\n#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */\n#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */\n#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */\n#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */\n#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */\n#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */\n#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */\n#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */\n#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */\n#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */\n#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */\n#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */\n#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */\n#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */\n#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */\n#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */\n#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */\n#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */\n#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */\n#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */\n#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */\n#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */\n#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */\n#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */\n#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */\n#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */\n#define DMA_GIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt flag */\n#define DMA_TCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete flag */\n#define DMA_HTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer flag */\n#define DMA_TEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error flag */\n\n/******************* Bit definition for DMA_INTFCR register *******************/\n#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */\n#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */\n#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */\n#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */\n#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */\n#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */\n#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */\n#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */\n#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */\n#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */\n#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */\n#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */\n#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */\n#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */\n#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */\n#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */\n#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */\n#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */\n#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */\n#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */\n#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */\n#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */\n#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */\n#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */\n#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */\n#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */\n#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */\n#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */\n#define DMA_CGIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt clear */\n#define DMA_CTCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete clear */\n#define DMA_CHTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer clear */\n#define DMA_CTEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error clear */\n\n/******************* Bit definition for DMA_CFGR1 register *******************/\n#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/\n#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */\n#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */\n#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */\n#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */\n#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */\n#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */\n#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */\n\n#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */\n#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */\n#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */\n\n#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */\n#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */\n#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */\n\n#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */\n#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */\n#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */\n\n#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */\n\n/******************* Bit definition for DMA_CFGR2 register *******************/\n#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */\n#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */\n#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */\n#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */\n#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */\n#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */\n#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */\n#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */\n\n#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */\n#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */\n#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */\n\n#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */\n#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */\n#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */\n\n#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */\n#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */\n#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */\n\n#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */\n\n/******************* Bit definition for DMA_CFGR3 register *******************/\n#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */\n#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */\n#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */\n#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */\n#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */\n#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */\n#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */\n#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */\n\n#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */\n#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */\n#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */\n\n#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */\n#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */\n#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */\n\n#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */\n#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */\n#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */\n\n#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */\n\n/******************* Bit definition for DMA_CFG4 register *******************/\n#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */\n#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */\n#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */\n#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */\n#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */\n#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */\n#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */\n#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */\n\n#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */\n#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */\n#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */\n\n#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */\n#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */\n#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */\n\n#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */\n#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */\n#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */\n\n#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */\n\n/****************** Bit definition for DMA_CFG5 register *******************/\n#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */\n#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */\n#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */\n#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */\n#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */\n#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */\n#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */\n#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */\n\n#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */\n#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */\n#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */\n\n#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */\n#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */\n#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */\n\n#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */\n#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */\n#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */\n\n#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */\n\n/******************* Bit definition for DMA_CFG6 register *******************/\n#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */\n#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */\n#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */\n#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */\n#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */\n#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */\n#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */\n#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */\n\n#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */\n#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */\n#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */\n\n#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */\n#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */\n#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */\n\n#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */\n#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */\n#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */\n\n#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */\n\n/******************* Bit definition for DMA_CFG7 register *******************/\n#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */\n#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */\n#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */\n#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */\n#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */\n#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */\n#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */\n#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */\n\n#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */\n#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */\n#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */\n\n#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */\n#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */\n#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */\n\n#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */\n#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */\n#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */\n\n#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */\n\n/******************* Bit definition for DMA_CFG8 register *******************/\n#define DMA_CFG8_EN ((uint16_t)0x0001) /* Channel enable */\n#define DMA_CFG8_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */\n#define DMA_CFG8_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */\n#define DMA_CFG8_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */\n#define DMA_CFG8_DIR ((uint16_t)0x0010) /* Data transfer direction */\n#define DMA_CFG8_CIRC ((uint16_t)0x0020) /* Circular mode */\n#define DMA_CFG8_PINC ((uint16_t)0x0040) /* Peripheral increment mode */\n#define DMA_CFG8_MINC ((uint16_t)0x0080) /* Memory increment mode */\n\n#define DMA_CFG8_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */\n#define DMA_CFG8_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */\n#define DMA_CFG8_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */\n\n#define DMA_CFG8_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */\n#define DMA_CFG8_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */\n#define DMA_CFG8_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */\n\n#define DMA_CFG8_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */\n#define DMA_CFG8_PL_0 ((uint16_t)0x1000) /* Bit 0 */\n#define DMA_CFG8_PL_1 ((uint16_t)0x2000) /* Bit 1 */\n\n#define DMA_CFG8_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */\n\n/****************** Bit definition for DMA_CNTR1 register ******************/\n#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */\n\n/****************** Bit definition for DMA_CNTR2 register ******************/\n#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */\n\n/****************** Bit definition for DMA_CNTR3 register ******************/\n#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */\n\n/****************** Bit definition for DMA_CNTR4 register ******************/\n#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */\n\n/****************** Bit definition for DMA_CNTR5 register ******************/\n#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */\n\n/****************** Bit definition for DMA_CNTR6 register ******************/\n#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */\n\n/****************** Bit definition for DMA_CNTR7 register ******************/\n#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */\n\n/****************** Bit definition for DMA_CNTR8 register ******************/\n#define DMA_CNTR8_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */\n\n/****************** Bit definition for DMA_PADDR1 register *******************/\n#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */\n\n/****************** Bit definition for DMA_PADDR2 register *******************/\n#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */\n\n/****************** Bit definition for DMA_PADDR3 register *******************/\n#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */\n\n/****************** Bit definition for DMA_PADDR4 register *******************/\n#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */\n\n/****************** Bit definition for DMA_PADDR5 register *******************/\n#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */\n\n/****************** Bit definition for DMA_PADDR6 register *******************/\n#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */\n\n/****************** Bit definition for DMA_PADDR7 register *******************/\n#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */\n\n/****************** Bit definition for DMA_PADDR8 register *******************/\n#define DMA_PADDR8_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */\n\n/****************** Bit definition for DMA_MADDR1 register *******************/\n#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */\n\n/****************** Bit definition for DMA_MADDR2 register *******************/\n#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */\n\n/****************** Bit definition for DMA_MADDR3 register *******************/\n#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */\n\n/****************** Bit definition for DMA_MADDR4 register *******************/\n#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */\n\n/****************** Bit definition for DMA_MADDR5 register *******************/\n#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */\n\n/****************** Bit definition for DMA_MADDR6 register *******************/\n#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */\n\n/****************** Bit definition for DMA_MADDR7 register *******************/\n#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */\n\n/****************** Bit definition for DMA_MADDR8 register *******************/\n#define DMA_MADDR8_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */\n\n/******************************************************************************/\n/* External Interrupt/Event Controller */\n/******************************************************************************/\n\n/******************* Bit definition for EXTI_INTENR register *******************/\n#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */\n#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */\n#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */\n#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */\n#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */\n#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */\n#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */\n#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */\n#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */\n#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */\n#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */\n#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */\n#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */\n#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */\n#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */\n#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */\n#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */\n#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */\n#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */\n#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */\n#define EXTI_INTENR_MR20 ((uint32_t)0x00100000) /* Interrupt Mask on line 20 */\n#define EXTI_INTENR_MR21 ((uint32_t)0x00200000) /* Interrupt Mask on line 21 */\n#define EXTI_INTENR_MR22 ((uint32_t)0x00400000) /* Interrupt Mask on line 22 */\n#define EXTI_INTENR_MR23 ((uint32_t)0x00800000) /* Interrupt Mask on line 23 */\n#define EXTI_INTENR_MR24 ((uint32_t)0x01000000) /* Interrupt Mask on line 24 */\n#define EXTI_INTENR_MR25 ((uint32_t)0x02000000) /* Interrupt Mask on line 25 */\n#define EXTI_INTENR_MR26 ((uint32_t)0x04000000) /* Interrupt Mask on line 26 */\n#define EXTI_INTENR_MR27 ((uint32_t)0x08000000) /* Interrupt Mask on line 27 */\n#define EXTI_INTENR_MR28 ((uint32_t)0x10000000) /* Interrupt Mask on line 28 */\n#define EXTI_INTENR_MR29 ((uint32_t)0x20000000) /* Interrupt Mask on line 29 */\n\n/******************* Bit definition for EXTI_EVENR register *******************/\n#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */\n#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */\n#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */\n#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */\n#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */\n#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */\n#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */\n#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */\n#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */\n#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */\n#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */\n#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */\n#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */\n#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */\n#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */\n#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */\n#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */\n#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */\n#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */\n#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */\n#define EXTI_EVENR_MR20 ((uint32_t)0x00100000) /* Event Mask on line 20 */\n#define EXTI_EVENR_MR21 ((uint32_t)0x00200000) /* Event Mask on line 21 */\n#define EXTI_EVENR_MR22 ((uint32_t)0x00400000) /* Event Mask on line 22 */\n#define EXTI_EVENR_MR23 ((uint32_t)0x00800000) /* Event Mask on line 23 */\n#define EXTI_EVENR_MR24 ((uint32_t)0x01000000) /* Event Mask on line 24 */\n#define EXTI_EVENR_MR25 ((uint32_t)0x02000000) /* Event Mask on line 25 */\n#define EXTI_EVENR_MR26 ((uint32_t)0x04000000) /* Event Mask on line 26 */\n#define EXTI_EVENR_MR27 ((uint32_t)0x08000000) /* Event Mask on line 27 */\n#define EXTI_EVENR_MR28 ((uint32_t)0x10000000) /* Event Mask on line 28 */\n#define EXTI_EVENR_MR29 ((uint32_t)0x20000000) /* Event Mask on line 29 */\n\n/****************** Bit definition for EXTI_RTENR register *******************/\n#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */\n#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */\n#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */\n#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */\n#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */\n#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */\n#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */\n#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */\n#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */\n#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */\n#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */\n#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */\n#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */\n#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */\n#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */\n#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */\n#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */\n#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */\n#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */\n#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */\n#define EXTI_RTENR_TR20 ((uint32_t)0x00100000) /* Rising trigger event configuration bit of line 20 */\n#define EXTI_RTENR_TR21 ((uint32_t)0x00200000) /* Rising trigger event configuration bit of line 21 */\n#define EXTI_RTENR_TR22 ((uint32_t)0x00400000) /* Rising trigger event configuration bit of line 22 */\n#define EXTI_RTENR_TR23 ((uint32_t)0x00800000) /* Rising trigger event configuration bit of line 23 */\n#define EXTI_RTENR_TR24 ((uint32_t)0x01000000) /* Rising trigger event configuration bit of line 24 */\n#define EXTI_RTENR_TR25 ((uint32_t)0x02000000) /* Rising trigger event configuration bit of line 25 */\n#define EXTI_RTENR_TR26 ((uint32_t)0x04000000) /* Rising trigger event configuration bit of line 26 */\n#define EXTI_RTENR_TR27 ((uint32_t)0x08000000) /* Rising trigger event configuration bit of line 27 */\n#define EXTI_RTENR_TR28 ((uint32_t)0x10000000) /* Rising trigger event configuration bit of line 28 */\n#define EXTI_RTENR_TR29 ((uint32_t)0x20000000) /* Rising trigger event configuration bit of line 29 */\n\n/****************** Bit definition for EXTI_FTENR register *******************/\n#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */\n#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */\n#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */\n#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */\n#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */\n#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */\n#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */\n#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */\n#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */\n#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */\n#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */\n#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */\n#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */\n#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */\n#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */\n#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */\n#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */\n#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */\n#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */\n#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */\n#define EXTI_FTENR_TR20 ((uint32_t)0x00100000) /* Falling trigger event configuration bit of line 20 */\n#define EXTI_FTENR_TR21 ((uint32_t)0x00200000) /* Falling trigger event configuration bit of line 21 */\n#define EXTI_FTENR_TR22 ((uint32_t)0x00400000) /* Falling trigger event configuration bit of line 22 */\n#define EXTI_FTENR_TR23 ((uint32_t)0x00800000) /* Falling trigger event configuration bit of line 23 */\n#define EXTI_FTENR_TR24 ((uint32_t)0x01000000) /* Falling trigger event configuration bit of line 24 */\n#define EXTI_FTENR_TR25 ((uint32_t)0x02000000) /* Falling trigger event configuration bit of line 25 */\n#define EXTI_FTENR_TR26 ((uint32_t)0x04000000) /* Falling trigger event configuration bit of line 26 */\n#define EXTI_FTENR_TR27 ((uint32_t)0x08000000) /* Falling trigger event configuration bit of line 27 */\n#define EXTI_FTENR_TR28 ((uint32_t)0x10000000) /* Falling trigger event configuration bit of line 28 */\n#define EXTI_FTENR_TR29 ((uint32_t)0x20000000) /* Falling trigger event configuration bit of line 29 */\n\n/****************** Bit definition for EXTI_SWIEVR register ******************/\n#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */\n#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */\n#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */\n#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */\n#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */\n#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */\n#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */\n#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */\n#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */\n#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */\n#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */\n#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */\n#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */\n#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */\n#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */\n#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */\n#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */\n#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */\n#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */\n#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */\n#define EXTI_SWIEVR_SWIEVR20 ((uint32_t)0x00100000) /* Software Interrupt on line 20 */\n#define EXTI_SWIEVR_SWIEVR21 ((uint32_t)0x00200000) /* Software Interrupt on line 21 */\n#define EXTI_SWIEVR_SWIEVR22 ((uint32_t)0x00400000) /* Software Interrupt on line 22 */\n#define EXTI_SWIEVR_SWIEVR23 ((uint32_t)0x00800000) /* Software Interrupt on line 23 */\n#define EXTI_SWIEVR_SWIEVR24 ((uint32_t)0x01000000) /* Software Interrupt on line 24 */\n#define EXTI_SWIEVR_SWIEVR25 ((uint32_t)0x02000000) /* Software Interrupt on line 25 */\n#define EXTI_SWIEVR_SWIEVR26 ((uint32_t)0x04000000) /* Software Interrupt on line 26 */\n#define EXTI_SWIEVR_SWIEVR27 ((uint32_t)0x08000000) /* Software Interrupt on line 27 */\n#define EXTI_SWIEVR_SWIEVR28 ((uint32_t)0x10000000) /* Software Interrupt on line 28 */\n#define EXTI_SWIEVR_SWIEVR29 ((uint32_t)0x20000000) /* Software Interrupt on line 29 */\n\n/******************* Bit definition for EXTI_INTFR register ********************/\n#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */\n#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */\n#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */\n#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */\n#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */\n#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */\n#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */\n#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */\n#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */\n#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */\n#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */\n#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */\n#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */\n#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */\n#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */\n#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */\n#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */\n#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */\n#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */\n#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */\n#define EXTI_INTF_INTF20 ((uint32_t)0x00100000) /* Pending bit for line 20 */\n#define EXTI_INTF_INTF21 ((uint32_t)0x00200000) /* Pending bit for line 21 */\n#define EXTI_INTF_INTF22 ((uint32_t)0x00400000) /* Pending bit for line 22 */\n#define EXTI_INTF_INTF23 ((uint32_t)0x00800000) /* Pending bit for line 23 */\n#define EXTI_INTF_INTF24 ((uint32_t)0x01000000) /* Pending bit for line 24 */\n#define EXTI_INTF_INTF25 ((uint32_t)0x02000000) /* Pending bit for line 25 */\n#define EXTI_INTF_INTF26 ((uint32_t)0x04000000) /* Pending bit for line 26 */\n#define EXTI_INTF_INTF27 ((uint32_t)0x08000000) /* Pending bit for line 27 */\n#define EXTI_INTF_INTF28 ((uint32_t)0x10000000) /* Pending bit for line 28 */\n#define EXTI_INTF_INTF29 ((uint32_t)0x20000000) /* Pending bit for line 29 */\n\n/******************************************************************************/\n/* FLASH and Option Bytes Registers */\n/******************************************************************************/\n\n/******************* Bit definition for FLASH_ACTLR register ******************/\n#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */\n#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */\n#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */\n#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */\n\n/****************** Bit definition for FLASH_KEYR register ******************/\n#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */\n\n/***************** Bit definition for FLASH_OBKEYR register ****************/\n#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */\n\n/****************** Bit definition for FLASH_STATR register *******************/\n#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */\n#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */\n#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */\n#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */\n#define FLASH_STATR_FWAKE_FLAG ((uint8_t)0x40) /* Flag of wake */\n#define FLASH_STATR_TURBO ((uint8_t)0x80) /* The state of TURBO Enable */\n#define FLASH_STATR_BOOT_AVA ((uint16_t)0x100) /* The state of Init Config */\n#define FLASH_STATR_BOOT_STATUS ((uint16_t)0x200) /* The source of Execute Program */\n#define FLASH_STATR_BOOT_MODE ((uint16_t)0x400) /* The switch of user section or boot section*/\n#define FLASH_STATR_BOOT_LOCK ((uint16_t)0x800) /* Lock boot area*/\n\n/******************* Bit definition for FLASH_CTLR register *******************/\n#define FLASH_CTLR_PG ((uint32_t)0x00000001) /* Programming */\n#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 4K */\n#define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */\n#define FLASH_CTLR_OPTPG ((uint32_t)0x00000010) /* Option Byte Programming */\n#define FLASH_CTLR_OPTER ((uint32_t)0x00000020) /* Option Byte Erase */\n#define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */\n#define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */\n#define FLASH_CTLR_OBWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */\n#define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */\n#define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */\n#define FLASH_CTLR_FWAKEIE ((uint32_t)0x00002000) /* Wake inter Enable */\n#define FLASH_CTLR_FLOCK ((uint32_t)0x00008000) /* Fast Lock */\n#define FLASH_CTLR_FTPG ((uint32_t)0x00010000) /* Fast Program */\n#define FLASH_CTLR_FTER ((uint32_t)0x00020000) /* Fast Erase */\n#define FLASH_CTLR_BUFLOAD ((uint32_t)0x00040000) /* BUF Load */\n#define FLASH_CTLR_BUFRST ((uint32_t)0x00080000) /* BUF Reset */\n#define FLASH_CTLR_BER32 ((uint32_t)0x00800000) /* Block Erase 32K */\n\n/******************* Bit definition for FLASH_ADDR register *******************/\n#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */\n\n/****************** Bit definition for FLASH_OBR register *******************/\n#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */\n#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */\n\n#define FLASH_OBR_USER ((uint16_t)0x007C) /* User Option Bytes */\n#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */\n#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */\n#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */\n#define FLASH_OBR_CFGRSTT ((uint16_t)0x0060) /* Config Reset delay time */\n\n#define FLASH_OBR_FIX_11 ((uint16_t)0x0300) /* fix 11 */\n#define FLASH_OBR_DATA0 ((uint32_t)0x3FC00) /* Data byte0 */\n#define FLASH_OBR_DATA1 ((uint32_t)0x3FC0000) /* Data byte1 */\n\n/****************** Bit definition for FLASH_WPR register ******************/\n#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */\n\n/****************** Bit definition for FLASH_MODEKEYR register ******************/\n#define FLASH_MODEKEYR_MODEKEYR ((uint32_t)0xFFFFFFFF) /* Open fast program /erase */\n#define FLASH_MODEKEYR_MODEKEYR1 ((uint32_t)0x45670123) \n#define FLASH_MODEKEYR_MODEKEYR2 ((uint32_t)0xCDEF89AB) \n\n/****************** Bit definition for BOOT_MODEKEYP register ******************/\n#define BOOT_MODEKEYP_MODEKEYR ((uint32_t)0xFFFFFFFF) /* Open Boot section */\n#define BOOT_MODEKEYP_MODEKEYR1 ((uint32_t)0x45670123)\n#define BOOT_MODEKEYP_MODEKEYR2 ((uint32_t)0xCDEF89AB)\n\n/****************** Bit definition for FLASH_RDPR register *******************/\n#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */\n#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */\n\n/****************** Bit definition for FLASH_USER register ******************/\n#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */\n#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */\n\n/****************** Bit definition for FLASH_Data0 register *****************/\n#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */\n#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */\n\n/****************** Bit definition for FLASH_Data1 register *****************/\n#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */\n#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */\n\n/****************** Bit definition for FLASH_WRPR0 register ******************/\n#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */\n#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */\n\n/****************** Bit definition for FLASH_WRPR1 register ******************/\n#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */\n#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */\n\n/****************** Bit definition for FLASH_WRPR2 register ******************/\n#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */\n#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */\n\n/****************** Bit definition for FLASH_WRPR3 register ******************/\n#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */\n#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */\n\n/******************************* FLASH keys *********************************/\n#define FLASH_KEY1 ((uint32_t)0x45670123)\n#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)\n\n/******************************************************************************/\n/* General Purpose and Alternate Function I/O */\n/******************************************************************************/\n\n/******************* Bit definition for GPIO_CFGLR register *******************/\n#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */\n\n#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */\n#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */\n#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */\n\n#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */\n#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */\n#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */\n\n#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */\n#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */\n#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */\n\n#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */\n#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */\n#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */\n\n#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */\n#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */\n#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */\n\n#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */\n#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */\n#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */\n\n#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */\n#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */\n#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */\n\n#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */\n#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */\n#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */\n\n#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */\n\n#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */\n#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */\n#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */\n\n#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */\n#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */\n#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */\n\n#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */\n#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */\n#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */\n\n#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */\n#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */\n#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */\n\n#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */\n#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */\n#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */\n\n#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */\n#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */\n#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */\n\n#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */\n#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */\n#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */\n\n#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */\n#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */\n#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */\n\n/******************* Bit definition for GPIO_CFGHR register *******************/\n#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */\n\n#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */\n#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */\n#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */\n\n#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */\n#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */\n#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */\n\n#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */\n#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */\n#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */\n\n#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */\n#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */\n#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */\n\n#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */\n#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */\n#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */\n\n#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */\n#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */\n#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */\n\n#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */\n#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */\n#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */\n\n#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */\n#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */\n#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */\n\n#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */\n\n#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */\n#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */\n#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */\n\n#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */\n#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */\n#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */\n\n#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */\n#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */\n#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */\n\n#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */\n#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */\n#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */\n\n#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */\n#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */\n#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */\n\n#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */\n#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */\n#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */\n\n#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */\n#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */\n#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */\n\n#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */\n#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */\n#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */\n\n/******************* Bit definition for GPIO_INDR register *******************/\n#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */\n#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */\n#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */\n#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */\n#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */\n#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */\n#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */\n#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */\n#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */\n#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */\n#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */\n#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */\n#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */\n#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */\n#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */\n#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */\n#define GPIO_INDR_IDR16 ((uint32_t)0x10000) /* Port input data, bit 16 */\n#define GPIO_INDR_IDR17 ((uint32_t)0x20000) /* Port input data, bit 17 */\n#define GPIO_INDR_IDR18 ((uint32_t)0x40000) /* Port input data, bit 18 */\n#define GPIO_INDR_IDR19 ((uint32_t)0x80000) /* Port input data, bit 19 */\n#define GPIO_INDR_IDR20 ((uint32_t)0x100000) /* Port input data, bit 20 */\n#define GPIO_INDR_IDR21 ((uint32_t)0x200000) /* Port input data, bit 21 */\n#define GPIO_INDR_IDR22 ((uint32_t)0x400000) /* Port input data, bit 22 */\n#define GPIO_INDR_IDR23 ((uint32_t)0x800000) /* Port input data, bit 23 */\n\n/******************* Bit definition for GPIO_OUTDR register *******************/\n#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */\n#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */\n#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */\n#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */\n#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */\n#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */\n#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */\n#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */\n#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */\n#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */\n#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */\n#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */\n#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */\n#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */\n#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */\n#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */\n#define GPIO_OUTDR_ODR16 ((uint32_t)0x10000) /* Port output data, bit 16 */\n#define GPIO_OUTDR_ODR17 ((uint32_t)0x20000) /* Port output data, bit 17 */\n#define GPIO_OUTDR_ODR18 ((uint32_t)0x40000) /* Port output data, bit 18 */\n#define GPIO_OUTDR_ODR19 ((uint32_t)0x80000) /* Port output data, bit 19 */\n#define GPIO_OUTDR_ODR20 ((uint32_t)0x100000) /* Port output data, bit 20 */\n#define GPIO_OUTDR_ODR21 ((uint32_t)0x200000) /* Port output data, bit 21 */\n#define GPIO_OUTDR_ODR22 ((uint32_t)0x400000) /* Port output data, bit 22 */\n#define GPIO_OUTDR_ODR23 ((uint32_t)0x800000) /* Port output data, bit 23 */\n\n/****************** Bit definition for GPIO_BSHR register *******************/\n#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */\n#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */\n#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */\n#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */\n#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */\n#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */\n#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */\n#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */\n#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */\n#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */\n#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */\n#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */\n#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */\n#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */\n#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */\n#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */\n\n#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */\n#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */\n#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */\n#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */\n#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */\n#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */\n#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */\n#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */\n#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */\n#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */\n#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */\n#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */\n#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */\n#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */\n#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */\n#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */\n\n/******************* Bit definition for GPIO_BCR register *******************/\n#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */\n#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */\n#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */\n#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */\n#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */\n#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */\n#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */\n#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */\n#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */\n#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */\n#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */\n#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */\n#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */\n#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */\n#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */\n#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */\n#define GPIO_BCR_BR16 ((uint32_t)0x10000) /* Port x Reset bit 16 */\n#define GPIO_BCR_BR17 ((uint32_t)0x20000) /* Port x Reset bit 17 */\n#define GPIO_BCR_BR18 ((uint32_t)0x40000) /* Port x Reset bit 18 */\n#define GPIO_BCR_BR19 ((uint32_t)0x80000) /* Port x Reset bit 19 */\n#define GPIO_BCR_BR20 ((uint32_t)0x100000) /* Port x Reset bit 20 */\n#define GPIO_BCR_BR21 ((uint32_t)0x200000) /* Port x Reset bit 21 */\n#define GPIO_BCR_BR22 ((uint32_t)0x400000) /* Port x Reset bit 22 */\n#define GPIO_BCR_BR23 ((uint32_t)0x800000) /* Port x Reset bit 23 */\n\n\n/****************** Bit definition for GPIO_LCKR register *******************/\n#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */\n#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */\n#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */\n#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */\n#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */\n#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */\n#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */\n#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */\n#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */\n#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */\n#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */\n#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */\n#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */\n#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */\n#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */\n#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */\n#define GPIO_LCK16 ((uint32_t)0x00010000) /* Port x Lock bit 16 */\n#define GPIO_LCK17 ((uint32_t)0x00020000) /* Port x Lock bit 17 */\n#define GPIO_LCK18 ((uint32_t)0x00040000) /* Port x Lock bit 18 */\n#define GPIO_LCK19 ((uint32_t)0x00080000) /* Port x Lock bit 19 */\n#define GPIO_LCK20 ((uint32_t)0x00100000) /* Port x Lock bit 20 */\n#define GPIO_LCK21 ((uint32_t)0x00200000) /* Port x Lock bit 21 */\n#define GPIO_LCK22 ((uint32_t)0x00400000) /* Port x Lock bit 22 */\n#define GPIO_LCK23 ((uint32_t)0x00800000) /* Port x Lock bit 23 */\n\n#define GPIO_LCKK ((uint32_t)0x01000000) /* Lock key */\n\n/******************* Bit definition for GPIO_CFGXR register *******************/\n#define GPIO_CFGXR_MODE ((uint32_t)0x33333333) /* Port x mode bits */\n\n#define GPIO_CFGXR_MODE16 ((uint32_t)0x00000003) /* MODE16[1:0] bits (Port x mode bits, pin 0) */\n#define GPIO_CFGXR_MODE16_0 ((uint32_t)0x00000001) /* Bit 0 */\n#define GPIO_CFGXR_MODE16_1 ((uint32_t)0x00000002) /* Bit 1 */\n\n#define GPIO_CFGXR_MODE17 ((uint32_t)0x00000030) /* MODE17[1:0] bits (Port x mode bits, pin 1) */\n#define GPIO_CFGXR_MODE17_0 ((uint32_t)0x00000010) /* Bit 0 */\n#define GPIO_CFGXR_MODE17_1 ((uint32_t)0x00000020) /* Bit 1 */\n\n#define GPIO_CFGXR_MODE18 ((uint32_t)0x00000300) /* MODE18[1:0] bits (Port x mode bits, pin 2) */\n#define GPIO_CFGXR_MODE18_0 ((uint32_t)0x00000100) /* Bit 0 */\n#define GPIO_CFGXR_MODE18_1 ((uint32_t)0x00000200) /* Bit 1 */\n\n#define GPIO_CFGXR_MODE19 ((uint32_t)0x00003000) /* MODE19[1:0] bits (Port x mode bits, pin 3) */\n#define GPIO_CFGXR_MODE19_0 ((uint32_t)0x00001000) /* Bit 0 */\n#define GPIO_CFGXR_MODE19_1 ((uint32_t)0x00002000) /* Bit 1 */\n\n#define GPIO_CFGXR_MODE20 ((uint32_t)0x00030000) /* MODE20[1:0] bits (Port x mode bits, pin 4) */\n#define GPIO_CFGXR_MODE20_0 ((uint32_t)0x00010000) /* Bit 0 */\n#define GPIO_CFGXR_MODE20_1 ((uint32_t)0x00020000) /* Bit 1 */\n\n#define GPIO_CFGXR_MODE21 ((uint32_t)0x00300000) /* MODE21[1:0] bits (Port x mode bits, pin 5) */\n#define GPIO_CFGXR_MODE21_0 ((uint32_t)0x00100000) /* Bit 0 */\n#define GPIO_CFGXR_MODE21_1 ((uint32_t)0x00200000) /* Bit 1 */\n\n#define GPIO_CFGXR_MODE22 ((uint32_t)0x03000000) /* MODE22[1:0] bits (Port x mode bits, pin 6) */\n#define GPIO_CFGXR_MODE22_0 ((uint32_t)0x01000000) /* Bit 0 */\n#define GPIO_CFGXR_MODE22_1 ((uint32_t)0x02000000) /* Bit 1 */\n\n#define GPIO_CFGXR_MODE23 ((uint32_t)0x30000000) /* MODE23[1:0] bits (Port x mode bits, pin 7) */\n#define GPIO_CFGXR_MODE23_0 ((uint32_t)0x10000000) /* Bit 0 */\n#define GPIO_CFGXR_MODE23_1 ((uint32_t)0x20000000) /* Bit 1 */\n\n#define GPIO_CFGXR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */\n\n#define GPIO_CFGXR_CNF16 ((uint32_t)0x0000000C) /* CNF16[1:0] bits (Port x configuration bits, pin 0) */\n#define GPIO_CFGXR_CNF16_0 ((uint32_t)0x00000004) /* Bit 0 */\n#define GPIO_CFGXR_CNF16_1 ((uint32_t)0x00000008) /* Bit 1 */\n\n#define GPIO_CFGXR_CNF17 ((uint32_t)0x000000C0) /* CNF17[1:0] bits (Port x configuration bits, pin 1) */\n#define GPIO_CFGXR_CNF17_0 ((uint32_t)0x00000040) /* Bit 0 */\n#define GPIO_CFGXR_CNF17_1 ((uint32_t)0x00000080) /* Bit 1 */\n\n#define GPIO_CFGXR_CNF18 ((uint32_t)0x00000C00) /* CNF18[1:0] bits (Port x configuration bits, pin 2) */\n#define GPIO_CFGXR_CNF18_0 ((uint32_t)0x00000400) /* Bit 0 */\n#define GPIO_CFGXR_CNF18_1 ((uint32_t)0x00000800) /* Bit 1 */\n\n#define GPIO_CFGXR_CNF19 ((uint32_t)0x0000C000) /* CNF19[1:0] bits (Port x configuration bits, pin 3) */\n#define GPIO_CFGXR_CNF19_0 ((uint32_t)0x00004000) /* Bit 0 */\n#define GPIO_CFGXR_CNF19_1 ((uint32_t)0x00008000) /* Bit 1 */\n\n#define GPIO_CFGXR_CNF20 ((uint32_t)0x000C0000) /* CNF20[1:0] bits (Port x configuration bits, pin 4) */\n#define GPIO_CFGXR_CNF20_0 ((uint32_t)0x00040000) /* Bit 0 */\n#define GPIO_CFGXR_CNF20_1 ((uint32_t)0x00080000) /* Bit 1 */\n\n#define GPIO_CFGXR_CNF21 ((uint32_t)0x00C00000) /* CNF21[1:0] bits (Port x configuration bits, pin 5) */\n#define GPIO_CFGXR_CNF21_0 ((uint32_t)0x00400000) /* Bit 0 */\n#define GPIO_CFGXR_CNF21_1 ((uint32_t)0x00800000) /* Bit 1 */\n\n#define GPIO_CFGXR_CNF22 ((uint32_t)0x0C000000) /* CNF22[1:0] bits (Port x configuration bits, pin 6) */\n#define GPIO_CFGXR_CNF22_0 ((uint32_t)0x04000000) /* Bit 0 */\n#define GPIO_CFGXR_CNF22_1 ((uint32_t)0x08000000) /* Bit 1 */\n\n#define GPIO_CFGXR_CNF23 ((uint32_t)0xC0000000) /* CNF23[1:0] bits (Port x configuration bits, pin 7) */\n#define GPIO_CFGXR_CNF23_0 ((uint32_t)0x40000000) /* Bit 0 */\n#define GPIO_CFGXR_CNF23_1 ((uint32_t)0x80000000) /* Bit 1 */\n\n/****************** Bit definition for GPIO_BSXR register *******************/\n#define GPIO_BSXR_BS16 ((uint32_t)0x00000001) /* Port x Set bit 0 */\n#define GPIO_BSXR_BS17 ((uint32_t)0x00000002) /* Port x Set bit 1 */\n#define GPIO_BSXR_BS18 ((uint32_t)0x00000004) /* Port x Set bit 2 */\n#define GPIO_BSXR_BS19 ((uint32_t)0x00000008) /* Port x Set bit 3 */\n#define GPIO_BSXR_BS20 ((uint32_t)0x00000010) /* Port x Set bit 4 */\n#define GPIO_BSXR_BS21 ((uint32_t)0x00000020) /* Port x Set bit 5 */\n#define GPIO_BSXR_BS22 ((uint32_t)0x00000040) /* Port x Set bit 6 */\n#define GPIO_BSXR_BS23 ((uint32_t)0x00000080) /* Port x Set bit 7 */\n\n#define GPIO_BSXR_BR16 ((uint32_t)0x00010000) /* Port x Reset bit 0 */\n#define GPIO_BSXR_BR17 ((uint32_t)0x00020000) /* Port x Reset bit 1 */\n#define GPIO_BSXR_BR18 ((uint32_t)0x00040000) /* Port x Reset bit 2 */\n#define GPIO_BSXR_BR19 ((uint32_t)0x00080000) /* Port x Reset bit 3 */\n#define GPIO_BSXR_BR20 ((uint32_t)0x00100000) /* Port x Reset bit 4 */\n#define GPIO_BSXR_BR21 ((uint32_t)0x00200000) /* Port x Reset bit 5 */\n#define GPIO_BSXR_BR22 ((uint32_t)0x00400000) /* Port x Reset bit 6 */\n#define GPIO_BSXR_BR23 ((uint32_t)0x00800000) /* Port x Reset bit 7 */\n\n/****************** Bit definition for AFIO_PCFR1register *******************/\n#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000003) /* SPI1_REMAP[1:0] bits (SPI1 remapping) */\n#define AFIO_PCFR1_SPI1_REMAP_0 ((uint32_t)0x00000001) /* Bit 0 */\n#define AFIO_PCFR1_SPI1_REMAP_1 ((uint32_t)0x00000002) /* Bit 1 */\n\n#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x0000001C) /* I2C1_REMAP[4:2] bits (I2C1 remapping) */\n#define AFIO_PCFR1_I2C1_REMAP_0 ((uint32_t)0x00000004) /* Bit 0 */\n#define AFIO_PCFR1_I2C1_REMAP_1 ((uint32_t)0x00000008) /* Bit 1 */\n#define AFIO_PCFR1_I2C1_REMAP_2 ((uint32_t)0x00000010) /* Bit 2 */\n\n#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000060) /* USART1_REMAP[6:5] bits (USART1 remapping) */\n#define AFIO_PCFR1_USART1_REMAP_0 ((uint32_t)0x00000020) /* Bit 0 */\n#define AFIO_PCFR1_USART1_REMAP_1 ((uint32_t)0x00000040) /* Bit 1 */\n\n#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000380) /* USART2_REMAP[9:7] bits (USART2 remapping) */\n#define AFIO_PCFR1_USART2_REMAP_0 ((uint32_t)0x00000080) /* Bit 0 */\n#define AFIO_PCFR1_USART2_REMAP_1 ((uint32_t)0x00000100) /* Bit 1 */\n#define AFIO_PCFR1_USART2_REMAP_2 ((uint32_t)0x00000200) /* Bit 2 */\n\n#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000C00) /* USART3_REMAP[11:10] bits (USART3 remapping) */\n#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */\n#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */\n\n#define AFIO_PCFR1_USART4_REMAP ((uint32_t)0x00000700) /* USART4_REMAP[14:12] bits (USART4 remapping) */\n#define AFIO_PCFR1_USART4_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */\n#define AFIO_PCFR1_USART4_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */\n#define AFIO_PCFR1_USART4_REMAP_2 ((uint32_t)0x00000400) /* Bit 2 */\n\n#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x00003800) /* TIM1_REMAP[17:15] bits (TIM1 remapping) */\n#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000800) /* Bit 0 */\n#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00001000) /* Bit 1 */\n#define AFIO_PCFR1_TIM1_REMAP_2 ((uint32_t)0x00002000) /* Bit 2 */\n\n#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x0001C000) /* TIM2_REMAP[20:18] bits (TIM2 remapping) */\n#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00004000) /* Bit 0 */\n#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00008000) /* Bit 1 */\n#define AFIO_PCFR1_TIM2_REMAP_2 ((uint32_t)0x00010000) /* Bit 2 */\n\n#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00060000) /* TIM3_REMAP[22:21] bits (TIM3 remapping) */\n#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00020000) /* Bit 0 */\n#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00040000) /* Bit 1 */\n\n#define AFIO_PCFR1_PIOC_REMAP ((uint32_t)0x00080000) /* PIOC[23] bits (PIOC remapping) */\n\n#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */\n#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */\n#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */\n#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */\n\n/***************** Bit definition for AFIO_EXTICR1 register *****************/\n#define AFIO_EXTICR1_EXTI0 ((uint32_t)0x00000003) /* EXTI 0 configuration */\n#define AFIO_EXTICR1_EXTI1 ((uint32_t)0x0000000C) /* EXTI 1 configuration */\n#define AFIO_EXTICR1_EXTI2 ((uint32_t)0x00000030) /* EXTI 2 configuration */\n#define AFIO_EXTICR1_EXTI3 ((uint32_t)0x000000C0) /* EXTI 3 configuration */\n#define AFIO_EXTICR1_EXTI4 ((uint32_t)0x00000300) /* EXTI 4 configuration */\n#define AFIO_EXTICR1_EXTI5 ((uint32_t)0x00000C00) /* EXTI 5 configuration */\n#define AFIO_EXTICR1_EXTI6 ((uint32_t)0x00003000) /* EXTI 6 configuration */\n#define AFIO_EXTICR1_EXTI7 ((uint32_t)0x0000C000) /* EXTI 7 configuration */\n#define AFIO_EXTICR1_EXTI8 ((uint32_t)0x00030000) /* EXTI 8 configuration */\n#define AFIO_EXTICR1_EXTI9 ((uint32_t)0x000C0000) /* EXTI 9 configuration */\n#define AFIO_EXTICR1_EXTI10 ((uint32_t)0x00300000) /* EXTI 10 configuration */\n#define AFIO_EXTICR1_EXTI11 ((uint32_t)0x00C00000) /* EXTI 11 configuration */\n#define AFIO_EXTICR1_EXTI12 ((uint32_t)0x03000000) /* EXTI 12 configuration */\n#define AFIO_EXTICR1_EXTI13 ((uint32_t)0x0C000000) /* EXTI 13 configuration */\n#define AFIO_EXTICR1_EXTI14 ((uint32_t)0x30000000) /* EXTI 14 configuration */\n#define AFIO_EXTICR1_EXTI15 ((uint32_t)0xC0000000) /* EXTI 15 configuration */\n\n#define AFIO_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /* PA[0] pin */\n#define AFIO_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /* PB[0] pin */\n#define AFIO_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /* PC[0] pin */\n\n#define AFIO_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /* PA[1] pin */\n#define AFIO_EXTICR1_EXTI1_PB ((uint32_t)0x00000004) /* PB[1] pin */\n#define AFIO_EXTICR1_EXTI1_PC ((uint32_t)0x00000008) /* PC[1] pin */\n\n#define AFIO_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /* PA[2] pin */\n#define AFIO_EXTICR1_EXTI2_PB ((uint32_t)0x00000010) /* PB[2] pin */\n#define AFIO_EXTICR1_EXTI2_PC ((uint32_t)0x00000020) /* PC[2] pin */\n\n#define AFIO_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /* PA[3] pin */\n#define AFIO_EXTICR1_EXTI3_PB ((uint32_t)0x00000040) /* PB[3] pin */\n#define AFIO_EXTICR1_EXTI3_PC ((uint32_t)0x00000080) /* PC[3] pin */\n\n#define AFIO_EXTICR1_EXTI4_PA ((uint32_t)0x00000000) /* PA[4] pin */\n#define AFIO_EXTICR1_EXTI4_PB ((uint32_t)0x00000100) /* PB[4] pin */\n#define AFIO_EXTICR1_EXTI4_PC ((uint32_t)0x00000200) /* PC[4] pin */\n\n#define AFIO_EXTICR1_EXTI5_PA ((uint32_t)0x00000000) /* PA[5] pin */\n#define AFIO_EXTICR1_EXTI5_PB ((uint32_t)0x00000400) /* PB[5] pin */\n#define AFIO_EXTICR1_EXTI5_PC ((uint32_t)0x00000800) /* PC[5] pin */\n\n#define AFIO_EXTICR1_EXTI6_PA ((uint32_t)0x00000000) /* PA[6] pin */\n#define AFIO_EXTICR1_EXTI6_PB ((uint32_t)0x00001000) /* PB[6] pin */\n#define AFIO_EXTICR1_EXTI6_PC ((uint32_t)0x00002000) /* PC[6] pin */\n\n#define AFIO_EXTICR1_EXTI7_PA ((uint32_t)0x00000000) /* PA[7] pin */\n#define AFIO_EXTICR1_EXTI7_PB ((uint32_t)0x00004000) /* PB[7] pin */\n#define AFIO_EXTICR1_EXTI7_PC ((uint32_t)0x00008000) /* PC[7] pin */\n\n#define AFIO_EXTICR1_EXTI8_PA ((uint32_t)0x00000000) /* PA[8] pin */\n#define AFIO_EXTICR1_EXTI8_PB ((uint32_t)0x00010000) /* PB[8] pin */\n#define AFIO_EXTICR1_EXTI8_PC ((uint32_t)0x00020000) /* PC[8] pin */\n\n#define AFIO_EXTICR1_EXTI9_PA ((uint32_t)0x00000000) /* PA[9] pin */\n#define AFIO_EXTICR1_EXTI9_PB ((uint32_t)0x00040000) /* PB[9] pin */\n#define AFIO_EXTICR1_EXTI9_PC ((uint32_t)0x00080000) /* PC[9] pin */\n\n#define AFIO_EXTICR1_EXTI10_PA ((uint32_t)0x00000000) /* PA[10] pin */\n#define AFIO_EXTICR1_EXTI10_PB ((uint32_t)0x00100000) /* PB[10] pin */\n#define AFIO_EXTICR1_EXTI10_PC ((uint32_t)0x00200000) /* PC[10] pin */\n\n#define AFIO_EXTICR1_EXTI11_PA ((uint32_t)0x00000000) /* PA[11] pin */\n#define AFIO_EXTICR1_EXTI11_PB ((uint32_t)0x00400000) /* PB[11] pin */\n#define AFIO_EXTICR1_EXTI11_PC ((uint32_t)0x00800000) /* PC[11] pin */\n\n#define AFIO_EXTICR1_EXTI12_PA ((uint32_t)0x00000000) /* PA[12] pin */\n#define AFIO_EXTICR1_EXTI12_PB ((uint32_t)0x01000000) /* PB[12] pin */\n#define AFIO_EXTICR1_EXTI12_PC ((uint32_t)0x02000000) /* PC[12] pin */\n\n#define AFIO_EXTICR1_EXTI13_PA ((uint32_t)0x00000000) /* PA[13] pin */\n#define AFIO_EXTICR1_EXTI13_PB ((uint32_t)0x04000000) /* PB[13] pin */\n#define AFIO_EXTICR1_EXTI13_PC ((uint32_t)0x08000000) /* PC[13] pin */\n\n#define AFIO_EXTICR1_EXTI14_PA ((uint32_t)0x00000000) /* PA[14] pin */\n#define AFIO_EXTICR1_EXTI14_PB ((uint32_t)0x10000000) /* PB[14] pin */\n#define AFIO_EXTICR1_EXTI14_PC ((uint32_t)0x20000000) /* PC[14] pin */\n\n#define AFIO_EXTICR1_EXTI15_PA ((uint32_t)0x00000000) /* PA[15] pin */\n#define AFIO_EXTICR1_EXTI15_PB ((uint32_t)0x40000000) /* PB[15] pin */\n#define AFIO_EXTICR1_EXTI15_PC ((uint32_t)0x80000000) /* PC[15] pin */\n\n/***************** Bit definition for AFIO_EXTICR2 register *****************/\n#define AFIO_EXTICR2_EXTI16 ((uint32_t)0x00000003) /* EXTI 16 configuration */\n#define AFIO_EXTICR2_EXTI17 ((uint32_t)0x0000000C) /* EXTI 17 configuration */\n#define AFIO_EXTICR2_EXTI18 ((uint32_t)0x00000030) /* EXTI 18 configuration */\n#define AFIO_EXTICR2_EXTI19 ((uint32_t)0x000000C0) /* EXTI 19 configuration */\n#define AFIO_EXTICR2_EXTI20 ((uint32_t)0x00000300) /* EXTI 20 configuration */\n#define AFIO_EXTICR2_EXTI21 ((uint32_t)0x00000C00) /* EXTI 21 configuration */\n#define AFIO_EXTICR2_EXTI22 ((uint32_t)0x00003000) /* EXTI 22 configuration */\n#define AFIO_EXTICR2_EXTI23 ((uint32_t)0x0000C000) /* EXTI 23 configuration */\n\n#define AFIO_EXTICR2_EXTI16_PA ((uint32_t)0x00000000) /* PA[16] pin */\n#define AFIO_EXTICR2_EXTI16_PB ((uint32_t)0x00000001) /* PB[16] pin */\n#define AFIO_EXTICR2_EXTI16_PC ((uint32_t)0x00000002) /* PC[16] pin */\n\n#define AFIO_EXTICR2_EXTI17_PA ((uint32_t)0x00000000) /* PA[17] pin */\n#define AFIO_EXTICR2_EXTI17_PB ((uint32_t)0x00000004) /* PB[17] pin */\n#define AFIO_EXTICR2_EXTI17_PC ((uint32_t)0x00000008) /* PC[17] pin */\n\n#define AFIO_EXTICR2_EXTI18_PA ((uint32_t)0x00000000) /* PA[18] pin */\n#define AFIO_EXTICR2_EXTI18_PB ((uint32_t)0x00000010) /* PB[18] pin */\n#define AFIO_EXTICR2_EXTI18_PC ((uint32_t)0x00000020) /* PC[18] pin */\n\n#define AFIO_EXTICR2_EXTI19_PA ((uint32_t)0x00000000) /* PA[19] pin */\n#define AFIO_EXTICR2_EXTI19_PB ((uint32_t)0x00000040) /* PB[19] pin */\n#define AFIO_EXTICR2_EXTI19_PC ((uint32_t)0x00000080) /* PC[19] pin */\n\n#define AFIO_EXTICR2_EXTI20_PA ((uint32_t)0x00000000) /* PA[20] pin */\n#define AFIO_EXTICR2_EXTI20_PB ((uint32_t)0x00000100) /* PB[20] pin */\n#define AFIO_EXTICR2_EXTI20_PC ((uint32_t)0x00000200) /* PC[20] pin */\n\n#define AFIO_EXTICR2_EXTI21_PA ((uint32_t)0x00000000) /* PA[21] pin */\n#define AFIO_EXTICR2_EXTI21_PB ((uint32_t)0x00000400) /* PB[21] pin */\n#define AFIO_EXTICR2_EXTI21_PC ((uint32_t)0x00000800) /* PC[21] pin */\n\n#define AFIO_EXTICR2_EXTI22_PA ((uint32_t)0x00000000) /* PA[22] pin */\n#define AFIO_EXTICR2_EXTI22_PB ((uint32_t)0x00001000) /* PB[22] pin */\n#define AFIO_EXTICR2_EXTI22_PC ((uint32_t)0x00002000) /* PC[22] pin */\n\n#define AFIO_EXTICR2_EXTI23_PA ((uint32_t)0x00000000) /* PA[23] pin */\n#define AFIO_EXTICR2_EXTI23_PB ((uint32_t)0x00004000) /* PB[23] pin */\n#define AFIO_EXTICR2_EXTI23_PC ((uint32_t)0x00008000) /* PC[23] pin */\n\n/******************* Bit definition for AFIO_CTLR register ********************/\n#define AFIO_CTLR_UDM_PUE ((uint32_t)0x00000003) /* PC16/UDM Pin pull-up Mode*/\n#define AFIO_CTLR_UDM_PUE_0 ((uint32_t)0x00000001) /* bit[0] */\n#define AFIO_CTLR_UDM_PUE_1 ((uint32_t)0x00000002) /* bit[1] */\n#define AFIO_CTLR_UDM_PUE_1K5 ((uint32_t)0x00000003) /* pull-up 1.5KΩ */\n#define AFIO_CTLR_UDM_PUE_10K ((uint32_t)0x00000002) /* pull-up 10KΩ */\n\n#define AFIO_CTLR_UDP_PUE ((uint32_t)0x0000000c) /* PC17/UDP Pin pull-up Mode*/\n#define AFIO_CTLR_UDP_PUE_0 ((uint32_t)0x00000004) /* bit[2] */\n#define AFIO_CTLR_UDP_PUE_1 ((uint32_t)0x00000008) /* bit[3] */\n#define AFIO_CTLR_UDP_PUE_1K5 ((uint32_t)0x0000000c) /* pull-up 1.5KΩ */\n#define AFIO_CTLR_UDP_PUE_10K ((uint32_t)0x00000008) /* pull-up 10KΩ */\n\n#define AFIO_CTLR_USB_PHY_V33 ((uint32_t)0x00000040) /* USB transceiver PHY output and pull-up limiter configuration */\n#define AFIO_CTLR_USB_IOEN ((uint32_t)0x00000080) /* USB Remap pin enable */\n#define AFIO_CTLR_USBPD_PHY_V33 ((uint32_t)0x00000100) /* USBPD transceiver PHY output and pull-up limiter configuration */\n#define AFIO_CTLR_USBPD_IN_HVT ((uint32_t)0x00000200) /* PD pin PC14/PC15 high threshold input mode */\n#define AFIO_CTLR_UDP_BC_VSRC ((uint32_t)0x00010000) /* PC17/UDP pin BC protocol source voltage enable */\n#define AFIO_CTLR_UDM_BC_VSRC ((uint32_t)0x00020000) /* PC16/UDM pin BC protocol source voltage enable */\n#define AFIO_CTLR_UDP_BC_CMPO ((uint32_t)0x00040000) /* PC17/UDP pin BC protocol comparator status */\n#define AFIO_CTLR_UDM_BC_CMPO ((uint32_t)0x00080000) /* PC16/UDM pin BC protocol comparator status */\n#define AFIO_CTLR_PA3_FILT_EN ((uint32_t)0x01000000) /* Controls the input filtering of the PA3 pin */\n#define AFIO_CTLR_PA4_FILT_EN ((uint32_t)0x02000000) /* Controls the input filtering of the PA4 pin */\n#define AFIO_CTLR_PB5_FILT_EN ((uint32_t)0x04000000) /* Controls the input filtering of the PB5 pin */\n#define AFIO_CTLR_PB6_FILT_EN ((uint32_t)0x08000000) /* Controls the input filtering of the PB6 pin */\n\n\n/******************************************************************************/\n/* Independent WATCHDOG */\n/******************************************************************************/\n\n/******************* Bit definition for IWDG_CTLR register ********************/\n#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */\n\n/******************* Bit definition for IWDG_PSCR register ********************/\n#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */\n#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */\n#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */\n#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */\n\n/******************* Bit definition for IWDG_RLDR register *******************/\n#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */\n\n/******************* Bit definition for IWDG_STATR register ********************/\n#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */\n#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */\n\n/******************************************************************************/\n/* Inter-integrated Circuit Interface */\n/******************************************************************************/\n\n/******************* Bit definition for I2C_CTLR1 register ********************/\n#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */\n#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */\n#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */\n#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */\n#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */\n#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */\n#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */\n#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */\n#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */\n#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */\n#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */\n#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */\n\n/******************* Bit definition for I2C_CTLR2 register ********************/\n#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */\n#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */\n#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */\n#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */\n#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */\n#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */\n#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */\n\n#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */\n#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */\n#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */\n#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */\n#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */\n\n/******************* Bit definition for I2C_OADDR1 register *******************/\n#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */\n#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */\n\n#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */\n#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */\n#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */\n#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */\n#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */\n#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */\n#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */\n#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */\n#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */\n#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */\n\n#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */\n\n/******************* Bit definition for I2C_OADDR2 register *******************/\n#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */\n#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */\n\n/******************** Bit definition for I2C_DATAR register ********************/\n#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */\n\n/******************* Bit definition for I2C_STAR1 register ********************/\n#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */\n#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */\n#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */\n#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */\n#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */\n#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */\n#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */\n#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */\n#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */\n#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */\n#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */\n#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */\n\n/******************* Bit definition for I2C_STAR2 register ********************/\n#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */\n#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */\n#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */\n#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */\n#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */\n#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */\n\n/******************* Bit definition for I2C_CKCFGR register ********************/\n#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */\n#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */\n#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */\n\n/******************************************************************************/\n/* Operational Amplifiers and Comparators */\n/******************************************************************************/\n\n/****************** Bit definition for OPA_CFGR1 register *******************/\n#define OPA_CFGR1_POLL_EN1 ((uint16_t)0x0001) /* OPA1 positive polling enable */\n#define OPA_CFGR1_POLL_EN2 ((uint16_t)0x0002) /* OPA2 positive polling enable */\n#define OPA_CFGR1_BKIN_EN1 ((uint16_t)0x0004) /* Timer's brake input source OPA1 enable */\n#define OPA_CFGR1_BKIN_EN2 ((uint16_t)0x0008) /* Timer's brake input source OPA2 enable */\n#define OPA_CFGR1_RST_EN1 ((uint16_t)0x0010) /* OPA1 reset system enable */\n#define OPA_CFGR1_RST_EN2 ((uint16_t)0x0020) /* OPA2 reset system enable */\n#define OPA_CFGR1_BKIN_SEL ((uint16_t)0x0040) /* Timer selection for brake input connection */\n#define OPA_CFGR1_POLL_LOCK ((uint16_t)0x0080) /* POLL lock */\n#define OPA_CFGR1_IE_OUT1 ((uint16_t)0x0100) /* OPA1 interrupt enable */\n#define OPA_CFGR1_IE_OUT2 ((uint16_t)0x0200) /* OPA2 interrupt enable */\n#define OPA_CFGR1_IE_CNT ((uint16_t)0x0400) /* OPA end-of-polling-interval interrupt enable */\n#define OPA_CFGR1_NMI_EN ((uint16_t)0x0800) /* OPA connection NMI interrupt enable */\n#define OPA_CFGR1_IF_OUT1 ((uint16_t)0x1000) /* Interrupt flag for polling to an OPA1 output high */\n#define OPA_CFGR1_IF_OUT2 ((uint16_t)0x2000) /* Interrupt flag for polling to an OPA2 output high */\n#define OPA_CFGR1_IF_CNT ((uint16_t)0x4000) /* Interrupt flag for the end of the OPA polling interval */\n\n/****************** Bit definition for OPA_CFGR2 register *******************/\n#define OPA_CFGR2_POLL_VLU ((uint16_t)0x01ff) /* OPA positive end polling interval */\n#define OPA_CFGR2_POLL1_NUM ((uint16_t)0x0600) /* Configure the number of positive ends polled by OPA1 */\n#define OPA_CFGR2_POLL1_NUM_1 ((uint16_t)0x0000) /* 1, O1P0 */\n#define OPA_CFGR2_POLL1_NUM_2 ((uint16_t)0x0200) /* 2, O1P0 + O1P1 */\n#define OPA_CFGR2_POLL1_NUM_3 ((uint16_t)0x0400) /* 3, O1P0 + O1P1 + O1P2*/\n#define OPA_CFGR2_POLL2_NUM ((uint16_t)0x1800) /* Configure the number of positive ends polled by OPA2 */\n#define OPA_CFGR2_POLL2_NUM_1 ((uint16_t)0x0000) /* 1, O2P0 */\n#define OPA_CFGR2_POLL2_NUM_2 ((uint16_t)0x0800) /* 2, O2P0 + O2P1 */\n#define OPA_CFGR2_POLL2_NUM_3 ((uint16_t)0x1000) /* 3, O2P0 + O2P1 + O2P2*/\n\n/****************** Bit definition for OPA_CTLR1 register *******************/\n#define OPA_CTLR1_EN1 ((uint32_t)0x00000001) /* OPA1 enable */\n#define OPA_CTLR1_MODE1 ((uint32_t)0x00000002) /* OPA1 output channel selection */\n#define OPA_CTLR1_MODE1_PA3 ((uint32_t)0x00000000) /* OPA1 output channel is PA3 */\n#define OPA_CTLR1_MODE1_PB5 ((uint32_t)0x00000002) /* OPA1 output channel is PB5 */\n#define OPA_CTLR1_PSEL1 ((uint32_t)0x00000018) /* OPA1 positive input selection */\n#define OPA_CTLR1_PSEL1_PB0 ((uint32_t)0x00000000) /* OPA1 positive input is PB0 */\n#define OPA_CTLR1_PSEL1_PB8 ((uint32_t)0x00000008) /* OPA1 positive input is PB8 */\n#define OPA_CTLR1_PSEL1_PB4 ((uint32_t)0x00000010) /* OPA1 positive input is PB4 */\n#define OPA_CTLR1_FB_EN1 ((uint32_t)0x00000020) /* OPA1 internal feedback resistor enable */\n#define OPA_CTLR1_NSEL1 ((uint32_t)0x000001c0) /* OPA1 negative input selection and gain selection */\n#define OPA_CTLR1_NSEL1_PA6 ((uint32_t)0x00000000) /* OPA1 negative input is PA6 */\n#define OPA_CTLR1_NSEL1_PB6 ((uint32_t)0x00000040) /* OPA1 negative input is PB6 */\n#define OPA_CTLR1_NSEL1_PA1 ((uint32_t)0x00000080) /* OPA1 negative input is PA1, PGA 16x */\n#define OPA_CTLR1_NSEL1_PGA_4X ((uint32_t)0x000000c0) /* OPA1 PGA 4x amplification */\n#define OPA_CTLR1_NSEL1_PGA_8X ((uint32_t)0x00000100) /* OPA1 PGA 8x amplification */\n#define OPA_CTLR1_NSEL1_PGA_16X ((uint32_t)0x00000140) /* OPA1 PGA 16x amplification */\n#define OPA_CTLR1_NSEL1_PGA_32X ((uint32_t)0x00000180) /* OPA1 PGA 32x amplification */\n#define OPA_CTLR1_NSEL1_OFF ((uint32_t)0x000001c0) /* OPA1 negative input off */\n\n#define OPA_CTLR1_EN2 ((uint32_t)0x00010000) /* OPA2 enable */\n#define OPA_CTLR1_MODE2 ((uint32_t)0x00020000) /* OPA2 output channel selection */\n#define OPA_CTLR1_MODE2_PA4 ((uint32_t)0x00000000) /* OPA2 output channel is PA4 */\n#define OPA_CTLR1_MODE2_PA2 ((uint32_t)0x00020000) /* OPA2 output channel is PA2 */\n#define OPA_CTLR1_PSEL2 ((uint32_t)0x00180000) /* OPA2 positive input selection */\n#define OPA_CTLR1_PSEL2_PA7 ((uint32_t)0x00000000) /* OPA2 positive input is PA7 */\n#define OPA_CTLR1_PSEL2_PB3 ((uint32_t)0x00080000) /* OPA2 positive input is PB3 */\n#define OPA_CTLR1_PSEL2_PB7 ((uint32_t)0x00100000) /* OPA2 positive input is PB7 */\n#define OPA_CTLR1_FB_EN2 ((uint32_t)0x00200000) /* OPA2 internal feedback resistor enable */\n#define OPA_CTLR1_NSEL2 ((uint32_t)0x01c00000) /* OPA2 negative input selection and gain selection */\n#define OPA_CTLR1_NSEL2_PA5 ((uint32_t)0x00000000) /* OPA2 negative input is PA5 */\n#define OPA_CTLR1_NSEL2_PB1 ((uint32_t)0x00400000) /* OPA2 negative input is PB1 */\n#define OPA_CTLR1_NSEL2_PA1 ((uint32_t)0x00800000) /* OPA2 negative input is PA1, PGA 16x */\n#define OPA_CTLR1_NSEL2_PGA_4X ((uint32_t)0x00c00000) /* OPA2 PGA 4x amplification */\n#define OPA_CTLR1_NSEL2_PGA_8X ((uint32_t)0x01000000) /* OPA2 PGA 8x amplification */\n#define OPA_CTLR1_NSEL2_PGA_16X ((uint32_t)0x01400000) /* OPA2 PGA 16x amplification */\n#define OPA_CTLR1_NSEL2_PGA_32X ((uint32_t)0x01800000) /* OPA2 PGA 32x amplification */\n#define OPA_CTLR1_NSEL2_OFF ((uint32_t)0x01c00000) /* OPA2 negative input off */\n\n#define OPA_CTLR1_OPA_LOCK ((uint32_t)0x80000000) /* OPA lock */\n\n/****************** Bit definition for OPA_CTLR2 register *******************/\n#define OPA_CTLR2_EN1 ((uint32_t)0x00000001) /* CMP1 enable */\n#define OPA_CTLR2_MODE1 ((uint32_t)0x00000002) /* CMP1 output channel selection */\n#define OPA_CTLR2_MODE1_T2C1 ((uint32_t)0x00000000) /* CMP1 output channel is TIM2_CH1 */\n#define OPA_CTLR2_MODE1_PA1 ((uint32_t)0x00000002) /* CMP1 output channel is PA1 */\n#define OPA_CTLR2_NSEL1 ((uint32_t)0x00000004) /* CMP1 negative input channel selection */\n#define OPA_CTLR2_NSEL1_PC3 ((uint32_t)0x00000000) /* CMP1 negative input is PC3 */\n#define OPA_CTLR2_NSEL1_PA23 ((uint32_t)0x00000004) /* CMP1 negative input is PA23 */\n#define OPA_CTLR2_PSEL1 ((uint32_t)0x00000008) /* CMP1 negative input channel selection */\n#define OPA_CTLR2_PSEL1_PC19 ((uint32_t)0x00000000) /* CMP1 negative input is PC3 */\n#define OPA_CTLR2_PSEL1_PA0 ((uint32_t)0x00000008) /* CMP1 negative input is PA23 */\n#define OPA_CTLR2_HYEN1 ((uint32_t)0x00000010) /* CMP1 comparator hysteresis enable */\n\n#define OPA_CTLR2_EN2 ((uint32_t)0x00000020) /* CMP2 enable */\n#define OPA_CTLR2_MODE2 ((uint32_t)0x00000040) /* CMP2 output channel selection */\n#define OPA_CTLR2_MODE2_T2C2 ((uint32_t)0x00000000) /* CMP2 output channel is TIM2_CH2 */\n#define OPA_CTLR2_MODE2_PB2 ((uint32_t)0x00000040) /* CMP2 output channel is PB2 */\n#define OPA_CTLR2_NSEL2 ((uint32_t)0x00000080) /* CMP2 negative input channel selection */\n#define OPA_CTLR2_NSEL2_PA22 ((uint32_t)0x00000000) /* CMP2 negative input is PA22 */\n#define OPA_CTLR2_NSEL2_PC3 ((uint32_t)0x00000080) /* CMP2 negative input is PC3 */\n#define OPA_CTLR2_PSEL2 ((uint32_t)0x00000100) /* CMP2 negative input channel selection */\n#define OPA_CTLR2_PSEL2_PA12 ((uint32_t)0x00000000) /* CMP2 negative input is PA12 */\n#define OPA_CTLR2_PSEL2_PA11 ((uint32_t)0x00000100) /* CMP2 negative input is PA11 */\n#define OPA_CTLR2_HYEN2 ((uint32_t)0x00000200) /* CMP2 comparator hysteresis enable */\n\n#define OPA_CTLR2_EN3 ((uint32_t)0x00000400) /* CMP3 enable */\n#define OPA_CTLR2_MODE3 ((uint32_t)0x00000800) /* CMP3 output channel selection */\n#define OPA_CTLR2_MODE3_T2C3 ((uint32_t)0x00000000) /* CMP3 output channel is TIM2_CH3 */\n#define OPA_CTLR2_MODE3_PB3 ((uint32_t)0x00000800) /* CMP3 output channel is PB3 */\n#define OPA_CTLR2_NSEL3 ((uint32_t)0x00001000) /* CMP3 negative input channel selection */\n#define OPA_CTLR2_NSEL3_PA2 ((uint32_t)0x00000000) /* CMP3 negative input is PA2 */\n#define OPA_CTLR2_NSEL3_PC3 ((uint32_t)0x00001000) /* CMP3 negative input is PC3 */\n#define OPA_CTLR2_PSEL3 ((uint32_t)0x00002000) /* CMP3 negative input channel selection */\n#define OPA_CTLR2_PSEL3_PA13 ((uint32_t)0x00000000) /* CMP3 negative input is PA13 */\n#define OPA_CTLR2_PSEL3_PA14 ((uint32_t)0x00002000) /* CMP3 negative input is PA14 */\n#define OPA_CTLR2_HYEN3 ((uint32_t)0x00004000) /* CMP3 comparator hysteresis enable */\n\n#define OPA_CTLR2_CMP_LOCK ((uint32_t)0x80000000) /* CMP lock */\n\n/******************* Bit definition for OPA_KEY register ********************/\n#define OPA_KEY1 ((uint32_t)0x45670123) /* OPA unlock keys */\n#define OPA_KEY2 ((uint32_t)0xCDEF89AB) /* OPA unlock keys */\n\n/******************* Bit definition for CMP_KEY register ********************/\n#define CMP_KEY1 ((uint32_t)0x45670123) /* CMP unlock keys */\n#define CMP_KEY2 ((uint32_t)0xCDEF89AB) /* CMP unlock keys */\n\n/******************* Bit definition for POLL_KEY register *******************/\n#define POLL_KEY1 ((uint32_t)0x45670123) /* POLL unlock keys */\n#define POLL_KEY2 ((uint32_t)0xCDEF89AB) /* POLL unlock keys */\n\n/******************************************************************************/\n/* Power Control */\n/******************************************************************************/\n\n/******************** Bit definition for PWR_CTLR register ********************/\n#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */\n\n#define PWR_CTLR_PLS ((uint16_t)0x0060) /* PLS[2:0] bits (PVD Level Selection) */\n#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */\n#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */\n\n#define PWR_CTLR_PLS_2V1 ((uint16_t)0x0000)\n#define PWR_CTLR_PLS_2V3 ((uint16_t)0x0020)\n#define PWR_CTLR_PLS_3V0 ((uint16_t)0x0040)\n#define PWR_CTLR_PLS_4V0 ((uint16_t)0x0060)\n\n#define PWR_CTLR_LP_REG ((uint16_t)0x0200) /* Software configure flash into lower energy mode */\n#define PWR_CTLR_LP ((uint16_t)0x0C00) /* Software configure flash Status */\n#define PWR_CTLR_LP_0 ((uint16_t)0x0400)\n#define PWR_CTLR_LP_1 ((uint16_t)0x0800)\n\n/******************* Bit definition for PWR_CSR register ********************/\n#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */\n#define PWR_CSR_Flash_ack ((uint16_t)0x0200) /* Flash Status */\n\n/******************************************************************************/\n/* Reset and Clock Control */\n/******************************************************************************/\n\n/******************** Bit definition for RCC_CTLR register ********************/\n#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */\n#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */\n#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */\n#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */\n\n/******************* Bit definition for RCC_CFGR0 register *******************/\n#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */\n#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */\n#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */\n#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */\n#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */\n\n#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */\n#define RCC_HPRE_DIV2 ((uint32_t)0x00000010) /* SYSCLK divided by 2 */\n#define RCC_HPRE_DIV3 ((uint32_t)0x00000020) /* SYSCLK divided by 3 */\n#define RCC_HPRE_DIV4 ((uint32_t)0x00000030) /* SYSCLK divided by 4 */\n#define RCC_HPRE_DIV5 ((uint32_t)0x00000040) /* SYSCLK divided by 5 */\n#define RCC_HPRE_DIV6 ((uint32_t)0x00000050) /* SYSCLK divided by 6 */\n#define RCC_HPRE_DIV7 ((uint32_t)0x00000060) /* SYSCLK divided by 7 */\n#define RCC_HPRE_DIV8 ((uint32_t)0x00000070) /* SYSCLK divided by 8 */\n#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */\n#define RCC_HPRE_DIV32 ((uint32_t)0x000000C0) /* SYSCLK divided by 32 */\n#define RCC_HPRE_DIV64 ((uint32_t)0x000000D0) /* SYSCLK divided by 64 */\n#define RCC_HPRE_DIV128 ((uint32_t)0x000000E0) /* SYSCLK divided by 128 */\n#define RCC_HPRE_DIV256 ((uint32_t)0x000000F0) /* SYSCLK divided by 256 */\n\n#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */\n#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */\n#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */\n#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */\n\n#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */\n#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */\n#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */\n\n/***************** Bit definition for RCC_APB2PRSTR register *****************/\n#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */\n#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */\n#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */\n#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */\n#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */\n#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */\n#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */\n#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */\n\n/***************** Bit definition for RCC_APB1PRSTR register *****************/\n#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */\n#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */\n#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */\n#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */\n#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */\n#define RCC_USART4RST ((uint32_t)0x00080000) /* USART 4 reset */\n#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */\n#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */\n\n/****************** Bit definition for RCC_AHBPCENR register ******************/\n#define RCC_DMA1EN ((uint32_t)0x00000001) /* DMA1 clock enable */\n#define RCC_SRAMEN ((uint32_t)0x00000004) /* SRAM interface clock enable */\n#define RCC_USBFS ((uint32_t)0x00001000) /* USBFS clock enable */\n#define RCC_USBPD ((uint32_t)0x00020000) /* USBPD clock enable */\n\n/****************** Bit definition for RCC_APB2PCENR register *****************/\n#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */\n#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */\n#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */\n#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */\n#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */\n#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */\n#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */\n#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */\n\n/***************** Bit definition for RCC_APB1PCENR register ******************/\n#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/\n#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */\n#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */\n#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */\n#define RCC_USART3EN ((uint32_t)0x00040000) /* USART 3 clock enable */\n#define RCC_USART4EN ((uint32_t)0x00080000) /* USART 4 clock enable */\n#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */\n#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */\n\n/******************* Bit definition for RCC_RSTSCKR register ********************/\n#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */\n#define RCC_OPARSTF ((uint32_t)0x02000000) /* OPA reset flag */\n#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */\n#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */\n#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */\n#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */\n#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */\n#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */\n\n/******************* Bit definition for RCC_AHBRSTR register ********************/\n#define RCC_USBFSRST ((uint32_t)0x00001000) /* USBFS reset */\n#define RCC_PIOCRST ((uint32_t)0x00002000) /* PIOC RST */\n#define RCC_USBPDRST ((uint32_t)0x00020000) /* USBPD reset */\n\n/******************************************************************************/\n/* Serial Peripheral Interface */\n/******************************************************************************/\n\n/******************* Bit definition for SPI_CTLR1 register ********************/\n#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */\n#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */\n#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */\n\n#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */\n#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */\n#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */\n#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */\n\n#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */\n#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */\n#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */\n#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */\n#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */\n#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */\n#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */\n#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */\n#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */\n#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */\n\n/******************* Bit definition for SPI_CTLR2 register ********************/\n#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */\n#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */\n#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */\n#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */\n#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */\n#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */\n#define SPI_CTLR2_ODEN ((uint16_t)0x8000) /* SPI OD output Enable */\n\n/******************** Bit definition for SPI_STATR register ********************/\n#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */\n#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */\n#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */\n#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */\n#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */\n#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */\n#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */\n#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */\n\n/******************** Bit definition for SPI_DATAR register ********************/\n#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */\n\n/******************* Bit definition for SPI_CRCR register ******************/\n#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */\n\n/****************** Bit definition for SPI_RCRCR register ******************/\n#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */\n\n/****************** Bit definition for SPI_TCRCR register ******************/\n#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */\n\n/****************** Bit definition for SPI_HSCR register *****************/\n#define SPI_HSCR_HSRXEN ((uint16_t)0x0001) /* Read Enable under SPI High speed mode */\n\n/******************************************************************************/\n/* TIM */\n/******************************************************************************/\n\n/******************* Bit definition for TIM_CTLR1 register ********************/\n#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */\n#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */\n#define TIM_URS ((uint16_t)0x0004) /* Update request source */\n#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */\n#define TIM_DIR ((uint16_t)0x0010) /* Direction */\n\n#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */\n#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */\n#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */\n\n#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */\n\n#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */\n#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */\n#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */\n\n#define TIM_CMP_BK ((uint16_t)0x1000) /* voltage comparator break enable, TIM1 only */\n#define TIM_CAPOV ((uint16_t)0x4000) /* Cfg mode of capture value */\n#define TIM_CAPLVL ((uint16_t)0x8000) \n\n/******************* Bit definition for TIM_CTLR2 register ********************/\n#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */\n#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */\n#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */\n\n#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */\n#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */\n#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */\n#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */\n\n#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */\n#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */\n#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */\n#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */\n#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */\n#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */\n#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */\n#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */\n\n/******************* Bit definition for TIM_SMCFGR register *******************/\n#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */\n#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */\n#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */\n#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */\n\n#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */\n#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */\n#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */\n#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */\n\n#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */\n\n#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */\n#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */\n#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */\n#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */\n#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */\n\n#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */\n#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */\n#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */\n\n#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */\n#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */\n\n/******************* Bit definition for TIM_DMAINTENR register *******************/\n#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */\n#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */\n#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */\n#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */\n#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */\n#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */\n#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */\n#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */\n#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */\n#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */\n#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */\n#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */\n#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */\n#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */\n#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */\n\n/******************** Bit definition for TIM_INTFR register ********************/\n#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */\n#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */\n#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */\n#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */\n#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */\n#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */\n#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */\n#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */\n#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */\n#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */\n#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */\n#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */\n\n/******************* Bit definition for TIM_SWEVGR register ********************/\n#define TIM_UG ((uint8_t)0x01) /* Update Generation */\n#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */\n#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */\n#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */\n#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */\n#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */\n#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */\n#define TIM_BG ((uint8_t)0x80) /* Break Generation */\n\n/****************** Bit definition for TIM_CHCTLR1 register *******************/\n#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */\n#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */\n\n#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */\n#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */\n\n#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */\n#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */\n#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */\n#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */\n\n#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */\n\n#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */\n#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */\n\n#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */\n#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */\n\n#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */\n#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */\n#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */\n#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */\n\n#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */\n\n#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */\n#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */\n\n#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */\n#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */\n#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */\n#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */\n#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */\n\n#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\n#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */\n#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */\n\n#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */\n#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */\n#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */\n#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */\n#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */\n\n/****************** Bit definition for TIM_CHCTLR2 register *******************/\n#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */\n#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */\n#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */\n\n#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */\n#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */\n\n#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */\n#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */\n#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */\n#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */\n\n#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */\n\n#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */\n#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */\n\n#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */\n#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */\n\n#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */\n#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */\n#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */\n#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */\n\n#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */\n\n#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */\n#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */\n\n#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */\n#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */\n#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */\n#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */\n#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */\n\n#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */\n#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */\n\n#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */\n#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */\n#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */\n#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */\n#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */\n\n/******************* Bit definition for TIM_CCER register *******************/\n#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */\n#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */\n#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */\n#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */\n#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */\n#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */\n#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */\n#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */\n#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */\n#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */\n#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */\n#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */\n#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */\n#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */\n\n/******************* Bit definition for TIM_CNT register ********************/\n#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */\n\n/******************* Bit definition for TIM_PSC register ********************/\n#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */\n\n/******************* Bit definition for TIM_ATRLR register ********************/\n#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */\n\n/******************* Bit definition for TIM_RPTCR register ********************/\n#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */\n\n/******************* Bit definition for TIM_CH1CVR register *******************/\n#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */\n\n/******************* Bit definition for TIM_CH2CVR register *******************/\n#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */\n\n/******************* Bit definition for TIM_CH3CVR register *******************/\n#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */\n\n/******************* Bit definition for TIM_CH4CVR register *******************/\n#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */\n\n/******************* Bit definition for TIM_BDTR register *******************/\n#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */\n#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */\n#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */\n#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */\n#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */\n#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */\n#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */\n#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */\n#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */\n\n#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */\n#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */\n#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */\n\n#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */\n#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */\n#define TIM_BKE ((uint16_t)0x1000) /* Break enable */\n#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */\n#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */\n#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */\n\n/******************* Bit definition for TIM_DMACFGR register ********************/\n#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */\n#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */\n#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */\n#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */\n#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */\n#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */\n\n#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */\n#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */\n#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */\n#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */\n#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */\n#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */\n\n/******************* Bit definition for TIM_DMAADR register *******************/\n#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */\n\n/******************* Bit definition for TIM_SPEC register *******************/\n#define TIM_SPEC_PWM_EN_1_2 ((uint16_t)0x0001) /* Channel 1 and Channel 2 alternate */\n#define TIM_SPEC_PWM_EN_3_4 ((uint16_t)0x0002) /* Channel 3 and Channel 4 alternate */\n#define TIM_SPEC_PWM_OC1 ((uint16_t)0x0010) /* Channel 1 invalid level under alternate mode */\n#define TIM_SPEC_PWM_OC2 ((uint16_t)0x0020) /* Channel 2 invalid level under alternate mode */\n#define TIM_SPEC_PWM_OC3 ((uint16_t)0x0040) /* Channel 3 invalid level under alternate mode */\n#define TIM_SPEC_PWM_OC4 ((uint16_t)0x0080) /* Channel 4 invalid level under alternate mode */\n#define TIM_SPEC_TOGGLE ((uint16_t)0x8000) /* valid channel indicator */\n\n/******************************************************************************/\n/* Universal Synchronous Asynchronous Receiver Transmitter */\n/******************************************************************************/\n\n/******************* Bit definition for USART_STATR register *******************/\n#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */\n#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */\n#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */\n#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */\n#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */\n#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */\n#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */\n#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */\n#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */\n#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */\n\n/******************* Bit definition for USART_DATAR register *******************/\n#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */\n\n/****************** Bit definition for USART_BRR register *******************/\n#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */\n#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */\n\n/****************** Bit definition for USART_CTLR1 register *******************/\n#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */\n#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */\n#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */\n#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */\n#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */\n#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */\n#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */\n#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */\n#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */\n#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */\n#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */\n#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */\n#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */\n#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */\n\n/****************** Bit definition for USART_CTLR2 register *******************/\n#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */\n#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */\n#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */\n#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */\n#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */\n#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */\n#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */\n\n#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */\n#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */\n#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */\n\n#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */\n\n/****************** Bit definition for USART_CTLR3 register *******************/\n#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */\n#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */\n#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */\n#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */\n#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */\n#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */\n#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */\n#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */\n#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */\n#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */\n#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */\n\n/****************** Bit definition for USART_GPR register ******************/\n#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */\n#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */\n#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */\n#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */\n#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */\n#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */\n#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */\n#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */\n#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */\n\n#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */\n\n/******************************************************************************/\n/* Window WATCHDOG */\n/******************************************************************************/\n\n/******************* Bit definition for WWDG_CTLR register ********************/\n#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */\n#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */\n#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */\n#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */\n#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */\n#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */\n#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */\n\n#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */\n\n/******************* Bit definition for WWDG_CFGR register *******************/\n#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */\n#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */\n#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */\n#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */\n#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */\n#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */\n#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */\n#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */\n\n#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */\n#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */\n#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */\n\n#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */\n\n/******************* Bit definition for WWDG_STATR register ********************/\n#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */\n\n/******************************************************************************/\n/* PIOC */\n/******************************************************************************/\n\n/****************** Bit definition for TMR0_CTRL register *******************/\n#define PIOC_EN_LEVEL1 ((uint8_t)0x80) // RO/RW, enable IO1 level change to wakeup & action interrupt flag\n#define PIOC_EN_LEVEL0 ((uint8_t)0x40) // RO/RW, enable IO0 level change to wakeup & action interrupt flag\n#define PIOC_GP_BIT_Y ((uint8_t)0x20) // RO/RW, general-purpose bit 1, reset by power on, no effect if system reset or RB_MST_RESET reset\n#define PIOC_GP_BIT_X ((uint8_t)0x10) // RO/RW, general-purpose bit 0, reset by power on, no effect if system reset or RB_MST_RESET reset\n#define PIOC_TMR0_MODE ((uint8_t)0x08) // RO/RW, timer mode: 0-timer, 1-PWM\n#define PIOC_TMR0_FREQ2 ((uint8_t)0x04) // RO/RW, timer clock frequency selection 2\n#define PIOC_TMR0_FREQ1 ((uint8_t)0x02) // RO/RW, timer clock frequency selection 1\n#define PIOC_TMR0_FREQ0 ((uint8_t)0x01) // RO/RW, timer clock frequency selection 0\n\n/****************** Bit definition for BIT_CYCLE register *******************/\n#define PIOC_BIT_TX_IO0 ((uint8_t)0x80) // RO/RW, bit data for IO0 port encode output\n#define PIOC_BIT_CYCLE ((uint8_t)0x7F) // RO/RW, IO0 port bit data cycle -1\n\n/****************** Bit definition for PORT_DIR register ********************/\n#define PIOC_PORT_MOD3 ((uint8_t)0x80) // RO/RW, IO port mode 3\n#define PIOC_PORT_MOD2 ((uint8_t)0x40) // RO/RW, IO port mode 2\n#define PIOC_PORT_MOD1 ((uint8_t)0x20) // RO/RW, IO port mode 1\n#define PIOC_PORT_MOD0 ((uint8_t)0x10) // RO/RW, IO port mode 0\n#define PIOC_PORT_PU1 ((uint8_t)0x08) // RO/RW, IO1 port pullup enable\n#define PIOC_PORT_PU0 ((uint8_t)0x04) // RO/RW, IO0 port pullup enable\n#define PIOC_PORT_DIR1 ((uint8_t)0x02) // RO/RW, IO1 port direction\n#define PIOC_PORT_DIR0 ((uint8_t)0x01) // RO/RW, IO0 port direction\n\n/******************* Bit definition for PORT_IO register ********************/\n#define PIOC_PORT_IN_XOR ((uint8_t)0x80) // RO/RO, IO0 XOR IO1 port input\n#define PIOC_BIT_RX_I0 ((uint8_t)0x40) // RO/RO, decoced bit data for IO0 port received\n#define PIOC_PORT_IN1 ((uint8_t)0x20) // RO/RO, IO1 port input\n#define PIOC_PORT_IN0 ((uint8_t)0x10) // RO/RO, IO0 port input\n#define PIOC_PORT_XOR1 ((uint8_t)0x08) // RO/RO, IO1 port output XOR input\n#define PIOC_PORT_XOR0 ((uint8_t)0x04) // RO/RO, IO0 port output XOR input\n#define PIOC_PORT_OUT1 ((uint8_t)0x02) // RO/RW, IO1 port output\n#define PIOC_PORT_OUT0 ((uint8_t)0x01) // RO/RW, IO0 port output\n\n/******************* Bit definition for SYS_CFG register ********************/\n#define PIOC_INT_REQ ((uint8_t)0x80) // RO/RW, PIOC interrupt request action, set 1/0 by PIOC, clear 0 by master write R8_CTRL_RD (no effect)\n#define PIOC_DATA_SW_MR ((uint8_t)0x40) // RO/RO, R8_CTRL_RD wait for read status, set 1 by PIOC write R8_CTRL_RD, clear 0 by master read R8_CTRL_RD\n#define PIOC_DATA_MW_SR ((uint8_t)0x20) // RO/RO, R8_CTRL_WR wait for read status, set 1 by master write R8_CTRL_WR, clear 0 by PIOC read R8_CTRL_WR\n#define PIOC_MST_CFG_B4 ((uint8_t)0x10) // RW/RO, config inform bit, default 0\n#define PIOC_MST_IO_EN1 ((uint8_t)0x08) // RW/RO, IO1 switch enable, default 0\n#define PIOC_MST_IO_EN0 ((uint8_t)0x04) // RW/RO, IO0 switch enable, default 0\n#define PIOC_MST_RESET ((uint8_t)0x02) // RW/RO, force PIOC reset, high action, default 0\n#define PIOC_MST_CLK_GATE ((uint8_t)0x01) // RW/RO, PIOC global clock enable, high action, default 0\n\n/******************************************************************************/\n/* Programmable Fast Interrupt Controller (PFIC) */\n/******************************************************************************/\n\n/****************** Bit definition for PFIC_CFGR register *******************/\n#define PFIC_RESETSYS ((uint32_t)0x00000080) /* System reset */\n#define PFIC_KEY1 ((uint32_t)0xFA050000)\n#define PFIC_KEY2 ((uint32_t)0xBCAF0000)\n#define PFIC_KEY3 ((uint32_t)0xBEEF0000)\n\n#define NVIC_RESETSYS ((uint32_t)0x00000080)\n#define NVIC_KEY1 ((uint32_t)0xFA050000)\n#define NVIC_KEY2 ((uint32_t)0xBCAF0000)\n#define NVIC_KEY3 ((uint32_t)0xBEEF0000)\n\n/****************** Bit definition for PFIC_SCTLR register ******************/\n#define PFIC_SYSRESET ((uint32_t)0x80000000) /* System reset */\n#define PFIC_SETEVENT ((uint32_t)0x00000020) /* Set event to wake up WFE case */\n#define PFIC_SEVONPEND ((uint32_t)0x00000010) /* All events and IRQ can wake up */\n#define PFIC_WFITOWFE ((uint32_t)0x00000008) /* Treat WFI as WFE */\n#define PFIC_SLEEPDEEP ((uint32_t)0x00000004) /* 1:deep sleep; 0:sleep */\n#define PFIC_SLEEPONEXIT ((uint32_t)0x00000002) /* 1:sleep after ISR */\n\n#define NVIC_SYSRESET ((uint32_t)0x80000000)\n#define NVIC_SETEVENT ((uint32_t)0x00000020)\n#define NVIC_SEVONPEND ((uint32_t)0x00000010)\n#define NVIC_WFITOWFE ((uint32_t)0x00000008)\n#define NVIC_SLEEPDEEP ((uint32_t)0x00000004)\n#define NVIC_SLEEPONEXIT ((uint32_t)0x00000002)\n\n/******************************************************************************/\n/* System Counter (STK / SysTick) */\n/******************************************************************************/\n\n/******************* Bit definition for STK_CTLR register *******************/\n#define STK_CTLR_STE ((uint32_t)0x00000001) /* System counter enable */\n#define STK_CTLR_STIE ((uint32_t)0x00000002) /* Counter interrupt enable */\n#define STK_CTLR_STCLK ((uint32_t)0x00000004) /* 1: use HCLK; 0: use HCLK/8 */\n#define STK_CTLR_STRE ((uint32_t)0x00000008) /* Auto-reload count enable */\n#define STK_CTLR_MODE ((uint32_t)0x00000010) /* 0: upcount, 1: down count */\n#define STK_CTLR_INIT ((uint32_t)0x00000020) /* counter init value update */\n#define STK_CTLR_SWIE ((uint32_t)0x80000000) /* Software interrupt enable */\n\n/******************** Bit definition for STK_SR register ********************/\n#define STK_SR_CNTIF ((uint8_t)0x01) /* Count value comparison flag */\n\n/******************************************************************************/\n/* USBFS FUNCTION */\n/******************************************************************************/\n\n/****************************** CTRL register *******************************/\n#define USBFS_UC_DMA_EN ((uint8_t)0x01) /* Enable DMA mode */\n#define USBFS_UC_CLR_ALL ((uint8_t)0x02) /* Clear USB FIFO and interrupt flag */\n#define USBFS_UC_RESET_SIE ((uint8_t)0x04) /* Reset USB protocol processor */\n#define USBFS_UC_INT_BUSY ((uint8_t)0x08) /* Auto-suspend enable */\n#define USBFS_UC_SYS_CTRL_MASK ((uint8_t)0x30) /* USB system configuration */\n#define USBFS_UC_DEV_PU_EN ((uint8_t)0x20) /* USB device and pull-up enable */\n#define USBFS_UC_LOW_SPEED ((uint8_t)0x40) /* 0: 12Mbps, 1: 1.5Mbps */\n#define USBFS_UC_HOST_MODE ((uint8_t)0x80) /* 0: Host mode, 1: Device mode */\n\n/***************************** INT_EN register *****************************/\n#define USBFS_UIE_DETECT ((uint8_t)0x01) /* USB host: device (dis)connect interrupt */\n#define USBFS_UIE_BUS_RST ((uint8_t)0x01) /* USB device: bus reset interrupt */\n#define USBFS_UIE_TRANSFER ((uint8_t)0x02) /* USB transfer completion interrupt */\n#define USBFS_UIE_SUSPEND ((uint8_t)0x04) /* USB bus suspend/wake-up interrupt */\n#define USBFS_UIE_HST_SOF ((uint8_t)0x08) /* USB host: SOF timing interrupt */\n#define USBFS_UIE_FIFO_OV ((uint8_t)0x10) /* FIFO overrun interrupt */\n#define USBFS_UIE_DEV_NAK ((uint8_t)0x40) /* USB device: receive NAK interrupt */\n#define USBFS_UIE_DEV_SOF ((uint8_t)0x80) /* USB device: receive SOF packet interrupt */\n\n/***************************** DEV_AD register *****************************/\n#define USBFS_USB_ADDR_MASK ((uint8_t)0x7f) /* USB device address */\n#define USBFS_UDA_GP_BIT ((uint8_t)0x80) /* USB general flag, user self-defined */\n\n/***************************** MIS_ST register *****************************/\n#define USBFS_UMS_DEV_ATTACH ((uint8_t)0x01) /* USB host: USB device connected to port */\n#define USBFS_UMS_DM_LEVEL ((uint8_t)0x02) /* USB host: 0: full speed, 1: low speed */\n#define USBFS_UMS_SUSPEND ((uint8_t)0x04) /* USB suspension status */\n#define USBFS_UMS_BUS_RESET ((uint8_t)0x08) /* USB bus reset status */\n#define USBFS_UMS_R_FIFO_RDY ((uint8_t)0x10) /* USB receiver FIFO data ready status */\n#define USBFS_UMS_SIE_FREE ((uint8_t)0x20) /* USB protocol processor idle status */\n#define USBFS_UMS_SOF_ACT ((uint8_t)0x40) /* USB host: SOF packet transmission status */\n#define USBFS_UMS_SOF_PRES ((uint8_t)0x80) /* USB host: SOF packet indicator status */\n\n/***************************** INT_FG register *****************************/\n#define USBFS_UIF_DETECT ((uint8_t)0x01) /* USB host: device (dis)connect interrupt */\n#define USBFS_UIF_BUS_RST ((uint8_t)0x01) /* USB device: bus reset interrupt */\n#define USBFS_UIF_TRANSFER ((uint8_t)0x02) /* USB transfer completion interrupt */\n#define USBFS_UIF_SUSPEND ((uint8_t)0x04) /* USB bus suspend/wake-up interrupt */\n#define USBFS_UIF_HST_SOF ((uint8_t)0x08) /* USB host: SOF timing interrupt */\n#define USBFS_UIF_FIFO_OV ((uint8_t)0x10) /* FIFO overrun interrupt */\n#define USBFS_U_SIE_FREE ((uint8_t)0x20) /* USB protocol processor idle status */\n#define USBFS_U_TOG_OK ((uint8_t)0x40) /* Current synchronous flag match status */\n#define USBFS_U_IS_NAK ((uint8_t)0x80) /* USB device: NAK acknowledge status */\n\n/***************************** INT_ST register *****************************/\n#define USBFS_UIS_H_RES_MASK ((uint8_t)0x0f) /* USB host: response PID of current transfer */\n#define USBFS_UIS_ENDP_MASK ((uint8_t)0x0f) /* USB device: endpoint number of current transfer */\n#define USBFS_UIS_TOKEN_MASK ((uint8_t)0x30) /* USB device: token PID of current transfer */\n#define USBFS_UIS_TOKEN_OUT ((uint8_t)0x00)\n#define USBFS_UIS_TOKEN_SOF ((uint8_t)0x10)\n#define USBFS_UIS_TOKEN_IN ((uint8_t)0x20)\n#define USBFS_UIS_TOKEN_SETUP ((uint8_t)0x30)\n#define USBFS_UIS_TOG_OK ((uint8_t)0x40) /* Current synchronous flag match status */\n#define USBFS_UIS_SETUP_ACT ((uint8_t)0x80) /* SETUP transaction complete */\n\n/***************************** RX_LEN register *****************************/\n#define USBFS_RX_LEN_MASK ((uint16_t)0x007f) /* Number of bytes received by current endpoint */\n\n/******************************** UEP4_1_MOD *******************************/\n#define USBFS_UEP4_BUF_MOD ((uint8_t)0x01) /* Endpoint 4 data buffer mode */\n#define USBFS_UEP4_TX_EN ((uint8_t)0x04) /* Enable endpoint 4 transmission (IN) */\n#define USBFS_UEP4_RX_EN ((uint8_t)0x08) /* Enable endpoint 4 reception (OUT) */\n#define USBFS_UEP1_BUF_MOD ((uint8_t)0x10) /* Endpoint 1 data buffer mode */\n#define USBFS_UEP1_TX_EN ((uint8_t)0x40) /* Enable endpoint 1 transmission (IN) */\n#define USBFS_UEP1_RX_EN ((uint8_t)0x80) /* Enable endpoint 1 reception (OUT) */\n\n/******************************** UEP2_3_MOD *******************************/\n#define USBFS_UEP2_BUF_MOD ((uint8_t)0x01) /* Endpoint 2 data buffer mode */\n#define USBFS_UEP2_TX_EN ((uint8_t)0x04) /* Enable endpoint 2 transmission (IN) */\n#define USBFS_UEP2_RX_EN ((uint8_t)0x08) /* Enable endpoint 2 reception (OUT) */\n#define USBFS_UEP3_BUF_MOD ((uint8_t)0x10) /* Endpoint data buffer mode */\n#define USBFS_UEP3_TX_EN ((uint8_t)0x40) /* Enable endpoint transmission (IN) */\n#define USBFS_UEP3_RX_EN ((uint8_t)0x80) /* Enable endpoint 3 reception (OUT) */\n\n/******************************** UEP567_MOD ********************************/\n#define USBFS_UEP5_TX_EN ((uint8_t)0x01) /* Enable endpoint 5 transmission (IN) */\n#define USBFS_UEP5_RX_EN ((uint8_t)0x02) /* Enable endpoint 5 reception (OUT) */\n#define USBFS_UEP6_TX_EN ((uint8_t)0x04) /* Enable endpoint 6 transmission (IN) */\n#define USBFS_UEP6_RX_EN ((uint8_t)0x08) /* Enable endpoint 6 reception (OUT) */\n#define USBFS_UEP7_TX_EN ((uint8_t)0x10) /* Enable endpoint 7 transmission (IN) */\n#define USBFS_UEP7_RX_EN ((uint8_t)0x20) /* Enable endpoint 7 reception (OUT) */\n\n/******************************** UDEV_CTRL ********************************/\n#define USBFS_UD_PORT_EN ((uint8_t)0x01) /* USB device physical port enable */\n#define USBFS_UD_GP_BIT ((uint8_t)0x02) /* USB device mode general flag, user-defined */\n#define USBFS_UD_LOW_SPEED ((uint8_t)0x04) /* USB device physical port low-speed enable */\n#define USBFS_UD_DM_PIN ((uint8_t)0x10) /* Current UDM pin status */\n#define USBFS_UD_DP_PIN ((uint8_t)0x20) /* Current UDP pin status */\n#define USBFS_UD_PD_DIS ((uint8_t)0x80) /* UDP/UDM pull-down disable */\n\n/******************************** UEPn_CTRL_H ******************************/\n#define USBFS_UEP_T_RES_MASK ((uint16_t)0x0003) /* Response control by transmitter to IN services */\n#define USBFS_UEP_T_RES_ACK ((uint16_t)0x0000) /* Rensponse ACK (ready) to IN services */\n#define USBFS_UEP_T_RES_TOUT ((uint16_t)0x0001) /* No response to IN services */\n#define USBFS_UEP_T_RES_NAK ((uint16_t)0x0002) /* Rensponse NAK (busy) to IN services */\n#define USBFS_UEP_T_RES_STALL ((uint16_t)0x0003) /* Rensponse STALL (error) to IN services */\n#define USBFS_UEP_R_RES_MASK ((uint16_t)0x000c) /* Response control by transmitter to OUT services */\n#define USBFS_UEP_R_RES_ACK ((uint16_t)0x0000) /* Rensponse ACK (ready) to OUT services */\n#define USBFS_UEP_R_RES_TOUT ((uint16_t)0x0004) /* No response to OUT services */\n#define USBFS_UEP_R_RES_NAK ((uint16_t)0x0008) /* Rensponse NAK (busy) to OUT services */\n#define USBFS_UEP_R_RES_STALL ((uint16_t)0x000c) /* Rensponse STALL (error) to OUT services */\n#define USBFS_UEP_AUTO_TOG ((uint16_t)0x0010) /* Synchronous trigger bit auto flip enable */\n#define USBFS_UEP_T_TOG ((uint16_t)0x0040) /* Synchronization trigger bit for IN services */\n#define USBFS_UEP_R_TOG ((uint16_t)0x0080) /* Synchronization trigger bit for OUT services */\n#define USBFS_UEP_RES_MASK (USBFS_UEP_T_RES_MASK | USBFS_UEP_R_RES_MASK)\n\n/********************************* UEPX_MOD *********************************/\n#define USBFS_UEP8_TX_EN ((uint32_t)0x00000001) /* Enable endpoint 8 transmission (IN) */\n#define USBFS_UEP9_TX_EN ((uint32_t)0x00000002) /* Enable endpoint 9 transmission (IN) */\n#define USBFS_UEP10_TX_EN ((uint32_t)0x00000004) /* Enable endpoint 10 transmission (IN) */\n#define USBFS_UEP11_TX_EN ((uint32_t)0x00000008) /* Enable endpoint 11 transmission (IN) */\n#define USBFS_UEP12_TX_EN ((uint32_t)0x00000010) /* Enable endpoint 12 transmission (IN) */\n#define USBFS_UEP13_TX_EN ((uint32_t)0x00000020) /* Enable endpoint 13 transmission (IN) */\n#define USBFS_UEP14_TX_EN ((uint32_t)0x00000040) /* Enable endpoint 14 transmission (IN) */\n#define USBFS_UEP15_TX_EN ((uint32_t)0x00000080) /* Enable endpoint 15 transmission (IN) */\n#define USBFS_UEP8_RX_EN ((uint32_t)0x00000100) /* Enable endpoint 8 reception (OUT) */\n#define USBFS_UEP9_RX_EN ((uint32_t)0x00000200) /* Enable endpoint 9 reception (OUT) */\n#define USBFS_UEP10_RX_EN ((uint32_t)0x00000400) /* Enable endpoint 10 reception (OUT) */\n#define USBFS_UEP11_RX_EN ((uint32_t)0x00000800) /* Enable endpoint 11 reception (OUT) */\n#define USBFS_UEP12_RX_EN ((uint32_t)0x00001000) /* Enable endpoint 12 reception (OUT) */\n#define USBFS_UEP13_RX_EN ((uint32_t)0x00002000) /* Enable endpoint 13 reception (OUT) */\n#define USBFS_UEP14_RX_EN ((uint32_t)0x00004000) /* Enable endpoint 14 reception (OUT) */\n#define USBFS_UEP15_RX_EN ((uint32_t)0x00008000) /* Enable endpoint 15 reception (OUT) */\n#define USBFS_UEP8_TX_AF ((uint32_t)0x00010000) /* Enable endpoint 8 alternate (IN) */\n#define USBFS_UEP9_TX_AF ((uint32_t)0x00020000) /* Enable endpoint 9 alternate (IN) */\n#define USBFS_UEP10_TX_AF ((uint32_t)0x00040000) /* Enable endpoint 10 alternate (IN) */\n#define USBFS_UEP11_TX_AF ((uint32_t)0x00080000) /* Enable endpoint 11 alternate (IN) */\n#define USBFS_UEP12_TX_AF ((uint32_t)0x00100000) /* Enable endpoint 12 alternate (IN) */\n#define USBFS_UEP13_TX_AF ((uint32_t)0x00200000) /* Enable endpoint 13 alternate (IN) */\n#define USBFS_UEP14_TX_AF ((uint32_t)0x00400000) /* Enable endpoint 14 alternate (IN) */\n#define USBFS_UEP15_TX_AF ((uint32_t)0x00800000) /* Enable endpoint 15 alternate (IN) */\n\n/******************************** UHOST_CTRL *******************************/\n#define USBFS_UH_PORT_EN ((uint8_t)0x01) /* USB host port enable */\n#define USBFS_UH_BUS_RESET ((uint8_t)0x02) /* USB host mode bus reset */\n#define USBFS_UH_LOW_SPEED ((uint8_t)0x04) /* USB host port low-speed mode enable */\n#define USBFS_UH_DM_PIN ((uint8_t)0x10) /* Current UDM pin status */\n#define USBFS_UH_DP_PIN ((uint8_t)0x20) /* Current UDP pin status */\n#define USBFS_UH_PD_DIS ((uint8_t)0x80) /* USB host port UDP/UDM pull-down disable */\n\n/********************************* UH_EP_MOD *******************************/\n#define USBFS_UH_EP_RBUF_MOD ((uint8_t)0x01) /* USB host reception endpoint data buffer mode */\n#define USBFS_UH_EP_RX_EN ((uint8_t)0x08) /* Host reception endpoint receive (IN) enable */\n#define USBFS_UH_EP_TBUF_MOD ((uint8_t)0x10) /* Host transmission endpoint data buffer mode */\n#define USBFS_UH_EP_TX_EN ((uint8_t)0x40) /* Host transmission endpoint transmit (SETUP/OUT) enable */\n\n/********************************* UH_SETUP ********************************/\n#define USBFS_UH_SOF_EN ((uint8_t)0x40) /* Automatically generate SOF packet enable */\n#define USBFS_UH_PRE_PID_EN ((uint8_t)0x80) /* Low-speed preamble packet PRE PID enable */\n\n/********************************* UH_EP_PID *******************************/\n#define USBFS_UH_ENDP_MASK ((uint8_t)0x0f) /* Set endpoint number of current target device */\n#define USBFS_UH_TOKEN_MASK ((uint8_t)0xf0) /* Set token PID identification of this USB transmission */\n\n/******************************** UH_RX_CTRL *******************************/\n#define USBFS_UH_R_RES ((uint8_t)0x04) /* Control on response to IN transactions */\n#define USBFS_UH_R_AUTO_TOG ((uint8_t)0x10) /* Synchronous trigger bit auto flip enable */\n#define USBFS_UH_R_TOG ((uint8_t)0x80) /* Synchronous trigger bit expected by receiver */\n\n/******************************** UH_TX_CTRL *******************************/\n#define USBFS_UH_T_RES ((uint8_t)0x01) /* Response control to SETUP/OUT transaction */\n#define USBFS_UH_T_AUTO_TOG ((uint8_t)0x10) /* Synchronous trigger bit auto flip enable */\n#define USBFS_UH_T_TOG ((uint8_t)0x40) /* Synchronous trigger bit prepared by transmitter */\n\n/*************************** USB host mode aliases *************************/\n#define USBFS_UHOST_CTRL USBFS_UDEV_CTRL\n#define USBFS_UH_EP_MOD USBFS_UEP2_3_MOD\n#define USBFS_UH_RX_DMA USBFS_UEP2_DMA\n#define USBFS_UH_TX_DMA USBFS_UEP3_DMA\n#define USBFS_UH_SETUP USBFS_UEP1_CTRL\n#define USBFS_UH_EP_PID USBFS_UEP2_T_LEN\n#define USBFS_UH_RX_CTRL USBFS_UEP2_CTRL\n#define USBFS_UH_TX_LEN USBFS_UEP3_T_LEN\n#define USBFS_UH_TX_CTRL USBFS_UEP3_CTRL\n\n/************************ AFIO->CTLR register aliases **********************/\n#define USBFS_UDM_PUE AFIO_CTLR_UDM_PUE /* PC16/UDM Pin pull-up Mode*/\n#define USBFS_UDM_PUE_1K5 AFIO_CTLR_UDM_PUE_1K5 /* pull-up 1.5KΩ */\n#define USBFS_UDM_PUE_10K AFIO_CTLR_UDM_PUE_10K /* pull-up 10KΩ */\n\n#define USBFS_UDP_PUE AFIO_CTLR_UDP_PUE /* PC17/UDP Pin pull-up Mode*/\n#define USBFS_UDP_PUE_1K5 AFIO_CTLR_UDP_PUE_1K5 /* pull-up 1.5KΩ */\n#define USBFS_UDP_PUE_10K AFIO_CTLR_UDP_PUE_10K /* pull-up 10KΩ */\n\n#define USBFS_USB_PHY_V33 AFIO_CTLR_USB_PHY_V33 /* USB transceiver PHY output and pull-up limiter configuration */\n#define USBFS_USB_IOEN AFIO_CTLR_USB_IOEN /* USB Remap pin enable */\n\n/******************************************************************************/\n/* USBPD FUNCTION */\n/******************************************************************************/\n\n/***************************** CONFIG register ******************************/\n#define USBPD_PD_FILT_EN ((uint16_t)0x0001) // input filter enable on the PD pin\n#define USBPD_PD_ALL_CLR ((uint16_t)0x0002) // clear all interrupt flags\n#define USBPD_CC_SEL ((uint16_t)0x0004) // select current PD port (0:CC1, 1:CC2)\n#define USBPD_PD_DMA_EN ((uint16_t)0x0008) // enable DMA function and DMA interrupt\n#define USBPD_PD_RST_EN ((uint16_t)0x0010) // PD mode reset command enable\n#define USBPD_WAKE_POLAR ((uint16_t)0x0020) // PD port wake-up level (0:active low, 1: active high)\n#define USBPD_IE_PD_IO ((uint16_t)0x0400) // PD IO interrupt enable\n#define USBPD_IE_RX_BIT ((uint16_t)0x0800) // receive bit interrupt enable\n#define USBPD_IE_RX_BYTE ((uint16_t)0x1000) // receive byte interrupt enable\n#define USBPD_IE_RX_ACT ((uint16_t)0x2000) // receive complete interrupt enable\n#define USBPD_IE_RX_RESET ((uint16_t)0x4000) // receive reset interrupt enable\n#define USBPD_IE_TX_END ((uint16_t)0x8000) // transmit end interrupt enable\n\n/***************************** CONTROL register *****************************/\n#define USBPD_PD_TX_EN ((uint8_t)0x01) // PD mode (0: RX enable, 1: TX enable)\n#define USBPD_BMC_START ((uint8_t)0x02) // BMC transmit start signal\n#define USBPD_RX_STATE ((uint8_t)0x1c) // PD receive status identification\n#define USBPD_DATA_FLAG ((uint8_t)0x20) // cache data valid flag bit\n#define USBPD_TX_BIT_BACK ((uint8_t)0x40) // current bit status of the BMC (0: idle, 1: BMC byte is being transmitted)\n#define USBPD_BMC_BYTE_HI ((uint8_t)0x80) // current half-byte status PD data (0: low nibble, 1: high nibble)\n\n#define USBPD_RX_STATE_INIT ((uint8_t)0x00) // receive initial status\n#define USBPD_RX_STATE_START ((uint8_t)0x04) // start receiving SOP\n#define USBPD_RX_STATE_RESET ((uint8_t)0x08) // receive reset\n#define USBPD_RX_STATE_SOP ((uint8_t)0x0c) // receive SOP\n#define USBPD_RX_STATE_END ((uint8_t)0x10) // receive end\n#define USBPD_RX_STATE_UNUSED ((uint8_t)0x14) // receive unused\n#define USBPD_RX_STATE_EOP ((uint8_t)0x18) // receive EOP\n#define USBPD_RX_STATE_BYTE ((uint8_t)0x1c) // receive byte\n\n/****************************** TX_SEL register ******************************/\n#define USBPD_TX_SEL1 ((uint8_t)0x01) // K-CODE1 type selection in PD transmit mode\n#define USBPD_TX_SEL2 ((uint8_t)0x0c) // K-CODE2 type selection in PD transmit mode\n#define USBPD_TX_SEL3 ((uint8_t)0x30) // K-CODE3 type selection in PD transmit mode\n#define USBPD_TX_SEL4 ((uint8_t)0xc0) // K-CODE4 type selection in PD transmit mode\n\n#define USBPD_TX_SEL1_SYNC1 ((uint8_t)0x00) // SYNC1\n#define USBPD_TX_SEL1_RST1 ((uint8_t)0x01) // RST1\n#define USBPD_TX_SEL2_SYNC1 ((uint8_t)0x00) // SYNC1\n#define USBPD_TX_SEL2_SYNC3 ((uint8_t)0x04) // SYNC3\n#define USBPD_TX_SEL2_RST1 ((uint8_t)0x08) // RST1\n#define USBPD_TX_SEL3_SYNC1 ((uint8_t)0x00) // SYNC1\n#define USBPD_TX_SEL3_SYNC3 ((uint8_t)0x10) // SYNC3\n#define USBPD_TX_SEL3_RST1 ((uint8_t)0x20) // RST1\n#define USBPD_TX_SEL4_SYNC2 ((uint8_t)0x00) // SYNC2\n#define USBPD_TX_SEL4_SYNC3 ((uint8_t)0x40) // SYNC3\n#define USBPD_TX_SEL4_RST1 ((uint8_t)0x80) // RST2\n\n#define USBPD_TX_SOP0 (USBPD_TX_SEL1_SYNC1 | USBPD_TX_SEL2_SYNC1 | USBPD_TX_SEL3_SYNC1 | USBPD_TX_SEL4_SYNC2) // Start of Packet Sequence\n#define USBPD_TX_SOP1 (USBPD_TX_SEL1_SYNC1 | USBPD_TX_SEL2_SYNC1 | USBPD_TX_SEL3_SYNC3 | USBPD_TX_SEL4_SYNC3) // Start of Packet Sequence Prime\n#define USBPD_TX_SOP2 (USBPD_TX_SEL1_SYNC1 | USBPD_TX_SEL2_SYNC3 | USBPD_TX_SEL3_SYNC1 | USBPD_TX_SEL4_SYNC3) // Start of Packet Sequence Double Prime\n#define USBPD_TX_HARD_RESET (USBPD_TX_SEL1_RST1 | USBPD_TX_SEL2_RST1 | USBPD_TX_SEL3_RST1 | USBPD_TX_SEL4_RST2 ) // Hard Reset\n#define USBPD_TX_CABLE_RESET (USBPD_TX_SEL1_RST1 | USBPD_TX_SEL2_SYNC1 | USBPD_TX_SEL3_RST1 | USBPD_TX_SEL4_SYNC3) // Cable Reset\n\n/****************************** STATUS register ******************************/\n#define USBPD_BMC_AUX ((uint8_t)0x03) // current PD status\n#define USBPD_BUF_ERR ((uint8_t)0x04) // BUFFER or DMA error interrupt flag, write 1 to clear\n#define USBPD_IF_RX_BIT ((uint8_t)0x08) // receive bit or 5bit interrupt flag, write 1 to clear\n#define USBPD_IF_RX_BYTE ((uint8_t)0x10) // receive byte or SOP interrupt flag, write 1 to clear\n#define USBPD_IF_RX_ACT ((uint8_t)0x20) // receive complete interrupt flag, write 1 to clear\n#define USBPD_IF_RX_RESET ((uint8_t)0x40) // receive reset interrupt flag, write 1 to clear\n#define USBPD_IF_TX_END ((uint8_t)0x80) // transmit complete interrupt flag, write 1 to clear\n\n#define USBPD_BMC_AUX_INVALID ((uint8_t)0x00) // reception idle or no valid packet received\n#define USBPD_BMC_AUX_SOP0 ((uint8_t)0x01) // SOP received i.e. SOP0\n#define USBPD_BMC_AUX_SOP1_HRST ((uint8_t)0x02) // SOP received i.e. SOP1 or hard reset\n#define USBPD_BMC_AUX_SOP2_CRST ((uint8_t)0x03) // SOP received i.e. SOP2 or cable reset\n\n#define USBPD_BMC_AUX_CRC0 ((uint8_t)0x00) // CRC32[ 7: 0] is being transmitted\n#define USBPD_BMC_AUX_CRC1 ((uint8_t)0x01) // CRC32[15: 8] is being transmitted\n#define USBPD_BMC_AUX_CRC2 ((uint8_t)0x02) // CRC32[23:16] is being transmitted\n#define USBPD_BMC_AUX_CRC3 ((uint8_t)0x03) // CRC32[31:24] is being transmitted\n\n/***************************** PORT_CCx register *****************************/\n#define USBPD_PA_CC_AI ((uint16_t)0x0001) // CCx port comparator analog input\n#define USBPD_CC_PD ((uint16_t)0x0002) // CCx port pull-down enable\n#define USBPD_CC_PU ((uint16_t)0x000c) // CCx port pull-up current selection\n#define USBPD_CC_LVE ((uint16_t)0x0010) // CCx port output low voltage enable\n#define USBPD_CC_CE ((uint16_t)0x00e0) // CCx voltage comparator enable\n\n#define USBPD_CC_PU_CLR ((uint16_t)0x000c) // CCx port pull-up current selection\n#define USBPD_CC_PU_NO ((uint16_t)0x0000) // pull-up current disable\n#define USBPD_CC_PU_330 ((uint16_t)0x0004) // 330uA\n#define USBPD_CC_PU_180 ((uint16_t)0x0008) // 180uA\n#define USBPD_CC_PU_80 ((uint16_t)0x000c) // 80uA\n\n#define USBPD_CC_CMP_NO ((uint16_t)0x0000) // CCx voltage comparator disable\n#define USBPD_CC_CMP_22 ((uint16_t)0x0040) // 0.22V\n#define USBPD_CC_CMP_43 ((uint16_t)0x0060) // 0.43V\n#define USBPD_CC_CMP_55 ((uint16_t)0x0080) // 0.55V\n#define USBPD_CC_CMP_66 ((uint16_t)0x00a0) // 0.66V\n#define USBPD_CC_CMP_96 ((uint16_t)0x00c0) // 0.96V\n#define USBPD_CC_CMP_123 ((uint16_t)0x00e0) // 1.23V\n\n/************************* AFIO->CTLR register aliases ***********************/\n#define USBPD_IN_HVT AFIO_CTLR_USBPD_IN_HVT // PD pin PC14/PC15 high threshold input mode\n#define USBPD_PHY_V33 AFIO_CTLR_USBPD_PHY_V33 // USBPD transceiver PHY output and pull-up limiter configuration\n\n#ifdef __cplusplus\n}\n#endif\n" }, { "path": "software/pd_tester/src/gpio.h", "content": "// ===================================================================================\n// Basic GPIO Functions for CH32X035/X034/X033 * v0.4 *\n// ===================================================================================\n//\n// Pins must be defined as PA0, PA1, .., PB0, PB1, .. - e.g.:\n// #define PIN_LED PC0 // LED on pin PC0\n//\n// PIN functions available:\n// ------------------------\n// PIN_input(PIN) set PIN as INPUT (floating, no pullup/pulldown)\n// PIN_input_PU(PIN) set PIN as INPUT with internal PULLUP resistor\n// PIN_input_PD(PIN) set PIN as INPUT with internal PULLDOWN resistor\n// PIN_input_AN(PIN) set PIN as INPUT for analog peripherals (e.g. ADC) (*)\n// PIN_output(PIN) set PIN as OUTPUT (push-pull)\n// PIN_alternate(PIN) set PIN as alternate output mode\n//\n// PIN_low(PIN) set PIN output value to LOW (*)\n// PIN_high(PIN) set PIN output value to HIGH\n// PIN_toggle(PIN) TOGGLE PIN output value\n// PIN_read(PIN) read PIN input value\n// PIN_write(PIN, val) write PIN output value (0 = LOW / 1 = HIGH)\n//\n// PIN interrupt and event functions available:\n// --------------------------------------------\n// PIN_EVT_set(PIN,TYPE) Setup PIN event TYPE:\n// PIN_EVT_OFF, PIN_EVT_RISING, PIN_EVT_FALLING, PIN_EVT_BOTH\n// PIN_INT_set(PIN,TYPE) Setup PIN interrupt TYPE:\n// PIN_INT_OFF, PIN_INT_RISING, PIN_INT_FALLING, PIN_INT_BOTH\n// PIN_INT_enable() Enable PIN interrupts\n// PIN_INT_disable() Disable PIN interrupts\n// PIN_INTFLAG_read(PIN) Read interrupt flag of PIN\n// PIN_INTFLAG_clear(PIN) Clear interrupt flag of PIN\n// PIN_INT_ISR { } Pin interrupt service routine\n//\n// PORT functions available:\n// -------------------------\n// PORT_enable(PIN) enable GPIO PORT of PIN\n// PORTA_enable() enable GPIO PORT A\n// PORTB_enable() enable GPIO PORT B\n// PORTC_enable() enable GPIO PORT C\n// PORTS_enable() enable all GPIO PORTS\n//\n// PORT_disable(PIN) disable GPIO PORT of PIN\n// PORTA_disable() disable GPIO PORT A\n// PORTB_disable() disable GPIO PORT B\n// PORTC_disable() disable GPIO PORT C\n// PORTS_disable() disable all GPIO PORTS\n//\n// Analog-to-Digital Converter (ADC) functions available:\n// ------------------------------------------------------\n// ADC_init() init and enable ADC (must be called first)\n// ADC_enable() enable ADC (power-up)\n// ADC_disable() disable ADC (power-down) (*)\n// ADC_fast() set fast mode (fast speed, least accurate)\n// ADC_slow() set slow mode (slow speed, most accurate) (*)\n// ADC_medium() set medium mode (medium speed, medium accurate)\n//\n// ADC_input(PIN) set PIN as ADC input\n// ADC_input_VREF() set internal voltage referece (Vref) as ADC input\n//\n// ADC_read() sample and read 12-bit ADC value (0..4095)\n// ADC_read_VDD() sample and read supply voltage (VDD) in millivolts (mV)\n//\n// Analog Comparator (CMP) functions available:\n// --------------------------------------------\n// CMP_lock() lock comparators (*)\n// CMP_unlock() unlock comparators\n//\n// CMPx_enable() enable CMPx (x = 1..3)\n// CMPx_disable() disable CMPx (*)\n// CMPx_HYS_enable() enable CMPx hysteresis\n// CMPx_HYS_disable() disable CMPx hysteresis (*)\n//\n// CMP1_OUT_PA1() set CMP1 output to pin PA1\n// CMP1_OUT_T2C1() set CMP1 output to timer2, channel1 (*)\n// CMP1_NEG_PA23() set CMP1 negative input to pin PA23\n// CMP1_NEG_PC3() set CMP1 negative input to pin PC3 (*)\n// CMP1_POS_PA0() set CMP1 positive input to pin PA0\n// CMP1_POS_PC19() set CMP1 positive input to pin PC19 (*)\n//\n// CMP2_OUT_PB2() set CMP2 output to pin PB2\n// CMP2_OUT_T2C2() set CMP2 output to timer2, channel2 (*)\n// CMP2_NEG_PC3() set CMP2 negative input to pin PC3\n// CMP2_NEG_PA22() set CMP2 negative input to pin PA22 (*)\n// CMP2_POS_PA11() set CMP2 positive input to pin PA11\n// CMP2_POS_PA12() set CMP2 positive input to pin PA12 (*)\n//\n// CMP3_OUT_PB3() set CMP3 output to pin PB3\n// CMP3_OUT_T2C3() set CMP3 output to timer2, channel3 (*)\n// CMP3_NEG_PC3() set CMP3 negative input to pin PC3\n// CMP3_NEG_PA2() set CMP3 negative input to pin PA2 (*)\n// CMP3_POS_PA14() set CMP3 positive input to pin PA14\n// CMP3_POS_PA13() set CMP3 positive input to pin PA13 (*)\n//\n// Operational Amplifier (OPA) functions available:\n// ------------------------------------------------\n// not yet implemented\n//\n// Touch Key (TK) functions available:\n// -----------------------------------\n// TK_init() init and enable touch key functions (must be called first)\n// TK_input(PIN) set PIN as touch key input\n// TK_read() returns TRUE if touch key is pressed\n//\n// Notes:\n// ------\n// - (*) default state\n// - For interrupts and events: Each PIN number can only be used once simultaneously.\n// (For example, PA1 and PC1 cannot be used simultaneously, but PA1 and PC2).\n// - Pins used for ADC must be set with PIN_input_AN beforehand. ADC input pins are:\n// PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PB0, PB1, PC0, PC1, PC2, PC3.\n//\n// 2023 by Stefan Wagner: https://github.com/wagiminator\n\n#pragma once\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"system.h\"\n\n// ===================================================================================\n// Enumerate PIN Designators (use these designators to define pins)\n// ===================================================================================\nenum{\n PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15,\n PA16, PA17, PA18, PA19, PA20, PA21, PA22, PA23, PA24, PA25, PA26, PA27, PA28, PA29, PA30, PA31,\n PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15,\n PB16, PB17, PB18, PB19, PB20, PB21, PB22, PB23, PB24, PB25, PB26, PB27, PB28, PB29, PB30, PB31,\n PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15,\n PC16, PC17, PC18, PC19, PC20, PC21, PC22, PC23\n};\n\n// ===================================================================================\n// Set PIN as INPUT (high impedance, no pullup/pulldown)\n// ===================================================================================\n#define PIN_input(PIN) \\\n ((PIN>=PA0)&&(PIN<=PA7) ? ( GPIOA->CFGLR = (GPIOA->CFGLR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b0100<<(((PIN)&7)<<2))) : \\\n ((PIN>=PA8)&&(PIN<=PA15) ? ( GPIOA->CFGHR = (GPIOA->CFGHR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b0100<<(((PIN)&7)<<2))) : \\\n ((PIN>=PA16)&&(PIN<=PA23) ? ( GPIOA->CFGXR = (GPIOA->CFGXR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b0100<<(((PIN)&7)<<2))) : \\\n ((PIN>=PB0)&&(PIN<=PB7) ? ( GPIOB->CFGLR = (GPIOB->CFGLR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b0100<<(((PIN)&7)<<2))) : \\\n ((PIN>=PB8)&&(PIN<=PB15) ? ( GPIOB->CFGHR = (GPIOB->CFGHR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b0100<<(((PIN)&7)<<2))) : \\\n ((PIN>=PB16)&&(PIN<=PB23) ? ( GPIOB->CFGXR = (GPIOB->CFGXR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b0100<<(((PIN)&7)<<2))) : \\\n ((PIN>=PC0)&&(PIN<=PC7) ? ( GPIOC->CFGLR = (GPIOC->CFGLR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b0100<<(((PIN)&7)<<2))) : \\\n ((PIN>=PC8)&&(PIN<=PC15) ? ( GPIOC->CFGHR = (GPIOC->CFGHR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b0100<<(((PIN)&7)<<2))) : \\\n ((PIN>=PC16)&&(PIN<=PC23) ? ( GPIOC->CFGXR = (GPIOC->CFGXR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b0100<<(((PIN)&7)<<2))) : \\\n(0))))))))))\n#define PIN_input_HI PIN_input\n#define PIN_input_FL PIN_input\n\n// ===================================================================================\n// Set PIN as INPUT with internal PULLUP resistor\n// ===================================================================================\n#define PIN_input_PU(PIN) \\\n ((PIN>=PA0)&&(PIN<=PA7) ? ({GPIOA->CFGLR = (GPIOA->CFGLR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1000<<(((PIN)&7)<<2)); \\\n GPIOA->BSHR = ((uint32_t)1<<((PIN)&15)); }) : \\\n ((PIN>=PA8)&&(PIN<=PA15) ? ({GPIOA->CFGHR = (GPIOA->CFGHR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1000<<(((PIN)&7)<<2)); \\\n GPIOA->BSHR = ((uint32_t)1<<((PIN)&15)); }) : \\\n ((PIN>=PA16)&&(PIN<=PA23) ? ({GPIOA->CFGXR = (GPIOA->CFGXR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1000<<(((PIN)&7)<<2)); \\\n GPIOA->BSXR = ((uint32_t)1<<((PIN)&15)); }) : \\\n ((PIN>=PB0)&&(PIN<=PB7) ? ({GPIOB->CFGLR = (GPIOB->CFGLR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1000<<(((PIN)&7)<<2)); \\\n GPIOB->BSHR = ((uint32_t)1<<((PIN)&15)); }) : \\\n ((PIN>=PB8)&&(PIN<=PB15) ? ({GPIOB->CFGHR = (GPIOB->CFGHR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1000<<(((PIN)&7)<<2)); \\\n GPIOB->BSHR = ((uint32_t)1<<((PIN)&15)); }) : \\\n ((PIN>=PB16)&&(PIN<=PB23) ? ({GPIOB->CFGXR = (GPIOB->CFGXR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1000<<(((PIN)&7)<<2)); \\\n GPIOB->BSXR = ((uint32_t)1<<((PIN)&15)); }) : \\\n ((PIN>=PC0)&&(PIN<=PC7) ? ({GPIOC->CFGLR = (GPIOC->CFGLR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1000<<(((PIN)&7)<<2)); \\\n GPIOC->BSHR = ((uint32_t)1<<((PIN)&15)); }) : \\\n ((PIN>=PC8)&&(PIN<=PC15) ? ({GPIOC->CFGHR = (GPIOC->CFGHR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1000<<(((PIN)&7)<<2)); \\\n GPIOC->BSHR = ((uint32_t)1<<((PIN)&15)); }) : \\\n ((PIN>=PC16)&&(PIN<=PC23) ? ({GPIOC->CFGXR = (GPIOC->CFGXR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1000<<(((PIN)&7)<<2)); \\\n GPIOC->BSXR = ((uint32_t)1<<((PIN)&15)); }) : \\\n(0))))))))))\n\n// ===================================================================================\n// Set PIN as INPUT with internal PULLDOWN resistor\n// ===================================================================================\n#define PIN_input_PD(PIN) \\\n ((PIN>=PA0)&&(PIN<=PA7) ? ({GPIOA->CFGLR = (GPIOA->CFGLR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1000<<(((PIN)&7)<<2)); \\\n GPIOA->BSHR = (((uint32_t)1<<16)<<((PIN)&15));}) : \\\n ((PIN>=PA8)&&(PIN<=PA15) ? ({GPIOA->CFGHR = (GPIOA->CFGHR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1000<<(((PIN)&7)<<2)); \\\n GPIOA->BSHR = (((uint32_t)1<<16)<<((PIN)&15));}) : \\\n ((PIN>=PA16)&&(PIN<=PA23) ? ({GPIOA->CFGXR = (GPIOA->CFGXR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1000<<(((PIN)&7)<<2)); \\\n GPIOA->BSXR = (((uint32_t)1<<16)<<((PIN)&15));}) : \\\n ((PIN>=PB0)&&(PIN<=PB7) ? ({GPIOB->CFGLR = (GPIOB->CFGLR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1000<<(((PIN)&7)<<2)); \\\n GPIOB->BSHR = (((uint32_t)1<<16)<<((PIN)&15));}) : \\\n ((PIN>=PB8)&&(PIN<=PB15) ? ({GPIOB->CFGHR = (GPIOB->CFGHR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1000<<(((PIN)&7)<<2)); \\\n GPIOB->BSHR = (((uint32_t)1<<16)<<((PIN)&15));}) : \\\n ((PIN>=PB16)&&(PIN<=PB23) ? ({GPIOB->CFGXR = (GPIOB->CFGXR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1000<<(((PIN)&7)<<2)); \\\n GPIOB->BSXR = (((uint32_t)1<<16)<<((PIN)&15));}) : \\\n ((PIN>=PC0)&&(PIN<=PC7) ? ({GPIOC->CFGLR = (GPIOC->CFGLR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1000<<(((PIN)&7)<<2)); \\\n GPIOC->BSHR = (((uint32_t)1<<16)<<((PIN)&15));}) : \\\n ((PIN>=PC8)&&(PIN<=PC15) ? ({GPIOC->CFGHR = (GPIOC->CFGHR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1000<<(((PIN)&7)<<2)); \\\n GPIOC->BSHR = (((uint32_t)1<<16)<<((PIN)&15));}) : \\\n ((PIN>=PC16)&&(PIN<=PC23) ? ({GPIOC->CFGXR = (GPIOC->CFGXR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1000<<(((PIN)&7)<<2)); \\\n GPIOC->BSXR = (((uint32_t)1<<16)<<((PIN)&15));}) : \\\n(0))))))))))\n\n// ===================================================================================\n// Set PIN as INPUT for analog peripherals (e.g. ADC)\n// ===================================================================================\n#define PIN_input_AN(PIN) \\\n ((PIN>=PA0)&&(PIN<=PA7) ? ( GPIOA->CFGLR &= ~((uint32_t)0b1111<<(((PIN)&7)<<2)) ) : \\\n ((PIN>=PA8)&&(PIN<=PA15) ? ( GPIOA->CFGHR &= ~((uint32_t)0b1111<<(((PIN)&7)<<2)) ) : \\\n ((PIN>=PA16)&&(PIN<=PA23) ? ( GPIOA->CFGXR &= ~((uint32_t)0b1111<<(((PIN)&7)<<2)) ) : \\\n ((PIN>=PB0)&&(PIN<=PB7) ? ( GPIOB->CFGLR &= ~((uint32_t)0b1111<<(((PIN)&7)<<2)) ) : \\\n ((PIN>=PB8)&&(PIN<=PB15) ? ( GPIOB->CFGHR &= ~((uint32_t)0b1111<<(((PIN)&7)<<2)) ) : \\\n ((PIN>=PB16)&&(PIN<=PB23) ? ( GPIOB->CFGXR &= ~((uint32_t)0b1111<<(((PIN)&7)<<2)) ) : \\\n ((PIN>=PC0)&&(PIN<=PC7) ? ( GPIOC->CFGLR &= ~((uint32_t)0b1111<<(((PIN)&7)<<2)) ) : \\\n ((PIN>=PC8)&&(PIN<=PC15) ? ( GPIOC->CFGHR &= ~((uint32_t)0b1111<<(((PIN)&7)<<2)) ) : \\\n ((PIN>=PC16)&&(PIN<=PC23) ? ( GPIOC->CFGXR &= ~((uint32_t)0b1111<<(((PIN)&7)<<2)) ) : \\\n(0))))))))))\n#define PIN_input_AD PIN_input_AN\n#define PIN_input_ADC PIN_input_AN\n\n// ===================================================================================\n// Set PIN as OUTPUT (push-pull)\n// ===================================================================================\n#define PIN_output(PIN) \\\n ((PIN>=PA0)&&(PIN<=PA7) ? ( GPIOA->CFGLR = (GPIOA->CFGLR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b0011<<(((PIN)&7)<<2))) : \\\n ((PIN>=PA8)&&(PIN<=PA15) ? ( GPIOA->CFGHR = (GPIOA->CFGHR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b0011<<(((PIN)&7)<<2))) : \\\n ((PIN>=PA16)&&(PIN<=PA23) ? ( GPIOA->CFGXR = (GPIOA->CFGXR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b0011<<(((PIN)&7)<<2))) : \\\n ((PIN>=PB0)&&(PIN<=PB7) ? ( GPIOB->CFGLR = (GPIOB->CFGLR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b0011<<(((PIN)&7)<<2))) : \\\n ((PIN>=PB8)&&(PIN<=PB15) ? ( GPIOB->CFGHR = (GPIOB->CFGHR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b0011<<(((PIN)&7)<<2))) : \\\n ((PIN>=PB16)&&(PIN<=PB23) ? ( GPIOB->CFGXR = (GPIOB->CFGXR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b0011<<(((PIN)&7)<<2))) : \\\n ((PIN>=PC0)&&(PIN<=PC7) ? ( GPIOC->CFGLR = (GPIOC->CFGLR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b0011<<(((PIN)&7)<<2))) : \\\n ((PIN>=PC8)&&(PIN<=PC15) ? ( GPIOC->CFGHR = (GPIOC->CFGHR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b0011<<(((PIN)&7)<<2))) : \\\n ((PIN>=PC16)&&(PIN<=PC23) ? ( GPIOC->CFGXR = (GPIOC->CFGXR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b0011<<(((PIN)&7)<<2))) : \\\n(0))))))))))\n#define PIN_output_PP PIN_output\n\n// ===================================================================================\n// Set PIN as alternate output mode\n// ===================================================================================\n#define PIN_alternate(PIN) \\\n ((PIN>=PA0)&&(PIN<=PA7) ? ( GPIOA->CFGLR = (GPIOA->CFGLR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1011<<(((PIN)&7)<<2))) : \\\n ((PIN>=PA8)&&(PIN<=PA15) ? ( GPIOA->CFGHR = (GPIOA->CFGHR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1011<<(((PIN)&7)<<2))) : \\\n ((PIN>=PA16)&&(PIN<=PA23) ? ( GPIOA->CFGXR = (GPIOA->CFGXR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1011<<(((PIN)&7)<<2))) : \\\n ((PIN>=PB0)&&(PIN<=PB7) ? ( GPIOB->CFGLR = (GPIOB->CFGLR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1011<<(((PIN)&7)<<2))) : \\\n ((PIN>=PB8)&&(PIN<=PB15) ? ( GPIOB->CFGHR = (GPIOB->CFGHR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1011<<(((PIN)&7)<<2))) : \\\n ((PIN>=PB16)&&(PIN<=PB23) ? ( GPIOB->CFGXR = (GPIOB->CFGXR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1011<<(((PIN)&7)<<2))) : \\\n ((PIN>=PC0)&&(PIN<=PC7) ? ( GPIOC->CFGLR = (GPIOC->CFGLR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1011<<(((PIN)&7)<<2))) : \\\n ((PIN>=PC8)&&(PIN<=PC15) ? ( GPIOC->CFGHR = (GPIOC->CFGHR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1011<<(((PIN)&7)<<2))) : \\\n ((PIN>=PC16)&&(PIN<=PC23) ? ( GPIOC->CFGXR = (GPIOC->CFGXR \\\n & ~((uint32_t)0b1111<<(((PIN)&7)<<2))) \\\n | ((uint32_t)0b1011<<(((PIN)&7)<<2))) : \\\n(0))))))))))\n\n// ===================================================================================\n// Set PIN output value to LOW\n// ===================================================================================\n#define PIN_low(PIN) \\\n ((PIN>=PA0 )&&(PIN<=PA15) ? ( GPIOA->BCR = 1<<((PIN)&15) ) : \\\n ((PIN>=PB0 )&&(PIN<=PB15) ? ( GPIOB->BCR = 1<<((PIN)&15) ) : \\\n ((PIN>=PC0 )&&(PIN<=PC15) ? ( GPIOC->BCR = 1<<((PIN)&15) ) : \\\n ((PIN>=PA16)&&(PIN<=PA23) ? ( GPIOA->BSXR = ((1<<16)<<((PIN)&15)) ) : \\\n ((PIN>=PB16)&&(PIN<=PB23) ? ( GPIOB->BSXR = ((1<<16)<<((PIN)&15)) ) : \\\n ((PIN>=PC16)&&(PIN<=PC23) ? ( GPIOC->BSXR = ((1<<16)<<((PIN)&15)) ) : \\\n(0)))))))\n\n// ===================================================================================\n// Set PIN output value to HIGH\n// ===================================================================================\n#define PIN_high(PIN) \\\n ((PIN>=PA0 )&&(PIN<=PA15) ? ( GPIOA->BSHR = 1<<((PIN)&15) ) : \\\n ((PIN>=PA16)&&(PIN<=PA23) ? ( GPIOA->BSXR = 1<<((PIN)&15) ) : \\\n ((PIN>=PB0 )&&(PIN<=PB15) ? ( GPIOB->BSHR = 1<<((PIN)&15) ) : \\\n ((PIN>=PB16)&&(PIN<=PB23) ? ( GPIOB->BSXR = 1<<((PIN)&15) ) : \\\n ((PIN>=PC0 )&&(PIN<=PC15) ? ( GPIOC->BSHR = 1<<((PIN)&15) ) : \\\n ((PIN>=PC16)&&(PIN<=PC23) ? ( GPIOC->BSXR = 1<<((PIN)&15) ) : \\\n(0)))))))\n\n// ===================================================================================\n// Toggle PIN output value\n// ===================================================================================\n#define PIN_toggle(PIN) \\\n ((PIN>=PA0)&&(PIN<=PA23) ? ( GPIOA->OUTDR ^= 1<<((PIN)&31) ) : \\\n ((PIN>=PB0)&&(PIN<=PB23) ? ( GPIOB->OUTDR ^= 1<<((PIN)&31) ) : \\\n ((PIN>=PC0)&&(PIN<=PC23) ? ( GPIOC->OUTDR ^= 1<<((PIN)&31) ) : \\\n(0))))\n\n// ===================================================================================\n// Read PIN input value (returns 0 for LOW, 1 for HIGH)\n// ===================================================================================\n#define PIN_read(PIN) \\\n ((PIN>=PA0)&&(PIN<=PA23) ? ( (GPIOA->INDR>>((PIN)&31))&1 ) : \\\n ((PIN>=PB0)&&(PIN<=PB23) ? ( (GPIOB->INDR>>((PIN)&31))&1 ) : \\\n ((PIN>=PC0)&&(PIN<=PC23) ? ( (GPIOC->INDR>>((PIN)&31))&1 ) : \\\n(0))))\n\n// ===================================================================================\n// Write PIN output value (0 = LOW / 1 = HIGH)\n// ===================================================================================\n#define PIN_write(PIN, val) (val)?(PIN_high(PIN)):(PIN_low(PIN))\n\n// ===================================================================================\n// Setup PIN interrupt\n// ===================================================================================\nenum{PIN_INT_OFF, PIN_INT_RISING, PIN_INT_FALLING, PIN_INT_BOTH};\n\n#define EXTICR1 EXTICR[0]\n#define EXTICR2 EXTICR[1]\n\n#define PIN_INT_set(PIN, TYPE) { \\\n ((PIN>=PA0 )&&(PIN<=PA15) ? ({RCC->APB2PCENR |= RCC_AFIOEN | RCC_IOPAEN; \\\n AFIO->EXTICR1 &= ~((uint32_t)3<<(((PIN)&15)<<1)); }) : \\\n ((PIN>=PA16)&&(PIN<=PA23) ? ({RCC->APB2PCENR |= RCC_AFIOEN | RCC_IOPAEN; \\\n AFIO->EXTICR2 &= ~((uint32_t)3<<(((PIN)&15)<<1)); }) : \\\n ((PIN>=PB0 )&&(PIN<=PB15) ? ({RCC->APB2PCENR |= RCC_AFIOEN | RCC_IOPBEN; \\\n AFIO->EXTICR1 = (AFIO->EXTICR1 \\\n & ~((uint32_t)3<<(((PIN)&15)<<1))) \\\n | ((uint32_t)2<<(((PIN)&15)<<1)); }) : \\\n ((PIN>=PB16)&&(PIN<=PB23) ? ({RCC->APB2PCENR |= RCC_AFIOEN | RCC_IOPBEN; \\\n AFIO->EXTICR2 = (AFIO->EXTICR2 \\\n & ~((uint32_t)3<<(((PIN)&15)<<1))) \\\n | ((uint32_t)2<<(((PIN)&15)<<1)); }) : \\\n ((PIN>=PC0 )&&(PIN<=PC15) ? ({RCC->APB2PCENR |= RCC_AFIOEN | RCC_IOPCEN; \\\n AFIO->EXTICR1 |= ((uint32_t)3<<(((PIN)&15)<<1)); }) : \\\n ((PIN>=PC16)&&(PIN<=PC23) ? ({RCC->APB2PCENR |= RCC_AFIOEN | RCC_IOPCEN; \\\n AFIO->EXTICR2 |= ((uint32_t)3<<(((PIN)&15)<<1)); }) : \\\n (0))))))); \\\n (TYPE & 3) ? (EXTI->INTENR |= (uint32_t)1<<((PIN)&31)) : \\\n (EXTI->INTENR &= ~((uint32_t)1<<((PIN)&31))); \\\n (TYPE & 1) ? (EXTI->RTENR |= (uint32_t)1<<((PIN)&31)) : \\\n (EXTI->RTENR &= ~((uint32_t)1<<((PIN)&31))); \\\n (TYPE & 2) ? (EXTI->FTENR |= (uint32_t)1<<((PIN)&31)) : \\\n (EXTI->FTENR &= ~((uint32_t)1<<((PIN)&31))); \\\n}\n\n#define PIN_INT_enable() {NVIC_EnableIRQ(EXTI7_0_IRQn); \\\n NVIC_EnableIRQ(EXTI15_8_IRQn); \\\n NVIC_EnableIRQ(EXTI25_16_IRQn); }\n#define PIN_INT_disable() {NVIC_DisableIRQ(EXTI7_0_IRQn); \\\n NVIC_DisableIRQ(EXTI15_8_IRQn); \\\n NVIC_DisableIRQ(EXTI25_16_IRQn);}\n\n#define PIN_INTFLAG_read(PIN) (EXTI->INTFR & ((uint32_t)1 << ((PIN) & 31)))\n#define PIN_INTFLAG_clear(PIN) EXTI->INTFR = ((uint32_t)1 << ((PIN) & 31))\n\n#define PIN_INT_ISR \\\n void PIN_INT_IRQHandler(void) __attribute__((interrupt)); \\\n void EXTI7_0_IRQHandler(void) __attribute__((alias(\"PIN_INT_IRQHandler\"))); \\\n void EXTI15_8_IRQHandler(void) __attribute__((alias(\"PIN_INT_IRQHandler\"))); \\\n void EXTI25_16_IRQHandler(void) __attribute__((alias(\"PIN_INT_IRQHandler\"))); \\\n void PIN_INT_IRQHandler(void)\n\n// ===================================================================================\n// Setup PIN event\n// ===================================================================================\nenum{PIN_EVT_OFF, PIN_EVT_RISING, PIN_EVT_FALLING, PIN_EVT_BOTH};\n\n#define PIN_EVT_set(PIN, TYPE) { \\\n ((PIN>=PA0 )&&(PIN<=PA15) ? ({RCC->APB2PCENR |= RCC_AFIOEN | RCC_IOPAEN; \\\n AFIO->EXTICR1 &= ~((uint32_t)3<<(((PIN)&15)<<1)); }) : \\\n ((PIN>=PA16)&&(PIN<=PA23) ? ({RCC->APB2PCENR |= RCC_AFIOEN | RCC_IOPAEN; \\\n AFIO->EXTICR2 &= ~((uint32_t)3<<(((PIN)&15)<<1)); }) : \\\n ((PIN>=PB0 )&&(PIN<=PB15) ? ({RCC->APB2PCENR |= RCC_AFIOEN | RCC_IOPBEN; \\\n AFIO->EXTICR1 = (AFIO->EXTICR1 \\\n & ~((uint32_t)3<<(((PIN)&15)<<1))) \\\n | ((uint32_t)2<<(((PIN)&15)<<1)); }) : \\\n ((PIN>=PB16)&&(PIN<=PB23) ? ({RCC->APB2PCENR |= RCC_AFIOEN | RCC_IOPBEN; \\\n AFIO->EXTICR2 = (AFIO->EXTICR2 \\\n & ~((uint32_t)3<<(((PIN)&15)<<1))) \\\n | ((uint32_t)2<<(((PIN)&15)<<1)); }) : \\\n ((PIN>=PC0 )&&(PIN<=PC15) ? ({RCC->APB2PCENR |= RCC_AFIOEN | RCC_IOPCEN; \\\n AFIO->EXTICR1 |= ((uint32_t)3<<(((PIN)&15)<<1)); }) : \\\n ((PIN>=PC16)&&(PIN<=PC23) ? ({RCC->APB2PCENR |= RCC_AFIOEN | RCC_IOPCEN; \\\n AFIO->EXTICR2 |= ((uint32_t)3<<(((PIN)&15)<<1)); }) : \\\n (0))))))); \\\n (TYPE & 3) ? (EXTI->EVENR |= (uint32_t)1<<((PIN)&31)) : \\\n (EXTI->EVENR &= ~((uint32_t)1<<((PIN)&31))); \\\n (TYPE & 1) ? (EXTI->RTENR |= (uint32_t)1<<((PIN)&31)) : \\\n (EXTI->RTENR &= ~((uint32_t)1<<((PIN)&31))); \\\n (TYPE & 2) ? (EXTI->FTENR |= (uint32_t)1<<((PIN)&31)) : \\\n (EXTI->FTENR &= ~((uint32_t)1<<((PIN)&31))); \\\n}\n\n// ===================================================================================\n// Enable GPIO PORTS\n// ===================================================================================\n#define PORTA_enable() RCC->APB2PCENR |= RCC_IOPAEN;\n#define PORTB_enable() RCC->APB2PCENR |= RCC_IOPBEN;\n#define PORTC_enable() RCC->APB2PCENR |= RCC_IOPCEN;\n#define PORTS_enable() RCC->APB2PCENR |= RCC_IOPAEN | RCC_IOPBEN | RCC_IOPCEN\n\n#define PORT_enable(PIN) \\\n ((PIN>=PA0)&&(PIN<=PA15) ? ( RCC->APB2PCENR |= RCC_IOPAEN ) : \\\n ((PIN>=PB0)&&(PIN<=PB15) ? ( RCC->APB2PCENR |= RCC_IOPBEN ) : \\\n ((PIN>=PC0)&&(PIN<=PC15) ? ( RCC->APB2PCENR |= RCC_IOPCEN ) : \\\n(0))))\n\n// ===================================================================================\n// Disable GPIO PORTS\n// ===================================================================================\n#define PORTA_disable() RCC->APB2PCENR &= ~RCC_IOPAEN\n#define PORTB_disable() RCC->APB2PCENR &= ~RCC_IOPBEN\n#define PORTC_disable() RCC->APB2PCENR &= ~RCC_IOPCEN\n#define PORTS_disable() RCC->APB2PCENR &= ~(RCC_IOPAEN | RCC_IOPBEN | RCC_IOPCEN)\n\n#define PORT_disable(PIN) \\\n ((PIN>=PA0)&&(PIN<=PA15) ? ( RCC->APB2PCENR &= ~RCC_IOPAEN ) : \\\n ((PIN>=PB0)&&(PIN<=PB15) ? ( RCC->APB2PCENR &= ~RCC_IOPBEN ) : \\\n ((PIN>=PC0)&&(PIN<=PC15) ? ( RCC->APB2PCENR &= ~RCC_IOPCEN ) : \\\n(0))))\n\n// ===================================================================================\n// Analog-to-Digital Converter (ADC) Functions\n// ===================================================================================\n#define ADC_enable() ADC1->CTLR2 |= ADC_ADON\n#define ADC_disable() ADC1->CTLR2 &= ~ADC_ADON\n\n#define ADC_fast() { ADC1->CTLR3 = 0b00000000000000000000000000000101; \\\n ADC1->SAMPTR1 = 0b00000000000000000000000000000000; \\\n ADC1->SAMPTR2 = 0b00000000000000000000000000000000; }\n#define ADC_slow() { ADC1->CTLR3 = 0b00000000000000000000000000001011; \\\n ADC1->SAMPTR1 = 0b00111111111111111111111111111111; \\\n ADC1->SAMPTR2 = 0b00111111111111111111111111111111; }\n#define ADC_medium() { ADC1->CTLR3 = 0b00000000000000000000000000001000; \\\n ADC1->SAMPTR1 = 0b00011011011011011011011011011011; \\\n ADC1->SAMPTR2 = 0b00011011011011011011011011011011; }\n\n#define ADC_input_VREF() ADC1->RSQR3 = 15\n\n#define ADC_input(PIN) \\\n ((PIN>=PA0)&&(PIN<=PA7) ? (ADC1->RSQR3 = (PIN)&7) : \\\n ((PIN>=PB0)&&(PIN<=PB1) ? (ADC1->RSQR3 = ((PIN)&7)+8) : \\\n ((PIN>=PC0)&&(PIN<=PC3) ? (ADC1->RSQR3 = ((PIN)&7)+10) : \\\n(0))))\n\nstatic inline void ADC_init(void) {\n RCC->APB2PCENR |= RCC_ADC1EN | RCC_AFIOEN; // enable ADC and AFIO\n ADC_slow(); // set slow speed as default\n ADC1->CTLR2 = ADC_ADON // turn on ADC\n | ADC_EXTSEL; // software triggering\n}\n\nstatic inline uint16_t ADC_read(void) {\n ADC_enable(); // make sure ADC is enabled\n ADC1->CTLR2 |= ADC_SWSTART; // start conversion\n while(!(ADC1->STATR & ADC_EOC)); // wait until finished\n return ADC1->RDATAR; // return result\n}\n\nstatic inline uint16_t ADC_read_VDD(void) {\n ADC_input_VREF(); // set VREF as ADC input\n return((uint32_t)1200 * 4095 / ADC_read()); // return VDD in mV\n}\n\n// ===================================================================================\n// Analog Comparator (CMP) Functions\n// ===================================================================================\n#define CMP_lock() OPA->CTLR2 |= OPA_CTLR2_CMP_LOCK\n#define CMP_unlock() {CMP->KEY = CMP_KEY1; CMP->KEY = CMP_KEY2;}\n\n#define CMP1_enable() OPA->CTLR2 |= OPA_CTLR2_EN1\n#define CMP1_disable() OPA->CTLR2 &= ~OPA_CTLR2_EN1\n#define CMP1_HYS_enable() OPA->CTLR2 |= OPA_CTLR2_HYEN1\n#define CMP1_HYS_disable() OPA->CTLR2 &= ~OPA_CTLR2_HYEN1\n#define CMP1_OUT_PA1() OPA->CTLR2 |= OPA_CTLR2_MODE1\n#define CMP1_OUT_T2C1() OPA->CTLR2 &= ~OPA_CTLR2_MODE1\n#define CMP1_NEG_PA23() OPA->CTLR2 |= OPA_CTLR2_NSEL1\n#define CMP1_NEG_PC3() OPA->CTLR2 &= ~OPA_CTLR2_NSEL1\n#define CMP1_POS_PA0() OPA->CTLR2 |= OPA_CTLR2_PSEL1\n#define CMP1_POS_PC19() OPA->CTLR2 &= ~OPA_CTLR2_PSEL1\n\n#define CMP2_enable() OPA->CTLR2 |= OPA_CTLR2_EN2\n#define CMP2_disable() OPA->CTLR2 &= ~OPA_CTLR2_EN2\n#define CMP2_HYS_enable() OPA->CTLR2 |= OPA_CTLR2_HYEN2\n#define CMP2_HYS_disable() OPA->CTLR2 &= ~OPA_CTLR2_HYEN2\n#define CMP2_OUT_PB2() OPA->CTLR2 |= OPA_CTLR2_MODE2\n#define CMP2_OUT_T2C2() OPA->CTLR2 &= ~OPA_CTLR2_MODE2\n#define CMP2_NEG_PC3() OPA->CTLR2 |= OPA_CTLR2_NSEL2\n#define CMP2_NEG_PA22() OPA->CTLR2 &= ~OPA_CTLR2_NSEL2\n#define CMP2_POS_PA11() OPA->CTLR2 |= OPA_CTLR2_PSEL2\n#define CMP2_POS_PA12() OPA->CTLR2 &= ~OPA_CTLR2_PSEL2\n\n#define CMP3_enable() OPA->CTLR2 |= OPA_CTLR2_EN3\n#define CMP3_disable() OPA->CTLR2 &= ~OPA_CTLR2_EN3\n#define CMP3_HYS_enable() OPA->CTLR2 |= OPA_CTLR2_HYEN3\n#define CMP3_HYS_disable() OPA->CTLR2 &= ~OPA_CTLR2_HYEN3\n#define CMP3_OUT_PB3() OPA->CTLR2 |= OPA_CTLR2_MODE3\n#define CMP3_OUT_T2C3() OPA->CTLR2 &= ~OPA_CTLR2_MODE3\n#define CMP3_NEG_PC3() OPA->CTLR2 |= OPA_CTLR2_NSEL3\n#define CMP3_NEG_PA2() OPA->CTLR2 &= ~OPA_CTLR2_NSEL3\n#define CMP3_POS_PA14() OPA->CTLR2 |= OPA_CTLR2_PSEL3\n#define CMP3_POS_PA13() OPA->CTLR2 &= ~OPA_CTLR2_PSEL3\n\n// ===================================================================================\n// Operational Amplifier (OPA) Functions\n// ===================================================================================\n// not yet implemented\n\n// ===================================================================================\n// Touch Key (TK) Functions\n// ===================================================================================\n#define TK_input(PIN) ADC_input(PIN)\n\nstatic inline void TK_init(void) {\n ADC_init(); // init ADC\n ADC1->CTLR1 |= ADC_TKENABLE; // enable touch key\n ADC1->IDATAR1 = 0x80; // TKEY1->CHGOFFSET = 0x80;\n}\n\nstatic inline uint8_t TK_read(void) {\n uint8_t result;\n uint16_t value;\n ADC_enable(); // (re-)enable ADC\n ADC1->RDATAR = 0x08; // (TKEY1->ACT_DCG) set discharge time and start\n while(!(ADC1->STATR & ADC_EOC)); // wait until sampling completed\n value = ADC1->RDATAR; // read sampling value\n result = (value == 2047); // 2047 if pressed\n ADC1->RDATAR = 0x08; // second sampling (blind)\n while(!(ADC1->STATR & ADC_EOC));\n value = ADC1->RDATAR;\n return result;\n}\n\n#ifdef __cplusplus\n};\n#endif\n" }, { "path": "software/pd_tester/src/i2c_soft.c", "content": "// ===================================================================================\n// Software I2C Master Functions for CH32X035/X034/X033 * v1.1 *\n// ===================================================================================\n//\n// Simple I2C bitbanging. ACK bit of the slave is ignored. Clock stretching by the \n// slave is not allowed. External pull-up resistors (4k7 - 10k) are mandatory!\n//\n// Further information: https://github.com/wagiminator/ATtiny13-TinyOLEDdemo\n// 2023 by Stefan Wagner: https://github.com/wagiminator\n\n#include \"i2c_soft.h\"\n\n// ===================================================================================\n// I2C Delay\n// ===================================================================================\n#define I2C_DLY_TICKS_H (((F_CPU * 9) / (I2C_CLKRATE * 25)) - 41)\n#define I2C_DLY_TICKS_L (((F_CPU * 16) / (I2C_CLKRATE * 25)) - 76)\n\n#if I2C_DLY_TICKS_H >= 1\n #define I2C_DELAY_H() DLY_ticks(I2C_DLY_TICKS_H)\n#else\n #define I2C_DELAY_H()\n#endif\n\n#if I2C_DLY_TICKS_L >= 1\n #define I2C_DELAY_L() DLY_ticks(I2C_DLY_TICKS_L)\n#else\n #define I2C_DELAY_L()\n#endif\n\n// ===================================================================================\n// I2C Pin Macros\n// ===================================================================================\n#define I2C_SDA_HIGH() PIN_input(PIN_SDA) // release SDA -> pulled HIGH by resistor\n#define I2C_SDA_LOW() PIN_output(PIN_SDA) // SDA LOW -> pulled LOW by MCU\n#define I2C_SCL_HIGH() PIN_input(PIN_SCL) // release SCL -> pulled HIGH by resistor\n#define I2C_SCL_LOW() PIN_output(PIN_SCL) // SCL LOW -> pulled LOW by MCU\n#define I2C_SDA_READ() PIN_read(PIN_SDA) // read SDA pin\n#define I2C_CLOCKOUT() I2C_DELAY_L();I2C_SCL_HIGH();I2C_DELAY_H();I2C_SCL_LOW()\n\n// ===================================================================================\n// I2C Functions\n// ===================================================================================\n\n// I2C init function\nvoid I2C_init(void) {\n PIN_input(PIN_SCL); // release SCL\n PIN_input(PIN_SDA); // release SDA\n PIN_low(PIN_SCL); // preset for SCL low\n PIN_low(PIN_SDA); // preset for SDA low\n}\n\n// I2C transmit one data byte to the slave, ignore ACK bit, no clock stretching allowed\nvoid I2C_write(uint8_t data) {\n uint8_t i;\n for(i=8; i; i--, data<<=1) { // transmit 8 bits, MSB first\n (data & 0x80) ? (I2C_SDA_HIGH()) : (I2C_SDA_LOW()); // SDA HIGH if bit is 1\n I2C_CLOCKOUT(); // clock out -> slave reads the bit\n }\n I2C_SDA_HIGH(); // release SDA for ACK bit of slave\n I2C_CLOCKOUT(); // 9th clock pulse is for the ignored ACK bit\n}\n\n// I2C start transmission\nvoid I2C_start(uint8_t addr) {\n I2C_SDA_LOW(); // start condition: SDA goes LOW first\n I2C_DELAY_H(); // delay\n I2C_SCL_LOW(); // start condition: SCL goes LOW second\n I2C_write(addr); // send slave address\n}\n\n// I2C restart transmission\nvoid I2C_restart(uint8_t addr) {\n I2C_SDA_HIGH(); // prepare SDA for HIGH to LOW transition\n I2C_DELAY_H(); // delay\n I2C_SCL_HIGH(); // restart condition: clock HIGH\n I2C_start(addr); // start again\n}\n\n// I2C stop transmission\nvoid I2C_stop(void) {\n I2C_SDA_LOW(); // prepare SDA for LOW to HIGH transition\n I2C_DELAY_H(); // delay\n I2C_SCL_HIGH(); // stop condition: SCL goes HIGH first\n I2C_DELAY_H(); // delay\n I2C_SDA_HIGH(); // stop condition: SDA goes HIGH second\n}\n\n// I2C receive one data byte from the slave (ack=0 for last byte, ack>0 if more bytes to follow)\nuint8_t I2C_read(uint8_t ack) {\n uint8_t i;\n uint8_t data = 0; // variable for the received byte\n I2C_SDA_HIGH(); // release SDA -> will be toggled by slave\n for(i=8; i; i--) { // receive 8 bits\n data <<= 1; // bits shifted in right (MSB first)\n I2C_DELAY_L(); // delay\n I2C_SCL_HIGH(); // clock HIGH\n I2C_DELAY_H(); // delay\n if(I2C_SDA_READ()) data |= 1; // read bit\n I2C_SCL_LOW(); // clock LOW -> slave prepares next bit\n }\n if(ack) I2C_SDA_LOW(); // pull SDA LOW to acknowledge (ACK)\n I2C_CLOCKOUT(); // clock out -> slave reads ACK bit\n return data; // return the received byte\n}\n\n// Send data buffer via I2C bus and stop\nvoid I2C_writeBuffer(uint8_t* buf, uint16_t len) {\n while(len--) I2C_write(*buf++); // write buffer\n I2C_stop(); // stop transmission\n}\n\n// Read data via I2C bus to buffer and stop\nvoid I2C_readBuffer(uint8_t* buf, uint16_t len) {\n while(len--) *buf++ = I2C_read(len > 0);\n I2C_stop();\n}\n" }, { "path": "software/pd_tester/src/i2c_soft.h", "content": "// ===================================================================================\n// Software I2C Master Functions for CH32X035/X034/X033 * v1.1 *\n// ===================================================================================\n//\n// Simple I2C bitbanging. ACK bit of the slave is ignored. Clock stretching by the \n// slave is not allowed. External pull-up resistors (4k7 - 10k) are mandatory!\n//\n// Functions available:\n// --------------------\n// I2C_init() I2C init function\n// I2C_start(addr) I2C start transmission, address must contain R/W bit\n// I2C_restart(addr) I2C restart transmission, address must contain R/W bit\n// I2C_stop() I2C stop transmission\n// I2C_write(data) I2C transmit one data byte to the slave\n// I2C_read(ack) I2C receive one data byte (set ack=0 for last byte)\n//\n// I2C_writeBuffer(buf,len) Send buffer (*buf) with length (len) via I2C and stop\n// I2C_readBuffer(buf,len) Read buffer (*buf) with length (len) via I2C and stop\n//\n// Define SDA/SCL pin and clock rate below!\n//\n// Further information: https://github.com/wagiminator/ATtiny13-TinyOLEDdemo\n// 2023 by Stefan Wagner: https://github.com/wagiminator\n\n#pragma once\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"config.h\"\n#include \"system.h\"\n#include \"gpio.h\"\n\n// I2C parameters\n#ifndef PIN_SDA\n#define PIN_SDA PA11 // pin connected to serial data of the I2C bus\n#define PIN_SCL PA10 // pin connected to serial clock of the I2C bus\n#endif\n#define I2C_CLKRATE 400000 // I2C bus clock rate in Hz\n\n// I2C Functions\nvoid I2C_init(void); // I2C init function\nvoid I2C_start(uint8_t addr); // I2C start transmission\nvoid I2C_restart(uint8_t addr); // I2C restart transmission\nvoid I2C_stop(void); // I2C stop transmission\nvoid I2C_write(uint8_t data); // I2C transmit one data byte to the slave\nuint8_t I2C_read(uint8_t ack); // I2C receive one data byte from the slave\n\nvoid I2C_writeBuffer(uint8_t* buf, uint16_t len);\nvoid I2C_readBuffer(uint8_t* buf, uint16_t len);\n\n#ifdef __cplusplus\n};\n#endif\n" }, { "path": "software/pd_tester/src/main.c", "content": "// ===================================================================================\n// Project: USB PD Tester for CH32X035\n// Version: v1.3\n// Year: 2024\n// Author: Stefan Wagner\n// Github: https://github.com/wagiminator\n// EasyEDA: https://easyeda.com/wagiminator\n// License: http://creativecommons.org/licenses/by-sa/3.0/\n// ===================================================================================\n//\n// Description:\n// ------------\n// The USB PD Tester allows users to retrieve and test the capabilities of a connected\n// USB Power Delivery Adapter.\n//\n// References:\n// -----------\n// - WCH Nanjing Qinheng Microelectronics: http://wch.cn\n//\n// Compilation Instructions:\n// -------------------------\n// - Make sure GCC toolchain (gcc-riscv64-unknown-elf, newlib) and Python3 with chprog\n// are installed. In addition, Linux requires access rights to the USB bootloader.\n// - Press the BOOT button on the MCU board and keep it pressed while connecting it\n// via USB to your PC.\n// - Run 'make flash'.\n\n\n// ===================================================================================\n// Libraries, Definitions and Macros\n// ===================================================================================\n#include // user configurations\n#include // OLED text functions\n#include // USB PD sink functions\n\n// Global variables\nuint8_t select = 1; // selected PDO\nuint8_t active = 1; // active PDO\nuint16_t voltage = 5000; // selected voltage\n\n// ===================================================================================\n// Functions\n// ===================================================================================\n\n// Set selected PDO marker\nvoid setSelect(uint8_t pdo) {\n OLED_cursor(120, select - 1); OLED_write(' ');\n if(pdo > PD_getPDONum()) select = 1;\n else if(pdo < 1) select = PD_getPDONum();\n else select = pdo;\n OLED_cursor(120, select - 1); OLED_write('<');\n}\n\n// Set active PDO marker\nvoid setActive(uint8_t pdo) {\n OLED_cursor( 0, active - 1); OLED_write(' ');\n active = pdo;\n OLED_cursor( 0, active - 1); OLED_write('*');\n}\n\n// Set selected voltage\nvoid setVoltage(uint16_t v) {\n if (v <= PD_getPDOMinVoltage(select)) voltage = PD_getPDOMinVoltage(select);\n else if(v >= PD_getPDOMaxVoltage(select)) voltage = PD_getPDOMaxVoltage(select);\n else voltage = v;\n OLED_cursor(30, 6); OLED_printf(\">%6dmV <\", voltage);\n}\n\n// Print source capabilities\nvoid printSourceCap(void) {\n uint8_t i;\n OLED_clear();\n for(i = 1; i <= PD_getPDONum(); i++) {\n if(i <= PD_getFixedNum())\n OLED_printf(\" (%d)%6dmV %5dmA \", i, PD_getPDOVoltage(i), PD_getPDOMaxCurrent(i));\n else\n OLED_printf(\" [%d]%6dmV-%5dmV \", i, PD_getPDOMinVoltage(i), PD_getPDOMaxVoltage(i));\n }\n setSelect(select);\n setActive(active);\n}\n\n// Print selected programmable power PDO infos\nvoid printPPS(void) {\n OLED_clear();\n OLED_printf(\"Select voltage of [%d]\\n\", select);\n OLED_printf(\"min voltage:%7dmV\", PD_getPDOMinVoltage(select));\n OLED_printf(\"max voltage:%7dmV\", PD_getPDOMaxVoltage(select));\n OLED_printf(\"max current:%7dmA\", PD_getPDOMaxCurrent(select));\n setVoltage(voltage);\n}\n\n// ===================================================================================\n// Main Function\n// ===================================================================================\nint main(void) {\n // Variables\n uint8_t i;\n uint8_t keydelay;\n\n // Setup OLED and USB-PD\n #if DISABLE_SWJ\n RCC->APB2PCENR |= RCC_AFIOEN; // enable AFIO clock\n AFIO->PCFR1 |= AFIO_PCFR1_SWJ_CFG_2; // disable SWJ on pins PC18 and PC19\n #endif\n OLED_init();\n OLED_clear();\n OLED_printf(\"Connecting...\");\n if(!PD_connect()) {\n OLED_printf(\"FAILED\");\n while(1);\n }\n\n // Print source capabilities\n printSourceCap();\n\n // Setup button pins\n PIN_input_PU(PIN_KEY_UP);\n PIN_input_PU(PIN_KEY_DOWN);\n PIN_input_PU(PIN_KEY_SLCT);\n \n // Loop\n while(1) {\n\n if(!PIN_read(PIN_KEY_UP)) {\n setSelect(select - 1);\n while(!PIN_read(PIN_KEY_UP));\n }\n\n if(!PIN_read(PIN_KEY_DOWN)) {\n setSelect(select + 1);\n while(!PIN_read(PIN_KEY_DOWN));\n }\n\n if(!PIN_read(PIN_KEY_SLCT)) {\n if(select <= PD_getFixedNum()) {\n if(PD_setPDO(select, PD_getPDOVoltage(select)))\n setActive(select);\n }\n else {\n printPPS();\n while(!PIN_read(PIN_KEY_SLCT));\n DLY_ms(10);\n while(PIN_read(PIN_KEY_SLCT)) {\n\n if(!PIN_read(PIN_KEY_UP)) {\n setVoltage(voltage + 20);\n i = keydelay;\n while((i--) && (!PIN_read(PIN_KEY_UP))) DLY_ms(10);\n keydelay = 2;\n }\n\n else if(!PIN_read(PIN_KEY_DOWN)) {\n setVoltage(voltage - 20);\n i = keydelay;\n while((i--) && (!PIN_read(PIN_KEY_DOWN))) DLY_ms(10);\n keydelay = 2;\n }\n\n else keydelay = 50;\n\n PD_negotiate();\n }\n\n if(PD_setPDO(select, voltage))\n active = select;\n printSourceCap();\n }\n while(!PIN_read(PIN_KEY_SLCT));\n }\n\n PD_negotiate();\n DLY_ms(10);\n }\n}\n" }, { "path": "software/pd_tester/src/print.c", "content": "// ===================================================================================\n// Basic PRINT Functions * v1.1 *\n// ===================================================================================\n// 2023 by Stefan Wagner: https://github.com/wagiminator\n\n#include \n#include \"print.h\"\n\n// Print decimal value\nvoid printD(void (*putchar) (char c), uint32_t value) {\n uint8_t digitval; // current digit value\n uint8_t leadflag = 0; // flag for leading spaces\n uint32_t divider = 1000000000; // current divider\n while(divider) { // for all digits\n digitval = value / divider; // calculate digit value\n value = value % divider; // set value to division remainder\n divider /= 10; // calculate next divider\n if(digitval) leadflag++; // end of leading spaces\n if(!divider) leadflag++; // least digit has to be printed\n if(leadflag) putchar(digitval + '0'); // print the digit\n }\n}\n\n// Convert 4-bit byte nibble into hex character and print it via putchar\nvoid printN(void (*putchar) (char c), uint8_t nibble) {\n putchar((nibble <= 9) ? ('0' + nibble) : ('A' - 10 + nibble));\n}\n\n// Convert 8-bit byte into hex characters and print it via putchar\nvoid printB(void (*putchar) (char c), uint8_t value) {\n printN(putchar, value >> 4);\n printN(putchar, value & 0x0f);\n}\n\n// Convert 16-bit half-word into hex characters and print it via putchar\nvoid printH(void (*putchar) (char c), uint16_t value) {\n printB(putchar, value >> 8);\n printB(putchar, value);\n}\n\n// Convert 32-bit word into hex characters and print it via putchar\nvoid printW(void (*putchar) (char c), uint32_t value) {\n printH(putchar, value >> 16);\n printH(putchar, value);\n}\n\n// Print string via putchar\nvoid printS(void (*putchar) (char c), const char* str) {\n while(*str) putchar(*str++);\n}\n\n// Print string with newline via putchar\nvoid println(void (*putchar) (char c), const char* str) {\n while(*str) putchar(*str++);\n putchar('\\n');\n}\n\n// printf, supports %s, %c, %d, %u, %x, %b, %02d, %%\nvoid _itoa(void (*putchar) (char c), int32_t, int8_t, int8_t);\nstatic void _vfprintf(void (*putchar) (char c), const char *format, va_list arg);\n\nvoid printF(void (*putchar) (char c), const char *format, ...) {\n va_list arg;\n va_start(arg, format);\n _vfprintf(putchar, format, arg);\n va_end(arg);\n}\n\nstatic void _vfprintf(void (*putchar) (char c), const char* str, va_list arp) {\n int32_t d, r, w, s;\n char *c;\n\n while((d = *str++) != 0) {\n if(d != '%') {\n putchar(d);\n continue;\n }\n d = *str++;\n w = r = s = 0;\n if(d == '%') {\n putchar(d);\n d = *str++;\n }\n if(d == '0') {\n d = *str++;\n s = 1;\n }\n while((d >= '0') && (d <= '9')) {\n w += w * 10 + (d - '0');\n d = *str++;\n }\n if(s) w = -w;\n if(d == 's') {\n c = va_arg(arp, char*);\n while(*c) putchar(*(c++));\n continue;\n }\n if(d == 'c') {\n putchar((char)va_arg(arp, int));\n continue;\n }\n if(d =='\\0') break;\n else if(d == 'u') r = 10;\n else if(d == 'd') r = -10;\n else if(d == 'x') r = 16;\n else if(d == 'b') r = 2;\n else str--;\n if(r == 0) continue;\n if(r > 0) _itoa(putchar, (uint32_t)va_arg(arp, int32_t), r, w);\n else _itoa(putchar, (int32_t)va_arg(arp, int32_t), r, w);\n }\n}\n\nvoid _itoa(void (*putchar) (char c), int32_t val, int8_t rad, int8_t len) {\n char c, sgn = 0, pad = ' ';\n char s[20];\n uint8_t i = 0;\n\n if(rad < 0) {\n rad = -rad;\n if(val < 0) {\n val = -val;\n sgn = '-';\n }\n }\n if(len < 0) {\n len = -len;\n pad = '0';\n }\n if(len > 20) return;\n do {\n c = (char)((uint32_t)val % rad);\n if (c >= 10) c += ('A' - 10);\n else c += '0';\n s[i++] = c;\n val = (uint32_t)val / rad;\n } while(val);\n if((sgn != 0) && (pad != '0')) s[i++] = sgn;\n while(i < len) s[i++] = pad;\n if((sgn != 0) && (pad == '0')) s[i++] = sgn;\n do putchar(s[--i]);\n while(i);\n}\n" }, { "path": "software/pd_tester/src/print.h", "content": "// ===================================================================================\n// Basic PRINT Functions * v1.1 *\n// ===================================================================================\n//\n// Functions available:\n// --------------------\n// printF(putchar, f, ...) Uses printf (supports %s, %c, %d, %u, %x, %b, %02d, %%)\n// printD(putchar, n) Print decimal value as string via putchar function\n// printW(putchar, n) Print 32-bit hex word value as string via putchar function\n// printH(putchar, n) Print 16-bit hex half-word value as string via putchar function\n// printB(putchar, n) Print 8-bit hex byte value as string via putchar function\n// printS(putchar, s) Print string via putchar function\n// println(putchar, s) Print string with newline via putchar function\n//\n// 2023 by Stefan Wagner: https://github.com/wagiminator\n\n#pragma once\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n\nvoid printD(void (*putchar) (char c), uint32_t value);\nvoid printB(void (*putchar) (char c), uint8_t value);\nvoid printH(void (*putchar) (char c), uint16_t value);\nvoid printW(void (*putchar) (char c), uint32_t value);\nvoid printS(void (*putchar) (char c), const char* str);\nvoid println(void (*putchar) (char c), const char* str);\nvoid printF(void (*putchar) (char c), const char *format, ...);\n\n#ifdef __cplusplus\n};\n#endif\n" }, { "path": "software/pd_tester/src/ssd1306_txt.c", "content": "// ===================================================================================\n// SSD1306/SH1106/SH1107 I2C OLED Text Functions * v1.3 *\n// ===================================================================================\n//\n// Collection of the most necessary functions for controlling an SSD1306/SH1106 I2C \n// OLED for the display of simple text.\n//\n// References:\n// -----------\n// - Neven Boyanov: https://github.com/tinusaur/ssd1306xled\n// - Stephen Denne: https://github.com/datacute/Tiny4kOLED\n// - David Johnson-Davies: http://www.technoblogy.com/show?TV4\n// - TinyOLEDdemo: https://github.com/wagiminator/attiny13-tinyoleddemo\n// - TinyTerminal: https://github.com/wagiminator/ATtiny85-TinyTerminal\n// - OLED Font Editor: http://sourpuss.net/projects/fontedit/\n//\n// 2022 by Stefan Wagner: https://github.com/wagiminator\n\n#include \"ssd1306_txt.h\"\n\n// ===================================================================================\n// Standard ASCII 5x8 Font (chars 32 - 127)\n// ===================================================================================\nconst uint8_t OLED_FONT[] = {\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5F, 0x00, 0x00, 0x00, 0x07, 0x00, 0x07, 0x00,\n 0x14, 0x7F, 0x14, 0x7F, 0x14, 0x24, 0x2A, 0x7F, 0x2A, 0x12, 0x23, 0x13, 0x08, 0x64, 0x62,\n 0x36, 0x49, 0x55, 0x22, 0x50, 0x00, 0x04, 0x03, 0x00, 0x00, 0x00, 0x1C, 0x22, 0x41, 0x00,\n 0x00, 0x41, 0x22, 0x1C, 0x00, 0x14, 0x08, 0x3E, 0x08, 0x14, 0x08, 0x08, 0x3E, 0x08, 0x08,\n 0x00, 0x80, 0x60, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x60, 0x60, 0x00, 0x00,\n 0x20, 0x10, 0x08, 0x04, 0x02, 0x3E, 0x51, 0x49, 0x45, 0x3E, 0x44, 0x42, 0x7F, 0x40, 0x40,\n 0x42, 0x61, 0x51, 0x49, 0x46, 0x22, 0x41, 0x49, 0x49, 0x36, 0x18, 0x14, 0x12, 0x7F, 0x10,\n 0x2F, 0x49, 0x49, 0x49, 0x31, 0x3E, 0x49, 0x49, 0x49, 0x32, 0x03, 0x01, 0x71, 0x09, 0x07,\n 0x36, 0x49, 0x49, 0x49, 0x36, 0x26, 0x49, 0x49, 0x49, 0x3E, 0x00, 0x36, 0x36, 0x00, 0x00,\n 0x00, 0x80, 0x68, 0x00, 0x00, 0x00, 0x08, 0x14, 0x22, 0x00, 0x14, 0x14, 0x14, 0x14, 0x14,\n 0x00, 0x22, 0x14, 0x08, 0x00, 0x02, 0x01, 0x51, 0x09, 0x06, 0x3E, 0x41, 0x5D, 0x55, 0x5E,\n 0x7C, 0x12, 0x11, 0x12, 0x7C, 0x7F, 0x49, 0x49, 0x49, 0x36, 0x3E, 0x41, 0x41, 0x41, 0x22,\n 0x7F, 0x41, 0x41, 0x22, 0x1C, 0x7F, 0x49, 0x49, 0x49, 0x41, 0x7F, 0x09, 0x09, 0x09, 0x01,\n 0x3E, 0x41, 0x49, 0x49, 0x3A, 0x7F, 0x08, 0x08, 0x08, 0x7F, 0x41, 0x41, 0x7F, 0x41, 0x41,\n 0x20, 0x40, 0x41, 0x3F, 0x01, 0x7F, 0x08, 0x14, 0x22, 0x41, 0x7F, 0x40, 0x40, 0x40, 0x40,\n 0x7F, 0x02, 0x0C, 0x02, 0x7F, 0x7F, 0x04, 0x08, 0x10, 0x7F, 0x3E, 0x41, 0x41, 0x41, 0x3E,\n 0x7F, 0x09, 0x09, 0x09, 0x06, 0x3E, 0x41, 0x41, 0xC1, 0xBE, 0x7F, 0x09, 0x19, 0x29, 0x46,\n 0x26, 0x49, 0x49, 0x49, 0x32, 0x01, 0x01, 0x7F, 0x01, 0x01, 0x3F, 0x40, 0x40, 0x40, 0x3F,\n 0x1F, 0x20, 0x40, 0x20, 0x1F, 0x3F, 0x40, 0x38, 0x40, 0x3F, 0x63, 0x14, 0x08, 0x14, 0x63,\n 0x07, 0x08, 0x70, 0x08, 0x07, 0x61, 0x51, 0x49, 0x45, 0x43, 0x00, 0x7F, 0x41, 0x41, 0x00,\n 0x02, 0x04, 0x08, 0x10, 0x20, 0x00, 0x41, 0x41, 0x7F, 0x00, 0x08, 0x04, 0x02, 0x04, 0x08,\n 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x06, 0x09, 0x09, 0x06, 0x20, 0x54, 0x54, 0x54, 0x78,\n 0x7F, 0x44, 0x44, 0x44, 0x38, 0x38, 0x44, 0x44, 0x44, 0x28, 0x38, 0x44, 0x44, 0x44, 0x7F,\n 0x38, 0x54, 0x54, 0x54, 0x18, 0x08, 0xFE, 0x09, 0x01, 0x02, 0x18, 0xA4, 0xA4, 0xA4, 0x78,\n 0x7F, 0x04, 0x04, 0x04, 0x78, 0x00, 0x44, 0x7D, 0x40, 0x00, 0x00, 0x80, 0x84, 0x7D, 0x00,\n 0x41, 0x7F, 0x10, 0x28, 0x44, 0x00, 0x41, 0x7F, 0x40, 0x00, 0x7C, 0x04, 0x7C, 0x04, 0x78,\n 0x7C, 0x04, 0x04, 0x04, 0x78, 0x38, 0x44, 0x44, 0x44, 0x38, 0xFC, 0x24, 0x24, 0x24, 0x18,\n 0x18, 0x24, 0x24, 0x24, 0xFC, 0x7C, 0x08, 0x04, 0x04, 0x08, 0x08, 0x54, 0x54, 0x54, 0x20,\n 0x04, 0x3F, 0x44, 0x40, 0x20, 0x3C, 0x40, 0x40, 0x40, 0x3C, 0x1C, 0x20, 0x40, 0x20, 0x1C,\n 0x3C, 0x40, 0x30, 0x40, 0x3C, 0x44, 0x28, 0x10, 0x28, 0x44, 0x1C, 0xA0, 0xA0, 0xA0, 0x7C,\n 0x44, 0x64, 0x54, 0x4C, 0x44, 0x08, 0x08, 0x36, 0x41, 0x41, 0x00, 0x00, 0xFF, 0x00, 0x00,\n 0x41, 0x41, 0x36, 0x08, 0x08, 0x08, 0x04, 0x08, 0x10, 0x08, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF\n};\n\n// ===================================================================================\n// 13x32 7-Segment Font (0 - 9)\n// ===================================================================================\n#if OLED_SEG_FONT == 1\nconst uint8_t OLED_FONT_SEG[] = {\n 0xFC, 0xF9, 0xF3, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0xF3, 0xF9, 0xFC, // 0\n 0x7F, 0x3F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x3F, 0x7F, \n 0xFF, 0xFE, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFE, 0xFF, \n 0x1F, 0x4F, 0x67, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x67, 0x4F, 0x1F, \n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xF8, 0xFC, // 1\n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x3F, 0x7F, \n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFE, 0xFF, \n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0F, 0x1F, \n 0x00, 0x01, 0x03, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0xF3, 0xF9, 0xFC, // 2\n 0x00, 0x00, 0x80, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0x9F, 0x3F, 0x7F, \n 0xFF, 0xFE, 0xFC, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, \n 0x1F, 0x4F, 0x67, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x60, 0x40, 0x00, \n 0x00, 0x01, 0x03, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0xF3, 0xF9, 0xFC, // 3\n 0x00, 0x00, 0x80, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0x9F, 0x3F, 0x7F, \n 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xFC, 0xFE, 0xFF, \n 0x00, 0x40, 0x60, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x67, 0x4F, 0x1F, \n 0xFC, 0xF8, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xF8, 0xFC, // 4\n 0x7F, 0x3F, 0x9F, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0x9F, 0x3F, 0x7F, \n 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xFC, 0xFE, 0xFF, \n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0F, 0x1F, \n 0xFC, 0xF9, 0xF3, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x03, 0x01, 0x00, // 5\n 0x7F, 0x3F, 0x9F, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0x80, 0x00, 0x00, \n 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xFC, 0xFE, 0xFF, \n 0x00, 0x40, 0x60, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x67, 0x4F, 0x1F, \n 0xFC, 0xF9, 0xF3, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x03, 0x01, 0x00, // 6\n 0x7F, 0x3F, 0x9F, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0x80, 0x00, 0x00, \n 0xFF, 0xFE, 0xFC, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xFC, 0xFE, 0xFF, \n 0x1F, 0x4F, 0x67, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x67, 0x4F, 0x1F, \n 0xFC, 0xF9, 0xF3, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0xF3, 0xF9, 0xFC, // 7\n 0x7F, 0x3F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x3F, 0x7F, \n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFE, 0xFF, \n 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0F, 0x1F, \n 0xFC, 0xF9, 0xF3, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0xF3, 0xF9, 0xFC, // 8\n 0x7F, 0x3F, 0x9F, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0x9F, 0x3F, 0x7F, \n 0xFF, 0xFE, 0xFC, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xFC, 0xFE, 0xFF, \n 0x1F, 0x4F, 0x67, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x67, 0x4F, 0x1F, \n 0xFC, 0xF9, 0xF3, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0xF3, 0xF9, 0xFC, // 9\n 0x7F, 0x3F, 0x9F, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0x9F, 0x3F, 0x7F, \n 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xFC, 0xFE, 0xFF, \n 0x00, 0x40, 0x60, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x70, 0x67, 0x4F, 0x1F\n};\n\nconst uint8_t OLED_FONT_POINT[] = {\n 0x00, 0x00, 0x00,\n 0x00, 0x00, 0x00,\n 0x00, 0x00, 0x00,\n 0x70, 0x70, 0x70\n};\n#endif\n\n// ===================================================================================\n// 5x16 7-Segment Font (0 - 9)\n// ===================================================================================\n#if OLED_SEG_FONT == 2\nconst uint8_t OLED_FONT_SEG[] = {\n 0x7C, 0x02, 0x02, 0x02, 0x7C, 0x1F, 0x20, 0x20, 0x20, 0x1F, // 0\n 0x00, 0x00, 0x00, 0x00, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x1F, // 1\n 0x00, 0x82, 0x82, 0x82, 0x7C, 0x1F, 0x20, 0x20, 0x20, 0x00, // 2\n 0x00, 0x82, 0x82, 0x82, 0x7C, 0x00, 0x20, 0x20, 0x20, 0x1F, // 3\n 0x7C, 0x80, 0x80, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x1F, // 4\n 0x7C, 0x82, 0x82, 0x82, 0x00, 0x00, 0x20, 0x20, 0x20, 0x1F, // 5\n 0x7C, 0x82, 0x82, 0x82, 0x00, 0x1F, 0x20, 0x20, 0x20, 0x1F, // 6\n 0x7C, 0x02, 0x02, 0x02, 0x7C, 0x00, 0x00, 0x00, 0x00, 0x1F, // 7\n 0x7C, 0x82, 0x82, 0x82, 0x7C, 0x1F, 0x20, 0x20, 0x20, 0x1F, // 8\n 0x7C, 0x82, 0x82, 0x82, 0x7C, 0x00, 0x20, 0x20, 0x20, 0x1F // 9\n};\n\nconst uint8_t OLED_FONT_POINT[] = {\n 0x00, 0x00,\n 0x30, 0x30\n};\n#endif\n\n// ===================================================================================\n// OLED Control Functions\n// ===================================================================================\n\n// Screen offsets\n#if OLED_SH1106 == 1\n #define OLED_XOFF ((128 - OLED_WIDTH) / 2) + 2\n#else\n #define OLED_XOFF ((128 - OLED_WIDTH) / 2)\n#endif\n\n// OLED initialisation sequence\nconst uint8_t OLED_INIT_CMD[] = {\n OLED_MULTIPLEX, OLED_HEIGHT - 1, // set multiplex ratio\n OLED_CHARGEPUMP, 0x14, // set DC-DC enable \n OLED_MEMORYMODE, 0x00, // set horizontal addressing mode\n #if OLED_WIDTH == 128 && OLED_HEIGHT == 32\n OLED_COMPINS, 0x02, // set com pins\n #else\n OLED_COMPINS, 0x12, // set com pins\n #endif\n #if OLED_XFLIP > 0\n OLED_XFLIP_ON, // flip screen in X-direction\n #endif\n #if OLED_YFLIP > 0\n OLED_YFLIP_ON, // flip screen in Y-direction\n #endif\n #if OLED_INVERT > 0\n OLED_INVERT_ON, // invert screen\n #endif\n OLED_DISPLAY_ON // display on\n};\n\n// OLED init function\nvoid OLED_init(void) {\n #if OLED_INIT_I2C > 0\n I2C_init(); // initialize I2C first\n #endif\n #if OLED_BOOT_TIME > 0\n DLY_ms(OLED_BOOT_TIME); // time for the OLED to boot up\n #endif\n I2C_start(OLED_ADDR << 1); // start transmission to OLED\n I2C_write(OLED_CMD_MODE); // set command mode\n I2C_writeBuffer((uint8_t*)OLED_INIT_CMD, sizeof(OLED_INIT_CMD)); // send the command bytes\n}\n\n// Switch display on/off (0: display off, 1: display on)\nvoid OLED_display(uint8_t val) {\n I2C_start(OLED_ADDR << 1); // start transmission to OLED\n I2C_write(OLED_CMD_MODE); // set command mode\n I2C_write(val ? OLED_DISPLAY_ON : OLED_DISPLAY_OFF); // set display power\n I2C_stop(); // stop transmission\n}\n\n// Set display contrast (0-255)\nvoid OLED_contrast(uint8_t val) {\n I2C_start(OLED_ADDR << 1); // start transmission to OLED\n I2C_write(OLED_CMD_MODE); // set command mode\n I2C_write(OLED_CONTRAST); // contrast command\n I2C_write(val); // set contrast value\n I2C_stop(); // stop transmission\n}\n\n// Invert display (0: inverse off, 1: inverse on)\nvoid OLED_invert(uint8_t val) {\n I2C_start(OLED_ADDR << 1); // start transmission to OLED\n I2C_write(OLED_CMD_MODE); // set command mode\n I2C_write(val ? OLED_INVERT_ON : OLED_INVERT_OFF); // set invert mode\n I2C_stop(); // stop transmission\n}\n\n// Flip display (0: flip off, 1: flip on)\nvoid OLED_flip(uint8_t xflip, uint8_t yflip) {\n I2C_start(OLED_ADDR << 1); // start transmission to OLED\n I2C_write(OLED_CMD_MODE); // set command mode\n I2C_write(xflip ? OLED_XFLIP_ON : OLED_XFLIP_OFF); // set x-flip\n I2C_write(yflip ? OLED_YFLIP_ON : OLED_YFLIP_OFF); // set y-flip\n I2C_stop(); // stop transmission\n}\n\n// Scroll display vertically\nvoid OLED_vscroll(uint8_t y) {\n I2C_start(OLED_ADDR << 1); // start transmission to OLED\n I2C_write(OLED_CMD_MODE); // set command mode\n I2C_write(OLED_OFFSET); // offset command\n I2C_write(y); // set y-scroll\n I2C_stop(); // stop transmission\n}\n\n// ===================================================================================\n// OLED Text Functions\n// ===================================================================================\n\n// OLED global variables\nuint8_t OLED_x, OLED_y, OLED_i;\n\n// OLED clear line\nvoid OLED_clearLine(uint8_t y) {\n uint8_t i;\n OLED_cursor(0, y); // set cursor to line start\n I2C_start(OLED_ADDR << 1); // start transmission to OLED\n I2C_write(OLED_DAT_MODE); // set data mode\n for(i=OLED_WIDTH; i; i--) I2C_write(0x00); // clear line\n I2C_stop(); // stop transmission\n OLED_cursor(0, y); // re-set cursor to line start\n}\n\n// OLED clear screen\nvoid OLED_clear(void) {\n uint8_t y = OLED_HEIGHT / 8;\n while(y--) OLED_clearLine(y); // clear all lines\n}\n\n// OLED set cursor to specified position\nvoid OLED_cursor(uint8_t x, uint8_t y) {\n if(y >= OLED_HEIGHT / 8) y = 0; // limit y\n OLED_x = x; OLED_y = y; // set cursor variables\n x += OLED_XOFF; // add offset\n I2C_start(OLED_ADDR << 1); // start transmission to OLED\n I2C_write(OLED_CMD_MODE); // set command mode\n I2C_write(OLED_PAGE + y); // set line\n I2C_write(x & 0xf); // set column\n I2C_write((x >> 4) | 0x10);\n I2C_stop(); // stop transmission\n}\n\n// OLED set text invert\nvoid OLED_textinvert(uint8_t yes) {\n OLED_i = yes;\n}\n\n#if OLED_BIGCHARS > 0\n\n// Character buffer\nuint8_t OLED_buf[2*10];\nuint8_t OLED_sz;\n\n// Converts bit pattern abcdefgh into aabbccddeeffgghh\nuint16_t OLED_stretch(uint16_t x) {\n x = (x & 0xF0)<<4 | (x & 0x0F);\n x = (x<<2 | x) & 0x3333;\n x = (x<<1 | x) & 0x5555;\n return x | x<<1;\n}\n\n// Set character size\nvoid OLED_textsize(uint8_t size) {\n OLED_sz = size;\n}\n\n#endif // OLED_BIGCHARS > 0\n\n// OLED plot a single character\nvoid OLED_plotChar(char c) {\n uint16_t ptr = c - 32; // character pointer\n ptr += ptr << 2; // -> ptr = (ch - 32) * 5;\n #if OLED_BIGCHARS > 0\n if(OLED_sz == 0) { // normal character (5x8)\n #endif\n if(OLED_x > OLED_WIDTH - 6) OLED_cursor(0, OLED_y + 1);\n I2C_start(OLED_ADDR << 1); // start transmission to OLED\n I2C_write(OLED_DAT_MODE); // set data mode\n I2C_write(OLED_i ? 0xff : 0x00); // write space between characters\n for(uint8_t i=5; i; i--) I2C_write(OLED_i ? ~OLED_FONT[ptr++] : OLED_FONT[ptr++]);\n I2C_stop();\n OLED_x += 6; // move cursor\n #if OLED_BIGCHARS > 0\n }\n else if(OLED_sz == 1) { // v-stretched character (5x16)\n if(OLED_x > OLED_WIDTH - 6) OLED_cursor(0, OLED_y + 2);\n for(uint8_t i=0; i<5; i++) {\n uint16_t ch = OLED_stretch(OLED_FONT[ptr++]);\n OLED_buf[i] = ch; OLED_buf[i+5] = ch >> 8;\n }\n OLED_drawBitmap(OLED_buf, 5, 2);\n OLED_clearRect(1, 2);\n }\n else { // double-sized smoothed character (10x16)\n uint16_t col0L, col0R, col1L, col1R; // David Johnson-Davies' Smooth Big Text algorithm\n uint8_t col0 = OLED_FONT[ptr++];\n if(OLED_x > OLED_WIDTH - 12) OLED_cursor(0, OLED_y + 2);\n col0L = OLED_stretch(col0);\n col0R = col0L;\n for(uint8_t col=0; col<10; col+=2) {\n uint8_t col1 = OLED_FONT[ptr++];\n if(col == 8) col1 = 0;\n col1L = OLED_stretch(col1);\n col1R = col1L; \n for(int8_t i=6; i>=0; i--) {\n for(int8_t j=1; j<3; j++) {\n if(((col0>>i & 0b11) == (3 - j)) && ((col1>>i & 0b11) == j)) {\n col0R = col0R | 1<<((i << 1) + j);\n col1L = col1L | 1<<((i << 1) + 3 - j);\n }\n }\n }\n OLED_buf[col] = col0L; OLED_buf[col + 1] = col0R;\n OLED_buf[col + 10] = col0L >> 8; OLED_buf[col + 11] = col0R >> 8;\n col0 = col1; col0L = col1L; col0R = col1R;\n }\n OLED_drawBitmap(OLED_buf, 10, 2);\n OLED_clearRect(2, 2);\n }\n #endif\n}\n\n// OLED write a character or handle control characters\nvoid OLED_write(char c) {\n c &= 0x7f; // ignore top bit\n if(c >= 32) OLED_plotChar(c); // normal character\n #if OLED_BIGCHARS > 0\n else if(c == '\\n') OLED_cursor(0, OLED_y + (OLED_sz ? 2 : 1));\n #else\n else if(c == '\\n') OLED_cursor(0, OLED_y + 1); // new line\n #endif\n else if(c == '\\r') OLED_cursor(0, OLED_y); // carriage return\n}\n\n// OLED print a string\nvoid OLED_print(char* str) {\n while(*str) OLED_write(*str++);\n}\n\n// ===================================================================================\n// OLED Bitmap Functions\n// ===================================================================================\n\n// Draw bitmap (pointer *bmp) at cursor position width (w) in pixels, hight (h) in 8-pixel lines\nvoid OLED_drawBitmap(const uint8_t* bmp, uint8_t w, uint8_t h) {\n uint8_t y = OLED_y;\n while(h--) {\n I2C_start(OLED_ADDR << 1); // start transmission to OLED\n I2C_write(OLED_DAT_MODE); // set data mode\n for(uint8_t i=w; i; i--) I2C_write(OLED_i ? ~(*bmp++) : *bmp++);\n I2C_stop();\n OLED_cursor(OLED_x, OLED_y + 1); // set next line\n }\n OLED_cursor(OLED_x + w, y); // move cursor\n}\n\n// ===================================================================================\n// OLED 7-Segment Functions\n// ===================================================================================\n\n// Clear a rectangle starting from cursor position\nvoid OLED_clearRect(uint8_t w, uint8_t h) {\n uint8_t y = OLED_y;\n while(h--) {\n I2C_start(OLED_ADDR << 1); // start transmission to OLED\n I2C_write(OLED_DAT_MODE); // set data mode\n for(uint8_t i=w; i; i--) I2C_write(OLED_i ? 0xff : 0x00); // clear line\n I2C_stop(); // stop transmission\n OLED_cursor(OLED_x, OLED_y + 1); // set next line\n }\n OLED_cursor(OLED_x + w, y); // move cursor\n}\n\n// Print value as 7-segment digits (BCD conversion by substraction method)\nvoid OLED_printSegment(uint16_t value, uint8_t digits, uint8_t lead, uint8_t decimal) {\n static const uint16_t DIVIDER[] = {1, 10, 100, 1000, 10000};\n uint8_t leadflag = 0; // flag for leading spaces\n while(digits--) { // for all digits digits\n uint8_t digitval = 0; // start with digit value 0\n uint16_t divider = DIVIDER[digits]; // read current divider\n while(value >= divider) { // if current divider fits into the value\n leadflag = 1; // end of leading spaces\n digitval++; // increase digit value\n value -= divider; // decrease value by divider\n }\n if(digits == decimal) leadflag++; // end leading characters before decimal\n if(leadflag || !lead) {\n #if OLED_SEG_FONT == 0\n OLED_write(digitval + '0');\n #elif OLED_SEG_FONT == 1\n uint16_t ptr = (uint16_t)digitval; // character pointer\n ptr = (ptr << 5) + (ptr << 4) + (ptr << 2); // -> ptr = c * 13 * 4;\n OLED_drawBitmap((uint8_t*)&OLED_FONT_SEG[ptr], 13, 4);\n #elif OLED_SEG_FONT == 2\n uint16_t ptr = (uint16_t)digitval; // character pointer\n ptr = (ptr << 3) + (ptr << 1); // -> ptr = c * 5 * 2;\n OLED_drawBitmap((uint8_t*)&OLED_FONT_SEG[ptr], 5, 2);\n #endif\n }\n else {\n #if OLED_SEG_FONT == 0\n OLED_write(' ');\n #elif OLED_SEG_FONT == 1\n OLED_clearRect(13, 4);\n #elif OLED_SEG_FONT == 2\n OLED_clearRect( 5, 2);\n #endif\n }\n #if OLED_SEG_FONT == 1\n OLED_clearRect(OLED_SEG_SPACE, 4);\n #elif OLED_SEG_FONT == 2\n OLED_clearRect(OLED_SEG_SPACE, 2);\n #endif\n if(decimal && (digits == decimal)) {\n #if OLED_SEG_FONT == 0\n OLED_write('.');\n #elif OLED_SEG_FONT == 1\n OLED_drawBitmap(OLED_FONT_POINT, 3, 4);\n OLED_clearRect(OLED_SEG_SPACE, 4);\n #elif OLED_SEG_FONT == 2\n OLED_drawBitmap(OLED_FONT_POINT, 2, 2);\n OLED_clearRect(OLED_SEG_SPACE, 2);\n #endif\n }\n }\n}\n" }, { "path": "software/pd_tester/src/ssd1306_txt.h", "content": "// ===================================================================================\n// SSD1306/SH1106/SH1107 I2C OLED Text Functions * v1.3 *\n// ===================================================================================\n//\n// Collection of the most necessary functions for controlling an SSD1306/SH1106 I2C \n// OLED for the display of simple text, working without a screen buffer.\n//\n// Functions available:\n// --------------------\n// OLED_init() Init OLED display\n// OLED_display(v) Switch display on/off (0: display off, 1: display on)\n// OLED_contrast(v) Set OLED contrast (0-255)\n// OLED_invert(v) Invert display (0: inverse off, 1: inverse on)\n// OLED_flip(xflip,yflip) Flip display (0: flip off, 1: flip on)\n// OLED_vscroll(y) Scroll display vertically (0-64)\n// OLED_clear() Clear screen of OLED display\n// OLED_clearLine(y) Clear line y\n//\n// OLED_cursor(x,y) Set text cursor at position (x,y)\n// OLED_textsize(sz) Set text size (0: 5x8, 1: 5x16, 2: 10x16), enable OLED_BIGCHARS\n// OLED_textinvert(v) Invert text (0: inverse off, 1: inverse on)\n// OLED_write(c) Write character at cursor position or handle control characters\n// OLED_print(str) Print string (*str) at cursor position\n// OLED_printSegment(v,d,l,dp) Print value (v) at cursor position using defined segment font\n// with (d) number of digits, (l) leading (0: '0', 1: space) and \n// decimal point at position (dp) counted from the right\n// OLED_drawBitmap(bmp,w,h) Draw bitmap (pointer *bmp) at cursor position \n// width (w) in pixels, hight (h) in 8-pixel lines\n//\n// If print functions are activated (see below, print.h must be included):\n// -----------------------------------------------------------------------\n// OLED_printf(f, ...) printf (supports %s, %c, %d, %u, %x, %b, %02d, %%)\n// OLED_printD(n) Print decimal value\n// OLED_printW(n) Print 32-bit hex word value\n// OLED_printH(n) Print 16-bit hex half-word value\n// OLED_printB(n) Print 8-bit hex byte value\n// OLED_printS(s) Print string\n// OLED_println(s) Print string with newline\n// OLED_newline() Send newline\n//\n// Tested devices:\n// ---------------\n// - 1.5\" 128x128 SH1107\n// - 1.3\" 128x64 SH1106\n// - 0.96\" 128x64 SSD1306\n// - 0.91\" 128x32 SSD1306\n// - 0.49\" 64x32 SSD1306\n// - 0.42\" 72x40 SSD1306\n//\n// References:\n// -----------\n// - Neven Boyanov: https://github.com/tinusaur/ssd1306xled\n// - Stephen Denne: https://github.com/datacute/Tiny4kOLED\n// - David Johnson-Davies: http://www.technoblogy.com/show?TV4\n// - TinyOLEDdemo: https://github.com/wagiminator/attiny13-tinyoleddemo\n// - TinyTerminal: https://github.com/wagiminator/ATtiny85-TinyTerminal\n// - OLED Font Editor: http://sourpuss.net/projects/fontedit/\n//\n// 2022 by Stefan Wagner: https://github.com/wagiminator\n\n#pragma once\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"i2c_soft.h\" // choose your I2C library\n#include \"system.h\"\n\n// OLED Parameters\n#define OLED_ADDR 0x3C // OLED I2C device address\n#define OLED_WIDTH 128 // OLED width in pixels\n#define OLED_HEIGHT 64 // OLED height in pixels\n#define OLED_SH1106 0 // OLED driver - 0: SSD1306/SH1107, 1: SH1106\n\n#define OLED_BOOT_TIME 50 // OLED boot up time in milliseconds\n#define OLED_INIT_I2C 1 // 1: init I2C with OLED_init()\n#define OLED_XFLIP 1 // 1: flip screen in X-direction with OLED_init()\n#define OLED_YFLIP 1 // 1: flip screen in Y-direction with OLED_init()\n#define OLED_INVERT 0 // 1: invert screen with OLED_init()\n\n// OLED Text Settings\n#define OLED_PRINT 1 // 1: include print functions (needs print.h)\n#define OLED_BIGCHARS 0 // 1: use big fonts (OLED_textsize())\n#define OLED_SEG_FONT 0 // 0: standard font, 1: 13x32 digits, 2: 5x16 digits\n#define OLED_SEG_SPACE 3 // width of space between segment digits in pixels\n\n// OLED Modes\n#define OLED_CMD_MODE 0x00 // set command mode\n#define OLED_DAT_MODE 0x40 // set data mode\n#define OLED_CMD_ONCE 0x80 // send one command byte\n#define OLED_DAT_ONCE 0xC0 // send one data byte\n\n// OLED Commands\n#define OLED_COLUMN_LOW 0x00 // set lower 4 bits of start column (0x00 - 0x0F)\n#define OLED_COLUMN_HIGH 0x10 // set higher 4 bits of start column (0x10 - 0x1F)\n#define OLED_MEMORYMODE 0x20 // set memory addressing mode (following byte)\n#define OLED_COLUMNS 0x21 // set start and end column (following 2 bytes)\n#define OLED_PAGES 0x22 // set start and end page (following 2 bytes)\n#define OLED_STARTLINE 0x40 // set display start line (0x40-0x7F = 0-63)\n#define OLED_CONTRAST 0x81 // set display contrast (following byte, 0-255)\n#define OLED_CHARGEPUMP 0x8D // (following byte - 0x14:enable, 0x10: disable)\n#define OLED_XFLIP_OFF 0xA0 // don't flip display horizontally\n#define OLED_XFLIP_ON 0xA1 // flip display horizontally\n#define OLED_RESUME 0xA4 // display all on resume\n#define OLED_ALL_ON 0xA5 // display all on\n#define OLED_INVERT_OFF 0xA6 // set non-inverted display\n#define OLED_INVERT_ON 0xA7 // set inverse display\n#define OLED_MULTIPLEX 0xA8 // set multiplex ratio (following byte)\n#define OLED_DISPLAY_OFF 0xAE // set display off (sleep mode)\n#define OLED_DISPLAY_ON 0xAF // set display on\n#define OLED_PAGE 0xB0 // set start page (0xB0-0xB7 = 0-7)\n#define OLED_YFLIP_OFF 0xC0 // don't flip display vertically\n#define OLED_YFLIP_ON 0xC8 // flip display vertically\n#define OLED_OFFSET 0xD3 // set display offset (y-scroll: following byte)\n#define OLED_CLOCK 0xD5 // set frequency (bits 7-4) and divider (bits 3-0)\n#define OLED_PRECHARGE 0xD9 // set pre-charge period (following byte)\n#define OLED_COMPINS 0xDA // set COM pin config (following byte)\n#define OLED_VCOM_DETECT 0xDB // set VCOM detect (following byte)\n\n// OLED Control Functions\nvoid OLED_init(void); // OLED init function\nvoid OLED_display(uint8_t val); // Switch display on/off (0: display off, 1: display on)\nvoid OLED_contrast(uint8_t val); // Set display contrast (0-255)\nvoid OLED_invert(uint8_t val); // Invert display (0: inverse off, 1: inverse on)\nvoid OLED_flip(uint8_t xflip, uint8_t yflip); // Flip display (0: flip off, 1: flip on)\nvoid OLED_vscroll(uint8_t y); // Scroll display vertically (0-64)\n\n// OLED Text Functions\nvoid OLED_clear(void); // Clear screen\nvoid OLED_clearLine(uint8_t y); // Clear line y\nvoid OLED_write(char c); // Write a character or handle control characters\nvoid OLED_print(char* str); // Print a string\nvoid OLED_cursor(uint8_t x, uint8_t y); // Set cursor\nvoid OLED_textinvert(uint8_t yes); // Invert text\n\n#if OLED_BIGCHARS > 0\nvoid OLED_textsize(uint8_t size); // Set text size (0: 5x8, 1: 5x16, 2: 10x16)\n#endif\n\n// OLED Special Functions\nvoid OLED_drawBitmap(const uint8_t* bmp, uint8_t w, uint8_t h);\nvoid OLED_clearRect(uint8_t w, uint8_t h);\nvoid OLED_printSegment(uint16_t value, uint8_t digits, uint8_t lead, uint8_t decimal);\n\n#define OLED_textcolor(c) OLED_textinvert(!(c))\n\n// OLED Cursor Position\nextern uint8_t OLED_x, OLED_y;\n\n// Additional print functions (if activated, see above)\n#if OLED_PRINT == 1\n#include \"print.h\"\n#define OLED_printD(n) printD(OLED_write, n) // print decimal as string\n#define OLED_printW(n) printW(OLED_write, n) // print word as string\n#define OLED_printH(n) printH(OLED_write, n) // print half-word as string\n#define OLED_printB(n) printB(OLED_write, n) // print byte as string\n#define OLED_printS(s) printS(OLED_write, s) // print string\n#define OLED_println(s) println(OLED_write, s) // print string with newline\n#define OLED_newline() OLED_write('\\n') // send newline\n#define OLED_printf(f, ...) printF(OLED_write, f, ##__VA_ARGS__)\n#endif\n\n#ifdef __cplusplus\n};\n#endif\n" }, { "path": "software/pd_tester/src/system.c", "content": "// ===================================================================================\n// Basic System Functions for CH32X035/X034/X033 * v1.1 *\n// ===================================================================================\n//\n// This file must be included!!!!\n//\n// References:\n// -----------\n// - WCH Nanjing Qinheng Microelectronics: http://wch.cn\n//\n// 2023 by Stefan Wagner: https://github.com/wagiminator\n\n#include \"system.h\"\n\n// ===================================================================================\n// Setup Microcontroller (this function is called automatically at startup)\n// ===================================================================================\nvoid SYS_init(void) {\n\n // Init system clock\n #if SYS_CLK_INIT > 0\n #if F_CPU <= 12000000\n //FLASH->ACTLR = FLASH_ACTLR_LATENCY_0;\n #elif F_CPU <= 24000000\n FLASH->ACTLR = FLASH_ACTLR_LATENCY_1;\n #else\n FLASH->ACTLR = FLASH_ACTLR_LATENCY_2;\n #endif\n RCC->CFGR0 = SYS_CLK_DIV;\n #endif\n\n // Init SYSTICK\n #if SYS_TICK_INIT > 0\n STK_init();\n #endif\n\n // Enable GPIO\n #if SYS_GPIO_EN > 0\n RCC->APB2PCENR = RCC_IOPAEN | RCC_IOPBEN | RCC_IOPCEN;\n #endif\n}\n\n// ===================================================================================\n// System Clock Functions\n// ===================================================================================\n\n// Reset system clock to default state\nvoid CLK_reset(void) {\n RCC->CTLR |= (uint32_t)0x00000001;\n RCC->CFGR0 = (uint32_t)0x00000050;\n FLASH->ACTLR = (uint32_t)0x00000000;\n}\n\n// Setup pin PB9 for MCO (output, push-pull, alternate)\nvoid MCO_init(void) {\n RCC->APB2PCENR |= RCC_AFIOEN | RCC_IOPBEN;\n GPIOB->CFGHR = (GPIOB->CFGHR & ~((uint32_t)0b1111<<(1<<2))) | ((uint32_t)0b1011<<(1<<2));\n RCC->CFGR0 |= RCC_CFGR0_MCO_SYSCLK;\n}\n\n// ===================================================================================\n// Delay Functions\n// ===================================================================================\n\n// Wait n counts of SysTick\nvoid DLY_ticks(uint32_t n) {\n uint32_t end = STK->CNTL + n;\n while(((int32_t)(STK->CNTL - end)) < 0);\n}\n\n// ===================================================================================\n// Bootloader (BOOT) Functions\n// ===================================================================================\n\n// Perform software reset and jump to bootloader\nvoid BOOT_now(void) {\n FLASH->KEYR = FLASH_KEY1;\n FLASH->KEYR = FLASH_KEY2;\n FLASH->BOOT_MODEKEYR = FLASH_KEY1;\n FLASH->BOOT_MODEKEYR = FLASH_KEY2; // unlock flash\n FLASH->STATR |= FLASH_STATR_BOOT_MODE; // start bootloader after software reset\n FLASH->CTLR |= FLASH_CTLR_LOCK; // lock flash\n RCC->RSTSCKR |= RCC_RMVF; // clear reset flags\n NVIC->CFGR = NVIC_RESETSYS | NVIC_KEY3; // perform software reset\n}\n\n// ===================================================================================\n// Independent Watchdog Timer (IWDG) Functions\n// ===================================================================================\n\n// Start independent watchdog timer (IWDG) with given amount of WDG clock cycles\n// (ticks). The IWDG clock is HSI/1024/prescaler. One tick is 64*1024*1000/48000000 ms\n// long, max ticks is 4095 = 5591ms.\n// Once the IWDG has been started, it cannot be disabled, only reloaded (feed).\nvoid IWDG_start_t(uint16_t ticks) {\n IWDG->CTLR = 0x5555; // allow register modification\n while(IWDG->STATR & IWDG_PVU); // wait for clock register to be ready\n IWDG->PSCR = 0b100; // set clock prescaler 64\n while(IWDG->STATR & IWDG_RVU); // wait for reload register to be ready\n IWDG->RLDR = ticks; // set watchdog counter reload value\n IWDG->CTLR = 0xAAAA; // load reload value into watchdog counter\n IWDG->CTLR = 0xCCCC; // enable IWDG\n}\n\n// Reload watchdog counter with n ticks, n<=4095\nvoid IWDG_reload_t(uint16_t ticks) {\n IWDG->CTLR = 0x5555; // allow register modification\n while(IWDG->STATR & IWDG_RVU); // wait for reload register to be ready\n IWDG->RLDR = ticks; // set watchdog counter reload value\n IWDG->CTLR = 0xAAAA; // load reload value into watchdog counter\n}\n\n// ===================================================================================\n// Automatic Wake-up Timer (AWU) Functions\n// ===================================================================================\n\n// Init and start automatic wake-up timer\nvoid AWU_init(void) {\n AWU->CSR = 0x02; // enable automatic wake-up timer\n EXTI->EVENR |= ((uint32_t)1<<27); // enable AWU event\n EXTI->RTENR |= ((uint32_t)1<<27); // enable AWU rising edge triggering\n}\n\n// Stop automatic wake-up timer\nvoid AWU_stop(void) {\n AWU->CSR = 0x00; // disable automatic wake-up timer\n EXTI->EVENR &= ~((uint32_t)1<<27); // disable AWU event\n EXTI->RTENR &= ~((uint32_t)1<<27); // disable AWU rising edge triggering\n}\n\n// ===================================================================================\n// Sleep Functions\n// ===================================================================================\n\n// Put device into sleep, wake up by interrupt\nvoid SLEEP_WFI_now(void) {\n PFIC->SCTLR &= ~PFIC_SLEEPDEEP; // set power-down mode to SLEEP\n __WFI(); // wait for interrupt\n}\n\n// Put device into sleep, wake up by event\nvoid SLEEP_WFE_now(void) {\n PFIC->SCTLR &= ~PFIC_SLEEPDEEP; // set power-down mode to SLEEP\n __WFE(); // wait for event\n}\n\n// Put device into stop, wake up interrupt\nvoid STOP_WFI_now(void) {\n PFIC->SCTLR |= PFIC_SLEEPDEEP; // set power-down mode to STOP\n __WFI(); // wait for interrupt\n}\n\n// Put device into stop, wake up event\nvoid STOP_WFE_now(void) {\n PFIC->SCTLR |= PFIC_SLEEPDEEP; // set power-down mode to STOP\n __WFE(); // wait for event\n}\n\n// Put device into standby (deep sleep), wake up interrupt\nvoid STDBY_WFI_now(void) {\n RCC->APB1PCENR |= RCC_PWREN; // enable power module\n PWR->CTLR |= PWR_CTLR_PDDS; // set power-down mode to STANDBY\n PFIC->SCTLR |= PFIC_SLEEPDEEP;\n __WFI(); // wait for interrupt\n PWR->CTLR &= ~PWR_CTLR_PDDS; // reset power-down mode\n}\n\n// Put device into standby (deep sleep), wake up event\nvoid STDBY_WFE_now(void) {\n RCC->APB1PCENR |= RCC_PWREN; // enable power module\n PWR->CTLR |= PWR_CTLR_PDDS; // set power-down mode to STANDBY\n PFIC->SCTLR |= PFIC_SLEEPDEEP;\n __WFE(); // wait for event\n PWR->CTLR &= ~PWR_CTLR_PDDS; // reset power-down mode\n}\n\n// ===================================================================================\n// C++ Support\n// ===================================================================================\n#ifdef __cplusplus\nextern void __cxa_pure_virtual() { while (1); }\nextern void (*__preinit_array_start[]) (void) __attribute__((weak));\nextern void (*__preinit_array_end[]) (void) __attribute__((weak));\nextern void (*__init_array_start[]) (void) __attribute__((weak));\nextern void (*__init_array_end[]) (void) __attribute__((weak));\n\nvoid __libc_init_array(void) {\n uint32_t count, i;\n count = __preinit_array_end - __preinit_array_start;\n for (i = 0; i < count; i++) __preinit_array_start[i]();\n count = __init_array_end - __init_array_start;\n for (i = 0; i < count; i++) __init_array_start[i]();\n}\n#endif\n\n// ===================================================================================\n// C version of CH32X035 Startup .s file from WCH\n// ===================================================================================\nextern uint32_t _sbss;\nextern uint32_t _ebss;\nextern uint32_t _data_lma;\nextern uint32_t _data_vma;\nextern uint32_t _edata;\n\n// Prototypes\nint main(void) __attribute__((section(\".text.main\"), used));\nvoid jump_reset(void) __attribute__((section(\".init.jump\"), naked, used));\nvoid (*const vectors[])(void) __attribute__((section(\".vector\"), used));\nvoid reset_handler(void) __attribute__((section(\".text.reset_handler\"), naked, used));\n\n#if SYS_USE_VECTORS > 0\n// Unless a specific handler is overridden, it just spins forever\nvoid default_handler(void) __attribute__((section(\".text.vector_handler\"), naked, used));\nvoid default_handler(void) { while(1); }\n\n// All interrupt handlers are aliased to default_handler unless overridden individually\n#define DUMMY_HANDLER __attribute__((section(\".text.vector_handler\"), weak, alias(\"default_handler\"), used))\nDUMMY_HANDLER void NMI_Handler(void);\nDUMMY_HANDLER void HardFault_Handler(void);\nDUMMY_HANDLER void Ecall_M_Mode_Handler(void);\nDUMMY_HANDLER void Ecall_U_Mode_Handler(void);\nDUMMY_HANDLER void Break_Point_Handler(void);\nDUMMY_HANDLER void SysTick_Handler(void);\nDUMMY_HANDLER void SW_Handler(void);\nDUMMY_HANDLER void WWDG_IRQHandler(void);\nDUMMY_HANDLER void PVD_IRQHandler(void);\nDUMMY_HANDLER void FLASH_IRQHandler(void);\nDUMMY_HANDLER void EXTI7_0_IRQHandler(void);\nDUMMY_HANDLER void AWU_IRQHandler(void);\nDUMMY_HANDLER void DMA1_Channel1_IRQHandler(void);\nDUMMY_HANDLER void DMA1_Channel2_IRQHandler(void);\nDUMMY_HANDLER void DMA1_Channel3_IRQHandler(void);\nDUMMY_HANDLER void DMA1_Channel4_IRQHandler(void);\nDUMMY_HANDLER void DMA1_Channel5_IRQHandler(void);\nDUMMY_HANDLER void DMA1_Channel6_IRQHandler(void);\nDUMMY_HANDLER void DMA1_Channel7_IRQHandler(void);\nDUMMY_HANDLER void ADC1_IRQHandler(void);\nDUMMY_HANDLER void I2C1_EV_IRQHandler(void);\nDUMMY_HANDLER void I2C1_ER_IRQHandler(void);\nDUMMY_HANDLER void USART1_IRQHandler(void);\nDUMMY_HANDLER void SPI1_IRQHandler(void);\nDUMMY_HANDLER void TIM1_BRK_IRQHandler(void);\nDUMMY_HANDLER void TIM1_UP_IRQHandler(void);\nDUMMY_HANDLER void TIM1_TRG_COM_IRQHandler(void);\nDUMMY_HANDLER void TIM1_CC_IRQHandler(void);\nDUMMY_HANDLER void TIM2_UP_IRQHandler(void);\nDUMMY_HANDLER void USART2_IRQHandler(void);\nDUMMY_HANDLER void EXTI15_8_IRQHandler(void);\nDUMMY_HANDLER void EXTI25_16_IRQHandler(void);\nDUMMY_HANDLER void USART3_IRQHandler(void);\nDUMMY_HANDLER void USART4_IRQHandler(void);\nDUMMY_HANDLER void DMA1_Channel8_IRQHandler(void);\nDUMMY_HANDLER void USBFS_IRQHandler(void);\nDUMMY_HANDLER void USBFSWakeUp_IRQHandler(void);\nDUMMY_HANDLER void PIOC_IRQHandler(void);\nDUMMY_HANDLER void OPA_IRQHandler(void);\nDUMMY_HANDLER void USBPD_IRQHandler(void);\nDUMMY_HANDLER void USBPDWakeUp_IRQHandler(void);\nDUMMY_HANDLER void TIM2_CC_IRQHandler(void);\nDUMMY_HANDLER void TIM2_TRG_COM_IRQHandler(void);\nDUMMY_HANDLER void TIM2_BRK_IRQHandler(void);\nDUMMY_HANDLER void TIM3_IRQHandler(void);\n#endif // SYS_USE_VECTORS > 0\n\n// FLASH starts with a jump to the reset handler\nvoid jump_reset(void) { asm volatile(\"j reset_handler\"); }\n\n// Interrupt vector table\nvoid (* const vectors[])(void) = {\n // RISC-V handlers\n jump_reset, // 0 - Reset\n #if SYS_USE_VECTORS > 0\n 0, // 1 - Reserved\n NMI_Handler, // 2 - NMI Handler\n HardFault_Handler, // 3 - Hard Fault Handler\n 0, // 4 - Reserved\n Ecall_M_Mode_Handler, // 5 - Ecall M Mode Handler\n 0, // 6 - Reserved\n 0, // 7 - Reserved\n Ecall_U_Mode_Handler, // 8 - Ecall U Mode Handler\n Break_Point_Handler, // 9 - Break Point Handler\n 0, // 10 - Reserved\n 0, // 11 - Reserved\n SysTick_Handler, // 12 - SysTick Handler\n 0, // 13 - Reserved\n SW_Handler, // 14 - SW Handler\n 0, // 15 - Reserved\n \n // Peripheral handlers\n WWDG_IRQHandler, // 16 - Window Watchdog\n PVD_IRQHandler, // 17 - PVD through EXTI Line detect\n FLASH_IRQHandler, // 18 - Flash\n 0, // 19 - Reserved\n EXTI7_0_IRQHandler, // 20 - EXTI Line 7..0\n AWU_IRQHandler, // 21 - Auto Wake-up\n DMA1_Channel1_IRQHandler, // 22 - DMA1 Channel 1\n DMA1_Channel2_IRQHandler, // 23 - DMA1 Channel 2\n DMA1_Channel3_IRQHandler, // 24 - DMA1 Channel 3\n DMA1_Channel4_IRQHandler, // 25 - DMA1 Channel 4\n DMA1_Channel5_IRQHandler, // 26 - DMA1 Channel 5\n DMA1_Channel6_IRQHandler, // 27 - DMA1 Channel 6\n DMA1_Channel7_IRQHandler, // 28 - DMA1 Channel 7\n ADC1_IRQHandler, // 29 - ADC1\n I2C1_EV_IRQHandler, // 30 - I2C1 Event\n I2C1_ER_IRQHandler, // 31 - I2C1 Error\n USART1_IRQHandler, // 32 - USART1\n SPI1_IRQHandler, // 33 - SPI1\n TIM1_BRK_IRQHandler, // 34 - TIM1 Break\n TIM1_UP_IRQHandler, // 35 - TIM1 Update\n TIM1_TRG_COM_IRQHandler, // 36 - TIM1 Trigger and Commutation\n TIM1_CC_IRQHandler, // 37 - TIM1 Capture Compare\n TIM2_UP_IRQHandler, // 38 - TIM2 Update\n USART2_IRQHandler, // 39 - USART2\n EXTI15_8_IRQHandler, // 40 - EXTI Line 15..8\n EXTI25_16_IRQHandler, // 41 - EXTI Line 25..16\n USART3_IRQHandler, // 42 - USART3\n USART4_IRQHandler, // 43 - USART4\n DMA1_Channel8_IRQHandler, // 44 - DMA1 Channel8\n USBFS_IRQHandler, // 45 - USBFS Break\n USBFSWakeUp_IRQHandler, // 46 - USBFS Wake up from suspend\n PIOC_IRQHandler, // 47 - PIOC\n OPA_IRQHandler, // 48 - OPA\n USBPD_IRQHandler, // 49 - USBPD\n USBPDWakeUp_IRQHandler, // 50 - USBPD Wake-up\n TIM2_CC_IRQHandler, // 51 - TIM2 Capture Compare\n TIM2_TRG_COM_IRQHandler, // 52 - TIM2 Trigger and Commutation\n TIM2_BRK_IRQHandler, // 53 - TIM2 Break\n TIM3_IRQHandler // 54 - TIM3\n #endif // SYS_USE_VECTORS > 0\n};\n\n// Reset handler\nvoid reset_handler(void) {\n uint32_t *src, *dst;\n \n // Set pointers, vectors, processor status, and interrupts\n asm volatile(\n \" .option push \\n\\\n .option norelax \\n\\\n la gp, __global_pointer$ \\n\\\n .option pop \\n\\\n la sp, _eusrstack \\n\"\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \" li a0, 0x1f \\n\\\n csrw 0xbc0, a0 \\n\\\n li a0, 0x88 \\n\\\n csrs mstatus, a0 \\n\\\n li a1, 0x3 \\n\\\n csrw 0x804, a1 \\n\\\n la a0, vectors \\n\\\n or a0, a0, a1 \\n\\\n csrw mtvec, a0 \\n\\\n csrw mepc, %[main] \\n\"\n : : [main] \"r\" (main) : \"a0\", \"a1\" , \"memory\"\n );\n\n // Copy data from FLASH to RAM\n src = &_data_lma;\n dst = &_data_vma;\n while(dst < &_edata) *dst++ = *src++;\n\n // Clear uninitialized variables\n #if SYS_CLEAR_BSS > 0\n dst = &_sbss;\n while(dst < &_ebss) *dst++ = 0;\n #endif\n\n // C++ Support\n #ifdef __cplusplus\n __libc_init_array();\n #endif\n\n // Init system\n SYS_init();\n\n // Return\n asm volatile(\"mret\");\n}\n" }, { "path": "software/pd_tester/src/system.h", "content": "// ===================================================================================\n// Basic System Functions for CH32X035/X034/X033 * v1.1 *\n// ===================================================================================\n//\n// This file must be included!!! The system configuration and the system clock are \n// set up automatically on system start.\n//\n// System clock functions available:\n// ---------------------------------\n// CLK_init() init system clock according to F_CPU\n// CLK_reset() reset system clock to default state\n//\n// HSI_enable() enable internal 48 MHz high-speed clock (HSI)\n// HSI_disable() disable HSI\n// HSI_ready() check if HSI is stable\n//\n// MCO_init() init clock output to pin PB9\n// MCO_setSYS() output SYS_CLK on pin PB9\n// MCO_setHSI() output internal oscillator on pin PB9\n// MCO_stop() stop clock output\n//\n// Delay (DLY) functions available:\n// --------------------------------\n// DLY_ticks(n) delay n system clock cycles\n// DLY_us(n) delay n microseconds\n// DLY_ms(n) delay n milliseconds\n//\n// Reset (RST) and Bootloader (BOOT) functions available:\n// ------------------------------------------------------\n// BOOT_now() conduct software reset and jump to bootloader\n// RST_now() conduct software reset\n// RST_clearFlags() clear all reset flags\n// RST_wasLowPower() check if last reset was caused by low power\n// RST_wasWWDG() check if last reset was caused by window watchdog\n// RST_wasIWDG() check if last reset was caused by independent watchdog\n// RST_wasSoftware() check if last reset was caused by software\n// RST_wasPower() check if last reset was caused by power up\n// RST_wasPin() check if last reset was caused by RST pin low\n// RST_wasOPA() check if last reset was caused by OPA\n//\n// Independent Watchdog Timer (IWDG) functions available:\n// ------------------------------------------------------\n// IWDG_start(n) start independent watchdog timer, n milliseconds, n<=5591\n// IWDG_reload(n) reload watchdog counter with n milliseconds, n<=5591\n// IWDG_feed() feed the dog (reload last time)\n//\n// Automatic Wake-up Timer (AWU) functions available:\n// --------------------------------------------------\n// AWU_start(n) start AWU with n milliseconds period and event trigger\n// AWU_stop() stop AWU and event trigger\n// AWU_set(n) set AWU period to n milliseconds\n//\n// AWU_enable() enable AWU\n// AWU_disable() disable AWU\n// AWU_RT_enable() enable AWU rising edge trigger\n// AWU_RT_disable() disable AWU rising edge trigger\n// AWU_EV_enable() enable AWU event\n// AWU_EV_disable() disable AWU event\n// AWU_INT_enable() enable AWU interrupt (without NVIC)\n// AWU_INT_disable() disable AWU interrupt (without NVIC)\n//\n// Sleep functions available:\n// --------------------------\n// SLEEP_WFI_now() put device into SLEEP, wake up by interrupt\n// SLEEP_WFE_now() put device into SLEEP, wake up by event\n// STOP_WFI_now() put device into STOP, wake up by interrupt\n// STOP_WFE_now() put device into STOP, wake up by event\n// STDBY_WFI_now() put device into STANDBY (deep sleep), wake by interrupt\n// STDBY_WFE_now() put device into STANDBY (deep sleep), wake by event\n//\n// SLEEP_ms(n) put device into SLEEP for n milliseconds (uses AWU)\n// STOP_ms(n) put device into STOP for n milliseconds (uses AWU)\n// STDBY_ms(n) put device into STANDBY for n milliseconds (uses AWU)\n//\n// Programmable Voltage Detector (PVD) functions available:\n// --------------------------------------------------------\n// PVD_enable() enable PVD (power module clock)\n// PVD_set_2V1() set detection level to 2.1V\n// PVD_set_2V3() set detection level to 2.3V\n// PVD_set_3V0() set detection level to 3.0V\n// PVD_set_4V0() set detection level to 4.0V\n// PVD_isLow() check if VDD is below detection level\n//\n// Interrupt (INT) functions available:\n// ------------------------------------\n// INT_enable() global interrupt enable\n// INT_disable() global interrupt disable\n// INT_ATOMIC_BLOCK { } execute block without being interrupted\n//\n// References:\n// -----------\n// - WCH Nanjing Qinheng Microelectronics: http://wch.cn\n//\n// 2023 by Stefan Wagner: https://github.com/wagiminator\n\n#pragma once\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"ch32x035.h\"\n\n// ===================================================================================\n// System Options (set \"1\" to activate)\n// ===================================================================================\n#define SYS_CLK_INIT 1 // 1: init system clock on startup\n#define SYS_TICK_INIT 1 // 1: init and start SYSTICK on startup\n#define SYS_GPIO_EN 1 // 1: enable GPIO ports on startup\n#define SYS_CLEAR_BSS 1 // 1: clear uninitialized variables\n#define SYS_USE_VECTORS 1 // 1: create interrupt vector table\n\n// ===================================================================================\n// Sytem Clock Defines\n// ===================================================================================\n// Set system clock frequency\n#ifndef F_CPU\n #define F_CPU 8000000 // 8 Mhz if not otherwise defined\n#endif\n\n// Calculate system clock settings\n#if F_CPU == 48000000\n #define SYS_CLK_DIV RCC_HPRE_DIV1\n#elif F_CPU == 24000000\n #define SYS_CLK_DIV RCC_HPRE_DIV2\n#elif F_CPU == 16000000\n #define SYS_CLK_DIV RCC_HPRE_DIV3\n#elif F_CPU == 12000000\n #define SYS_CLK_DIV RCC_HPRE_DIV4\n#elif F_CPU == 9600000\n #define SYS_CLK_DIV RCC_HPRE_DIV5\n#elif F_CPU == 8000000\n #define SYS_CLK_DIV RCC_HPRE_DIV6\n#elif F_CPU == 6000000\n #define SYS_CLK_DIV RCC_HPRE_DIV8\n#elif F_CPU == 3000000\n #define SYS_CLK_DIV RCC_HPRE_DIV16\n#elif F_CPU == 1500000\n #define SYS_CLK_DIV RCC_HPRE_DIV32\n#elif F_CPU == 750000\n #define SYS_CLK_DIV RCC_HPRE_DIV64\n#elif F_CPU == 375000\n #define SYS_CLK_DIV RCC_HPRE_DIV128\n#elif F_CPU == 187500\n #define SYS_CLK_DIV RCC_HPRE_DIV256\n#else\n #warning Unsupported system clock frequency, using internal 8 MHz\n #define SYS_CLK_DIV RCC_HPRE_DIV6\n #undef F_CPU\n #define F_CPU 8000000\n#endif\n\n// ===================================================================================\n// System Clock Functions\n// ===================================================================================\nvoid CLK_reset(void); // reset system clock to default state\nvoid MCO_init(void); // init clock output to pin PB9\n\n// Internal 48MHz high-speed clock (HSI) functions\n#define CLK_init() RCC->CFGR0 = SYS_CLK_DIV // init system clock\n#define HSI_enable() RCC->CTLR |= RCC_HSION // enable HSI\n#define HSI_disable() RCC->CTLR &= ~RCC_HSION // disable HSI\n#define HSI_ready() (RCC->CTLR & RCC_HSIRDY) // check if HSI is stable\n\n// Clock output functions (pin PA8)\n#define MCO_setSYS() RCC->CFGR0 = (RCC->CFGR0 & ~RCC_CFGR0_MCO) | RCC_CFGR0_MCO_SYSCLK\n#define MCO_setHSI() RCC->CFGR0 = (RCC->CFGR0 & ~RCC_CFGR0_MCO) | RCC_CFGR0_MCO_HSI\n#define MCO_stop() RCC->CFGR0 &= ~RCC_CFGR0_MCO // stop clock output to pin PB9\n\n// ===================================================================================\n// Delay (DLY) Functions\n// ===================================================================================\nvoid DLY_ticks(uint32_t n); // delay n system ticks\n\n#define STK_init() STK->CTLR = STK_CTLR_STE | STK_CTLR_STCLK // init SYSTICK @ F_CPU\n#define DLY_US_TIME (F_CPU / 1000000) // system ticks per us\n#define DLY_MS_TIME (F_CPU / 1000) // system ticks per ms\n#define DLY_us(n) DLY_ticks((n) * DLY_US_TIME) // delay n microseconds\n#define DLY_ms(n) DLY_ticks((n) * DLY_MS_TIME) // delay n milliseconds\n#define DLY_cycles DLY_ticks // alias\n\n// ===================================================================================\n// Reset (RST) Functions\n// ===================================================================================\n#define RST_now() PFIC->CFGR = PFIC_RESETSYS | PFIC_KEY3\n#define RST_clearFlags() RCC->RSTSCKR |= RCC_RMVF\n#define RST_wasLowPower() (RCC->RSTSCKR & RCC_LPWRRSTF)\n#define RST_wasWWDG() (RCC->RSTSCKR & RCC_WWDGRSTF)\n#define RST_wasIWDG() (RCC->RSTSCKR & RCC_IWDGRSTF)\n#define RST_wasSoftware() (RCC->RSTSCKR & RCC_SFTRSTF)\n#define RST_wasPower() (RCC->RSTSCKR & RCC_PORRSTF)\n#define RST_wasPin() (RCC->RSTSCKR & RCC_PINRSTF)\n#define RST_wasOPA() (RCC->RSTSCKR & RCC_OPARSTF)\n\n// ===================================================================================\n// Bootloader (BOOT) Functions\n// ===================================================================================\nvoid BOOT_now(void); // perform software reset and jump to bootloader\n\n// ===================================================================================\n// Independent Watchdog Timer (IWDG) Functions\n// ===================================================================================\nvoid IWDG_start_t(uint16_t ticks); // start IWDG with n ticks\nvoid IWDG_reload_t(uint16_t ticks); // reload IWDG with n ticks\n\n#define IWDG_start(n) IWDG_start_t((HSI_VALUE/1000)*(n)/65536)\n#define IWDG_reload(n) IWDG_reload_t((HSI_VALUE/1000)*(n)/65536)\n#define IWDG_feed() IWDG->CTLR = 0xAAAA\n#define IWDG_reset() IWDG->CTLR = 0xAAAA // alias\n\n// ===================================================================================\n// Automatic Wake-up Timer (AWU) Functions\n// ===================================================================================\nvoid AWU_init(void);\nvoid AWU_stop(void);\n\n#define AWU_start(n) {AWU_init(); AWU_set(n);}\n#define AWU_enable() AWU->CSR = 0x02\n#define AWU_disable() AWU->CSR = 0x00\n#define AWU_RT_enable() EXTI->RTENR |= ((uint32_t)1 << 27)\n#define AWU_RT_disable() EXTI->RTENR &= ~((uint32_t)1 << 27)\n#define AWU_EV_enable() EXTI->EVENR |= ((uint32_t)1 << 27)\n#define AWU_EV_disable() EXTI->EVENR &= ~((uint32_t)1 << 27)\n#define AWU_INT_enable() EXTI->INTENR |= ((uint32_t)1 << 27)\n#define AWU_INT_disable() EXTI->INTENR &= ~((uint32_t)1 << 27)\n\n#define AWU_WRVAL(n) ((HSI_VALUE/1000)*(n)/1024)\n#define AWU_LIMIT(n) (63*(n)*1024/(HSI_VALUE/1000))\n\n#define AWU_set(n) \\\n (n <= AWU_LIMIT( 32) ? ({AWU->PSC = 0b0110; AWU->WR = AWU_WRVAL(n) / 32;}) : \\\n (n <= AWU_LIMIT( 64) ? ({AWU->PSC = 0b0111; AWU->WR = AWU_WRVAL(n) / 64;}) : \\\n (n <= AWU_LIMIT( 128) ? ({AWU->PSC = 0b1000; AWU->WR = AWU_WRVAL(n) / 128;}) : \\\n (n <= AWU_LIMIT( 256) ? ({AWU->PSC = 0b1001; AWU->WR = AWU_WRVAL(n) / 256;}) : \\\n (n <= AWU_LIMIT( 512) ? ({AWU->PSC = 0b1010; AWU->WR = AWU_WRVAL(n) / 512;}) : \\\n (n <= AWU_LIMIT( 1024) ? ({AWU->PSC = 0b1011; AWU->WR = AWU_WRVAL(n) / 1024;}) : \\\n (n <= AWU_LIMIT( 2048) ? ({AWU->PSC = 0b1100; AWU->WR = AWU_WRVAL(n) / 2048;}) : \\\n (n <= AWU_LIMIT( 4096) ? ({AWU->PSC = 0b1101; AWU->WR = AWU_WRVAL(n) / 4096;}) : \\\n (n <= AWU_LIMIT(10240) ? ({AWU->PSC = 0b1110; AWU->WR = AWU_WRVAL(n) / 10240;}) : \\\n (n <= AWU_LIMIT(61440) ? ({AWU->PSC = 0b1111; AWU->WR = AWU_WRVAL(n) / 61440;}) : \\\n (0)))))))))))\n\n#define AWU_SLEEP(n) {AWU_set(n); SLEEP_WFE_now();}\n#define AWU_STOP(n) {AWU_set(n); STOP_WFE_now();}\n#define AWU_STDBY(n) {AWU_set(n); STDBY_WFE_now();}\n\n// ===================================================================================\n// Sleep Functions\n// ===================================================================================\nvoid SLEEP_WFI_now(void); // put device into sleep, wake up by interrupt\nvoid SLEEP_WFE_now(void); // put device into sleep, wake up by event\nvoid STOP_WFI_now(void); // put device into stop, wake up by interrupt\nvoid STOP_WFE_now(void); // put device into stop, wake up by event\nvoid STDBY_WFI_now(void); // put device into standby (deep sleep), wake up interrupt\nvoid STDBY_WFE_now(void); // put device into standby (deep sleep), wake up event\n\n#define SLEEP_ms(n) {AWU_start(n); SLEEP_WFE_now(); AWU_stop();}\n#define STOP_ms(n) {AWU_start(n); STOP_WFE_now(); AWU_stop();}\n#define STDBY_ms(n) {AWU_start(n); STDBY_WFE_now(); AWU_stop();}\n\n// ===================================================================================\n// Programmable Voltage Detector (PVD) Functions\n// ===================================================================================\n#define PVD_enable() RCC->APB1PCENR |= RCC_PWREN\n#define PVD_set_2V1() PWR->CTLR &= ~PWR_CTLR_PLS\n#define PVD_set_2V3() PWR->CTLR = (PWR->CTLR & ~PWR_CTLR_PLS) | PWR_CTLR_PLS_2V3\n#define PVD_set_3V0() PWR->CTLR = (PWR->CTLR & ~PWR_CTLR_PLS) | PWR_CTLR_PLS_3V0\n#define PVD_set_4V0() PWR->CTLR |= PWR_CTLR_PLS\n#define PVD_isLow() (PWR->CSR & PWR_CSR_PVDO)\n\n#define PVD_RT_enable() EXTI->RTENR |= ((uint32_t)1 << 26)\n#define PVD_RT_disable() EXTI->RTENR &= ~((uint32_t)1 << 26)\n#define PVD_FT_enable() EXTI->FTENR |= ((uint32_t)1 << 26)\n#define PVD_FT_disable() EXTI->FTENR &= ~((uint32_t)1 << 26)\n#define PVD_EV_enable() EXTI->EVENR |= ((uint32_t)1 << 26)\n#define PVD_EV_disable() EXTI->EVENR &= ~((uint32_t)1 << 26)\n#define PVD_INT_enable() EXTI->INTENR |= ((uint32_t)1 << 26)\n#define PVD_INT_disable() EXTI->INTENR &= ~((uint32_t)1 << 26)\n\n// ===================================================================================\n// Interrupt (INT) Functions\n// ===================================================================================\n#define INT_enable() __enable_irq()\n#define INT_disable() __disable_irq()\n#define INT_ATOMIC_BLOCK for(INT_ATOMIC_RESTORE, __ToDo = 1; __ToDo; __ToDo = 0)\n#define INT_ATOMIC_RESTORE uint32_t __reg_save __attribute__((__cleanup__(__iRestore))) = __iSave()\n\n// Save interrupt status and disable interrupts\nstatic inline uint32_t __iSave(void) {\n uint32_t result;\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrr %0, 0x800 \\n\"\n \"csrw 0x800, %1 \\n\"\n : \"=&r\" (result) : \"r\" (0x6000)\n );\n return result;\n}\n\n// Restore interrupt status\nstatic inline void __iRestore(const uint32_t *__s) {\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrw 0x800, %0\" : : \"r\" (*__s)\n );\n}\n\n// ===================================================================================\n// Device Electronic Signature (ESIG)\n// ===================================================================================\n#define ESIG_FLASHSIZE (*(__I uint16_t*)(0x1FFFF7E0))\n#define ESIG_UID1 (*(__I uint32_t*)(0x1FFFF7E8))\n#define ESIG_UID2 (*(__I uint32_t*)(0x1FFFF7EC))\n#define ESIG_UID3 (*(__I uint32_t*)(0x1FFFF7F0))\n\n// ===================================================================================\n// Imported System Functions\n// ===================================================================================\n// Enable Global Interrupt\n__attribute__((always_inline)) static inline void __enable_irq(void) {\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrw 0x800, %0\" : : \"r\" (0x6088)\n );\n}\n\n// Disable Global Interrupt\n__attribute__((always_inline)) static inline void __disable_irq(void) {\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrw 0x800, %0\" : : \"r\" (0x6000)\n );\n}\n\n// Return the Machine Status Register\n__attribute__((always_inline)) static inline uint32_t __get_MSTATUS(void) {\n uint32_t result;\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrr %0, mstatus\" : \"=r\"(result)\n );\n return (result);\n}\n\n// Set the Machine Status Register\n__attribute__((always_inline)) static inline void __set_MSTATUS(uint32_t value) {\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrw mstatus, %0\" : : \"r\"(value)\n );\n}\n\n// Return the Machine ISA Register\n__attribute__((always_inline)) static inline uint32_t __get_MISA(void) {\n uint32_t result;\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrr %0, misa\" : \"=r\"(result)\n );\n return (result);\n}\n\n// Set the Machine ISA Register\n__attribute__((always_inline)) static inline void __set_MISA(uint32_t value) {\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrw misa, %0\" : : \"r\"(value)\n );\n}\n\n// Return the Machine Trap-Vector Base-Address Register\n__attribute__((always_inline)) static inline uint32_t __get_MTVEC(void) {\n uint32_t result;\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrr %0, mtvec\": \"=r\"(result)\n );\n return (result);\n}\n\n// Set the Machine Trap-Vector Base-Address Register\n__attribute__((always_inline)) static inline void __set_MTVEC(uint32_t value) {\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrw mtvec, %0\" : : \"r\"(value)\n );\n}\n\n// Return the Machine Seratch Register\n__attribute__((always_inline)) static inline uint32_t __get_MSCRATCH(void) {\n uint32_t result;\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrr %0, mscratch\" : \"=r\"(result)\n );\n return (result);\n}\n\n// Set the Machine Seratch Register\n__attribute__((always_inline)) static inline void __set_MSCRATCH(uint32_t value) {\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrw mscratch, %0\" : : \"r\"(value)\n );\n}\n\n// Return the Machine Exception Program Register\n__attribute__((always_inline)) static inline uint32_t __get_MEPC(void) {\n uint32_t result;\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrr %0, mepc\" : \"=r\"(result)\n );\n return (result);\n}\n\n// Set the Machine Exception Program Register\n__attribute__((always_inline)) static inline void __set_MEPC(uint32_t value) {\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrw mepc, %0\" : : \"r\"(value)\n );\n}\n\n// Return the Machine Cause Register\n__attribute__((always_inline)) static inline uint32_t __get_MCAUSE(void) {\n uint32_t result;\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrr %0, mcause\": \"=r\"(result)\n );\n return (result);\n}\n\n// Set the Machine Cause Register\n__attribute__((always_inline)) static inline void __set_MCAUSE(uint32_t value) {\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrw mcause, %0\" : : \"r\"(value)\n );\n}\n\n// Return Vendor ID Register\n__attribute__((always_inline)) static inline uint32_t __get_MVENDORID(void) {\n uint32_t result;\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrr %0, mvendorid\" : \"=r\"(result)\n );\n return (result);\n}\n\n// Return Machine Architecture ID Register\n__attribute__((always_inline)) static inline uint32_t __get_MARCHID(void) {\n uint32_t result;\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrr %0, marchid\" : \"=r\"(result)\n );\n return (result);\n}\n\n// Return Machine Implementation ID Register\n__attribute__((always_inline)) static inline uint32_t __get_MIMPID(void) {\n uint32_t result;\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrr %0, mimpid\" : \"=r\"(result)\n );\n return (result);\n}\n\n// Return Hart ID Register\n__attribute__((always_inline)) static inline uint32_t __get_MHARTID(void) {\n uint32_t result;\n __asm volatile(\n #if __GNUC__ > 10\n \".option arch, +zicsr \\n\"\n #endif\n \"csrr %0, mhartid\" : \"=r\"(result)\n );\n return (result);\n}\n\n// Return SP Register\n__attribute__((always_inline)) static inline uint32_t __get_SP(void) {\n uint32_t result;\n __asm volatile(\"mv %0, sp\" : \"=r\"(result):);\n return (result);\n}\n\n// No OPeration\n__attribute__((always_inline)) static inline void __NOP(void) {\n __asm volatile(\"nop\");\n}\n\n// Enable NVIC interrupt (interrupt numbers)\n__attribute__((always_inline)) static inline void NVIC_EnableIRQ(IRQn_Type IRQn) {\n NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));\n}\n\n// Disable NVIC interrupt (interrupt numbers)\n__attribute__((always_inline)) static inline void NVIC_DisableIRQ(IRQn_Type IRQn) {\n NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));\n}\n\n// Get Interrupt Enable State\n__attribute__((always_inline)) static inline uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) {\n return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\n}\n\n// Get Interrupt Pending State\n__attribute__((always_inline)) static inline uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) {\n return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\n}\n\n// Set Interrupt Pending\n__attribute__((always_inline)) static inline void NVIC_SetPendingIRQ(IRQn_Type IRQn) {\n NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));\n}\n\n// Clear Interrupt Pending\n__attribute__((always_inline)) static inline void NVIC_ClearPendingIRQ(IRQn_Type IRQn) {\n NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));\n}\n\n// Get Interrupt Active State\n__attribute__((always_inline)) static inline uint32_t NVIC_GetActive(IRQn_Type IRQn) {\n return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));\n}\n\n// Set Interrupt Priority\n__attribute__((always_inline)) static inline void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) {\n NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;\n}\n\n// Wait for Interrupt\n__attribute__((always_inline)) static inline void __WFI(void) {\n NVIC->SCTLR &= ~(1<<3); // wfi\n asm volatile (\"wfi\");\n}\n\n// Set Event\n__attribute__((always_inline)) static inline void _SEV(void) {\n uint32_t t;\n t = NVIC->SCTLR;\n NVIC->SCTLR |= (1<<3)|(1<<5);\n NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));\n}\n\n// Wait for Events\n__attribute__((always_inline)) static inline void _WFE(void) {\n NVIC->SCTLR |= (1<<3);\n __asm volatile (\"wfi\");\n}\n\n// Wait for Events\n__attribute__((always_inline)) static inline void __WFE(void) {\n _SEV();\n _WFE();\n _WFE();\n}\n\n// Set VTF Interrupt\n__attribute__((always_inline)) static inline void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState) {\n if(num > 3) return;\n if(NewState != DISABLE) {\n NVIC->VTFIDR[num] = IRQn;\n NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);\n }\n else {\n NVIC->VTFIDR[num] = IRQn;\n NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));\n }\n}\n\n// Initiate a system reset request\n__attribute__((always_inline)) static inline void NVIC_SystemReset(void) {\n NVIC->CFGR = NVIC_KEY3|(1<<7);\n}\n\n// Atomic Add with 32bit value\n__attribute__((always_inline)) static inline int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) {\n int32_t result;\n __asm volatile (\"amoadd.w %0, %2, %1\" : \"=r\"(result), \"+A\"(*addr) : \"r\"(value) : \"memory\");\n return *addr;\n}\n\n// Atomic And with 32bit value\n__attribute__((always_inline)) static inline int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) {\n int32_t result;\n __asm volatile (\"amoand.w %0, %2, %1\" : \"=r\"(result), \"+A\"(*addr) : \"r\"(value) : \"memory\");\n return *addr;\n}\n\n// Atomic signed MAX with 32bit value\n__attribute__((always_inline)) static inline int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) {\n int32_t result;\n __asm volatile (\"amomax.w %0, %2, %1\" : \"=r\"(result), \"+A\"(*addr) : \"r\"(value) : \"memory\");\n return *addr;\n}\n\n// Atomic unsigned MAX with 32bit value\n__attribute__((always_inline)) static inline uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) {\n uint32_t result;\n __asm volatile (\"amomaxu.w %0, %2, %1\" : \"=r\"(result), \"+A\"(*addr) : \"r\"(value) : \"memory\");\n return *addr;\n}\n\n// Atomic signed MIN with 32bit value\n__attribute__((always_inline)) static inline int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) {\n int32_t result;\n __asm volatile (\"amomin.w %0, %2, %1\" : \"=r\"(result), \"+A\"(*addr) : \"r\"(value) : \"memory\");\n return *addr;\n}\n\n// Atomic unsigned MIN with 32bit value\n__attribute__((always_inline)) static inline uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) {\n uint32_t result;\n __asm volatile (\"amominu.w %0, %2, %1\" : \"=r\"(result), \"+A\"(*addr) : \"r\"(value) : \"memory\");\n return *addr;\n}\n\n// Atomic OR with 32bit value\n__attribute__((always_inline)) static inline int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) {\n int32_t result;\n __asm volatile (\"amoor.w %0, %2, %1\" : \"=r\"(result), \"+A\"(*addr) : \"r\"(value) : \"memory\");\n return *addr;\n}\n\n// Atomically swap new 32bit value into memory using amoswap.d\n__attribute__((always_inline)) static inline uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) {\n uint32_t result;\n __asm volatile (\"amoswap.w %0, %2, %1\" : \"=r\"(result), \"+A\"(*addr) : \"r\"(newval) : \"memory\");\n return result;\n}\n\n// Atomic XOR with 32bit value\n__attribute__((always_inline)) static inline int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) {\n int32_t result;\n __asm volatile (\"amoxor.w %0, %2, %1\" : \"=r\"(result), \"+A\"(*addr) : \"r\"(value) : \"memory\");\n return *addr;\n}\n\n#ifdef __cplusplus\n};\n#endif\n" }, { "path": "software/pd_tester/src/usbpd.h", "content": "// ===================================================================================\n// USB PD Constant and Structure Defines * v1.1 *\n// ===================================================================================\n\n#pragma once\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \n\n// Get values from PDO representation\n#define POWER_DECODE_50MV(value) ((uint16_t)(((value) * 50))) // From 50mV multiples to mV\n#define POWER_DECODE_100MV(value) ((uint16_t)(((value) * 100))) // From 100mV multiples to mV\n#define POWER_DECODE_10MA(value) ((uint16_t)(((value) * 10))) // From 10mA multiples to mA\n#define POWER_DECODE_50MA(value) ((uint16_t)(((value) * 50))) // From 50mA multiples to mA\n\n// PD PHY Channel\n#define USBPD_CCNONE 0x00u\n#define USBPD_CC1 0x01u\n#define USBPD_CC2 0x02u\n\n// USB PD Revision\n#define USBPD_SPECIFICATION_REV1 0x00u // Revision 1.0\n#define USBPD_SPECIFICATION_REV2 0x01u // Revision 2.0\n#define USBPD_SPECIFICATION_REV3 0x02u // Revision 3.0\n\n// USB PD Revision aliases\n#define USBPD_REVISION_10 0x00u // Revision 1.0\n#define USBPD_REVISION_20 0x01u // Revision 2.0\n#define USBPD_REVISION_30 0x02u // Revision 3.0\n\ntypedef struct {\n uint32_t MaxCurrentIn10mAunits : 10u;\n uint32_t VoltageIn50mVunits : 10u;\n uint32_t PeakCurrent : 2u;\n uint32_t Reserved_22bit : 1u;\n uint32_t EPRModeCapable : 1u;\n uint32_t UnchunkedExtendedMessage : 1u;\n uint32_t DualRoleData : 1u;\n uint32_t USBCommunicationsCapable : 1u;\n uint32_t UnconstrainedPower : 1u;\n uint32_t USBSuspendSupported : 1u;\n uint32_t DualRolePower : 1u;\n uint32_t FixedSupply : 2u;\n} USBPD_SourceFixedSupplyPDO_t;\n\ntypedef struct {\n uint32_t MaxCurrentIn50mAincrements : 7u;\n uint32_t Reserved_7bit : 1u; // shall be set to zero\n uint32_t MinVoltageIn100mVincrements: 8u;\n uint32_t Reserved_16bit : 1u; // shall be set to zero\n uint32_t MaxVoltageIn100mVincrements: 8u;\n uint32_t Reserved_25_26bit : 2u; // shall be set to zero\n uint32_t PPSpowerLimited : 1u; \n uint32_t SPRprogrammablePowerSupply : 2u; // 00b\n uint32_t AugmentedPowerDataObject : 2u; // 11b\n} USBPD_SourcePPSSupplyPDO_t;\n\ntypedef struct {\n uint32_t MaxPowerIn1Wincrements : 8u;\n uint32_t MinVoltageIn100mVincrements: 8u;\n uint32_t Reserved_16bit : 1u; // shall be set to zero\n uint32_t MaxVoltageIn100mVincrements: 9u;\n uint32_t Reserved_26_27bit : 2u; // shall be set to zero\n uint32_t EPRprogrammablePowerSupply : 2u; // 01b\n uint32_t AugmentedPowerDataObject : 2u; // 11b\n} USBPD_SourceEPRSupplyPDO_t;\n\ntypedef union {\n uint32_t d32;\n USBPD_SourceFixedSupplyPDO_t SourceFixedPDO;\n USBPD_SourcePPSSupplyPDO_t SourcePPSPDO;\n USBPD_SourceEPRSupplyPDO_t SourceEPRPDO;\n} USBPD_PDO_t;\n\ntypedef enum {\n USBPD_CONTROL_MSG_GOODCRC = 0x01u,\n USBPD_CONTROL_MSG_GOTOMIN = 0x02u, \n USBPD_CONTROL_MSG_ACCEPT = 0x03u, \n USBPD_CONTROL_MSG_REJECT = 0x04u, \n USBPD_CONTROL_MSG_PING = 0x05u, \n USBPD_CONTROL_MSG_PS_RDY = 0x06u, \n USBPD_CONTROL_MSG_GET_SRC_CAP = 0x07u, \n USBPD_CONTROL_MSG_GET_SNK_CAP = 0x08u, \n USBPD_CONTROL_MSG_DR_SWAP = 0x09u, \n USBPD_CONTROL_MSG_PR_SWAP = 0x0Au, \n USBPD_CONTROL_MSG_VCONN_SWAP = 0x0Bu, \n USBPD_CONTROL_MSG_WAIT = 0x0Cu, \n USBPD_CONTROL_MSG_SOFT_RESET = 0x0Du, \n USBPD_CONTROL_MSG_DATA_RESET = 0x0Eu, \n USBPD_CONTROL_MSG_DATA_RESET_COMPLETE = 0x0Fu, \n USBPD_CONTROL_MSG_NOT_SUPPORTED = 0x10u, \n USBPD_CONTROL_MSG_GET_SRC_CAPEXT = 0x11u, \n USBPD_CONTROL_MSG_GET_STATUS = 0x12u, \n USBPD_CONTROL_MSG_FR_SWAP = 0x13u, \n USBPD_CONTROL_MSG_GET_PPS_STATUS = 0x14u, \n USBPD_CONTROL_MSG_GET_COUNTRY_CODES = 0x15u, \n USBPD_CONTROL_MSG_GET_SNK_CAPEXT = 0x16u,\n USBPD_CONTROL_MSG_GET_SRC_INFO = 0x17u, \n USBPD_CONTROL_MSG_GET_REVISION = 0x18u, \n} USBPD_ControlMessage_t;\n\ntypedef enum {\n USBPD_DATA_MSG_SRC_CAP = 0x01u,\n USBPD_DATA_MSG_REQUEST = 0x02u, \n USBPD_DATA_MSG_BIST = 0x03u, \n USBPD_DATA_MSG_SNK_CAP = 0x04u, \n USBPD_DATA_MSG_BATTERY_STATUS = 0x05u, \n USBPD_DATA_MSG_ALERT = 0x06u, \n USBPD_DATA_MSG_GET_COUNTRY_INFO = 0x07u, \n USBPD_DATA_MSG_ENTER_USB = 0x08u,\n USBPD_DATA_MSG_EPR_REUEST = 0x09u,\n USBPD_DATA_MSG_EPR_MODE = 0x0Au,\n USBPD_DATA_MSG_SRC_INFO = 0x0Bu,\n USBPD_DATA_MSG_REVISION = 0x0Cu,\n USBPD_DATA_MSG_VENDOR_DEFINED = 0x0Fu \n} USBPD_DataMessage_t;\n\ntypedef union {\n uint16_t d16;\n USBPD_DataMessage_t DataMessage;\n USBPD_ControlMessage_t ControlMessage;\n} USBPD_MessageType_t;\n\ntypedef struct {\n uint16_t MessageType : 5u;\n uint16_t PortDataRole : 1u; // 0b->UFP, 1b->DFP\n uint16_t SpecificationRevision : 2u; // 00b->v1.0, 01b->v2.0, 10b->v3.0\n uint16_t PortPowerRole : 1u; // 0b->sink, 1b->source\n uint16_t MessageID : 3u;\n uint16_t NumberOfDataObjects : 3u;\n uint16_t Extended : 1u;\n} USBPD_MessageHeader_tt;\n\ntypedef union {\n uint16_t d16;\n USBPD_MessageHeader_tt MessageHeader;\n} USBPD_MessageHeader_t;\n\ntypedef struct {\n uint32_t MaxOperatingCurrent10mAunits : 10u;\n uint32_t OperatingCurrentIn10mAunits : 10u;\n uint32_t Reserved20_21 : 2u; // 00b\n uint32_t EPRModeCapable : 1u; \n uint32_t UnchunkedExtendedMessage : 1u;\n uint32_t NoUSBSuspend : 1u;\n uint32_t USBCommunicationsCapable : 1u;\n uint32_t CapabilityMismatch : 1u;\n uint32_t GiveBackFlag : 1u;\n uint32_t ObjectPosition : 4u;\n} USBPD_SinkFixedVariableRDO_t;\n\ntypedef struct {\n uint32_t OperatingCurrentIn50mAunits : 7u;\n uint32_t Reserved7_8 : 2u; // shall be set to zero\n uint32_t OutputVoltageIn20mVunits : 12u;\n uint32_t Reserved21 : 1u; // shall be set to zero\n uint32_t EPRModeCapable : 1u;\n uint32_t UnchunkedExtendedMessage : 1u;\n uint32_t NoUSBSuspend : 1u;\n uint32_t USBCommunicationsCapable : 1u;\n uint32_t CapabilityMismatch : 1u;\n uint32_t Rserved27 : 1u; // shall be set to zero\n uint32_t ObjectPosition : 4u;\n} USBPD_SinkPPSRDO_t;\n\ntypedef union {\n uint32_t d32;\n USBPD_SinkFixedVariableRDO_t SinkFixedVariableRDO;\n USBPD_SinkPPSRDO_t SinkPPSRDO;\n} USBPD_SINKRDO_t;\n\n#ifdef __cplusplus\n}\n#endif\n" }, { "path": "software/pd_tester/src/usbpd_sink.c", "content": "// ===================================================================================\n// USB PD SINK Handler for CH32X035 * v1.5 *\n// ===================================================================================\n//\n// Reference: https://github.com/openwch/ch32x035\n// 2023 by Stefan Wagner: https://github.com/wagiminator\n\n#include \"usbpd_sink.h\"\n\n// Variables\nstatic pd_control_t PD_control = {\n .CC_State = CC_IDLE,\n .CC1_ConnectTimes = 0,\n .CC2_ConnectTimes = 0,\n};\n\nFixedSourceCap_t PD_SC_fixed[5];\nPPSSourceCap_t PD_SC_PPS[2];\n\n// Buffers\n__attribute__ ((aligned(4))) uint8_t PD_TR_buffer[34]; // PD transmit/receive buffer \n__attribute__ ((aligned(4))) uint8_t PD_SC_buffer[28]; // PD Source Cap buffer\n\n// ===================================================================================\n// USB PD SINK Front End Functions\n// ===================================================================================\n\n// Prototype\nvoid PD_update(void);\n\n// Negotiate current settings and wait until finished (return 1) or timeout (return 0)\nuint8_t PD_negotiate(void) {\n uint8_t counter = 255;\n PD_control.LastSetVoltage = 0;\n PD_control.USBPD_READY = 0;\n while((!PD_control.USBPD_READY) && (--counter)) {\n DLY_ms(5);\n PD_update();\n }\n return(counter > 0);\n}\n\n// Get total number of PDOs (fixed and programmable)\nuint8_t PD_getPDONum(void) {\n return PD_control.SourcePDONum;\n}\n\n// Get number of fixed power PDOs\nuint8_t PD_getFixedNum(void) {\n return PD_control.SourcePDONum - PD_control.SourcePPSNum;\n}\n\n// Get number of programmable power PDOs\nuint8_t PD_getPPSNum(void) {\n return PD_control.SourcePPSNum;\n}\n\n// Get voltage of specified fixed power PDO\nuint16_t PD_getPDOVoltage(uint8_t pdonum) {\n return PD_control.FixedSourceCap[pdonum - 1].Voltage;\n}\n\n// Get minimum voltage of specified PDO (fixed and programmable)\nuint16_t PD_getPDOMinVoltage(uint8_t pdonum) {\n uint8_t ppspos = PD_control.SourcePDONum - PD_control.SourcePPSNum;\n if(pdonum <= ppspos)\n return PD_control.FixedSourceCap[pdonum - 1].Voltage;\n else return PD_control.PPSSourceCap[pdonum - ppspos - 1].MinVoltage;\n}\n\n// Get maximum voltage of specified PDO (fixed and programmable)\nuint16_t PD_getPDOMaxVoltage(uint8_t pdonum) {\n uint8_t ppspos = PD_control.SourcePDONum - PD_control.SourcePPSNum;\n if(pdonum <= ppspos)\n return PD_control.FixedSourceCap[pdonum - 1].Voltage;\n else return PD_control.PPSSourceCap[pdonum - ppspos - 1].MaxVoltage;\n}\n\n// Get max current of specified PDO (fixed and programmable)\nuint16_t PD_getPDOMaxCurrent(uint8_t pdonum) {\n uint8_t ppspos = PD_control.SourcePDONum - PD_control.SourcePPSNum;\n if(pdonum <= ppspos)\n return PD_control.FixedSourceCap[pdonum - 1].Current;\n else return PD_control.PPSSourceCap[pdonum - ppspos - 1].Current;\n}\n\n// Set specified PDO and voltage; returns 0:failed, 1:success\nuint8_t PD_setPDO(uint8_t pdonum, uint16_t voltage) {\n PD_control.SetPDONum = pdonum;\n PD_control.SetVoltage = voltage;\n return PD_negotiate();\n}\n\n// Set specified voltage (in millivolts) if available; returns 0:failed, 1:success\nuint8_t PD_setVoltage(uint16_t voltage) {\n uint8_t i;\n uint8_t ppspos = PD_control.SourcePDONum - PD_control.SourcePPSNum;\n for(i=0; i= voltage)) {\n return PD_setPDO(i + 1, voltage);\n }\n }\n }\n return 0;\n}\n\n// Get active PDO\nuint8_t PD_getPDO(void) {\n return PD_control.SetPDONum;\n}\n\n// Get active voltage\nuint16_t PD_getVoltage(void) {\n return PD_control.SetVoltage;\n}\n\n// Get active max current\nuint16_t PD_getCurrent(void) {\n uint8_t pdonum = PD_control.SetPDONum;\n uint8_t ppspos = PD_control.SourcePDONum - PD_control.SourcePPSNum;\n if(pdonum <= ppspos)\n return PD_control.FixedSourceCap[pdonum - 1].Current;\n else return PD_control.PPSSourceCap[pdonum - ppspos - 1].Current;\n}\n\n// Initialize PD registers and states, then connect\nuint8_t PD_connect(void) {\n RCC->APB2PCENR |= RCC_AFIOEN | RCC_IOPCEN;\n RCC->AHBPCENR |= RCC_USBPD;\n GPIOB->CFGHR = (GPIOB->CFGHR & ~( (uint32_t)0b1111<<(((14)&7)<<2) | (uint32_t)0b1111<<(((15)&7)<<2)))\n | ( (uint32_t)0b0100<<(((14)&7)<<2) | (uint32_t)0b0100<<(((15)&7)<<2));\n #ifdef USB_VDD\n #if USB_VDD > 0\n AFIO->CTLR |= USBPD_IN_HVT;\n #else\n AFIO->CTLR |= USBPD_IN_HVT | USBPD_PHY_V33;\n #endif\n #else\n RCC->APB1PCENR |= RCC_PWREN;\n PWR->CTLR |= PWR_CTLR_PLS;\n if(PWR->CSR & PWR_CSR_PVDO) AFIO->CTLR |= USBPD_IN_HVT | USBPD_PHY_V33;\n else AFIO->CTLR |= USBPD_IN_HVT;\n #endif\n\n USBPD->DMA = (uint32_t)PD_TR_buffer;\n USBPD->CONFIG = USBPD_IE_RX_ACT | USBPD_IE_RX_RESET | USBPD_IE_TX_END | USBPD_PD_DMA_EN;\n USBPD->STATUS = USBPD_BUF_ERR | USBPD_IF_RX_BIT | USBPD_IF_RX_BYTE \n | USBPD_IF_RX_ACT | USBPD_IF_RX_RESET | USBPD_IF_TX_END;\n return PD_negotiate();\n}\n\n// ===================================================================================\n// USB PD SINK Back End Functions\n// ===================================================================================\n\n// Enter reception mode\nvoid PD_RX_mode(void) {\n USBPD->BMC_CLK_CNT = USBPD_TMR_RX;\n USBPD->CONTROL = (USBPD->CONTROL & ~USBPD_PD_TX_EN) | USBPD_BMC_START;\n}\n\n// Reset PD\nvoid PD_reset(void) {\n USBPD->PORT_CC1 = USBPD_CC_CMP_66 | USBPD_CC_PD;\n USBPD->PORT_CC2 = USBPD_CC_CMP_66 | USBPD_CC_PD;\n PD_control.CC1_ConnectTimes = 0;\n PD_control.CC2_ConnectTimes = 0;\n PD_control.CC_NoneTimes = 0;\n PD_control.SourcePDONum = 0;\n PD_control.SourcePPSNum = 0;\n PD_control.FixedSourceCap = PD_SC_fixed;\n PD_control.PPSSourceCap = PD_SC_PPS;\n PD_control.CC_State = CC_IDLE;\n PD_control.CC_LastState = CC_IDLE;\n PD_control.SinkMessageID = 0;\n PD_control.SinkGoodCRCOver = 0;\n PD_control.SourceGoodCRCOver = 0;\n PD_control.PD_Version = USBPD_REVISION_20;\n PD_control.USBPD_READY = 0;\n PD_control.SetPDONum = 1;\n PD_control.LastSetPDONum = 1;\n PD_control.SetVoltage = 5000;\n PD_control.LastSetVoltage = 5000;\n}\n\n// Copy buffers\nvoid PD_memcpy(uint8_t* dest, const uint8_t* src, uint8_t n) {\n while(n--) *dest++ = *src++;\n}\n\n// Send PD data\nvoid PD_sendData(uint8_t length) {\n if((USBPD->CONFIG & USBPD_CC_SEL) == USBPD_CC_SEL) USBPD->PORT_CC2 |= USBPD_CC_LVE;\n else USBPD->PORT_CC1 |= USBPD_CC_LVE;\n\n USBPD->BMC_CLK_CNT = USBPD_TMR_TX;\n USBPD->TX_SEL = USBPD_TX_SOP0;\n USBPD->BMC_TX_SZ = length;\n USBPD->STATUS = 0;\n USBPD->CONTROL |= USBPD_BMC_START | USBPD_PD_TX_EN;\n}\n\n// Detect CC connection; returns 0:No connection, 1:CC1 connection, 2:CC2 connection\nuint8_t PD_checkCC(void) {\n uint8_t ccLine = USBPD_CCNONE;\n\n USBPD->PORT_CC1 &= ~(USBPD_CC_CE | USBPD_PA_CC_AI);\n USBPD->PORT_CC1 |= USBPD_CC_CMP_22;\n if(USBPD->PORT_CC1 & USBPD_PA_CC_AI) ccLine = USBPD_CC1;\n\n USBPD->PORT_CC2 &= ~(USBPD_CC_CE | USBPD_PA_CC_AI);\n USBPD->PORT_CC2 |= USBPD_CC_CMP_22;\n if(USBPD->PORT_CC2 & USBPD_PA_CC_AI) ccLine = USBPD_CC2;\n\n return ccLine;\n}\n\nvoid PD_PDO_analyze(void) {\n USBPD_PDO_t test;\n PD_control.SourcePPSNum = 0;\n\n for(uint8_t i=0; i (PD_control.SourcePDONum - PD_control.SourcePPSNum)) {\n pdo.SinkPPSRDO.ObjectPosition = pdoNum;\n pdo.SinkPPSRDO.OutputVoltageIn20mVunits = PD_control.SetVoltage / 20;\n pdo.SinkPPSRDO.OperatingCurrentIn50mAunits = PD_SC_PPS[pdoNum+PD_control.SourcePPSNum-PD_control.SourcePDONum-1].Current/50;\n pdo.SinkPPSRDO.NoUSBSuspend = 1u;\n pdo.SinkPPSRDO.USBCommunicationsCapable = 1u;\n }\n else {\n pdo.SinkFixedVariableRDO.ObjectPosition = pdoNum;\n pdo.SinkFixedVariableRDO.MaxOperatingCurrent10mAunits = PD_SC_fixed[pdoNum-1].Current/10;\n pdo.SinkFixedVariableRDO.OperatingCurrentIn10mAunits = PD_SC_fixed[pdoNum-1].Current/10;\n pdo.SinkFixedVariableRDO.USBCommunicationsCapable = 1u;\n pdo.SinkFixedVariableRDO.NoUSBSuspend = 1u;\n }\n\n *(uint16_t*)&PD_TR_buffer[0] = mh.d16;\n *(uint32_t*)&PD_TR_buffer[2] = pdo.d32;\n PD_sendData(6);\n}\n\nvoid PD_process(void) {\n cc_state_t temp = PD_control.CC_State;\n USBPD_MessageHeader_t mh;\n\n switch (PD_control.CC_State) {\n\n case CC_IDLE:\n NVIC_DisableIRQ(USBPD_IRQn); \n PD_reset();\n PD_control.CC_State = CC_CHECK_CONNECT;\n break;\n\n case CC_CHECK_CONNECT:\n break;\n\n case CC_CONNECT:\n if(PD_control.CC_LastState != PD_control.CC_State) {\n PD_RX_mode();\n NVIC_SetPriority(USBPD_IRQn, 0x00);\n NVIC_EnableIRQ(USBPD_IRQn); \n }\n break;\n\n case CC_SOURCE_CAP:\n if(PD_control.SinkGoodCRCOver) {\n PD_control.SinkGoodCRCOver = 0;\n NVIC_DisableIRQ(USBPD_IRQn);\n PD_PDO_analyze();\n NVIC_EnableIRQ(USBPD_IRQn);\n PD_control.CC_State = CC_SEND_REQUEST;\n }\n break;\n\n case CC_SEND_REQUEST:\n if(PD_control.CC_LastState != PD_control.CC_State) {\n PD_PDO_request();\n }\n if(PD_control.SourceGoodCRCOver) {\n PD_control.SourceGoodCRCOver = 0;\n PD_control.CC_State = CC_WAIT_ACCEPT;\n }\n break;\n\n case CC_WAIT_PS_RDY:\n break;\n\n case CC_PS_RDY:\n if(PD_control.SinkGoodCRCOver) {\n PD_control.SinkGoodCRCOver = 0;\n PD_control.CC_State = CC_GET_SOURCE_CAP;\n PD_control.WaitTime = 0;\n }\n break;\n\n case CC_GET_SOURCE_CAP:\n PD_control.USBPD_READY = 1; \n if((PD_control.SetPDONum != PD_control.LastSetPDONum) ||\n (PD_control.SetVoltage != PD_control.LastSetVoltage)) {\n PD_control.LastSetPDONum = PD_control.SetPDONum;\n PD_control.LastSetVoltage = PD_control.SetVoltage;\n PD_control.USBPD_READY = 0; \n\n mh.d16 = 0u;\n mh.MessageHeader.MessageID = PD_control.SinkMessageID;\n mh.MessageHeader.MessageType = USBPD_CONTROL_MSG_GET_SRC_CAP;\n mh.MessageHeader.NumberOfDataObjects = 0u;\n mh.MessageHeader.SpecificationRevision = PD_control.PD_Version;\n *(uint16_t*)&PD_TR_buffer[0] = mh.d16;\n PD_sendData(2);\n PD_control.CC_State = CC_GET_SOURCE_CAP+1;\n }\n break;\n\n default:\n break;\n }\n PD_control.CC_LastState = temp;\n}\n\nvoid PD_update(void) {\n uint8_t ccLine = PD_checkCC();\n PD_control.WaitTime++;\n\n if(PD_control.CC_State == CC_CHECK_CONNECT) {\n if(ccLine == USBPD_CC1) {\n PD_control.CC2_ConnectTimes = 0;\n PD_control.CC1_ConnectTimes++;\n if(PD_control.CC1_ConnectTimes > 5) {\n PD_control.CC1_ConnectTimes = 0;\n PD_control.CC_State = CC_CONNECT;\n USBPD->CONFIG &= ~USBPD_CC_SEL;\n }\n }\n else if(ccLine == USBPD_CC2) {\n PD_control.CC1_ConnectTimes = 0;\n PD_control.CC2_ConnectTimes++;\n if(PD_control.CC2_ConnectTimes > 5) {\n PD_control.CC2_ConnectTimes = 0;\n PD_control.CC_State = CC_CONNECT;\n USBPD->CONFIG |= USBPD_CC_SEL;\n }\n }\n else {\n PD_control.CC1_ConnectTimes = 0;\n PD_control.CC2_ConnectTimes = 0;\n }\n }\n\n if(PD_control.CC_State > CC_CHECK_CONNECT) {\n if(ccLine == USBPD_CCNONE) {\n PD_control.CC_NoneTimes++;\n if(PD_control.CC_NoneTimes > 5) {\n PD_control.CC_NoneTimes = 0;\n PD_control.CC_State = CC_IDLE;\n NVIC_DisableIRQ(USBPD_IRQn); \n }\n } \n else PD_control.CC_NoneTimes = 0; \n }\n\n PD_process();\n}\n\n// Analyze received data\nvoid PD_RX_analyze(void) {\n uint8_t sendGoodCRCFlag = 1;\n USBPD_MessageHeader_t mh;\n mh.d16 = *(uint16_t*)PD_TR_buffer;\n\n if(mh.MessageHeader.Extended == 0u) {\n if(mh.MessageHeader.NumberOfDataObjects == 0u) {\n switch(mh.MessageHeader.MessageType) {\n\n case USBPD_CONTROL_MSG_GOODCRC:\n sendGoodCRCFlag = 0;\n PD_control.SourceGoodCRCOver = 1;\n PD_control.SinkMessageID++;\n break;\n\n case USBPD_CONTROL_MSG_ACCEPT:\n PD_control.CC_State = CC_WAIT_PS_RDY;\n break;\n\n case USBPD_CONTROL_MSG_PS_RDY:\n PD_control.CC_State = CC_PS_RDY;\n break;\n\n default:\n break;\n }\n }\n else {\n switch(mh.MessageHeader.MessageType) {\n\n case USBPD_DATA_MSG_SRC_CAP:\n PD_control.CC_State = CC_SOURCE_CAP;\n PD_control.SourcePDONum = mh.MessageHeader.NumberOfDataObjects;\n PD_control.PD_Version = mh.MessageHeader.SpecificationRevision;\n PD_memcpy(PD_SC_buffer, &PD_TR_buffer[2], 28);\n break;\n\n default:\n break;\n }\n }\n }\n\n if(sendGoodCRCFlag) {\n DLY_us(30);\n PD_control.SinkGoodCRCOver = 0;\n USBPD_MessageHeader_t my_mh;\n my_mh.d16 = 0u;\n my_mh.MessageHeader.MessageID = mh.MessageHeader.MessageID;\n my_mh.MessageHeader.MessageType = USBPD_CONTROL_MSG_GOODCRC;\n my_mh.MessageHeader.SpecificationRevision = PD_control.PD_Version;\n *(uint16_t*)&PD_TR_buffer[0] = my_mh.d16;\n PD_sendData(2);\n } \n}\n\n// ===================================================================================\n// USB PD Interrupt Service Routine\n// ===================================================================================\nvoid USBPD_IRQHandler(void) __attribute__((interrupt));\nvoid USBPD_IRQHandler(void) {\n\n // Receive complete interrupt\n if(USBPD->STATUS & USBPD_IF_RX_ACT) {\n if((USBPD->STATUS & USBPD_BMC_AUX) == USBPD_BMC_AUX_SOP0) {\n if(USBPD->BMC_BYTE_CNT >= 6) {\n PD_RX_analyze();\n }\n }\n USBPD->STATUS |= USBPD_IF_RX_ACT;\n }\n\n // Transmit complete interrupt (GoodCRC only)\n if(USBPD->STATUS & USBPD_IF_TX_END) {\n USBPD->PORT_CC1 &= ~USBPD_CC_LVE;\n USBPD->PORT_CC2 &= ~USBPD_CC_LVE;\n PD_RX_mode();\n PD_control.SinkGoodCRCOver = 1;\n USBPD->STATUS |= USBPD_IF_TX_END;\n }\n\n // Reset interrupt\n if(USBPD->STATUS & USBPD_IF_RX_RESET) {\n USBPD->STATUS |= USBPD_IF_RX_RESET;\n PD_reset();\n }\n}\n" }, { "path": "software/pd_tester/src/usbpd_sink.h", "content": "// ===================================================================================\n// USB PD SINK Handler for CH32X035 * v1.5 *\n// ===================================================================================\n//\n// Functions available:\n// --------------------\n// PD_connect() Initialize USB-PD and connect, returns 0 if failed\n// PD_negotiate() Negotiate current settings, returns 0 if failed\n// PD_setVoltage(mV) Request specified voltage in millivolts, returns 0 if failed\n//\n// PD_getPDONum() Get total number of PDOs\n// PD_getFixedNum() Get number of fixed power PDOs\n// PD_getPPSNum() Get number of programmable power PDOs \n//\n// PD_getPDOVoltage(p) Get voltage of specified fixed power PDO (1..PD_getFixedNum())\n// PD_getPDOMinVoltage(p) Get min voltage of specified PDO (p = 1..PD_getPDONum())\n// PD_getPDOMaxVoltage(p) Get max voltage of specified PDO (p = 1..PD_getPDONum())\n// PD_getPDOMaxCurrent(p) Get max current of specified PDO (p = 1..PD_getPDONum())\n//\n// PD_getPDO() Get active PDO\n// PD_getVoltage() Get active voltage\n// PD_getCurrent() Get active max current\n//\n// Reference: https://github.com/openwch/ch32x035\n// 2023 by Stefan Wagner: https://github.com/wagiminator\n\n#pragma once\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"config.h\"\n#include \"system.h\"\n#include \"usbpd.h\"\n\n// ===================================================================================\n// Parameters and Checks\n// ===================================================================================\n#if SYS_USE_VECTORS == 0\n #error Interrupt vector table must be enabled (SYS_USE_VECTORS in system.h)!\n#endif\n\n#if F_CPU == 48000000\n #define USBPD_TMR_TX (80-1) // timer value for USB PD BMC TX @ F_CPU=48MHz\n #define USBPD_TMR_RX (120-1) // timer value for USB PD BMC RX @ F_CPU=48MHz\n#elif F_CPU == 24000000\n #define USBPD_TMR_TX (40-1) // timer value for USB PD BMC TX @ F_CPU=24MHz\n #define USBPD_TMR_RX (60-1) // timer value for USB PD BMC RX @ F_CPU=24MHz\n#elif F_CPU == 12000000\n #define USBPD_TMR_TX (20-1) // timer value for USB PD BMC TX @ F_CPU=12MHz\n #define USBPD_TMR_RX (30-1) // timer value for USB PD BMC RX @ F_CPU=12MHz\n#elif F_CPU == 6000000\n #define USBPD_TMR_TX (10-1) // timer value for USB PD BMC TX @ F_CPU=6MHz\n #define USBPD_TMR_RX (15-1) // timer value for USB PD BMC RX @ F_CPU=6MHz\n#else\n #error Unsupported system frequency for USBPD!\n#endif\n\n// ===================================================================================\n// Type defines\n// ===================================================================================\ntypedef struct {\n uint16_t Current;\n uint16_t Voltage;\n} FixedSourceCap_t;\n\ntypedef struct {\n uint16_t MinVoltage;\n uint16_t MaxVoltage;\n uint16_t Current;\n} PPSSourceCap_t;\n\ntypedef enum {\n CC_IDLE = 0u,\n CC_CHECK_CONNECT,\n CC_CONNECT,\n CC_SOURCE_CAP,\n CC_SEND_REQUEST,\n CC_WAIT_ACCEPT,\n CC_ACCEPT,\n CC_WAIT_PS_RDY,\n CC_PS_RDY,\n CC_GET_SOURCE_CAP,\n} cc_state_t;\n\ntypedef struct {\n volatile cc_state_t CC_State;\n volatile cc_state_t CC_LastState;\n volatile uint8_t CC_NoneTimes;\n volatile uint8_t CC1_ConnectTimes;\n volatile uint8_t CC2_ConnectTimes;\n FixedSourceCap_t* FixedSourceCap;\n PPSSourceCap_t* PPSSourceCap;\n volatile uint8_t SourcePDONum;\n volatile uint8_t SourcePPSNum;\n volatile uint8_t PD_Version;\n volatile uint16_t WaitTime;\n volatile uint8_t SetPDONum;\n volatile uint8_t LastSetPDONum;\n volatile uint16_t SetVoltage;\n volatile uint16_t LastSetVoltage;\n volatile uint8_t USBPD_READY;\n volatile uint8_t SourceMessageID;\n volatile uint8_t SinkMessageID;\n volatile uint8_t SinkGoodCRCOver;\n volatile uint8_t SourceGoodCRCOver;\n} pd_control_t;\n\n// ===================================================================================\n// Functions\n// ===================================================================================\nuint8_t PD_connect(void); // Initialize PD and connect\nuint8_t PD_negotiate(void); // Negotiate current settings\nuint8_t PD_setVoltage(uint16_t voltage); // Set specified voltage (in millivolts)\n\nuint8_t PD_getPDONum(void); // Get total number of PDOs\nuint8_t PD_getFixedNum(void); // Get number of fixed power PDOs\nuint8_t PD_getPPSNum(void); // Get number of programmable power PDOs \n\nuint16_t PD_getPDOVoltage(uint8_t pdonum); // Get voltage of specified fixed power PDO\nuint16_t PD_getPDOMinVoltage(uint8_t pdonum); // Get minimum voltage of specified PDO\nuint16_t PD_getPDOMaxVoltage(uint8_t pdonum); // Get maximum voltage of specified PDO\nuint16_t PD_getPDOMaxCurrent(uint8_t pdonum); // Get max current of specified PDO\n\nuint8_t PD_getPDO(void); // Get active PDO\nuint16_t PD_getVoltage(void); // Get active voltage\nuint16_t PD_getCurrent(void); // Get active max current\n\nuint8_t PD_setPDO(uint8_t pdonum, uint16_t voltage); // Set specified PDO and voltage\n\n#ifdef __cplusplus\n}\n#endif\n" } ]