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Repository: CMU-SAFARI/SoftMC
Branch: master
Commit: 50b09a68f4ab
Files: 163
Total size: 1.6 MB
Directory structure:
gitextract_u_mc_d1s/
├── LICENSE
├── README.md
├── hw/
│ └── boards/
│ └── ML605/
│ ├── SoftMC.xise
│ ├── apply_patches.sh
│ ├── autoref_config.v
│ ├── instr_decoder.v
│ ├── instr_dispatcher.v
│ ├── instr_receiver.v
│ ├── ipcore_dir/
│ │ ├── instr_fifo.xco
│ │ ├── instr_fifo.xise
│ │ ├── pcie_endpoint.xco
│ │ ├── pcie_endpoint.xise
│ │ ├── rdback_fifo.xco
│ │ ├── rdback_fifo.xise
│ │ ├── riffa/
│ │ │ ├── async_fifo.v
│ │ │ ├── async_fifo_fwft.v
│ │ │ ├── axi_basic_rx.v
│ │ │ ├── axi_basic_rx_null_gen.v
│ │ │ ├── axi_basic_rx_pipeline.v
│ │ │ ├── axi_basic_top.v
│ │ │ ├── axi_basic_tx.v
│ │ │ ├── axi_basic_tx_pipeline.v
│ │ │ ├── axi_basic_tx_thrtl_ctl.v
│ │ │ ├── channel_128.v
│ │ │ ├── channel_32.v
│ │ │ ├── channel_64.v
│ │ │ ├── chnl_tester.v
│ │ │ ├── common_functions.v
│ │ │ ├── cross_domain_signal.v
│ │ │ ├── demux_1_to_n.v
│ │ │ ├── ff.v
│ │ │ ├── fifo_packer_128.v
│ │ │ ├── fifo_packer_32.v
│ │ │ ├── fifo_packer_64.v
│ │ │ ├── gtx_drp_chanalign_fix_3752_v6.v
│ │ │ ├── gtx_rx_valid_filter_v6.v
│ │ │ ├── gtx_tx_sync_rate_v6.v
│ │ │ ├── gtx_wrapper_v6.v
│ │ │ ├── interrupt.v
│ │ │ ├── interrupt_controller.v
│ │ │ ├── pcie_2_0_v6.v
│ │ │ ├── pcie_bram_top_v6.v
│ │ │ ├── pcie_bram_v6.v
│ │ │ ├── pcie_brams_v6.v
│ │ │ ├── pcie_clocking_v6.v
│ │ │ ├── pcie_endpoint.v
│ │ │ ├── pcie_gtx_v6.v
│ │ │ ├── pcie_pipe_lane_v6.v
│ │ │ ├── pcie_pipe_misc_v6.v
│ │ │ ├── pcie_pipe_v6.v
│ │ │ ├── pcie_reset_delay_v6.v
│ │ │ ├── pcie_upconfig_fix_3451_v6.v
│ │ │ ├── ram_1clk_1w_1r.v
│ │ │ ├── ram_2clk_1w_1r.v
│ │ │ ├── recv_credit_flow_ctrl.v
│ │ │ ├── reorder_queue.v
│ │ │ ├── reorder_queue_input.v
│ │ │ ├── reorder_queue_output.v
│ │ │ ├── riffa_adapter_v6_pcie_v2_5.v
│ │ │ ├── riffa_endpoint.v
│ │ │ ├── riffa_endpoint_128.v
│ │ │ ├── riffa_endpoint_32.v
│ │ │ ├── riffa_endpoint_64.v
│ │ │ ├── riffa_top_v6_pcie_v2_5.v
│ │ │ ├── rx_engine_128.v
│ │ │ ├── rx_engine_32.v
│ │ │ ├── rx_engine_64.v
│ │ │ ├── rx_engine_req.v
│ │ │ ├── rx_port_128.v
│ │ │ ├── rx_port_32.v
│ │ │ ├── rx_port_64.v
│ │ │ ├── rx_port_channel_gate.v
│ │ │ ├── rx_port_reader.v
│ │ │ ├── rx_port_requester_mux.v
│ │ │ ├── sg_list_reader_128.v
│ │ │ ├── sg_list_reader_32.v
│ │ │ ├── sg_list_reader_64.v
│ │ │ ├── sg_list_requester.v
│ │ │ ├── sync_fifo.v
│ │ │ ├── syncff.v
│ │ │ ├── translation_layer.v
│ │ │ ├── translation_layer_128.v
│ │ │ ├── translation_layer_32.v
│ │ │ ├── translation_layer_64.v
│ │ │ ├── tx_engine_128.v
│ │ │ ├── tx_engine_32.v
│ │ │ ├── tx_engine_64.v
│ │ │ ├── tx_engine_formatter_128.v
│ │ │ ├── tx_engine_formatter_32.v
│ │ │ ├── tx_engine_formatter_64.v
│ │ │ ├── tx_engine_lower_128.v
│ │ │ ├── tx_engine_lower_32.v
│ │ │ ├── tx_engine_lower_64.v
│ │ │ ├── tx_engine_selector.v
│ │ │ ├── tx_engine_upper_128.v
│ │ │ ├── tx_engine_upper_32.v
│ │ │ ├── tx_engine_upper_64.v
│ │ │ ├── tx_port_128.v
│ │ │ ├── tx_port_32.v
│ │ │ ├── tx_port_64.v
│ │ │ ├── tx_port_buffer_128.v
│ │ │ ├── tx_port_buffer_32.v
│ │ │ ├── tx_port_buffer_64.v
│ │ │ ├── tx_port_channel_gate_128.v
│ │ │ ├── tx_port_channel_gate_32.v
│ │ │ ├── tx_port_channel_gate_64.v
│ │ │ ├── tx_port_monitor_128.v
│ │ │ ├── tx_port_monitor_32.v
│ │ │ ├── tx_port_monitor_64.v
│ │ │ ├── tx_port_writer.v
│ │ │ ├── tx_qword_aligner_128.v
│ │ │ └── tx_qword_aligner_64.v
│ │ ├── xilinx_mig/
│ │ │ ├── example_design/
│ │ │ │ └── mig.prj
│ │ │ └── user_design/
│ │ │ └── mig.prj
│ │ ├── xilinx_mig.xco
│ │ └── xilinx_mig.xise
│ ├── iseq_dispatcher.v
│ ├── maint_ctrl.v
│ ├── maint_handler.v
│ ├── patches/
│ │ ├── iodelay_ctrl.patch
│ │ ├── phy_rdctrl_sync.patch
│ │ ├── phy_read.patch
│ │ └── phy_top.patch
│ ├── pipe_reg.v
│ ├── read_capturer.v
│ ├── softMC.inc
│ ├── softMC.v
│ ├── softMC_constraints.ucf
│ ├── softMC_pcie_app.v
│ ├── softMC_top.v
│ └── tb_softMC_top.v
├── prebuilt/
│ ├── SoftMC.bit
│ └── SoftMC_RetentionTest
└── sw/
├── RetentionTest/
│ ├── Makefile
│ └── RetentionTest.cpp
├── SoftMC_API/
│ ├── softmc.cpp
│ └── softmc.h
└── riffa_2.1/
├── LICENSE
├── README.txt
└── driver/
├── linux/
│ ├── Makefile
│ ├── README.txt
│ ├── circ_queue.c
│ ├── circ_queue.h
│ ├── riffa.c
│ ├── riffa.h
│ ├── riffa_driver.c
│ └── riffa_driver.h
└── windows/
├── README.txt
├── dirs
├── install/
│ ├── install.bat
│ ├── license.txt
│ └── win7.iss
├── sys/
│ ├── makefile
│ ├── makefile.inc
│ ├── precomp.h
│ ├── riffa.c
│ ├── riffa.inx
│ ├── riffa.rc
│ ├── riffa_driver.h
│ ├── riffa_private.h
│ ├── sources
│ └── trace.h
└── win7install.bat
================================================
FILE CONTENTS
================================================
================================================
FILE: LICENSE
================================================
Copyright (c) [2017] [SAFARI Research Group at Carnegie Mellon University and ETH Zurich]
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
================================================
FILE: README.md
================================================
## [DRAM Bender](https://github.com/CMU-SAFARI/DRAM-Bender) (a.k.a. SoftMC v2) supersedes SoftMC. We suggest that you use DRAM Bender instead of SoftMC.
# SoftMC v1.0
SoftMC is an experimental FPGA-based memory controller design that could be used to develop tests for DDR3 SODIMMs. SoftMC currently supports only the *Xilinx ML605* board. Soon, we will port SoftMC on other popularly used boards (e.g., *Xilinx VC709*).
A paper describing SoftMC in detail is published at HPCA 2017 and is available here:
>*Hasan Hassan, Nandita Vijaykumar, Samira Khan, Saugata Ghose, Kevin Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, and Onur Mutlu,*
**"[SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies](https://people.inf.ethz.ch/omutlu/projects.htm)"**
*Proceedings of the 23rd International Symposium on High-Performance Computer Architecture (HPCA), Austin, TX, USA, February 2017.*
If you use or build on SoftMC, please cite that paper.
We provide a) prebuilt binaries for quick installation and b) the source
code (both in Verilog and C++) that you could modify as you wish.
## Prerequisites:
- A Xilinx ML605 FPGA or other compatible board (We only tested ML605)
- A Linux Host Machine, (We have tested on Ubuntu 12.04/14.04)
- SoftMC uses an 8-lane PCIe interface to communicate with the Host Machine.
So, you would also need to attach the board to the 8x/16x PCIe slot on the
motherboard of the Host Machine
- Single Rank DDR3 SODIMM attached to your FPGA board
- Xilinx ISE 14.6 (in case you want to build your own bitfile from the
source)
## Installation Guide:
### 1) Installing the RIFFA driver:
You need to have [RIFFA](http://riffa.ucsd.edu) driver installed on your system to enable
the communication with the FPGA via the PCIe bus. Do not forget to attach
your FPGA board to a PCIe slot.
First switch to the directory of the source files of the RIFFA driver:
```$ cd sw/riffa_2.1/driver/linux```
Then run make to build the driver
```$ make```
Then install the driver to your system
```$ sudo make install```
### 2) Creating and Downloading the SoftMC bitfile to the FPGA:
**a) Quick Installation using Prebuilt Binaries**
You will find all that you need inside "prebuilt" folder
(including an executable for the Retention Time test).
- You need to download the bitfile into your FPGA using an appropriate tool
(Xilinx *Impact* does the job for ML605)
- After restarting the machine that the FPGA is connected to via PCIe, you
should be able to run the Retention Time test application by typing to
command below:
```$ ./SoftMC_RetentionTime [Target Retention Time in milliseconds]```
**b) Installation from the Source Code**
Generating the SoftMC bitfile is straightforward:
- Use Xilinx ISE 14.6 to open the project, which is located located at *hw/boards/ML605/SoftMC.xise*. Ignore *missing files* pop-up windows by clicking the "Cancel" button. The missing files will be generated once the steps below are followed.
- Double-click on *xilinx_mig* IPCore file to open Memory Interface Generator's (MIG) configuration window. Keep clicking the "Next" button until the windows closes. Doing this will generate the necessary files required by SoftMC in ```hw/boards/ML605/ipcore_dir/xilinx_mig```.
- Open a terminal and go to hw/boards/ML605. Run:
```$ sh apply_patches.sh```
This will apply modifications to the files generated by MIG.
- Go back to Xilinx ISE and click "Generate Programming File" and then click "Yes" on the dialogs
that ask for IPCore to be compiled
- If you get the following error during synthesis:
`hw/boards/ML605/ipcore_dir/pcie_endpoint/source/gtx_wrapper_v6.v" Line
277: Instantiating <GTX_DRP_CHANALIGN_FIX_3752> from unknown module
<GTX_DRP_CHANALIGN_FIX_3752_V6>`
1. Add `` `include "gtx_drp_chanalign_fix_3752_v6.v" `` before the module
declaration in `` "gtx_wrapper_v6.v" ``. Save the file.
2. Comment-out the line that you have just added. Save the file again.
3. Click Synthesize again
The error occurs due to a bug in Xilinx ISE software. A workaround for it
is doing the steps that we listed above.
- After the operation completes successfully, you will find the generated
bitfile in the project folder
- Then follow the steps in **a)**
*(Where necessary to simulate the SoftMC hardware, we provide a sample testbench module ("tb_softMC_top.v") that you can start with. To enable simulation, you will need to uncomment the SIM definition in "softMC.inc". This will change the I/O interface of the top module to exclude the PCIe signals and let you easily issue instructions to SoftMC)*
To compile the sample application (retention time test) that we provide:
```
$ cd sw/RetentionTest
$ make
$ ./SoftMC_RetentionTest [Target Retention Time in milliseconds]
```
## Known Issues:
- Multi Rank SODIMMs are currently not supported.
- An instruction sequence could consist maximum of 8192 instructions (see our HPCA 2017 paper for details).
- Motherboards with B75 Chipset seems to be incompatible with ML605's PCIe endpoint.
You are welcome to contribute to the project. If you find/solve any issues
or port SoftMC to a new FPGA board, please contact the people below.
## Contacts:
Hasan Hassan (hhasan [at] inf [dot] ethz [dot] ch)
================================================
FILE: hw/boards/ML605/SoftMC.xise
================================================
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
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<file xil_pn:name="ipcore_dir/rdback_fifo.xco" xil_pn:type="FILE_COREGEN">
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<file xil_pn:name="ipcore_dir/pcie_endpoint.xco" xil_pn:type="FILE_COREGEN">
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<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_softMC_top/u_comp_ddr3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.ddr3_model" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="98" xil_pn:valueState="non-default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.ddr3_model" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-1" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Address for Fallback Configuration virtex6" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="30" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Board for Hardware Co-Simulation" xil_pn:value="N/A" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/home/hasanh/Xilinx/14.6/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value virtex5" xil_pn:value="0x000000" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|tb_softMC_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-07-29T13:36:22" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="89468CDA7D01623370029767AE853482" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/softMC_top" xil_pn:name="softMC_constraints.ucf"/>
</bindings>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="softMC.inc" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="ipcore_dir/riffa/common_functions.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="ipcore_dir/xilinx_mig/user_design/sim/ddr3_model_parameters.vh" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
</project>
================================================
FILE: hw/boards/ML605/apply_patches.sh
================================================
for f in ./patches/*.patch
do
patch -p0 < $f
done
================================================
FILE: hw/boards/ML605/autoref_config.v
================================================
`timescale 1ns / 1ps
//Hasan
module autoref_config(
input clk,
input rst,
input set_interval,
input[27:0] interval_in,
input set_trfc,
input[27:0] trfc_in,
output reg aref_en,
output reg[27:0] aref_interval,
output reg[27:0] trfc
);
always@(posedge clk) begin
if(rst) begin
aref_en <= 0;
aref_interval <= 0;
trfc <= 0;
end
else begin
if(set_interval) begin
aref_en <= |interval_in;
aref_interval <= interval_in;
end //set_interval
if(set_trfc) begin
trfc <= trfc_in;
end
end
end
endmodule
================================================
FILE: hw/boards/ML605/instr_decoder.v
================================================
`timescale 1ns / 1ps
`include "softMC.inc"
module instr_decoder #(parameter ROW_WIDTH = 15, BANK_WIDTH = 3, CS_WIDTH = 1)(
input en,
input[31:0] instr,
output reg[ROW_WIDTH - 1:0] dfi_address,
output reg[BANK_WIDTH - 1:0] dfi_bank,
output reg dfi_cas_n,
output reg[CS_WIDTH - 1:0] dfi_cs_n,
output reg dfi_ras_n,
output reg dfi_we_n
);
localparam LOW = 1'b0;
localparam HIGH = 1'b1;
always@* begin
dfi_address = {ROW_WIDTH{1'bx}};
dfi_bank = {BANK_WIDTH{1'bx}};
dfi_cas_n = HIGH;
dfi_cs_n = {CS_WIDTH{HIGH}};
dfi_ras_n = HIGH;
dfi_we_n = HIGH;
if(en) begin
dfi_address = instr[ROW_WIDTH - 1:0];
dfi_bank = instr[`ROW_OFFSET +: BANK_WIDTH];
dfi_we_n = instr[`WE_OFFSET];
dfi_cas_n = instr[`CAS_OFFSET];
dfi_ras_n = instr[`RAS_OFFSET];
dfi_cs_n = instr[`CS_OFFSET +: CS_WIDTH];
end //en
end
endmodule
================================================
FILE: hw/boards/ML605/instr_dispatcher.v
================================================
`timescale 1ns / 1ps
`include "softMC.inc"
module instr_dispatcher #(parameter ROW_WIDTH = 15, BANK_WIDTH = 3, CKE_WIDTH = 1, RANK_WIDTH = 1,
CS_WIDTH = 1, nCS_PER_RANK = 1, DQ_WIDTH = 64) (
input clk,
input rst,
input periodic_read_lock,
//There are two instructions queues to fetch from. Since PHY issues DDR commands at both pos and neg edges,
//we dispatch two instructions in the same cycle, running at half of the frequency of the DDR bus
input en_in0,
output en_ack0,
input[31:0] instr_in0,
input en_in1,
output en_ack1,
input[31:0] instr_in1,
//DFI Interface
// DFI Control/Address
input dfi_ready,
output[ROW_WIDTH-1:0] dfi_address0,
output[ROW_WIDTH-1:0] dfi_address1,
output[BANK_WIDTH-1:0] dfi_bank0,
output[BANK_WIDTH-1:0] dfi_bank1,
output dfi_cke0,
output dfi_cke1,
output dfi_cas_n0,
output dfi_cas_n1,
output[CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n0,
output[CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n1,
output[CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt0,
output[CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt1,
output dfi_ras_n0,
output dfi_ras_n1,
output dfi_we_n0,
output dfi_we_n1,
// DFI Write
output reg dfi_wrdata_en,
output [4*DQ_WIDTH-1:0] dfi_wrdata,
output [4*(DQ_WIDTH/8)-1:0] dfi_wrdata_mask,
// DFI Read
output reg dfi_rddata_en,
output reg dfi_rddata_en_even,
output reg dfi_rddata_en_odd,
//Bus Command
output reg io_config_strobe,
output reg[1:0] io_config,
//Misc.
output pr_rd_ack,
//auto-refresh
output reg aref_set_interval,
output reg[27:0] aref_interval,
output reg aref_set_trfc,
output reg[27:0] aref_trfc
);
localparam ONE = 1;
localparam TWO = 2;
localparam HIGH = 1'b1;
localparam LOW = 1'b0;
reg[9:0] wait_cycles_r = ONE[0 +: 10], wait_cycles_ns;
reg read_burst_r, read_burst_ns;
reg read_burst_even_r, read_burst_even_ns;
reg read_burst_odd_r, read_burst_odd_ns;
reg write_burst_r, write_burst_ns;
reg[7:0] write_burst_data_r, write_burst_data_ns;
reg bus_write, bus_write_r;
reg pr_rd_ack_r, pr_rd_ack_ns;
reg ack0, ack1;
reg instr_src_r, instr_src_ns;
reg dec0_en;
wire[31:0] dec0_instr;
reg dec1_en;
wire[31:0] dec1_instr;
wire en0 = instr_src_r ? en_in1 : en_in0;
wire[31:0] instr0 = instr_src_r ? instr_in1 : instr_in0;
assign en_ack0 = instr_src_r ? ack1 : ack0;
wire en1 = instr_src_r ? en_in0 : en_in1;
wire[31:0] instr1 = instr_src_r ? instr_in0 : instr_in1;
assign en_ack1 = instr_src_r ? ack0 : ack1;
assign dec0_instr = instr0;
assign dec1_instr = instr1;
reg block_other_slot;
reg cke0, cke0_r, cke1, cke1_r;
//auto-refresh
reg aref_set_interval_ns, aref_set_trfc_ns;
reg[27:0] aref_interval_ns, aref_trfc_ns;
//Counter saturating at zero
reg load_counter;
always@(posedge clk) begin
if(rst)
wait_cycles_r <= 10'd0;
else begin
if(load_counter) begin
wait_cycles_r <= wait_cycles_ns;
end //load_counter
else begin
if(|wait_cycles_r[9:1])
wait_cycles_r <= wait_cycles_r - TWO[0 +: 10];
else
wait_cycles_r <= 10'd0;
end
end
end
always@* begin
io_config_strobe = LOW;
io_config = 2'b00;
bus_write = bus_write_r;
instr_src_ns = ~(en_in0 | en_in1) ? LOW : instr_src_r;
ack0 = HIGH;
ack1 = HIGH;
dec0_en = LOW;
dec1_en = LOW;
read_burst_ns = LOW;
read_burst_even_ns = LOW;
read_burst_odd_ns = LOW;
write_burst_ns = LOW;
write_burst_data_ns = write_burst_data_r;
dfi_rddata_en = read_burst_r;
dfi_rddata_en_even = read_burst_even_r;
dfi_rddata_en_odd = read_burst_odd_r;
dfi_wrdata_en = write_burst_r;
pr_rd_ack_ns = LOW;
aref_set_interval_ns = 1'b0;
aref_interval_ns = {28{1'bx}};
aref_set_trfc_ns = 1'b0;
aref_trfc_ns = {28{1'bx}};
wait_cycles_ns = 10'dx;
load_counter = LOW;
block_other_slot = LOW;
cke0 = cke0_r;
cke1 = cke1_r;
if(dfi_ready & (wait_cycles_r <= 10'd1)) begin
if(en0) begin
casex(instr0[31:28])
`SET_BUSDIR: begin
io_config_strobe = HIGH;
io_config = instr0[1:0];
if(instr0[1:0] == `BUS_DIR_WRITE)
bus_write = 1'b1;
else
bus_write = 1'b0;
end //SET_BUSDIR
`DDR_INSTR: begin
dec0_en = HIGH;
cke0 = instr0[`CKE_OFFSET];
if(~|instr0[`CS_OFFSET +: CS_WIDTH] && instr0[`RAS_OFFSET] && ~instr0[`CAS_OFFSET] &&
instr0[`WE_OFFSET] && cke0 && cke0_r) begin //check whether we have a read instruction
dfi_rddata_en = HIGH;
dfi_rddata_en_even = HIGH;
read_burst_ns = HIGH;
read_burst_even_ns = HIGH;
dfi_rddata_en_odd = periodic_read_lock; //to indicate periodic read response
read_burst_odd_ns = periodic_read_lock;
pr_rd_ack_ns = HIGH;
end
if(~|instr0[`CS_OFFSET +: CS_WIDTH] && instr0[`RAS_OFFSET] && ~instr0[`CAS_OFFSET] &&
~instr0[`WE_OFFSET] && cke0 && cke0_r) begin //check whether we have a write instruction
dfi_wrdata_en = HIGH;
write_burst_ns = HIGH;
write_burst_data_ns = {instr0[30:25], instr0[(`ROW_OFFSET - 1) -:2]};
end
end //DDR_INSTR
`WAIT: begin
load_counter = HIGH;
wait_cycles_ns = instr0[9:0] - 10'd1; //reducing by one for the second slot
if(instr0[9:0] > 10'd1)
block_other_slot = HIGH;
if(~instr0[0])
instr_src_ns = ~instr_src_r;
end //WAIT
`SET_TREFI: begin
aref_set_interval_ns = 1'b1;
aref_interval_ns = instr0[27:0];
end //SET_TREFI
`SET_TRFC: begin
aref_set_trfc_ns = 1'b1;
aref_trfc_ns = instr0[27:0];
end //SET_TRFC
endcase //instr0
end //en0
end
else begin
ack0 = LOW;
end
if(~(en0 & block_other_slot) & dfi_ready & (wait_cycles_r <= 10'd2)) begin
if(en1) begin
casex(instr1[31:28])
`SET_BUSDIR: begin
io_config_strobe = HIGH;
io_config = instr1[1:0];
if(instr1[1:0] == `BUS_DIR_WRITE)
bus_write = 1'b1;
else
bus_write = 1'b0;
end //SET_BUSDIR
`DDR_INSTR: begin
dec1_en = HIGH;
cke1 = instr1[`CKE_OFFSET];
if(~|instr1[`CS_OFFSET +: CS_WIDTH] && instr1[`RAS_OFFSET] && ~instr1[`CAS_OFFSET] &&
instr1[`WE_OFFSET] && cke1 && cke1_r) begin //check whether we have a read command
dfi_rddata_en = HIGH;
read_burst_ns = HIGH;
dfi_rddata_en_odd = periodic_read_lock; //to indicate periodic read response
read_burst_odd_ns = periodic_read_lock;
pr_rd_ack_ns = HIGH;
end
if(~|instr1[`CS_OFFSET +: CS_WIDTH] && instr1[`RAS_OFFSET] && ~instr1[`CAS_OFFSET] &&
~instr1[`WE_OFFSET] && cke1 && cke1_r) begin //check whether we have a write command
dfi_wrdata_en = HIGH;
write_burst_ns = HIGH;
write_burst_data_ns = {instr1[30:25], instr1[(`ROW_OFFSET - 1) -:2]};
end
end //DDR_INSTR
`WAIT: begin
wait_cycles_ns = instr1[9:0];
load_counter = HIGH;
if(~instr1[0])
instr_src_ns = ~instr_src_r;
end //WAIT
`SET_TREFI: begin
aref_set_interval_ns = 1'b1;
aref_interval_ns = instr1[27:0];
end //SET_TREFI
`SET_TRFC: begin
aref_set_trfc_ns = 1'b1;
aref_trfc_ns = instr1[27:0];
end //SET_TRFC
endcase //instr1
end //en1
end
else begin
ack1 = LOW;
end
end
instr_decoder #(.ROW_WIDTH(ROW_WIDTH), .BANK_WIDTH(BANK_WIDTH), .CS_WIDTH(CS_WIDTH)) instr_dec0(
.en(dec0_en),
.instr(dec0_instr),
.dfi_address(dfi_address0),
.dfi_bank(dfi_bank0),
.dfi_cas_n(dfi_cas_n0),
.dfi_cs_n(dfi_cs_n0),
.dfi_ras_n(dfi_ras_n0),
.dfi_we_n(dfi_we_n0)
);
instr_decoder #(.ROW_WIDTH(ROW_WIDTH), .BANK_WIDTH(BANK_WIDTH), .CS_WIDTH(CS_WIDTH)) i_instr_dec1(
.en(dec1_en),
.instr(dec1_instr),
.dfi_address(dfi_address1),
.dfi_bank(dfi_bank1),
.dfi_cas_n(dfi_cas_n1),
.dfi_cs_n(dfi_cs_n1),
.dfi_ras_n(dfi_ras_n1),
.dfi_we_n(dfi_we_n1)
);
assign dfi_wrdata_mask = 0;
assign dfi_wrdata = dfi_cas_n0 ? {4*(DQ_WIDTH/8){write_burst_data_r}} : {4*(DQ_WIDTH/8){write_burst_data_ns}};
always@(posedge clk) begin
pr_rd_ack_r <= pr_rd_ack_ns;
end
assign pr_rd_ack = pr_rd_ack_r;
always@(posedge clk) begin
if(rst) begin
aref_set_interval <= 0;
aref_set_trfc <= 0;
aref_interval <= 0;
aref_trfc <= 0;
cke0_r <= 1'b1; //not sure what would happen if the clock is disabled on reset
cke1_r <= 1'b1;
end
else begin
aref_set_interval <= aref_set_interval_ns;
aref_set_trfc <= aref_set_trfc_ns;
aref_interval <= aref_interval_ns;
aref_trfc <= aref_trfc_ns;
cke0_r <= cke0;
cke1_r <= cke1;
end
end
always@(posedge clk) begin
if(rst) begin
read_burst_r <= LOW;
read_burst_even_r <= LOW;
read_burst_odd_r <= LOW;
write_burst_r <= LOW;
write_burst_data_r <= 0;
bus_write_r <= LOW;
instr_src_r <= LOW;
end
else begin
read_burst_r <= read_burst_ns;
read_burst_even_r <= read_burst_even_ns;
read_burst_odd_r <= read_burst_odd_ns;
write_burst_r <= write_burst_ns;
write_burst_data_r <= write_burst_data_ns;
bus_write_r <= bus_write;
instr_src_r <= instr_src_ns;
end //!rst
end
assign dfi_odt0 = bus_write_r;
assign dfi_odt1 = bus_write_r;
assign dfi_cke0 = cke0_r;
assign dfi_cke1 = cke1_r;
endmodule
================================================
FILE: hw/boards/ML605/instr_receiver.v
================================================
`timescale 1ns / 1ps
`include "softMC.inc"
module instr_receiver (
input clk,
input rst,
input dispatcher_ready,
input app_en,
output reg app_ack,
input[31:0] app_instr,
input maint_en,
output reg maint_ack,
input[31:0] maint_instr,
output instr0_fifo_en,
output[31:0] instr0_fifo_data,
output instr1_fifo_en,
output[31:0] instr1_fifo_data,
output process_iseq
);
reg process_iseq_r = 1'b0, process_iseq_ns;
localparam STATE_IDLE = 2'b00;
localparam STATE_APP = 2'b01;
localparam STATE_MAINT = 2'b10;
reg[1:0] state_ns, state_r;
reg sel_fifo = 1'b0;
reg instr_en_ns, instr_en_r;
reg[31:0] instr_ns, instr_r;
always@* begin
process_iseq_ns = 1'b0;
state_ns = state_r;
instr_en_ns = 1'b0;
instr_ns = instr_r;
app_ack = 1'b0;
maint_ack = 1'b0;
case(state_r)
STATE_IDLE: begin
if(dispatcher_ready & ~process_iseq_r) begin
if(app_en) begin
state_ns = STATE_APP;
instr_en_ns = app_en;
instr_ns = app_instr;
app_ack = 1'b1;
end
else if(maint_en) begin
state_ns = STATE_MAINT;
instr_en_ns = maint_en;
instr_ns = maint_instr;
maint_ack = 1'b1;
end
end //dispatcher_ready
end //STATE_IDLE
STATE_APP: begin
app_ack = 1'b1;
instr_en_ns = app_en;
instr_ns = app_instr;
if(instr_en_ns & (instr_ns[31:28] == `END_ISEQ)) begin
process_iseq_ns = 1'b1;
state_ns = STATE_IDLE;
end
end //STATE_APP
STATE_MAINT: begin
maint_ack = 1'b1;
instr_en_ns = maint_en;
instr_ns = maint_instr;
if(instr_en_ns & (instr_ns[31:28] == `END_ISEQ)) begin
instr_en_ns = 1'b0;
process_iseq_ns = 1'b1;
state_ns = STATE_IDLE;
end
end //STATE_MAINT
endcase //state_r
end //always
assign instr0_fifo_en = ~sel_fifo & instr_en_r;
assign instr0_fifo_data = instr_r;
assign instr1_fifo_en = sel_fifo & instr_en_r;
assign instr1_fifo_data = instr_r;
always@(posedge clk) begin
if(rst) begin
process_iseq_r <= 1'b0;
sel_fifo <= 1'b0;
state_r <= STATE_IDLE;
instr_en_r <= 1'b0;
instr_r <= 0;
end
else begin
state_r <= state_ns;
process_iseq_r <= process_iseq_ns;
instr_en_r <= instr_en_ns;
instr_r <= instr_ns;
if(process_iseq_r)
sel_fifo <= 1'b0;
else if(instr_en_r)
sel_fifo <= ~sel_fifo;
end //!rst
end
assign process_iseq = process_iseq_r;
endmodule
================================================
FILE: hw/boards/ML605/ipcore_dir/instr_fifo.xco
================================================
##############################################################
#
# Xilinx Core Generator version 14.6
# Date: Fri Feb 3 17:08:40 2017
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6vlx240t
SET devicefamily = virtex6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff1156
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -1
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=instr_fifo
CSET data_count=false
CSET data_count_width=11
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=5
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Common_Clock_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=0
CSET full_threshold_assert_value=1023
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=1022
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=32
CSET input_depth=1024
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=32
CSET output_depth=1024
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=11
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Synchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=true
CSET use_extra_logic=true
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=11
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T12:39:56Z
# END Extra information
GENERATE
# CRC: 944578b5
================================================
FILE: hw/boards/ML605/ipcore_dir/instr_fifo.xise
================================================
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="instr_fifo.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="instr_fifo.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc6vlx240t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|instr_fifo" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="instr_fifo.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/instr_fifo" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="ff1156" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-1" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="instr_fifo" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-02-03T18:09:45" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B2426FF841A8837D23279412D806CBB4" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
================================================
FILE: hw/boards/ML605/ipcore_dir/pcie_endpoint.xco
================================================
##############################################################
#
# Xilinx Core Generator version 14.6
# Date: Fri Feb 3 17:11:58 2017
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:v6_pcie:2.5
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6vlx240t
SET devicefamily = virtex6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff1156
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -1
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Virtex-6_Integrated_Block_for_PCI_Express xilinx.com:ip:v6_pcie:2.5
# END Select
# BEGIN Parameters
CSET acceptable_l0s_latency=Maximum_of_64_ns
CSET acceptable_l1_latency=No_limit
CSET ack_nak_timeout_func=Absolute
CSET ack_nak_timeout_value=0000
CSET bar0_64bit=false
CSET bar0_enabled=true
CSET bar0_prefetchable=false
CSET bar0_scale=Kilobytes
CSET bar0_size=1
CSET bar0_type=Memory
CSET bar1_64bit=false
CSET bar1_enabled=false
CSET bar1_prefetchable=false
CSET bar1_scale=Kilobytes
CSET bar1_size=2
CSET bar1_type=N/A
CSET bar2_64bit=false
CSET bar2_enabled=false
CSET bar2_prefetchable=false
CSET bar2_scale=Bytes
CSET bar2_size=128
CSET bar2_type=N/A
CSET bar3_64bit=false
CSET bar3_enabled=false
CSET bar3_prefetchable=false
CSET bar3_scale=Kilobytes
CSET bar3_size=2
CSET bar3_type=N/A
CSET bar4_64bit=false
CSET bar4_enabled=false
CSET bar4_prefetchable=false
CSET bar4_scale=Kilobytes
CSET bar4_size=2
CSET bar4_type=N/A
CSET bar5_enabled=false
CSET bar5_prefetchable=false
CSET bar5_scale=Kilobytes
CSET bar5_size=2
CSET bar5_type=N/A
CSET base_class_menu=Simple_communication_controllers
CSET buf_opt_bma=true
CSET cardbus_cis_pointer=00000000
CSET class_code_base=05
CSET class_code_interface=00
CSET class_code_sub=00
CSET component_name=pcie_endpoint
CSET cost_table=1
CSET cpl_finite=false
CSET cpl_timeout_disable_sup=false
CSET cpl_timeout_range=Range_B
CSET d0_pme_support=true
CSET d0_power_consumed=0
CSET d0_power_consumed_factor=0
CSET d0_power_dissipated=0
CSET d0_power_dissipated_factor=0
CSET d1_pme_support=true
CSET d1_power_consumed=0
CSET d1_power_consumed_factor=0
CSET d1_power_dissipated=0
CSET d1_power_dissipated_factor=0
CSET d1_support=false
CSET d2_pme_support=true
CSET d2_power_consumed=0
CSET d2_power_consumed_factor=0
CSET d2_power_dissipated=0
CSET d2_power_dissipated_factor=0
CSET d2_support=false
CSET d3_power_consumed=0
CSET d3_power_consumed_factor=0
CSET d3_power_dissipated=0
CSET d3_power_dissipated_factor=0
CSET d3cold_pme_support=false
CSET d3hot_pme_support=true
CSET de_emph=0
CSET device_id=6018
CSET device_port_type=PCI_Express_Endpoint_device
CSET device_specific_initialization=false
CSET disable_tx_aspm_l0s=false
CSET dll_link_active_cap=false
CSET downstream_link_num=00
CSET dsn_enabled=true
CSET en_route_err_cor=false
CSET en_route_err_ftl=false
CSET en_route_err_nfl=false
CSET en_route_inta=false
CSET en_route_intb=false
CSET en_route_intc=false
CSET en_route_intd=false
CSET en_route_pm_pme=false
CSET en_route_pme_to=false
CSET en_route_pme_to_ack=false
CSET en_route_unlock=false
CSET enable_ack_nak_timer=false
CSET enable_lane_reversal=false
CSET enable_replay_timer=true
CSET enable_slot_clock_cfg=false
CSET expansion_rom_enabled=false
CSET expansion_rom_scale=Kilobytes
CSET expansion_rom_size=2
CSET ext_pci_cfg_space=false
CSET ext_pci_cfg_space_addr=3FF
CSET extended_tag_field=false
CSET force_no_scrambling=false
CSET hw_auton_spd_disable=false
CSET intx_generation=true
CSET io_base_limit_registers=Disabled
CSET legacy_interrupt=INTA
CSET link_speed=2.5_GT/s
CSET max_payload_size=512_bytes
CSET maximum_link_width=X8
CSET msi_64b=true
CSET msi_enabled=true
CSET msi_vec_mask=false
CSET msix_enabled=false
CSET msix_pba_bir=BAR_0
CSET msix_pba_offset=0
CSET msix_table_bir=BAR_0
CSET msix_table_offset=0
CSET msix_table_size=1
CSET multiple_message_capable=1_vector
CSET no_soft_reset=true
CSET pci_cfg_space=false
CSET pci_cfg_space_addr=3F
CSET pcie_blk_locn=X0Y0
CSET pcie_cap_slot_implemented=false
CSET pcie_debug_ports=false
CSET perf_level=High
CSET phantom_functions=No_function_number_bits_used
CSET pipe_pipeline=None
CSET prefetchable_memory_base_limit_registers=Disabled
CSET rcb=64_byte
CSET ref_clk_freq=100_MHz
CSET replay_timeout_func=Add
CSET replay_timeout_value=0026
CSET revision_id=00
CSET root_cap_crs=false
CSET slot_cap_attn_butn=false
CSET slot_cap_attn_ind=false
CSET slot_cap_elec_interlock=false
CSET slot_cap_hotplug_cap=false
CSET slot_cap_hotplug_surprise=false
CSET slot_cap_mrl=false
CSET slot_cap_no_cmd_comp_sup=false
CSET slot_cap_physical_slot_num=0
CSET slot_cap_pwr_ctrl=false
CSET slot_cap_pwr_ind=false
CSET slot_cap_pwr_limit_scale=0
CSET slot_cap_pwr_limit_value=0
CSET sub_class_interface_menu=Generic_XT_compatible_serial_controller
CSET subsystem_id=0007
CSET subsystem_vendor_id=10EE
CSET trans_buf_pipeline=None
CSET trgt_link_speed=4'h1
CSET trim_tlp_digest=false
CSET upconfigure_capable=true
CSET user_clk_freq=250_default
CSET vc_cap_enabled=false
CSET vc_cap_reject_snoop=false
CSET vendor_id=10EE
CSET vsec_enabled=false
CSET xlnx_ref_board=ML_605
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-06-08T22:50:04Z
# END Extra information
GENERATE
# CRC: 2cdb8933
================================================
FILE: hw/boards/ML605/ipcore_dir/pcie_endpoint.xise
================================================
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="pcie_endpoint/source/gtx_tx_sync_rate_v6.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="pcie_endpoint/source/gtx_wrapper_v6.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="pcie_endpoint/source/gtx_rx_valid_filter_v6.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="pcie_endpoint/source/pcie_upconfig_fix_3451_v6.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="pcie_endpoint/source/pcie_2_0_v6.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="pcie_endpoint/source/pcie_bram_top_v6.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="pcie_endpoint/source/pcie_bram_v6.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="pcie_endpoint/source/pcie_brams_v6.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="pcie_endpoint/source/pcie_clocking_v6.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="pcie_endpoint/source/pcie_gtx_v6.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="pcie_endpoint/source/pcie_pipe_lane_v6.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="pcie_endpoint/source/pcie_pipe_misc_v6.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="pcie_endpoint/source/pcie_pipe_v6.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="pcie_endpoint/source/pcie_reset_delay_v6.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="pcie_endpoint/source/axi_basic_tx_thrtl_ctl.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="pcie_endpoint/source/axi_basic_rx.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="pcie_endpoint/source/axi_basic_rx_null_gen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="pcie_endpoint/source/axi_basic_rx_pipeline.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="pcie_endpoint/source/axi_basic_tx_pipeline.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="pcie_endpoint/source/axi_basic_tx.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="pcie_endpoint/source/axi_basic_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="pcie_endpoint/source/pcie_endpoint.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="22"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc6vlx240t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|pcie_endpoint" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="pcie_endpoint/source/pcie_endpoint.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/pcie_endpoint" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="ff1156" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-1" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="pcie_endpoint" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-02-03T18:12:06" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="FB4B2F5BC38A2473FB9976AD51E006B7" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
================================================
FILE: hw/boards/ML605/ipcore_dir/rdback_fifo.xco
================================================
##############################################################
#
# Xilinx Core Generator version 14.6
# Date: Fri Feb 3 17:12:17 2017
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6vlx240t
SET devicefamily = virtex6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff1156
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -1
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=false
CSET almost_full_flag=true
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=rdback_fifo
CSET data_count=false
CSET data_count_width=11
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=5
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Common_Clock_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Block_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Block_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Block_RAM
CSET full_flags_reset_value=0
CSET full_threshold_assert_value=1023
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=1022
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=256
CSET input_depth=1024
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=256
CSET output_depth=1024
CSET overflow_flag=false
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=11
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Synchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=false
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=true
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=11
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T12:39:56Z
# END Extra information
GENERATE
# CRC: 38434af1
================================================
FILE: hw/boards/ML605/ipcore_dir/rdback_fifo.xise
================================================
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
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<file xil_pn:name="rdback_fifo.ngc" xil_pn:type="FILE_NGC">
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</project>
================================================
FILE: hw/boards/ML605/ipcore_dir/riffa/async_fifo.v
================================================
`timescale 1ns/1ns
//----------------------------------------------------------------------------
// This software is Copyright © 2012 The Regents of the University of
// California. All Rights Reserved.
//
// Permission to copy, modify, and distribute this software and its
// documentation for educational, research and non-profit purposes, without
// fee, and without a written agreement is hereby granted, provided that the
// above copyright notice, this paragraph and the following three paragraphs
// appear in all copies.
//
// Permission to make commercial use of this software may be obtained by
// contacting:
// Technology Transfer Office
// 9500 Gilman Drive, Mail Code 0910
// University of California
// La Jolla, CA 92093-0910
// (858) 534-5815
// invent@ucsd.edu
//
// This software program and documentation are copyrighted by The Regents of
// the University of California. The software program and documentation are
// supplied "as is", without any accompanying services from The Regents. The
// Regents does not warrant that the operation of the program will be
// uninterrupted or error-free. The end-user understands that the program was
// developed for research purposes and is advised not to rely exclusively on
// the program for any reason.
//
// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO
// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
// THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
// MODIFICATIONS.
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: async_fifo.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Asynchronous capable parameterized FIFO. As with all
// traditional FIFOs, the RD_DATA will be valid one cycle following a RD_EN
// assertion. RD_EMPTY will remain low until the cycle following the last RD_EN
// assertion. Note, that RD_EMPTY may actually be high on the same cycle that
// RD_DATA contains valid data.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
// Additional Comments: Based on design by CE Cummings in Simulation and
// Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer
// Comparisons
//-----------------------------------------------------------------------------
module async_fifo #(
parameter C_WIDTH = 32, // Data bus width
parameter C_DEPTH = 1024, // Depth of the FIFO
// Local parameters
parameter C_REAL_DEPTH = 2**clog2(C_DEPTH),
parameter C_DEPTH_BITS = clog2(C_REAL_DEPTH),
parameter C_DEPTH_P1_BITS = clog2(C_REAL_DEPTH+1)
)
(
input RD_CLK, // Read clock
input RD_RST, // Read synchronous reset
input WR_CLK, // Write clock
input WR_RST, // Write synchronous reset
input [C_WIDTH-1:0] WR_DATA, // Write data input (WR_CLK)
input WR_EN, // Write enable, high active (WR_CLK)
output [C_WIDTH-1:0] RD_DATA, // Read data output (RD_CLK)
input RD_EN, // Read enable, high active (RD_CLK)
output WR_FULL, // Full condition (WR_CLK)
output RD_EMPTY // Empty condition (RD_CLK)
);
`include "common_functions.v"
wire wCmpEmpty;
wire wCmpFull;
wire [C_DEPTH_BITS-1:0] wWrPtr;
wire [C_DEPTH_BITS-1:0] wRdPtr;
wire [C_DEPTH_BITS-1:0] wWrPtrP1;
wire [C_DEPTH_BITS-1:0] wRdPtrP1;
// Memory block (synthesis attributes applied to this module will
// determine the memory option).
ram_2clk_1w_1r #(.C_RAM_WIDTH(C_WIDTH), .C_RAM_DEPTH(C_REAL_DEPTH)) mem (
.CLKA(WR_CLK),
.ADDRA(wWrPtr),
.WEA(WR_EN & !WR_FULL),
.DINA(WR_DATA),
.CLKB(RD_CLK),
.ADDRB(wRdPtr),
.DOUTB(RD_DATA)
);
// Compare the pointers.
async_cmp #(.C_DEPTH_BITS(C_DEPTH_BITS)) asyncCompare (
.WR_RST(WR_RST),
.WR_CLK(WR_CLK),
.RD_RST(RD_RST),
.RD_CLK(RD_CLK),
.RD_VALID(RD_EN & !RD_EMPTY),
.WR_VALID(WR_EN & !WR_FULL),
.EMPTY(wCmpEmpty),
.FULL(wCmpFull),
.WR_PTR(wWrPtr),
.WR_PTR_P1(wWrPtrP1),
.RD_PTR(wRdPtr),
.RD_PTR_P1(wRdPtrP1)
);
// Calculate empty
rd_ptr_empty #(.C_DEPTH_BITS(C_DEPTH_BITS)) rdPtrEmpty (
.RD_EMPTY(RD_EMPTY),
.RD_PTR(wRdPtr),
.RD_PTR_P1(wRdPtrP1),
.CMP_EMPTY(wCmpEmpty),
.RD_EN(RD_EN),
.RD_CLK(RD_CLK),
.RD_RST(RD_RST)
);
// Calculate full
wr_ptr_full #(.C_DEPTH_BITS(C_DEPTH_BITS)) wrPtrFull (
.WR_CLK(WR_CLK),
.WR_RST(WR_RST),
.WR_EN(WR_EN),
.WR_FULL(WR_FULL),
.WR_PTR(wWrPtr),
.WR_PTR_P1(wWrPtrP1),
.CMP_FULL(wCmpFull)
);
endmodule
module async_cmp #(
parameter C_DEPTH_BITS = 4,
// Local parameters
parameter N = C_DEPTH_BITS-1
)
(
input WR_RST,
input WR_CLK,
input RD_RST,
input RD_CLK,
input RD_VALID,
input WR_VALID,
output EMPTY,
output FULL,
input [C_DEPTH_BITS-1:0] WR_PTR,
input [C_DEPTH_BITS-1:0] RD_PTR,
input [C_DEPTH_BITS-1:0] WR_PTR_P1,
input [C_DEPTH_BITS-1:0] RD_PTR_P1
);
reg rDir=0;
wire wDirSet = ( (WR_PTR[N]^RD_PTR[N-1]) & ~(WR_PTR[N-1]^RD_PTR[N]));
wire wDirClr = ((~(WR_PTR[N]^RD_PTR[N-1]) & (WR_PTR[N-1]^RD_PTR[N])) | WR_RST);
reg rRdValid=0;
reg rEmpty=1;
reg rFull=0;
wire wATBEmpty = ((WR_PTR == RD_PTR_P1) && (RD_VALID | rRdValid));
wire wATBFull = ((WR_PTR_P1 == RD_PTR) && WR_VALID);
wire wEmpty = ((WR_PTR == RD_PTR) && !rDir);
wire wFull = ((WR_PTR == RD_PTR) && rDir);
assign EMPTY = wATBEmpty || rEmpty;
assign FULL = wATBFull || rFull;
always @(posedge wDirSet or posedge wDirClr)
if (wDirClr)
rDir <= 1'b0;
else
rDir <= 1'b1;
always @(posedge RD_CLK) begin
rEmpty <= (RD_RST ? 1'd1 : wEmpty);
rRdValid <= (RD_RST ? 1'd0 : RD_VALID);
end
always @(posedge WR_CLK) begin
rFull <= (WR_RST ? 1'd0 : wFull);
end
endmodule
module rd_ptr_empty #(
parameter C_DEPTH_BITS = 4
)
(
input RD_CLK,
input RD_RST,
input RD_EN,
output RD_EMPTY,
output [C_DEPTH_BITS-1:0] RD_PTR,
output [C_DEPTH_BITS-1:0] RD_PTR_P1,
input CMP_EMPTY
);
reg rEmpty=1;
reg rEmpty2=1;
reg [C_DEPTH_BITS-1:0] rRdPtr=0;
reg [C_DEPTH_BITS-1:0] rRdPtrP1=0;
reg [C_DEPTH_BITS-1:0] rBin=0;
reg [C_DEPTH_BITS-1:0] rBinP1=1;
wire [C_DEPTH_BITS-1:0] wGrayNext;
wire [C_DEPTH_BITS-1:0] wGrayNextP1;
wire [C_DEPTH_BITS-1:0] wBinNext;
wire [C_DEPTH_BITS-1:0] wBinNextP1;
assign RD_EMPTY = rEmpty;
assign RD_PTR = rRdPtr;
assign RD_PTR_P1 = rRdPtrP1;
// Gray coded pointer
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST) begin
rBin <= #1 0;
rBinP1 <= #1 1;
rRdPtr <= #1 0;
rRdPtrP1 <= #1 0;
end
else begin
rBin <= #1 wBinNext;
rBinP1 <= #1 wBinNextP1;
rRdPtr <= #1 wGrayNext;
rRdPtrP1 <= #1 wGrayNextP1;
end
end
// Increment the binary count if not empty
assign wBinNext = (!rEmpty ? rBin + RD_EN : rBin);
assign wBinNextP1 = (!rEmpty ? rBinP1 + RD_EN : rBinP1);
assign wGrayNext = ((wBinNext>>1) ^ wBinNext); // binary-to-gray conversion
assign wGrayNextP1 = ((wBinNextP1>>1) ^ wBinNextP1); // binary-to-gray conversion
always @(posedge RD_CLK) begin
if (CMP_EMPTY)
{rEmpty, rEmpty2} <= #1 2'b11;
else
{rEmpty, rEmpty2} <= #1 {rEmpty2, CMP_EMPTY};
end
endmodule
module wr_ptr_full #(
parameter C_DEPTH_BITS = 4
)
(
input WR_CLK,
input WR_RST,
input WR_EN,
output WR_FULL,
output [C_DEPTH_BITS-1:0] WR_PTR,
output [C_DEPTH_BITS-1:0] WR_PTR_P1,
input CMP_FULL
);
reg rFull=0;
reg rFull2=0;
reg [C_DEPTH_BITS-1:0] rPtr=0;
reg [C_DEPTH_BITS-1:0] rPtrP1=0;
reg [C_DEPTH_BITS-1:0] rBin=0;
reg [C_DEPTH_BITS-1:0] rBinP1=1;
wire [C_DEPTH_BITS-1:0] wGrayNext;
wire [C_DEPTH_BITS-1:0] wGrayNextP1;
wire [C_DEPTH_BITS-1:0] wBinNext;
wire [C_DEPTH_BITS-1:0] wBinNextP1;
assign WR_FULL = rFull;
assign WR_PTR = rPtr;
assign WR_PTR_P1 = rPtrP1;
// Gray coded pointer
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST) begin
rBin <= #1 0;
rBinP1 <= #1 1;
rPtr <= #1 0;
rPtrP1 <= #1 0;
end
else begin
rBin <= #1 wBinNext;
rBinP1 <= #1 wBinNextP1;
rPtr <= #1 wGrayNext;
rPtrP1 <= #1 wGrayNextP1;
end
end
// Increment the binary count if not full
assign wBinNext = (!rFull ? rBin + WR_EN : rBin);
assign wBinNextP1 = (!rFull ? rBinP1 + WR_EN : rBinP1);
assign wGrayNext = ((wBinNext>>1) ^ wBinNext); // binary-to-gray conversion
assign wGrayNextP1 = ((wBinNextP1>>1) ^ wBinNextP1); // binary-to-gray conversion
always @(posedge WR_CLK) begin
if (WR_RST)
{rFull, rFull2} <= #1 2'b00;
else if (CMP_FULL)
{rFull, rFull2} <= #1 2'b11;
else
{rFull, rFull2} <= #1 {rFull2, CMP_FULL};
end
endmodule
================================================
FILE: hw/boards/ML605/ipcore_dir/riffa/async_fifo_fwft.v
================================================
`timescale 1ns/1ns
//----------------------------------------------------------------------------
// This software is Copyright © 2012 The Regents of the University of
// California. All Rights Reserved.
//
// Permission to copy, modify, and distribute this software and its
// documentation for educational, research and non-profit purposes, without
// fee, and without a written agreement is hereby granted, provided that the
// above copyright notice, this paragraph and the following three paragraphs
// appear in all copies.
//
// Permission to make commercial use of this software may be obtained by
// contacting:
// Technology Transfer Office
// 9500 Gilman Drive, Mail Code 0910
// University of California
// La Jolla, CA 92093-0910
// (858) 534-5815
// invent@ucsd.edu
//
// This software program and documentation are copyrighted by The Regents of
// the University of California. The software program and documentation are
// supplied "as is", without any accompanying services from The Regents. The
// Regents does not warrant that the operation of the program will be
// uninterrupted or error-free. The end-user understands that the program was
// developed for research purposes and is advised not to rely exclusively on
// the program for any reason.
//
// IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO
// ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING
// OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,
// EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE. THE UNIVERSITY OF
// CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
// THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS,
// AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATIONS TO
// PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
// MODIFICATIONS.
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: async_fifo_fwft.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: An asynchronous capable parameterized FIFO. As with all
// first word fall through FIFOs, the RD_DATA will be valid when RD_EMPTY is
// low. Asserting RD_EN will consume the current RD_DATA value and cause the
// next value (if it exists) to appear on RD_DATA on the following cycle. Be sure
// to check if RD_EMPTY is low each cycle to determine if RD_DATA is valid.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
module async_fifo_fwft #(
parameter C_WIDTH = 32, // Data bus width
parameter C_DEPTH = 1024, // Depth of the FIFO
// Local parameters
parameter C_REAL_DEPTH = 2**clog2(C_DEPTH),
parameter C_DEPTH_BITS = clog2s(C_REAL_DEPTH),
parameter C_DEPTH_P1_BITS = clog2s(C_REAL_DEPTH+1)
)
(
input RD_CLK, // Read clock
input RD_RST, // Read synchronous reset
input WR_CLK, // Write clock
input WR_RST, // Write synchronous reset
input [C_WIDTH-1:0] WR_DATA, // Write data input (WR_CLK)
input WR_EN, // Write enable, high active (WR_CLK)
output [C_WIDTH-1:0] RD_DATA, // Read data output (RD_CLK)
input RD_EN, // Read enable, high active (RD_CLK)
output WR_FULL, // Full condition (WR_CLK)
output RD_EMPTY // Empty condition (RD_CLK)
);
`include "common_functions.v"
reg [C_WIDTH-1:0] rData=0;
reg [C_WIDTH-1:0] rCache=0;
reg [1:0] rCount=0;
reg rFifoDataValid=0;
reg rDataValid=0;
reg rCacheValid=0;
wire [C_WIDTH-1:0] wData;
wire wEmpty;
wire wRen = RD_EN || (rCount < 2'd2);
assign RD_DATA = rData;
assign RD_EMPTY = !rDataValid;
// Wrapped non-FWFT FIFO (synthesis attributes applied to this module will
// determine the memory option).
async_fifo #(.C_WIDTH(C_WIDTH), .C_DEPTH(C_DEPTH)) fifo (
.WR_CLK(WR_CLK),
.WR_RST(WR_RST),
.RD_CLK(RD_CLK),
.RD_RST(RD_RST),
.WR_EN(WR_EN),
.WR_DATA(WR_DATA),
.WR_FULL(WR_FULL),
.RD_EN(wRen),
.RD_DATA(wData),
.RD_EMPTY(wEmpty)
);
always @ (posedge RD_CLK) begin
if (RD_RST) begin
rCount <= #1 0;
rDataValid <= #1 0;
rCacheValid <= #1 0;
rFifoDataValid <= #1 0;
end
else begin
// Keep track of the count
rCount <= #1 rCount + (wRen & !wEmpty) - (!RD_EMPTY & RD_EN);
// Signals when wData from FIFO is valid
rFifoDataValid <= #1 (wRen & !wEmpty);
// Keep rData up to date
if (rFifoDataValid) begin
if (RD_EN | !rDataValid) begin
rData <= #1 wData;
rDataValid <= #1 1'd1;
rCacheValid <= #1 1'd0;
end
else begin
rCacheValid <= #1 1'd1;
end
rCache <= #1 wData;
end
else begin
if (RD_EN | !rDataValid) begin
rData <= #1 rCache;
rDataValid <= #1 rCacheValid;
rCacheValid <= #1 1'd0;
end
end
end
end
endmodule
================================================
FILE: hw/boards/ML605/ipcore_dir/riffa/axi_basic_rx.v
================================================
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : axi_basic_rx.v
// Version : 2.4
//----------------------------------------------------------------------------//
// File: axi_basic_rx.v //
// //
// Description: //
// TRN to AXI RX module. Instantiates pipeline and null generator RX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_rx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires
wire null_rx_tvalid;
wire null_rx_tlast;
wire [KEEP_WIDTH-1:0] null_rx_tkeep;
wire null_rdst_rdy;
wire [4:0] null_is_eof;
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
axi_basic_rx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_pipeline_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// Null Inputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// RX Null Packet Generator //
//---------------------------------------------//
axi_basic_rx_null_gen #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.TCQ( TCQ ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_null_gen_inst (
// Inputs
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Null Outputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
================================================
FILE: hw/boards/ML605/ipcore_dir/riffa/axi_basic_rx_null_gen.v
================================================
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : axi_basic_rx_null_gen.v
// Version : 2.4
//----------------------------------------------------------------------------//
// File: axi_basic_rx_null_gen.v //
// //
// Description: //
// TRN to AXI RX null generator. Generates null packets for use in //
// discontinue situations. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// axi_basic_rx_null_gen //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_rx_null_gen # (
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
// AXI RX
//-----------
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
input m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
input m_axis_rx_tlast, // RX data is last
input [21:0] m_axis_rx_tuser, // RX user signals
// Null Inputs
//-----------
output null_rx_tvalid, // NULL generated tvalid
output null_rx_tlast, // NULL generated tlast
output [KEEP_WIDTH-1:0] null_rx_tkeep, // NULL generated tkeep
output null_rdst_rdy, // NULL generated rdst_rdy
output reg [4:0] null_is_eof, // NULL generated is_eof
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
localparam INTERFACE_WIDTH_DWORDS = (C_DATA_WIDTH == 128) ? 11'd4 :
(C_DATA_WIDTH == 64) ? 11'd2 : 11'd1;
//----------------------------------------------------------------------------//
// NULL packet generator state machine //
// This state machine shadows the AXI RX interface, tracking each packet as //
// it's passed to the AXI user. When a multi-cycle packet is detected, the //
// state machine automatically generates a "null" packet. In the event of a //
// discontinue, the RX pipeline can switch over to this null packet as //
// necessary. //
//----------------------------------------------------------------------------//
// State machine variables and states
localparam IDLE = 0;
localparam IN_PACKET = 1;
reg cur_state;
reg next_state;
// Signals for tracking a packet on the AXI interface
reg [11:0] reg_pkt_len_counter;
reg [11:0] pkt_len_counter;
wire [11:0] pkt_len_counter_dec;
wire pkt_done;
// Calculate packet fields, which are needed to determine total packet length.
wire [11:0] new_pkt_len;
wire [9:0] payload_len;
wire [1:0] packet_fmt;
wire packet_td;
reg [3:0] packet_overhead;
// Misc.
wire [KEEP_WIDTH-1:0] eof_tkeep;
wire straddle_sof;
wire eof;
// Create signals to detect sof and eof situations. These signals vary depending
// on data width.
assign eof = m_axis_rx_tuser[21];
generate
if(C_DATA_WIDTH == 128) begin : sof_eof_128
assign straddle_sof = (m_axis_rx_tuser[14:13] == 2'b11);
end
else begin : sof_eof_64_32
assign straddle_sof = 1'b0;
end
endgenerate
//----------------------------------------------------------------------------//
// Calculate the length of the packet being presented on the RX interface. To //
// do so, we need the relevent packet fields that impact total packet length. //
// These are: //
// - Header length: obtained from bit 1 of FMT field in 1st DWORD of header //
// - Payload length: obtained from LENGTH field in 1st DWORD of header //
// - TLP digist: obtained from TD field in 1st DWORD of header //
// - Current data: the number of bytes that have already been presented //
// on the data interface //
// //
// packet length = header + payload + tlp digest - # of DWORDS already //
// transmitted //
// //
// packet_overhead is where we calculate everything except payload. //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : len_calc_128
assign packet_fmt = straddle_sof ?
m_axis_rx_tdata[94:93] : m_axis_rx_tdata[30:29];
assign packet_td = straddle_sof ?
m_axis_rx_tdata[79] : m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ?
(straddle_sof ? m_axis_rx_tdata[73:64] : m_axis_rx_tdata[9:0]) : 10'h0;
always @(*) begin
// In 128-bit mode, the amount of data currently on the interface
// depends on whether we're straddling or not. If so, 2 DWORDs have been
// seen. If not, 4 DWORDs.
case({packet_fmt[0], packet_td, straddle_sof})
// Header + TD - Data currently on interface
3'b0_0_0: packet_overhead = 4'd3 + 4'd0 - 4'd4;
3'b0_0_1: packet_overhead = 4'd3 + 4'd0 - 4'd2;
3'b0_1_0: packet_overhead = 4'd3 + 4'd1 - 4'd4;
3'b0_1_1: packet_overhead = 4'd3 + 4'd1 - 4'd2;
3'b1_0_0: packet_overhead = 4'd4 + 4'd0 - 4'd4;
3'b1_0_1: packet_overhead = 4'd4 + 4'd0 - 4'd2;
3'b1_1_0: packet_overhead = 4'd4 + 4'd1 - 4'd4;
3'b1_1_1: packet_overhead = 4'd4 + 4'd1 - 4'd2;
endcase
end
end
else if(C_DATA_WIDTH == 64) begin : len_calc_64
assign packet_fmt = m_axis_rx_tdata[30:29];
assign packet_td = m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
always @(*) begin
// 64-bit mode: no straddling, so always 2 DWORDs
case({packet_fmt[0], packet_td})
// Header + TD - Data currently on interface
2'b0_0: packet_overhead = 4'd3 + 4'd0 - 4'd2;
2'b0_1: packet_overhead = 4'd3 + 4'd1 - 4'd2;
2'b1_0: packet_overhead = 4'd4 + 4'd0 - 4'd2;
2'b1_1: packet_overhead = 4'd4 + 4'd1 - 4'd2;
endcase
end
end
else begin : len_calc_32
assign packet_fmt = m_axis_rx_tdata[30:29];
assign packet_td = m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
always @(*) begin
// 32-bit mode: no straddling, so always 1 DWORD
case({packet_fmt[0], packet_td})
// Header + TD - Data currently on interface
2'b0_0: packet_overhead = 4'd3 + 4'd0 - 4'd1;
2'b0_1: packet_overhead = 4'd3 + 4'd1 - 4'd1;
2'b1_0: packet_overhead = 4'd4 + 4'd0 - 4'd1;
2'b1_1: packet_overhead = 4'd4 + 4'd1 - 4'd1;
endcase
end
end
endgenerate
// Now calculate actual packet length, adding the packet overhead and the
// payload length. This is signed math, so sign-extend packet_overhead.
// NOTE: a payload length of zero means 1024 DW in the PCIe spec, but this
// behavior isn't supported in our block.
assign new_pkt_len =
{{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
// Math signals needed in the state machine below. These are seperate wires to
// help ensure synthesis tools sre smart about optimizing them.
assign pkt_len_counter_dec = reg_pkt_len_counter - INTERFACE_WIDTH_DWORDS;
assign pkt_done = (reg_pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
//----------------------------------------------------------------------------//
// Null generator Mealy state machine. Determine outputs based on: //
// 1) current st //
// 2) current inp //
//----------------------------------------------------------------------------//
always @(*) begin
case (cur_state)
// IDLE state: the interface is IDLE and we're waiting for a packet to
// start. If a packet starts, move to state IN_PACKET and begin tracking
// it as long as it's NOT a single cycle packet (indicated by assertion of
// eof at packet start)
IDLE: begin
if(m_axis_rx_tvalid && m_axis_rx_tready && !eof) begin
next_state = IN_PACKET;
end
else begin
next_state = IDLE;
end
pkt_len_counter = new_pkt_len;
end
// IN_PACKET: a mutli-cycle packet is in progress and we're tracking it. We
// are in lock-step with the AXI interface decrementing our packet length
// tracking reg, and waiting for the packet to finish.
//
// * If packet finished and a new one starts, this is a straddle situation.
// Next state is IN_PACKET (128-bit only).
// * If the current packet is done, next state is IDLE.
// * Otherwise, next state is IN_PACKET.
IN_PACKET: begin
// Straddle packet
if((C_DATA_WIDTH == 128) && straddle_sof && m_axis_rx_tvalid) begin
pkt_len_counter = new_pkt_len;
next_state = IN_PACKET;
end
// Current packet finished
else if(m_axis_rx_tready && pkt_done)
begin
pkt_len_counter = new_pkt_len;
next_state = IDLE;
end
// Packet in progress
else begin
if(m_axis_rx_tready) begin
// Not throttled
pkt_len_counter = pkt_len_counter_dec;
end
else begin
// Throttled
pkt_len_counter = reg_pkt_len_counter;
end
next_state = IN_PACKET;
end
end
default: begin
pkt_len_counter = reg_pkt_len_counter;
next_state = IDLE;
end
endcase
end
// Synchronous NULL packet generator state machine logic
always @(posedge user_clk) begin
if(user_rst) begin
cur_state <= #TCQ IDLE;
reg_pkt_len_counter <= #TCQ 12'h0;
end
else begin
cur_state <= #TCQ next_state;
reg_pkt_len_counter <= #TCQ pkt_len_counter;
end
end
// Generate tkeep/is_eof for an end-of-packet situation.
generate
if(C_DATA_WIDTH == 128) begin : strb_calc_128
always @(*) begin
// Assign null_is_eof depending on how many DWORDs are left in the
// packet.
case(pkt_len_counter)
10'd1: null_is_eof = 5'b10011;
10'd2: null_is_eof = 5'b10111;
10'd3: null_is_eof = 5'b11011;
10'd4: null_is_eof = 5'b11111;
default: null_is_eof = 5'b00011;
endcase
end
// tkeep not used in 128-bit interface
assign eof_tkeep = {KEEP_WIDTH{1'b0}};
end
else if(C_DATA_WIDTH == 64) begin : strb_calc_64
always @(*) begin
// Assign null_is_eof depending on how many DWORDs are left in the
// packet.
case(pkt_len_counter)
10'd1: null_is_eof = 5'b10011;
10'd2: null_is_eof = 5'b10111;
default: null_is_eof = 5'b00011;
endcase
end
// Assign tkeep to 0xFF or 0x0F depending on how many DWORDs are left in
// the current packet.
assign eof_tkeep = { ((pkt_len_counter == 12'd2) ? 4'hF:4'h0), 4'hF };
end
else begin : strb_calc_32
always @(*) begin
// is_eof is either on or off for 32-bit
if(pkt_len_counter == 12'd1) begin
null_is_eof = 5'b10011;
end
else begin
null_is_eof = 5'b00011;
end
end
// The entire DWORD is always valid in 32-bit mode, so tkeep is always 0xF
assign eof_tkeep = 4'hF;
end
endgenerate
// Finally, use everything we've generated to calculate our NULL outputs
assign null_rx_tvalid = 1'b1;
assign null_rx_tlast = (pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
assign null_rx_tkeep = null_rx_tlast ? eof_tkeep : {KEEP_WIDTH{1'b1}};
assign null_rdst_rdy = null_rx_tlast;
endmodule
================================================
FILE: hw/boards/ML605/ipcore_dir/riffa/axi_basic_rx_pipeline.v
================================================
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : axi_basic_rx_pipeline.v
// Version : 2.4
//----------------------------------------------------------------------------//
// File: axi_basic_rx_pipeline.v //
// //
// Description: //
// TRN to AXI RX pipeline. Converts received data from TRN protocol to AXI. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// axi_basic_rx_pipeline //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_rx_pipeline #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
// AXI RX
//-----------
output reg [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output reg m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output reg [21:0] m_axis_rx_tuser, // RX user signals
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output reg trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// Null Inputs
//-----------
input null_rx_tvalid, // NULL generated tvalid
input null_rx_tlast, // NULL generated tlast
input [KEEP_WIDTH-1:0] null_rx_tkeep, // NULL generated tkeep
input null_rdst_rdy, // NULL generated rdst_rdy
input [4:0] null_is_eof, // NULL generated is_eof
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires and regs for creating AXI signals
wire [4:0] is_sof;
wire [4:0] is_sof_prev;
wire [4:0] is_eof;
wire [4:0] is_eof_prev;
reg [KEEP_WIDTH-1:0] reg_tkeep;
wire [KEEP_WIDTH-1:0] tkeep;
wire [KEEP_WIDTH-1:0] tkeep_prev;
reg reg_tlast;
wire rsrc_rdy_filtered;
// Wires and regs for previous value buffer
wire [C_DATA_WIDTH-1:0] trn_rd_DW_swapped;
reg [C_DATA_WIDTH-1:0] trn_rd_prev;
wire data_hold;
reg data_prev;
reg trn_reof_prev;
reg [REM_WIDTH-1:0] trn_rrem_prev;
reg trn_rsrc_rdy_prev;
reg trn_rsrc_dsc_prev;
reg trn_rsof_prev;
reg [6:0] trn_rbar_hit_prev;
reg trn_rerrfwd_prev;
reg trn_recrc_err_prev;
// Null packet handling signals
reg null_mux_sel;
reg trn_in_packet;
wire dsc_flag;
wire dsc_detect;
reg reg_dsc_detect;
reg trn_rsrc_dsc_d;
// Create "filtered" version of rsrc_rdy, where discontinued SOFs are removed.
assign rsrc_rdy_filtered = trn_rsrc_rdy &&
(trn_in_packet || (trn_rsof && !trn_rsrc_dsc));
//----------------------------------------------------------------------------//
// Previous value buffer //
// --------------------- //
// We are inserting a pipeline stage in between TRN and AXI, which causes //
// some issues with handshaking signals m_axis_rx_tready/trn_rdst_rdy. The //
// added cycle of latency in the path causes the user design to fall behind //
// the TRN interface whenever it throttles. //
// //
// To avoid loss of data, we must keep the previous value of all trn_r* //
// signals in case the user throttles. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
trn_rd_prev <= #TCQ {C_DATA_WIDTH{1'b0}};
trn_rsof_prev <= #TCQ 1'b0;
trn_rrem_prev <= #TCQ {REM_WIDTH{1'b0}};
trn_rsrc_rdy_prev <= #TCQ 1'b0;
trn_rbar_hit_prev <= #TCQ 7'h00;
trn_rerrfwd_prev <= #TCQ 1'b0;
trn_recrc_err_prev <= #TCQ 1'b0;
trn_reof_prev <= #TCQ 1'b0;
trn_rsrc_dsc_prev <= #TCQ 1'b0;
end
else begin
// prev buffer works by checking trn_rdst_rdy. When trn_rdst_rdy is
// asserted, a new value is present on the interface.
if(trn_rdst_rdy) begin
trn_rd_prev <= #TCQ trn_rd_DW_swapped;
trn_rsof_prev <= #TCQ trn_rsof;
trn_rrem_prev <= #TCQ trn_rrem;
trn_rbar_hit_prev <= #TCQ trn_rbar_hit;
trn_rerrfwd_prev <= #TCQ trn_rerrfwd;
trn_recrc_err_prev <= #TCQ trn_recrc_err;
trn_rsrc_rdy_prev <= #TCQ rsrc_rdy_filtered;
trn_reof_prev <= #TCQ trn_reof;
trn_rsrc_dsc_prev <= #TCQ trn_rsrc_dsc || dsc_flag;
end
end
end
//----------------------------------------------------------------------------//
// Create TDATA //
//----------------------------------------------------------------------------//
// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN
// 128-bit: 64-bit: 32-bit:
// TRN DW0 maps to AXI DW3 TRN DW0 maps to AXI DW1 TNR DW0 maps to AXI DW0
// TRN DW1 maps to AXI DW2 TRN DW1 maps to AXI DW0
// TRN DW2 maps to AXI DW1
// TRN DW3 maps to AXI DW0
generate
if(C_DATA_WIDTH == 128) begin : rd_DW_swap_128
assign trn_rd_DW_swapped = {trn_rd[31:0],
trn_rd[63:32],
trn_rd[95:64],
trn_rd[127:96]};
end
else if(C_DATA_WIDTH == 64) begin : rd_DW_swap_64
assign trn_rd_DW_swapped = {trn_rd[31:0], trn_rd[63:32]};
end
else begin : rd_DW_swap_32
assign trn_rd_DW_swapped = trn_rd;
end
endgenerate
// Create special buffer which locks in the proper value of TDATA depending
// on whether the user is throttling or not. This buffer has three states:
//
// HOLD state: TDATA maintains its current value
// - the user has throttled the PCIe block
// PREVIOUS state: the buffer provides the previous value on trn_rd
// - the user has finished throttling, and is a little behind
// the PCIe block
// CURRENT state: the buffer passes the current value on trn_rd
// - the user is caught up and ready to receive the latest
// data from the PCIe block
always @(posedge user_clk) begin
if(user_rst) begin
m_axis_rx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
end
else begin
if(!data_hold) begin
// PREVIOUS state
if(data_prev) begin
m_axis_rx_tdata <= #TCQ trn_rd_prev;
end
// CURRENT state
else begin
m_axis_rx_tdata <= #TCQ trn_rd_DW_swapped;
end
end
// else HOLD state
end
end
// Logic to instruct pipeline to hold its value
assign data_hold = (!m_axis_rx_tready && m_axis_rx_tvalid);
// Logic to instruct pipeline to use previous bus values. Always use previous
// value after holding a value.
always @(posedge user_clk) begin
if(user_rst) begin
data_prev <= #TCQ 1'b0;
end
else begin
data_prev <= #TCQ data_hold;
end
end
//----------------------------------------------------------------------------//
// Create TVALID, TLAST, tkeep, TUSER //
// ----------------------------------- //
// Use the same strategy for these signals as for TDATA, except here we need //
// an extra provision for null packets. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
m_axis_rx_tvalid <= #TCQ 1'b0;
reg_tlast <= #TCQ 1'b0;
reg_tkeep <= #TCQ {KEEP_WIDTH{1'b1}};
m_axis_rx_tuser <= #TCQ 22'h0;
end
else begin
if(!data_hold) begin
// If in a null packet, use null generated value
if(null_mux_sel) begin
m_axis_rx_tvalid <= #TCQ null_rx_tvalid;
reg_tlast <= #TCQ null_rx_tlast;
reg_tkeep <= #TCQ null_rx_tkeep;
m_axis_rx_tuser <= #TCQ {null_is_eof, 17'h0000};
end
// PREVIOUS state
else if(data_prev) begin
m_axis_rx_tvalid <= #TCQ (trn_rsrc_rdy_prev || dsc_flag);
reg_tlast <= #TCQ trn_reof_prev;
reg_tkeep <= #TCQ tkeep_prev;
m_axis_rx_tuser <= #TCQ {is_eof_prev, // TUSER bits [21:17]
2'b00, // TUSER bits [16:15]
is_sof_prev, // TUSER bits [14:10]
1'b0, // TUSER bit [9]
trn_rbar_hit_prev, // TUSER bits [8:2]
trn_rerrfwd_prev, // TUSER bit [1]
trn_recrc_err_prev}; // TUSER bit [0]
end
// CURRENT state
else begin
m_axis_rx_tvalid <= #TCQ (rsrc_rdy_filtered || dsc_flag);
reg_tlast <= #TCQ trn_reof;
reg_tkeep <= #TCQ tkeep;
m_axis_rx_tuser <= #TCQ {is_eof, // TUSER bits [21:17]
2'b00, // TUSER bits [16:15]
is_sof, // TUSER bits [14:10]
1'b0, // TUSER bit [9]
trn_rbar_hit, // TUSER bits [8:2]
trn_rerrfwd, // TUSER bit [1]
trn_recrc_err}; // TUSER bit [0]
end
end
// else HOLD state
end
end
// Hook up TLAST and tkeep depending on interface width
generate
// For 128-bit interface, don't pass TLAST and tkeep to user (is_eof and
// is_data passed to user instead). reg_tlast is still used internally.
if(C_DATA_WIDTH == 128) begin : tlast_tkeep_hookup_128
assign m_axis_rx_tlast = 1'b0;
assign m_axis_rx_tkeep = {KEEP_WIDTH{1'b1}};
end
// For 64/32-bit interface, pass TLAST to user.
else begin : tlast_tkeep_hookup_64_32
assign m_axis_rx_tlast = reg_tlast;
assign m_axis_rx_tkeep = reg_tkeep;
end
endgenerate
//----------------------------------------------------------------------------//
// Create tkeep //
// ------------ //
// Convert RREM to STRB. Here, we are converting the encoding method for the //
// location of the EOF from TRN flavor (rrem) to AXI (tkeep). //
// //
// NOTE: for each configuration, we need two values of tkeep, the current and //
// previous values. The need for these two values is described below. //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : rrem_to_tkeep_128
// TLAST and tkeep not used in 128-bit interface. is_sof and is_eof used
// instead.
assign tkeep = 16'h0000;
assign tkeep_prev = 16'h0000;
end
else if(C_DATA_WIDTH == 64) begin : rrem_to_tkeep_64
// 64-bit interface: contains 2 DWORDs per cycle, for a total of 8 bytes
// - tkeep has only two possible values here, 0xFF or 0x0F
assign tkeep = trn_rrem ? 8'hFF : 8'h0F;
assign tkeep_prev = trn_rrem_prev ? 8'hFF : 8'h0F;
end
else begin : rrem_to_tkeep_32
// 32-bit interface: contains 1 DWORD per cycle, for a total of 4 bytes
// - tkeep is always 0xF in this case, due to the nature of the PCIe block
assign tkeep = 4'hF;
assign tkeep_prev = 4'hF;
end
endgenerate
//----------------------------------------------------------------------------//
// Create is_sof //
// ------------- //
// is_sof is a signal to the user indicating the location of SOF in TDATA . //
// Due to inherent 64-bit alignment of packets from the block, the only //
// possible values are: //
// Value Valid data widths //
// 5'b11000 (sof @ byte 8) 128 //
// 5'b10000 (sof @ byte 0) 128, 64, 32 //
// 5'b00000 (sof not present) 128, 64, 32 //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : is_sof_128
assign is_sof = {(trn_rsof && !trn_rsrc_dsc), // bit 4: enable
(trn_rsof && !trn_rrem[1]), // bit 3: sof @ byte 8?
3'b000}; // bit 2-0: hardwired 0
assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4
(trn_rsof_prev && !trn_rrem_prev[1]), // bit 3
3'b000}; // bit 2-0
end
else begin : is_sof_64_32
assign is_sof = {(trn_rsof && !trn_rsrc_dsc), // bit 4: enable
4'b0000}; // bit 3-0: hardwired 0
assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4
4'b0000}; // bit 3-0
end
endgenerate
//----------------------------------------------------------------------------//
// Create is_eof //
// ------------- //
// is_eof is a signal to the user indicating the location of EOF in TDATA . //
// Due to DWORD granularity of packets from the block, the only //
// possible values are: //
// Value Valid data widths //
// 5'b11111 (eof @ byte 15) 128 //
// 5'b11011 (eof @ byte 11) 128 //
// 5'b10111 (eof @ byte 7) 128, 64 //
// 5'b10011 (eof @ byte 3)` 128, 64, 32 //
// 5'b00011 (eof not present) 128, 64, 32 //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : is_eof_128
assign is_eof = {trn_reof, // bit 4: enable
trn_rrem, // bit 3-2: encoded eof loc rom block
2'b11}; // bit 1-0: hardwired 1
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
trn_rrem_prev, // bit 3-2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
end
else if(C_DATA_WIDTH == 64) begin : is_eof_64
assign is_eof = {trn_reof, // bit 4: enable
1'b0, // bit 3: hardwired 0
trn_rrem, // bit 2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
1'b0, // bit 3: hardwired 0
trn_rrem_prev, // bit 2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
end
else begin : is_eof_32
assign is_eof = {trn_reof, // bit 4: enable
4'b0011}; // bit 3-0: hardwired to byte 3
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
4'b0011}; // bit 3-0: hardwired to byte 3
end
endgenerate
//----------------------------------------------------------------------------//
// Create trn_rdst_rdy //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
trn_rdst_rdy <= #TCQ 1'b0;
end
else begin
// If in a null packet, use null generated value
if(null_mux_sel && m_axis_rx_tready) begin
trn_rdst_rdy <= #TCQ null_rdst_rdy;
end
// If a discontinue needs to be serviced, throttle the block until we are
// ready to pad out the packet.
else if(dsc_flag) begin
trn_rdst_rdy <= #TCQ 1'b0;
end
// If in a packet, pass user back-pressure directly to block
else if(m_axis_rx_tvalid) begin
trn_rdst_rdy <= #TCQ m_axis_rx_tready;
end
// If idle, default to no back-pressure. We need to default to the
// "ready to accept data" state to make sure we catch the first
// clock of data of a new packet.
else begin
trn_rdst_rdy <= #TCQ 1'b1;
end
end
end
//----------------------------------------------------------------------------//
// Create null_mux_sel //
// null_mux_sel is the signal used to detect a discontinue situation and //
// mux in the null packet generated in rx_null_gen. Only mux in null data //
// when not at the beginningof a packet. SOF discontinues do not require //
// padding, as the whole packet is simply squashed instead. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
null_mux_sel <= #TCQ 1'b0;
end
else begin
// NULL packet done
if(null_mux_sel && null_rx_tlast && m_axis_rx_tready)
begin
null_mux_sel <= #TCQ 1'b0;
end
// Discontinue detected and we're in packet, so switch to NULL packet
else if(dsc_flag && !data_hold) begin
null_mux_sel <= #TCQ 1'b1;
end
end
end
//----------------------------------------------------------------------------//
// Create discontinue tracking signals //
//----------------------------------------------------------------------------//
// Create signal trn_in_packet, which is needed to validate trn_rsrc_dsc. We
// should ignore trn_rsrc_dsc when it's asserted out-of-packet.
always @(posedge user_clk) begin
if(user_rst) begin
trn_in_packet <= #TCQ 1'b0;
end
else begin
if(trn_rsof && !trn_reof && rsrc_rdy_filtered && trn_rdst_rdy)
begin
trn_in_packet <= #TCQ 1'b1;
end
else if(trn_rsrc_dsc) begin
trn_in_packet <= #TCQ 1'b0;
end
else if(trn_reof && !trn_rsof && trn_rsrc_rdy && trn_rdst_rdy) begin
trn_in_packet <= #TCQ 1'b0;
end
end
end
// Create dsc_flag, which identifies and stores mid-packet discontinues that
// require null packet padding. This signal is edge sensitive to trn_rsrc_dsc,
// to make sure we don't service the same dsc twice in the event that
// trn_rsrc_dsc stays asserted for longer than it takes to pad out the packet.
assign dsc_detect = trn_rsrc_dsc && !trn_rsrc_dsc_d && trn_in_packet &&
(!trn_rsof || trn_reof) && !(trn_rdst_rdy && trn_reof);
always @(posedge user_clk) begin
if(user_rst) begin
reg_dsc_detect <= #TCQ 1'b0;
trn_rsrc_dsc_d <= #TCQ 1'b0;
end
else begin
if(dsc_detect) begin
reg_dsc_detect <= #TCQ 1'b1;
end
else if(null_mux_sel) begin
reg_dsc_detect <= #TCQ 1'b0;
end
trn_rsrc_dsc_d <= #TCQ trn_rsrc_dsc;
end
end
assign dsc_flag = dsc_detect || reg_dsc_detect;
//----------------------------------------------------------------------------//
// Create np_counter (V6 128-bit only). This counter tells the V6 128-bit //
// interface core how many NP packets have left the RX pipeline. The V6 //
// 128-bit interface uses this count to perform rnp_ok modulation. //
//----------------------------------------------------------------------------//
generate
if(C_FAMILY == "V6" && C_DATA_WIDTH == 128) begin : np_cntr_to_128_enabled
reg [2:0] reg_np_counter;
// Look for NP packets beginning on lower (i.e. unaligned) start
wire mrd_lower = (!(|m_axis_rx_tdata[92:88]) && !m_axis_rx_tdata[94]);
wire mrd_lk_lower = (m_axis_rx_tdata[92:88] == 5'b00001);
wire io_rdwr_lower = (m_axis_rx_tdata[92:88] == 5'b00010);
wire cfg_rdwr_lower = (m_axis_rx_tdata[92:89] == 4'b0010);
wire atomic_lower = ((&m_axis_rx_tdata[91:90]) && m_axis_rx_tdata[94]);
wire np_pkt_lower = (mrd_lower ||
mrd_lk_lower ||
io_rdwr_lower ||
cfg_rdwr_lower ||
atomic_lower) && m_axis_rx_tuser[13];
// Look for NP packets beginning on upper (i.e. aligned) start
wire mrd_upper = (!(|m_axis_rx_tdata[28:24]) && !m_axis_rx_tdata[30]);
wire mrd_lk_upper = (m_axis_rx_tdata[28:24] == 5'b00001);
wire io_rdwr_upper = (m_axis_rx_tdata[28:24] == 5'b00010);
wire cfg_rdwr_upper = (m_axis_rx_tdata[28:25] == 4'b0010);
wire atomic_upper = ((&m_axis_rx_tdata[27:26]) && m_axis_rx_tdata[30]);
wire np_pkt_upper = (mrd_upper ||
mrd_lk_upper ||
io_rdwr_upper ||
cfg_rdwr_upper ||
atomic_upper) && !m_axis_rx_tuser[13];
wire pkt_accepted =
m_axis_rx_tuser[14] && m_axis_rx_tready && m_axis_rx_tvalid;
// Increment counter whenever an NP packet leaves the RX pipeline
always @(posedge user_clk) begin
if (user_rst) begin
reg_np_counter <= #TCQ 0;
end
else begin
if((np_pkt_lower || np_pkt_upper) && pkt_accepted)
begin
reg_np_counter <= #TCQ reg_np_counter + 3'h1;
end
end
end
assign np_counter = reg_np_counter;
end
else begin : np_cntr_to_128_disabled
assign np_counter = 3'h0;
end
endgenerate
endmodule
================================================
FILE: hw/boards/ML605/ipcore_dir/riffa/axi_basic_top.v
================================================
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear fac
gitextract_u_mc_d1s/
├── LICENSE
├── README.md
├── hw/
│ └── boards/
│ └── ML605/
│ ├── SoftMC.xise
│ ├── apply_patches.sh
│ ├── autoref_config.v
│ ├── instr_decoder.v
│ ├── instr_dispatcher.v
│ ├── instr_receiver.v
│ ├── ipcore_dir/
│ │ ├── instr_fifo.xco
│ │ ├── instr_fifo.xise
│ │ ├── pcie_endpoint.xco
│ │ ├── pcie_endpoint.xise
│ │ ├── rdback_fifo.xco
│ │ ├── rdback_fifo.xise
│ │ ├── riffa/
│ │ │ ├── async_fifo.v
│ │ │ ├── async_fifo_fwft.v
│ │ │ ├── axi_basic_rx.v
│ │ │ ├── axi_basic_rx_null_gen.v
│ │ │ ├── axi_basic_rx_pipeline.v
│ │ │ ├── axi_basic_top.v
│ │ │ ├── axi_basic_tx.v
│ │ │ ├── axi_basic_tx_pipeline.v
│ │ │ ├── axi_basic_tx_thrtl_ctl.v
│ │ │ ├── channel_128.v
│ │ │ ├── channel_32.v
│ │ │ ├── channel_64.v
│ │ │ ├── chnl_tester.v
│ │ │ ├── common_functions.v
│ │ │ ├── cross_domain_signal.v
│ │ │ ├── demux_1_to_n.v
│ │ │ ├── ff.v
│ │ │ ├── fifo_packer_128.v
│ │ │ ├── fifo_packer_32.v
│ │ │ ├── fifo_packer_64.v
│ │ │ ├── gtx_drp_chanalign_fix_3752_v6.v
│ │ │ ├── gtx_rx_valid_filter_v6.v
│ │ │ ├── gtx_tx_sync_rate_v6.v
│ │ │ ├── gtx_wrapper_v6.v
│ │ │ ├── interrupt.v
│ │ │ ├── interrupt_controller.v
│ │ │ ├── pcie_2_0_v6.v
│ │ │ ├── pcie_bram_top_v6.v
│ │ │ ├── pcie_bram_v6.v
│ │ │ ├── pcie_brams_v6.v
│ │ │ ├── pcie_clocking_v6.v
│ │ │ ├── pcie_endpoint.v
│ │ │ ├── pcie_gtx_v6.v
│ │ │ ├── pcie_pipe_lane_v6.v
│ │ │ ├── pcie_pipe_misc_v6.v
│ │ │ ├── pcie_pipe_v6.v
│ │ │ ├── pcie_reset_delay_v6.v
│ │ │ ├── pcie_upconfig_fix_3451_v6.v
│ │ │ ├── ram_1clk_1w_1r.v
│ │ │ ├── ram_2clk_1w_1r.v
│ │ │ ├── recv_credit_flow_ctrl.v
│ │ │ ├── reorder_queue.v
│ │ │ ├── reorder_queue_input.v
│ │ │ ├── reorder_queue_output.v
│ │ │ ├── riffa_adapter_v6_pcie_v2_5.v
│ │ │ ├── riffa_endpoint.v
│ │ │ ├── riffa_endpoint_128.v
│ │ │ ├── riffa_endpoint_32.v
│ │ │ ├── riffa_endpoint_64.v
│ │ │ ├── riffa_top_v6_pcie_v2_5.v
│ │ │ ├── rx_engine_128.v
│ │ │ ├── rx_engine_32.v
│ │ │ ├── rx_engine_64.v
│ │ │ ├── rx_engine_req.v
│ │ │ ├── rx_port_128.v
│ │ │ ├── rx_port_32.v
│ │ │ ├── rx_port_64.v
│ │ │ ├── rx_port_channel_gate.v
│ │ │ ├── rx_port_reader.v
│ │ │ ├── rx_port_requester_mux.v
│ │ │ ├── sg_list_reader_128.v
│ │ │ ├── sg_list_reader_32.v
│ │ │ ├── sg_list_reader_64.v
│ │ │ ├── sg_list_requester.v
│ │ │ ├── sync_fifo.v
│ │ │ ├── syncff.v
│ │ │ ├── translation_layer.v
│ │ │ ├── translation_layer_128.v
│ │ │ ├── translation_layer_32.v
│ │ │ ├── translation_layer_64.v
│ │ │ ├── tx_engine_128.v
│ │ │ ├── tx_engine_32.v
│ │ │ ├── tx_engine_64.v
│ │ │ ├── tx_engine_formatter_128.v
│ │ │ ├── tx_engine_formatter_32.v
│ │ │ ├── tx_engine_formatter_64.v
│ │ │ ├── tx_engine_lower_128.v
│ │ │ ├── tx_engine_lower_32.v
│ │ │ ├── tx_engine_lower_64.v
│ │ │ ├── tx_engine_selector.v
│ │ │ ├── tx_engine_upper_128.v
│ │ │ ├── tx_engine_upper_32.v
│ │ │ ├── tx_engine_upper_64.v
│ │ │ ├── tx_port_128.v
│ │ │ ├── tx_port_32.v
│ │ │ ├── tx_port_64.v
│ │ │ ├── tx_port_buffer_128.v
│ │ │ ├── tx_port_buffer_32.v
│ │ │ ├── tx_port_buffer_64.v
│ │ │ ├── tx_port_channel_gate_128.v
│ │ │ ├── tx_port_channel_gate_32.v
│ │ │ ├── tx_port_channel_gate_64.v
│ │ │ ├── tx_port_monitor_128.v
│ │ │ ├── tx_port_monitor_32.v
│ │ │ ├── tx_port_monitor_64.v
│ │ │ ├── tx_port_writer.v
│ │ │ ├── tx_qword_aligner_128.v
│ │ │ └── tx_qword_aligner_64.v
│ │ ├── xilinx_mig/
│ │ │ ├── example_design/
│ │ │ │ └── mig.prj
│ │ │ └── user_design/
│ │ │ └── mig.prj
│ │ ├── xilinx_mig.xco
│ │ └── xilinx_mig.xise
│ ├── iseq_dispatcher.v
│ ├── maint_ctrl.v
│ ├── maint_handler.v
│ ├── patches/
│ │ ├── iodelay_ctrl.patch
│ │ ├── phy_rdctrl_sync.patch
│ │ ├── phy_read.patch
│ │ └── phy_top.patch
│ ├── pipe_reg.v
│ ├── read_capturer.v
│ ├── softMC.inc
│ ├── softMC.v
│ ├── softMC_constraints.ucf
│ ├── softMC_pcie_app.v
│ ├── softMC_top.v
│ └── tb_softMC_top.v
├── prebuilt/
│ ├── SoftMC.bit
│ └── SoftMC_RetentionTest
└── sw/
├── RetentionTest/
│ ├── Makefile
│ └── RetentionTest.cpp
├── SoftMC_API/
│ ├── softmc.cpp
│ └── softmc.h
└── riffa_2.1/
├── LICENSE
├── README.txt
└── driver/
├── linux/
│ ├── Makefile
│ ├── README.txt
│ ├── circ_queue.c
│ ├── circ_queue.h
│ ├── riffa.c
│ ├── riffa.h
│ ├── riffa_driver.c
│ └── riffa_driver.h
└── windows/
├── README.txt
├── dirs
├── install/
│ ├── install.bat
│ ├── license.txt
│ └── win7.iss
├── sys/
│ ├── makefile
│ ├── makefile.inc
│ ├── precomp.h
│ ├── riffa.c
│ ├── riffa.inx
│ ├── riffa.rc
│ ├── riffa_driver.h
│ ├── riffa_private.h
│ ├── sources
│ └── trace.h
└── win7install.bat
SYMBOL INDEX (110 symbols across 11 files)
FILE: sw/RetentionTest/RetentionTest.cpp
function writeRow (line 12) | void writeRow(fpga_t* fpga, uint row, uint bank, uint8_t pattern, Instru...
function readAndCompareRow (line 54) | void readAndCompareRow(fpga_t* fpga, const uint row, const uint bank, co...
function turnBus (line 110) | void turnBus(fpga_t* fpga, BUSDIR b, InstructionSequence* iseq = nullptr){
function testRetention (line 134) | void testRetention(fpga_t* fpga, const int retention){
function setRefreshConfig (line 217) | void setRefreshConfig(fpga_t* fpga, uint trefi, uint trfc){
function printHelp (line 232) | void printHelp(char* argv[]){
function main (line 238) | int main(int argc, char* argv[]){
FILE: sw/SoftMC_API/softmc.cpp
function Instruction (line 46) | Instruction genACT(uint bank, uint row){
function Instruction (line 66) | Instruction genPRE(uint bank, PRE_TYPE pc){
function Instruction (line 98) | Instruction genWR(uint bank, uint col, uint8_t pattern, AUTO_PRECHARGE a...
function Instruction (line 144) | Instruction genRD(uint bank, uint col, AUTO_PRECHARGE ap, BURST_LENGTH bl){
function Instruction (line 177) | Instruction genWAIT(uint cycles){ //min 1, max 1023
function Instruction (line 195) | Instruction genBUSDIR(BUSDIR dir){
function Instruction (line 207) | Instruction genEND(){
function Instruction (line 215) | Instruction genZQ(){
function Instruction (line 228) | Instruction genREF(){
function Instruction (line 248) | Instruction genREF_CONFIG(uint val, REGISTER r){
FILE: sw/SoftMC_API/softmc.h
type Instruction (line 35) | typedef uint64_t Instruction;
type uint (line 36) | typedef uint32_t uint;
type class (line 39) | enum class
type class (line 47) | enum class
type class (line 52) | enum class
type class (line 57) | enum class
type class (line 62) | enum class
function REGISTER (line 67) | enum class REGISTER {
FILE: sw/riffa_2.1/driver/linux/circ_queue.c
function circ_queue (line 56) | circ_queue * init_circ_queue(int len)
function queue_count_to_index (line 90) | unsigned int queue_count_to_index(unsigned int count, unsigned int len)
function push_circ_queue (line 95) | int push_circ_queue(circ_queue * q, unsigned int val1, unsigned int val2)
function pop_circ_queue (line 117) | int pop_circ_queue(circ_queue * q, unsigned int * val1, unsigned int * v...
function circ_queue_empty (line 153) | int circ_queue_empty(circ_queue * q)
function circ_queue_full (line 168) | int circ_queue_full(circ_queue * q)
function free_circ_queue (line 182) | void free_circ_queue(circ_queue * q)
FILE: sw/riffa_2.1/driver/linux/circ_queue.h
type circ_queue (line 58) | struct circ_queue {
type circ_queue (line 64) | typedef struct circ_queue circ_queue;
FILE: sw/riffa_2.1/driver/linux/riffa.c
type fpga_t (line 58) | struct fpga_t
function fpga_t (line 64) | fpga_t * fpga_open(int id)
function fpga_close (line 84) | void fpga_close(fpga_t * fpga)
function fpga_send (line 91) | int fpga_send(fpga_t * fpga, int chnl, void * data, int len, int destoff,
function fpga_recv (line 107) | int fpga_recv(fpga_t * fpga, int chnl, void * data, int len, long long t...
function fpga_reset (line 120) | void fpga_reset(fpga_t * fpga)
function fpga_list (line 125) | int fpga_list(fpga_info_list * list) {
FILE: sw/riffa_2.1/driver/linux/riffa.h
type fpga_t (line 60) | struct fpga_t
type fpga_t (line 61) | typedef struct fpga_t fpga_t;
FILE: sw/riffa_2.1/driver/linux/riffa_driver.c
type sg_mapping (line 84) | struct sg_mapping {
type chnl_dir (line 94) | struct chnl_dir {
type fpga_state (line 103) | struct fpga_state {
type class (line 125) | struct class
type fpga_state (line 128) | struct fpga_state
function read_reg (line 137) | static inline unsigned int read_reg(struct fpga_state * sc, int offset)
function write_reg (line 145) | static inline void write_reg(struct fpga_state * sc, int offset, unsigne...
function __udivdi3 (line 155) | unsigned long long __udivdi3(unsigned long long num, unsigned long long ...
function process_intr_vector (line 170) | static inline void process_intr_vector(struct fpga_state * sc, int off,
function irqreturn_t (line 278) | static irqreturn_t intrpt_handler(int irq, void *dev_id)
type sg_mapping (line 321) | struct sg_mapping
type fpga_state (line 321) | struct fpga_state
type dma_data_direction (line 323) | enum dma_data_direction
type sg_mapping (line 325) | struct sg_mapping
type page (line 326) | struct page
type scatterlist (line 327) | struct scatterlist
type scatterlist (line 328) | struct scatterlist
type sg_mapping (line 342) | struct sg_mapping
function free_sg_buf (line 424) | static inline void free_sg_buf(struct fpga_state * sc, struct sg_mapping...
function chnl_recv (line 467) | static inline unsigned int chnl_recv(struct fpga_state * sc, int chnl,
function chnl_send (line 644) | static inline unsigned int chnl_send(struct fpga_state * sc, int chnl,
function list_fpgas (line 785) | static inline int list_fpgas(fpga_info_list * list)
function reset (line 819) | static inline void reset(int id)
function fpga_ioctl (line 849) | static long fpga_ioctl(struct file *filp, unsigned int ioctlnum,
function allocate_chnls (line 897) | static inline int __devinit allocate_chnls(struct pci_dev *dev, struct f...
function fpga_probe (line 958) | static int __devinit fpga_probe(struct pci_dev *dev, const struct pci_de...
function fpga_remove (line 1297) | static void __devexit fpga_remove(struct pci_dev *dev)
type pci_driver (line 1348) | struct pci_driver
type file_operations (line 1355) | struct file_operations
function fpga_init (line 1363) | static int __init fpga_init(void)
function fpga_exit (line 1399) | static void __exit fpga_exit(void)
FILE: sw/riffa_2.1/driver/linux/riffa_driver.h
type fpga_chnl_io (line 107) | struct fpga_chnl_io
type fpga_chnl_io (line 117) | typedef struct fpga_chnl_io fpga_chnl_io;
type fpga_info_list (line 119) | struct fpga_info_list
type fpga_info_list (line 128) | typedef struct fpga_info_list fpga_info_list;
FILE: sw/riffa_2.1/driver/windows/sys/riffa.c
function NTSTATUS (line 39) | NTSTATUS DriverEntry(IN PDRIVER_OBJECT DriverObject, IN PUNICODE_STRING...
function NTSTATUS (line 94) | NTSTATUS RiffaEvtDeviceAdd(IN WDFDRIVER Driver, IN PWDFDEVICE_INIT Devic...
function VOID (line 208) | VOID RiffaEvtDriverContextCleanup(IN WDFDRIVER Driver) {
function NTSTATUS (line 231) | NTSTATUS RiffaEvtDevicePrepareHardware(WDFDEVICE Device, WDFCMRESLIST Re...
function NTSTATUS (line 484) | NTSTATUS RiffaEvtDeviceReleaseHardware(IN WDFDEVICE Device, IN WDFCMRESL...
function NTSTATUS (line 514) | NTSTATUS RiffaReadHardwareIds(IN PDEVICE_EXTENSION DevExt) {
function BOOLEAN (line 616) | BOOLEAN RiffaEvtInterruptIsr(IN WDFINTERRUPT Interrupt, IN ULONG Message...
function BOOLEAN (line 669) | BOOLEAN RiffaProcessInterrupt(IN PDEVICE_EXTENSION DevExt, IN UINT32 Off...
function VOID (line 737) | VOID RiffaEvtInterruptDpc(IN WDFINTERRUPT Interrupt, IN WDFDEVICE Device) {
function VOID (line 904) | VOID RiffaEvtIoDeviceControl(IN WDFQUEUE Queue, IN WDFREQUEST Request,
function VOID (line 953) | VOID RiffaIoctlSend(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,
function VOID (line 1077) | VOID RiffaIoctlRecv(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,
function VOID (line 1222) | VOID RiffaIoctlList(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request,
function VOID (line 1314) | VOID RiffaIoctlReset(IN PDEVICE_EXTENSION DevExt, IN WDFREQUEST Request) {
function BOOLEAN (line 1364) | BOOLEAN RiffaThreadEnter(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl) {
function VOID (line 1391) | VOID RiffaThreadExit(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl) {
function VOID (line 1417) | VOID RiffaCompleteRequest(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl,
function VOID (line 1445) | VOID RiffaEvtRequestCancel(IN WDFREQUEST Request) {
function VOID (line 1496) | VOID RiffaEvtTimerFunc(IN WDFTIMER Timer) {
function VOID (line 1571) | VOID RiffaStartRecvTransaction(IN PDEVICE_EXTENSION DevExt, IN UINT32 Ch...
function NTSTATUS (line 1641) | NTSTATUS RiffaStartDmaTransaction(IN PDEVICE_EXTENSION DevExt, IN UINT32...
function VOID (line 1707) | VOID RiffaProgramScatterGather(IN PDEVICE_EXTENSION DevExt, IN UINT32 Ch...
function VOID (line 1827) | VOID RiffaTransactionComplete(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl,
function VOID (line 1900) | VOID RiffaProgramSend(IN PDEVICE_EXTENSION DevExt, IN UINT32 Chnl, IN UI...
function BOOLEAN (line 1935) | BOOLEAN RiffaEvtProgramDma(IN WDFDMATRANSACTION Transaction, IN WDFDEVIC...
FILE: sw/riffa_2.1/driver/windows/sys/riffa_private.h
type RIFFA_FPGA_CHNL_IO (line 46) | typedef struct RIFFA_FPGA_CHNL_IO {
type RIFFA_FPGA_INFO (line 56) | typedef struct RIFFA_FPGA_INFO {
type CHNL_DIR_STATE (line 66) | typedef struct CHNL_DIR_STATE {
type INTR_CHNL_DIR_DATA (line 94) | typedef struct INTR_CHNL_DIR_DATA {
type DEVICE_EXTENSION (line 103) | typedef struct _DEVICE_EXTENSION {
type REQUEST_EXTENSION (line 123) | typedef struct _REQUEST_EXTENSION {
type TIMER_EXTENSION (line 128) | typedef struct _TIMER_EXTENSION {
Condensed preview — 163 files, each showing path, character count, and a content snippet. Download the .json file or copy for the full structured content (1,791K chars).
[
{
"path": "LICENSE",
"chars": 1114,
"preview": "Copyright (c) [2017] [SAFARI Research Group at Carnegie Mellon University and ETH Zurich]\n\nPermission is hereby granted,"
},
{
"path": "README.md",
"chars": 5299,
"preview": "## [DRAM Bender](https://github.com/CMU-SAFARI/DRAM-Bender) (a.k.a. SoftMC v2) supersedes SoftMC. We suggest that you us"
},
{
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"chars": 65773,
"preview": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<project xmlns=\"http://www.xilinx.com/XMLSchema\" xmlns:xil_pn=\"h"
},
{
"path": "hw/boards/ML605/apply_patches.sh",
"chars": 54,
"preview": "for f in ./patches/*.patch\ndo\n patch -p0 < $f\ndone\n"
},
{
"path": "hw/boards/ML605/autoref_config.v",
"chars": 577,
"preview": "`timescale 1ns / 1ps\n//Hasan\n\nmodule autoref_config(\n\t\tinput clk,\n\t\tinput rst,\n\t\t\n\t\tinput set_interval,\n\t\tinput[27:0] in"
},
{
"path": "hw/boards/ML605/instr_decoder.v",
"chars": 866,
"preview": "`timescale 1ns / 1ps\n\n`include \"softMC.inc\"\n\nmodule instr_decoder #(parameter ROW_WIDTH = 15, BANK_WIDTH = 3, CS_WIDTH ="
},
{
"path": "hw/boards/ML605/instr_dispatcher.v",
"chars": 9714,
"preview": "`timescale 1ns / 1ps\n\n`include \"softMC.inc\"\n\nmodule instr_dispatcher #(parameter ROW_WIDTH = 15, BANK_WIDTH = 3, CKE_WID"
},
{
"path": "hw/boards/ML605/instr_receiver.v",
"chars": 2394,
"preview": "`timescale 1ns / 1ps\n\n`include \"softMC.inc\"\n\nmodule instr_receiver (\r\n\tinput clk,\r\n\tinput rst,\n\t\n\tinput dispatcher_ready"
},
{
"path": "hw/boards/ML605/ipcore_dir/instr_fifo.xco",
"chars": 7106,
"preview": "##############################################################\n#\n# Xilinx Core Generator version 14.6\n# Date: Fri Feb 3"
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"chars": 14637,
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"chars": 8938,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
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{
"path": "hw/boards/ML605/ipcore_dir/riffa/async_fifo_fwft.v",
"chars": 5036,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
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{
"path": "hw/boards/ML605/ipcore_dir/riffa/axi_basic_rx.v",
"chars": 8364,
"preview": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, In"
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"path": "hw/boards/ML605/ipcore_dir/riffa/axi_basic_rx_null_gen.v",
"chars": 15673,
"preview": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, In"
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{
"path": "hw/boards/ML605/ipcore_dir/riffa/axi_basic_rx_pipeline.v",
"chars": 26810,
"preview": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, In"
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{
"path": "hw/boards/ML605/ipcore_dir/riffa/axi_basic_top.v",
"chars": 11105,
"preview": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, In"
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{
"path": "hw/boards/ML605/ipcore_dir/riffa/axi_basic_tx.v",
"chars": 10085,
"preview": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, In"
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"chars": 22519,
"preview": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, In"
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"path": "hw/boards/ML605/ipcore_dir/riffa/axi_basic_tx_thrtl_ctl.v",
"chars": 29542,
"preview": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, In"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/channel_128.v",
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"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
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{
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"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
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"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
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"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
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"path": "hw/boards/ML605/ipcore_dir/riffa/pcie_2_0_v6.v",
"chars": 80152,
"preview": "//-----------------------------------------------------------------------------\n//\n// (c) Copyright 2009-2011 Xilinx, In"
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"path": "hw/boards/ML605/ipcore_dir/riffa/ram_1clk_1w_1r.v",
"chars": 3230,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/ram_2clk_1w_1r.v",
"chars": 3291,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/recv_credit_flow_ctrl.v",
"chars": 4511,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/reorder_queue.v",
"chars": 7655,
"preview": "`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// "
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/reorder_queue_input.v",
"chars": 11409,
"preview": "`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// "
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/reorder_queue_output.v",
"chars": 7633,
"preview": "`timescale 1ns / 1ps\n//////////////////////////////////////////////////////////////////////////////////\n// Company: \n// "
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/riffa_adapter_v6_pcie_v2_5.v",
"chars": 16532,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/riffa_endpoint.v",
"chars": 17856,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/riffa_endpoint_128.v",
"chars": 21666,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/riffa_endpoint_32.v",
"chars": 21392,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/riffa_endpoint_64.v",
"chars": 21511,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/riffa_top_v6_pcie_v2_5.v",
"chars": 18317,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/rx_engine_128.v",
"chars": 21662,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/rx_engine_32.v",
"chars": 15774,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/rx_engine_64.v",
"chars": 16316,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/rx_engine_req.v",
"chars": 7109,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/rx_port_128.v",
"chars": 14807,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/rx_port_32.v",
"chars": 14800,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/rx_port_64.v",
"chars": 14800,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/rx_port_channel_gate.v",
"chars": 6000,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/rx_port_reader.v",
"chars": 18187,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/rx_port_requester_mux.v",
"chars": 6655,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/sg_list_reader_128.v",
"chars": 4927,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/sg_list_reader_32.v",
"chars": 5821,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/sg_list_reader_64.v",
"chars": 5283,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/sg_list_requester.v",
"chars": 9746,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/sync_fifo.v",
"chars": 5869,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/syncff.v",
"chars": 2743,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/translation_layer.v",
"chars": 18636,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/translation_layer_128.v",
"chars": 16748,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/translation_layer_32.v",
"chars": 10436,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/translation_layer_64.v",
"chars": 17120,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_128.v",
"chars": 7665,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_32.v",
"chars": 7568,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_64.v",
"chars": 7638,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_formatter_128.v",
"chars": 5690,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_formatter_32.v",
"chars": 6430,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_formatter_64.v",
"chars": 6130,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_lower_128.v",
"chars": 11028,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_lower_32.v",
"chars": 11773,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_lower_64.v",
"chars": 11691,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_selector.v",
"chars": 4618,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_upper_128.v",
"chars": 15762,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_upper_32.v",
"chars": 15311,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_engine_upper_64.v",
"chars": 15462,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_128.v",
"chars": 8104,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_32.v",
"chars": 7824,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_64.v",
"chars": 8085,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_buffer_128.v",
"chars": 8004,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_buffer_32.v",
"chars": 3972,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_buffer_64.v",
"chars": 7844,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_channel_gate_128.v",
"chars": 6838,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_channel_gate_32.v",
"chars": 6820,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_channel_gate_64.v",
"chars": 6807,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_monitor_128.v",
"chars": 7958,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_monitor_32.v",
"chars": 8277,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_monitor_64.v",
"chars": 7938,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_port_writer.v",
"chars": 17980,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_qword_aligner_128.v",
"chars": 15202,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/riffa/tx_qword_aligner_64.v",
"chars": 14248,
"preview": "`timescale 1ns/1ns\n//----------------------------------------------------------------------------\n// This software is Co"
},
{
"path": "hw/boards/ML605/ipcore_dir/xilinx_mig/example_design/mig.prj",
"chars": 3160,
"preview": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<Project NoOfControllers=\"1\" >\n <ModuleName>xilinx_mig</ModuleName>\n <dci_i"
},
{
"path": "hw/boards/ML605/ipcore_dir/xilinx_mig/user_design/mig.prj",
"chars": 3160,
"preview": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<Project NoOfControllers=\"1\" >\n <ModuleName>xilinx_mig</ModuleName>\n <dci_i"
},
{
"path": "hw/boards/ML605/ipcore_dir/xilinx_mig.xco",
"chars": 1412,
"preview": "##############################################################\n#\n# Xilinx Core Generator version 14.6\n# Date: Fri Feb 3"
},
{
"path": "hw/boards/ML605/ipcore_dir/xilinx_mig.xise",
"chars": 28792,
"preview": "<?xml version=\"1.0\" encoding=\"UTF-8\" standalone=\"no\" ?>\n<project xmlns=\"http://www.xilinx.com/XMLSchema\" xmlns:xil_pn=\"h"
},
{
"path": "hw/boards/ML605/iseq_dispatcher.v",
"chars": 4468,
"preview": "`timescale 1ns / 1ps\n\nmodule iseq_dispatcher #(parameter ROW_WIDTH = 15, BANK_WIDTH = 3, CKE_WIDTH = 1, \r\n\t\t\t\t\t\t\t\t\t\tCS_W"
},
{
"path": "hw/boards/ML605/maint_ctrl.v",
"chars": 8316,
"preview": "`timescale 1ps / 1ps\r\n//Hasan\r\n\r\nmodule maint_ctrl_top #(parameter RANK_WIDTH = 1, TCQ = 100, tCK = 2500, nCK_PER_CLK = "
},
{
"path": "hw/boards/ML605/maint_handler.v",
"chars": 9894,
"preview": "`timescale 1ps / 1ps\r\n\r\n`include \"softMC.inc\"\r\n\r\nmodule maint_handler #(parameter CS_WIDTH = 1)(\r\n\t\t\tinput clk,\r\n\t\t\tinpu"
},
{
"path": "hw/boards/ML605/patches/iodelay_ctrl.patch",
"chars": 260,
"preview": "--- ipcore_dir/xilinx_mig/user_design/rtl/ip_top/iodelay_ctrl.v\n@@ -94,1 +94,2 @@\n input sys_rst,\n+ output clk_200"
},
{
"path": "hw/boards/ML605/patches/phy_rdctrl_sync.patch",
"chars": 1742,
"preview": "--- ipcore_dir/xilinx_mig/user_design/rtl/phy/phy_rdctrl_sync.v\t2017-02-03 15:11:19.000000000 +0100\n@@ -91,4 +91,8 @@\n "
},
{
"path": "hw/boards/ML605/patches/phy_read.patch",
"chars": 896,
"preview": "--- ipcore_dir/xilinx_mig/user_design/rtl/phy/phy_read.v\t2017-02-03 15:11:19.000000000 +0100\n@@ -129,4 +129,8 @@\n inp"
},
{
"path": "hw/boards/ML605/patches/phy_top.patch",
"chars": 1341,
"preview": "--- ipcore_dir/xilinx_mig/user_design/rtl/phy/phy_top.v\t2017-02-03 15:11:19.000000000 +0100\n@@ -93,1 +93,1 @@\n- parame"
},
{
"path": "hw/boards/ML605/pipe_reg.v",
"chars": 1414,
"preview": "`timescale 1ps / 1ps\n\nmodule pipe_reg #(parameter WIDTH = 8) (\n input clk,\n input rst,\n \n in"
},
{
"path": "hw/boards/ML605/read_capturer.v",
"chars": 1305,
"preview": "`timescale 1ns / 1ps\n\nmodule read_capturer #(parameter DQ_WIDTH = 64) (\r\n\tinput clk,\r\n\tinput rst,\n\t\n\t//DFI Interface\r\n\ti"
},
{
"path": "hw/boards/ML605/softMC.inc",
"chars": 641,
"preview": "//uncomment the line below to run a simulation using \"tb_softMC_top\"\n//`define SIM\n\n`define tCK 2500\n\n// instruction opc"
},
{
"path": "hw/boards/ML605/softMC.v",
"chars": 8428,
"preview": "`timescale 1ps / 1ps\r\n\n`include \"softMC.inc\"\n\n//NOTE: currently accepts only one instruction sequence, need to process i"
},
{
"path": "hw/boards/ML605/softMC_constraints.ucf",
"chars": 24416,
"preview": "############################################################################\n# Timing constraints "
},
{
"path": "hw/boards/ML605/softMC_pcie_app.v",
"chars": 2875,
"preview": "`timescale 1ns / 1ps\n\nmodule softMC_pcie_app #(\n\tparameter C_PCI_DATA_WIDTH = 9'd32, DQ_WIDTH = 64\n)(\n\tinput clk,\n\tinput"
},
{
"path": "hw/boards/ML605/softMC_top.v",
"chars": 17619,
"preview": "`timescale 1ps / 1ps\n\n`include \"softMC.inc\"\n\nmodule softMC_top #\n (\n\tparameter TCQ = 100,\n\tparameter tCK = "
},
{
"path": "hw/boards/ML605/tb_softMC_top.v",
"chars": 36941,
"preview": "`timescale 1ps / 1ps\n\n`include \"softMC.inc\"\n\nmodule tb_softMC_top;\n\t\n parameter REFCLK_FREQ = 200;\n "
},
{
"path": "sw/RetentionTest/Makefile",
"chars": 754,
"preview": "program_NAME := SoftMC_RetentionTest\nprogram_CXX_SRCS := $(wildcard *.cpp) $(wildcard ../SoftMC_API/*.cpp)\nprogram_CXX_O"
},
{
"path": "sw/RetentionTest/RetentionTest.cpp",
"chars": 8274,
"preview": "#include <stdio.h>\n#include <riffa.h>\n#include <cassert>\n#include <string.h>\n#include <iostream>\n#include <cmath>\n#inclu"
},
{
"path": "sw/SoftMC_API/softmc.cpp",
"chars": 7252,
"preview": "#include \"softmc.h\"\n#include <fstream>\n#include <iostream>\n#include <cassert>\n\nusing namespace std;\n\nInstructionSequence"
},
{
"path": "sw/SoftMC_API/softmc.h",
"chars": 2417,
"preview": "#ifndef SOFTMC_H\n#define SOFTMC_H\n\n#include <unistd.h>\n#include <stdint.h>\n#include <stdlib.h>\n#include <vector>\n#includ"
},
{
"path": "sw/riffa_2.1/LICENSE",
"chars": 1733,
"preview": "----------------------------------------------------------------------\nCopyright (c) 2016, The Regents of the University"
},
{
"path": "sw/riffa_2.1/README.txt",
"chars": 3305,
"preview": "To install RIFFA 2.0, find the instructions in the install directory for your\nos. The source directory contains all the "
},
{
"path": "sw/riffa_2.1/driver/linux/Makefile",
"chars": 5912,
"preview": "# This software is Copyright © 2012 The Regents of the University of \n# California. All Rights Reserved.\n# \n# Permission"
},
{
"path": "sw/riffa_2.1/driver/linux/README.txt",
"chars": 1490,
"preview": "You must build the Linux driver against the version of the Linux kernel you have\ninstalled. This will require the Linux "
},
{
"path": "sw/riffa_2.1/driver/linux/circ_queue.c",
"chars": 6301,
"preview": "/*******************************************************************************\n * This software is Copyright © 2012 Th"
},
{
"path": "sw/riffa_2.1/driver/linux/circ_queue.h",
"chars": 3845,
"preview": "/*******************************************************************************\n * This software is Copyright © 2012 Th"
},
{
"path": "sw/riffa_2.1/driver/linux/riffa.c",
"chars": 3585,
"preview": "/*******************************************************************************\n * This software is Copyright © 2012 Th"
},
{
"path": "sw/riffa_2.1/driver/linux/riffa.h",
"chars": 5195,
"preview": "/*******************************************************************************\n * This software is Copyright © 2012 Th"
},
{
"path": "sw/riffa_2.1/driver/linux/riffa_driver.c",
"chars": 45700,
"preview": "/*******************************************************************************\n * This software is Copyright © 2012 Th"
},
{
"path": "sw/riffa_2.1/driver/linux/riffa_driver.h",
"chars": 4917,
"preview": "/*******************************************************************************\n * This software is Copyright © 2012 Th"
},
{
"path": "sw/riffa_2.1/driver/windows/README.txt",
"chars": 2239,
"preview": "To build the Windows driver:\r\n\r\n1) Install Windows Driver Development Kit supporting Windows 7 (tested on \r\n version 7"
},
{
"path": "sw/riffa_2.1/driver/windows/dirs",
"chars": 17,
"preview": "DIRS= \\\r\n sys"
},
{
"path": "sw/riffa_2.1/driver/windows/install/install.bat",
"chars": 748,
"preview": "@echo off\r\n\r\nrmdir /s /q build\r\nmd build\r\nmd build\\x86\r\nmd build\\x64\r\n\r\ncopy win7.iss .\\build\r\ncopy license.txt .\\build\r"
},
{
"path": "sw/riffa_2.1/driver/windows/install/license.txt",
"chars": 1775,
"preview": "This software is Copyright 2012 The Regents of the University of California. All Rights Reserved.\n\nPermission to copy, "
},
{
"path": "sw/riffa_2.1/driver/windows/install/win7.iss",
"chars": 4434,
"preview": "; -- 64Bit.iss --\r\n; Demonstrates installation of a program built for the x64 (a.k.a. AMD64)\r\n; architecture.\r\n; To succ"
},
{
"path": "sw/riffa_2.1/driver/windows/sys/makefile",
"chars": 249,
"preview": "#\r\n# DO NOT EDIT THIS FILE!!! Edit .\\sources. if you want to add a new source\r\n# file to this component. This file mer"
},
{
"path": "sw/riffa_2.1/driver/windows/sys/makefile.inc",
"chars": 1078,
"preview": "_LNG=$(LANGUAGE)\r\n_INX=.\r\nSTAMP=stampinf -f $@ -a $(_BUILDARCH) -k $(KMDF_VERSION_MAJOR).$(KMDF_VERSION_MINOR)\r\n\r\n\r\n$(OB"
},
{
"path": "sw/riffa_2.1/driver/windows/sys/precomp.h",
"chars": 450,
"preview": "#define WIN9X_COMPAT_SPINLOCK\r\n#include <ntddk.h>\r\n#pragma warning(disable:4201) // nameless struct/union warning\r\n\r\n#i"
},
{
"path": "sw/riffa_2.1/driver/windows/sys/riffa.c",
"chars": 73645,
"preview": "#include \"precomp.h\"\r\n\r\n// The trace message header (.tmh) file must be included in a source file\r\n// before any WPP mac"
},
{
"path": "sw/riffa_2.1/driver/windows/sys/riffa.inx",
"chars": 3256,
"preview": "\r\n[Version]\r\nSignature=\"$WINDOWS NT$\"\r\nClass=FPGA\r\nClassGuid={78A1C341-4539-11d3-B88D-00C04FAD5171}\r\nProvider=%UCSD%\r\nDr"
},
{
"path": "sw/riffa_2.1/driver/windows/sys/riffa.rc",
"chars": 336,
"preview": "#include <windows.h>\r\n\r\n#include <ntverp.h>\r\n\r\n#define VER_FILETYPE VFT_DRV\r\n#define VER_FILESUBTYPE "
},
{
"path": "sw/riffa_2.1/driver/windows/sys/riffa_driver.h",
"chars": 791,
"preview": "//\r\n// The following value is arbitrarily chosen from the space defined\r\n// by Microsoft as being \"for non-Microsoft use"
},
{
"path": "sw/riffa_2.1/driver/windows/sys/riffa_private.h",
"chars": 6611,
"preview": "#if !defined(_RIFFA_H_)\r\n#define _RIFFA_H_\r\n\r\n// Adjusts register offsets for each channel\r\n#define CHNL_REG(c, o) (((c)"
},
{
"path": "sw/riffa_2.1/driver/windows/sys/sources",
"chars": 1088,
"preview": "TARGETNAME=riffa\r\nTARGETTYPE=DRIVER\r\n\r\n\r\nKMDF_VERSION_MAJOR=1\r\n\r\nINF_NAME=riffa\r\nNTTARGETFILE0=$(OBJ_PATH)\\$(O)\\$(INF_NA"
},
{
"path": "sw/riffa_2.1/driver/windows/sys/trace.h",
"chars": 1347,
"preview": "#include <evntrace.h> // For TRACE_LEVEL definitions\r\n\r\n//\r\n// If software tracing is defined in the sources file..\r\n// "
},
{
"path": "sw/riffa_2.1/driver/windows/win7install.bat",
"chars": 242,
"preview": "@echo off\r\n\r\nset OLDDIR=%CD%\r\nset BDIR1=%CD%\\sys\\obj%_BUILDTYPE%_%DDK_TARGET_OS%_x86\\i386\r\nset BDIR2=%CD%\\sys\\obj%_BUILD"
}
]
// ... and 2 more files (download for full content)
About this extraction
This page contains the full source code of the CMU-SAFARI/SoftMC GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 163 files (1.6 MB), approximately 504.5k tokens, and a symbol index with 110 extracted functions, classes, methods, constants, and types. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.
Extracted by GitExtract — free GitHub repo to text converter for AI. Built by Nikandr Surkov.