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Repository: FlyGoat/CSMWrap
Branch: main
Commit: 808ac8ea5393
Files: 80
Total size: 1.4 MB
Directory structure:
gitextract_bu0ihczz/
├── .github/
│ ├── dependabot.yml
│ └── workflows/
│ └── build.yml
├── .gitignore
├── .gitmodules
├── GNUmakefile
├── LICENSE
├── README.md
├── seabios-config
└── src/
├── acpi.c
├── ap_trampoline.asm
├── apic.c
├── apic.h
├── arch/
│ ├── ia32/
│ │ └── Thunk16.asm
│ └── x86_64/
│ └── Thunk16.asm
├── bios_proxy.c
├── bios_proxy.h
├── bootdev.c
├── bootdev.h
├── config.c
├── config.h
├── coreboot.c
├── csmwrap.c
├── csmwrap.h
├── e820.c
├── edk2/
│ ├── Acpi.h
│ ├── Acpi10.h
│ ├── Acpi20.h
│ ├── Acpi30.h
│ ├── Acpi40.h
│ ├── Acpi50.h
│ ├── Acpi51.h
│ ├── Acpi60.h
│ ├── Acpi61.h
│ ├── Acpi62.h
│ ├── Acpi63.h
│ ├── Acpi64.h
│ ├── Acpi65.h
│ ├── AcpiAml.h
│ ├── Coreboot.h
│ ├── E820.h
│ ├── Edk2Compat.h
│ ├── LegacyBios.h
│ ├── LegacyRegion2.h
│ ├── Pci.h
│ ├── Pci22.h
│ ├── Pci23.h
│ ├── Pci30.h
│ ├── PciCodeId.h
│ ├── PciExpress21.h
│ ├── PciExpress30.h
│ ├── PciExpress31.h
│ ├── PciExpress40.h
│ ├── PciExpress50.h
│ └── PciExpress60.h
├── intel_workarounds.c
├── io.h
├── iommu.c
├── iommu.h
├── libc.c
├── libc.h
├── mptable.c
├── mptable.h
├── oprom.c
├── oprom.h
├── pci.c
├── pci.h
├── pir.c
├── pir.h
├── printf.c
├── printf.h
├── qsort.c
├── qsort.h
├── time.c
├── time.h
├── uacpi_config.h
├── unlock_region.c
├── video.c
├── video.h
├── x86thunk.c
└── x86thunk.h
================================================
FILE CONTENTS
================================================
================================================
FILE: .github/dependabot.yml
================================================
version: 2
updates:
- package-ecosystem: github-actions
directory: "/"
schedule:
interval: "daily"
target-branch: main
================================================
FILE: .github/workflows/build.yml
================================================
name: Build
on:
push:
branches: ['**']
tags: ['[0-9]*']
pull_request:
workflow_dispatch:
jobs:
build:
runs-on: ubuntu-latest
container: archlinux:latest
permissions:
contents: write
steps:
- name: Install distro deps
run: pacman --noconfirm -Syu && pacman --needed --noconfirm -S base-devel python git vim nasm
- name: Mark workspace safe for git
run: git config --global --add safe.directory '*'
- uses: actions/checkout@v6
with:
submodules: true
fetch-depth: 0
fetch-tags: true
- name: make x86_64
run: |
make ARCH=x86_64
mkdir -p bin
cp bin-x86_64/csmwrap.efi bin/csmwrapx64.efi
- name: make ia32
run: |
make ARCH=ia32
mkdir -p bin
cp bin-ia32/csmwrap.efi bin/csmwrapia32.efi
- uses: actions/upload-artifact@v7
with:
name: csmwrap.efi
path: bin/*.efi
- name: Create draft release
if: startsWith(github.ref, 'refs/tags/')
uses: softprops/action-gh-release@v3
with:
draft: true
fail_on_unmatched_files: true
files: |
bin/csmwrapx64.efi
bin/csmwrapia32.efi
================================================
FILE: .gitignore
================================================
/compile_commands.json
/.cache
/boot
/edk2-ovmf
/src/bins
/bin-*
/obj-*
================================================
FILE: .gitmodules
================================================
[submodule "freestnd-c-hdrs"]
path = freestnd-c-hdrs
url = https://github.com/osdev0/freestnd-c-hdrs-0bsd.git
[submodule "cc-runtime"]
path = cc-runtime
url = https://github.com/osdev0/cc-runtime.git
[submodule "picoefi"]
path = picoefi
url = https://github.com/PicoEFI/PicoEFI.git
[submodule "nanoprintf"]
path = nanoprintf
url = https://github.com/charlesnicholson/nanoprintf.git
[submodule "seabios"]
path = seabios
url = https://github.com/CSMWrap/seabios-csmwrap.git
[submodule "uACPI"]
path = uACPI
url = https://github.com/uACPI/uACPI.git
[submodule "flanterm"]
path = flanterm
url = https://github.com/Mintsuki/Flanterm.git
================================================
FILE: GNUmakefile
================================================
# Nuke built-in rules.
.SUFFIXES:
# This is the name that our final executable will have.
# Change as needed.
override OUTPUT := csmwrap
# Target architecture to build for. Default to x86_64.
ARCH := x86_64
# Install prefix; /usr/local is a good, standard default pick.
PREFIX := /usr/local
# Check if the architecture is supported.
ifeq ($(filter $(ARCH),ia32 x86_64),)
$(error Architecture $(ARCH) not supported)
endif
# Default user QEMU flags. These are appended to the QEMU command calls.
QEMUFLAGS := -m 2G -smp 2
# User controllable host C compiler.
HOST_CC := cc
# User controllable toolchain and toolchain prefix.
TOOLCHAIN :=
TOOLCHAIN_PREFIX :=
ifneq ($(TOOLCHAIN),)
ifeq ($(TOOLCHAIN_PREFIX),)
TOOLCHAIN_PREFIX := $(TOOLCHAIN)-
endif
endif
# User controllable C compiler command.
ifneq ($(TOOLCHAIN_PREFIX),)
CC := $(TOOLCHAIN_PREFIX)gcc
else
CC := cc
endif
# User controllable linker command.
LD := $(TOOLCHAIN_PREFIX)ld
# User controllable objcopy command.
OBJCOPY := $(TOOLCHAIN_PREFIX)objcopy
# User controllable objdump command.
OBJDUMP := $(TOOLCHAIN_PREFIX)objdump
# User controllable strip command.
STRIP := $(TOOLCHAIN_PREFIX)strip
# Defaults overrides for variables if using "llvm" as toolchain.
ifeq ($(TOOLCHAIN),llvm)
CC := clang
LD := ld.lld
endif
# User controllable C flags.
CFLAGS := -g -O2 -pipe
# User controllable C preprocessor flags. We set none by default.
CPPFLAGS :=
# User controllable nasm flags.
NASMFLAGS := -g
# User controllable linker flags. We set none by default.
LDFLAGS :=
# User controllable version string.
BUILD_VERSION := $(shell git describe --tags --always 2>/dev/null || echo "Unknown")
# Check if CC is Clang.
override CC_IS_CLANG := $(shell ! $(CC) --version 2>/dev/null | grep -q '^Target: '; echo $$?)
# Save user CFLAGS, CPPFLAGS, and LDFLAGS before we append internal flags.
override USER_CFLAGS := $(CFLAGS)
override USER_CPPFLAGS := $(CPPFLAGS)
override USER_LDFLAGS := $(LDFLAGS)
override define SEABIOS_CALL
$(MAKE) -C seabios $(1) \
HOSTCC="$(HOST_CC)" \
CC="$(CC)" \
LD="$(LD)" \
OBJCOPY="$(OBJCOPY)" \
OBJDUMP="$(OBJDUMP)" \
STRIP="$(STRIP)" \
CFLAGS="$(USER_CFLAGS)" \
CPPFLAGS="$(USER_CPPFLAGS)" \
LDFLAGS="$(USER_LDFLAGS)" \
EXTRAVERSION=\"$(SEABIOS_EXTRAVERSION)\"
endef
# Internal C flags that should not be changed by the user.
override CFLAGS += \
-Wall \
-Wextra \
-std=gnu11 \
-nostdinc \
-ffreestanding \
-fno-stack-protector \
-fno-stack-check \
-fno-delete-null-pointer-checks \
-fshort-wchar \
-fno-lto \
-fPIE \
-ffunction-sections \
-fdata-sections
# Internal C preprocessor flags that should not be changed by the user.
override CPPFLAGS := \
-I src \
-I picoefi/inc \
-I flanterm/src \
-I uACPI/include \
-DUACPI_OVERRIDE_CONFIG \
-DBUILD_VERSION=\"$(BUILD_VERSION)\" \
-isystem freestnd-c-hdrs/include \
$(CPPFLAGS) \
-MMD \
-MP
obj-$(ARCH)/flanterm/src/flanterm_backends/fb.c.o: override CPPFLAGS += \
-DFLANTERM_FB_DISABLE_BUMP_ALLOC
# Internal nasm flags that should not be changed by the user.
override NASMFLAGS := \
$(patsubst -g,-g -F dwarf,$(NASMFLAGS)) \
-Wall
# Architecture specific internal flags.
ifeq ($(ARCH),ia32)
ifeq ($(CC_IS_CLANG),1)
override CC += \
-target i686-unknown-none-elf
endif
override CFLAGS += \
-m32 \
-march=i686 \
-mabi=sysv \
-mno-80387 \
-mno-mmx \
-malign-double
override LDFLAGS += \
-m elf_i386
override NASMFLAGS := \
-f elf32 \
$(NASMFLAGS)
endif
ifeq ($(ARCH),x86_64)
ifeq ($(CC_IS_CLANG),1)
override CC += \
-target x86_64-unknown-none-elf
endif
override CFLAGS += \
-m64 \
-march=x86-64 \
-mabi=sysv \
-mno-80387 \
-mno-mmx \
-mno-sse \
-mno-sse2 \
-mno-red-zone
override LDFLAGS += \
-m elf_x86_64
override NASMFLAGS := \
-f elf64 \
$(NASMFLAGS)
endif
# Internal linker flags that should not be changed by the user.
override LDFLAGS += \
-nostdlib \
-pie \
-z text \
-z max-page-size=0x1000 \
--gc-sections \
-T picoefi/$(ARCH)/link_script.lds
# Use "find" to glob all *.c, *.S, and *.asm files in the tree
# (except the src/arch/* directories, as those are gonna be added
# in the next step).
override SRCFILES := $(shell find -L src cc-runtime/src picoefi/$(ARCH) flanterm/src uACPI/source -type f -not -path 'src/arch/*' 2>/dev/null | LC_ALL=C sort)
# Add architecture specific files, if they exist.
override SRCFILES += $(shell find -L src/arch/$(ARCH) -type f 2>/dev/null | LC_ALL=C sort)
# Obtain the object and header dependencies file names.
override CFILES := $(filter %.c,$(SRCFILES))
override ASFILES := $(filter %.S,$(SRCFILES))
ifneq ($(filter $(ARCH),ia32 x86_64),)
override NASMFILES := $(filter %.asm,$(SRCFILES))
endif
override OBJ := $(addprefix obj-$(ARCH)/,$(CFILES:.c=.c.o) $(ASFILES:.S=.S.o))
ifneq ($(filter $(ARCH),ia32 x86_64),)
override OBJ += $(addprefix obj-$(ARCH)/,$(NASMFILES:.asm=.asm.o))
endif
override HEADER_DEPS := $(addprefix obj-$(ARCH)/,$(CFILES:.c=.c.d) $(ASFILES:.S=.S.d))
# Default target. This must come first, before header dependencies.
.PHONY: all
all:
$(MAKE) seabios
$(MAKE) bin-$(ARCH)/$(OUTPUT).efi
# Include header dependencies.
-include $(HEADER_DEPS)
obj-$(ARCH)/src/csmwrap.c.o: src/bins/Csm16.h
obj-$(ARCH)/src/video.c.o: src/bins/vgabios.h
obj-$(ARCH)/src/printf.c.o: override CPPFLAGS += \
-I nanoprintf
# Rule to convert the final ELF executable to a .EFI PE executable.
bin-$(ARCH)/$(OUTPUT).efi: bin-$(ARCH)/$(OUTPUT) GNUmakefile
mkdir -p "$(dir $@)"
$(OBJCOPY) -O binary $< $@
dd if=/dev/zero of=$@ bs=4096 count=0 seek=$$(( ($$(wc -c < $@) + 4095) / 4096 )) 2>/dev/null
# Link rules for the final executable.
bin-$(ARCH)/$(OUTPUT): GNUmakefile picoefi/$(ARCH)/link_script.lds $(OBJ)
mkdir -p "$(dir $@)"
$(LD) $(LDFLAGS) $(OBJ) -o $@
# Compilation rules for *.c files.
obj-$(ARCH)/%.c.o: %.c GNUmakefile
mkdir -p "$(dir $@)"
$(CC) $(CFLAGS) $(CPPFLAGS) -c $< -o $@
# Compilation rules for *.S files.
obj-$(ARCH)/%.S.o: %.S GNUmakefile
mkdir -p "$(dir $@)"
$(CC) $(CFLAGS) $(CPPFLAGS) -c $< -o $@
ifneq ($(filter $(ARCH),ia32 x86_64),)
# Compilation rules for *.asm (nasm) files.
obj-$(ARCH)/%.asm.o: %.asm GNUmakefile
mkdir -p "$(dir $@)"
nasm $(NASMFLAGS) $< -o $@
endif
# Rules to download the UEFI firmware per architecture for testing.
edk2-ovmf:
curl -L https://github.com/osdev0/edk2-ovmf-nightly/releases/latest/download/edk2-ovmf.tar.gz | gunzip | tar -xf -
# Rules for running our executable in QEMU.
.PHONY: run
run: all edk2-ovmf
mkdir -p boot/EFI/BOOT
ifeq ($(ARCH),ia32)
cp bin-$(ARCH)/$(OUTPUT).efi boot/EFI/BOOT/BOOTIA32.EFI
qemu-system-i386 \
-M q35 \
-drive if=pflash,unit=0,format=raw,file=edk2-ovmf/ovmf-code-$(ARCH).fd,readonly=on \
-drive file=fat:rw:boot \
$(QEMUFLAGS)
endif
ifeq ($(ARCH),x86_64)
cp bin-$(ARCH)/$(OUTPUT).efi boot/EFI/BOOT/BOOTX64.EFI
qemu-system-x86_64 \
-M q35 \
-drive if=pflash,unit=0,format=raw,file=edk2-ovmf/ovmf-code-$(ARCH).fd,readonly=on \
-drive file=fat:rw:boot \
$(QEMUFLAGS)
endif
rm -rf boot
# Remove object files and the final executable.
.PHONY: clean
clean: seabios/.config
$(call SEABIOS_CALL,clean)
rm -rf bin-$(ARCH) obj-$(ARCH)
# Remove everything built and generated including downloaded dependencies.
.PHONY: distclean
distclean: seabios/.config
$(call SEABIOS_CALL,distclean)
rm -rf src/bins
rm -rf bin-* obj-* .cache compile_commands.json edk2-ovmf
# Install the final built executable to its final on-root location.
.PHONY: install
install: all
install -d "$(DESTDIR)$(PREFIX)/share/$(OUTPUT)"
install -m 644 bin-$(ARCH)/$(OUTPUT).efi "$(DESTDIR)$(PREFIX)/share/$(OUTPUT)/$(OUTPUT)-$(ARCH).efi"
# Try to undo whatever the "install" target did.
.PHONY: uninstall
uninstall:
rm -f "$(DESTDIR)$(PREFIX)/share/$(OUTPUT)/$(OUTPUT)-$(ARCH).efi"
-rmdir "$(DESTDIR)$(PREFIX)/share/$(OUTPUT)"
# SeaBIOS build targets.
SEABIOS_EXTRAVERSION := -CSMWrap-$(BUILD_VERSION)
.PHONY: seabios
seabios: seabios/.config
$(call SEABIOS_CALL,)
src/bins/Csm16.h: GNUmakefile seabios/out/Csm16.bin
mkdir -p src/bins
cd seabios/out && xxd -i Csm16.bin >../../src/bins/Csm16.h
src/bins/vgabios.h: GNUmakefile seabios/out/vgabios.bin
mkdir -p src/bins
cd seabios/out && xxd -i vgabios.bin >../../src/bins/vgabios.h
seabios/.config: GNUmakefile seabios-config
cp seabios-config seabios/.config
$(call SEABIOS_CALL,olddefconfig)
================================================
FILE: LICENSE
================================================
GNU LESSER GENERAL PUBLIC LICENSE
Version 2.1, February 1999
Copyright (C) 1991, 1999 Free Software Foundation, Inc.
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
[This is the first released version of the Lesser GPL. It also counts
as the successor of the GNU Library Public License, version 2, hence
the version number 2.1.]
Preamble
The licenses for most software are designed to take away your
freedom to share and change it. By contrast, the GNU General Public
Licenses are intended to guarantee your freedom to share and change
free software--to make sure the software is free for all its users.
This license, the Lesser General Public License, applies to some
specially designated software packages--typically libraries--of the
Free Software Foundation and other authors who decide to use it. You
can use it too, but we suggest you first think carefully about whether
this license or the ordinary General Public License is the better
strategy to use in any particular case, based on the explanations below.
When we speak of free software, we are referring to freedom of use,
not price. Our General Public Licenses are designed to make sure that
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That's all there is to it!
================================================
FILE: README.md
================================================
<h1 align="center">CSMWrap</h1>
<p align="center">
<a href="https://github.com/CSMWrap/CSMWrap/actions/workflows/build.yml"><img src="https://github.com/CSMWrap/CSMWrap/actions/workflows/build.yml/badge.svg" alt="Build Status"></a>
<a href="https://discord.gg/3CCgJpzNXH"><img src="https://img.shields.io/discord/1390940493873025074?color=5865F2&label=Discord&logo=discord&logoColor=white" alt="Discord"></a>
</p>
<p align="center">
<img src="logo.svg?raw=true" alt="CSMWrap logo" title="CSMWrap logo" width="400">
</p>
CSMWrap is an EFI application designed to be a drop-in solution to enable legacy BIOS booting on modern UEFI-only (class 3) systems.
It achieves this by wrapping a Compatibility Support Module (CSM) build of the [SeaBIOS project](https://www.seabios.org/)
as an out-of-firmware EFI application, effectively creating a compatibility layer for traditional PC BIOS operation.
Logo art by [conkkerxd](https://github.com/conkkerxd).
## Executive Summary
The idea is to drop the 64-bit or 32-bit version of CSMWrap (depending on the hardware, dropping both also works) into a `/EFI/BOOT/`
directory on a FAT (12, 16, or 32) partition on the medium containing the legacy BIOS OS. UEFI firmware will pick this up and show the
medium as a bootable device. Ideally, that's all that would be needed.
1. **Download:** Get the latest `csmwrap<ARCH>.efi` from the [Releases page](https://github.com/CSMWrap/CSMWrap/releases).
2. **Deploy:** Copy `csmwrap<ARCH>.efi` to a FAT-formatted partition, typically as `/EFI/BOOT/BOOTX64.EFI` (for 64-bit)
or `/EFI/BOOT/BOOTIA32.EFI` (for 32-bit) (the hardcoded path is needed so that the firmware picks it up automatically).
3. **Boot:** Select the UEFI boot entry for the drive onto which CSMWrap was deployed.
It is highly recommended that the partition table used is MBR (MS-DOS partition table), as UEFI firmwares are perfectly capable of
booting off of this format, and because it is the most compatible with most legacy OSes one may want to boot.
## Additional Prerequisites
### Secure Boot
Secure boot should be disabled unless one wants to manually sign the CSMWrap EFI application, which is possible, but beyond the
scope of this README.
### Firmware Settings
CSMWrap is designed to be as drop-in as possible, without requiring changes to firmware for settings that may not even be exposed
(depending on the firmware), or that might conflict with other UEFI OSes being multi-booted on the system. That said, if at all
possible, disabling these settings is highly recommended for best legacy OS compatibility:
1. **X2APIC**
Additional settings to try to disable if things still do not work (ideally this should *not* be necessary, please report an issue
if you need this on your hardware!):
1. **Above 4G Decoding**
2. **Resizable BAR/Smart Access Memory**
### Video Card Considerations
CSMWrap also wraps the "SeaVGABIOS" module of SeaBIOS for providing a bare bones implementation of a legacy Video BIOS. That said,
SeaVGABIOS is far from ideal, and many, **many** things requiring more direct access to legacy video modes won't work properly
(e.g. pretty much all MS-DOS games, MS-DOS Editor, etc.). More modern OSes using the VESA BIOS extensions (VBE) standard only
(e.g. more modern Windows NT, Linux, etc.) should still work fine, though.
Therefore it is **highly recommended**, if possible, to install a legacy-capable video card. If one is present, its Video BIOS
will be used instead of SeaVGABIOS, providing a much better, pretty much native-like, experience.
## Configuration
CSMWrap supports an optional INI-style configuration file. Place a file named `csmwrap.ini` in the same directory as the CSMWrap
EFI executable (e.g. `/EFI/BOOT/csmwrap.ini`). If the file is absent, sensible defaults are used.
### Options
| Key | Type | Default | Description |
|-----|------|---------|-------------|
| `serial` | bool | `false` | Enable serial debug output |
| `serial_port` | hex/int | `0x3f8` | Serial I/O port address (COM1=`0x3f8`, COM2=`0x2f8`, COM3=`0x3e8`, COM4=`0x2e8`) |
| `serial_baud` | int | `115200` | Serial baud rate |
| `vgabios` | string | *(empty)* | Path to a custom VBIOS file on the ESP (e.g. `\EFI\CSMWrap\vgabios.bin`). When empty, the card's built-in OpROM is used, and, failing that, SeaVGABIOS is used |
| `iommu_disable` | bool | `true` | Disable IOMMUs (Intel VT-d / AMD-Vi) before legacy boot |
| `verbose` | bool | `false` | Show debug output on screen via Flanterm |
| `vga` | PCI address | *(empty)* | PCI address of the VGA card to use (e.g. `00:02.0`). Format: `BB:DD.F` (hex). When empty, the first available card is used |
| `system_thread` | int/hex | *(auto)* | APIC ID of the logical CPU to reserve as the CSMWrap system thread (see [the FAQs](#frequently-asked-questions)). Must be an enabled AP (not the BSP) and have an APIC ID below `0xFF`/`255`. When empty, CSMWrap auto-picks the highest-ID AP below `0xFF`/`255`. The selected CPU is hidden from the OS in both the MADT and the MP table |
| `cpu_allowlist` | int/hex list | *(unset)* | Comma-separated list of APIC IDs of logical CPUs that should be exposed to the OS in the MADT and the MP table. Each entry is either a single ID or an inclusive range `N-M` (e.g. `0,2-4,7`). An empty value (`cpu_allowlist =`) is itself a setting and means "hide every AP" (only the BSP stays visible). The BSP is always exposed regardless. The system thread is always hidden regardless. Mutually exclusive with `cpu_blocklist` |
| `cpu_blocklist` | int/hex list | *(unset)* | Comma-separated list of APIC IDs of logical CPUs that should be hidden from the OS in the MADT and the MP table. Each entry is either a single ID or an inclusive range `N-M` (e.g. `5-7`). An empty value (`cpu_blocklist =`) is a no-op for visibility but still claims the slot, so `cpu_allowlist` cannot also be set. The BSP is always exposed regardless. The system thread is always hidden regardless. Mutually exclusive with `cpu_allowlist` |
Boolean values accept `true`/`yes`/`1` and `false`/`no`/`0` (case-insensitive). Comments start with `;` or `#`.
### Example
```ini
; CSMWrap configuration
serial = true
serial_port = 0x3f8
serial_baud = 115200
vgabios = \EFI\CSMWrap\vgabios.bin
iommu_disable = true
; Pin the system thread to APIC ID 7 and hide APIC IDs 4 through 6 from the OS.
system_thread = 7
cpu_blocklist = 4-6
```
## Frequently Asked Questions
### Is this an emulator?
No! At least not in the sense of it being a full-screened emulator window. Running a legacy OS with CSMWrap means that it is *natively*
running on the system. CSMWrap attempts to recreate, natively, and as closely as possible, a legacy BIOS PC environment on modern
UEFI class 3 systems.
### I booted a multi-core capable OS and I am missing a logical processor (thread), what gives?
This is expected. CSMWrap reserves 1 logical processor for "system" use due to the limitations of running out-of-firmware and not being able to
use [SMM (System Management Mode)](https://en.wikipedia.org/wiki/System_Management_Mode).
Therefore, this means that CSMWrap **does not support running on systems with only 1 logical processor (i.e. only 1 core and no SMT/hyperthreading)**.
That said, most systems that CSMWrap targets (i.e. modern UEFI class 3 systems) will definitely have way more than a single logical processor,
so this is mostly a non-issue.
### Does CSMWrap have any advantages over native CSM?
Yes! Native CSM firmware is often riddled with issues and hardly tested against legacy OSes anymore. CSMWrap ships a reliable, free, and open-source
legacy BIOS implementation - SeaBIOS - and it is tested against legacy OSes. Issues affecting modern, commonly shipped CSM implementations do
not affect CSMWrap, like for example:
- Dirty control register values at handoff. (This is something that [cregfix](https://github.com/mintsuki/cregfix) was created to work around).
- Legacy BIOS routines failing to reliably run when called from Virtual 8086 Mode. EMM386, Windows 3.x under 386 enhanced mode, and more, are affected
by this issue and it results in crashes. The reason for this is a bit technical for this README file, but CSMWrap is not affected.
And when it comes to improvements that are not necessarily bugs in CSM implementations, CSMWrap, amongst other things:
- Generates MP tables for legacy OSes that support the legacy Intel MultiProcessor Specification standard but not ACPI.
- Allows one to select a non-primary video card for VGA output which native CSM implementations do not allow. This is useful for
multi-booting modern and legacy OSes.
## Contributing
Contributions are welcome! Whether it's reporting bugs, suggesting features, improving documentation, or submitting code changes, your help is appreciated.
Additionally, one can join our [Discord server](https://discord.gg/3CCgJpzNXH) for any project-related discussion, or to otherwise chat with likeminded
people.
## Credits & Acknowledgements
* The **[SeaBIOS project](https://www.seabios.org/)** for their CSM and VBIOS code.
* **[PicoEFI](https://github.com/PicoEFI/PicoEFI)** for the EFI C runtime, build system, and headers.
* **[EDK2 (TianoCore)](https://github.com/tianocore/edk2)** for UEFI specifications and some code snippets.
* **[uACPI](https://github.com/uACPI/uACPI)** for ACPI table handling.
* **@CanonKong** for test feedback and general knowledge.
* All contributors and testers from the community!
================================================
FILE: seabios-config
================================================
CONFIG_CSM=y
# CONFIG_FLASH_FLOPPY is not set
# CONFIG_VGAHOOKS is not set
# CONFIG_TCGBIOS is not set
CONFIG_VGA_COREBOOT=y
================================================
FILE: src/acpi.c
================================================
#include <efi.h>
#include <io.h>
#include <pci.h>
#include <printf.h>
#include <time.h>
#include "csmwrap.h"
#include <uacpi/kernel_api.h>
#include <uacpi/tables.h>
#include <uacpi/uacpi.h>
uintptr_t g_rsdp = 0;
static inline const char *uacpi_log_level_to_string(uacpi_log_level lvl) {
switch (lvl) {
case UACPI_LOG_DEBUG:
return "DEBUG";
case UACPI_LOG_TRACE:
return "TRACE";
case UACPI_LOG_INFO:
return "INFO";
case UACPI_LOG_WARN:
return "WARN";
case UACPI_LOG_ERROR:
default:
return "ERROR";
}
}
void uacpi_kernel_log(enum uacpi_log_level lvl, const char *text) {
printf("[uACPI][%s] %s", uacpi_log_level_to_string(lvl), text);
}
void *uacpi_kernel_map(uacpi_phys_addr addr, EFI_UNUSED uacpi_size len) {
return (void*)((uintptr_t)addr);
}
void uacpi_kernel_unmap(EFI_UNUSED void *ptr, EFI_UNUSED uacpi_size len) {
}
uacpi_status uacpi_kernel_pci_device_open(uacpi_pci_address address, uacpi_handle *out_handle) {
void *handle;
if (gBS->AllocatePool(EfiLoaderData, sizeof(struct pci_address), &handle) != EFI_SUCCESS) {
return UACPI_STATUS_OUT_OF_MEMORY;
}
struct pci_address *pci_address = (struct pci_address *)handle;
pci_address->segment = address.segment;
pci_address->bus = address.bus;
pci_address->slot = address.device;
pci_address->function = address.function;
*out_handle = handle;
return UACPI_STATUS_OK;
}
void uacpi_kernel_pci_device_close(uacpi_handle handle) {
gBS->FreePool(handle);
}
uacpi_status uacpi_kernel_pci_read8(uacpi_handle device, uacpi_size offset, uacpi_u8 *value) {
*value = pci_read8((struct pci_address *)device, offset);
return UACPI_STATUS_OK;
}
uacpi_status uacpi_kernel_pci_read16(uacpi_handle device, uacpi_size offset, uacpi_u16 *value) {
*value = pci_read16((struct pci_address *)device, offset);
return UACPI_STATUS_OK;
}
uacpi_status uacpi_kernel_pci_read32(uacpi_handle device, uacpi_size offset, uacpi_u32 *value) {
*value = pci_read32((struct pci_address *)device, offset);
return UACPI_STATUS_OK;
}
uacpi_status uacpi_kernel_pci_write8(uacpi_handle device, uacpi_size offset, uacpi_u8 value) {
pci_write8((struct pci_address *)device, offset, value);
return UACPI_STATUS_OK;
}
uacpi_status uacpi_kernel_pci_write16(uacpi_handle device, uacpi_size offset, uacpi_u16 value) {
pci_write16((struct pci_address *)device, offset, value);
return UACPI_STATUS_OK;
}
uacpi_status uacpi_kernel_pci_write32(uacpi_handle device, uacpi_size offset, uacpi_u32 value) {
pci_write32((struct pci_address *)device, offset, value);
return UACPI_STATUS_OK;
}
struct mapped_io {
uacpi_io_addr base;
uacpi_size len;
};
uacpi_status uacpi_kernel_io_map(uacpi_io_addr base, uacpi_size len, uacpi_handle *out_handle) {
void *handle;
if (gBS->AllocatePool(EfiLoaderData, sizeof(struct mapped_io), &handle) != EFI_SUCCESS) {
return UACPI_STATUS_OUT_OF_MEMORY;
}
struct mapped_io *io = (struct mapped_io *)handle;
io->base = base;
io->len = len;
*out_handle = handle;
return UACPI_STATUS_OK;
}
void uacpi_kernel_io_unmap(uacpi_handle handle) {
gBS->FreePool(handle);
}
uacpi_status uacpi_kernel_io_read8(uacpi_handle handle, uacpi_size offset, uacpi_u8 *out_value) {
struct mapped_io *io = (struct mapped_io *)handle;
if (offset >= io->len) {
return UACPI_STATUS_INVALID_ARGUMENT;
}
*out_value = inb(io->base + offset);
return UACPI_STATUS_OK;
}
uacpi_status uacpi_kernel_io_read16(uacpi_handle handle, uacpi_size offset, uacpi_u16 *out_value) {
struct mapped_io *io = (struct mapped_io *)handle;
if (offset >= io->len) {
return UACPI_STATUS_INVALID_ARGUMENT;
}
*out_value = inw(io->base + offset);
return UACPI_STATUS_OK;
}
uacpi_status uacpi_kernel_io_read32(uacpi_handle handle, uacpi_size offset, uacpi_u32 *out_value) {
struct mapped_io *io = (struct mapped_io *)handle;
if (offset >= io->len) {
return UACPI_STATUS_INVALID_ARGUMENT;
}
*out_value = inl(io->base + offset);
return UACPI_STATUS_OK;
}
uacpi_status uacpi_kernel_io_write8(uacpi_handle handle, uacpi_size offset, uacpi_u8 in_value) {
struct mapped_io *io = (struct mapped_io *)handle;
if (offset >= io->len) {
return UACPI_STATUS_INVALID_ARGUMENT;
}
outb(io->base + offset, in_value);
return UACPI_STATUS_OK;
}
uacpi_status uacpi_kernel_io_write16(uacpi_handle handle, uacpi_size offset, uacpi_u16 in_value) {
struct mapped_io *io = (struct mapped_io *)handle;
if (offset >= io->len) {
return UACPI_STATUS_INVALID_ARGUMENT;
}
outw(io->base + offset, in_value);
return UACPI_STATUS_OK;
}
uacpi_status uacpi_kernel_io_write32(uacpi_handle handle, uacpi_size offset, uacpi_u32 in_value) {
struct mapped_io *io = (struct mapped_io *)handle;
if (offset >= io->len) {
return UACPI_STATUS_INVALID_ARGUMENT;
}
outl(io->base + offset, in_value);
return UACPI_STATUS_OK;
}
uacpi_interrupt_state uacpi_kernel_disable_interrupts(void) {
uacpi_interrupt_state flags;
asm volatile ("pushf; pop %0; cli" : "=rm"(flags) :: "memory");
return flags;
}
void uacpi_kernel_restore_interrupts(uacpi_interrupt_state state) {
asm volatile ("push %0; popf" :: "rm"(state) : "memory", "cc");
}
uacpi_handle uacpi_kernel_create_spinlock(void) {
void *handle;
if (gBS->AllocatePool(EfiLoaderData, 0x1, &handle) != EFI_SUCCESS) {
return NULL;
}
return handle;
}
void uacpi_kernel_free_spinlock(uacpi_handle handle) {
gBS->FreePool(handle);
}
uacpi_cpu_flags uacpi_kernel_lock_spinlock(uacpi_handle handle) {
(void)handle;
return 0;
}
void uacpi_kernel_unlock_spinlock(uacpi_handle handle, uacpi_cpu_flags cpu_flags) {
(void)handle;
(void)cpu_flags;
}
uacpi_handle uacpi_kernel_create_event(void) {
void *handle;
if (gBS->AllocatePool(EfiLoaderData, 0x1, &handle) != EFI_SUCCESS) {
return NULL;
}
return handle;
}
void uacpi_kernel_free_event(uacpi_handle handle) {
gBS->FreePool(handle);
}
uacpi_bool uacpi_kernel_wait_for_event(uacpi_handle handle, uacpi_u16 timeout) {
(void)handle;
(void)timeout;
return UACPI_TRUE;
}
void uacpi_kernel_signal_event(uacpi_handle handle) {
(void)handle;
}
void uacpi_kernel_reset_event(uacpi_handle handle) {
(void)handle;
}
uacpi_u64 uacpi_kernel_get_nanoseconds_since_boot(void) {
return get_nanoseconds_since_boot();
}
void uacpi_kernel_stall(uacpi_u8 usec) {
gBS->Stall(usec);
}
void uacpi_kernel_sleep(uacpi_u64 msec) {
gBS->Stall(msec * 1000);
}
uacpi_thread_id uacpi_kernel_get_thread_id(void) {
return (uacpi_thread_id)1;
}
uacpi_status uacpi_kernel_handle_firmware_request(uacpi_firmware_request *request) {
(void)request;
return UACPI_STATUS_UNIMPLEMENTED;
}
uacpi_status uacpi_kernel_install_interrupt_handler(
uacpi_u32 irq, uacpi_interrupt_handler handler, uacpi_handle ctx,
uacpi_handle *out_irq_handle) {
(void)irq;
(void)handler;
(void)ctx;
(void)out_irq_handle;
return UACPI_STATUS_OK;
}
uacpi_status uacpi_kernel_uninstall_interrupt_handler(uacpi_interrupt_handler handler, uacpi_handle irq_handle) {
(void)handler;
(void)irq_handle;
return UACPI_STATUS_UNIMPLEMENTED;
}
uacpi_status uacpi_kernel_schedule_work(uacpi_work_type work_type, uacpi_work_handler handler, uacpi_handle ctx) {
(void)work_type;
(void)handler;
(void)ctx;
return UACPI_STATUS_UNIMPLEMENTED;
}
uacpi_status uacpi_kernel_wait_for_work_completion(void) {
return UACPI_STATUS_UNIMPLEMENTED;
}
void *uacpi_kernel_alloc(uacpi_size size) {
void *result;
if (gBS->AllocatePool(EfiLoaderData, size, &result) != EFI_SUCCESS) {
return NULL;
}
return result;
}
void uacpi_kernel_free(void *mem) {
if (mem != NULL) {
gBS->FreePool(mem);
}
}
uacpi_handle uacpi_kernel_create_mutex(void) {
void *handle;
if (gBS->AllocatePool(EfiLoaderData, 0x1, &handle) != EFI_SUCCESS) {
return NULL;
}
return handle;
}
void uacpi_kernel_free_mutex(uacpi_handle handle) {
gBS->FreePool(handle);
}
uacpi_status uacpi_kernel_acquire_mutex(uacpi_handle handle, uacpi_u16 timeout) {
(void)handle;
(void)timeout;
return UACPI_STATUS_OK;
}
void uacpi_kernel_release_mutex(uacpi_handle handle) {
(void)handle;
}
uacpi_status uacpi_kernel_get_rsdp(uacpi_phys_addr *rsdp) {
if (!g_rsdp) {
return UACPI_STATUS_NOT_FOUND;
}
*rsdp = g_rsdp;
return UACPI_STATUS_OK;
}
static void *early_table_buffer;
bool acpi_init(struct csmwrap_priv *priv) {
UINTN i;
EFI_GUID acpiGuid = ACPI_TABLE_GUID;
EFI_GUID acpi2Guid = ACPI_20_TABLE_GUID;
void *table_target = priv->csm_bin + (priv->csm_efi_table->AcpiRsdPtrPointer - priv->csm_bin_base);
for (i = 0; i < gST->NumberOfTableEntries; i++) {
EFI_CONFIGURATION_TABLE *table;
table = gST->ConfigurationTable + i;
if (!efi_guidcmp(table->VendorGuid, acpi2Guid)) {
printf("Found ACPI 2.0 RSDT at %x, copied to %x\n", (uintptr_t)table->VendorTable, (uintptr_t)table_target);
memcpy(table_target, table->VendorTable, sizeof(EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER));
g_rsdp = (uintptr_t)table->VendorTable;
break;
}
}
if (g_rsdp == 0) {
for (i = 0; i < gST->NumberOfTableEntries; i++) {
EFI_CONFIGURATION_TABLE *table;
table = gST->ConfigurationTable + i;
if (!efi_guidcmp(table->VendorGuid, acpiGuid)) {
printf("Found ACPI 1.0 RSDT at %x, copied to %x\n", (uintptr_t)table->VendorTable, (uintptr_t)table_target);
memcpy(table_target, table->VendorTable, sizeof(EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER));
g_rsdp = (uintptr_t)table->VendorTable;
break;
}
}
}
if (g_rsdp) {
const size_t table_buffer_size = 4096;
if (gBS->AllocatePool(EfiLoaderData, table_buffer_size, &early_table_buffer) != EFI_SUCCESS) {
return false;
}
enum uacpi_status uacpi_status;
uacpi_status = uacpi_setup_early_table_access(early_table_buffer, table_buffer_size);
if (uacpi_status != UACPI_STATUS_OK) {
printf("uACPI early table setup failed: %s\n", uacpi_status_to_string(uacpi_status));
return false;
}
return true;
}
printf("No ACPI RSDT found\n");
return false;
}
/*
* Initialize ACPI namespace without running _INI methods.
* This is sufficient for PCI root bridge discovery via _CRS evaluation.
* Avoids side effects like changing power button behavior.
*/
bool acpi_namespace_init(void) {
enum uacpi_status uacpi_status;
uacpi_status = uacpi_initialize(UACPI_FLAG_NO_ACPI_MODE);
if (uacpi_status != UACPI_STATUS_OK) {
printf("uACPI initialization failed: %s\n", uacpi_status_to_string(uacpi_status));
return false;
}
uacpi_status = uacpi_namespace_load();
if (uacpi_status != UACPI_STATUS_OK) {
printf("uACPI namespace load failed: %s\n", uacpi_status_to_string(uacpi_status));
return false;
}
/* Note: We intentionally skip uacpi_namespace_initialize() which runs _INI methods */
return true;
}
================================================
FILE: src/ap_trampoline.asm
================================================
; AP Trampoline for BIOS Proxy Helper Core
; This code is copied to 0x7000 and runs when an AP wakes from SIPI
; AP starts at CS:IP = 0x0700:0x0000 = linear 0x7000
;
; This trampoline stays in 16-bit real mode and jumps to the SeaBIOS
; 16-bit entry point, which handles the GDT load and 32-bit mode switch.
bits 16
section .rodata
; APIC MSR
%define MSR_IA32_APIC_BASE 0x1B
%define APIC_BASE_EXTD (1 << 10)
%define APIC_BASE_EN (1 << 11)
; AMD MTRR MSR addresses
%define MSR_SYS_CFG 0xC0010010
%define SYS_CFG_MTRR_FIX_DRAM_EN (1 << 18)
%define SYS_CFG_MTRR_FIX_DRAM_MOD_EN (1 << 19)
; Fixed MTRRs for conventional memory (0x00000-0x9FFFF)
%define AMD_MTRR_FIX64k_00000 0x250 ; 0x00000-0x7FFFF (512KB, 8x64KB)
%define AMD_MTRR_FIX16k_80000 0x258 ; 0x80000-0x9FFFF (128KB, 8x16KB)
%define AMD_MTRR_FIX16k_A0000 0x259 ; 0xA0000-0xBFFFF (VGA, 128KB, 8x16KB)
; Fixed MTRRs for BIOS region (0xC0000-0xFFFFF)
%define AMD_MTRR_FIX4k_C0000 0x268
%define AMD_MTRR_FIX4k_C8000 0x269
%define AMD_MTRR_FIX4k_D0000 0x26A
%define AMD_MTRR_FIX4k_D8000 0x26B
%define AMD_MTRR_FIX4k_E0000 0x26C
%define AMD_MTRR_FIX4k_E8000 0x26D
%define AMD_MTRR_FIX4k_F0000 0x26E
%define AMD_MTRR_FIX4k_F8000 0x26F
; WB_DRAM = 0x1E per segment (8 segments per MSR = 0x1E1E1E1E1E1E1E1E)
%define MTRR_WB_DRAM_LO 0x1E1E1E1E
%define MTRR_WB_DRAM_HI 0x1E1E1E1E
global ap_trampoline_start
ap_trampoline_start:
cli
cld
; Set up DS=0 so we can read from trampoline data area
xor ax, ax
mov ds, ax
mov es, ax
mov ss, ax
jmp 0x0000:word (0x7000 + .reload_cs - ap_trampoline_start)
.reload_cs:
; ========================================
; AMD MTRR unlock for low memory (00000-FFFFF)
; Sets conventional memory and BIOS region to WB_DRAM
; Required for helper core to access EBDA and F-segment
; Skipped on Intel (PAM registers are global, already unlocked by BSP)
; Skipped if region is already writable (e.g., under hypervisors)
; ========================================
; First test if the BIOS region is already writable
; Try writing a test pattern to 0xF0000 and reading it back
; Use segmentation: 0xF000:0x0000 = linear 0xF0000
; Save and restore original value to avoid corrupting CSM code
mov ax, 0xF000
mov fs, ax
mov eax, [fs:0] ; save original value
mov ebx, eax
xor eax, 0xFFFFFFFF ; flip all bits to create test pattern
mov [fs:0], eax ; try to write
cmp [fs:0], eax ; did the write succeed?
mov [fs:0], ebx ; restore original (regardless of result)
je .skip_mtrr_unlock ; Region already writable, skip MTRR unlock
; Region not writable - check if this is AMD
; On Intel, PAM registers are global so BSP unlock applies to all cores
; If we get here on Intel, something is wrong - halt
mov eax, 0
cpuid
cmp ebx, 0x68747541 ; "Auth" (AuthenticAMD)
jne .unlock_failed ; Not AMD and not writable - halt
; AMD APM Vol 2 §7.6.3: disable cache and flush around MTRR change.
; Paging is off in real mode so no TLB / PGE handling is required.
; (CD=1, NW=1) is unsupported per Intel SDM Vol 3A §11.5.3.
mov eax, cr0
mov edi, eax ; save CR0
or eax, 0x40000000 ; CR0.CD = 1
and eax, ~0x20000000 ; CR0.NW = 0
mov cr0, eax
wbinvd
; AMD system with locked region - attempt MTRR unlock
; Enable MTRR modification: set SYS_CFG.MtrrFixDramModEn (bit 19)
mov ecx, MSR_SYS_CFG
rdmsr
or eax, SYS_CFG_MTRR_FIX_DRAM_MOD_EN
wrmsr
; Set conventional memory (00000-9FFFF) to WB_DRAM
mov eax, MTRR_WB_DRAM_LO
mov edx, MTRR_WB_DRAM_HI
mov ecx, AMD_MTRR_FIX64k_00000 ; 0x00000-0x7FFFF
wrmsr
mov ecx, AMD_MTRR_FIX16k_80000 ; 0x80000-0x9FFFF (includes EBDA)
wrmsr
; Set VGA region (A0000-BFFFF) to UC (MMIO)
xor eax, eax
xor edx, edx
mov ecx, AMD_MTRR_FIX16k_A0000
wrmsr
; Set BIOS region (C0000-FFFFF) to WB_DRAM
mov eax, MTRR_WB_DRAM_LO
mov edx, MTRR_WB_DRAM_HI
mov ecx, AMD_MTRR_FIX4k_C0000
wrmsr
mov ecx, AMD_MTRR_FIX4k_C8000
wrmsr
mov ecx, AMD_MTRR_FIX4k_D0000
wrmsr
mov ecx, AMD_MTRR_FIX4k_D8000
wrmsr
mov ecx, AMD_MTRR_FIX4k_E0000
wrmsr
mov ecx, AMD_MTRR_FIX4k_E8000
wrmsr
mov ecx, AMD_MTRR_FIX4k_F0000
wrmsr
mov ecx, AMD_MTRR_FIX4k_F8000
wrmsr
; Disable modification, enable fixed MTRR DRAM attributes
mov ecx, MSR_SYS_CFG
rdmsr
and eax, ~SYS_CFG_MTRR_FIX_DRAM_MOD_EN
or eax, SYS_CFG_MTRR_FIX_DRAM_EN
wrmsr
wbinvd
mov cr0, edi ; restore CR0
; Verify the unlock worked by testing write again
; FS still points to 0xF000 from earlier
; Save and restore original value to avoid corrupting CSM code
mov eax, [fs:0] ; save original value
mov ebx, eax
xor eax, 0xFFFFFFFF ; flip all bits to create test pattern
mov [fs:0], eax ; try to write
cmp [fs:0], eax ; did the write succeed?
mov [fs:0], ebx ; restore original (regardless of result)
jne .unlock_failed ; MTRR unlock didn't help - halt
.skip_mtrr_unlock:
; Continue to load registers and jump to SeaBIOS
jmp .continue_boot
.unlock_failed:
; Region still not writable - halt so BSP detects timeout
hlt
jmp .unlock_failed
.continue_boot:
; Hardware-disable LAPIC to prevent the legacy OS from sending IPIs
; (including INIT) to this core. The helper core communicates via
; memory mailbox only and does not need interrupt delivery.
; Must clear both EN (bit 11) and EXTD (bit 10) simultaneously
; to correctly transition from x2APIC mode to disabled state.
;
; If the AP came up already in x2APIC mode (EXTD set), the BSP-side
; apic_prepare_for_legacy() must have left x2APIC alone, meaning the
; mode is locked (e.g. Nova Lake xAPIC deprecation) or the silicon has
; no xAPIC support at all. In either case clearing EXTD here would #GP,
; so we leave the APIC enabled. A legacy OS cannot send x2APIC-mode
; IPIs via MMIO anyway, so the helper stays unreachable to it.
mov ecx, MSR_IA32_APIC_BASE
rdmsr
test eax, APIC_BASE_EXTD
jnz .skip_apic_disable
and eax, ~(APIC_BASE_EN | APIC_BASE_EXTD)
wrmsr
.skip_apic_disable:
; Load 32-bit values into registers for SeaBIOS
; (16-bit mode can still use 32-bit registers with operand size prefix)
mov ebx, [0x7000 + trampoline_mailbox - ap_trampoline_start]
mov esp, [0x7000 + trampoline_stack - ap_trampoline_start]
mov esi, (0x7000 + trampoline_helper_ready - ap_trampoline_start)
; Far jump to SeaBIOS 16-bit entry point (segment:offset)
jmp far [0x7000 + trampoline_target16 - ap_trampoline_start]
; --- Data area (filled in by C code) ---
align 4
trampoline_mailbox:
dd 0
trampoline_stack:
dd 0
; Far pointer for 16-bit jump: offset (16-bit) then segment (16-bit)
trampoline_target16:
dw 0 ; offset
dw 0 ; segment
trampoline_helper_ready:
dd 0
ap_trampoline_end:
global ap_trampoline_size
ap_trampoline_size: equ (ap_trampoline_end - ap_trampoline_start)
; Export size and offsets for C code
global ap_trampoline_size_value
ap_trampoline_size_value: dd ap_trampoline_size
global ap_trampoline_mailbox_offset
ap_trampoline_mailbox_offset: dd (trampoline_mailbox - ap_trampoline_start)
global ap_trampoline_stack_offset
ap_trampoline_stack_offset: dd (trampoline_stack - ap_trampoline_start)
global ap_trampoline_target16_offset
ap_trampoline_target16_offset: dd (trampoline_target16 - ap_trampoline_start)
global ap_trampoline_helper_ready_offset
ap_trampoline_helper_ready_offset: dd (trampoline_helper_ready - ap_trampoline_start)
section .note.GNU-stack noalloc noexec nowrite progbits
================================================
FILE: src/apic.c
================================================
/*
* APIC handling for legacy BIOS compatibility
*
* Modern UEFI systems boot with x2APIC enabled, which prevents legacy PIC
* interrupts (like IRQ0 timer) from reaching the CPU. This module handles
* the transition to a state compatible with legacy BIOS operation.
*
* References:
* - Intel 64 Architecture x2APIC Specification
* - EDK2 BaseXApicX2ApicLib
* - Linux kernel x86/apic code
*/
#include <efi.h>
#include <stdbool.h>
#include <io.h>
#include <printf.h>
#include <uacpi/acpi.h>
#include <uacpi/tables.h>
#include <uacpi/uacpi.h>
/* MSR addresses */
#define MSR_IA32_APIC_BASE 0x1B
#define MSR_IA32_ARCH_CAPABILITIES 0x10A
#define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD
/* IA32_APIC_BASE bits */
#define APIC_BASE_BSP (1ULL << 8) /* Bootstrap processor */
#define APIC_BASE_EXTD (1ULL << 10) /* x2APIC mode enable */
#define APIC_BASE_EN (1ULL << 11) /* APIC global enable */
#define APIC_BASE_ADDR_MASK 0xFFFFFFFFFFFFF000ULL
/* IA32_ARCH_CAPABILITIES bits */
#define ARCH_CAP_XAPIC_DISABLE (1ULL << 21) /* IA32_XAPIC_DISABLE_STATUS exists */
/* IA32_XAPIC_DISABLE_STATUS bits */
#define XAPIC_DISABLE_LEGACY_DISABLED (1ULL << 0) /* xAPIC mode locked out */
/* x2APIC MSR addresses (base 0x800, offset = xAPIC offset >> 4) */
#define X2APIC_MSR_SIVR 0x80F /* Spurious Interrupt Vector (0xF0 >> 4) */
#define X2APIC_MSR_LVT_CMCI 0x82F /* LVT CMCI (0x2F0 >> 4) */
#define X2APIC_MSR_LVT_TIMER 0x832 /* LVT Timer (0x320 >> 4) */
#define X2APIC_MSR_LVT_THERMAL 0x833 /* LVT Thermal (0x330 >> 4) */
#define X2APIC_MSR_LVT_PMC 0x834 /* LVT PMC (0x340 >> 4) */
#define X2APIC_MSR_LVT_LINT0 0x835 /* LVT LINT0 (0x350 >> 4) */
#define X2APIC_MSR_LVT_LINT1 0x836 /* LVT LINT1 (0x360 >> 4) */
#define X2APIC_MSR_LVT_ERROR 0x837 /* LVT Error (0x370 >> 4) */
#define X2APIC_MSR_VERSION 0x803 /* Version (0x030 >> 4) */
#define X2APIC_MSR_TPR 0x808 /* Task Priority (0x080 >> 4) */
/* xAPIC MMIO offsets (from APIC base, typically 0xFEE00000) */
#define XAPIC_VERSION_OFFSET 0x030
#define XAPIC_TPR_OFFSET 0x080
#define XAPIC_SIVR_OFFSET 0x0F0
#define XAPIC_LVT_CMCI_OFFSET 0x2F0
#define XAPIC_LVT_TIMER_OFFSET 0x320
#define XAPIC_LVT_THERMAL_OFFSET 0x330
#define XAPIC_LVT_PMC_OFFSET 0x340
#define XAPIC_LVT_LINT0_OFFSET 0x350
#define XAPIC_LVT_LINT1_OFFSET 0x360
#define XAPIC_LVT_ERROR_OFFSET 0x370
/* LVT register bits */
#define LVT_VECTOR_MASK 0xFF
#define LVT_DELIVERY_MODE_SHIFT 8
#define LVT_DELIVERY_MODE_MASK (0x7 << LVT_DELIVERY_MODE_SHIFT)
#define LVT_DELIVERY_FIXED (0 << LVT_DELIVERY_MODE_SHIFT)
#define LVT_DELIVERY_NMI (4 << LVT_DELIVERY_MODE_SHIFT)
#define LVT_DELIVERY_EXTINT (7 << LVT_DELIVERY_MODE_SHIFT)
#define LVT_POLARITY_ACTIVE_LOW (1 << 13)
#define LVT_TRIGGER_LEVEL (1 << 15)
#define LVT_MASK (1 << 16)
/* Spurious Interrupt Vector Register bits */
#define SIVR_VECTOR_MASK 0xFF
#define SIVR_APIC_ENABLE (1 << 8)
#define SIVR_FOCUS_DISABLE (1 << 9)
/*
* Check if x2APIC mode is locked and cannot be disabled.
* Returns true if x2APIC is locked (will #GP on disable attempt).
*/
static bool x2apic_is_locked(void)
{
uint32_t eax, ebx, ecx, edx;
/* Check CPUID for IA32_ARCH_CAPABILITIES support (leaf 7, ECX bit 29) */
asm volatile ("cpuid"
: "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
: "a"(7), "c"(0));
if (!(edx & (1 << 29))) {
/* IA32_ARCH_CAPABILITIES not supported, no lock possible */
return false;
}
/* Check if IA32_XAPIC_DISABLE_STATUS MSR exists */
uint64_t arch_cap = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
if (!(arch_cap & ARCH_CAP_XAPIC_DISABLE)) {
/* MSR not supported, no lock possible */
return false;
}
/* Read the lock status */
uint64_t xapic_status = rdmsr(MSR_IA32_XAPIC_DISABLE_STATUS);
return !!(xapic_status & XAPIC_DISABLE_LEGACY_DISABLED);
}
static bool lvt_should_mask(uint32_t lvt)
{
switch ((lvt >> LVT_DELIVERY_MODE_SHIFT) & 7) {
case 0b000: /* Fixed */
case 0b001: /* Lowest Priority */
case 0b100: /* NMI */
case 0b111: /* ExtINT */
return true;
default: /* SMI, INIT, Reserved */
return false;
}
}
/* MADT NMI routing (loaded once by apic_prepare_for_legacy). */
static uint8_t g_nmi_lint = 1; /* default: NMI on LINT1 */
static uint16_t g_nmi_madt_flags = 0; /* MADT polarity/trigger flags */
static void load_nmi_madt_info(void)
{
struct uacpi_table madt_table;
if (uacpi_table_find_by_signature(ACPI_MADT_SIGNATURE, &madt_table)
!= UACPI_STATUS_OK) {
return;
}
struct acpi_madt *madt = (struct acpi_madt *)madt_table.virt_addr;
uint8_t *entry = (uint8_t *)(madt + 1);
uint8_t *end = (uint8_t *)madt + madt->hdr.length;
while (entry < end) {
struct acpi_entry_hdr *hdr = (struct acpi_entry_hdr *)entry;
if (hdr->length < 2) break;
if (hdr->type == ACPI_MADT_ENTRY_TYPE_LAPIC_NMI) {
struct acpi_madt_lapic_nmi *nmi =
(struct acpi_madt_lapic_nmi *)entry;
g_nmi_lint = nmi->lint & 1;
g_nmi_madt_flags = nmi->flags;
break;
}
if (hdr->type == ACPI_MADT_ENTRY_TYPE_LOCAL_X2APIC_NMI) {
struct acpi_madt_x2apic_nmi *nmi =
(struct acpi_madt_x2apic_nmi *)entry;
g_nmi_lint = nmi->lint & 1;
g_nmi_madt_flags = nmi->flags;
break;
}
entry += hdr->length;
}
uacpi_table_unref(&madt_table);
}
/* Build the LVT value (delivery mode + polarity/trigger) for one LINT pin.
* The pin matching MADT's NMI routing gets NMI delivery with MADT-supplied
* polarity/trigger; the other gets ExtINT (edge, active high). */
static uint32_t lint_lvt_value(int pin)
{
if (pin == g_nmi_lint) {
uint32_t val = LVT_DELIVERY_NMI;
if ((g_nmi_madt_flags & ACPI_MADT_POLARITY_MASK)
== ACPI_MADT_POLARITY_ACTIVE_LOW)
val |= LVT_POLARITY_ACTIVE_LOW;
if ((g_nmi_madt_flags & ACPI_MADT_TRIGGERING_MASK)
== ACPI_MADT_TRIGGERING_LEVEL)
val |= LVT_TRIGGER_LEVEL;
return val;
}
return LVT_DELIVERY_EXTINT;
}
/*
* Configure LAPIC for legacy BIOS operation in x2APIC mode (MSR access).
* Sets up LINT0/LINT1 per MADT-reported NMI routing (default: LINT1=NMI).
*
* Note: The LAPIC ignores trigger mode for ExtINT and NMI delivery modes,
* always using edge-triggered internally.
*/
static void x2apic_configure_for_legacy(void)
{
uint64_t val;
uint32_t max_lvt = ((uint32_t)rdmsr(X2APIC_MSR_VERSION) >> 16) & 0xFF;
/* Clear task priority to allow all interrupts */
wrmsr(X2APIC_MSR_TPR, 0);
/* Mask stale LVT entries to prevent unexpected interrupts.
* Only mask entries with Fixed, Lowest Priority, NMI, or ExtINT delivery
* mode. Leave SMI, INIT, and reserved delivery modes untouched as firmware
* may rely on them (e.g. thermal management via SMI). */
uint64_t lvt;
lvt = rdmsr(X2APIC_MSR_LVT_TIMER);
if (lvt_should_mask(lvt))
wrmsr(X2APIC_MSR_LVT_TIMER, lvt | LVT_MASK);
lvt = rdmsr(X2APIC_MSR_LVT_ERROR);
if (lvt_should_mask(lvt))
wrmsr(X2APIC_MSR_LVT_ERROR, lvt | LVT_MASK);
if (max_lvt >= 4) {
lvt = rdmsr(X2APIC_MSR_LVT_PMC);
if (lvt_should_mask(lvt))
wrmsr(X2APIC_MSR_LVT_PMC, lvt | LVT_MASK);
}
if (max_lvt >= 5) {
lvt = rdmsr(X2APIC_MSR_LVT_THERMAL);
if (lvt_should_mask(lvt))
wrmsr(X2APIC_MSR_LVT_THERMAL, lvt | LVT_MASK);
}
if (max_lvt >= 6) {
lvt = rdmsr(X2APIC_MSR_LVT_CMCI);
if (lvt_should_mask(lvt))
wrmsr(X2APIC_MSR_LVT_CMCI, lvt | LVT_MASK);
}
/* Configure LINT0 / LINT1: one gets NMI (per MADT), the other ExtINT. */
val = rdmsr(X2APIC_MSR_LVT_LINT0);
printf(" x2APIC LINT0 before: 0x%08lx\n", (uint32_t)val);
val &= ~(LVT_VECTOR_MASK | LVT_DELIVERY_MODE_MASK | LVT_TRIGGER_LEVEL |
LVT_POLARITY_ACTIVE_LOW | LVT_MASK);
val |= lint_lvt_value(0);
wrmsr(X2APIC_MSR_LVT_LINT0, val);
printf(" x2APIC LINT0 after: 0x%08lx\n", (uint32_t)rdmsr(X2APIC_MSR_LVT_LINT0));
val = rdmsr(X2APIC_MSR_LVT_LINT1);
printf(" x2APIC LINT1 before: 0x%08lx\n", (uint32_t)val);
val &= ~(LVT_VECTOR_MASK | LVT_DELIVERY_MODE_MASK | LVT_TRIGGER_LEVEL |
LVT_POLARITY_ACTIVE_LOW | LVT_MASK);
val |= lint_lvt_value(1);
wrmsr(X2APIC_MSR_LVT_LINT1, val);
printf(" x2APIC LINT1 after: 0x%08lx\n", (uint32_t)rdmsr(X2APIC_MSR_LVT_LINT1));
/* Configure Spurious Interrupt Vector Register:
* - APIC software enable (bit 8) - required for LAPIC to work
* - Spurious vector = 0x0F (matches legacy 8259 PIC IRQ7 spurious interrupt)
*/
val = rdmsr(X2APIC_MSR_SIVR);
printf(" x2APIC SIVR before: 0x%08lx\n", (uint32_t)val);
val &= ~SIVR_VECTOR_MASK;
val |= SIVR_APIC_ENABLE | 0x0F;
wrmsr(X2APIC_MSR_SIVR, val);
printf(" x2APIC SIVR after: 0x%08lx\n", (uint32_t)rdmsr(X2APIC_MSR_SIVR));
}
/*
* Configure LAPIC for legacy BIOS operation in xAPIC mode (MMIO access).
* Sets up LINT0 for ExtINT, LINT1 for NMI per Intel SDM Appendix D.
*
* Note: The LAPIC ignores trigger mode for ExtINT and NMI delivery modes,
* always using edge-triggered internally. We set edge-triggered explicitly
* to match Intel's documented example (0x0700 for ExtINT, 0x0400 for NMI).
*/
static void xapic_configure_for_legacy(uintptr_t apic_base)
{
volatile uint32_t *lint0_reg = (volatile uint32_t *)(apic_base + XAPIC_LVT_LINT0_OFFSET);
volatile uint32_t *lint1_reg = (volatile uint32_t *)(apic_base + XAPIC_LVT_LINT1_OFFSET);
volatile uint32_t *sivr_reg = (volatile uint32_t *)(apic_base + XAPIC_SIVR_OFFSET);
uint32_t val;
uint32_t max_lvt = (*(volatile uint32_t *)(apic_base + XAPIC_VERSION_OFFSET) >> 16) & 0xFF;
/* Clear task priority to allow all interrupts */
*(volatile uint32_t *)(apic_base + XAPIC_TPR_OFFSET) = 0;
/* Mask stale LVT entries to prevent unexpected interrupts.
* Only mask entries with Fixed, Lowest Priority, NMI, or ExtINT delivery
* mode. Leave SMI, INIT, and reserved delivery modes untouched as firmware
* may rely on them (e.g. thermal management via SMI). */
uint32_t lvt;
lvt = *(volatile uint32_t *)(apic_base + XAPIC_LVT_TIMER_OFFSET);
if (lvt_should_mask(lvt))
*(volatile uint32_t *)(apic_base + XAPIC_LVT_TIMER_OFFSET) = lvt | LVT_MASK;
lvt = *(volatile uint32_t *)(apic_base + XAPIC_LVT_ERROR_OFFSET);
if (lvt_should_mask(lvt))
*(volatile uint32_t *)(apic_base + XAPIC_LVT_ERROR_OFFSET) = lvt | LVT_MASK;
if (max_lvt >= 4) {
lvt = *(volatile uint32_t *)(apic_base + XAPIC_LVT_PMC_OFFSET);
if (lvt_should_mask(lvt))
*(volatile uint32_t *)(apic_base + XAPIC_LVT_PMC_OFFSET) = lvt | LVT_MASK;
}
if (max_lvt >= 5) {
lvt = *(volatile uint32_t *)(apic_base + XAPIC_LVT_THERMAL_OFFSET);
if (lvt_should_mask(lvt))
*(volatile uint32_t *)(apic_base + XAPIC_LVT_THERMAL_OFFSET) = lvt | LVT_MASK;
}
if (max_lvt >= 6) {
lvt = *(volatile uint32_t *)(apic_base + XAPIC_LVT_CMCI_OFFSET);
if (lvt_should_mask(lvt))
*(volatile uint32_t *)(apic_base + XAPIC_LVT_CMCI_OFFSET) = lvt | LVT_MASK;
}
/* Configure LINT0 / LINT1: one gets NMI (per MADT), the other ExtINT. */
val = *lint0_reg;
printf(" xAPIC LINT0 before: 0x%08x\n", val);
val &= ~(LVT_VECTOR_MASK | LVT_DELIVERY_MODE_MASK | LVT_TRIGGER_LEVEL |
LVT_POLARITY_ACTIVE_LOW | LVT_MASK);
val |= lint_lvt_value(0);
*lint0_reg = val;
printf(" xAPIC LINT0 after: 0x%08x\n", *lint0_reg);
val = *lint1_reg;
printf(" xAPIC LINT1 before: 0x%08x\n", val);
val &= ~(LVT_VECTOR_MASK | LVT_DELIVERY_MODE_MASK | LVT_TRIGGER_LEVEL |
LVT_POLARITY_ACTIVE_LOW | LVT_MASK);
val |= lint_lvt_value(1);
*lint1_reg = val;
printf(" xAPIC LINT1 after: 0x%08x\n", *lint1_reg);
/* Configure Spurious Interrupt Vector Register:
* - APIC software enable (bit 8) - required for LAPIC to work
* - Spurious vector = 0x0F (matches legacy 8259 PIC IRQ7 spurious interrupt)
*/
val = *sivr_reg;
printf(" xAPIC SIVR before: 0x%08x\n", val);
val &= ~SIVR_VECTOR_MASK;
val |= SIVR_APIC_ENABLE | 0x0F;
*sivr_reg = val;
printf(" xAPIC SIVR after: 0x%08x\n", *sivr_reg);
}
/*
* Prepare APIC for legacy BIOS operation.
*
* This function handles the APIC configuration needed for legacy software
* that expects PIC interrupts (especially IRQ0 timer) to work correctly.
*
* Strategy: Keep LAPIC enabled in xAPIC mode with LINT0 configured for
* ExtINT passthrough. This matches QEMU's default behavior and is the
* standard configuration for legacy BIOS systems.
*
* - If in x2APIC mode (not locked): transition to xAPIC, configure ExtINT
* - If in x2APIC mode (locked): configure ExtINT via MSR (cannot leave x2APIC)
* - If already in xAPIC mode: configure ExtINT via MMIO
*/
void apic_prepare_for_legacy(void)
{
uint64_t apic_base_msr;
uintptr_t apic_base_addr;
bool lapic_enabled, x2apic_enabled;
printf("Configuring APIC for legacy BIOS compatibility...\n");
load_nmi_madt_info();
printf(" NMI on LINT%u (MADT flags 0x%04x)\n", g_nmi_lint, g_nmi_madt_flags);
/* Read current APIC state */
apic_base_msr = rdmsr(MSR_IA32_APIC_BASE);
apic_base_addr = apic_base_msr & APIC_BASE_ADDR_MASK;
lapic_enabled = !!(apic_base_msr & APIC_BASE_EN);
x2apic_enabled = !!(apic_base_msr & APIC_BASE_EXTD);
printf(" IA32_APIC_BASE: 0x%016lx (addr=0x%lx, EN=%d, x2APIC=%d, BSP=%d)\n",
apic_base_msr, apic_base_addr,
lapic_enabled, x2apic_enabled,
!!(apic_base_msr & APIC_BASE_BSP));
if (!lapic_enabled) {
printf(" LAPIC disabled, enabling in xAPIC mode\n");
apic_base_msr |= APIC_BASE_EN;
apic_base_msr &= ~APIC_BASE_EXTD;
wrmsr(MSR_IA32_APIC_BASE, apic_base_msr);
apic_base_addr = apic_base_msr & APIC_BASE_ADDR_MASK;
xapic_configure_for_legacy(apic_base_addr);
printf(" APIC configuration complete\n");
return;
}
if (x2apic_enabled) {
/* Check if x2APIC mode is locked */
bool locked = x2apic_is_locked();
printf(" x2APIC lock status: %s\n", locked ? "LOCKED" : "not locked");
if (!locked) {
/*
* Transition from x2APIC to xAPIC mode.
* Cannot go directly x2APIC -> xAPIC (causes #GP).
* Must disable first, then re-enable in xAPIC mode.
*/
printf(" Transitioning x2APIC -> xAPIC mode\n");
/* Step 1: Disable LAPIC (clear both EN and EXTD) */
apic_base_msr &= ~(APIC_BASE_EN | APIC_BASE_EXTD);
wrmsr(MSR_IA32_APIC_BASE, apic_base_msr);
/* Step 2: Re-enable in xAPIC mode (set EN, keep EXTD clear) */
apic_base_msr |= APIC_BASE_EN;
wrmsr(MSR_IA32_APIC_BASE, apic_base_msr);
/* Verify transition */
apic_base_msr = rdmsr(MSR_IA32_APIC_BASE);
printf(" IA32_APIC_BASE after: 0x%016lx (EN=%d, x2APIC=%d)\n",
apic_base_msr,
!!(apic_base_msr & APIC_BASE_EN),
!!(apic_base_msr & APIC_BASE_EXTD));
/* Now configure LAPIC via MMIO */
xapic_configure_for_legacy(apic_base_addr);
} else {
/*
* x2APIC is locked. Cannot leave x2APIC mode without #GP.
* Configure LAPIC for legacy operation via MSR.
*/
printf(" x2APIC locked, configuring for legacy via MSR\n");
x2apic_configure_for_legacy();
}
} else {
/*
* Already in xAPIC mode. Configure LAPIC via MMIO.
* This matches QEMU's default LAPIC configuration.
*/
printf(" Configuring xAPIC for legacy operation\n");
xapic_configure_for_legacy(apic_base_addr);
}
printf(" APIC configuration complete\n");
}
================================================
FILE: src/apic.h
================================================
/*
* APIC handling for legacy BIOS compatibility
*/
#ifndef _APIC_H
#define _APIC_H
/*
* Prepare APIC for legacy BIOS operation.
*
* Disables LAPIC or configures it for ExtINT passthrough so that
* legacy 8259 PIC interrupts (especially IRQ0 timer) can reach the CPU.
*
* Must be called after ExitBootServices but before CSM initialization.
*/
void apic_prepare_for_legacy(void);
#endif /* _APIC_H */
================================================
FILE: src/arch/ia32/Thunk16.asm
================================================
;------------------------------------------------------------------------------
;
; Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
;
; Thunk.asm
;
; Abstract:
;
; Real mode thunk
;
;------------------------------------------------------------------------------
%define THUNK_ATTRIBUTE_BIG_REAL_MODE 0x00000001
%define THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 0x00000002
%define THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL 0x00000004
%define ASM_PFX(name) name
global ASM_PFX(m16Size)
global ASM_PFX(mThunk16Attr)
global ASM_PFX(m16Gdt)
global ASM_PFX(m16GdtrBase)
global ASM_PFX(mTransition)
global ASM_PFX(m16Start)
struc IA32_REGS
._EDI: resd 1
._ESI: resd 1
._EBP: resd 1
._ESP: resd 1
._EBX: resd 1
._EDX: resd 1
._ECX: resd 1
._EAX: resd 1
._DS: resw 1
._ES: resw 1
._FS: resw 1
._GS: resw 1
._EFLAGS: resd 1
._EIP: resd 1
._CS: resw 1
._SS: resw 1
.size:
endstruc
;; .const
SECTION .data
;
; These are global constant to convey information to C code.
;
ASM_PFX(m16Size) DW ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)
ASM_PFX(mThunk16Attr) DW _BackFromUserCode.ThunkAttrEnd - 4 - ASM_PFX(m16Start)
ASM_PFX(m16Gdt) DW _NullSegDesc - ASM_PFX(m16Start)
ASM_PFX(m16GdtrBase) DW _16GdtrBase - ASM_PFX(m16Start)
ASM_PFX(mTransition) DW _EntryPoint - ASM_PFX(m16Start)
SECTION .text
ASM_PFX(m16Start):
SavedGdt:
dw 0
dd 0
;------------------------------------------------------------------------------
; _BackFromUserCode() takes control in real mode after 'retf' has been executed
; by user code. It will be shadowed to somewhere in memory below 1MB.
;------------------------------------------------------------------------------
_BackFromUserCode:
;
; The order of saved registers on the stack matches the order they appears
; in IA32_REGS structure. This facilitates wrapper function to extract them
; into that structure.
;
BITS 16
push ss
push cs
;
; Note: We can't use o32 on the next instruction because of a bug
; in NASM 2.09.04 through 2.10rc1.
;
call dword .Base ; push eip
.Base:
pushfd
cli ; disable interrupts
push gs
push fs
push es
push ds
pushad
mov edx, strict dword 0
.ThunkAttrEnd:
test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15
jz .1
mov ax, 2401h
int 15h
cli ; disable interrupts
jnc .2
.1:
test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL
jz .2
in al, 92h
or al, 2
out 92h, al ; deactivate A20M#
.2:
xor eax, eax
mov ax, ss
lea ebp, [esp + IA32_REGS.size]
mov [bp - IA32_REGS.size + IA32_REGS._ESP], ebp
mov bx, [bp - IA32_REGS.size + IA32_REGS._EIP]
shl eax, 4 ; shl eax, 4
add ebp, eax ; add ebp, eax
mov eax, strict dword 0
.SavedCr4End:
mov cr4, eax
o32 lgdt [cs:bx + (SavedGdt - .Base)]
mov eax, strict dword 0
.SavedCr3End:
mov cr3, eax ; restore page tables before enabling paging
mov eax, strict dword 0
.SavedCr0End:
mov cr0, eax
mov ax, strict word 0
.SavedSsEnd:
mov ss, eax
mov esp, strict dword 0
.SavedEspEnd:
o32 retf ; return to protected mode
_EntryPoint:
DD _ToUserCode - ASM_PFX(m16Start)
DW 8h
_16Idtr:
DW (1 << 10) - 1
DD 0
_16Gdtr_zero:
DW 0
DD 0
_16Gdtr:
DW GdtEnd - _NullSegDesc - 1
_16GdtrBase:
DD 0
;------------------------------------------------------------------------------
; _ToUserCode() takes control in real mode before passing control to user code.
; It will be shadowed to somewhere in memory below 1MB.
;------------------------------------------------------------------------------
_ToUserCode:
BITS 16
mov dx, ss
mov ss, cx ; set new segment selectors
mov ds, cx
mov es, cx
mov fs, cx
mov gs, cx
and byte [edi + 5], 0xFD ; clear TSS busy bit for next ltr
mov cx, TSS_SEL
ltr cx
mov cr0, eax ; real mode starts at next instruction
; which (per SDM) *must* be a far JMP.
jmp 0:strict word 0
.RealAddrEnd:
mov cr4, ebp
xor eax, eax
mov cr3, eax ; clear stale page table pointer
mov ss, si ; set up 16-bit stack segment
xchg esp, ebx ; set up 16-bit stack pointer
mov bp, [esp + IA32_REGS.size]
mov [cs:bp + (_BackFromUserCode.SavedSsEnd - 2 - _BackFromUserCode)], dx
mov [cs:bp + (_BackFromUserCode.SavedEspEnd - 4 - _BackFromUserCode)], ebx
lidt [cs:bp + (_16Idtr - _BackFromUserCode)]
lgdt [cs:bp + (_16Gdtr_zero - _BackFromUserCode)]
popad
pop ds
pop es
pop fs
pop gs
popfd
o32 retf ; transfer control to user code
ALIGN 16
_NullSegDesc DQ 0
_16CsDesc:
DW -1
DW 0
DB 0
DB 9bh
DB 8fh ; 16-bit segment, 4GB limit
DB 0
_16DsDesc:
DW -1
DW 0
DB 0
DB 93h
DB 8fh ; 16-bit segment, 4GB limit
DB 0
_TssSeg:
DW 0FFFFh ; Limit (match BIOS default)
DW 0 ; Base 15:0
DB 0 ; Base 23:16
DB 89h ; P=1, DPL=0, Type=9 (available TSS)
DB 0 ; G=0, Limit 19:16=0
DB 0 ; Base 31:24
TSS_SEL equ _TssSeg - _NullSegDesc
GdtEnd:
;------------------------------------------------------------------------------
; IA32_REGISTER_SET *
; EFIAPI
; InternalAsmThunk16 (
; IN IA32_REGISTER_SET *RegisterSet,
; IN OUT VOID *Transition
; );
;------------------------------------------------------------------------------
global ASM_PFX(InternalAsmThunk16)
ASM_PFX(InternalAsmThunk16):
BITS 32
push ebp
push ebx
push esi
push edi
push ds
push es
push fs
push gs
mov esi, [esp + 36] ; esi <- RegSet, the 1st parameter
movzx edx, word [esi + IA32_REGS._SS]
mov edi, [esi + IA32_REGS._ESP]
add edi, - (IA32_REGS.size + 4) ; reserve stack space
mov ebx, edi ; ebx <- stack offset
imul eax, edx, 16 ; eax <- edx * 16
push IA32_REGS.size / 4
add edi, eax ; edi <- linear address of 16-bit stack
pop ecx
rep movsd ; copy RegSet
mov eax, [esp + 40] ; eax <- address of transition code
mov esi, edx ; esi <- 16-bit stack segment
lea edx, [eax + (_BackFromUserCode.SavedCr0End - ASM_PFX(m16Start))]
mov ecx, eax
and ecx, 0fh
shl eax, 12
lea ecx, [ecx + (_BackFromUserCode - ASM_PFX(m16Start))]
mov ax, cx
stosd ; [edi] <- return address of user code
add eax, _ToUserCode.RealAddrEnd - _BackFromUserCode
mov [edx + (_ToUserCode.RealAddrEnd - 4 - _BackFromUserCode.SavedCr0End)], eax
sgdt [edx + (SavedGdt - _BackFromUserCode.SavedCr0End)]
sidt [esp + 36] ; save IDT stack in argument space
mov eax, cr0
mov [edx - 4], eax ; save CR0 in _BackFromUserCode.SavedCr0End - 4
mov eax, 00000010h ; clear all bits except ET
mov ebp, cr4
mov [edx + (_BackFromUserCode.SavedCr4End - 4 - _BackFromUserCode.SavedCr0End)], ebp
xor ebp, ebp ; zero out CR4
push eax ; save CR0 value (0x10)
mov eax, cr3
mov [edx + (_BackFromUserCode.SavedCr3End - 4 - _BackFromUserCode.SavedCr0End)], eax
pop eax ; restore CR0 value
lea edi, [edx + (_TssSeg - _BackFromUserCode.SavedCr0End)]
push 10h
pop ecx ; ecx <- selector for data segments
lgdt [edx + (_16Gdtr - _BackFromUserCode.SavedCr0End)]
pushfd ; Save df/if indeed
call dword far [edx + (_EntryPoint - _BackFromUserCode.SavedCr0End)]
popfd
lidt [esp + 36] ; restore protected mode IDTR
lea eax, [ebp - IA32_REGS.size] ; eax <- the address of IA32_REGS
pop gs
pop fs
pop es
pop ds
pop edi
pop esi
pop ebx
pop ebp
ret
================================================
FILE: src/arch/x86_64/Thunk16.asm
================================================
;------------------------------------------------------------------------------
;
; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Module Name:
;
; Thunk.asm
;
; Abstract:
;
; Real mode thunk
;
;------------------------------------------------------------------------------
%define THUNK_ATTRIBUTE_BIG_REAL_MODE 0x00000001
%define THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 0x00000002
%define THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL 0x00000004
%define ASM_PFX(name) name
global ASM_PFX(m16Size)
global ASM_PFX(mThunk16Attr)
global ASM_PFX(m16Gdt)
global ASM_PFX(m16GdtrBase)
global ASM_PFX(mTransition)
global ASM_PFX(m16Start)
struc IA32_REGS
._EDI: resd 1
._ESI: resd 1
._EBP: resd 1
._ESP: resd 1
._EBX: resd 1
._EDX: resd 1
._ECX: resd 1
._EAX: resd 1
._DS: resw 1
._ES: resw 1
._FS: resw 1
._GS: resw 1
._EFLAGS: resq 1
._EIP: resd 1
._CS: resw 1
._SS: resw 1
.size:
endstruc
SECTION .data
;
; These are global constant to convey information to C code.
;
ASM_PFX(m16Size) DW ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)
ASM_PFX(mThunk16Attr) DW _BackFromUserCode.ThunkAttrEnd - 4 - ASM_PFX(m16Start)
ASM_PFX(m16Gdt) DW _NullSeg - ASM_PFX(m16Start)
ASM_PFX(m16GdtrBase) DW _16GdtrBase - ASM_PFX(m16Start)
ASM_PFX(mTransition) DW _EntryPoint - ASM_PFX(m16Start)
SECTION .text
ASM_PFX(m16Start):
SavedGdt:
dw 0
dq 0
;------------------------------------------------------------------------------
; _BackFromUserCode() takes control in real mode after 'retf' has been executed
; by user code. It will be shadowed to somewhere in memory below 1MB.
;------------------------------------------------------------------------------
_BackFromUserCode:
;
; The order of saved registers on the stack matches the order they appears
; in IA32_REGS structure. This facilitates wrapper function to extract them
; into that structure.
;
BITS 16
push ss
push cs
;
; Note: We can't use o32 on the next instruction because of a bug
; in NASM 2.09.04 through 2.10rc1.
;
call dword .Base ; push eip
.Base:
push dword 0 ; reserved high order 32 bits of EFlags
pushfd
cli ; disable interrupts
push gs
push fs
push es
push ds
pushad
mov edx, strict dword 0
.ThunkAttrEnd:
test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15
jz .1
mov ax, 2401h
int 15h
cli ; disable interrupts
jnc .2
.1:
test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL
jz .2
in al, 92h
or al, 2
out 92h, al ; deactivate A20M#
.2:
xor eax, eax
mov ax, ss
lea ebp, [esp + IA32_REGS.size]
mov [bp - IA32_REGS.size + IA32_REGS._ESP], ebp
mov ebx, [bp - IA32_REGS.size + IA32_REGS._EIP]
shl eax, 4 ; shl eax, 4
add ebp, eax ; add ebp, eax
mov eax, cs
shl eax, 4
lea eax, [eax + ebx + (.X64JmpEnd - .Base)]
mov [cs:bx + (.X64JmpEnd - 6 - .Base)], eax
mov eax, strict dword 0
.SavedCr4End:
mov cr4, eax
o32 lgdt [cs:bx + (SavedGdt - .Base)]
mov ecx, 0c0000080h
mov eax, strict dword 0
.SavedEFERLowEnd:
mov edx, strict dword 0
.SavedEFERHighEnd:
wrmsr
mov eax, strict dword 0
.SavedCr3End:
mov cr3, eax ; restore page tables before enabling paging
mov eax, strict dword 0
.SavedCr0End:
mov cr0, eax
jmp 0:strict dword 0
.X64JmpEnd:
BITS 64
nop
mov rsp, strict qword 0
.SavedSpEnd:
nop
ret
_EntryPoint:
DD _ToUserCode - ASM_PFX(m16Start)
DW CODE16
_16Gdtr:
DW GDT_SIZE - 1
_16GdtrBase:
DQ 0
_16Idtr:
DW (1 << 10) - 1
DD 0
_16Gdtr_zero:
DW 0
DD 0
;------------------------------------------------------------------------------
; _ToUserCode() takes control in real mode before passing control to user code.
; It will be shadowed to somewhere in memory below 1MB.
;------------------------------------------------------------------------------
_ToUserCode:
BITS 16
mov ss, dx ; set new segment selectors
mov ds, dx
mov es, dx
mov fs, dx
mov gs, dx
and byte [edi + 5], 0xFD ; clear TSS busy bit for next ltr
mov cx, TSS_SEL
ltr cx
mov ecx, 0c0000080h
mov cr0, eax ; real mode starts at next instruction
xor eax, eax
mov cr3, eax ; clear stale page table pointer
xor edx, edx
wrmsr
mov cr4, ebp
mov ss, si ; set up 16-bit stack segment
mov esp, ebx ; set up 16-bit stack pointer
call dword .Base ; push eip
.Base:
pop ebp ; ebp <- address of .Base
push word [dword esp + IA32_REGS.size + 2]
lea ax, [bp + (.RealMode - .Base)]
push ax
retf ; execution begins at next instruction
.RealMode:
o32 lidt [cs:bp + (_16Idtr - .Base)]
o32 lgdt [cs:bp + (_16Gdtr_zero - .Base)]
popad
pop ds
pop es
pop fs
pop gs
popfd
lea esp, [esp + 4] ; skip high order 32 bits of EFlags
o32 retf ; transfer control to user code
ALIGN 8
CODE16 equ _16Code - $
DATA16 equ _16Data - $
DATA32 equ _32Data - $
_NullSeg DQ 0
_16Code:
DW -1
DW 0
DB 0
DB 9bh
DB 8fh ; 16-bit segment, 4GB limit
DB 0
_16Data:
DW -1
DW 0
DB 0
DB 93h
DB 8fh ; 16-bit segment, 4GB limit
DB 0
_32Data:
DW -1
DW 0
DB 0
DB 93h
DB 0cfh ; 16-bit segment, 4GB limit
DB 0
_TssSeg:
DW 0FFFFh ; Limit (match BIOS default)
DW 0 ; Base 15:0
DB 0 ; Base 23:16
DB 89h ; P=1, DPL=0, Type=9 (available TSS)
DB 0 ; G=0, Limit 19:16=0
DB 0 ; Base 31:24
DD 0 ; Base 63:32 (64-bit TSS descriptor
DD 0 ; requires 16 bytes in long mode)
TSS_SEL equ _TssSeg - _NullSeg
GDT_SIZE equ $ - _NullSeg
;------------------------------------------------------------------------------
; IA32_REGISTER_SET *
; EFIAPI
; InternalAsmThunk16 (
; IN IA32_REGISTER_SET *RegisterSet,
; IN OUT VOID *Transition
; );
;------------------------------------------------------------------------------
global ASM_PFX(InternalAsmThunk16)
ASM_PFX(InternalAsmThunk16):
BITS 64
push rbp
push rbx
push rsi
push rdi
mov ebx, ds
push rbx ; Save ds segment register on the stack
mov ebx, es
push rbx ; Save es segment register on the stack
mov ebx, ss
push rbx ; Save ss segment register on the stack
push fs
push gs
mov rsi, rcx
movzx r8d, word [rsi + IA32_REGS._SS]
mov edi, [rsi + IA32_REGS._ESP]
lea rdi, [edi - (IA32_REGS.size + 4)]
imul eax, r8d, 16 ; eax <- r8d(stack segment) * 16
mov ebx, edi ; ebx <- stack for 16-bit code
push IA32_REGS.size / 4
add edi, eax ; edi <- linear address of 16-bit stack
pop rcx
rep movsd ; copy RegSet
lea ecx, [rdx + (_BackFromUserCode.SavedCr4End - ASM_PFX(m16Start))]
mov eax, edx ; eax <- transition code address
and edx, 0fh
shl eax, 12 ; segment address in high order 16 bits
lea ax, [rdx + (_BackFromUserCode - ASM_PFX(m16Start))] ; offset address
stosd ; [edi] <- return address of user code
sgdt [rsp + 60h] ; save GDT stack in argument space
movzx r10, word [rsp + 60h] ; r10 <- GDT limit
lea r11, [rcx + (ASM_PFX(InternalAsmThunk16) - _BackFromUserCode.SavedCr4End) + 0xf]
and r11, ~0xf ; r11 <- 16-byte aligned shadowed GDT table in real mode buffer
mov [rcx + (SavedGdt - _BackFromUserCode.SavedCr4End)], r10w ; save the limit of shadowed GDT table
mov [rcx + (SavedGdt - _BackFromUserCode.SavedCr4End) + 2], r11 ; save the base address of shadowed GDT table
mov rsi, [rsp + 62h] ; rsi <- the original GDT base address
xchg rcx, r10 ; save rcx to r10 and initialize rcx to be the limit of GDT table
inc rcx ; rcx <- the size of memory to copy
xchg rdi, r11 ; save rdi to r11 and initialize rdi to the base address of shadowed GDT table
rep movsb ; perform memory copy to shadow GDT table
mov rcx, r10 ; restore the orignal rcx before memory copy
mov rdi, r11 ; restore the original rdi before memory copy
sidt [rsp + 50h] ; save IDT stack in argument space
mov rax, cr0
mov [rcx + (_BackFromUserCode.SavedCr0End - 4 - _BackFromUserCode.SavedCr4End)], eax
mov eax, 00000010h ; clear all bits except ET
push rax
push rcx
push rdx
mov ecx, 0c0000080h
rdmsr
btr eax, 10 ; Reset LMA flag to avoid crash on AMD Zen CPUs
mov r10d, eax
mov r11d, edx
pop rdx
pop rcx
pop rax
mov [rcx + (_BackFromUserCode.SavedEFERLowEnd - 4 - _BackFromUserCode.SavedCr4End)], r10d
mov [rcx + (_BackFromUserCode.SavedEFERHighEnd - 4 - _BackFromUserCode.SavedCr4End)], r11d
mov rbp, cr4
mov [rcx - 4], ebp ; save CR4 in _BackFromUserCode.SavedCr4End - 4
xor ebp, ebp ; zero out CR4
push rax ; save CR0 value (0x10)
mov rax, cr3
mov [rcx + (_BackFromUserCode.SavedCr3End - 4 - _BackFromUserCode.SavedCr4End)], eax
pop rax ; restore CR0 value
lea edi, [rcx + (_TssSeg - _BackFromUserCode.SavedCr4End)]
mov esi, r8d ; esi <- 16-bit stack segment
push DATA32
pop rdx ; rdx <- 32-bit data segment selector
lgdt [rcx + (_16Gdtr - _BackFromUserCode.SavedCr4End)]
mov ss, edx
pushfq
lea edx, [rdx + DATA16 - DATA32]
lea r8, [REL .RetFromRealMode]
push r8
mov r8d, cs
mov [rcx + (_BackFromUserCode.X64JmpEnd - 2 - _BackFromUserCode.SavedCr4End)], r8w
mov [rcx + (_BackFromUserCode.SavedSpEnd - 8 - _BackFromUserCode.SavedCr4End)], rsp
jmp dword far [rcx + (_EntryPoint - _BackFromUserCode.SavedCr4End)]
.RetFromRealMode:
popfq
lgdt [rsp + 60h] ; restore protected mode GDTR
lidt [rsp + 50h] ; restore protected mode IDTR
lea eax, [rbp - IA32_REGS.size]
pop gs
pop fs
pop rbx
mov ss, ebx
pop rbx
mov es, ebx
pop rbx
mov ds, ebx
pop rdi
pop rsi
pop rbx
pop rbp
ret
================================================
FILE: src/bios_proxy.c
================================================
/*
* BIOS Proxy Helper Core Support
*
* Starts a dedicated CPU core to handle BIOS calls when the main core
* is running in V86 mode (under EMM386). The helper core stays in
* protected mode and can execute call32 normally.
*/
#include <efi.h>
#include <csmwrap.h>
#include <config.h>
#include <io.h>
#include <time.h>
#include <uacpi/uacpi.h>
#include <uacpi/tables.h>
#include <uacpi/acpi.h>
/* Must match the signature in SeaBIOS stacks.c so it can find the mailbox. */
#define BIOS_PROXY_SIGNATURE 0x79787250504D5343ULL /* "CSMPPrxy" */
/* Authoritative size of the helper core's stack. SeaBIOS does not allocate
* or switch stacks for the helper - it runs every dispatched func_ptr (reset
* path, V86 BIOS handlers via call32_proxy, etc.) on this exact buffer - so
* this has to be deep enough for the worst-case proxied call chain. */
#define HELPER_STACK_SIZE 32768
struct bios_proxy_mailbox {
uint64_t signature;
volatile uint32_t request_pending;
uint32_t func_ptr;
uint32_t arg_eax;
uint32_t arg_edx;
uint32_t arg_ecx;
uint32_t result;
uint32_t helper_core_id;
/* UEFI reset callback fields (populated by CSMWrap) */
uint32_t reset_cr3;
uint32_t reset_fn_lo;
uint32_t reset_fn_hi;
};
/* Separately allocated stack for helper core */
static uint8_t *helper_stack_buffer = NULL;
/* Local APIC register offsets (xAPIC MMIO mode) */
#define LAPIC_ID 0x020
#define LAPIC_ICR_LOW 0x300
#define LAPIC_ICR_HIGH 0x310
/* APIC MSRs */
#define IA32_APIC_BASE_MSR 0x1B
#define APIC_BASE_ADDR_MASK 0xFFFFFFFFFFFFF000ULL /* Bits 12-51 contain base address */
#define APIC_BASE_EXTD (1 << 10) /* x2APIC mode enabled */
/* x2APIC MSRs */
#define X2APIC_ICR 0x830
#define X2APIC_ID 0x802
/* Get the LAPIC base address from IA32_APIC_BASE MSR */
static uintptr_t get_lapic_base(void)
{
return (uintptr_t)(rdmsr(IA32_APIC_BASE_MSR) & APIC_BASE_ADDR_MASK);
}
/* AP trampoline will be placed here */
#define AP_TRAMPOLINE_ADDR 0x7000
#define AP_TRAMPOLINE_VECTOR 0x07 /* SIPI vector = addr / 0x1000 */
static struct bios_proxy_mailbox *mailbox = NULL;
static uintptr_t mailbox_offset = 0;
static int selected_ap_id = -1;
static uint64_t reset_cr3_value = 0;
/*
* Build minimal identity-mapping page tables for the 64-bit reset path.
* Maps the first 4GB using 2MB pages (works on all x86-64 CPUs).
*
* Layout (6 pages = 24KB):
* Page 0: PML4 (1 entry → PDPT)
* Page 1: PDPT (4 entries → PD[0..3])
* Pages 2-5: PD[0..3] (512 × 2MB entries each = 1GB per PD)
*/
#define PT_P (1ULL << 0) /* Present */
#define PT_RW (1ULL << 1) /* Read/Write */
#define PT_PS (1ULL << 7) /* Page Size (2MB) */
#define RESET_PT_PAGES 6
static int build_reset_page_tables(void)
{
EFI_PHYSICAL_ADDRESS pt_addr = 0xFFFFFFFF;
EFI_STATUS status = gBS->AllocatePages(
AllocateMaxAddress,
EfiRuntimeServicesData,
RESET_PT_PAGES,
&pt_addr
);
if (EFI_ERROR(status)) {
printf("Failed to allocate reset page tables\n");
return -1;
}
memset((void *)(uintptr_t)pt_addr, 0, RESET_PT_PAGES * 4096);
uint64_t *pml4 = (uint64_t *)(uintptr_t)pt_addr;
uint64_t *pdpt = (uint64_t *)(uintptr_t)(pt_addr + 0x1000);
/* PML4[0] → PDPT */
pml4[0] = (pt_addr + 0x1000) | PT_P | PT_RW;
/* PDPT[0..3] → PD[0..3], each covering 1GB */
for (int i = 0; i < 4; i++) {
uint64_t pd_phys = pt_addr + 0x2000 + (uint64_t)i * 0x1000;
pdpt[i] = pd_phys | PT_P | PT_RW;
/* Fill PD with 512 × 2MB identity-mapped pages */
uint64_t *pd = (uint64_t *)(uintptr_t)pd_phys;
for (int j = 0; j < 512; j++) {
uint64_t phys = ((uint64_t)i * 512 + j) * 0x200000ULL;
pd[j] = phys | PT_P | PT_RW | PT_PS;
}
}
reset_cr3_value = pt_addr;
printf("Reset page tables at %p (4GB identity map, 2MB pages)\n",
(void *)(uintptr_t)pt_addr);
return 0;
}
/* Detect if running in x2APIC mode */
static int is_x2apic_mode(void)
{
uint64_t apic_base = rdmsr(IA32_APIC_BASE_MSR);
return (apic_base & APIC_BASE_EXTD) != 0;
}
/*
* Find the BIOS proxy mailbox in the CSM binary by scanning for signature.
*/
static uintptr_t find_proxy_mailbox(void *csm_base, size_t csm_size)
{
uint64_t *ptr = (uint64_t *)csm_base;
uint64_t *end = (uint64_t *)((uint8_t *)csm_base + csm_size - sizeof(struct bios_proxy_mailbox));
while (ptr < end) {
if (*ptr == BIOS_PROXY_SIGNATURE) {
return (uintptr_t)ptr - (uintptr_t)csm_base;
}
ptr++;
}
return 0;
}
/* Signature before 16-bit helper entry: "PRXY16EP" */
#define HELPER_16_ENTRY_SIGNATURE 0x5045363159585250ULL
/*
* Find the bios_proxy_helper_16_entry in the CSM binary by scanning for signature.
* Returns the linear address of the entry point.
*/
static uint32_t find_helper_16_entry(void *csm_base, size_t csm_size, uintptr_t final_base)
{
/* Signature is 8-byte aligned in romlayout.S */
uint64_t *base = (uint64_t *)csm_base;
uint64_t *end = (uint64_t *)((uint8_t *)csm_base + csm_size - 16);
for (uint64_t *ptr = base; ptr < end; ptr++) {
if (*ptr == HELPER_16_ENTRY_SIGNATURE) {
uint32_t offset_in_binary = ((uint8_t *)ptr - (uint8_t *)csm_base) + 8; /* Skip signature */
return (uint32_t)final_base + offset_in_binary;
}
}
return 0;
}
/* Trampoline from assembly file */
extern uint8_t ap_trampoline_start[];
extern uint32_t ap_trampoline_size_value;
extern uint32_t ap_trampoline_mailbox_offset;
extern uint32_t ap_trampoline_stack_offset;
extern uint32_t ap_trampoline_target16_offset;
extern uint32_t ap_trampoline_helper_ready_offset;
/*
* Create AP trampoline code at AP_TRAMPOLINE_ADDR
* target16_addr is a linear address which will be converted to segment:offset
*/
static void create_ap_trampoline(uint32_t target16_addr, uint32_t mailbox_addr, uint32_t stack_top)
{
uint8_t *tramp = (uint8_t *)AP_TRAMPOLINE_ADDR;
uint32_t size = ap_trampoline_size_value;
/* Convert linear address to segment:offset for far jump
* SeaBIOS is at 0xF0000 and expects CS=0xF000 (uses %cs: prefix for data access)
*/
uint16_t target_segment = 0xF000;
uint16_t target_offset = (uint16_t)(target16_addr - 0xF0000);
memcpy(tramp, ap_trampoline_start, size);
*(uint32_t *)(tramp + ap_trampoline_mailbox_offset) = mailbox_addr;
*(uint32_t *)(tramp + ap_trampoline_stack_offset) = stack_top;
/* Far pointer: offset first, then segment (little-endian) */
*(uint16_t *)(tramp + ap_trampoline_target16_offset) = target_offset;
*(uint16_t *)(tramp + ap_trampoline_target16_offset + 2) = target_segment;
}
/*
* Wait for ICR delivery to complete (xAPIC mode only)
*/
static void wait_icr_idle_xapic(uintptr_t lapic_base)
{
volatile uint32_t *icr_low = (volatile uint32_t *)(lapic_base + LAPIC_ICR_LOW);
int count = 0;
while (*icr_low & (1 << 12)) {
asm volatile ("pause");
if (++count > 1000000) return;
}
}
/*
* Send INIT-SIPI sequence (xAPIC MMIO mode)
*/
static void start_ap_xapic(uint32_t apic_id)
{
uintptr_t lapic_base = get_lapic_base();
volatile uint32_t *icr_high = (volatile uint32_t *)(lapic_base + LAPIC_ICR_HIGH);
volatile uint32_t *icr_low = (volatile uint32_t *)(lapic_base + LAPIC_ICR_LOW);
uint32_t dest = (apic_id & 0xFF) << 24; /* xAPIC physical destination is 8-bit */
wait_icr_idle_xapic(lapic_base);
*icr_high = dest;
*icr_low = 0x4500; /* INIT */
stall(10000);
wait_icr_idle_xapic(lapic_base);
*icr_high = dest;
*icr_low = 0x4600 | AP_TRAMPOLINE_VECTOR; /* SIPI */
stall(200);
wait_icr_idle_xapic(lapic_base);
*icr_high = dest;
*icr_low = 0x4600 | AP_TRAMPOLINE_VECTOR; /* SIPI (retry) */
wait_icr_idle_xapic(lapic_base);
}
/*
* Send INIT-SIPI sequence (x2APIC MSR mode)
*/
static void start_ap_x2apic(uint32_t apic_id)
{
wrmsr(X2APIC_ICR, ((uint64_t)apic_id << 32) | 0x4500); /* INIT */
stall(10000);
wrmsr(X2APIC_ICR, ((uint64_t)apic_id << 32) | 0x4600 | AP_TRAMPOLINE_VECTOR); /* SIPI */
stall(200);
wrmsr(X2APIC_ICR, ((uint64_t)apic_id << 32) | 0x4600 | AP_TRAMPOLINE_VECTOR); /* SIPI (retry) */
}
static void start_ap(uint32_t apic_id)
{
if (is_x2apic_mode()) {
start_ap_x2apic(apic_id);
} else {
start_ap_xapic(apic_id);
}
}
static uint32_t get_bsp_apic_id(void)
{
if (is_x2apic_mode()) {
return (uint32_t)rdmsr(X2APIC_ID);
}
uintptr_t lapic_base = get_lapic_base();
volatile uint32_t *lapic_id_reg = (volatile uint32_t *)(lapic_base + LAPIC_ID);
return (*lapic_id_reg >> 24) & 0xFF;
}
/*
* Walk the MADT and check if the given APIC ID names an enabled AP that
* we can deliver INIT-SIPI to (i.e. xAPIC-addressable: id < 0xFF).
*/
static bool madt_apic_id_is_valid_ap(uint32_t apic_id, uint32_t bsp_id)
{
if (apic_id == bsp_id || apic_id >= 0xFF)
return false;
struct uacpi_table madt_table;
if (uacpi_table_find_by_signature(ACPI_MADT_SIGNATURE, &madt_table)
!= UACPI_STATUS_OK) {
return false;
}
struct acpi_madt *madt = (struct acpi_madt *)madt_table.virt_addr;
uint8_t *entry = (uint8_t *)(madt + 1);
uint8_t *end = (uint8_t *)madt + madt->hdr.length;
bool ok = false;
while (entry < end) {
uint8_t type = entry[0];
uint8_t len = entry[1];
if (len < 2) break;
if (type == ACPI_MADT_ENTRY_TYPE_LAPIC) {
struct acpi_madt_lapic *lapic = (struct acpi_madt_lapic *)entry;
if (lapic->id == apic_id && (lapic->flags & ACPI_PIC_ENABLED)) {
ok = true;
break;
}
} else if (type == ACPI_MADT_ENTRY_TYPE_LOCAL_X2APIC) {
struct acpi_madt_x2apic *x2apic = (struct acpi_madt_x2apic *)entry;
if (x2apic->id == apic_id && (x2apic->flags & ACPI_PIC_ENABLED)) {
ok = true;
break;
}
}
entry += len;
}
uacpi_table_unref(&madt_table);
return ok;
}
/*
* Find an available AP to use as the system thread by parsing the MADT.
*
* If the user has pinned a specific APIC ID via the 'system_thread' config
* key, validate and use that. Otherwise, return the highest APIC ID AP so
* the system thread is least likely to be the one the OS would use first.
*/
static int find_available_ap(void)
{
uint32_t bsp_id = get_bsp_apic_id();
if (gConfig.system_thread_specified) {
uint32_t want = gConfig.system_thread_apic_id;
if (!madt_apic_id_is_valid_ap(want, bsp_id)) {
printf("BIOS proxy: configured system_thread APIC ID %u is not "
"a usable AP (must be enabled, not BSP %u, and < 0xFF)\n",
want, bsp_id);
return -1;
}
printf("BIOS proxy: using configured system thread (APIC ID %u)\n",
want);
return (int)want;
}
struct uacpi_table madt_table;
if (uacpi_table_find_by_signature(ACPI_MADT_SIGNATURE, &madt_table) != UACPI_STATUS_OK) {
return -1;
}
struct acpi_madt *madt = (struct acpi_madt *)madt_table.virt_addr;
uint8_t *entry = (uint8_t *)(madt + 1);
uint8_t *end = (uint8_t *)madt + madt->hdr.length;
int highest_ap_id = -1;
while (entry < end) {
uint8_t type = entry[0];
uint8_t len = entry[1];
if (len < 2) break;
if (type == ACPI_MADT_ENTRY_TYPE_LAPIC) {
struct acpi_madt_lapic *lapic = (struct acpi_madt_lapic *)entry;
if ((lapic->flags & 0x3) && lapic->id != bsp_id) {
if (lapic->id > highest_ap_id) highest_ap_id = lapic->id;
}
} else if (type == ACPI_MADT_ENTRY_TYPE_LOCAL_X2APIC) {
struct acpi_madt_x2apic *x2apic = (struct acpi_madt_x2apic *)entry;
/* Only consider APs with xAPIC-addressable IDs (<255) so we can
deliver INIT-SIPI; ID 0xFF is broadcast in physical dest mode */
if ((x2apic->flags & 0x3) && x2apic->id != bsp_id && x2apic->id < 0xFF) {
if ((int)x2apic->id > highest_ap_id) highest_ap_id = x2apic->id;
}
}
entry += len;
}
uacpi_table_unref(&madt_table);
return highest_ap_id;
}
/*
* Compute ACPI table checksum (sum of all bytes must be 0)
*/
static uint8_t acpi_checksum(void *data, size_t len)
{
uint8_t sum = 0;
uint8_t *p = (uint8_t *)data;
for (size_t i = 0; i < len; i++) {
sum += p[i];
}
return sum;
}
static void acpi_fix_checksum(struct acpi_sdt_hdr *hdr)
{
hdr->checksum = 0;
hdr->checksum = -acpi_checksum(hdr, hdr->length);
}
/* Pointers to allocated patched tables */
static void *patched_madt = NULL;
static void *patched_rsdt = NULL;
static void *patched_xsdt = NULL;
/*
* Decide whether a CPU MADT entry should appear in the OS-visible MADT.
*
* - The system thread (helper core) is always hidden.
* - The BSP is always kept (we run on it; the OS must see it).
* - Otherwise the user-configured allow/block list decides.
*/
static bool cpu_visible_to_os(uint32_t apic_id, uint32_t bsp_id,
int helper_apic_id)
{
if (helper_apic_id >= 0 && apic_id == (uint32_t)helper_apic_id)
return false;
if (apic_id == bsp_id)
return true;
return config_cpu_in_filter(apic_id);
}
/*
* Create a patched MADT with the helper core entry removed and any CPUs
* filtered out by the user's cpu_allowlist / cpu_blocklist also removed.
* Returns the new MADT or NULL on failure.
*/
static struct acpi_madt *create_patched_madt(int helper_apic_id)
{
struct uacpi_table madt_table;
if (uacpi_table_find_by_signature(ACPI_MADT_SIGNATURE, &madt_table) != UACPI_STATUS_OK) {
return NULL;
}
struct acpi_madt *orig_madt = (struct acpi_madt *)madt_table.virt_addr;
uint32_t orig_len = orig_madt->hdr.length;
uint32_t bsp_id = get_bsp_apic_id();
/* First pass: find entries to remove and calculate new size */
uint8_t *entry = (uint8_t *)(orig_madt + 1);
uint8_t *end = (uint8_t *)orig_madt + orig_len;
uint32_t removed_bytes = 0;
uint32_t removed_count = 0;
bool found_helper = false;
while (entry < end) {
uint8_t type = entry[0];
uint8_t len = entry[1];
if (len < 2) break;
uint32_t cpu_id;
bool is_cpu = false;
if (type == ACPI_MADT_ENTRY_TYPE_LAPIC) {
cpu_id = ((struct acpi_madt_lapic *)entry)->id;
is_cpu = true;
} else if (type == ACPI_MADT_ENTRY_TYPE_LOCAL_X2APIC) {
cpu_id = ((struct acpi_madt_x2apic *)entry)->id;
is_cpu = true;
}
if (is_cpu) {
if (helper_apic_id >= 0 && cpu_id == (uint32_t)helper_apic_id)
found_helper = true;
if (!cpu_visible_to_os(cpu_id, bsp_id, helper_apic_id)) {
removed_bytes += len;
removed_count++;
}
}
entry += len;
}
if (helper_apic_id >= 0 && !found_helper) {
printf("Warning: helper core APIC ID %d not found in MADT\n", helper_apic_id);
uacpi_table_unref(&madt_table);
return NULL;
}
/* Allocate new MADT (must be < 4GB for legacy OS) */
uint32_t new_len = orig_len - removed_bytes;
EFI_PHYSICAL_ADDRESS new_madt_addr = 0xFFFFFFFF;
EFI_STATUS status = gBS->AllocatePages(
AllocateMaxAddress,
EfiACPIReclaimMemory,
(new_len + 4095) / 4096,
&new_madt_addr
);
if (EFI_ERROR(status)) {
printf("Failed to allocate memory for patched MADT\n");
uacpi_table_unref(&madt_table);
return NULL;
}
struct acpi_madt *new_madt = (struct acpi_madt *)(uintptr_t)new_madt_addr;
/* Copy MADT header */
memcpy(new_madt, orig_madt, sizeof(struct acpi_madt));
/* Copy entries, skipping helper core and any filtered-out CPUs */
uint8_t *dst = (uint8_t *)(new_madt + 1);
entry = (uint8_t *)(orig_madt + 1);
while (entry < end) {
uint8_t type = entry[0];
uint8_t len = entry[1];
if (len < 2) break;
bool skip = false;
if (type == ACPI_MADT_ENTRY_TYPE_LAPIC) {
uint32_t id = ((struct acpi_madt_lapic *)entry)->id;
if (!cpu_visible_to_os(id, bsp_id, helper_apic_id))
skip = true;
} else if (type == ACPI_MADT_ENTRY_TYPE_LOCAL_X2APIC) {
uint32_t id = ((struct acpi_madt_x2apic *)entry)->id;
if (!cpu_visible_to_os(id, bsp_id, helper_apic_id))
skip = true;
}
if (!skip) {
memcpy(dst, entry, len);
dst += len;
}
entry += len;
}
/* Update header */
new_madt->hdr.length = new_len;
acpi_fix_checksum(&new_madt->hdr);
uacpi_table_unref(&madt_table);
printf("Created patched MADT at %p (removed %u CPU entries, "
"system thread APIC ID %d)\n",
(void *)new_madt, removed_count, helper_apic_id);
return new_madt;
}
/*
* Create patched RSDT with updated MADT pointer.
*/
static struct acpi_rsdt *create_patched_rsdt(struct acpi_rsdp *rsdp, uintptr_t new_madt_addr)
{
if (!rsdp->rsdt_addr) {
return NULL;
}
struct acpi_rsdt *orig_rsdt = (struct acpi_rsdt *)(uintptr_t)rsdp->rsdt_addr;
uint32_t len = orig_rsdt->hdr.length;
size_t num_entries = (len - sizeof(struct acpi_sdt_hdr)) / sizeof(uint32_t);
/* Allocate new RSDT */
EFI_PHYSICAL_ADDRESS new_rsdt_addr = 0xFFFFFFFF;
EFI_STATUS status = gBS->AllocatePages(
AllocateMaxAddress,
EfiACPIReclaimMemory,
(len + 4095) / 4096,
&new_rsdt_addr
);
if (EFI_ERROR(status)) {
printf("Failed to allocate memory for patched RSDT\n");
return NULL;
}
struct acpi_rsdt *new_rsdt = (struct acpi_rsdt *)(uintptr_t)new_rsdt_addr;
memcpy(new_rsdt, orig_rsdt, len);
/* Find and update all MADT entries (some firmware lists it more than once) */
for (size_t i = 0; i < num_entries; i++) {
struct acpi_sdt_hdr *hdr = (struct acpi_sdt_hdr *)(uintptr_t)new_rsdt->entries[i];
if (hdr && memcmp(hdr->signature, ACPI_MADT_SIGNATURE, 4) == 0) {
new_rsdt->entries[i] = (uint32_t)new_madt_addr;
}
}
acpi_fix_checksum(&new_rsdt->hdr);
printf("Created patched RSDT at %p\n", (void *)new_rsdt);
return new_rsdt;
}
/*
* Create patched XSDT with updated MADT pointer.
*/
static struct acpi_xsdt *create_patched_xsdt(struct acpi_rsdp *rsdp, uintptr_t new_madt_addr)
{
if (rsdp->revision < 2 || !rsdp->xsdt_addr) {
return NULL;
}
struct acpi_xsdt *orig_xsdt = (struct acpi_xsdt *)(uintptr_t)rsdp->xsdt_addr;
uint32_t len = orig_xsdt->hdr.length;
size_t num_entries = (len - sizeof(struct acpi_sdt_hdr)) / sizeof(uint64_t);
/* Allocate new XSDT */
EFI_PHYSICAL_ADDRESS new_xsdt_addr = 0xFFFFFFFF;
EFI_STATUS status = gBS->AllocatePages(
AllocateMaxAddress,
EfiACPIReclaimMemory,
(len + 4095) / 4096,
&new_xsdt_addr
);
if (EFI_ERROR(status)) {
printf("Failed to allocate memory for patched XSDT\n");
return NULL;
}
struct acpi_xsdt *new_xsdt = (struct acpi_xsdt *)(uintptr_t)new_xsdt_addr;
memcpy(new_xsdt, orig_xsdt, len);
/* Find and update all MADT entries (some firmware lists it more than once) */
for (size_t i = 0; i < num_entries; i++) {
struct acpi_sdt_hdr *hdr = (struct acpi_sdt_hdr *)(uintptr_t)new_xsdt->entries[i];
if (hdr && memcmp(hdr->signature, ACPI_MADT_SIGNATURE, 4) == 0) {
new_xsdt->entries[i] = (uint64_t)new_madt_addr;
}
}
acpi_fix_checksum(&new_xsdt->hdr);
printf("Created patched XSDT at %p\n", (void *)new_xsdt);
return new_xsdt;
}
/*
* Patch ACPI tables to hide the helper core from the OS.
* Updates the RSDP copy in CSM region to point to patched tables.
*/
static int patch_acpi_hide_helper(void *rsdp_copy, int helper_apic_id)
{
extern uintptr_t g_rsdp; /* Original RSDP from acpi.c */
if (!g_rsdp) {
printf("No RSDP available for MADT patching\n");
return -1;
}
struct acpi_rsdp *orig_rsdp = (struct acpi_rsdp *)g_rsdp;
struct acpi_rsdp *copy_rsdp = (struct acpi_rsdp *)rsdp_copy;
/* Create patched MADT */
struct acpi_madt *new_madt = create_patched_madt(helper_apic_id);
if (!new_madt) {
return -1;
}
patched_madt = new_madt;
/* Create patched RSDT */
struct acpi_rsdt *new_rsdt = create_patched_rsdt(orig_rsdp, (uintptr_t)new_madt);
if (new_rsdt) {
patched_rsdt = new_rsdt;
copy_rsdp->rsdt_addr = (uint32_t)(uintptr_t)new_rsdt;
}
/* Create patched XSDT (if ACPI 2.0+) */
struct acpi_xsdt *new_xsdt = create_patched_xsdt(orig_rsdp, (uintptr_t)new_madt);
if (new_xsdt) {
patched_xsdt = new_xsdt;
copy_rsdp->xsdt_addr = (uint64_t)(uintptr_t)new_xsdt;
}
/* Fix RSDP checksums */
copy_rsdp->checksum = 0;
copy_rsdp->checksum = -acpi_checksum(copy_rsdp, 20); /* First 20 bytes for ACPI 1.0 */
if (copy_rsdp->revision >= 2) {
copy_rsdp->extended_checksum = 0;
copy_rsdp->extended_checksum = -acpi_checksum(copy_rsdp, copy_rsdp->length);
}
printf("ACPI tables patched to hide helper core (APIC ID %d)\n", helper_apic_id);
return 0;
}
static void *saved_csm_base = NULL;
static size_t saved_csm_size = 0;
static void *saved_rsdp_copy = NULL;
/*
* Initialize the BIOS proxy helper core.
* Call after CSM binary is loaded but before ExitBootServices.
*
* Parameters:
* csm_base - Pointer to the loaded CSM binary
* csm_size - Size of the CSM binary
* rsdp_copy - Pointer to the RSDP copy in CSM region (for MADT patching)
*/
int bios_proxy_init(void *csm_base, size_t csm_size, void *rsdp_copy)
{
printf("Initializing BIOS proxy helper core...\n");
saved_csm_base = csm_base;
saved_csm_size = csm_size;
saved_rsdp_copy = rsdp_copy;
mailbox_offset = find_proxy_mailbox(csm_base, csm_size);
if (!mailbox_offset) {
printf("BIOS proxy mailbox not found\n");
return -1;
}
selected_ap_id = find_available_ap();
if (selected_ap_id < 0) {
printf("No AP available for BIOS proxy\n");
return -1;
}
/* Patch ACPI tables to hide the helper core from the OS */
if (rsdp_copy) {
if (patch_acpi_hide_helper(rsdp_copy, selected_ap_id) < 0) {
printf("Warning: Failed to patch MADT, OS may see helper core\n");
/* Continue anyway - helper will still work */
}
}
/* Build identity-mapping page tables for the 64-bit reset path */
if (build_reset_page_tables() < 0) {
printf("Warning: UEFI reset callback will not be available\n");
}
/* Allocate stack for helper core (must be < 4GB) */
EFI_PHYSICAL_ADDRESS stack_addr = 0xFFFFFFFF;
EFI_STATUS status = gBS->AllocatePages(
AllocateMaxAddress,
EfiRuntimeServicesData,
(HELPER_STACK_SIZE + 4095) / 4096,
&stack_addr
);
if (EFI_ERROR(status)) {
printf("Failed to allocate helper stack\n");
return -1;
}
helper_stack_buffer = (uint8_t *)(uintptr_t)stack_addr;
printf("BIOS proxy ready (AP %d)\n", selected_ap_id);
return 0;
}
/*
* Start the helper core.
* Call after ExitBootServices.
*/
int bios_proxy_start_helper(uintptr_t csm_final_base)
{
if (!mailbox_offset || !saved_csm_base || selected_ap_id < 0) {
return -1;
}
uint32_t target16_addr = find_helper_16_entry(saved_csm_base, saved_csm_size, csm_final_base);
if (!target16_addr) {
return -1;
}
mailbox = (struct bios_proxy_mailbox *)(csm_final_base + mailbox_offset);
/* Populate UEFI reset callback fields in the mailbox */
if (reset_cr3_value && gRT && gRT->ResetSystem) {
uint64_t fn = (uint64_t)(uintptr_t)gRT->ResetSystem;
mailbox->reset_cr3 = (uint32_t)reset_cr3_value;
mailbox->reset_fn_lo = (uint32_t)fn;
mailbox->reset_fn_hi = (uint32_t)(fn >> 32);
printf("UEFI ResetSystem callback at %p (CR3=%p)\n",
(void *)(uintptr_t)fn, (void *)(uintptr_t)reset_cr3_value);
} else {
mailbox->reset_cr3 = 0;
mailbox->reset_fn_lo = 0;
mailbox->reset_fn_hi = 0;
printf("Warning: UEFI ResetSystem callback not available\n");
}
if (!helper_stack_buffer) {
return -1;
}
uint32_t stack_top = (uint32_t)(uintptr_t)(helper_stack_buffer + HELPER_STACK_SIZE);
create_ap_trampoline(target16_addr, (uint32_t)(uintptr_t)mailbox, stack_top);
start_ap(selected_ap_id);
/* Wait for helper to signal ready */
volatile uint32_t *helper_ready = (volatile uint32_t *)(uintptr_t)(AP_TRAMPOLINE_ADDR + ap_trampoline_helper_ready_offset);
for (int timeout = 0; timeout < 100; timeout++) {
asm volatile ("" ::: "memory");
if (*helper_ready) {
return 0;
}
stall(10000);
}
return -1;
}
/*
* Get the APIC ID of the helper core.
* Returns -1 if no helper core has been selected.
*/
int bios_proxy_get_helper_apic_id(void)
{
return selected_ap_id;
}
================================================
FILE: src/bios_proxy.h
================================================
/*
* BIOS Proxy Helper Core Support
*
* Provides a dedicated CPU core to handle BIOS calls when the main core
* is running in V86 mode (under EMM386).
*/
#ifndef _BIOS_PROXY_H
#define _BIOS_PROXY_H
#include <stddef.h>
#include <stdint.h>
/*
* Initialize the BIOS proxy helper core.
* Call this after CSM binary is loaded but before Legacy16Boot.
*
* @param csm_base Base address of the loaded CSM binary
* @param csm_size Size of the CSM binary in bytes
* @param rsdp_copy Pointer to the RSDP copy in CSM region (for MADT patching)
* If NULL, MADT patching is skipped.
* @return 0 on success, -1 on failure
*/
int bios_proxy_init(void *csm_base, size_t csm_size, void *rsdp_copy);
/*
* Start the helper core.
* Call this after ExitBootServices when we have full control of the system,
* and after the CSM binary has been copied to its final location.
*
* @param csm_final_base The address where the CSM binary was copied to
* @return 0 on success, -1 on failure
*/
int bios_proxy_start_helper(uintptr_t csm_final_base);
/*
* Get the APIC ID of the helper core.
* Returns -1 if no helper core has been selected.
* Used by mptable generation to exclude the helper from MP tables.
*/
int bios_proxy_get_helper_apic_id(void);
#endif /* _BIOS_PROXY_H */
================================================
FILE: src/bootdev.c
================================================
#include <efi.h>
#include <csmwrap.h>
#include <bootdev.h>
#include <printf.h>
/*
* Boot device detection and BBS table building for CSMWrap
*
* This module detects which drive CSMWrap was booted from and creates
* a BBS table that prioritizes that drive for SeaBIOS boot order.
*/
/*
* Parse device path to extract boot device information
*/
static bool parse_device_path(EFI_DEVICE_PATH_PROTOCOL *device_path,
struct boot_device_info *info)
{
EFI_DEVICE_PATH_PROTOCOL *node;
bool found_pci = false;
if (!device_path || !info) {
return false;
}
memset(info, 0, sizeof(*info));
info->device_type = BBS_HARDDISK; /* Default to hard disk */
/* Walk the device path to extract information */
for (node = device_path; !IsDevicePathEnd(node); node = NextDevicePathNode(node)) {
uint8_t type = DevicePathType(node);
uint8_t subtype = DevicePathSubType(node);
switch (type) {
case HARDWARE_DEVICE_PATH:
if (subtype == HW_PCI_DP) {
PCI_DEVICE_PATH *pci = (PCI_DEVICE_PATH *)node;
info->bus = 0; /* Will be updated if we find ACPI path first */
info->device = pci->Device;
info->function = pci->Function;
found_pci = true;
}
break;
case MESSAGING_DEVICE_PATH:
switch (subtype) {
case MSG_SATA_DP:
{
SATA_DEVICE_PATH *sata = (SATA_DEVICE_PATH *)node;
info->sata_port = sata->HBAPortNumber;
info->device_type = BBS_HARDDISK;
}
break;
case MSG_USB_DP:
info->is_usb = true;
info->device_type = BBS_USB;
break;
case MSG_ATAPI_DP:
{
ATAPI_DEVICE_PATH *atapi = (ATAPI_DEVICE_PATH *)node;
/* Check if this is a CD-ROM based on typical ATAPI usage */
(void)atapi; /* May use later for more specific detection */
}
break;
case MSG_SCSI_DP:
info->device_type = BBS_HARDDISK;
break;
}
break;
case MEDIA_DEVICE_PATH:
switch (subtype) {
case MEDIA_HARDDRIVE_DP:
info->device_type = BBS_HARDDISK;
break;
case MEDIA_CDROM_DP:
info->device_type = BBS_CDROM;
break;
}
break;
}
}
info->valid = found_pci;
return found_pci;
}
/*
* Get PCI bus number by walking up to the PCI I/O protocol
*/
static bool get_pci_location(EFI_HANDLE device_handle, struct boot_device_info *info)
{
EFI_STATUS status;
EFI_GUID pci_io_guid = EFI_PCI_IO_PROTOCOL_GUID;
EFI_GUID device_path_guid = EFI_DEVICE_PATH_PROTOCOL_GUID;
EFI_DEVICE_PATH_PROTOCOL *device_path;
EFI_PCI_IO_PROTOCOL *pci_io;
EFI_HANDLE pci_handle;
UINTN seg, bus, dev, func;
/* First get the device path */
status = gBS->HandleProtocol(device_handle, &device_path_guid,
(void **)&device_path);
if (EFI_ERROR(status) || !device_path) {
printf("bootdev: Failed to get device path: %d\n", (int)status);
return false;
}
/* Parse the device path for basic info */
parse_device_path(device_path, info);
/* Try to find PCI I/O protocol on this device path */
status = gBS->LocateDevicePath(&pci_io_guid, &device_path, &pci_handle);
if (EFI_ERROR(status)) {
printf("bootdev: No PCI I/O on device path: %d\n", (int)status);
return info->valid; /* Return what we got from device path parsing */
}
/* Get the PCI I/O protocol */
status = gBS->HandleProtocol(pci_handle, &pci_io_guid, (void **)&pci_io);
if (EFI_ERROR(status)) {
printf("bootdev: Failed to get PCI I/O protocol: %d\n", (int)status);
return info->valid;
}
/* Get the actual PCI location */
status = pci_io->GetLocation(pci_io, &seg, &bus, &dev, &func);
if (EFI_ERROR(status)) {
printf("bootdev: Failed to get PCI location: %d\n", (int)status);
return info->valid;
}
info->bus = (uint8_t)bus;
info->device = (uint8_t)dev;
info->function = (uint8_t)func;
info->valid = true;
/* Read PCI class code from config space offset 0x0B (class) and 0x0A (subclass) */
uint8_t class_code[2];
status = pci_io->Pci.Read(pci_io, EfiPciIoWidthUint8, 0x0A, 2, class_code);
if (!EFI_ERROR(status)) {
info->pci_subclass = class_code[0]; /* Offset 0x0A */
info->pci_class = class_code[1]; /* Offset 0x0B */
}
printf("bootdev: PCI location %02x:%02x.%x class=%02x subclass=%02x\n",
info->bus, info->device, info->function, info->pci_class, info->pci_subclass);
return true;
}
/*
* Check if two boot device info structures match (same controller)
*/
static bool devices_match(const struct boot_device_info *a,
const struct boot_device_info *b)
{
if (!a->valid || !b->valid) {
return false;
}
return (a->bus == b->bus &&
a->device == b->device &&
a->function == b->function);
}
/*
* Get device type string for debug output
*/
static const char *device_type_str(uint16_t type)
{
switch (type) {
case BBS_FLOPPY: return "Floppy";
case BBS_HARDDISK: return "HDD";
case BBS_CDROM: return "CDROM";
case BBS_PCMCIA: return "PCMCIA";
case BBS_USB: return "USB";
case BBS_EMBED_NETWORK: return "Network";
default: return "Unknown";
}
}
/*
* Add a BBS entry for a block device
*
* priority: 0 = highest (boot device), 1+ = lower priority
*/
static void add_bbs_entry(struct low_stub *low_stub,
const struct boot_device_info *info,
int priority)
{
BBS_TABLE *entry;
char *desc;
size_t idx;
if (low_stub->bbs_entry_count >= MAX_BBS_ENTRIES) {
printf("bootdev: BBS table full, skipping device\n");
return;
}
idx = low_stub->bbs_entry_count;
entry = &low_stub->bbs_entries[idx];
desc = low_stub->bbs_desc_strings[idx];
memset(entry, 0, sizeof(*entry));
/* Set boot priority - 0 is highest, higher numbers = lower priority */
entry->BootPriority = priority;
/* PCI location */
entry->Bus = info->bus;
entry->Device = info->device;
entry->Function = info->function;
/* Device type */
entry->DeviceType = info->device_type;
/* PCI class codes - use actual values from device */
entry->Class = info->pci_class;
entry->SubClass = info->pci_subclass;
/* Status flags - mark as enabled and media present */
entry->StatusFlags.Enabled = 1;
entry->StatusFlags.MediaPresent = 2; /* Media present and bootable */
/* Description string - stored in low memory */
if (priority == 0) {
snprintf(desc, BBS_DESC_STRING_SIZE, "Boot %s %02x:%02x.%x",
device_type_str(info->device_type),
info->bus, info->device, info->function);
} else {
snprintf(desc, BBS_DESC_STRING_SIZE, "%s %02x:%02x.%x",
device_type_str(info->device_type),
info->bus, info->device, info->function);
}
/* Set description string pointer (segment:offset for real mode) */
uintptr_t desc_addr = (uintptr_t)desc;
entry->DescStringSegment = EFI_SEGMENT(desc_addr);
entry->DescStringOffset = EFI_OFFSET(desc_addr);
printf("bootdev: BBS[%zu] %s pri=%d\n", idx, desc, entry->BootPriority);
low_stub->bbs_entry_count++;
}
/*
* Enumerate block I/O devices and build BBS entries
*/
static int enumerate_block_devices(struct low_stub *low_stub,
const struct boot_device_info *boot_info)
{
EFI_STATUS status;
EFI_GUID block_io_guid = EFI_BLOCK_IO_PROTOCOL_GUID;
EFI_HANDLE *handles = NULL;
UINTN handle_count = 0;
int next_priority = 1; /* Priority 0 reserved for boot device */
/* Find all block I/O devices */
status = gBS->LocateHandleBuffer(ByProtocol, &block_io_guid, NULL,
&handle_count, &handles);
if (EFI_ERROR(status)) {
printf("bootdev: Failed to locate block devices: %d\n", (int)status);
return -1;
}
printf("bootdev: Found %lu block devices\n", (unsigned long)handle_count);
for (UINTN i = 0; i < handle_count; i++) {
EFI_BLOCK_IO_PROTOCOL *block_io;
struct boot_device_info dev_info;
status = gBS->HandleProtocol(handles[i], &block_io_guid, (void **)&block_io);
if (EFI_ERROR(status)) {
continue;
}
/* Skip logical partitions, only want raw devices */
if (block_io->Media->LogicalPartition) {
continue;
}
/* Get PCI location for this device */
if (!get_pci_location(handles[i], &dev_info)) {
continue;
}
bool is_boot_device = boot_info->valid && devices_match(&dev_info, boot_info);
int priority = is_boot_device ? 0 : next_priority++;
add_bbs_entry(low_stub, &dev_info, priority);
}
gBS->FreePool(handles);
return 0;
}
/*
* Main entry point: build BBS table for SeaBIOS
*/
int build_bbs_table(struct csmwrap_priv *priv, EFI_HANDLE image_handle)
{
EFI_STATUS status;
EFI_GUID loaded_image_guid = EFI_LOADED_IMAGE_PROTOCOL_GUID;
EFI_LOADED_IMAGE_PROTOCOL *loaded_image = NULL;
struct boot_device_info boot_info = {0};
struct low_stub *low_stub = priv->low_stub;
if (!low_stub) {
printf("bootdev: low_stub not initialized\n");
return -1;
}
printf("bootdev: Building BBS table...\n");
/* Get loaded image protocol to find boot device */
status = gBS->HandleProtocol(image_handle, &loaded_image_guid,
(void **)&loaded_image);
if (EFI_ERROR(status) || !loaded_image) {
printf("bootdev: Failed to get loaded image: %d\n", (int)status);
/* Continue without boot device info - will enumerate all devices */
} else if (loaded_image->DeviceHandle) {
/* Get boot device information */
printf("bootdev: Detecting boot device...\n");
if (get_pci_location(loaded_image->DeviceHandle, &boot_info)) {
printf("bootdev: Boot device: PCI %02x:%02x.%x type=%s\n",
boot_info.bus, boot_info.device, boot_info.function,
device_type_str(boot_info.device_type));
}
}
/* Reset BBS table */
low_stub->bbs_entry_count = 0;
memset(low_stub->bbs_entries, 0, sizeof(low_stub->bbs_entries));
memset(low_stub->bbs_desc_strings, 0, sizeof(low_stub->bbs_desc_strings));
/* Enumerate all block devices and build BBS entries */
if (enumerate_block_devices(low_stub, &boot_info) < 0) {
printf("bootdev: Failed to enumerate block devices\n");
/* Not fatal - SeaBIOS can still enumerate drives itself */
}
/* Set up boot_table to point to our BBS table */
if (low_stub->bbs_entry_count > 0) {
low_stub->boot_table.NumberBbsEntries = low_stub->bbs_entry_count;
low_stub->boot_table.BbsTable = (uintptr_t)low_stub->bbs_entries;
printf("bootdev: BBS table built with %zu entries\n", low_stub->bbs_entry_count);
} else {
printf("bootdev: No BBS entries created\n");
}
return 0;
}
================================================
FILE: src/bootdev.h
================================================
#ifndef _BOOTDEV_H
#define _BOOTDEV_H
#include <efi.h>
/* Forward declaration */
struct csmwrap_priv;
/*
* Boot device detection and BBS table building
*
* This module detects the boot device (the drive CSMWrap was loaded from)
* and builds a BBS (BIOS Boot Specification) table for SeaBIOS with the
* boot device prioritized first.
*/
/* Boot device information extracted from device path */
struct boot_device_info {
bool valid;
uint8_t bus;
uint8_t device;
uint8_t function;
uint8_t pci_class; /* PCI class code */
uint8_t pci_subclass; /* PCI subclass code */
uint16_t device_type; /* BBS_HARDDISK, BBS_CDROM, etc. */
bool is_usb;
uint16_t sata_port; /* SATA port number if applicable */
};
/*
* Detect boot device and build BBS table
*
* This function:
* 1. Parses the device path of the boot device to get PCI location
* 2. Enumerates all block I/O devices
* 3. Builds a BBS table with the boot device at highest priority
*
* @param priv CSMWrap private data structure (must have low_stub initialized)
* @param image_handle EFI image handle (used to get loaded image info)
* @return 0 on success, -1 on failure
*/
int build_bbs_table(struct csmwrap_priv *priv, EFI_HANDLE image_handle);
#endif /* _BOOTDEV_H */
================================================
FILE: src/config.c
================================================
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#include <efi.h>
#include <csmwrap.h>
#include <config.h>
#include <printf.h>
struct csmwrap_config gConfig = {
.serial_debug = false,
.serial_port = 0x3f8,
.serial_baud = 115200,
.vgabios_path = {0},
.iommu_disable = true,
.verbose = false,
.vga_specified = false,
.vga_bus = 0,
.vga_device = 0,
.vga_function = 0,
.system_thread_specified = false,
.system_thread_apic_id = 0,
.cpu_filter_mode = CPU_FILTER_NONE,
.cpu_filter_list = NULL,
.cpu_filter_count = 0,
};
bool config_cpu_in_filter(uint32_t apic_id)
{
if (gConfig.cpu_filter_mode == CPU_FILTER_NONE)
return true;
bool found = false;
for (size_t i = 0; i < gConfig.cpu_filter_count; i++) {
if (gConfig.cpu_filter_list[i] == apic_id) {
found = true;
break;
}
}
if (gConfig.cpu_filter_mode == CPU_FILTER_ALLOWLIST)
return found;
/* CPU_FILTER_BLOCKLIST */
return !found;
}
static bool char_eq_nocase(char a, char b)
{
if (a >= 'A' && a <= 'Z') a += 'a' - 'A';
if (b >= 'A' && b <= 'Z') b += 'a' - 'A';
return a == b;
}
static bool streq_nocase(const char *a, const char *b)
{
while (*a && *b) {
if (!char_eq_nocase(*a, *b))
return false;
a++;
b++;
}
return *a == *b;
}
static bool parse_bool(const char *val, bool *out)
{
if (streq_nocase(val, "true") || streq_nocase(val, "yes") || streq_nocase(val, "1")) {
*out = true;
return true;
}
if (streq_nocase(val, "false") || streq_nocase(val, "no") || streq_nocase(val, "0")) {
*out = false;
return true;
}
return false;
}
static bool parse_uint32(const char *val, uint32_t *out)
{
uint32_t result = 0;
bool hex = false;
if (val[0] == '0' && (val[1] == 'x' || val[1] == 'X')) {
hex = true;
val += 2;
}
if (*val == '\0')
return false;
while (*val) {
char c = *val;
uint32_t digit;
if (c >= '0' && c <= '9') {
digit = c - '0';
} else if (hex && c >= 'a' && c <= 'f') {
digit = 10 + c - 'a';
} else if (hex && c >= 'A' && c <= 'F') {
digit = 10 + c - 'A';
} else {
return false;
}
result = result * (hex ? 16 : 10) + digit;
val++;
}
*out = result;
return true;
}
static bool parse_hex_byte(const char *s, size_t len, uint32_t *out)
{
if (len == 0)
return false;
uint32_t result = 0;
for (size_t i = 0; i < len; i++) {
char c = s[i];
uint32_t digit;
if (c >= '0' && c <= '9')
digit = c - '0';
else if (c >= 'a' && c <= 'f')
digit = 10 + c - 'a';
else if (c >= 'A' && c <= 'F')
digit = 10 + c - 'A';
else
return false;
result = result * 16 + digit;
}
*out = result;
return true;
}
/*
* Parse a single token (already null-terminated) of the form "N" or "N-M"
* into either a single value or an inclusive range. Both N and M are
* decimal or 0x-prefixed hex. Whitespace around the '-' is allowed.
*
* Returns false on malformed input or if N > M.
*/
static bool parse_apic_id_token(char *tok, uint32_t *lo, uint32_t *hi)
{
char *dash = NULL;
/* Skip a leading 0x prefix when scanning for '-' so we don't mistake
* the hex digit sequence for a range delimiter (no negatives allowed). */
char *scan = tok;
if (scan[0] == '0' && (scan[1] == 'x' || scan[1] == 'X'))
scan += 2;
for (char *q = scan; *q; q++) {
if (*q == '-') { dash = q; break; }
}
if (!dash) {
uint32_t v;
if (!parse_uint32(tok, &v))
return false;
*lo = *hi = v;
return true;
}
/* Split into "lo" and "hi" halves, trimming whitespace around the dash. */
char *lo_end = dash;
while (lo_end > tok && (lo_end[-1] == ' ' || lo_end[-1] == '\t'))
lo_end--;
char *hi_start = dash + 1;
while (*hi_start == ' ' || *hi_start == '\t')
hi_start++;
if (lo_end == tok || *hi_start == '\0')
return false;
*lo_end = '\0';
uint32_t lo_v, hi_v;
if (!parse_uint32(tok, &lo_v) || !parse_uint32(hi_start, &hi_v))
return false;
if (lo_v > hi_v)
return false;
*lo = lo_v;
*hi = hi_v;
return true;
}
/*
* Parse a comma-separated list of APIC IDs.
*
* Each entry is either a single ID (decimal or 0x-prefixed hex) or an
* inclusive range "N-M". Whitespace around commas and dashes is ignored.
*
* If out is non-NULL, expanded IDs are written to out[0 .. *out_count - 1]
* and parsing fails if more than out_capacity entries would be produced.
* If out is NULL, the call counts entries without writing anything; this
* lets callers size an allocation up front.
*
* Returns false on malformed input.
*/
static bool parse_apic_id_list(const char *val, uint32_t *out,
size_t out_capacity, size_t *out_count)
{
size_t count = 0;
const char *p = val;
while (*p) {
while (*p == ' ' || *p == '\t')
p++;
if (*p == '\0' || *p == ',') {
if (*p == ',') p++;
continue;
}
const char *start = p;
while (*p && *p != ',')
p++;
const char *end = p;
while (end > start && (end[-1] == ' ' || end[-1] == '\t'))
end--;
char buf[64];
size_t len = (size_t)(end - start);
if (len == 0 || len >= sizeof(buf))
return false;
for (size_t i = 0; i < len; i++)
buf[i] = start[i];
buf[len] = '\0';
uint32_t lo, hi;
if (!parse_apic_id_token(buf, &lo, &hi))
return false;
for (uint32_t v = lo; ; v++) {
if (out != NULL) {
if (count >= out_capacity)
return false;
out[count] = v;
}
/* Guard against size_t overflow: a single uint32_t range can
* span 2^32 entries, which wraps size_t on 32-bit builds. */
if (count == SIZE_MAX)
return false;
count++;
if (v == hi)
break;
}
if (*p == ',')
p++;
}
*out_count = count;
return true;
}
/*
* Parse a PCI address in BB:DD.F format (all hex).
*/
static bool parse_pci_address(const char *val, uint8_t *bus, uint8_t *device, uint8_t *function)
{
/* Find ':' separator between bus and device */
const char *colon = NULL;
for (const char *p = val; *p; p++) {
if (*p == ':') { colon = p; break; }
}
if (!colon)
return false;
/* Find '.' separator between device and function */
const char *dot = NULL;
for (const char *p = colon + 1; *p; p++) {
if (*p == '.') { dot = p; break; }
}
if (!dot)
return false;
uint32_t b, d, f;
if (!parse_hex_byte(val, (size_t)(colon - val), &b) || b > 0xFF)
return false;
if (!parse_hex_byte(colon + 1, (size_t)(dot - colon - 1), &d) || d > 0x1F)
return false;
size_t flen = 0;
while (dot[1 + flen]) flen++;
if (!parse_hex_byte(dot + 1, flen, &f) || f > 0x7)
return false;
*bus = (uint8_t)b;
*device = (uint8_t)d;
*function = (uint8_t)f;
return true;
}
static const char *skip_whitespace(const char *s)
{
while (*s == ' ' || *s == '\t')
s++;
return s;
}
static size_t trim_trailing(const char *start, size_t len)
{
while (len > 0 && (start[len - 1] == ' ' || start[len - 1] == '\t' ||
start[len - 1] == '\r' || start[len - 1] == '\n'))
len--;
return len;
}
/*
* Parse a single key=value line and apply it to gConfig.
* key and val are null-terminated, trimmed strings.
*/
static void config_apply(const char *key, const char *val)
{
if (streq_nocase(key, "serial")) {
bool v;
if (parse_bool(val, &v)) {
gConfig.serial_debug = v;
printf(" serial = %s\n", v ? "true" : "false");
} else {
printf(" warning: invalid value for 'serial': %s\n", val);
}
} else if (streq_nocase(key, "serial_port")) {
uint32_t v;
if (parse_uint32(val, &v) && v <= 0xFFFF) {
gConfig.serial_port = (uint16_t)v;
printf(" serial_port = 0x%x\n", gConfig.serial_port);
} else {
printf(" warning: invalid value for 'serial_port': %s\n", val);
}
} else if (streq_nocase(key, "serial_baud")) {
uint32_t v;
if (parse_uint32(val, &v) && v > 0) {
gConfig.serial_baud = v;
printf(" serial_baud = %u\n", gConfig.serial_baud);
} else {
printf(" warning: invalid value for 'serial_baud': %s\n", val);
}
} else if (streq_nocase(key, "vgabios")) {
/* Convert ASCII path to CHAR16 */
size_t i;
for (i = 0; val[i] && i < CONFIG_VGABIOS_PATH_MAX - 1; i++)
gConfig.vgabios_path[i] = (CHAR16)(unsigned char)val[i];
gConfig.vgabios_path[i] = 0;
printf(" vgabios = %s\n", val);
} else if (streq_nocase(key, "iommu_disable")) {
bool v;
if (parse_bool(val, &v)) {
gConfig.iommu_disable = v;
printf(" iommu_disable = %s\n", v ? "true" : "false");
} else {
printf(" warning: invalid value for 'iommu_disable': %s\n", val);
}
} else if (streq_nocase(key, "verbose")) {
bool v;
if (parse_bool(val, &v)) {
gConfig.verbose = v;
printf(" verbose = %s\n", v ? "true" : "false");
} else {
printf(" warning: invalid value for 'verbose': %s\n", val);
}
} else if (streq_nocase(key, "vga")) {
uint8_t b, d, f;
if (parse_pci_address(val, &b, &d, &f)) {
gConfig.vga_specified = true;
gConfig.vga_bus = b;
gConfig.vga_device = d;
gConfig.vga_function = f;
printf(" vga = %02x:%02x.%x\n", b, d, f);
} else {
printf(" warning: invalid PCI address for 'vga': %s (expected BB:DD.F)\n", val);
}
} else if (streq_nocase(key, "system_thread")) {
uint32_t v;
if (parse_uint32(val, &v)) {
gConfig.system_thread_specified = true;
gConfig.system_thread_apic_id = v;
printf(" system_thread = APIC ID %u\n", v);
} else {
printf(" warning: invalid value for 'system_thread': %s\n", val);
}
} else if (streq_nocase(key, "cpu_allowlist") ||
streq_nocase(key, "cpu_blocklist")) {
enum csmwrap_cpu_filter_mode mode =
streq_nocase(key, "cpu_allowlist") ? CPU_FILTER_ALLOWLIST
: CPU_FILTER_BLOCKLIST;
if (gConfig.cpu_filter_mode != CPU_FILTER_NONE &&
gConfig.cpu_filter_mode != mode) {
printf(" warning: '%s' ignored - cpu_allowlist and cpu_blocklist "
"are mutually exclusive\n", key);
} else {
/* First pass: validate syntax and compute the expanded count. */
size_t count = 0;
if (!parse_apic_id_list(val, NULL, 0, &count)) {
printf(" warning: invalid value for '%s': %s\n", key, val);
} else if (count > SIZE_MAX / sizeof(uint32_t)) {
/* Allocation size would wrap size_t. */
printf(" warning: '%s' has too many entries (%zu)\n",
key, count);
} else {
uint32_t *list = NULL;
if (count > 0) {
EFI_STATUS st = gBS->AllocatePool(
EfiLoaderData, count * sizeof(uint32_t),
(void **)&list);
if (EFI_ERROR(st)) {
printf(" warning: out of memory for '%s' (%zu IDs)\n",
key, count);
goto cpu_filter_done;
}
/* Second pass: actually fill the buffer. */
size_t actual = 0;
if (!parse_apic_id_list(val, list, count, &actual)
|| actual != count) {
gBS->FreePool(list);
printf(" warning: parse mismatch for '%s'\n", key);
goto cpu_filter_done;
}
}
/* Replace any previously-set list. */
if (gConfig.cpu_filter_list) {
gBS->FreePool(gConfig.cpu_filter_list);
gConfig.cpu_filter_list = NULL;
}
gConfig.cpu_filter_mode = mode;
gConfig.cpu_filter_list = list;
gConfig.cpu_filter_count = count;
if (count == 0) {
printf(" %s = (empty)%s\n", key,
mode == CPU_FILTER_ALLOWLIST
? " - only the BSP will be visible to the OS"
: " - no CPUs hidden");
} else {
printf(" %s = %zu APIC ID(s):", key, count);
/* Cap the printed list so a giant range doesn't spam. */
size_t shown = count < 16 ? count : 16;
for (size_t i = 0; i < shown; i++)
printf(" %u", list[i]);
if (shown < count)
printf(" ... (+%zu more)", count - shown);
printf("\n");
}
}
cpu_filter_done: ;
}
} else {
printf(" warning: unknown config key '%s'\n", key);
}
}
/*
* Parse an INI-style buffer (flat key=value, no sections).
*/
static void config_parse(char *buf, size_t len)
{
char *line = buf;
char *end = buf + len;
while (line < end) {
/* Find end of line */
char *eol = line;
while (eol < end && *eol != '\n')
eol++;
/* Null-terminate the line */
if (eol < end)
*eol = '\0';
const char *p = skip_whitespace(line);
/* Skip empty lines and comments */
if (*p == '\0' || *p == ';' || *p == '#') {
line = eol + 1;
continue;
}
/* Find '=' separator */
const char *eq = p;
while (*eq && *eq != '=')
eq++;
if (*eq != '=') {
printf(" warning: malformed line (no '='): %s\n", p);
line = eol + 1;
continue;
}
/* Extract key: from p to eq, trimmed */
size_t key_len = trim_trailing(p, (size_t)(eq - p));
if (key_len == 0) {
line = eol + 1;
continue;
}
/* Null-terminate key in place */
char *key_start = (char *)p;
key_start[key_len] = '\0';
/* Extract value: after '=', trimmed */
const char *val_start = skip_whitespace(eq + 1);
size_t val_len = trim_trailing(val_start, eol - val_start);
/* Null-terminate value in place */
char *val_mut = (char *)val_start;
val_mut[val_len] = '\0';
config_apply(key_start, val_mut);
line = eol + 1;
}
}
/*
* Build the config file path by finding the directory of the running
* EFI executable from its device path and appending "csmwrap.ini".
*/
static bool config_build_path(EFI_DEVICE_PATH_PROTOCOL *file_path,
CHAR16 *out, size_t out_chars)
{
if (!file_path)
return false;
/* Reconstruct the file path string from FILEPATH_DEVICE_PATH nodes */
size_t pos = 0;
out[0] = 0;
EFI_DEVICE_PATH_PROTOCOL *node;
for (node = file_path; !IsDevicePathEnd(node); node = NextDevicePathNode(node)) {
if (DevicePathType(node) == MEDIA_DEVICE_PATH &&
DevicePathSubType(node) == MEDIA_FILEPATH_DP) {
FILEPATH_DEVICE_PATH *fp = (FILEPATH_DEVICE_PATH *)node;
CHAR16 *src = fp->PathName;
while (*src && pos < out_chars - 1) {
out[pos++] = *src++;
}
}
}
out[pos] = 0;
if (pos == 0)
return false;
/* Find the last backslash to strip the filename */
size_t last_sep = 0;
bool found_sep = false;
for (size_t i = 0; i < pos; i++) {
if (out[i] == L'\\' || out[i] == L'/') {
last_sep = i;
found_sep = true;
}
}
size_t dir_end;
if (found_sep) {
dir_end = last_sep + 1; /* keep the trailing backslash */
} else {
/* No separator - file is at root, prepend backslash */
dir_end = 0;
if (pos + 1 < out_chars) {
out[0] = L'\\';
dir_end = 1;
}
}
/* Append "csmwrap.ini" */
static const CHAR16 ini_name[] = L"csmwrap.ini";
size_t name_len = sizeof(ini_name) / sizeof(CHAR16) - 1;
if (dir_end + name_len >= out_chars)
return false;
for (size_t i = 0; i <= name_len; i++)
out[dir_end + i] = ini_name[i];
return true;
}
void config_load(EFI_FILE_PROTOCOL *root_dir, EFI_DEVICE_PATH_PROTOCOL *file_path)
{
if (!root_dir || !file_path)
return;
CHAR16 path[512];
if (!config_build_path(file_path, path, ARRAY_SIZE(path))) {
printf("Config: could not determine executable directory\n");
return;
}
EFI_FILE_PROTOCOL *file = NULL;
EFI_STATUS status = root_dir->Open(root_dir, &file, path, EFI_FILE_MODE_READ, 0);
if (status != EFI_SUCCESS) {
/* Not an error - config file is optional */
return;
}
/* Get file size via EFI_FILE_INFO */
EFI_GUID fi_guid = EFI_FILE_INFO_ID;
UINTN info_size = 0;
file->GetInfo(file, &fi_guid, &info_size, NULL);
void *info_buf = NULL;
if (gBS->AllocatePool(EfiLoaderData, info_size, &info_buf) != EFI_SUCCESS) {
file->Close(file);
return;
}
UINTN file_size = 0;
if (file->GetInfo(file, &fi_guid, &info_size, info_buf) == EFI_SUCCESS) {
EFI_FILE_INFO *fi = info_buf;
file_size = (UINTN)fi->FileSize;
}
gBS->FreePool(info_buf);
if (file_size == 0 || file_size > 64 * 1024) {
printf("Config: file empty or too large (%lu bytes)\n", (unsigned long)file_size);
file->Close(file);
return;
}
/* Read file contents */
char *buf = NULL;
if (gBS->AllocatePool(EfiLoaderData, file_size + 1, (void **)&buf) != EFI_SUCCESS) {
file->Close(file);
return;
}
UINTN read_size = file_size;
if (file->Read(file, &read_size, buf) != EFI_SUCCESS) {
gBS->FreePool(buf);
file->Close(file);
return;
}
buf[read_size] = '\0';
file->Close(file);
printf("Config: loaded csmwrap.ini (%lu bytes)\n", (unsigned long)read_size);
config_parse(buf, read_size);
gBS->FreePool(buf);
}
================================================
FILE: src/config.h
================================================
#ifndef CONFIG_H
#define CONFIG_H
#include <stddef.h>
#include <stdbool.h>
#include <stdint.h>
#include <efi.h>
#define CONFIG_VGABIOS_PATH_MAX 256
enum csmwrap_cpu_filter_mode {
CPU_FILTER_NONE = 0,
CPU_FILTER_ALLOWLIST,
CPU_FILTER_BLOCKLIST,
};
struct csmwrap_config {
bool serial_debug;
uint16_t serial_port;
uint32_t serial_baud;
CHAR16 vgabios_path[CONFIG_VGABIOS_PATH_MAX];
bool iommu_disable;
bool verbose;
bool vga_specified;
uint8_t vga_bus;
uint8_t vga_device;
uint8_t vga_function;
bool system_thread_specified;
uint32_t system_thread_apic_id;
/*
* cpu_filter_list points to an EFI-pool-allocated array of length
* cpu_filter_count, or is NULL when cpu_filter_count == 0. An empty
* list with mode ALLOWLIST means "no APs visible to the OS"; an
* empty list with mode BLOCKLIST means "no APs hidden from the OS".
*/
enum csmwrap_cpu_filter_mode cpu_filter_mode;
uint32_t *cpu_filter_list;
size_t cpu_filter_count;
};
extern struct csmwrap_config gConfig;
/*
* Returns true if the CPU with the given APIC ID is allowed by the
* user-configured allow/block list. Does NOT consider BSP-must-keep or
* system-thread-must-hide rules - callers handle those separately.
*
* With CPU_FILTER_NONE this always returns true.
*/
bool config_cpu_in_filter(uint32_t apic_id);
/*
* Load configuration from csmwrap.ini next to the running EFI executable.
* root_dir: filesystem root opened via EFI_SIMPLE_FILE_SYSTEM_PROTOCOL
* file_path: loaded image's FilePath device path (used to find our directory)
*
* If the file is missing or unreadable, defaults are silently retained.
*/
void config_load(EFI_FILE_PROTOCOL *root_dir, EFI_DEVICE_PATH_PROTOCOL *file_path);
#endif
================================================
FILE: src/coreboot.c
================================================
#include <efi.h>
#include "csmwrap.h"
static UINT16
CbCheckSum16 (
IN UINT16 *Buffer,
IN UINTN Length
)
{
UINT32 Sum;
UINT32 TmpValue;
UINTN Idx;
UINT8 *TmpPtr;
Sum = 0;
TmpPtr = (UINT8 *)Buffer;
for (Idx = 0; Idx < Length; Idx++) {
TmpValue = TmpPtr[Idx];
if (Idx % 2 == 1) {
TmpValue <<= 8;
}
Sum += TmpValue;
// Wrap
if (Sum >= 0x10000) {
Sum = (Sum + (Sum >> 16)) & 0xFFFF;
}
}
return (UINT16)((~Sum) & 0xFFFF);
}
int build_coreboot_table(struct csmwrap_priv *priv)
{
void *p = (void *)CB_TABLE_START;
void *tables;
uint32_t table_entries = 0;
struct cb_header *header = (struct cb_header *)p;
memset(header, 0, sizeof(struct cb_header));
header->signature = CB_HEADER_SIGNATURE;
header->header_bytes = sizeof(struct cb_header);
p += header->header_bytes;
tables = p;
/* cb_framebuffer */
if (priv->video_type != CSMWRAP_VIDEO_OPROM) {
struct cb_framebuffer *framebuffer = (struct cb_framebuffer *)p;
memcpy(framebuffer, &priv->cb_fb, sizeof(struct cb_framebuffer));
framebuffer->tag = CB_TAG_FRAMEBUFFER;
framebuffer->size = sizeof(struct cb_framebuffer);
p += framebuffer->size;
table_entries++;
}
/* Last header stuff */
header->table_entries = table_entries;
header->table_bytes = (uint32_t)((uintptr_t)p - (uintptr_t)tables);
header->table_checksum = CbCheckSum16((UINT16*)tables, header->table_bytes);
header->header_checksum = CbCheckSum16((UINT16*)header, header->header_bytes);
return 0;
}
================================================
FILE: src/csmwrap.c
================================================
#include <stdarg.h>
#include <efi.h>
#include <csmwrap.h>
#include <io.h>
#include <x86thunk.h>
#include <video.h>
#include <bootdev.h>
#include <iommu.h>
#include <apic.h>
#include <pci.h>
#include <time.h>
#include <bios_proxy.h>
#include <mptable.h>
#include <pir.h>
#include <config.h>
#include <oprom.h>
#include <flanterm.h>
#include <flanterm_backends/fb.h>
// Generated by: xxd -i Csm16.bin >> Csm16.h
#include <bins/Csm16.h>
#ifndef BUILD_VERSION
#define BUILD_VERSION "Unknown"
#endif
const char *banner =
"\033[38;2;0;102;128m _,,,,,,,,,,_\n"
" _,;l!l'''''''''''''l;l;,_\n"
" ,;l!''....................`ql;,_\n"
" ,;l'`............................`ql;_\n"
" ,;l'..........\033[38;2;141;211;95m_____\033[38;2;0;102;128m...................`ql,\n"
" lp`.........\033[38;2;141;211;95m,;#######;,\033[38;2;0;102;128m..................'ql\n"
" ,l'......\033[38;2;141;211;95m_,;####\033[38;2;228;230;109mooooooo\033[38;2;141;211;95m##;_\033[38;2;0;102;128m..................ql,\n"
" ,l'....\033[38;2;141;211;95m,#######################+,\033[38;2;0;102;128m..............ql,\n"
",l'...\033[38;2;141;211;95m,##############################,\033[38;2;0;102;128m...........ql,\n"
"lp....\033[38;2;199;221;133m############\033[38;2;141;211;95m######################,\033[38;2;0;102;128m.........ql \n"
"lp....\033[38;2;199;221;133m###############\033[38;2;141;211;95m######################,\033[38;2;0;102;128m......ql\n"
"lp....\033[38;2;199;221;133m`################\033[38;2;141;211;95m#####################\\\033[38;2;0;102;128m.....ql \n"
"lp.....\033[38;2;199;221;133m`################\033[38;2;141;211;95m#####################\\\033[38;2;0;102;128m....ql\n"
"`l,......\033[38;2;199;221;133m`###############\033[38;2;141;211;95m#####################\033[38;2;0;102;128m...,l'\n"
" `l........\033[38;2;199;221;133m`\"#########\033[38;2;141;211;95m########################\033[38;2;0;102;128m..,l'\n"
" `l,.........\033[38;2;199;221;133m`\"\"#####\033[38;2;141;211;95m######################%\033[38;2;0;102;128m..,l'\n"
" `l,.........\033[38;2;141;211;95m,,,,,;####################%\"\033[38;2;0;102;128m...,l' \n"
" `l;,...\033[38;2;141;211;95m\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"\"'\033[38;2;0;102;128m.....,;l' \n"
" `l;,_.............................._,;l' \n"
" `l;,_......................._,;l'' \n"
" `'l;p,_............_,,;lll'`\n"
" `'''::::::::::'''\033[0m\n"
"CSMWrap Version " BUILD_VERSION "\n"
"https://github.com/CSMWrap/CSMWrap\n"
"By: Jiaxun Yang <jiaxun.yang@flygoat.com>\n"
"And: Mintsuki <mintsuki@protonmail.com>\n";
EFI_SYSTEM_TABLE *gST;
EFI_BOOT_SERVICES *gBS;
EFI_RUNTIME_SERVICES *gRT;
EFI_TIME gTimeAtBoot;
bool gBootServicesExited = false;
struct csmwrap_priv priv = {
.csm_bin = Csm16_bin,
};
/*
* UEFI memory allocation wrappers for Flanterm.
* These use EFI Boot Services pool allocation.
*/
static void *flanterm_uefi_malloc(size_t size)
{
void *ptr = NULL;
if (gBS->AllocatePool(EfiLoaderData, size, &ptr) != EFI_SUCCESS) {
return NULL;
}
return ptr;
}
static void flanterm_uefi_free(void *ptr, size_t size)
{
(void)size; /* UEFI FreePool doesn't need size */
if (ptr != NULL) {
gBS->FreePool(ptr);
}
}
static void *find_table(uint32_t signature, uint8_t *csm_bin_base, size_t size)
{
/* Compatibility16 header: signature[4], checksum[1], length[1], ... */
for (uint8_t *Ptr = csm_bin_base; Ptr + 6 <= csm_bin_base + size; Ptr += 0x10) {
if (*(uint32_t *)Ptr != signature)
continue;
uint8_t table_len = Ptr[5];
if (table_len < 6 || (size_t)(Ptr - csm_bin_base) + table_len > size)
continue;
uint8_t sum = 0;
for (uint8_t i = 0; i < table_len; i++)
sum += Ptr[i];
if (sum == 0)
return Ptr;
}
return NULL;
}
/*
* SMBIOS entry point structures
*/
#define SMBIOS_21_SIGNATURE 0x5f4d535f /* "_SM_" */
#define SMBIOS_21_ENTRY_POINT_LENGTH 0x1F /* Standard length */
#pragma pack(1)
struct smbios_21_entry_point {
uint32_t signature; /* "_SM_" */
uint8_t checksum; /* Checksum of bytes 0x00-0x0F */
uint8_t length; /* Entry point length (usually 0x1F) */
uint8_t smbios_major_version;
uint8_t smbios_minor_version;
uint16_t max_structure_size;
uint8_t entry_point_revision;
uint8_t formatted_area[5];
char intermediate_anchor_string[5]; /* "_DMI_" */
uint8_t intermediate_checksum; /* Checksum of bytes 0x10-0x1E */
uint16_t structure_table_length; /* Total length of structure table */
uint32_t structure_table_address; /* Physical address of structure table */
uint16_t number_of_structures;
uint8_t smbios_bcd_revision;
};
struct smbios_30_entry_point {
char signature[5]; /* "_SM3_" */
uint8_t checksum;
uint8_t length;
uint8_t smbios_major_version;
uint8_t smbios_minor_version;
uint8_t smbios_docrev;
uint8_t entry_point_revision;
uint8_t reserved;
uint32_t structure_table_max_size;
uint64_t structure_table_address; /* 64-bit! */
};
/* SMBIOS structure header - at the start of every structure */
struct smbios_structure_header {
uint8_t type;
uint8_t length; /* Length of formatted area only, not including strings */
uint16_t handle;
};
#pragma pack()
static uint8_t smbios_checksum(const void *data, size_t len)
{
const uint8_t *p = data;
uint8_t sum = 0;
for (size_t i = 0; i < len; i++)
sum += p[i];
return sum;
}
/*
* Statistics gathered from walking the SMBIOS structure table.
* Using uint32_t for sizes to avoid overflow during calculation,
* even though SMBIOS 2.x limits these to 16-bit values.
*/
struct smbios_table_stats {
uint32_t number_of_structures;
uint32_t max_structure_size;
uint32_t table_length;
};
/*
* Walk the SMBIOS structure table and gather statistics.
* The structure table format is the same for SMBIOS 2.x and 3.0.
*
* Each structure consists of:
* - Formatted area (header.length bytes, starting with the header)
* - Unformatted area (null-terminated strings, ending with double-null)
*
* Returns true on success, false if the table appears corrupted.
*/
static bool smbios_walk_table(const void *table, uint32_t max_size, struct smbios_table_stats *stats)
{
const uint8_t *ptr = table;
const uint8_t *end = ptr + max_size;
stats->number_of_structures = 0;
stats->max_structure_size = 0;
stats->table_length = 0;
while (ptr + sizeof(struct smbios_structure_header) <= end) {
const struct smbios_structure_header *hdr = (const struct smbios_structure_header *)ptr;
/* Sanity check: length must be at least header size */
if (hdr->length < sizeof(struct smbios_structure_header)) {
printf(" Warning: Invalid structure length %u at offset %u\n",
hdr->length, (uint32_t)(ptr - (const uint8_t *)table));
return false;
}
/* Check formatted area doesn't exceed bounds */
if (ptr + hdr->length > end) {
printf(" Warning: Structure exceeds table bounds\n");
return false;
}
/* Find the end of the unformatted area (strings) */
const uint8_t *strings_start = ptr + hdr->length;
const uint8_t *strings_ptr = strings_start;
/* Look for double-null terminator */
bool found_terminator = false;
while (strings_ptr + 1 < end) {
if (strings_ptr[0] == 0 && strings_ptr[1] == 0) {
strings_ptr += 2; /* Include both nulls */
found_terminator = true;
break;
}
strings_ptr++;
}
if (!found_terminator) {
printf(" Warning: Missing double-null terminator\n");
return false;
}
/* Calculate this structure's total size */
uint32_t struct_size = (uint32_t)(strings_ptr - ptr);
if (struct_size > stats->max_structure_size) {
stats->max_structure_size = struct_size;
}
stats->number_of_structures++;
/* Type 127 marks end of table */
if (hdr->type == 127) {
stats->table_length = (uint32_t)(strings_ptr - (const uint8_t *)table);
return true;
}
ptr = strings_ptr;
}
/* Reached end without finding type 127 - use what we have */
stats->table_length = (uint32_t)(ptr - (const uint8_t *)table);
return true;
}
/*
* Allocated buffer for synthesized/relocated SMBIOS data.
*/
static void *smbios_buffer = NULL;
/*
* Synthesize an SMBIOS 2.x entry point from SMBIOS 3.0 data.
* The structure table data format is identical; only the entry point differs.
*
* Allocates memory for entry point + structure table below 4GB.
* Returns the new SMBIOS 2.x entry point, or NULL on failure.
*/
static struct smbios_21_entry_point *synthesize_smbios_21_from_30(
struct smbios_30_entry_point *ep30,
uint64_t st_addr,
uint32_t st_max_size)
{
/* Walk the structure table to get accurate statistics */
struct smbios_table_stats stats;
if (!smbios_walk_table((void *)(uintptr_t)st_addr, st_max_size, &stats)) {
printf(" Failed to parse SMBIOS structure table\n");
return NULL;
}
printf(" Table stats: %u structures, max size %u, actual length %u\n",
stats.number_of_structures, stats.max_structure_size, stats.table_length);
/* Check for SMBIOS 2.x limitations (16-bit fields) */
if (stats.table_length > 0xFFFF) {
printf(" Warning: Table length %u exceeds SMBIOS 2.x limit (65535)\n",
stats.table_length);
/* Truncate - some data will be missing but better than nothing */
stats.table_length = 0xFFFF;
}
if (stats.max_structure_size > 0xFFFF) {
printf(" Warning: Max structure size exceeds SMBIOS 2.x limit\n");
stats.max_structure_size = 0xFFFF;
}
if (stats.number_of_structures > 0xFFFF) {
printf(" Warning: Structure count exceeds SMBIOS 2.x limit\n");
stats.number_of_structures = 0xFFFF;
}
/* Allocate buffer for entry point + structure table below 4GB */
size_t total_size = SMBIOS_21_ENTRY_POINT_LENGTH + stats.table_length;
EFI_PHYSICAL_ADDRESS max_addr = 0xFFFFFFFF;
EFI_STATUS status = gBS->AllocatePages(
AllocateMaxAddress,
EfiRuntimeServicesData,
(total_size + EFI_PAGE_SIZE - 1) / EFI_PAGE_SIZE,
&max_addr
);
if (status != EFI_SUCCESS) {
printf(" Failed to allocate memory for SMBIOS synthesis\n");
return NULL;
}
smbios_buffer = (void *)(uintptr_t)max_addr;
printf(" Synthesizing SMBIOS 2.x at %p\n", smbios_buffer);
/* Build the SMBIOS 2.x entry point */
struct smbios_21_entry_point *ep21 = smbios_buffer;
memset(ep21, 0, SMBIOS_21_ENTRY_POINT_LENGTH);
ep21->signature = SMBIOS_21_SIGNATURE;
ep21->length = SMBIOS_21_ENTRY_POINT_LENGTH;
ep21->smbios_major_version = ep30->smbios_major_version;
ep21->smbios_minor_version = ep30->smbios_minor_version;
ep21->max_structure_size = (uint16_t)stats.max_structure_size;
ep21->entry_point_revision = 0;
memcpy(ep21->intermediate_anchor_string, "_DMI_", 5);
ep21->structure_table_length = (uint16_t)stats.table_length;
ep21->number_of_structures = stats.number_of_structures;
/* BCD revision: major in high nibble, minor in low nibble */
ep21->smbios_bcd_revision = ((ep30->smbios_major_version & 0xF) << 4) |
(ep30->smbios_minor_version & 0xF);
/* Copy structure table after entry point */
void *st_dest = (uint8_t *)smbios_buffer + SMBIOS_21_ENTRY_POINT_LENGTH;
memcpy(st_dest, (void *)(uintptr_t)st_addr, stats.table_length);
ep21->structure_table_address = (uint32_t)(uintptr_t)st_dest;
/* Calculate checksums */
ep21->checksum = 0;
ep21->intermediate_checksum = 0;
ep21->intermediate_checksum = -smbios_checksum((uint8_t *)ep21 + 0x10,
SMBIOS_21_ENTRY_POINT_LENGTH - 0x10);
ep21->checksum = -smbios_checksum(ep21, SMBIOS_21_ENTRY_POINT_LENGTH);
printf(" Synthesis complete: SMBIOS %u.%u, %u structures, table at %x\n",
ep21->smbios_major_version, ep21->smbios_minor_version,
ep21->number_of_structures, ep21->structure_table_address);
return ep21;
}
#ifdef __x86_64__
/*
* Relocate SMBIOS 2.x entry point and structure table to below 4GB.
* Only needed on 64-bit systems where SMBIOS data may be above 4GB.
* Returns the new entry point address, or NULL on failure.
*/
static struct smbios_21_entry_point *relocate_smbios_21(
struct smbios_21_entry_point *ep,
uint64_t st_addr,
uint32_t st_size)
{
size_t ep_size = ep->length;
size_t total_size = ep_size + st_size;
/* Allocate below 4GB */
EFI_PHYSICAL_ADDRESS max_addr = 0xFFFFFFFF;
EFI_STATUS status = gBS->AllocatePages(
AllocateMaxAddress,
EfiRuntimeServicesData,
(total_size + EFI_PAGE_SIZE - 1) / EFI_PAGE_SIZE,
&max_addr
);
if (status != EFI_SUCCESS) {
printf(" Failed to allocate memory for SMBIOS relocation\n");
return NULL;
}
smbios_buffer = (void *)(uintptr_t)max_addr;
printf(" Relocating SMBIOS to %p\n", smbios_buffer);
/* Copy entry point */
struct smbios_21_entry_point *new_ep = smbios_buffer;
memcpy(new_ep, ep, ep_size);
/* Copy structure table right after entry point */
void *new_st = (uint8_t *)smbios_buffer + ep_size;
memcpy(new_st, (void *)(uintptr_t)st_addr, st_size);
/* Update structure table address in the new entry point */
new_ep->structure_table_address = (uint32_t)(uintptr_t)new_st;
/* Recalculate checksums */
new_ep->checksum = 0;
new_ep->intermediate_checksum = 0;
new_ep->intermediate_checksum = -smbios_checksum((uint8_t *)new_ep + 0x10, ep_size - 0x10);
new_ep->checksum = -smbios_checksum(new_ep, ep_size);
printf(" Relocation complete, new structure table at %x\n",
new_ep->structure_table_address);
return new_ep;
}
#endif /* __x86_64__ */
int set_smbios_table()
{
EFI_GUID smbiosGuid = SMBIOS_TABLE_GUID;
EFI_GUID smbios3Guid = SMBIOS3_TABLE_GUID;
struct smbios_21_entry_point *result_ep = NULL;
/* First, try to find SMBIOS 2.x table (preferred for legacy compatibility) */
for (size_t i = 0; i < gST->NumberOfTableEntries; i++) {
EFI_CONFIGURATION_TABLE *table = gST->ConfigurationTable + i;
if (!efi_guidcmp(table->VendorGuid, smbiosGuid)) {
struct smbios_21_entry_point *ep = table->VendorTable;
printf("Found SMBIOS 2.x entry point at %p\n", (void *)ep);
/* Validate signature */
if (ep->signature != SMBIOS_21_SIGNATURE) {
printf(" Invalid signature, skipping\n");
continue;
}
/* Validate checksums */
if (smbios_checksum(ep, 0x10) != 0) {
printf(" Invalid entry point checksum, skipping\n");
continue;
}
if (memcmp(ep->intermediate_anchor_string, "_DMI_", 5) != 0) {
printf(" Invalid DMI anchor, skipping\n");
continue;
}
if (smbios_checksum((uint8_t *)ep + 0x10, ep->length - 0x10) != 0) {
printf(" Invalid intermediate checksum, skipping\n");
continue;
}
printf(" Version: %u.%u, structure table at %x, length %u\n",
ep->smbios_major_version, ep->smbios_minor_version,
ep->structure_table_address, ep->structure_table_length);
#ifdef __x86_64__
/* Check if entry point or structure table is above 4GB */
uint64_t ep_addr = (uint64_t)(uintptr_t)ep;
uint64_t st_addr = ep->structure_table_address;
if (ep_addr >= 0x100000000ULL || st_addr >= 0x100000000ULL) {
printf(" Entry point or structure table above 4GB, relocation needed\n");
result_ep = relocate_smbios_21(ep, st_addr, ep->structure_table_length);
break;
}
#endif
result_ep = ep;
break;
}
}
/*
* If SMBIOS 2.x not found/usable, try SMBIOS 3.0.
* We synthesize an SMBIOS 2.x entry point from the 3.0 data since
* SeaBIOS and legacy operating systems only understand 2.x format.
*/
if (!result_ep) {
for (size_t i = 0; i < gST->NumberOfTableEntries; i++) {
EFI_CONFIGURATION_TABLE *table = gST->ConfigurationTable + i;
if (!efi_guidcmp(table->VendorGuid, smbios3Guid)) {
struct smbios_30_entry_point *ep = table->VendorTable;
printf("Found SMBIOS 3.0 entry point at %p\n", (void *)ep);
/* Validate signature */
if (memcmp(ep->signature, "_SM3_", 5) != 0) {
printf(" Invalid signature, skipping\n");
continue;
}
/* Validate checksum */
if (smbios_checksum(ep, ep->length) != 0) {
printf(" Invalid checksum, skipping\n");
continue;
}
printf(" Version: %u.%u, structure table at %lx, max size %u\n",
ep->smbios_major_version, ep->smbios_minor_version,
(unsigned long)ep->structure_table_address,
ep->structure_table_max_size);
/* Synthesize SMBIOS 2.x from 3.0 */
result_ep = synthesize_smbios_21_from_30(
ep, ep->structure_table_address, ep->structure_table_max_size);
break;
}
}
}
if (!result_ep) {
printf("No usable SMBIOS table found\n");
return -1;
}
priv.low_stub->boot_table.SmbiosTable = (uintptr_t)result_ep;
priv.low_stub->boot_table.SmbiosTableLength = result_ep->structure_table_length;
return 0;
}
void __attribute__((noreturn)) panic(const char *fmt, ...)
{
gConfig.verbose = true;
printf("\n*** PANIC: ");
va_list l;
va_start(l, fmt);
vprintf(fmt, l);
va_end(l);
printf("*** System halted.\n");
for (;;) { asm volatile("hlt"); }
}
EFI_STATUS efi_main(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *SystemTable)
{
EFI_PHYSICAL_ADDRESS HiPmm;
uintptr_t csm_bin_base;
EFI_STATUS Status;
EFI_IA32_REGISTER_SET Regs;
gST = SystemTable;
gBS = SystemTable->BootServices;
gRT = SystemTable->RuntimeServices;
calibrate_tsc();
csmwrap_video_early_init(&priv);
/* Initialise Flanterm (output gated on verbose; panics always show) */
if (priv.cb_fb.physical_address != 0) {
flanterm_ctx = flanterm_fb_init(
flanterm_uefi_malloc, flanterm_uefi_free,
(void *)(uintptr_t)priv.cb_fb.physical_address, priv.cb_fb.x_resolution, priv.cb_fb.y_resolution, priv.cb_fb.bytes_per_line,
priv.cb_fb.red_mask_size, priv.cb_fb.red_mask_pos, priv.cb_fb.green_mask_size, priv.cb_fb.green_mask_pos, priv.cb_fb.blue_mask_size, priv.cb_fb.blue_mask_pos,
NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, 0, 0, 0, 0, 0, 0,
FLANTERM_FB_ROTATE_0
);
}
gBS->SetWatchdogTimer(0, 0, 0, NULL);
/* Banner is always shown on screen */
gConfig.verbose = true;
printf("%s", banner);
gConfig.verbose = false;
for (EFI_PHYSICAL_ADDRESS i = 0; i < 0x100000; i += EFI_PAGE_SIZE) {
EFI_PHYSICAL_ADDRESS j = i;
if (gBS->AllocatePages(AllocateAddress, EfiLoaderData, 1, &j) != EFI_SUCCESS) {
if (i < 0xa0000) {
printf("warning: Early AllocatePages() failed for address 0x%llx\n", (unsigned long long)i);
}
}
}
if (gRT->GetTime(&gTimeAtBoot, NULL) != EFI_SUCCESS) {
panic("Failed to query current time\n");
}
EFI_GUID loaded_image_guid = EFI_LOADED_IMAGE_PROTOCOL_GUID;
EFI_LOADED_IMAGE_PROTOCOL *loaded_image = NULL;
if (gBS->HandleProtocol(ImageHandle, &loaded_image_guid, (void **)&loaded_image) != EFI_SUCCESS) {
loaded_image = NULL;
}
EFI_GUID sfs_protocol_guid = EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID;
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *sfs_protocol = NULL;
if (loaded_image == NULL || gBS->HandleProtocol(loaded_image->DeviceHandle, &sfs_protocol_guid, (void **)&sfs_protocol) != EFI_SUCCESS) {
sfs_protocol = NULL;
}
EFI_FILE_PROTOCOL *sfs_dir = NULL;
if (sfs_protocol == NULL || sfs_protocol->OpenVolume(sfs_protocol, &sfs_dir) != EFI_SUCCESS) {
sfs_dir = NULL;
}
/* Load configuration from csmwrap.ini next to our executable */
if (sfs_dir != NULL && loaded_image != NULL) {
config_load(sfs_dir, loaded_image->FilePath);
}
/* Load custom VGABIOS from config path if specified */
EFI_FILE_PROTOCOL *vgabios_file_handle = NULL;
if (sfs_dir != NULL && gConfig.vgabios_path[0] != 0) {
if (sfs_dir->Open(sfs_dir, &vgabios_file_handle, gConfig.vgabios_path, EFI_FILE_MODE_READ, 0) == EFI_SUCCESS) {
UINTN max_size = 256 * 1024;
if (gBS->AllocatePool(EfiLoaderData, max_size, &vbios_loc) != EFI_SUCCESS) {
vbios_loc = NULL;
} else {
if (vgabios_file_handle->Read(vgabios_file_handle, &max_size, vbios_loc) == EFI_SUCCESS) {
printf("Loaded custom VBIOS from config. Using it as our VBIOS!\n");
vbios_size = max_size;
} else {
gBS->FreePool(vbios_loc);
vbios_loc = NULL;
}
}
vgabios_file_handle->Close(vgabios_file_handle);
} else {
printf("warning: could not open configured vgabios path\n");
}
}
if (sfs_dir != NULL) {
sfs_dir->Close(sfs_dir);
}
if (unlock_bios_region()) {
panic("Unable to unlock BIOS region\n");
}
printf("Unlock!\n");
apply_intel_platform_workarounds();
csm_bin_base = (uintptr_t)BIOSROM_END - sizeof(Csm16_bin);
priv.csm_bin_base = csm_bin_base;
printf("csm_bin_base: 0x%lx\n", csm_bin_base);
if (csm_bin_base < VGABIOS_END) {
panic("Illegal csm_bin size\n");
}
priv.csm_efi_table = find_table(EFI_COMPATIBILITY16_TABLE_SIGNATURE, Csm16_bin, sizeof(Csm16_bin));
if (priv.csm_efi_table == NULL) {
panic("EFI_COMPATIBILITY16_TABLE not found\n");
}
/* Initialize ACPI first (needed for MADT parsing in bios_proxy_init) */
if (!acpi_init(&priv)) {
panic("ACPI initialization failed\n");
}
/* Calculate RSDP copy location for MADT patching */
void *rsdp_copy = priv.csm_bin + (priv.csm_efi_table->AcpiRsdPtrPointer - priv.csm_bin_base);
/* Initialize BIOS proxy (find mailbox and helper entry in CSM binary) */
if (bios_proxy_init(Csm16_bin, sizeof(Csm16_bin), rsdp_copy) != 0) {
panic("BIOS proxy initialization failed\n");
}
bool pci_initialized = pci_early_initialize();
if (!pci_initialized)
printf("pci_early_initialize failed, PCI BAR relocation will be skipped\n");
Status = csmwrap_video_init(&priv);
/* Enumerate non-VGA PCI option ROMs while boot services are available */
struct pci_oprom_list oprom_list;
oprom_enumerate(&priv, &oprom_list);
HiPmm = 0xffffffff;
if (gBS->AllocatePages(AllocateMaxAddress, EfiRuntimeServicesData, HIPMM_SIZE / EFI_PAGE_SIZE, &HiPmm) != EFI_SUCCESS) {
panic("Unable to alloc HiPmm\n");
}
priv.low_stub = (struct low_stub *)LOW_STUB_BASE;
memset((void*)LOW_STUB_BASE, 0, CONVEN_END - LOW_STUB_BASE);
set_smbios_table();
priv.low_stub->boot_table.AcpiTable = priv.csm_efi_table->AcpiRsdPtrPointer;
uintptr_t pmm_base = LegacyBiosInitializeThunkAndTable(LOW_STUB_BASE, sizeof(struct low_stub));
printf("Init Thunk pmm: %lx\n", (uintptr_t)pmm_base);
priv.low_stub->init_table.BiosLessThan1MB = 0; // SeaBIOS does not actually use this field.
priv.low_stub->init_table.ThunkStart = (uint32_t)(uintptr_t)priv.low_stub;
priv.low_stub->init_table.ThunkSizeInBytes = sizeof(struct low_stub);
priv.low_stub->init_table.LowPmmMemory = (uint32_t)pmm_base;
priv.low_stub->init_table.LowPmmMemorySizeInBytes = (uint32_t)CONVEN_END - (uint32_t)pmm_base;
priv.low_stub->init_table.HiPmmMemorySizeInBytes = HIPMM_SIZE;
priv.low_stub->init_table.HiPmmMemory = HiPmm;
priv.low_stub->vga_oprom_table.OpromSegment = EFI_SEGMENT(VGABIOS_START);
priv.low_stub->vga_oprom_table.PciBus = priv.vga_pci_bus;
priv.low_stub->vga_oprom_table.PciDeviceFunction = priv.vga_pci_devfn;
/* Build BBS table with boot device prioritized */
build_bbs_table(&priv, ImageHandle);
/* Build MP table from ACPI MADT (excludes helper core) */
mptable_init(&priv);
/* Build $PIR table from ACPI _PRT for legacy PCI BIOS callers */
pir_init(&priv);
printf("CALL16 %x:%x\n", priv.csm_efi_table->Compatibility16CallSegment,
priv.csm_efi_table->Compatibility16CallOffset);
/* WARNING: No EFI Video afterwards */
csmwrap_video_prepare_exitbs(&priv);
/* WARNING: No EFI runtime service afterwards */
UINTN efi_mmap_size = 0, efi_desc_size = 0, efi_mmap_key = 0;
UINT32 efi_desc_ver = 0;
EFI_MEMORY_DESCRIPTOR *efi_mmap = NULL;
UINTN efi_mmap_alloc = 0;
for (size_t retries = 0; ; retries++) {
if (retries == 128) {
panic("Failed to exit boot services\n");
}
efi_mmap_size = efi_mmap_alloc;
Status = gBS->GetMemoryMap(&efi_mmap_size, efi_mmap, &efi_mmap_key,
&efi_desc_size, &efi_desc_ver);
if (Status == EFI_BUFFER_TOO_SMALL) {
/* Map grew (or first call) - reallocate with slack for the
* descriptors that AllocatePool itself may add. */
if (efi_mmap != NULL) {
gBS->FreePool(efi_mmap);
}
efi_mmap_alloc = efi_mmap_size + 4096;
if (gBS->AllocatePool(EfiLoaderData, efi_mmap_alloc,
(void **)&efi_mmap) != EFI_SUCCESS) {
panic("AllocatePool() for EFI memory map failed\n");
}
continue;
}
if (Status != EFI_SUCCESS) {
panic("GetMemoryMap() failed\n");
}
Status = gBS->ExitBootServices(ImageHandle, efi_mmap_key);
if (Status == EFI_SUCCESS) {
break;
}
/* Key invalidated by a memory-map change - retry. */
}
/* Boot services protocols (including serial I/O) are no longer usable */
gBootServicesExited = true;
/* Disable external interrupts */
asm volatile ("cli");
/* Disable IOMMUs before PCI relocation and CSM init */
if (gConfig.iommu_disable)
iommu_disable();
/* Prepare APIC for legacy BIOS operation (disable or configure for ExtINT) */
apic_prepare_for_legacy();
pci_late_initialize();
build_coreboot_table(&priv);
build_e820_map(&priv, efi_mmap, efi_mmap_size, efi_desc_size);
uintptr_t e820_low = (uintptr_t)&priv.low_stub->e820_map;
priv.csm_efi_table->E820Pointer = e820_low;
priv.csm_efi_table->E820Length = sizeof(EFI_E820_ENTRY64) * priv.low_stub->e820_entries;
/* Hand SeaBIOS the exact extra root bus numbers we discovered via
* uACPI. Setting the pointer (even with count==0) signals authoritative
* info; if discovery failed we leave the fields zero and SeaBIOS uses
* its pre-extension default. */
if (pci_initialized) {
size_t extra_root_count = pci_get_extra_root_buses(
priv.low_stub->extra_pci_roots, EXTRA_PCI_ROOTS_MAX);
priv.low_stub->extra_pci_roots_count = (uint8_t)extra_root_count;
priv.csm_efi_table->ExtraPciRootListPointer =
(uint32_t)(uintptr_t)&priv.low_stub->extra_pci_roots[0];
priv.csm_efi_table->ExtraPciRootListCount = (uint8_t)extra_root_count;
printf("Reporting %zu extra PCI root bus(es) to SeaBIOS:", extra_root_count);
for (size_t i = 0; i < extra_root_count; i++)
printf(" %u", priv.low_stub->extra_pci_roots[i]);
printf("\n");
}
/* Disable 8259 PIC */
outb(0x21, 0xff);
outb(0xa1, 0xff);
outb(0x43, 0x36);
/* Program PIT to default */
outb(0x40, 0x00);
outb(0x40, 0x00);
/* Copy ROM to location, as late as possible */
memcpy((void*)csm_bin_base, Csm16_bin, sizeof(Csm16_bin));
if (vbios_loc != NULL) {
uintptr_t max_vbios_size = csm_bin_base - VGABIOS_START;
if (vbios_size > max_vbios_size) {
panic("VBIOS too large (%u bytes, max %u)\n",
(unsigned)vbios_size, (unsigned)max_vbios_size);
}
memcpy((void*)VGABIOS_START, vbios_loc, vbios_size
gitextract_bu0ihczz/
├── .github/
│ ├── dependabot.yml
│ └── workflows/
│ └── build.yml
├── .gitignore
├── .gitmodules
├── GNUmakefile
├── LICENSE
├── README.md
├── seabios-config
└── src/
├── acpi.c
├── ap_trampoline.asm
├── apic.c
├── apic.h
├── arch/
│ ├── ia32/
│ │ └── Thunk16.asm
│ └── x86_64/
│ └── Thunk16.asm
├── bios_proxy.c
├── bios_proxy.h
├── bootdev.c
├── bootdev.h
├── config.c
├── config.h
├── coreboot.c
├── csmwrap.c
├── csmwrap.h
├── e820.c
├── edk2/
│ ├── Acpi.h
│ ├── Acpi10.h
│ ├── Acpi20.h
│ ├── Acpi30.h
│ ├── Acpi40.h
│ ├── Acpi50.h
│ ├── Acpi51.h
│ ├── Acpi60.h
│ ├── Acpi61.h
│ ├── Acpi62.h
│ ├── Acpi63.h
│ ├── Acpi64.h
│ ├── Acpi65.h
│ ├── AcpiAml.h
│ ├── Coreboot.h
│ ├── E820.h
│ ├── Edk2Compat.h
│ ├── LegacyBios.h
│ ├── LegacyRegion2.h
│ ├── Pci.h
│ ├── Pci22.h
│ ├── Pci23.h
│ ├── Pci30.h
│ ├── PciCodeId.h
│ ├── PciExpress21.h
│ ├── PciExpress30.h
│ ├── PciExpress31.h
│ ├── PciExpress40.h
│ ├── PciExpress50.h
│ └── PciExpress60.h
├── intel_workarounds.c
├── io.h
├── iommu.c
├── iommu.h
├── libc.c
├── libc.h
├── mptable.c
├── mptable.h
├── oprom.c
├── oprom.h
├── pci.c
├── pci.h
├── pir.c
├── pir.h
├── printf.c
├── printf.h
├── qsort.c
├── qsort.h
├── time.c
├── time.h
├── uacpi_config.h
├── unlock_region.c
├── video.c
├── video.h
├── x86thunk.c
└── x86thunk.h
SYMBOL INDEX (1703 symbols across 57 files)
FILE: src/acpi.c
function uacpi_kernel_log (line 30) | void uacpi_kernel_log(enum uacpi_log_level lvl, const char *text) {
function uacpi_kernel_unmap (line 38) | void uacpi_kernel_unmap(EFI_UNUSED void *ptr, EFI_UNUSED uacpi_size len) {
function uacpi_status (line 41) | uacpi_status uacpi_kernel_pci_device_open(uacpi_pci_address address, uac...
function uacpi_kernel_pci_device_close (line 57) | void uacpi_kernel_pci_device_close(uacpi_handle handle) {
function uacpi_status (line 61) | uacpi_status uacpi_kernel_pci_read8(uacpi_handle device, uacpi_size offs...
function uacpi_status (line 66) | uacpi_status uacpi_kernel_pci_read16(uacpi_handle device, uacpi_size off...
function uacpi_status (line 71) | uacpi_status uacpi_kernel_pci_read32(uacpi_handle device, uacpi_size off...
function uacpi_status (line 76) | uacpi_status uacpi_kernel_pci_write8(uacpi_handle device, uacpi_size off...
function uacpi_status (line 81) | uacpi_status uacpi_kernel_pci_write16(uacpi_handle device, uacpi_size of...
function uacpi_status (line 86) | uacpi_status uacpi_kernel_pci_write32(uacpi_handle device, uacpi_size of...
type mapped_io (line 91) | struct mapped_io {
function uacpi_status (line 96) | uacpi_status uacpi_kernel_io_map(uacpi_io_addr base, uacpi_size len, uac...
function uacpi_kernel_io_unmap (line 110) | void uacpi_kernel_io_unmap(uacpi_handle handle) {
function uacpi_status (line 114) | uacpi_status uacpi_kernel_io_read8(uacpi_handle handle, uacpi_size offse...
function uacpi_status (line 124) | uacpi_status uacpi_kernel_io_read16(uacpi_handle handle, uacpi_size offs...
function uacpi_status (line 134) | uacpi_status uacpi_kernel_io_read32(uacpi_handle handle, uacpi_size offs...
function uacpi_status (line 144) | uacpi_status uacpi_kernel_io_write8(uacpi_handle handle, uacpi_size offs...
function uacpi_status (line 154) | uacpi_status uacpi_kernel_io_write16(uacpi_handle handle, uacpi_size off...
function uacpi_status (line 164) | uacpi_status uacpi_kernel_io_write32(uacpi_handle handle, uacpi_size off...
function uacpi_interrupt_state (line 174) | uacpi_interrupt_state uacpi_kernel_disable_interrupts(void) {
function uacpi_kernel_restore_interrupts (line 180) | void uacpi_kernel_restore_interrupts(uacpi_interrupt_state state) {
function uacpi_handle (line 184) | uacpi_handle uacpi_kernel_create_spinlock(void) {
function uacpi_kernel_free_spinlock (line 193) | void uacpi_kernel_free_spinlock(uacpi_handle handle) {
function uacpi_cpu_flags (line 197) | uacpi_cpu_flags uacpi_kernel_lock_spinlock(uacpi_handle handle) {
function uacpi_kernel_unlock_spinlock (line 202) | void uacpi_kernel_unlock_spinlock(uacpi_handle handle, uacpi_cpu_flags c...
function uacpi_handle (line 207) | uacpi_handle uacpi_kernel_create_event(void) {
function uacpi_kernel_free_event (line 216) | void uacpi_kernel_free_event(uacpi_handle handle) {
function uacpi_bool (line 220) | uacpi_bool uacpi_kernel_wait_for_event(uacpi_handle handle, uacpi_u16 ti...
function uacpi_kernel_signal_event (line 226) | void uacpi_kernel_signal_event(uacpi_handle handle) {
function uacpi_kernel_reset_event (line 230) | void uacpi_kernel_reset_event(uacpi_handle handle) {
function uacpi_u64 (line 234) | uacpi_u64 uacpi_kernel_get_nanoseconds_since_boot(void) {
function uacpi_kernel_stall (line 238) | void uacpi_kernel_stall(uacpi_u8 usec) {
function uacpi_kernel_sleep (line 242) | void uacpi_kernel_sleep(uacpi_u64 msec) {
function uacpi_thread_id (line 246) | uacpi_thread_id uacpi_kernel_get_thread_id(void) {
function uacpi_status (line 250) | uacpi_status uacpi_kernel_handle_firmware_request(uacpi_firmware_request...
function uacpi_status (line 255) | uacpi_status uacpi_kernel_install_interrupt_handler(
function uacpi_status (line 265) | uacpi_status uacpi_kernel_uninstall_interrupt_handler(uacpi_interrupt_ha...
function uacpi_status (line 271) | uacpi_status uacpi_kernel_schedule_work(uacpi_work_type work_type, uacpi...
function uacpi_status (line 278) | uacpi_status uacpi_kernel_wait_for_work_completion(void) {
function uacpi_kernel_free (line 291) | void uacpi_kernel_free(void *mem) {
function uacpi_handle (line 297) | uacpi_handle uacpi_kernel_create_mutex(void) {
function uacpi_kernel_free_mutex (line 306) | void uacpi_kernel_free_mutex(uacpi_handle handle) {
function uacpi_status (line 310) | uacpi_status uacpi_kernel_acquire_mutex(uacpi_handle handle, uacpi_u16 t...
function uacpi_kernel_release_mutex (line 316) | void uacpi_kernel_release_mutex(uacpi_handle handle) {
function uacpi_status (line 320) | uacpi_status uacpi_kernel_get_rsdp(uacpi_phys_addr *rsdp) {
function acpi_init (line 331) | bool acpi_init(struct csmwrap_priv *priv) {
function acpi_namespace_init (line 389) | bool acpi_namespace_init(void) {
FILE: src/apic.c
function x2apic_is_locked (line 84) | static bool x2apic_is_locked(void)
function lvt_should_mask (line 110) | static bool lvt_should_mask(uint32_t lvt)
function load_nmi_madt_info (line 127) | static void load_nmi_madt_info(void)
function lint_lvt_value (line 163) | static uint32_t lint_lvt_value(int pin)
function x2apic_configure_for_legacy (line 185) | static void x2apic_configure_for_legacy(void)
function xapic_configure_for_legacy (line 257) | static void xapic_configure_for_legacy(uintptr_t apic_base)
function apic_prepare_for_legacy (line 338) | void apic_prepare_for_legacy(void)
FILE: src/bios_proxy.c
type bios_proxy_mailbox (line 27) | struct bios_proxy_mailbox {
function get_lapic_base (line 60) | static uintptr_t get_lapic_base(void)
type bios_proxy_mailbox (line 69) | struct bios_proxy_mailbox
function build_reset_page_tables (line 88) | static int build_reset_page_tables(void)
function is_x2apic_mode (line 130) | static int is_x2apic_mode(void)
function find_proxy_mailbox (line 139) | static uintptr_t find_proxy_mailbox(void *csm_base, size_t csm_size)
function find_helper_16_entry (line 160) | static uint32_t find_helper_16_entry(void *csm_base, size_t csm_size, ui...
function create_ap_trampoline (line 187) | static void create_ap_trampoline(uint32_t target16_addr, uint32_t mailbo...
function wait_icr_idle_xapic (line 209) | static void wait_icr_idle_xapic(uintptr_t lapic_base)
function start_ap_xapic (line 222) | static void start_ap_xapic(uint32_t apic_id)
function start_ap_x2apic (line 248) | static void start_ap_x2apic(uint32_t apic_id)
function start_ap (line 257) | static void start_ap(uint32_t apic_id)
function get_bsp_apic_id (line 266) | static uint32_t get_bsp_apic_id(void)
function madt_apic_id_is_valid_ap (line 280) | static bool madt_apic_id_is_valid_ap(uint32_t apic_id, uint32_t bsp_id)
function find_available_ap (line 328) | static int find_available_ap(void)
function acpi_checksum (line 384) | static uint8_t acpi_checksum(void *data, size_t len)
function acpi_fix_checksum (line 394) | static void acpi_fix_checksum(struct acpi_sdt_hdr *hdr)
function cpu_visible_to_os (line 412) | static bool cpu_visible_to_os(uint32_t apic_id, uint32_t bsp_id,
type acpi_madt (line 427) | struct acpi_madt
type uacpi_table (line 429) | struct uacpi_table
type acpi_madt (line 434) | struct acpi_madt
type acpi_madt (line 434) | struct acpi_madt
type acpi_madt_lapic (line 453) | struct acpi_madt_lapic
type acpi_madt_x2apic (line 456) | struct acpi_madt_x2apic
type acpi_madt (line 492) | struct acpi_madt
type acpi_madt (line 492) | struct acpi_madt
type acpi_madt (line 495) | struct acpi_madt
type acpi_madt_lapic (line 508) | struct acpi_madt_lapic
type acpi_madt_x2apic (line 512) | struct acpi_madt_x2apic
type acpi_rsdt (line 538) | struct acpi_rsdt
type acpi_rsdp (line 538) | struct acpi_rsdp
type acpi_rsdt (line 544) | struct acpi_rsdt
type acpi_rsdt (line 544) | struct acpi_rsdt
type acpi_sdt_hdr (line 546) | struct acpi_sdt_hdr
type acpi_rsdt (line 561) | struct acpi_rsdt
type acpi_rsdt (line 561) | struct acpi_rsdt
type acpi_sdt_hdr (line 566) | struct acpi_sdt_hdr
type acpi_sdt_hdr (line 566) | struct acpi_sdt_hdr
type acpi_xsdt (line 580) | struct acpi_xsdt
type acpi_rsdp (line 580) | struct acpi_rsdp
type acpi_xsdt (line 586) | struct acpi_xsdt
type acpi_xsdt (line 586) | struct acpi_xsdt
type acpi_sdt_hdr (line 588) | struct acpi_sdt_hdr
type acpi_xsdt (line 603) | struct acpi_xsdt
type acpi_xsdt (line 603) | struct acpi_xsdt
type acpi_sdt_hdr (line 608) | struct acpi_sdt_hdr
type acpi_sdt_hdr (line 608) | struct acpi_sdt_hdr
function patch_acpi_hide_helper (line 623) | static int patch_acpi_hide_helper(void *rsdp_copy, int helper_apic_id)
function bios_proxy_init (line 682) | int bios_proxy_init(void *csm_base, size_t csm_size, void *rsdp_copy)
function bios_proxy_start_helper (line 737) | int bios_proxy_start_helper(uintptr_t csm_final_base)
function bios_proxy_get_helper_apic_id (line 791) | int bios_proxy_get_helper_apic_id(void)
FILE: src/bootdev.c
function parse_device_path (line 16) | static bool parse_device_path(EFI_DEVICE_PATH_PROTOCOL *device_path,
function get_pci_location (line 91) | static bool get_pci_location(EFI_HANDLE device_handle, struct boot_devic...
function devices_match (line 155) | static bool devices_match(const struct boot_device_info *a,
function add_bbs_entry (line 188) | static void add_bbs_entry(struct low_stub *low_stub,
function enumerate_block_devices (line 250) | static int enumerate_block_devices(struct low_stub *low_stub,
function build_bbs_table (line 302) | int build_bbs_table(struct csmwrap_priv *priv, EFI_HANDLE image_handle)
FILE: src/bootdev.h
type csmwrap_priv (line 7) | struct csmwrap_priv
type boot_device_info (line 18) | struct boot_device_info {
type csmwrap_priv (line 42) | struct csmwrap_priv
FILE: src/config.c
type csmwrap_config (line 10) | struct csmwrap_config
function config_cpu_in_filter (line 28) | bool config_cpu_in_filter(uint32_t apic_id)
function char_eq_nocase (line 47) | static bool char_eq_nocase(char a, char b)
function streq_nocase (line 54) | static bool streq_nocase(const char *a, const char *b)
function parse_bool (line 65) | static bool parse_bool(const char *val, bool *out)
function parse_uint32 (line 78) | static bool parse_uint32(const char *val, uint32_t *out)
function parse_hex_byte (line 111) | static bool parse_hex_byte(const char *s, size_t len, uint32_t *out)
function parse_apic_id_token (line 141) | static bool parse_apic_id_token(char *tok, uint32_t *lo, uint32_t *hi)
function parse_apic_id_list (line 198) | static bool parse_apic_id_list(const char *val, uint32_t *out,
function parse_pci_address (line 258) | static bool parse_pci_address(const char *val, uint8_t *bus, uint8_t *de...
function trim_trailing (line 299) | static size_t trim_trailing(const char *start, size_t len)
function config_apply (line 311) | static void config_apply(const char *key, const char *val)
function config_parse (line 455) | static void config_parse(char *buf, size_t len)
function config_build_path (line 518) | static bool config_build_path(EFI_DEVICE_PATH_PROTOCOL *file_path,
function config_load (line 578) | void config_load(EFI_FILE_PROTOCOL *root_dir, EFI_DEVICE_PATH_PROTOCOL *...
FILE: src/config.h
type csmwrap_cpu_filter_mode (line 11) | enum csmwrap_cpu_filter_mode {
type csmwrap_config (line 17) | struct csmwrap_config {
type csmwrap_config (line 43) | struct csmwrap_config
FILE: src/coreboot.c
function UINT16 (line 4) | static UINT16
function build_coreboot_table (line 34) | int build_coreboot_table(struct csmwrap_priv *priv)
FILE: src/csmwrap.c
type csmwrap_priv (line 64) | struct csmwrap_priv
function flanterm_uefi_free (line 81) | static void flanterm_uefi_free(void *ptr, size_t size)
type smbios_21_entry_point (line 114) | struct smbios_21_entry_point {
type smbios_30_entry_point (line 131) | struct smbios_30_entry_point {
type smbios_structure_header (line 145) | struct smbios_structure_header {
function smbios_checksum (line 152) | static uint8_t smbios_checksum(const void *data, size_t len)
type smbios_table_stats (line 166) | struct smbios_table_stats {
function smbios_walk_table (line 182) | static bool smbios_walk_table(const void *table, uint32_t max_size, stru...
type smbios_21_entry_point (line 261) | struct smbios_21_entry_point
type smbios_30_entry_point (line 262) | struct smbios_30_entry_point
type smbios_table_stats (line 267) | struct smbios_table_stats
type smbios_21_entry_point (line 311) | struct smbios_21_entry_point
type smbios_21_entry_point (line 353) | struct smbios_21_entry_point
type smbios_21_entry_point (line 354) | struct smbios_21_entry_point
type smbios_21_entry_point (line 379) | struct smbios_21_entry_point
function set_smbios_table (line 402) | int set_smbios_table()
function panic (line 504) | void __attribute__((noreturn)) panic(const char *fmt, ...)
function EFI_STATUS (line 516) | EFI_STATUS efi_main(EFI_HANDLE ImageHandle, EFI_SYSTEM_TABLE *SystemTable)
FILE: src/csmwrap.h
type csmwrap_video_type (line 20) | enum csmwrap_video_type {
type csmwrap_priv (line 26) | struct csmwrap_priv {
type csmwrap_priv (line 45) | struct csmwrap_priv
type csmwrap_priv (line 48) | struct csmwrap_priv
type csmwrap_priv (line 49) | struct csmwrap_priv
type csmwrap_priv (line 51) | struct csmwrap_priv
function efi_guidcmp (line 56) | static inline int
type low_stub (line 69) | struct low_stub {
FILE: src/e820.c
function remove_e820 (line 23) | static void
function insert_e820 (line 40) | static void
function dump_map (line 63) | static void
function dump_efi_memory_map (line 105) | static void
function e820_add (line 131) | void e820_add(struct csmwrap_priv *priv, uint64_t start,
function e820_remove (line 192) | void
function convert_memory_type (line 202) | static uint32_t convert_memory_type(EFI_MEMORY_TYPE type)
function cmos_write (line 227) | static inline void cmos_write(uint8_t reg, uint8_t val)
function e820_update_cmos (line 248) | static void
function build_e820_map (line 341) | int build_e820_map(struct csmwrap_priv *priv, EFI_MEMORY_DESCRIPTOR *mem...
FILE: src/edk2/Acpi10.h
type EFI_ACPI_COMMON_HEADER (line 19) | typedef struct {
type EFI_ACPI_DESCRIPTION_HEADER (line 28) | typedef struct {
type PACKED (line 117) | typedef PACKED struct
type PACKED (line 130) | typedef PACKED union
function PACKED (line 132) | PACKED struct {
type PACKED (line 139) | typedef PACKED struct
function PACKED (line 140) | PACKED union {
type PACKED (line 153) | typedef PACKED struct
type PACKED (line 161) | typedef PACKED struct
type PACKED (line 170) | typedef PACKED struct
type PACKED (line 179) | typedef PACKED struct
type PACKED (line 191) | typedef PACKED struct
type PACKED (line 200) | typedef PACKED struct
type PACKED (line 212) | typedef PACKED struct
type PACKED (line 224) | typedef PACKED struct
type PACKED (line 234) | typedef PACKED struct
type PACKED (line 249) | typedef PACKED struct
type PACKED (line 264) | typedef PACKED struct
type PACKED (line 279) | typedef PACKED struct
type EFI_ACPI_END_TAG_DESCRIPTOR (line 291) | typedef struct {
type EFI_ACPI_1_0_ROOT_SYSTEM_DESCRIPTION_POINTER (line 402) | typedef struct {
type EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE (line 424) | typedef struct {
type EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE (line 493) | typedef struct {
type EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER (line 513) | typedef struct {
type EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE (line 548) | typedef struct {
type EFI_ACPI_1_0_IO_APIC_STRUCTURE (line 564) | typedef struct {
type EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE (line 576) | typedef struct {
type EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE (line 588) | typedef struct {
type EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE (line 598) | typedef struct {
type EFI_ACPI_1_0_SMART_BATTERY_DESCRIPTION_TABLE (line 609) | typedef struct {
FILE: src/edk2/Acpi20.h
type PACKED (line 28) | typedef PACKED struct
type EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE (line 47) | typedef struct {
type EFI_ACPI_2_0_ROOT_SYSTEM_DESCRIPTION_POINTER (line 72) | typedef struct {
type EFI_ACPI_2_0_COMMON_HEADER (line 93) | typedef struct {
type EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE (line 123) | typedef struct {
type EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE (line 223) | typedef struct {
type EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER (line 250) | typedef struct {
type EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE (line 289) | typedef struct {
type EFI_ACPI_2_0_IO_APIC_STRUCTURE (line 305) | typedef struct {
type EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE (line 317) | typedef struct {
type EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE (line 329) | typedef struct {
type EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE (line 339) | typedef struct {
type EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE (line 350) | typedef struct {
type EFI_ACPI_2_0_IO_SAPIC_STRUCTURE (line 360) | typedef struct {
type EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE (line 372) | typedef struct {
type EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE (line 385) | typedef struct {
type EFI_ACPI_2_0_SMART_BATTERY_DESCRIPTION_TABLE (line 400) | typedef struct {
type EFI_ACPI_2_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE (line 417) | typedef struct {
FILE: src/edk2/Acpi30.h
type PACKED (line 53) | typedef PACKED struct
type EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE (line 88) | typedef struct {
type EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER (line 122) | typedef struct {
type EFI_ACPI_3_0_COMMON_HEADER (line 143) | typedef struct {
type EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE (line 173) | typedef struct {
type EFI_ACPI_3_0_FIRMWARE_ACPI_CONTROL_STRUCTURE (line 283) | typedef struct {
type EFI_ACPI_3_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER (line 320) | typedef struct {
type EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_STRUCTURE (line 359) | typedef struct {
type EFI_ACPI_3_0_IO_APIC_STRUCTURE (line 375) | typedef struct {
type EFI_ACPI_3_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE (line 387) | typedef struct {
type EFI_ACPI_3_0_PLATFORM_INTERRUPT_APIC_STRUCTURE (line 399) | typedef struct {
type EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE (line 423) | typedef struct {
type EFI_ACPI_3_0_LOCAL_APIC_NMI_STRUCTURE (line 433) | typedef struct {
type EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE (line 444) | typedef struct {
type EFI_ACPI_3_0_IO_SAPIC_STRUCTURE (line 454) | typedef struct {
type EFI_ACPI_3_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE (line 467) | typedef struct {
type EFI_ACPI_3_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE (line 481) | typedef struct {
type EFI_ACPI_3_0_SMART_BATTERY_DESCRIPTION_TABLE (line 502) | typedef struct {
type EFI_ACPI_3_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE (line 519) | typedef struct {
type EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER (line 536) | typedef struct {
type EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE (line 558) | typedef struct {
type EFI_ACPI_3_0_MEMORY_AFFINITY_STRUCTURE (line 577) | typedef struct {
type EFI_ACPI_3_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER (line 602) | typedef struct {
FILE: src/edk2/Acpi40.h
type EFI_ACPI_4_0_GENERIC_ADDRESS_STRUCTURE (line 37) | typedef struct {
type EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER (line 71) | typedef struct {
type EFI_ACPI_4_0_COMMON_HEADER (line 92) | typedef struct {
type EFI_ACPI_4_0_FIXED_ACPI_DESCRIPTION_TABLE (line 122) | typedef struct {
type EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE (line 232) | typedef struct {
type EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER (line 278) | typedef struct {
type EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_STRUCTURE (line 319) | typedef struct {
type EFI_ACPI_4_0_IO_APIC_STRUCTURE (line 335) | typedef struct {
type EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE (line 347) | typedef struct {
type EFI_ACPI_4_0_PLATFORM_INTERRUPT_APIC_STRUCTURE (line 359) | typedef struct {
type EFI_ACPI_4_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE (line 383) | typedef struct {
type EFI_ACPI_4_0_LOCAL_APIC_NMI_STRUCTURE (line 393) | typedef struct {
type EFI_ACPI_4_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE (line 404) | typedef struct {
type EFI_ACPI_4_0_IO_SAPIC_STRUCTURE (line 414) | typedef struct {
type EFI_ACPI_4_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE (line 427) | typedef struct {
type EFI_ACPI_4_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE (line 441) | typedef struct {
type EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE (line 462) | typedef struct {
type EFI_ACPI_4_0_LOCAL_X2APIC_NMI_STRUCTURE (line 474) | typedef struct {
type EFI_ACPI_4_0_SMART_BATTERY_DESCRIPTION_TABLE (line 486) | typedef struct {
type EFI_ACPI_4_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE (line 503) | typedef struct {
type EFI_ACPI_4_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER (line 520) | typedef struct {
type EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE (line 543) | typedef struct {
type EFI_ACPI_4_0_MEMORY_AFFINITY_STRUCTURE (line 562) | typedef struct {
type EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE (line 586) | typedef struct {
type EFI_ACPI_4_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER (line 601) | typedef struct {
type EFI_ACPI_4_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER (line 614) | typedef struct {
type EFI_ACPI_4_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE (line 632) | typedef struct {
type EFI_ACPI_4_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER (line 643) | typedef struct {
type EFI_ACPI_4_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE (line 659) | typedef struct {
type EFI_ACPI_4_0_BOOT_ERROR_RECORD_TABLE_HEADER (line 671) | typedef struct {
type EFI_ACPI_4_0_ERROR_BLOCK_STATUS (line 685) | typedef struct {
type EFI_ACPI_4_0_BOOT_ERROR_REGION_STRUCTURE (line 697) | typedef struct {
type EFI_ACPI_4_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE (line 717) | typedef struct {
type EFI_ACPI_4_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER (line 736) | typedef struct {
type EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE (line 766) | typedef struct {
type EFI_ACPI_4_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE (line 783) | typedef struct {
type EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE (line 814) | typedef struct {
type EFI_ACPI_4_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE (line 827) | typedef struct {
type EFI_ACPI_4_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE (line 842) | typedef struct {
type EFI_ACPI_4_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE (line 858) | typedef struct {
type EFI_ACPI_4_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE (line 870) | typedef struct {
type EFI_ACPI_4_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE (line 893) | typedef struct {
type EFI_ACPI_4_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE (line 915) | typedef struct {
type EFI_ACPI_4_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE (line 940) | typedef struct {
type EFI_ACPI_4_0_GENERIC_ERROR_STATUS_STRUCTURE (line 957) | typedef struct {
type EFI_ACPI_4_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER (line 968) | typedef struct {
type EFI_ACPI_4_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY (line 1040) | typedef struct {
type EFI_ACPI_4_0_ERROR_INJECTION_TABLE_HEADER (line 1053) | typedef struct {
type EFI_ACPI_4_0_EINJ_INJECTION_INSTRUCTION_ENTRY (line 1119) | typedef struct {
type EFI_ACPI_4_0_EINJ_TRIGGER_ACTION_TABLE (line 1132) | typedef struct {
FILE: src/edk2/Acpi50.h
type PACKED (line 52) | typedef PACKED struct
type PACKED (line 62) | typedef PACKED struct
type PACKED (line 84) | typedef PACKED struct
type PACKED (line 103) | typedef PACKED struct
type PACKED (line 119) | typedef PACKED struct
type PACKED (line 138) | typedef PACKED struct
type EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE (line 164) | typedef struct {
type EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER (line 199) | typedef struct {
type EFI_ACPI_5_0_COMMON_HEADER (line 220) | typedef struct {
type EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE (line 250) | typedef struct {
type EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE (line 366) | typedef struct {
type EFI_ACPI_5_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER (line 412) | typedef struct {
type EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_STRUCTURE (line 455) | typedef struct {
type EFI_ACPI_5_0_IO_APIC_STRUCTURE (line 471) | typedef struct {
type EFI_ACPI_5_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE (line 483) | typedef struct {
type EFI_ACPI_5_0_PLATFORM_INTERRUPT_APIC_STRUCTURE (line 495) | typedef struct {
type EFI_ACPI_5_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE (line 519) | typedef struct {
type EFI_ACPI_5_0_LOCAL_APIC_NMI_STRUCTURE (line 529) | typedef struct {
type EFI_ACPI_5_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE (line 540) | typedef struct {
type EFI_ACPI_5_0_IO_SAPIC_STRUCTURE (line 550) | typedef struct {
type EFI_ACPI_5_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE (line 563) | typedef struct {
type EFI_ACPI_5_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE (line 577) | typedef struct {
type EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE (line 598) | typedef struct {
type EFI_ACPI_5_0_LOCAL_X2APIC_NMI_STRUCTURE (line 610) | typedef struct {
type EFI_ACPI_5_0_GIC_STRUCTURE (line 622) | typedef struct {
type EFI_ACPI_5_0_GIC_DISTRIBUTOR_STRUCTURE (line 644) | typedef struct {
type EFI_ACPI_5_0_SMART_BATTERY_DESCRIPTION_TABLE (line 657) | typedef struct {
type EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE (line 674) | typedef struct {
type EFI_ACPI_5_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER (line 691) | typedef struct {
type EFI_ACPI_5_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE (line 714) | typedef struct {
type EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE (line 733) | typedef struct {
type EFI_ACPI_5_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE (line 757) | typedef struct {
type EFI_ACPI_5_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER (line 772) | typedef struct {
type EFI_ACPI_5_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER (line 785) | typedef struct {
type EFI_ACPI_5_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE (line 803) | typedef struct {
type EFI_ACPI_5_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER (line 814) | typedef struct {
type EFI_ACPI_5_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE (line 830) | typedef struct {
type EFI_ACPI_5_0_RAS_FEATURE_TABLE (line 842) | typedef struct {
type EFI_ACPI_5_0_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION (line 855) | typedef struct {
type EFI_ACPI_5_0_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE (line 880) | typedef struct {
type EFI_ACPI_5_0_MEMORY_POWER_STATUS_TABLE (line 901) | typedef struct {
type EFI_ACPI_5_0_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION (line 917) | typedef struct {
type EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE (line 945) | typedef struct {
type EFI_ACPI_5_0_MPST_MEMORY_POWER_STRUCTURE (line 950) | typedef struct {
type EFI_ACPI_5_0_MPST_MEMORY_POWER_NODE_TABLE (line 967) | typedef struct {
type EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE (line 975) | typedef struct {
type EFI_ACPI_5_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE (line 988) | typedef struct {
type EFI_ACPI_5_0_MEMORY_TOPOLOGY_TABLE (line 996) | typedef struct {
type EFI_ACPI_5_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 1009) | typedef struct {
type EFI_ACPI_5_0_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 1027) | typedef struct {
type EFI_ACPI_5_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 1037) | typedef struct {
type EFI_ACPI_5_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 1054) | typedef struct {
type EFI_ACPI_5_0_BOOT_GRAPHICS_RESOURCE_TABLE (line 1065) | typedef struct {
type EFI_ACPI_5_0_FPDT_PERFORMANCE_RECORD_HEADER (line 1159) | typedef struct {
type EFI_ACPI_5_0_FPDT_PERFORMANCE_TABLE_HEADER (line 1168) | typedef struct {
type EFI_ACPI_5_0_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD (line 1176) | typedef struct {
type EFI_ACPI_5_0_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD (line 1188) | typedef struct {
type EFI_ACPI_5_0_FPDT_FIRMWARE_BASIC_BOOT_RECORD (line 1200) | typedef struct {
type EFI_ACPI_5_0_FPDT_FIRMWARE_BASIC_BOOT_TABLE (line 1241) | typedef struct {
type EFI_ACPI_5_0_FPDT_FIRMWARE_S3_BOOT_TABLE (line 1256) | typedef struct {
type EFI_ACPI_5_0_FPDT_S3_RESUME_RECORD (line 1266) | typedef struct {
type EFI_ACPI_5_0_FPDT_S3_SUSPEND_RECORD (line 1288) | typedef struct {
type EFI_ACPI_5_0_FIRMWARE_PERFORMANCE_RECORD_TABLE (line 1306) | typedef struct {
type EFI_ACPI_5_0_GENERIC_TIMER_DESCRIPTION_TABLE (line 1313) | typedef struct {
type EFI_ACPI_5_0_BOOT_ERROR_RECORD_TABLE_HEADER (line 1347) | typedef struct {
type EFI_ACPI_5_0_ERROR_BLOCK_STATUS (line 1361) | typedef struct {
type EFI_ACPI_5_0_BOOT_ERROR_REGION_STRUCTURE (line 1373) | typedef struct {
type EFI_ACPI_5_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE (line 1393) | typedef struct {
type EFI_ACPI_5_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER (line 1412) | typedef struct {
type EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE (line 1442) | typedef struct {
type EFI_ACPI_5_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE (line 1459) | typedef struct {
type EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE (line 1490) | typedef struct {
type EFI_ACPI_5_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE (line 1503) | typedef struct {
type EFI_ACPI_5_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE (line 1518) | typedef struct {
type EFI_ACPI_5_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE (line 1534) | typedef struct {
type EFI_ACPI_5_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE (line 1546) | typedef struct {
type EFI_ACPI_5_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE (line 1569) | typedef struct {
type EFI_ACPI_5_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE (line 1591) | typedef struct {
type EFI_ACPI_5_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE (line 1616) | typedef struct {
type EFI_ACPI_5_0_GENERIC_ERROR_STATUS_STRUCTURE (line 1633) | typedef struct {
type EFI_ACPI_5_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER (line 1644) | typedef struct {
type EFI_ACPI_5_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY (line 1716) | typedef struct {
type EFI_ACPI_5_0_ERROR_INJECTION_TABLE_HEADER (line 1729) | typedef struct {
type EFI_ACPI_5_0_EINJ_INJECTION_INSTRUCTION_ENTRY (line 1795) | typedef struct {
type EFI_ACPI_5_0_EINJ_TRIGGER_ACTION_TABLE (line 1808) | typedef struct {
type EFI_ACPI_5_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER (line 1818) | typedef struct {
type EFI_ACPI_5_0_PCCT_SUBSPACE_HEADER (line 1842) | typedef struct {
type EFI_ACPI_5_0_PCCT_SUBSPACE_GENERIC (line 1850) | typedef struct {
type EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND (line 1868) | typedef struct {
type EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS (line 1874) | typedef struct {
type EFI_ACPI_5_0_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER (line 1883) | typedef struct {
FILE: src/edk2/Acpi51.h
type EFI_ACPI_5_1_GENERIC_ADDRESS_STRUCTURE (line 45) | typedef struct {
type EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER (line 80) | typedef struct {
type EFI_ACPI_5_1_COMMON_HEADER (line 101) | typedef struct {
type EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE (line 131) | typedef struct {
type EFI_ACPI_5_1_FIRMWARE_ACPI_CONTROL_STRUCTURE (line 256) | typedef struct {
type EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER (line 302) | typedef struct {
type EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_STRUCTURE (line 347) | typedef struct {
type EFI_ACPI_5_1_IO_APIC_STRUCTURE (line 363) | typedef struct {
type EFI_ACPI_5_1_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE (line 375) | typedef struct {
type EFI_ACPI_5_1_PLATFORM_INTERRUPT_APIC_STRUCTURE (line 387) | typedef struct {
type EFI_ACPI_5_1_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE (line 411) | typedef struct {
type EFI_ACPI_5_1_LOCAL_APIC_NMI_STRUCTURE (line 421) | typedef struct {
type EFI_ACPI_5_1_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE (line 432) | typedef struct {
type EFI_ACPI_5_1_IO_SAPIC_STRUCTURE (line 442) | typedef struct {
type EFI_ACPI_5_1_PROCESSOR_LOCAL_SAPIC_STRUCTURE (line 455) | typedef struct {
type EFI_ACPI_5_1_PLATFORM_INTERRUPT_SOURCES_STRUCTURE (line 469) | typedef struct {
type EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC_STRUCTURE (line 490) | typedef struct {
type EFI_ACPI_5_1_LOCAL_X2APIC_NMI_STRUCTURE (line 502) | typedef struct {
type EFI_ACPI_5_1_GIC_STRUCTURE (line 514) | typedef struct {
type EFI_ACPI_5_1_GIC_DISTRIBUTOR_STRUCTURE (line 542) | typedef struct {
type EFI_ACPI_5_1_GIC_MSI_FRAME_STRUCTURE (line 564) | typedef struct {
type EFI_ACPI_5_1_GICR_STRUCTURE (line 583) | typedef struct {
type EFI_ACPI_5_1_SMART_BATTERY_DESCRIPTION_TABLE (line 594) | typedef struct {
type EFI_ACPI_5_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE (line 611) | typedef struct {
type EFI_ACPI_5_1_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER (line 628) | typedef struct {
type EFI_ACPI_5_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE (line 652) | typedef struct {
type EFI_ACPI_5_1_MEMORY_AFFINITY_STRUCTURE (line 671) | typedef struct {
type EFI_ACPI_5_1_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE (line 695) | typedef struct {
type EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE (line 709) | typedef struct {
type EFI_ACPI_5_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER (line 727) | typedef struct {
type EFI_ACPI_5_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER (line 740) | typedef struct {
type EFI_ACPI_5_1_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE (line 758) | typedef struct {
type EFI_ACPI_5_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER (line 769) | typedef struct {
type EFI_ACPI_5_1_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE (line 785) | typedef struct {
type EFI_ACPI_5_1_RAS_FEATURE_TABLE (line 797) | typedef struct {
type EFI_ACPI_5_1_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION (line 810) | typedef struct {
type EFI_ACPI_5_1_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE (line 835) | typedef struct {
type EFI_ACPI_5_1_MEMORY_POWER_STATUS_TABLE (line 856) | typedef struct {
type EFI_ACPI_5_1_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION (line 872) | typedef struct {
type EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE (line 900) | typedef struct {
type EFI_ACPI_5_1_MPST_MEMORY_POWER_STRUCTURE (line 905) | typedef struct {
type EFI_ACPI_5_1_MPST_MEMORY_POWER_NODE_TABLE (line 922) | typedef struct {
type EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE (line 930) | typedef struct {
type EFI_ACPI_5_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE (line 943) | typedef struct {
type EFI_ACPI_5_1_MEMORY_TOPOLOGY_TABLE (line 951) | typedef struct {
type EFI_ACPI_5_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 964) | typedef struct {
type EFI_ACPI_5_1_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 982) | typedef struct {
type EFI_ACPI_5_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 992) | typedef struct {
type EFI_ACPI_5_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 1009) | typedef struct {
type EFI_ACPI_5_1_BOOT_GRAPHICS_RESOURCE_TABLE (line 1020) | typedef struct {
type EFI_ACPI_5_1_FPDT_PERFORMANCE_RECORD_HEADER (line 1112) | typedef struct {
type EFI_ACPI_5_1_FPDT_PERFORMANCE_TABLE_HEADER (line 1121) | typedef struct {
type EFI_ACPI_5_1_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD (line 1129) | typedef struct {
type EFI_ACPI_5_1_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD (line 1141) | typedef struct {
type EFI_ACPI_5_1_FPDT_FIRMWARE_BASIC_BOOT_RECORD (line 1153) | typedef struct {
type EFI_ACPI_5_1_FPDT_FIRMWARE_BASIC_BOOT_TABLE (line 1194) | typedef struct {
type EFI_ACPI_5_1_FPDT_FIRMWARE_S3_BOOT_TABLE (line 1209) | typedef struct {
type EFI_ACPI_5_1_FPDT_S3_RESUME_RECORD (line 1219) | typedef struct {
type EFI_ACPI_5_1_FPDT_S3_SUSPEND_RECORD (line 1241) | typedef struct {
type EFI_ACPI_5_1_FIRMWARE_PERFORMANCE_RECORD_TABLE (line 1259) | typedef struct {
type EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE (line 1266) | typedef struct {
type EFI_ACPI_5_1_GTDT_GT_BLOCK_STRUCTURE (line 1304) | typedef struct {
type EFI_ACPI_5_1_GTDT_GT_BLOCK_TIMER_STRUCTURE (line 1316) | typedef struct {
type EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE (line 1343) | typedef struct {
type EFI_ACPI_5_1_BOOT_ERROR_RECORD_TABLE_HEADER (line 1363) | typedef struct {
type EFI_ACPI_5_1_ERROR_BLOCK_STATUS (line 1377) | typedef struct {
type EFI_ACPI_5_1_BOOT_ERROR_REGION_STRUCTURE (line 1389) | typedef struct {
type EFI_ACPI_5_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE (line 1414) | typedef struct {
type EFI_ACPI_5_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER (line 1433) | typedef struct {
type EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE (line 1463) | typedef struct {
type EFI_ACPI_5_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE (line 1480) | typedef struct {
type EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE (line 1511) | typedef struct {
type EFI_ACPI_5_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE (line 1524) | typedef struct {
type EFI_ACPI_5_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE (line 1539) | typedef struct {
type EFI_ACPI_5_1_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE (line 1555) | typedef struct {
type EFI_ACPI_5_1_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE (line 1567) | typedef struct {
type EFI_ACPI_5_1_PCI_EXPRESS_DEVICE_AER_STRUCTURE (line 1590) | typedef struct {
type EFI_ACPI_5_1_PCI_EXPRESS_BRIDGE_AER_STRUCTURE (line 1612) | typedef struct {
type EFI_ACPI_5_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE (line 1637) | typedef struct {
type EFI_ACPI_5_1_GENERIC_ERROR_STATUS_STRUCTURE (line 1654) | typedef struct {
type EFI_ACPI_5_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER (line 1665) | typedef struct {
type EFI_ACPI_5_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY (line 1737) | typedef struct {
type EFI_ACPI_5_1_ERROR_INJECTION_TABLE_HEADER (line 1750) | typedef struct {
type EFI_ACPI_5_1_EINJ_INJECTION_INSTRUCTION_ENTRY (line 1817) | typedef struct {
type EFI_ACPI_5_1_EINJ_TRIGGER_ACTION_TABLE (line 1830) | typedef struct {
type EFI_ACPI_5_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER (line 1840) | typedef struct {
type EFI_ACPI_5_1_PCCT_SUBSPACE_HEADER (line 1864) | typedef struct {
type EFI_ACPI_5_1_PCCT_SUBSPACE_GENERIC (line 1872) | typedef struct {
type EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND (line 1890) | typedef struct {
type EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS (line 1896) | typedef struct {
type EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER (line 1905) | typedef struct {
FILE: src/edk2/Acpi60.h
type EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE (line 44) | typedef struct {
type EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER (line 79) | typedef struct {
type EFI_ACPI_6_0_COMMON_HEADER (line 100) | typedef struct {
type EFI_ACPI_6_0_FIXED_ACPI_DESCRIPTION_TABLE (line 130) | typedef struct {
type EFI_ACPI_6_0_FIRMWARE_ACPI_CONTROL_STRUCTURE (line 256) | typedef struct {
type EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER (line 302) | typedef struct {
type EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_STRUCTURE (line 348) | typedef struct {
type EFI_ACPI_6_0_IO_APIC_STRUCTURE (line 364) | typedef struct {
type EFI_ACPI_6_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE (line 376) | typedef struct {
type EFI_ACPI_6_0_PLATFORM_INTERRUPT_APIC_STRUCTURE (line 388) | typedef struct {
type EFI_ACPI_6_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE (line 412) | typedef struct {
type EFI_ACPI_6_0_LOCAL_APIC_NMI_STRUCTURE (line 422) | typedef struct {
type EFI_ACPI_6_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE (line 433) | typedef struct {
type EFI_ACPI_6_0_IO_SAPIC_STRUCTURE (line 443) | typedef struct {
type EFI_ACPI_6_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE (line 456) | typedef struct {
type EFI_ACPI_6_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE (line 470) | typedef struct {
type EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE (line 491) | typedef struct {
type EFI_ACPI_6_0_LOCAL_X2APIC_NMI_STRUCTURE (line 503) | typedef struct {
type EFI_ACPI_6_0_GIC_STRUCTURE (line 515) | typedef struct {
type EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE (line 545) | typedef struct {
type EFI_ACPI_6_0_GIC_MSI_FRAME_STRUCTURE (line 567) | typedef struct {
type EFI_ACPI_6_0_GICR_STRUCTURE (line 586) | typedef struct {
type EFI_ACPI_6_0_GIC_ITS_STRUCTURE (line 597) | typedef struct {
type EFI_ACPI_6_0_SMART_BATTERY_DESCRIPTION_TABLE (line 609) | typedef struct {
type EFI_ACPI_6_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE (line 626) | typedef struct {
type EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER (line 643) | typedef struct {
type EFI_ACPI_6_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE (line 667) | typedef struct {
type EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE (line 686) | typedef struct {
type EFI_ACPI_6_0_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE (line 710) | typedef struct {
type EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE (line 724) | typedef struct {
type EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER (line 742) | typedef struct {
type EFI_ACPI_6_0_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER (line 755) | typedef struct {
type EFI_ACPI_6_0_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE (line 773) | typedef struct {
type EFI_ACPI_6_0_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER (line 784) | typedef struct {
type EFI_ACPI_6_0_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE (line 800) | typedef struct {
type EFI_ACPI_6_0_RAS_FEATURE_TABLE (line 812) | typedef struct {
type EFI_ACPI_6_0_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION (line 825) | typedef struct {
type EFI_ACPI_6_0_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE (line 850) | typedef struct {
type EFI_ACPI_6_0_MEMORY_POWER_STATUS_TABLE (line 871) | typedef struct {
type EFI_ACPI_6_0_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION (line 887) | typedef struct {
type EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE (line 915) | typedef struct {
type EFI_ACPI_6_0_MPST_MEMORY_POWER_STRUCTURE (line 920) | typedef struct {
type EFI_ACPI_6_0_MPST_MEMORY_POWER_NODE_TABLE (line 937) | typedef struct {
type EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE (line 945) | typedef struct {
type EFI_ACPI_6_0_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE (line 958) | typedef struct {
type EFI_ACPI_6_0_MEMORY_TOPOLOGY_TABLE (line 966) | typedef struct {
type EFI_ACPI_6_0_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 979) | typedef struct {
type EFI_ACPI_6_0_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 997) | typedef struct {
type EFI_ACPI_6_0_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 1007) | typedef struct {
type EFI_ACPI_6_0_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 1024) | typedef struct {
type EFI_ACPI_6_0_BOOT_GRAPHICS_RESOURCE_TABLE (line 1035) | typedef struct {
type EFI_ACPI_6_0_FPDT_PERFORMANCE_RECORD_HEADER (line 1127) | typedef struct {
type EFI_ACPI_6_0_FPDT_PERFORMANCE_TABLE_HEADER (line 1136) | typedef struct {
type EFI_ACPI_6_0_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD (line 1144) | typedef struct {
type EFI_ACPI_6_0_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD (line 1156) | typedef struct {
type EFI_ACPI_6_0_FPDT_FIRMWARE_BASIC_BOOT_RECORD (line 1168) | typedef struct {
type EFI_ACPI_6_0_FPDT_FIRMWARE_BASIC_BOOT_TABLE (line 1209) | typedef struct {
type EFI_ACPI_6_0_FPDT_FIRMWARE_S3_BOOT_TABLE (line 1224) | typedef struct {
type EFI_ACPI_6_0_FPDT_S3_RESUME_RECORD (line 1234) | typedef struct {
type EFI_ACPI_6_0_FPDT_S3_SUSPEND_RECORD (line 1256) | typedef struct {
type EFI_ACPI_6_0_FIRMWARE_PERFORMANCE_RECORD_TABLE (line 1274) | typedef struct {
type EFI_ACPI_6_0_GENERIC_TIMER_DESCRIPTION_TABLE (line 1281) | typedef struct {
type EFI_ACPI_6_0_GTDT_GT_BLOCK_STRUCTURE (line 1319) | typedef struct {
type EFI_ACPI_6_0_GTDT_GT_BLOCK_TIMER_STRUCTURE (line 1331) | typedef struct {
type EFI_ACPI_6_0_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE (line 1358) | typedef struct {
type EFI_ACPI_6_0_NVDIMM_FIRMWARE_INTERFACE_TABLE (line 1378) | typedef struct {
type EFI_ACPI_6_0_NFIT_STRUCTURE_HEADER (line 1402) | typedef struct {
type EFI_ACPI_6_0_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE (line 1420) | typedef struct {
type EFI_ACPI_6_0_NFIT_DEVICE_HANDLE (line 1436) | typedef struct {
type EFI_ACPI_6_0_NFIT_MEMORY_DEVICE_TO_SYSTEM_ADDRESS_RANGE_MAP_STRUCTURE (line 1451) | typedef struct {
type EFI_ACPI_6_0_NFIT_INTERLEAVE_STRUCTURE (line 1471) | typedef struct {
type EFI_ACPI_6_0_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE (line 1484) | typedef struct {
type EFI_ACPI_6_0_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE (line 1495) | typedef struct {
type EFI_ACPI_6_0_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE (line 1521) | typedef struct {
type EFI_ACPI_6_0_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE (line 1535) | typedef struct {
type EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER (line 1547) | typedef struct {
type EFI_ACPI_6_0_ERROR_BLOCK_STATUS (line 1561) | typedef struct {
type EFI_ACPI_6_0_BOOT_ERROR_REGION_STRUCTURE (line 1573) | typedef struct {
type EFI_ACPI_6_0_GENERIC_ERROR_DATA_ENTRY_STRUCTURE (line 1598) | typedef struct {
type EFI_ACPI_6_0_HARDWARE_ERROR_SOURCE_TABLE_HEADER (line 1617) | typedef struct {
type EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE (line 1647) | typedef struct {
type EFI_ACPI_6_0_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE (line 1664) | typedef struct {
type EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE (line 1698) | typedef struct {
type EFI_ACPI_6_0_HARDWARE_ERROR_NOTIFICATION_STRUCTURE (line 1711) | typedef struct {
type EFI_ACPI_6_0_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE (line 1726) | typedef struct {
type EFI_ACPI_6_0_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE (line 1742) | typedef struct {
type EFI_ACPI_6_0_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE (line 1754) | typedef struct {
type EFI_ACPI_6_0_PCI_EXPRESS_DEVICE_AER_STRUCTURE (line 1777) | typedef struct {
type EFI_ACPI_6_0_PCI_EXPRESS_BRIDGE_AER_STRUCTURE (line 1799) | typedef struct {
type EFI_ACPI_6_0_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE (line 1824) | typedef struct {
type EFI_ACPI_6_0_GENERIC_ERROR_STATUS_STRUCTURE (line 1841) | typedef struct {
type EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER (line 1852) | typedef struct {
type EFI_ACPI_6_0_ERST_SERIALIZATION_INSTRUCTION_ENTRY (line 1924) | typedef struct {
type EFI_ACPI_6_0_ERROR_INJECTION_TABLE_HEADER (line 1937) | typedef struct {
type EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY (line 2004) | typedef struct {
type EFI_ACPI_6_0_EINJ_TRIGGER_ACTION_TABLE (line 2017) | typedef struct {
type EFI_ACPI_6_0_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER (line 2027) | typedef struct {
type EFI_ACPI_6_0_PCCT_SUBSPACE_HEADER (line 2053) | typedef struct {
type EFI_ACPI_6_0_PCCT_SUBSPACE_GENERIC (line 2061) | typedef struct {
type EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND (line 2079) | typedef struct {
type EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS (line 2085) | typedef struct {
type EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER (line 2094) | typedef struct {
type EFI_ACPI_6_0_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS (line 2106) | typedef struct {
type EFI_ACPI_6_0_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS (line 2125) | typedef struct {
FILE: src/edk2/Acpi61.h
type EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE (line 44) | typedef struct {
type EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER (line 79) | typedef struct {
type EFI_ACPI_6_1_COMMON_HEADER (line 100) | typedef struct {
type EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE (line 130) | typedef struct {
type EFI_ACPI_6_1_FIRMWARE_ACPI_CONTROL_STRUCTURE (line 256) | typedef struct {
type EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER (line 302) | typedef struct {
type EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_STRUCTURE (line 348) | typedef struct {
type EFI_ACPI_6_1_IO_APIC_STRUCTURE (line 364) | typedef struct {
type EFI_ACPI_6_1_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE (line 376) | typedef struct {
type EFI_ACPI_6_1_PLATFORM_INTERRUPT_APIC_STRUCTURE (line 388) | typedef struct {
type EFI_ACPI_6_1_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE (line 412) | typedef struct {
type EFI_ACPI_6_1_LOCAL_APIC_NMI_STRUCTURE (line 422) | typedef struct {
type EFI_ACPI_6_1_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE (line 433) | typedef struct {
type EFI_ACPI_6_1_IO_SAPIC_STRUCTURE (line 443) | typedef struct {
type EFI_ACPI_6_1_PROCESSOR_LOCAL_SAPIC_STRUCTURE (line 456) | typedef struct {
type EFI_ACPI_6_1_PLATFORM_INTERRUPT_SOURCES_STRUCTURE (line 470) | typedef struct {
type EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC_STRUCTURE (line 491) | typedef struct {
type EFI_ACPI_6_1_LOCAL_X2APIC_NMI_STRUCTURE (line 503) | typedef struct {
type EFI_ACPI_6_1_GIC_STRUCTURE (line 515) | typedef struct {
type EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE (line 545) | typedef struct {
type EFI_ACPI_6_1_GIC_MSI_FRAME_STRUCTURE (line 567) | typedef struct {
type EFI_ACPI_6_1_GICR_STRUCTURE (line 586) | typedef struct {
type EFI_ACPI_6_1_GIC_ITS_STRUCTURE (line 597) | typedef struct {
type EFI_ACPI_6_1_SMART_BATTERY_DESCRIPTION_TABLE (line 609) | typedef struct {
type EFI_ACPI_6_1_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE (line 626) | typedef struct {
type EFI_ACPI_6_1_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER (line 643) | typedef struct {
type EFI_ACPI_6_1_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE (line 667) | typedef struct {
type EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE (line 686) | typedef struct {
type EFI_ACPI_6_1_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE (line 710) | typedef struct {
type EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE (line 724) | typedef struct {
type EFI_ACPI_6_1_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER (line 742) | typedef struct {
type EFI_ACPI_6_1_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER (line 755) | typedef struct {
type EFI_ACPI_6_1_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE (line 773) | typedef struct {
type EFI_ACPI_6_1_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER (line 784) | typedef struct {
type EFI_ACPI_6_1_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE (line 800) | typedef struct {
type EFI_ACPI_6_1_RAS_FEATURE_TABLE (line 812) | typedef struct {
type EFI_ACPI_6_1_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION (line 825) | typedef struct {
type EFI_ACPI_6_1_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE (line 850) | typedef struct {
type EFI_ACPI_6_1_MEMORY_POWER_STATUS_TABLE (line 871) | typedef struct {
type EFI_ACPI_6_1_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION (line 887) | typedef struct {
type EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE (line 915) | typedef struct {
type EFI_ACPI_6_1_MPST_MEMORY_POWER_STRUCTURE (line 920) | typedef struct {
type EFI_ACPI_6_1_MPST_MEMORY_POWER_NODE_TABLE (line 937) | typedef struct {
type EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE (line 945) | typedef struct {
type EFI_ACPI_6_1_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE (line 958) | typedef struct {
type EFI_ACPI_6_1_MEMORY_TOPOLOGY_TABLE (line 966) | typedef struct {
type EFI_ACPI_6_1_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 979) | typedef struct {
type EFI_ACPI_6_1_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 997) | typedef struct {
type EFI_ACPI_6_1_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 1007) | typedef struct {
type EFI_ACPI_6_1_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 1024) | typedef struct {
type EFI_ACPI_6_1_BOOT_GRAPHICS_RESOURCE_TABLE (line 1035) | typedef struct {
type EFI_ACPI_6_1_FPDT_PERFORMANCE_RECORD_HEADER (line 1127) | typedef struct {
type EFI_ACPI_6_1_FPDT_PERFORMANCE_TABLE_HEADER (line 1136) | typedef struct {
type EFI_ACPI_6_1_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD (line 1144) | typedef struct {
type EFI_ACPI_6_1_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD (line 1156) | typedef struct {
type EFI_ACPI_6_1_FPDT_FIRMWARE_BASIC_BOOT_RECORD (line 1168) | typedef struct {
type EFI_ACPI_6_1_FPDT_FIRMWARE_BASIC_BOOT_TABLE (line 1209) | typedef struct {
type EFI_ACPI_6_1_FPDT_FIRMWARE_S3_BOOT_TABLE (line 1224) | typedef struct {
type EFI_ACPI_6_1_FPDT_S3_RESUME_RECORD (line 1234) | typedef struct {
type EFI_ACPI_6_1_FPDT_S3_SUSPEND_RECORD (line 1256) | typedef struct {
type EFI_ACPI_6_1_FIRMWARE_PERFORMANCE_RECORD_TABLE (line 1274) | typedef struct {
type EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE (line 1281) | typedef struct {
type EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE (line 1319) | typedef struct {
type EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE (line 1331) | typedef struct {
type EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE (line 1358) | typedef struct {
type EFI_ACPI_6_1_NVDIMM_FIRMWARE_INTERFACE_TABLE (line 1378) | typedef struct {
type EFI_ACPI_6_1_NFIT_STRUCTURE_HEADER (line 1402) | typedef struct {
type EFI_ACPI_6_1_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE (line 1420) | typedef struct {
type EFI_ACPI_6_1_NFIT_DEVICE_HANDLE (line 1436) | typedef struct {
type EFI_ACPI_6_1_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE (line 1452) | typedef struct {
type EFI_ACPI_6_1_NFIT_INTERLEAVE_STRUCTURE (line 1472) | typedef struct {
type EFI_ACPI_6_1_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE (line 1485) | typedef struct {
type EFI_ACPI_6_1_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE (line 1498) | typedef struct {
type EFI_ACPI_6_1_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE (line 1527) | typedef struct {
type EFI_ACPI_6_1_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE (line 1541) | typedef struct {
type EFI_ACPI_6_1_BOOT_ERROR_RECORD_TABLE_HEADER (line 1553) | typedef struct {
type EFI_ACPI_6_1_ERROR_BLOCK_STATUS (line 1567) | typedef struct {
type EFI_ACPI_6_1_BOOT_ERROR_REGION_STRUCTURE (line 1579) | typedef struct {
type EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE (line 1604) | typedef struct {
type EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER (line 1624) | typedef struct {
type EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE (line 1655) | typedef struct {
type EFI_ACPI_6_1_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE (line 1672) | typedef struct {
type EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE (line 1709) | typedef struct {
type EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE (line 1722) | typedef struct {
type EFI_ACPI_6_1_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE (line 1737) | typedef struct {
type EFI_ACPI_6_1_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE (line 1753) | typedef struct {
type EFI_ACPI_6_1_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE (line 1765) | typedef struct {
type EFI_ACPI_6_1_PCI_EXPRESS_DEVICE_AER_STRUCTURE (line 1788) | typedef struct {
type EFI_ACPI_6_1_PCI_EXPRESS_BRIDGE_AER_STRUCTURE (line 1810) | typedef struct {
type EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE (line 1835) | typedef struct {
type EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE (line 1852) | typedef struct {
type EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE (line 1872) | typedef struct {
type EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER (line 1883) | typedef struct {
type EFI_ACPI_6_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY (line 1956) | typedef struct {
type EFI_ACPI_6_1_ERROR_INJECTION_TABLE_HEADER (line 1969) | typedef struct {
type EFI_ACPI_6_1_EINJ_INJECTION_INSTRUCTION_ENTRY (line 2037) | typedef struct {
type EFI_ACPI_6_1_EINJ_TRIGGER_ACTION_TABLE (line 2050) | typedef struct {
type EFI_ACPI_6_1_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER (line 2060) | typedef struct {
type EFI_ACPI_6_1_PCCT_SUBSPACE_HEADER (line 2086) | typedef struct {
type EFI_ACPI_6_1_PCCT_SUBSPACE_GENERIC (line 2094) | typedef struct {
type EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND (line 2112) | typedef struct {
type EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS (line 2118) | typedef struct {
type EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER (line 2127) | typedef struct {
type EFI_ACPI_6_1_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS (line 2139) | typedef struct {
type EFI_ACPI_6_1_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS (line 2158) | typedef struct {
FILE: src/edk2/Acpi62.h
type PACKED (line 58) | typedef PACKED struct
type PACKED (line 74) | typedef PACKED struct
type PACKED (line 90) | typedef PACKED struct
type PACKED (line 103) | typedef PACKED struct
type PACKED (line 118) | typedef PACKED struct
type EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE (line 141) | typedef struct {
type EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER (line 176) | typedef struct {
type EFI_ACPI_6_2_COMMON_HEADER (line 197) | typedef struct {
type EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE (line 227) | typedef struct {
type EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE (line 353) | typedef struct {
type EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER (line 399) | typedef struct {
type EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_STRUCTURE (line 445) | typedef struct {
type EFI_ACPI_6_2_IO_APIC_STRUCTURE (line 461) | typedef struct {
type EFI_ACPI_6_2_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE (line 473) | typedef struct {
type EFI_ACPI_6_2_PLATFORM_INTERRUPT_APIC_STRUCTURE (line 485) | typedef struct {
type EFI_ACPI_6_2_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE (line 509) | typedef struct {
type EFI_ACPI_6_2_LOCAL_APIC_NMI_STRUCTURE (line 519) | typedef struct {
type EFI_ACPI_6_2_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE (line 530) | typedef struct {
type EFI_ACPI_6_2_IO_SAPIC_STRUCTURE (line 540) | typedef struct {
type EFI_ACPI_6_2_PROCESSOR_LOCAL_SAPIC_STRUCTURE (line 553) | typedef struct {
type EFI_ACPI_6_2_PLATFORM_INTERRUPT_SOURCES_STRUCTURE (line 567) | typedef struct {
type EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_STRUCTURE (line 588) | typedef struct {
type EFI_ACPI_6_2_LOCAL_X2APIC_NMI_STRUCTURE (line 600) | typedef struct {
type EFI_ACPI_6_2_GIC_STRUCTURE (line 612) | typedef struct {
type EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE (line 642) | typedef struct {
type EFI_ACPI_6_2_GIC_MSI_FRAME_STRUCTURE (line 664) | typedef struct {
type EFI_ACPI_6_2_GICR_STRUCTURE (line 683) | typedef struct {
type EFI_ACPI_6_2_GIC_ITS_STRUCTURE (line 694) | typedef struct {
type EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE (line 706) | typedef struct {
type EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE (line 723) | typedef struct {
type EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER (line 740) | typedef struct {
type EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE (line 765) | typedef struct {
type EFI_ACPI_6_2_MEMORY_AFFINITY_STRUCTURE (line 784) | typedef struct {
type EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE (line 808) | typedef struct {
type EFI_ACPI_6_2_GICC_AFFINITY_STRUCTURE (line 822) | typedef struct {
type EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE (line 839) | typedef struct {
type EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER (line 851) | typedef struct {
type EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER (line 864) | typedef struct {
type EFI_ACPI_6_2_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE (line 882) | typedef struct {
type EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER (line 893) | typedef struct {
type EFI_ACPI_6_2_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE (line 909) | typedef struct {
type EFI_ACPI_6_2_RAS_FEATURE_TABLE (line 921) | typedef struct {
type EFI_ACPI_6_2_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION (line 934) | typedef struct {
type EFI_ACPI_6_2_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE (line 962) | typedef struct {
type EFI_ACPI_6_2_MEMORY_POWER_STATUS_TABLE (line 983) | typedef struct {
type EFI_ACPI_6_2_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION (line 999) | typedef struct {
type EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE (line 1027) | typedef struct {
type EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE (line 1032) | typedef struct {
type EFI_ACPI_6_2_MPST_MEMORY_POWER_NODE_TABLE (line 1049) | typedef struct {
type EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE (line 1057) | typedef struct {
type EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE (line 1070) | typedef struct {
type EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE (line 1078) | typedef struct {
type EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 1091) | typedef struct {
type EFI_ACPI_6_2_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 1109) | typedef struct {
type EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 1119) | typedef struct {
type EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 1136) | typedef struct {
type EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE (line 1147) | typedef struct {
type EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER (line 1239) | typedef struct {
type EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER (line 1248) | typedef struct {
type EFI_ACPI_6_2_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD (line 1256) | typedef struct {
type EFI_ACPI_6_2_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD (line 1268) | typedef struct {
type EFI_ACPI_6_2_FPDT_FIRMWARE_BASIC_BOOT_RECORD (line 1280) | typedef struct {
type EFI_ACPI_6_2_FPDT_FIRMWARE_BASIC_BOOT_TABLE (line 1321) | typedef struct {
type EFI_ACPI_6_2_FPDT_FIRMWARE_S3_BOOT_TABLE (line 1336) | typedef struct {
type EFI_ACPI_6_2_FPDT_S3_RESUME_RECORD (line 1346) | typedef struct {
type EFI_ACPI_6_2_FPDT_S3_SUSPEND_RECORD (line 1368) | typedef struct {
type EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_RECORD_TABLE (line 1386) | typedef struct {
type EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE (line 1393) | typedef struct {
type EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE (line 1431) | typedef struct {
type EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_STRUCTURE (line 1443) | typedef struct {
type EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE (line 1470) | typedef struct {
type EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE (line 1490) | typedef struct {
type EFI_ACPI_6_2_NFIT_STRUCTURE_HEADER (line 1515) | typedef struct {
type EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE (line 1533) | typedef struct {
type EFI_ACPI_6_2_NFIT_DEVICE_HANDLE (line 1549) | typedef struct {
type EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE (line 1565) | typedef struct {
type EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE (line 1585) | typedef struct {
type EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE (line 1598) | typedef struct {
type EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE (line 1611) | typedef struct {
type EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE (line 1640) | typedef struct {
type EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE (line 1654) | typedef struct {
type EFI_ACPI_6_2_NFIT_PLATFORM_CAPABILITIES_STRUCTURE (line 1666) | typedef struct {
type EFI_ACPI_6_2_SECURE_DEVICES_TABLE_HEADER (line 1682) | typedef struct {
type EFI_ACPI_6_2_SDEV_STRUCTURE_HEADER (line 1705) | typedef struct {
type EFI_ACPI_6_2_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE (line 1714) | typedef struct {
type EFI_ACPI_6_2_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE (line 1729) | typedef struct {
type EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_HEADER (line 1742) | typedef struct {
type EFI_ACPI_6_2_ERROR_BLOCK_STATUS (line 1756) | typedef struct {
type EFI_ACPI_6_2_BOOT_ERROR_REGION_STRUCTURE (line 1768) | typedef struct {
type EFI_ACPI_6_2_GENERIC_ERROR_DATA_ENTRY_STRUCTURE (line 1793) | typedef struct {
type EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_HEADER (line 1813) | typedef struct {
type EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE (line 1846) | typedef struct {
type EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE (line 1863) | typedef struct {
type EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE (line 1901) | typedef struct {
type EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE (line 1914) | typedef struct {
type EFI_ACPI_6_2_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE (line 1929) | typedef struct {
type EFI_ACPI_6_2_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE (line 1945) | typedef struct {
type EFI_ACPI_6_2_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE (line 1957) | typedef struct {
type EFI_ACPI_6_2_PCI_EXPRESS_DEVICE_AER_STRUCTURE (line 1980) | typedef struct {
type EFI_ACPI_6_2_PCI_EXPRESS_BRIDGE_AER_STRUCTURE (line 2002) | typedef struct {
type EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE (line 2027) | typedef struct {
type EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE (line 2044) | typedef struct {
type EFI_ACPI_6_2_GENERIC_ERROR_STATUS_STRUCTURE (line 2064) | typedef struct {
type EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE (line 2075) | typedef struct {
type EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER (line 2091) | typedef struct {
type EFI_ACPI_6_2_HMAT_STRUCTURE_HEADER (line 2111) | typedef struct {
type EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS (line 2120) | typedef struct {
type EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE (line 2130) | typedef struct {
type EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS (line 2146) | typedef struct {
type EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO (line 2154) | typedef struct {
type EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES (line 2170) | typedef struct {
type EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO (line 2181) | typedef struct {
type EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_HEADER (line 2196) | typedef struct {
type EFI_ACPI_6_2_ERST_SERIALIZATION_INSTRUCTION_ENTRY (line 2269) | typedef struct {
type EFI_ACPI_6_2_ERROR_INJECTION_TABLE_HEADER (line 2282) | typedef struct {
type EFI_ACPI_6_2_EINJ_INJECTION_INSTRUCTION_ENTRY (line 2350) | typedef struct {
type EFI_ACPI_6_2_EINJ_TRIGGER_ACTION_TABLE (line 2363) | typedef struct {
type EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER (line 2373) | typedef struct {
type EFI_ACPI_6_2_PCCT_SUBSPACE_HEADER (line 2401) | typedef struct {
type EFI_ACPI_6_2_PCCT_SUBSPACE_GENERIC (line 2409) | typedef struct {
type EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND (line 2427) | typedef struct {
type EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS (line 2433) | typedef struct {
type EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER (line 2442) | typedef struct {
type EFI_ACPI_6_2_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS (line 2454) | typedef struct {
type EFI_ACPI_6_2_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS (line 2473) | typedef struct {
type EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC (line 2495) | typedef struct {
type EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC (line 2525) | typedef EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_2_PCCT_SUBS...
type EFI_ACPI_6_2_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER (line 2529) | typedef struct {
type EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER (line 2539) | typedef struct {
type EFI_ACPI_6_2_PDTT_PCC_IDENTIFIER (line 2554) | typedef struct {
type EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER (line 2570) | typedef EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6...
type EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER (line 2575) | typedef struct {
type EFI_ACPI_6_2_PPTT_STRUCTURE_HEADER (line 2594) | typedef struct {
type EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS (line 2609) | typedef struct {
type EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR (line 2618) | typedef struct {
type EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS (line 2631) | typedef struct {
type EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES (line 2657) | typedef struct {
type EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE (line 2667) | typedef struct {
type EFI_ACPI_6_2_PPTT_STRUCTURE_ID (line 2683) | typedef struct {
FILE: src/edk2/Acpi63.h
type EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE (line 44) | typedef struct {
type EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER (line 84) | typedef struct {
type EFI_ACPI_6_3_COMMON_HEADER (line 105) | typedef struct {
type EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE (line 135) | typedef struct {
type EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE (line 261) | typedef struct {
type EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER (line 307) | typedef struct {
type EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE (line 353) | typedef struct {
type EFI_ACPI_6_3_IO_APIC_STRUCTURE (line 370) | typedef struct {
type EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE (line 382) | typedef struct {
type EFI_ACPI_6_3_PLATFORM_INTERRUPT_APIC_STRUCTURE (line 394) | typedef struct {
type EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE (line 418) | typedef struct {
type EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE (line 428) | typedef struct {
type EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE (line 439) | typedef struct {
type EFI_ACPI_6_3_IO_SAPIC_STRUCTURE (line 449) | typedef struct {
type EFI_ACPI_6_3_PROCESSOR_LOCAL_SAPIC_STRUCTURE (line 462) | typedef struct {
type EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES_STRUCTURE (line 476) | typedef struct {
type EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE (line 497) | typedef struct {
type EFI_ACPI_6_3_LOCAL_X2APIC_NMI_STRUCTURE (line 509) | typedef struct {
type EFI_ACPI_6_3_GIC_STRUCTURE (line 521) | typedef struct {
type EFI_ACPI_6_3_GIC_DISTRIBUTOR_STRUCTURE (line 552) | typedef struct {
type EFI_ACPI_6_3_GIC_MSI_FRAME_STRUCTURE (line 574) | typedef struct {
type EFI_ACPI_6_3_GICR_STRUCTURE (line 593) | typedef struct {
type EFI_ACPI_6_3_GIC_ITS_STRUCTURE (line 604) | typedef struct {
type EFI_ACPI_6_3_SMART_BATTERY_DESCRIPTION_TABLE (line 616) | typedef struct {
type EFI_ACPI_6_3_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE (line 633) | typedef struct {
type EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER (line 650) | typedef struct {
type EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE (line 676) | typedef struct {
type EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE (line 695) | typedef struct {
type EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE (line 719) | typedef struct {
type EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE (line 733) | typedef struct {
type EFI_ACPI_6_3_GIC_ITS_AFFINITY_STRUCTURE (line 750) | typedef struct {
type EFI_ACPI_6_3_DEVICE_HANDLE_ACPI (line 769) | typedef struct {
type EFI_ACPI_6_3_DEVICE_HANDLE_PCI (line 778) | typedef struct {
type EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY_STRUCTURE (line 787) | typedef struct {
type EFI_ACPI_6_3_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER (line 813) | typedef struct {
type EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER (line 826) | typedef struct {
type EFI_ACPI_6_3_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE (line 844) | typedef struct {
type EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER (line 855) | typedef struct {
type EFI_ACPI_6_3_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE (line 871) | typedef struct {
type EFI_ACPI_6_3_RAS_FEATURE_TABLE (line 883) | typedef struct {
type EFI_ACPI_6_3_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION (line 896) | typedef struct {
type EFI_ACPI_6_3_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE (line 924) | typedef struct {
type EFI_ACPI_6_3_MEMORY_POWER_STATUS_TABLE (line 945) | typedef struct {
type EFI_ACPI_6_3_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION (line 961) | typedef struct {
type EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE (line 989) | typedef struct {
type EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE (line 994) | typedef struct {
type EFI_ACPI_6_3_MPST_MEMORY_POWER_NODE_TABLE (line 1011) | typedef struct {
type EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE (line 1019) | typedef struct {
type EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE (line 1032) | typedef struct {
type EFI_ACPI_6_3_MEMORY_TOPOLOGY_TABLE (line 1040) | typedef struct {
type EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 1053) | typedef struct {
type EFI_ACPI_6_3_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 1071) | typedef struct {
type EFI_ACPI_6_3_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 1081) | typedef struct {
type EFI_ACPI_6_3_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE (line 1098) | typedef struct {
type EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE (line 1109) | typedef struct {
type EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER (line 1201) | typedef struct {
type EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER (line 1210) | typedef struct {
type EFI_ACPI_6_3_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD (line 1218) | typedef struct {
type EFI_ACPI_6_3_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD (line 1230) | typedef struct {
type EFI_ACPI_6_3_FPDT_FIRMWARE_BASIC_BOOT_RECORD (line 1242) | typedef struct {
type EFI_ACPI_6_3_FPDT_FIRMWARE_BASIC_BOOT_TABLE (line 1283) | typedef struct {
type EFI_ACPI_6_3_FPDT_FIRMWARE_S3_BOOT_TABLE (line 1298) | typedef struct {
type EFI_ACPI_6_3_FPDT_S3_RESUME_RECORD (line 1308) | typedef struct {
type EFI_ACPI_6_3_FPDT_S3_SUSPEND_RECORD (line 1330) | typedef struct {
type EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_RECORD_TABLE (line 1348) | typedef struct {
type EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE (line 1355) | typedef struct {
type EFI_ACPI_6_3_GTDT_GT_BLOCK_STRUCTURE (line 1395) | typedef struct {
type EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_STRUCTURE (line 1407) | typedef struct {
type EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE (line 1434) | typedef struct {
type EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE (line 1454) | typedef struct {
type EFI_ACPI_6_3_NFIT_STRUCTURE_HEADER (line 1479) | typedef struct {
type EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE (line 1497) | typedef struct {
type EFI_ACPI_6_3_NFIT_DEVICE_HANDLE (line 1513) | typedef struct {
type EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE (line 1529) | typedef struct {
type EFI_ACPI_6_3_NFIT_INTERLEAVE_STRUCTURE (line 1549) | typedef struct {
type EFI_ACPI_6_3_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE (line 1562) | typedef struct {
type EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE (line 1575) | typedef struct {
type EFI_ACPI_6_3_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE (line 1604) | typedef struct {
type EFI_ACPI_6_3_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE (line 1618) | typedef struct {
type EFI_ACPI_6_3_NFIT_PLATFORM_CAPABILITIES_STRUCTURE (line 1630) | typedef struct {
type EFI_ACPI_6_3_SECURE_DEVICES_TABLE_HEADER (line 1646) | typedef struct {
type EFI_ACPI_6_3_SDEV_STRUCTURE_HEADER (line 1669) | typedef struct {
type EFI_ACPI_6_3_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE (line 1678) | typedef struct {
type EFI_ACPI_6_3_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE (line 1693) | typedef struct {
type EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_HEADER (line 1706) | typedef struct {
type EFI_ACPI_6_3_ERROR_BLOCK_STATUS (line 1720) | typedef struct {
type EFI_ACPI_6_3_BOOT_ERROR_REGION_STRUCTURE (line 1732) | typedef struct {
type EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_STRUCTURE (line 1757) | typedef struct {
type EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_HEADER (line 1777) | typedef struct {
type EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE (line 1810) | typedef struct {
type EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE (line 1827) | typedef struct {
type EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE (line 1865) | typedef struct {
type EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE (line 1878) | typedef struct {
type EFI_ACPI_6_3_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE (line 1893) | typedef struct {
type EFI_ACPI_6_3_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE (line 1909) | typedef struct {
type EFI_ACPI_6_3_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE (line 1921) | typedef struct {
type EFI_ACPI_6_3_PCI_EXPRESS_DEVICE_AER_STRUCTURE (line 1944) | typedef struct {
type EFI_ACPI_6_3_PCI_EXPRESS_BRIDGE_AER_STRUCTURE (line 1966) | typedef struct {
type EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE (line 1991) | typedef struct {
type EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE (line 2008) | typedef struct {
type EFI_ACPI_6_3_GENERIC_ERROR_STATUS_STRUCTURE (line 2028) | typedef struct {
type EFI_ACPI_6_3_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE (line 2039) | typedef struct {
type EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER (line 2055) | typedef struct {
type EFI_ACPI_6_3_HMAT_STRUCTURE_HEADER (line 2075) | typedef struct {
type EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS (line 2084) | typedef struct {
type EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES (line 2092) | typedef struct {
type EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS (line 2106) | typedef struct {
type EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO (line 2114) | typedef struct {
type EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES (line 2130) | typedef struct {
type EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO (line 2141) | typedef struct {
type EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_HEADER (line 2156) | typedef struct {
type EFI_ACPI_6_3_ERST_SERIALIZATION_INSTRUCTION_ENTRY (line 2229) | typedef struct {
type EFI_ACPI_6_3_ERROR_INJECTION_TABLE_HEADER (line 2242) | typedef struct {
type EFI_ACPI_6_3_EINJ_INJECTION_INSTRUCTION_ENTRY (line 2310) | typedef struct {
type EFI_ACPI_6_3_EINJ_TRIGGER_ACTION_TABLE (line 2323) | typedef struct {
type EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER (line 2333) | typedef struct {
type EFI_ACPI_6_3_PCCT_SUBSPACE_HEADER (line 2361) | typedef struct {
type EFI_ACPI_6_3_PCCT_SUBSPACE_GENERIC (line 2369) | typedef struct {
type EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND (line 2387) | typedef struct {
type EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS (line 2393) | typedef struct {
type EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER (line 2402) | typedef struct {
type EFI_ACPI_6_3_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS (line 2414) | typedef struct {
type EFI_ACPI_6_3_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS (line 2433) | typedef struct {
type EFI_ACPI_6_3_PCCT_SUBSPACE_3_EXTENDED_PCC (line 2455) | typedef struct {
type EFI_ACPI_6_3_PCCT_SUBSPACE_3_EXTENDED_PCC (line 2485) | typedef EFI_ACPI_6_3_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_3_PCCT_SUBS...
type EFI_ACPI_6_3_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER (line 2489) | typedef struct {
type EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER (line 2499) | typedef struct {
type EFI_ACPI_6_3_PDTT_PCC_IDENTIFIER (line 2514) | typedef struct {
type EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER (line 2531) | typedef EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6...
type EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER (line 2536) | typedef struct {
type EFI_ACPI_6_3_PPTT_STRUCTURE_HEADER (line 2555) | typedef struct {
type EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS (line 2578) | typedef struct {
type EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR (line 2590) | typedef struct {
type EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_FLAGS (line 2621) | typedef struct {
type EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_ATTRIBUTES (line 2647) | typedef struct {
type EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE (line 2657) | typedef struct {
type EFI_ACPI_6_3_PPTT_STRUCTURE_ID (line 2673) | typedef struct {
FILE: src/edk2/Acpi64.h
type EFI_ACPI_6_4_GENERIC_ADDRESS_STRUCTURE (line 44) | typedef struct {
type EFI_ACPI_6_4_ROOT_SYSTEM_DESCRIPTION_POINTER (line 84) | typedef struct {
type EFI_ACPI_6_4_COMMON_HEADER (line 105) | typedef struct {
type EFI_ACPI_6_4_FIXED_ACPI_DESCRIPTION_TABLE (line 135) | typedef struct {
type EFI_ACPI_6_4_FIRMWARE_ACPI_CONTROL_STRUCTURE (line 261) | typedef struct {
type EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER (line 307) | typedef struct {
type EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_STRUCTURE (line 354) | typedef struct {
type EFI_ACPI_6_4_IO_APIC_STRUCTURE (line 371) | typedef struct {
type EFI_ACPI_6_4_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE (line 383) | typedef struct {
type EFI_ACPI_6_4_PLATFORM_INTERRUPT_APIC_STRUCTURE (line 395) | typedef struct {
type EFI_ACPI_6_4_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE (line 419) | typedef struct {
type EFI_ACPI_6_4_LOCAL_APIC_NMI_STRUCTURE (line 429) | typedef struct {
type EFI_ACPI_6_4_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE (line 440) | typedef struct {
type EFI_ACPI_6_4_IO_SAPIC_STRUCTURE (line 450) | typedef struct {
type EFI_ACPI_6_4_PROCESSOR_LOCAL_SAPIC_STRUCTURE (line 463) | typedef struct {
type EFI_ACPI_6_4_PLATFORM_INTERRUPT_SOURCES_STRUCTURE (line 477) | typedef struct {
type EFI_ACPI_6_4_PROCESSOR_LOCAL_X2APIC_STRUCTURE (line 498) | typedef struct {
type EFI_ACPI_6_4_LOCAL_X2APIC_NMI_STRUCTURE (line 510) | typedef struct {
type EFI_ACPI_6_4_GIC_STRUCTURE (line 522) | typedef struct {
type EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE (line 553) | typedef struct {
type EFI_ACPI_6_4_GIC_MSI_FRAME_STRUCTURE (line 575) | typedef struct {
type EFI_ACPI_6_4_GICR_STRUCTURE (line 594) | typedef struct {
type EFI_ACPI_6_4_GIC_ITS_STRUCTURE (line 605) | typedef struct {
type EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_STRUCTURE (line 617) | typedef struct {
type EFI_ACPI_6_4_MULTIPROCESSOR_WAKEUP_MAILBOX_STRUCTURE (line 628) | typedef struct {
type EFI_ACPI_6_4_SMART_BATTERY_DESCRIPTION_TABLE (line 643) | typedef struct {
type EFI_ACPI_6_4_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE (line 660) | typedef struct {
type EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER (line 677) | typedef struct {
type EFI_ACPI_6_4_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE (line 703) | typedef struct {
type EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE (line 722) | typedef struct {
type EFI_ACPI_6_4_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE (line 746) | typedef struct {
type EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE (line 760) | typedef struct {
type EFI_ACPI_6_4_GIC_ITS_AFFINITY_STRUCTURE (line 777) | typedef struct {
type EFI_ACPI_6_4_DEVICE_HANDLE_ACPI (line 796) | typedef struct {
type EFI_ACPI_6_4_DEVICE_HANDLE_PCI (line 805) | typedef struct {
type EFI_ACPI_6_4_DEVICE_HANDLE (line 814) | typedef union {
type EFI_ACPI_6_4_GENERIC_INITIATOR_AFFINITY_STRUCTURE (line 822) | typedef struct {
type EFI_ACPI_6_4_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER (line 844) | typedef struct {
type EFI_ACPI_6_4_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER (line 857) | typedef struct {
type EFI_ACPI_6_4_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE (line 875) | typedef struct {
type EFI_ACPI_6_4_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER (line 886) | typedef struct {
type EFI_ACPI_6_4_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE (line 902) | typedef struct {
type EFI_ACPI_6_4_RAS_FEATURE_TABLE (line 914) | typedef struct {
type EFI_ACPI_6_4_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION (line 927) | typedef struct {
type EFI_ACPI_6_4_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE (line 955) | typedef struct {
type EFI_ACPI_6_4_MEMORY_POWER_STATUS_TABLE (line 976) | typedef struct {
type EFI_ACPI_6_4_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION (line 992) | typedef struct {
type EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE (line 1020) | typedef struct {
type EFI_ACPI_6_4_MPST_MEMORY_POWER_STRUCTURE (line 1025) | typedef struct {
type EFI_ACPI_6_4_MPST_MEMORY_POWER_NODE_TABLE (line 1042) | typedef struct {
type EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE (line 1050) | typedef struct {
type EFI_ACPI_6_4_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE (line 1063) | typedef struct {
type EFI_ACPI_6_4_PLATFORM_MEMORY_TOPOLOGY_TABLE (line 1071) | typedef struct {
type EFI_ACPI_6_4_PMTT_COMMON_MEMORY_DEVICE (line 1085) | typedef struct {
type EFI_ACPI_6_4_PMTT_SOCKET_TYPE_DATA (line 1107) | typedef struct {
type EFI_ACPI_6_4_PMTT_MEMORY_CONTROLLER_TYPE_DATA (line 1117) | typedef struct {
type EFI_ACPI_6_4_PMTT_DIMM_TYPE_SPECIFIC_DATA (line 1127) | typedef struct {
type EFI_ACPI_6_4_PMTT_VENDOR_SPECIFIC_TYPE_DATA (line 1135) | typedef struct {
type EFI_ACPI_6_4_BOOT_GRAPHICS_RESOURCE_TABLE (line 1145) | typedef struct {
type EFI_ACPI_6_4_FPDT_PERFORMANCE_RECORD_HEADER (line 1244) | typedef struct {
type EFI_ACPI_6_4_FPDT_PERFORMANCE_TABLE_HEADER (line 1253) | typedef struct {
type EFI_ACPI_6_4_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD (line 1261) | typedef struct {
type EFI_ACPI_6_4_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD (line 1273) | typedef struct {
type EFI_ACPI_6_4_FPDT_FIRMWARE_BASIC_BOOT_RECORD (line 1285) | typedef struct {
type EFI_ACPI_6_4_FPDT_FIRMWARE_BASIC_BOOT_TABLE (line 1326) | typedef struct {
type EFI_ACPI_6_4_FPDT_FIRMWARE_S3_BOOT_TABLE (line 1341) | typedef struct {
type EFI_ACPI_6_4_FPDT_S3_RESUME_RECORD (line 1351) | typedef struct {
type EFI_ACPI_6_4_FPDT_S3_SUSPEND_RECORD (line 1373) | typedef struct {
type EFI_ACPI_6_4_FIRMWARE_PERFORMANCE_RECORD_TABLE (line 1391) | typedef struct {
type EFI_ACPI_6_4_GENERIC_TIMER_DESCRIPTION_TABLE (line 1398) | typedef struct {
type EFI_ACPI_6_4_GTDT_GT_BLOCK_STRUCTURE (line 1438) | typedef struct {
type EFI_ACPI_6_4_GTDT_GT_BLOCK_TIMER_STRUCTURE (line 1450) | typedef struct {
type EFI_ACPI_6_4_GTDT_ARM_GENERIC_WATCHDOG_STRUCTURE (line 1477) | typedef struct {
type EFI_ACPI_6_4_NVDIMM_FIRMWARE_INTERFACE_TABLE (line 1497) | typedef struct {
type EFI_ACPI_6_4_NFIT_STRUCTURE_HEADER (line 1522) | typedef struct {
type EFI_ACPI_6_4_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE (line 1543) | typedef struct {
type EFI_ACPI_6_4_NFIT_DEVICE_HANDLE (line 1560) | typedef struct {
type EFI_ACPI_6_4_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE (line 1577) | typedef struct {
type EFI_ACPI_6_4_NFIT_INTERLEAVE_STRUCTURE (line 1597) | typedef struct {
type EFI_ACPI_6_4_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE (line 1610) | typedef struct {
type EFI_ACPI_6_4_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE (line 1624) | typedef struct {
type EFI_ACPI_6_4_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE (line 1653) | typedef struct {
type EFI_ACPI_6_4_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE (line 1667) | typedef struct {
type EFI_ACPI_6_4_NFIT_PLATFORM_CAPABILITIES_STRUCTURE (line 1679) | typedef struct {
type EFI_ACPI_6_4_SECURE_DEVICES_TABLE_HEADER (line 1695) | typedef struct {
type EFI_ACPI_6_4_SDEV_STRUCTURE_HEADER (line 1719) | typedef struct {
type EFI_ACPI_6_4_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE (line 1728) | typedef struct {
type EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_IDENTIFICATION_STRUCTURE (line 1747) | typedef struct {
type EFI_ACPI_6_4_SDEV_SECURE_ACCESS_COMPONENT_MEMORY_STRUCTURE (line 1764) | typedef struct {
type EFI_ACPI_6_4_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE (line 1774) | typedef struct {
type EFI_ACPI_6_4_BOOT_ERROR_RECORD_TABLE_HEADER (line 1787) | typedef struct {
type EFI_ACPI_6_4_ERROR_BLOCK_STATUS (line 1801) | typedef struct {
type EFI_ACPI_6_4_BOOT_ERROR_REGION_STRUCTURE (line 1813) | typedef struct {
type EFI_ACPI_6_4_GENERIC_ERROR_DATA_ENTRY_STRUCTURE (line 1838) | typedef struct {
type EFI_ACPI_6_4_HARDWARE_ERROR_SOURCE_TABLE_HEADER (line 1858) | typedef struct {
type EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE (line 1891) | typedef struct {
type EFI_ACPI_6_4_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE (line 1908) | typedef struct {
type EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE (line 1946) | typedef struct {
type EFI_ACPI_6_4_HARDWARE_ERROR_NOTIFICATION_STRUCTURE (line 1959) | typedef struct {
type EFI_ACPI_6_4_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE (line 1974) | typedef struct {
type EFI_ACPI_6_4_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE (line 1990) | typedef struct {
type EFI_ACPI_6_4_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE (line 2002) | typedef struct {
type EFI_ACPI_6_4_PCI_EXPRESS_DEVICE_AER_STRUCTURE (line 2025) | typedef struct {
type EFI_ACPI_6_4_PCI_EXPRESS_BRIDGE_AER_STRUCTURE (line 2047) | typedef struct {
type EFI_ACPI_6_4_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE (line 2072) | typedef struct {
type EFI_ACPI_6_4_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE (line 2089) | typedef struct {
type EFI_ACPI_6_4_GENERIC_ERROR_STATUS_STRUCTURE (line 2109) | typedef struct {
type EFI_ACPI_6_4_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE (line 2120) | typedef struct {
type EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER (line 2136) | typedef struct {
type EFI_ACPI_6_4_HMAT_STRUCTURE_HEADER (line 2156) | typedef struct {
type EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS (line 2165) | typedef struct {
type EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES (line 2173) | typedef struct {
type EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS (line 2187) | typedef struct {
type EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO (line 2196) | typedef struct {
type EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES (line 2213) | typedef struct {
type EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO (line 2224) | typedef struct {
type EFI_ACPI_6_4_ERROR_RECORD_SERIALIZATION_TABLE_HEADER (line 2239) | typedef struct {
type EFI_ACPI_6_4_ERST_SERIALIZATION_INSTRUCTION_ENTRY (line 2312) | typedef struct {
type EFI_ACPI_6_4_ERROR_INJECTION_TABLE_HEADER (line 2325) | typedef struct {
type EFI_ACPI_6_4_EINJ_INJECTION_INSTRUCTION_ENTRY (line 2393) | typedef struct {
type EFI_ACPI_6_4_EINJ_TRIGGER_ACTION_TABLE (line 2406) | typedef struct {
type EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER (line 2416) | typedef struct {
type EFI_ACPI_6_4_PCCT_SUBSPACE_HEADER (line 2445) | typedef struct {
type EFI_ACPI_6_4_PCCT_SUBSPACE_GENERIC (line 2453) | typedef struct {
type EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND (line 2471) | typedef struct {
type EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS (line 2477) | typedef struct {
type EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER (line 2486) | typedef struct {
type EFI_ACPI_6_4_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS (line 2498) | typedef struct {
type EFI_ACPI_6_4_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS (line 2517) | typedef struct {
type EFI_ACPI_6_4_PCCT_SUBSPACE_3_EXTENDED_PCC (line 2539) | typedef struct {
type EFI_ACPI_6_4_PCCT_SUBSPACE_3_EXTENDED_PCC (line 2569) | typedef EFI_ACPI_6_4_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_4_PCCT_SUBS...
type EFI_ACPI_6_4_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER (line 2573) | typedef struct {
type EFI_ACPI_6_4_PCCT_SUBSPACE_5_HW_REGISTERS_COMMUNICATIONS (line 2583) | typedef struct {
type EFI_6_4_PCCT_REDUCED_PCC_SUBSPACE_SHARED_MEMORY_REGION (line 2603) | typedef struct {
type EFI_ACPI_6_4_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER (line 2611) | typedef struct {
type EFI_ACPI_6_4_PDTT_PCC_IDENTIFIER (line 2626) | typedef struct {
type EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER (line 2643) | typedef EFI_ACPI_6_4_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6...
type EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER (line 2648) | typedef struct {
type EFI_ACPI_6_4_PPTT_STRUCTURE_HEADER (line 2666) | typedef struct {
type EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_FLAGS (line 2689) | typedef struct {
type EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR (line 2701) | typedef struct {
type EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_FLAGS (line 2734) | typedef struct {
type EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_ATTRIBUTES (line 2761) | typedef struct {
type EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE (line 2771) | typedef struct {
type EFI_ACPI_6_4_PLATFORM_HEALTH_ASSESSMENT_TABLE (line 2788) | typedef struct {
type EFI_ACPI_6_4_PHAT_RECORD (line 2798) | typedef struct {
type EFI_ACPI_6_4_PHAT_VERSION_ELEMENT (line 2814) | typedef struct {
type EFI_ACPI_6_4_PHAT_FIRMWARE_VERISON_DATA_RECORD (line 2823) | typedef struct {
type EFI_ACPI_6_4_PHAT_FIRMWARE_HEALTH_DATA_RECORD_STRUCTURE (line 2837) | typedef struct {
type EFI_ACPI_6_4_CEDT_CXL_HOST_BRIDGE_STRUCTURE (line 2875) | typedef struct {
type EFI_ACPI_6_4_CEDT_CXL_FIXED_MEMORY_WINDOW_STRUCTURE (line 2895) | typedef struct {
type EFI_ACPI_6_4_CEDT_CXL_XOR_INTERLEAVE_MATH_STRUCTURE (line 2952) | typedef struct {
type EFI_ACPI_6_4_CEDT_RCEC_DOWNSTREAM_PORT_ASSOCIATION_STRUCTURE (line 2965) | typedef struct {
type EFI_ACPI_6_4_CXL_EARLY_DISCOVERY_TABLE (line 2984) | typedef struct {
FILE: src/edk2/Acpi65.h
type EFI_ACPI_6_5_GENERIC_ADDRESS_STRUCTURE (line 54) | typedef struct {
type EFI_ACPI_6_5_ROOT_SYSTEM_DESCRIPTION_POINTER (line 95) | typedef struct {
type EFI_ACPI_6_5_COMMON_HEADER (line 116) | typedef struct {
type EFI_ACPI_6_5_FIXED_ACPI_DESCRIPTION_TABLE (line 146) | typedef struct {
type EFI_ACPI_6_5_FIRMWARE_ACPI_CONTROL_STRUCTURE (line 272) | typedef struct {
type EFI_ACPI_6_5_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER (line 318) | typedef struct {
type EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC_STRUCTURE (line 372) | typedef struct {
type EFI_ACPI_6_5_IO_APIC_STRUCTURE (line 389) | typedef struct {
type EFI_ACPI_6_5_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE (line 401) | typedef struct {
type EFI_ACPI_6_5_PLATFORM_INTERRUPT_APIC_STRUCTURE (line 413) | typedef struct {
type EFI_ACPI_6_5_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE (line 437) | typedef struct {
type EFI_ACPI_6_5_LOCAL_APIC_NMI_STRUCTURE (line 447) | typedef struct {
type EFI_ACPI_6_5_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE (line 458) | typedef struct {
type EFI_ACPI_6_5_IO_SAPIC_STRUCTURE (line 468) | typedef struct {
type EFI_ACPI_6_5_PROCESSOR_LOCAL_SAPIC_STRUCTURE (line 481) | typedef struct {
type EFI_ACPI_6_5_PLATFORM_INTERRUPT_SOURCES_STRUCTURE (line 495) | typedef struct {
type EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC_STRUCTURE (line 516) | typedef struct {
type EFI_ACPI_6_5_LOCAL_X2APIC_NMI_STRUCTURE (line 528) | typedef struct {
type EFI_ACPI_6_5_GIC_STRUCTURE (line 540) | typedef struct {
type EFI_ACPI_6_5_GIC_DISTRIBUTOR_STRUCTURE (line 573) | typedef struct {
type EFI_ACPI_6_5_GIC_MSI_FRAME_STRUCTURE (line 595) | typedef struct {
type EFI_ACPI_6_5_GICR_STRUCTURE (line 614) | typedef struct {
type EFI_ACPI_6_5_GIC_ITS_STRUCTURE (line 625) | typedef struct {
type EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_STRUCTURE (line 637) | typedef struct {
type EFI_ACPI_6_5_MULTIPROCESSOR_WAKEUP_MAILBOX_STRUCTURE (line 648) | typedef struct {
type EFI_ACPI_6_5_CORE_PIC_STRUCTURE (line 663) | typedef struct {
type EFI_ACPI_6_5_LIO_PIC_STRUCTURE (line 675) | typedef struct {
type EFI_ACPI_6_5_HT_PIC_STRUCTURE (line 688) | typedef struct {
type EFI_ACPI_6_5_EIO_PIC_STRUCTURE (line 700) | typedef struct {
type EFI_ACPI_6_5_MSI_PIC_STRUCTURE (line 712) | typedef struct {
type EFI_ACPI_6_5_BIO_PIC_STRUCTURE (line 724) | typedef struct {
type EFI_ACPI_6_5_LPC_PIC_STRUCTURE (line 737) | typedef struct {
type EFI_ACPI_6_5_SMART_BATTERY_DESCRIPTION_TABLE (line 749) | typedef struct {
type EFI_ACPI_6_5_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE (line 766) | typedef struct {
type EFI_ACPI_6_5_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER (line 783) | typedef struct {
type EFI_ACPI_6_5_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE (line 809) | typedef struct {
type EFI_ACPI_6_5_MEMORY_AFFINITY_STRUCTURE (line 828) | typedef struct {
type EFI_ACPI_6_5_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE (line 852) | typedef struct {
type EFI_ACPI_6_5_GICC_AFFINITY_STRUCTURE (line 866) | typedef struct {
type EFI_ACPI_6_5_GIC_ITS_AFFINITY_STRUCTURE (line 883) | typedef struct {
type EFI_ACPI_6_5_DEVICE_HANDLE_ACPI (line 902) | typedef struct {
type EFI_ACPI_6_5_DEVICE_HANDLE_PCI (line 911) | typedef struct {
type EFI_ACPI_6_5_DEVICE_HANDLE (line 920) | typedef union {
type EFI_ACPI_6_5_GENERIC_INITIATOR_AFFINITY_STRUCTURE (line 928) | typedef struct {
type EFI_ACPI_6_5_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER (line 950) | typedef struct {
type EFI_ACPI_6_5_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER (line 963) | typedef struct {
type EFI_ACPI_6_5_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE (line 981) | typedef struct {
type EFI_ACPI_6_5_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER (line 992) | typedef struct {
type EFI_ACPI_6_5_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE (line 1008) | typedef struct {
type EFI_ACPI_6_5_RAS_FEATURE_TABLE (line 1020) | typedef struct {
type EFI_ACPI_6_5_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION (line 1033) | typedef struct {
type EFI_ACPI_6_5_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE (line 1061) | typedef struct {
type EFI_ACPI_RAS2_PCC_DESCRIPTOR (line 1082) | typedef struct {
type EFI_ACPI_6_5_RAS2_FEATURE_TABLE (line 1092) | typedef struct {
type EFI_ACPI_6_5_MEMORY_POWER_STATUS_TABLE (line 1102) | typedef struct {
type EFI_ACPI_6_5_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION (line 1118) | typedef struct {
type EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE (line 1146) | typedef struct {
type EFI_ACPI_6_5_MPST_MEMORY_POWER_STRUCTURE (line 1151) | typedef struct {
type EFI_ACPI_6_5_MPST_MEMORY_POWER_NODE_TABLE (line 1168) | typedef struct {
type EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE (line 1176) | typedef struct {
type EFI_ACPI_6_5_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE (line 1189) | typedef struct {
type EFI_ACPI_6_5_PLATFORM_MEMORY_TOPOLOGY_TABLE (line 1197) | typedef struct {
type EFI_ACPI_6_5_PMTT_COMMON_MEMORY_DEVICE (line 1211) | typedef struct {
type EFI_ACPI_6_5_PMTT_SOCKET_TYPE_DATA (line 1233) | typedef struct {
type EFI_ACPI_6_5_PMTT_MEMORY_CONTROLLER_TYPE_DATA (line 1243) | typedef struct {
type EFI_ACPI_6_5_PMTT_DIMM_TYPE_SPECIFIC_DATA (line 1253) | typedef struct {
type EFI_ACPI_6_5_PMTT_VENDOR_SPECIFIC_TYPE_DATA (line 1261) | typedef struct {
type EFI_ACPI_6_5_BOOT_GRAPHICS_RESOURCE_TABLE (line 1271) | typedef struct {
type EFI_ACPI_6_5_FPDT_PERFORMANCE_RECORD_HEADER (line 1370) | typedef struct {
type EFI_ACPI_6_5_FPDT_PERFORMANCE_TABLE_HEADER (line 1379) | typedef struct {
type EFI_ACPI_6_5_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD (line 1387) | typedef struct {
type EFI_ACPI_6_5_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD (line 1399) | typedef struct {
type EFI_ACPI_6_5_FPDT_FIRMWARE_BASIC_BOOT_RECORD (line 1411) | typedef struct {
type EFI_ACPI_6_5_FPDT_FIRMWARE_BASIC_BOOT_TABLE (line 1452) | typedef struct {
type EFI_ACPI_6_5_FPDT_FIRMWARE_S3_BOOT_TABLE (line 1467) | typedef struct {
type EFI_ACPI_6_5_FPDT_S3_RESUME_RECORD (line 1477) | typedef struct {
type EFI_ACPI_6_5_FPDT_S3_SUSPEND_RECORD (line 1499) | typedef struct {
type EFI_ACPI_6_5_FIRMWARE_PERFORMANCE_RECORD_TABLE (line 1517) | typedef struct {
type EFI_ACPI_6_5_GENERIC_TIMER_DESCRIPTION_TABLE (line 1524) | typedef struct {
type EFI_ACPI_6_5_GTDT_GT_BLOCK_STRUCTURE (line 1564) | typedef struct {
type EFI_ACPI_6_5_GTDT_GT_BLOCK_TIMER_STRUCTURE (line 1576) | typedef struct {
type EFI_ACPI_6_5_GTDT_ARM_GENERIC_WATCHDOG_STRUCTURE (line 1603) | typedef struct {
type EFI_ACPI_6_5_NVDIMM_FIRMWARE_INTERFACE_TABLE (line 1623) | typedef struct {
type EFI_ACPI_6_5_NFIT_STRUCTURE_HEADER (line 1648) | typedef struct {
type EFI_ACPI_6_5_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE (line 1669) | typedef struct {
type EFI_ACPI_6_5_NFIT_DEVICE_HANDLE (line 1686) | typedef struct {
type EFI_ACPI_6_5_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE (line 1703) | typedef struct {
type EFI_ACPI_6_5_NFIT_INTERLEAVE_STRUCTURE (line 1723) | typedef struct {
type EFI_ACPI_6_5_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE (line 1736) | typedef struct {
type EFI_ACPI_6_5_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE (line 1750) | typedef struct {
type EFI_ACPI_6_5_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE (line 1779) | typedef struct {
type EFI_ACPI_6_5_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE (line 1793) | typedef struct {
type EFI_ACPI_6_5_NFIT_PLATFORM_CAPABILITIES_STRUCTURE (line 1805) | typedef struct {
type EFI_ACPI_6_5_SECURE_DEVICES_TABLE_HEADER (line 1821) | typedef struct {
type EFI_ACPI_6_5_SDEV_STRUCTURE_HEADER (line 1845) | typedef struct {
type EFI_ACPI_6_5_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE (line 1854) | typedef struct {
type EFI_ACPI_6_5_SDEV_SECURE_ACCESS_COMPONENT_IDENTIFICATION_STRUCTURE (line 1873) | typedef struct {
type EFI_ACPI_6_5_SDEV_SECURE_ACCESS_COMPONENT_MEMORY_STRUCTURE (line 1890) | typedef struct {
type EFI_ACPI_6_5_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE (line 1900) | typedef struct {
type EFI_ACPI_6_5_BOOT_ERROR_RECORD_TABLE_HEADER (line 1913) | typedef struct {
type EFI_ACPI_6_5_ERROR_BLOCK_STATUS (line 1927) | typedef struct {
type EFI_ACPI_6_5_BOOT_ERROR_REGION_STRUCTURE (line 1939) | typedef struct {
type EFI_ACPI_6_5_GENERIC_ERROR_DATA_ENTRY_STRUCTURE (line 1964) | typedef struct {
type EFI_ACPI_6_5_HARDWARE_ERROR_SOURCE_TABLE_HEADER (line 1984) | typedef struct {
type EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE (line 2017) | typedef struct {
type EFI_ACPI_6_5_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE (line 2034) | typedef struct {
type EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE (line 2072) | typedef struct {
type EFI_ACPI_6_5_HARDWARE_ERROR_NOTIFICATION_STRUCTURE (line 2085) | typedef struct {
type EFI_ACPI_6_5_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE (line 2100) | typedef struct {
type EFI_ACPI_6_5_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE (line 2116) | typedef struct {
type EFI_ACPI_6_5_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE (line 2128) | typedef struct {
type EFI_ACPI_6_5_PCI_EXPRESS_DEVICE_AER_STRUCTURE (line 2151) | typedef struct {
type EFI_ACPI_6_5_PCI_EXPRESS_BRIDGE_AER_STRUCTURE (line 2173) | typedef struct {
type EFI_ACPI_6_5_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE (line 2198) | typedef struct {
type EFI_ACPI_6_5_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE (line 2215) | typedef struct {
type EFI_ACPI_6_5_GENERIC_ERROR_STATUS_STRUCTURE (line 2235) | typedef struct {
type EFI_ACPI_6_5_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE (line 2246) | typedef struct {
type EFI_ACPI_6_5_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER (line 2262) | typedef struct {
type EFI_ACPI_6_5_HMAT_STRUCTURE_HEADER (line 2282) | typedef struct {
type EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS (line 2291) | typedef struct {
type EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES (line 2299) | typedef struct {
type EFI_ACPI_6_5_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS (line 2313) | typedef struct {
type EFI_ACPI_6_5_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO (line 2322) | typedef struct {
type EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES (line 2339) | typedef struct {
type EFI_ACPI_6_5_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO (line 2350) | typedef struct {
type EFI_ACPI_6_5_ERROR_RECORD_SERIALIZATION_TABLE_HEADER (line 2365) | typedef struct {
type EFI_ACPI_6_5_ERST_SERIALIZATION_INSTRUCTION_ENTRY (line 2438) | typedef struct {
type EFI_ACPI_6_5_ERROR_INJECTION_TABLE_HEADER (line 2451) | typedef struct {
type EFI_ACPI_6_5_EINJ_INJECTION_INSTRUCTION_ENTRY (line 2521) | typedef struct {
type EFI_ACPI_6_5_EINJ_TRIGGER_ACTION_TABLE (line 2534) | typedef struct {
type EFI_ACPI_6_5_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER (line 2544) | typedef struct {
type EFI_ACPI_6_5_PCCT_SUBSPACE_HEADER (line 2573) | typedef struct {
type EFI_ACPI_6_5_PCCT_SUBSPACE_GENERIC (line 2581) | typedef struct {
type EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND (line 2599) | typedef struct {
type EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS (line 2605) | typedef struct {
type EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER (line 2614) | typedef struct {
type EFI_ACPI_6_5_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS (line 2626) | typedef struct {
type EFI_ACPI_6_5_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS (line 2645) | typedef struct {
type EFI_ACPI_6_5_PCCT_SUBSPACE_3_EXTENDED_PCC (line 2667) | typedef struct {
type EFI_ACPI_6_5_PCCT_SUBSPACE_3_EXTENDED_PCC (line 2697) | typedef EFI_ACPI_6_5_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_5_PCCT_SUBS...
type EFI_ACPI_6_5_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER (line 2701) | typedef struct {
type EFI_ACPI_6_5_PCCT_SUBSPACE_5_HW_REGISTERS_COMMUNICATIONS (line 2711) | typedef struct {
type EFI_6_5_PCCT_REDUCED_PCC_SUBSPACE_SHARED_MEMORY_REGION (line 2731) | typedef struct {
type EFI_ACPI_6_5_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER (line 2739) | typedef struct {
type EFI_ACPI_6_5_PDTT_PCC_IDENTIFIER (line 2754) | typedef struct {
type EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER (line 2771) | typedef EFI_ACPI_6_5_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6...
type EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER (line 2776) | typedef struct {
type EFI_ACPI_6_5_PPTT_STRUCTURE_HEADER (line 2794) | typedef struct {
type EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS (line 2817) | typedef struct {
type EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR (line 2829) | typedef struct {
type EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE_FLAGS (line 2862) | typedef struct {
type EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE_ATTRIBUTES (line 2889) | typedef struct {
type EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE (line 2899) | typedef struct {
type EFI_ACPI_6_5_PLATFORM_HEALTH_ASSESSMENT_TABLE (line 2916) | typedef struct {
type EFI_ACPI_6_5_PHAT_RECORD (line 2926) | typedef struct {
type EFI_ACPI_6_5_PHAT_VERSION_ELEMENT (line 2942) | typedef struct {
type EFI_ACPI_6_5_PHAT_FIRMWARE_VERISON_DATA_RECORD (line 2951) | typedef struct {
type EFI_ACPI_6_5_PHAT_FIRMWARE_HEALTH_DATA_RECORD_STRUCTURE (line 2965) | typedef struct {
type EFI_ACPI_6_5_PHAT_RESET_REASON_HEALTH_RECORD_VENDOR_DATA_ENTRY (line 2990) | typedef struct {
type EFI_ACPI_6_5_PHAT_RESET_REASON_HEALTH_RECORD_STRUCTURE (line 3000) | typedef struct {
FILE: src/edk2/Coreboot.h
type cbmem_entry (line 52) | struct cbmem_entry {
type cbmem_root (line 59) | struct cbmem_root {
type imd_entry (line 67) | struct imd_entry {
type imd_root (line 74) | struct imd_root {
type cbuint64 (line 83) | struct cbuint64 {
type cb_header (line 90) | struct cb_header {
type cb_record (line 99) | struct cb_record {
type cb_memory_range (line 107) | struct cb_memory_range {
type cb_memory (line 121) | struct cb_memory {
type cb_mainboard (line 129) | struct cb_mainboard {
type cb_string (line 148) | struct cb_string {
type cb_serial (line 156) | struct cb_serial {
type cb_console (line 183) | struct cb_console {
type cb_forward (line 198) | struct cb_forward {
type cb_cbmem_ref (line 204) | struct cb_cbmem_ref {
type cb_framebuffer (line 212) | struct cb_framebuffer {
type cb_vdat (line 232) | struct cb_vdat {
type cbmem_console (line 241) | struct cbmem_console {
type cb_cbmem_tab (line 248) | struct cb_cbmem_tab {
type cb_smmstorev2 (line 255) | struct cb_smmstorev2 {
type cb_cfr (line 270) | struct cb_cfr {
type CB_MEMORY (line 287) | typedef struct cb_memory CB_MEMORY;
type lb_tmp_ppi_tpm_version (line 291) | enum lb_tmp_ppi_tpm_version {
type cb_tpm_physical_presence (line 307) | struct cb_tpm_physical_presence {
FILE: src/edk2/E820.h
type EFI_ACPI_MEMORY_TYPE (line 17) | typedef enum {
type EFI_E820_ENTRY64 (line 24) | typedef struct {
type EFI_E820_ENTRY (line 30) | typedef struct {
FILE: src/edk2/LegacyBios.h
type UINT8 (line 31) | typedef UINT8 SERIAL_MODE;
type UINT8 (line 32) | typedef UINT8 PARALLEL_MODE;
type EFI_COMPATIBILITY16_TABLE (line 44) | typedef struct {
type EFI_COMPATIBILITY_FUNCTIONS (line 276) | typedef enum {
type EFI_DISPATCH_OPROM_TABLE (line 385) | typedef struct {
type EFI_TO_COMPATIBILITY16_INIT_TABLE (line 406) | typedef struct {
type DEVICE_PRODUCER_SERIAL (line 466) | typedef struct {
type DEVICE_PRODUCER_PARALLEL (line 485) | typedef struct {
type DEVICE_PRODUCER_FLOPPY (line 504) | typedef struct {
type LEGACY_DEVICE_FLAGS (line 514) | typedef struct {
type DEVICE_PRODUCER_DATA_HEADER (line 523) | typedef struct {
type ATAPI_IDENTIFY (line 534) | typedef struct {
type HDD_INFO (line 541) | typedef struct {
type BBS_STATUS_FLAGS (line 602) | typedef struct {
type BBS_TABLE (line 623) | typedef struct {
type SMM_ATTRIBUTES (line 760) | typedef struct {
type SMM_FUNCTION (line 811) | typedef struct {
type SMM_ENTRY (line 835) | typedef struct {
type SMM_TABLE (line 861) | typedef struct {
type UDC_ATTRIBUTES (line 869) | typedef struct {
type UD_TABLE (line 895) | typedef struct {
type EFI_TO_COMPATIBILITY16_BOOT_TABLE (line 943) | typedef struct {
type EFI_LEGACY_INSTALL_PCI_HANDLER (line 978) | typedef struct {
type EFI_LEGACY_BIOS_PROTOCOL (line 1013) | typedef struct _EFI_LEGACY_BIOS_PROTOCOL EFI_LEGACY_BIOS_PROTOCOL;
type EFI_EFLAGS_REG (line 1038) | typedef struct {
type EFI_DWORD_REGS (line 1061) | typedef struct {
type EFI_FLAGS_REG (line 1082) | typedef struct {
type EFI_WORD_REGS (line 1103) | typedef struct {
type EFI_BYTE_REGS (line 1133) | typedef struct {
type EFI_IA32_REGISTER_SET (line 1147) | typedef union {
type _EFI_LEGACY_BIOS_PROTOCOL (line 1471) | struct _EFI_LEGACY_BIOS_PROTOCOL {
FILE: src/edk2/LegacyRegion2.h
type EFI_LEGACY_REGION2_PROTOCOL (line 24) | typedef struct _EFI_LEGACY_REGION2_PROTOCOL EFI_LEGACY_REGION2_PROTOCOL;
type EFI_LEGACY_REGION_ATTRIBUTE (line 152) | typedef enum {
type EFI_LEGACY_REGION_DESCRIPTOR (line 162) | typedef struct {
type _EFI_LEGACY_REGION2_PROTOCOL (line 217) | struct _EFI_LEGACY_REGION2_PROTOCOL {
FILE: src/edk2/Pci22.h
type PCI_DEVICE_INDEPENDENT_REGION (line 31) | typedef struct {
type PCI_DEVICE_HEADER_TYPE_REGION (line 48) | typedef struct {
type PCI_TYPE00 (line 67) | typedef struct {
type PCI_BRIDGE_CONTROL_REGISTER (line 76) | typedef struct {
type PCI_TYPE01 (line 105) | typedef struct {
type PCI_TYPE_GENERIC (line 110) | typedef union {
type PCI_CARDBUS_CONTROL_REGISTER (line 119) | typedef struct {
type PCI_CONFIG_ACCESS_CF8 (line 579) | typedef union {
type EFI_PCI_CAPABILITY_HDR (line 657) | typedef struct {
type EFI_PCI_PMC (line 666) | typedef union {
type EFI_PCI_PMCSR (line 686) | typedef union {
type EFI_PCI_PMCSR_BSE (line 709) | typedef union {
type EFI_PCI_CAPABILITY_PMI (line 722) | typedef struct {
type EFI_PCI_CAPABILITY_AGP (line 734) | typedef struct {
type EFI_PCI_CAPABILITY_VPD (line 746) | typedef struct {
type EFI_PCI_CAPABILITY_SLOTID (line 756) | typedef struct {
type EFI_PCI_CAPABILITY_MSI32 (line 766) | typedef struct {
type EFI_PCI_CAPABILITY_MSI64 (line 777) | typedef struct {
type EFI_PCI_CAPABILITY_HOTPLUG (line 789) | typedef struct {
type PCI_EXPANSION_ROM_HEADER (line 818) | typedef struct {
type EFI_LEGACY_EXPANSION_ROM_HEADER (line 828) | typedef struct {
type PCI_DATA_STRUCTURE (line 840) | typedef struct {
type EFI_PCI_EXPANSION_ROM_HEADER (line 859) | typedef struct {
type EFI_PCI_ROM_HEADER (line 871) | typedef union {
FILE: src/edk2/Pci23.h
type EFI_PCI_CAPABILITY_PCIX (line 96) | typedef struct {
type EFI_PCI_CAPABILITY_PCIX_BRDG (line 106) | typedef struct {
type EFI_PCI_CAPABILITY_VENDOR_HDR (line 118) | typedef struct {
FILE: src/edk2/Pci30.h
type PCI_3_0_DATA_STRUCTURE (line 53) | typedef struct {
FILE: src/edk2/PciExpress21.h
type PCI_REG_PCIE_CAPABILITY (line 36) | typedef union {
type PCI_REG_PCIE_DEVICE_CAPABILITY (line 58) | typedef union {
type PCI_REG_PCIE_DEVICE_CONTROL (line 78) | typedef union {
type PCI_REG_PCIE_DEVICE_STATUS (line 114) | typedef union {
type PCI_REG_PCIE_LINK_CAPABILITY (line 128) | typedef union {
type PCI_REG_PCIE_LINK_CONTROL (line 149) | typedef union {
type PCI_REG_PCIE_LINK_STATUS (line 169) | typedef union {
type PCI_REG_PCIE_SLOT_CAPABILITY (line 183) | typedef union {
type PCI_REG_PCIE_SLOT_CONTROL (line 201) | typedef union {
type PCI_REG_PCIE_SLOT_STATUS (line 221) | typedef union {
type PCI_REG_PCIE_ROOT_CONTROL (line 237) | typedef union {
type PCI_REG_PCIE_ROOT_CAPABILITY (line 250) | typedef union {
type PCI_REG_PCIE_ROOT_STATUS (line 258) | typedef union {
type PCI_REG_PCIE_DEVICE_CAPABILITY2 (line 268) | typedef union {
type PCI_REG_PCIE_DEVICE_CONTROL2 (line 309) | typedef union {
type PCI_REG_PCIE_LINK_CAPABILITY2 (line 342) | typedef union {
type PCI_REG_PCIE_LINK_CONTROL2 (line 357) | typedef union {
type PCI_REG_PCIE_LINK_STATUS2 (line 371) | typedef union {
type PCI_REG_PCIE_SLOT_CAPABILITY2 (line 390) | typedef union {
type PCI_CAPABILITY_PCIEXP (line 398) | typedef struct {
type SR_IOV_CAPABILITY_REGISTER (line 442) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER (line 482) | typedef struct {
type PCI_EXPRESS_REG_UNCORRECTABLE_ERROR (line 494) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING (line 520) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC (line 540) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY (line 548) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER (line 562) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION (line 570) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL (line 582) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING (line 592) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED (line 605) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION (line 618) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY (line 626) | typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI...
type PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC (line 631) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER (line 642) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST (line 654) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY (line 668) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL (line 676) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY (line 688) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR (line 693) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY (line 703) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION (line 712) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING (line 724) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH (line 733) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS_CAPABILITY (line 749) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS_CONTROL (line 759) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_ATS (line 768) | typedef struct {
FILE: src/edk2/PciExpress30.h
type PCI_EXPRESS_REG_LINK_CONTROL3 (line 21) | typedef union {
type PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL (line 30) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE (line 42) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_VF_RESIZABLE_BAR_CAPABILITY (line 56) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_VF_RESIZABLE_BAR_CONTROL (line 64) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_VF_RESIZABLE_BAR_ENTRY (line 76) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_VF_RESIZABLE_BAR (line 81) | typedef struct {
FILE: src/edk2/PciExpress31.h
type PCI_EXPRESS_REG_L1_PM_SUBSTATES_CAPABILITY (line 21) | typedef union {
type PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL1 (line 38) | typedef union {
type PCI_EXPRESS_REG_L1_PM_SUBSTATES_CONTROL2 (line 53) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_L1_PM_SUBSTATES (line 63) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CAPABILITY (line 77) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID_CONTROL (line 89) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_PASID (line 99) | typedef struct {
FILE: src/edk2/PciExpress40.h
type PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES (line 35) | typedef union {
type PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL (line 42) | typedef union {
type PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS (line 49) | typedef union {
type PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL (line 61) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0 (line 69) | typedef struct {
type PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 (line 89) | typedef union {
type PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 (line 98) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC (line 105) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_DATA_LINK_FEATURE_CAPABILITY (line 120) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_DATA_LINK_FEATURE_CONTROL (line 129) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_DATA_LINK_FEATURE (line 138) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_LANE_MARGINING_CAPABILITY (line 152) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_LANE_MARGINING_CONTROL (line 160) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_LANE_MARGINING_STATUS (line 169) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_LANE_MARGINING_AT_RECEIVER (line 177) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_PRI_CAPABILITY (line 193) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_PRI_CONTROL (line 208) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_PRI_STATUS (line 217) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_PRI (line 228) | typedef struct {
FILE: src/edk2/PciExpress50.h
type PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES (line 35) | typedef union {
type PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL (line 49) | typedef union {
type PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS (line 60) | typedef union {
type PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1 (line 77) | typedef union {
type PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2 (line 86) | typedef union {
type PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1 (line 95) | typedef union {
type PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2 (line 104) | typedef union {
type PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL (line 113) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0 (line 121) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_ALTERNATE_PROTOCOL (line 141) | typedef struct {
FILE: src/edk2/PciExpress60.h
type PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES (line 38) | typedef union {
type PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL (line 45) | typedef union {
type PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS (line 52) | typedef union {
type PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL (line 67) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_64_0 (line 75) | typedef struct {
type PCI_REG_PCIE_DEVICE_CAPABILITY3 (line 84) | typedef union {
type PCI_REG_PCIE_DEVICE_CONTROL3 (line 97) | typedef union {
type PCI_REG_PCIE_DEVICE_STATUS3 (line 109) | typedef union {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_DEVICE3 (line 119) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_FLIT_LOGGING (line 133) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_DATA_OBJECT_EXCHANGE (line 152) | typedef struct {
type PCI_EXPRESS_EXTENDED_CAPABILITIES_INTEGRITY_DATA_ENCRYPTION (line 171) | typedef struct {
FILE: src/intel_workarounds.c
type pch_info (line 13) | struct pch_info {
function get_pch_info (line 42) | static bool get_pch_info(struct pch_info *info)
function pit_8254cge_workaround (line 110) | static int pit_8254cge_workaround(void)
function apply_intel_platform_workarounds (line 198) | int apply_intel_platform_workarounds(void)
FILE: src/io.h
function clflush (line 10) | static inline void clflush(void *addr) {
function writel (line 26) | static inline void writel(void *addr, uint32_t val) {
function writew (line 30) | static inline void writew(void *addr, uint16_t val) {
function writeb (line 34) | static inline void writeb(void *addr, uint8_t val) {
function readq (line 38) | static inline uint64_t readq(const void *addr) {
function readl (line 43) | static inline uint32_t readl(const void *addr) {
function readw (line 48) | static inline uint16_t readw(const void *addr) {
function readb (line 53) | static inline uint8_t readb(const void *addr) {
function __inbc (line 74) | static inline uint8_t
function __inb (line 82) | static inline uint8_t
function insb (line 90) | static inline void
function __inwc (line 100) | static inline uint16_t
function __inw (line 108) | static inline uint16_t
function insw (line 116) | static inline void
function __inlc (line 126) | static inline uint32_t
function __inl (line 134) | static inline uint32_t
function insl (line 142) | static inline void
function __outbc (line 152) | static inline void
function __outb (line 158) | static inline void
function outsb (line 164) | static inline void
function __outwc (line 174) | static inline void
function __outw (line 180) | static inline void
function outsw (line 186) | static inline void
function __outlc (line 196) | static inline void
function __outl (line 202) | static inline void
function outsl (line 208) | static inline void
function pciSetAddress (line 218) | static inline void pciSetAddress(unsigned int bus, unsigned int slot,
function pciConfigReadByte (line 239) | static inline uint8_t pciConfigReadByte(unsigned int bus, unsigned int s...
function pciConfigReadWord (line 249) | static inline uint16_t pciConfigReadWord(unsigned int bus, unsigned int ...
function pciConfigReadDWord (line 259) | static inline uint32_t pciConfigReadDWord(unsigned int bus, unsigned int...
function pciConfigWriteByte (line 266) | static inline void pciConfigWriteByte(unsigned int bus, unsigned int slot,
function pciConfigWriteWord (line 277) | static inline void pciConfigWriteWord(unsigned int bus, unsigned int slot,
function pciConfigWriteDWord (line 288) | static inline void pciConfigWriteDWord(unsigned int bus, unsigned int slot,
function rdmsr (line 296) | static inline uint64_t rdmsr(uint32_t index) {
function wrmsr (line 302) | static inline void wrmsr(uint32_t index, uint64_t val) {
function rdtsc (line 306) | static inline uint64_t rdtsc(void) {
FILE: src/iommu.c
type dmar_header (line 28) | struct dmar_header {
type dmar_drhd (line 33) | struct dmar_drhd {
type acpi_ivrs (line 76) | struct acpi_ivrs {
type ivrs_header (line 82) | struct ivrs_header {
function vtd_disable_unit (line 118) | static bool vtd_disable_unit(uint64_t reg_base) {
function vtd_disable_all (line 173) | static int vtd_disable_all(void) {
function amd_iommu_disable_unit (line 220) | static bool amd_iommu_disable_unit(uint64_t iommu_base) {
function amd_iommu_disable_all (line 260) | static int amd_iommu_disable_all(void) {
function iommu_disable (line 307) | bool iommu_disable(void) {
FILE: src/libc.c
function memcmp (line 55) | int memcmp(const void *s1, const void *s2, size_t n) {
FILE: src/mptable.c
type pci_bus_info (line 59) | struct pci_bus_info {
type pci_bus_info (line 67) | struct pci_bus_info
function pci_device_exists (line 75) | static bool pci_device_exists(uint8_t bus, uint8_t dev, uint8_t func)
type mptable_floating (line 85) | struct mptable_floating {
type mptable_config (line 96) | struct mptable_config {
type mpt_cpu (line 112) | struct mpt_cpu {
type mpt_bus (line 122) | struct mpt_bus {
type mpt_ioapic (line 128) | struct mpt_ioapic {
type mpt_intsrc (line 136) | struct mpt_intsrc {
type madt_data (line 152) | struct madt_data {
function compute_checksum (line 182) | static uint8_t compute_checksum(void *data, size_t len)
function get_bsp_apic_id (line 193) | static uint32_t get_bsp_apic_id(void)
function get_cpu_info (line 204) | static void get_cpu_info(uint32_t *signature, uint32_t *features)
function get_lapic_version (line 213) | static uint8_t get_lapic_version(void)
function madt_flags_to_mp (line 224) | static uint16_t madt_flags_to_mp(uint16_t madt_flags)
function parse_madt (line 259) | static bool parse_madt(struct madt_data *data, int helper_apic_id)
function find_ioapic_for_gsi (line 397) | static int find_ioapic_for_gsi(struct madt_data *data, uint32_t gsi, uin...
function ioapic_read (line 411) | static uint32_t ioapic_read(uint32_t ioapic_addr, uint8_t reg)
function get_ioapic_version (line 421) | static uint8_t get_ioapic_version(uint32_t ioapic_addr)
function get_ioapic_input_count (line 427) | static uint8_t get_ioapic_input_count(uint32_t ioapic_addr)
type irq_find_ctx (line 436) | struct irq_find_ctx {
function uacpi_flags_to_madt (line 442) | static uint16_t uacpi_flags_to_madt(uint8_t triggering, uint8_t polarity)
function uacpi_iteration_decision (line 451) | static uacpi_iteration_decision find_irq_callback(void *user, uacpi_reso...
function get_link_device_gsi (line 473) | static int32_t get_link_device_gsi(uacpi_namespace_node *link, uint16_t ...
function uacpi_iteration_decision (line 492) | static uacpi_iteration_decision discover_pci_bus_callback(
function uacpi_iteration_decision (line 523) | static uacpi_iteration_decision discover_secondary_callback(
function discover_secondary_buses (line 567) | static void discover_secondary_buses(uacpi_namespace_node *root_bridge, ...
function discover_pci_buses (line 581) | static void discover_pci_buses(void)
function mptable_init (line 615) | bool mptable_init(struct csmwrap_priv *priv)
FILE: src/mptable.h
type csmwrap_priv (line 14) | struct csmwrap_priv
type csmwrap_priv (line 22) | struct csmwrap_priv
FILE: src/oprom.c
function EFI_STATUS (line 13) | EFI_STATUS
function oprom_enumerate (line 137) | void oprom_enumerate(struct csmwrap_priv *priv, struct pci_oprom_list *l...
function oprom_dispatch_all (line 214) | void oprom_dispatch_all(struct csmwrap_priv *priv, struct pci_oprom_list...
FILE: src/oprom.h
type pci_oprom_info (line 11) | struct pci_oprom_info {
type pci_oprom_list (line 21) | struct pci_oprom_list {
type csmwrap_priv (line 30) | struct csmwrap_priv
type pci_oprom_list (line 30) | struct pci_oprom_list
type csmwrap_priv (line 37) | struct csmwrap_priv
type pci_oprom_list (line 37) | struct pci_oprom_list
FILE: src/pci.c
type flanterm_context (line 10) | struct flanterm_context
type ecam_region (line 24) | struct ecam_region {
type ecam_region (line 31) | struct ecam_region
type ecam_region (line 35) | struct ecam_region
type ecam_region (line 37) | struct ecam_region
type ecam_region (line 50) | struct ecam_region
type pci_address (line 50) | struct pci_address
function pci_read_pio (line 59) | static uint32_t pci_read_pio(struct pci_address *address, uint32_t offse...
function pci_write_pio (line 73) | static void pci_write_pio(struct pci_address *address, uint32_t offset, ...
function pci_read_ecam (line 84) | static uint32_t pci_read_ecam(struct pci_address *address, uint32_t offs...
function pci_write_ecam (line 98) | static void pci_write_ecam(struct pci_address *address, uint32_t offset,...
type pci_address (line 113) | struct pci_address
type pci_address (line 114) | struct pci_address
function pci_read_config_space (line 119) | uint32_t pci_read_config_space(struct pci_address *address, uint32_t off...
function pci_write_config_space (line 123) | void pci_write_config_space(struct pci_address *address, uint32_t offset...
function pci_enable_for_oprom (line 127) | void pci_enable_for_oprom(uint8_t bus, uint8_t devfn) {
function parse_mcfg_table (line 139) | static bool parse_mcfg_table(void) {
function pci_find_ext_capability (line 191) | static uint16_t pci_find_ext_capability(struct pci_address *address, uin...
function pci_rebar_apply_quirks (line 219) | static uint32_t pci_rebar_apply_quirks(uint16_t vendor, uint16_t device,
function pci_try_resize_bar (line 236) | static uint64_t pci_try_resize_bar(struct pci_address *address, uint8_t ...
type pci_bus (line 328) | struct pci_bus
type pci_bus (line 333) | struct pci_bus
type pci_bus (line 336) | struct pci_bus
type pci_device (line 345) | struct pci_device
type pci_device (line 348) | struct pci_device
type pci_bar (line 357) | struct pci_bar
type pci_bar (line 360) | struct pci_bar
function add_root_bus (line 367) | static bool add_root_bus(struct pci_bus *bus) {
type pci_range (line 377) | struct pci_range
type pci_bus (line 377) | struct pci_bus
function drop_range (line 410) | static bool drop_range(struct pci_bus *bus, struct pci_range *range) {
function add_device (line 416) | static bool add_device(struct pci_bus *bus, struct pci_device *device) {
function add_bar (line 426) | static bool add_bar(struct pci_bus *bus, struct pci_bar *bar) {
function drop_bar (line 446) | static bool drop_bar(struct pci_bus *bus, struct pci_bar *bar) {
function is_address_in_prefetchable_range (line 464) | static bool is_address_in_prefetchable_range(struct pci_bus *bus, uint64...
function compare_bars (line 477) | static int compare_bars(const void *a, const void *b) {
function sort_bars (line 487) | static void sort_bars(struct pci_bus *bus) {
type pci_bus (line 502) | struct pci_bus
function reallocate_single_bar (line 506) | static void reallocate_single_bar(struct pci_bus *bus, struct pci_bar *b...
function reallocate_bars (line 683) | static void reallocate_bars(struct pci_bus *bus) {
function scan_bars (line 689) | static bool scan_bars(struct pci_device *device) {
type pci_bus (line 914) | struct pci_bus
function scan_function (line 916) | static bool scan_function(struct pci_bus *bus, struct pci_address *addre...
function scan_slot (line 979) | static bool scan_slot(struct pci_bus *bus, struct pci_address *address) {
function scan_bus (line 1014) | static bool scan_bus(struct pci_bus *bus) {
function pretty_print_bus (line 1030) | static void pretty_print_bus(struct pci_bus *bus, int indent) {
function uacpi_iteration_decision (line 1084) | static uacpi_iteration_decision uacpi_discover_root_bus(void *user, uacp...
function uacpi_discover_root_bridges (line 1173) | static bool uacpi_discover_root_bridges(void) {
function pci_get_extra_root_buses (line 1193) | size_t pci_get_extra_root_buses(uint8_t *out, size_t cap) {
function pci_early_initialize (line 1210) | bool pci_early_initialize(void) {
function has_bars_above_4g (line 1243) | static bool has_bars_above_4g(struct pci_bus *bus) {
function resize_bridge_windows (line 1264) | static bool resize_bridge_windows(struct pci_bus *bus) {
function pci_late_initialize (line 1355) | bool pci_late_initialize(void) {
FILE: src/pci.h
type pci_address (line 8) | struct pci_address {
type pci_range (line 15) | struct pci_range {
type pci_device_type (line 22) | enum pci_device_type {
type pci_device (line 27) | struct pci_device {
type pci_bar (line 44) | struct pci_bar {
type pci_bus (line 71) | struct pci_bus {
type pci_address (line 104) | struct pci_address
type pci_address (line 107) | struct pci_address
FILE: src/pir.c
type pir_link_info (line 40) | struct pir_link_info {
type pir_slot (line 45) | struct pir_slot {
type pir_header (line 53) | struct pir_header {
type pci_bus_info (line 67) | struct pci_bus_info {
type pci_bus_info (line 73) | struct pci_bus_info
type pir_slot (line 77) | struct pir_slot
type link_device_entry (line 80) | struct link_device_entry {
type link_device_entry (line 87) | struct link_device_entry
function pci_device_exists (line 92) | static bool pci_device_exists(uint8_t bus, uint8_t dev, uint8_t func)
function uacpi_iteration_decision (line 101) | static uacpi_iteration_decision discover_root_bus_callback(
function uacpi_iteration_decision (line 126) | static uacpi_iteration_decision discover_secondary_callback(
function discover_secondary_buses (line 159) | static void discover_secondary_buses(uacpi_namespace_node *root_bridge,
function discover_pci_buses (line 171) | static void discover_pci_buses(void)
function find_isa_bridge (line 194) | static bool find_isa_bridge(uint8_t *out_bus, uint8_t *out_devfn)
type pir_slot (line 223) | struct pir_slot
type pir_slot (line 232) | struct pir_slot
type prs_ctx (line 241) | struct prs_ctx {
function uacpi_iteration_decision (line 245) | static uacpi_iteration_decision link_prs_callback(void *user,
function get_link_id (line 267) | static uint8_t get_link_id(uacpi_namespace_node *link, uint16_t *bitmap_...
function pir_init (line 295) | bool pir_init(struct csmwrap_priv *priv)
FILE: src/pir.h
type csmwrap_priv (line 18) | struct csmwrap_priv
FILE: src/printf.c
type flanterm_context (line 23) | struct flanterm_context
function serial_protocol_initialise (line 29) | static void serial_protocol_initialise(void) {
function serial_direct_io_initialise (line 53) | static void serial_direct_io_initialise(void) {
function serial_out (line 77) | static void serial_out(uint8_t b) {
function _putchar (line 96) | static void _putchar(int character, void *extra_arg) {
function printf (line 112) | int printf(const char *restrict fmt, ...) {
function vprintf (line 120) | int vprintf(const char *restrict fmt, va_list l) {
function snprintf (line 124) | int snprintf(char *buffer, size_t bufsz, const char *restrict fmt, ...) {
FILE: src/printf.h
type flanterm_context (line 8) | struct flanterm_context
FILE: src/qsort.c
function swap (line 4) | static void swap(void* a, void* b, size_t size) {
function partition (line 19) | static int partition(void* base, size_t size, int (*cmp)(const void*, co...
function quick_sort (line 35) | static void quick_sort(void* base, size_t size, int (*cmp)(const void*, ...
function qsort (line 44) | void qsort(void* ptr, size_t count, size_t size, int (*comp)(const void*...
FILE: src/time.c
function tsc_freq_from_cpuid (line 13) | static uint64_t tsc_freq_from_cpuid(void) {
function calibrate_tsc (line 36) | void calibrate_tsc(void) {
function get_nanoseconds_since_boot (line 49) | uint64_t get_nanoseconds_since_boot(void) {
function stall (line 58) | void stall(uint64_t us) {
FILE: src/unlock_region.c
function EFI_STATUS (line 78) | EFI_STATUS unlock_legacy_region_protocol(void)
function unlock_piix4_pam (line 140) | int unlock_piix4_pam(void)
function unlock_q35_pam (line 161) | int unlock_q35_pam(void)
function unlock_sandybridge_pam (line 184) | int unlock_sandybridge_pam(void)
function unlock_amd_mtrr (line 211) | int unlock_amd_mtrr(void)
function EFI_STATUS (line 266) | EFI_STATUS print_legacy_region_info(EFI_LEGACY_REGION2_PROTOCOL *legacy_...
function test_bios_region_rw (line 322) | static bool test_bios_region_rw(void) {
function unlock_bios_region (line 352) | int unlock_bios_region(void)
FILE: src/video.c
function linear_masks_to_bpp (line 21) | static uint16_t linear_masks_to_bpp(uint32_t red_mask, uint32_t green_mask,
function gop_mode_usable (line 38) | static bool gop_mode_usable(EFI_GRAPHICS_OUTPUT_PROTOCOL *Gop)
function EFI_STATUS (line 67) | static EFI_STATUS FindGop(struct csmwrap_priv *priv)
function PopulateVgaPciInfo (line 155) | static void PopulateVgaPciInfo(struct csmwrap_priv *priv, EFI_PCI_IO_PRO...
function EFI_STATUS (line 181) | static EFI_STATUS FindPciDevice(uint8_t bus, uint8_t device, uint8_t fun...
function EFI_STATUS (line 224) | static EFI_STATUS FindVgaPciInfo(struct csmwrap_priv *priv)
function EFI_STATUS (line 269) | static EFI_STATUS csmwrap_pci_vgaarb(EFI_PCI_IO_PROTOCOL *PciIo)
function EFI_STATUS (line 328) | static EFI_STATUS try_gpu_oprom(struct csmwrap_priv *priv, EFI_PCI_IO_PR...
function EFI_STATUS (line 391) | static EFI_STATUS csmwrap_video_oprom_init(struct csmwrap_priv *priv)
function EFI_STATUS (line 477) | static EFI_STATUS csmwrap_video_seavgabios_init(struct csmwrap_priv *priv)
function EFI_STATUS (line 610) | EFI_STATUS csmwrap_video_prepare_exitbs(struct csmwrap_priv *priv)
function is_amd_vega_apu (line 658) | static bool is_amd_vega_apu(uint16_t device_id)
function is_amd_rdna_or_newer (line 682) | static bool is_amd_rdna_or_newer(uint16_t vendor_id, uint16_t device_id)
function csmwrap_video_early_init (line 717) | void csmwrap_video_early_init(struct csmwrap_priv *priv) {
function FindVgaGop (line 737) | static void FindVgaGop(struct csmwrap_priv *priv)
function EFI_STATUS (line 785) | EFI_STATUS csmwrap_video_init(struct csmwrap_priv *priv)
FILE: src/video.h
type csmwrap_priv (line 11) | struct csmwrap_priv
type csmwrap_priv (line 12) | struct csmwrap_priv
type csmwrap_priv (line 14) | struct csmwrap_priv
FILE: src/x86thunk.c
function AsmGetThunk16Properties (line 63) | void AsmGetThunk16Properties (uint32_t *RealModeBufferSize, uint32_t *E...
function AsmPrepareThunk16 (line 90) | void AsmPrepareThunk16 (THUNK_CONTEXT *ThunkContext)
function AsmThunk16 (line 204) | void AsmThunk16 (THUNK_CONTEXT *ThunkContext)
function AsmPrepareAndThunk16 (line 245) | void AsmPrepareAndThunk16 (THUNK_CONTEXT *ThunkContext)
function InternalLegacyBiosFarCall (line 253) | bool InternalLegacyBiosFarCall (uint16_t Segment, uint16_t Offset, EFI_I...
function LegacyBiosInitializeThunkAndTable (line 439) | uintptr_t LegacyBiosInitializeThunkAndTable(uintptr_t MemoryAddress, siz...
function LegacyBiosInt86 (line 455) | bool LegacyBiosInt86(uint8_t BiosInt, EFI_IA32_REGISTER_SET *Regs)
function LegacyBiosFarCall86 (line 509) | bool LegacyBiosFarCall86 (uint16_t Segment, uint16_t Offset, EFI_IA32_RE...
FILE: src/x86thunk.h
type IA32_EFLAGS32 (line 24) | typedef union {
type IA32_IDT_GATE_DESCRIPTOR (line 55) | typedef union {
type IA32_TASK_STATE_SEGMENT (line 75) | typedef struct {
type IA32_TSS_DESCRIPTOR (line 87) | typedef union {
type IA32_FX_BUFFER (line 113) | typedef struct {
type IA32_BYTE_REGS (line 120) | typedef struct {
type IA32_WORD_REGS (line 139) | typedef struct {
type IA32_DWORD_REGS (line 158) | typedef struct {
type IA32_REGISTER_SET (line 177) | typedef union {
type IA32_SEGMENT_DESCRIPTOR (line 183) | typedef union {
type THUNK_CONTEXT (line 205) | typedef struct {
type GDT64 (line 225) | typedef struct {
type DESCRIPTOR64 (line 238) | typedef struct {
type DESCRIPTOR32 (line 243) | typedef struct {
type LOW_MEMORY_THUNK (line 256) | typedef struct {
Condensed preview — 80 files, each showing path, character count, and a content snippet. Download the .json file or copy for the full structured content (1,509K chars).
[
{
"path": ".github/dependabot.yml",
"chars": 139,
"preview": "version: 2\nupdates:\n - package-ecosystem: github-actions\n directory: \"/\"\n schedule:\n interval: \"daily\"\n t"
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"chars": 1281,
"preview": "name: Build\n\non:\n push:\n branches: ['**']\n tags: ['[0-9]*']\n pull_request:\n workflow_dispatch:\n\njobs:\n build:\n"
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{
"path": ".gitignore",
"chars": 72,
"preview": "/compile_commands.json\n/.cache\n/boot\n/edk2-ovmf\n/src/bins\n/bin-*\n/obj-*\n"
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{
"path": ".gitmodules",
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"preview": "[submodule \"freestnd-c-hdrs\"]\n\tpath = freestnd-c-hdrs\n\turl = https://github.com/osdev0/freestnd-c-hdrs-0bsd.git\n[submodu"
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{
"path": "GNUmakefile",
"chars": 8687,
"preview": "# Nuke built-in rules.\n.SUFFIXES:\n\n# This is the name that our final executable will have.\n# Change as needed.\noverride "
},
{
"path": "LICENSE",
"chars": 26526,
"preview": " GNU LESSER GENERAL PUBLIC LICENSE\n Version 2.1, February 1999\n\n Copyright (C) 19"
},
{
"path": "README.md",
"chars": 9469,
"preview": "<h1 align=\"center\">CSMWrap</h1>\n\n<p align=\"center\">\n <a href=\"https://github.com/CSMWrap/CSMWrap/actions/workflows/bu"
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{
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"chars": 125,
"preview": "CONFIG_CSM=y\n# CONFIG_FLASH_FLOPPY is not set\n# CONFIG_VGAHOOKS is not set\n# CONFIG_TCGBIOS is not set\nCONFIG_VGA_COREBO"
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{
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"chars": 11527,
"preview": "#include <efi.h>\n#include <io.h>\n#include <pci.h>\n#include <printf.h>\n#include <time.h>\n#include \"csmwrap.h\"\n\n#include <"
},
{
"path": "src/ap_trampoline.asm",
"chars": 8087,
"preview": "; AP Trampoline for BIOS Proxy Helper Core\n; This code is copied to 0x7000 and runs when an AP wakes from SIPI\n; AP star"
},
{
"path": "src/apic.c",
"chars": 16669,
"preview": "/*\n * APIC handling for legacy BIOS compatibility\n *\n * Modern UEFI systems boot with x2APIC enabled, which prevents leg"
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{
"path": "src/apic.h",
"chars": 413,
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},
{
"path": "src/arch/ia32/Thunk16.asm",
"chars": 9474,
"preview": ";------------------------------------------------------------------------------\n;\n; Copyright (c) 2006 - 2013, Intel Cor"
},
{
"path": "src/arch/x86_64/Thunk16.asm",
"chars": 12248,
"preview": ";------------------------------------------------------------------------------\n;\n; Copyright (c) 2006 - 2018, Intel Cor"
},
{
"path": "src/bios_proxy.c",
"chars": 25587,
"preview": "/*\n * BIOS Proxy Helper Core Support\n *\n * Starts a dedicated CPU core to handle BIOS calls when the main core\n * is run"
},
{
"path": "src/bios_proxy.h",
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"preview": "/*\n * BIOS Proxy Helper Core Support\n *\n * Provides a dedicated CPU core to handle BIOS calls when the main core\n * is r"
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{
"path": "src/bootdev.c",
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{
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"chars": 1313,
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{
"path": "src/config.c",
"chars": 19193,
"preview": "#include <stddef.h>\n#include <stdbool.h>\n#include <stdint.h>\n\n#include <efi.h>\n#include <csmwrap.h>\n#include <config.h>\n"
},
{
"path": "src/config.h",
"chars": 1790,
"preview": "#ifndef CONFIG_H\n#define CONFIG_H\n\n#include <stddef.h>\n#include <stdbool.h>\n#include <stdint.h>\n#include <efi.h>\n\n#defin"
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{
"path": "src/coreboot.c",
"chars": 1705,
"preview": "#include <efi.h>\n#include \"csmwrap.h\"\n\nstatic UINT16\nCbCheckSum16 (\n IN UINT16 *Buffer,\n IN UINTN Length\n )\n{\n UI"
},
{
"path": "src/csmwrap.c",
"chars": 32187,
"preview": "#include <stdarg.h>\n\n#include <efi.h>\n#include <csmwrap.h>\n\n#include <io.h>\n#include <x86thunk.h>\n#include <video.h>\n#in"
},
{
"path": "src/csmwrap.h",
"chars": 4113,
"preview": "#ifndef _CSM_WRAP_H\n#define _CSM_WRAP_H\n\n#include <efi.h>\n#include <edk2/Acpi.h>\n#include <edk2/LegacyBios.h>\n#include <"
},
{
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"chars": 13258,
"preview": "#include <efi.h>\n\n#include <printf.h>\n#include \"csmwrap.h\"\n#include \"io.h\"\n\n/* This is not in E820.h */\n#define EfiAcpiA"
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{
"path": "src/edk2/Acpi.h",
"chars": 469,
"preview": "/** @file\n This file contains the latest ACPI definitions that are\n consumed by drivers that do not care about ACPI ve"
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{
"path": "src/edk2/Acpi10.h",
"chars": 19558,
"preview": "/** @file\n ACPI 1.0b definitions from the ACPI Specification, revision 1.0b\n\nCopyright (c) 2006 - 2018, Intel Corporati"
},
{
"path": "src/edk2/Acpi20.h",
"chars": 15940,
"preview": "/** @file\n ACPI 2.0 definitions from the ACPI Specification, revision 2.0\n\n Copyright (c) 2006 - 2018, Intel Corporati"
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{
"path": "src/edk2/Acpi30.h",
"chars": 22827,
"preview": "/** @file\n ACPI 3.0 definitions from the ACPI Specification Revision 3.0b October 10, 2006\n\n Copyright (c) 2006 - 2018"
},
{
"path": "src/edk2/Acpi40.h",
"chars": 43074,
"preview": "/** @file\n ACPI 4.0 definitions from the ACPI Specification Revision 4.0a April 5, 2010\n\n Copyright (c) 2010 - 2022, I"
},
{
"path": "src/edk2/Acpi50.h",
"chars": 70684,
"preview": "/** @file\n ACPI 5.0 definitions from the ACPI Specification Revision 5.0a November 13, 2013.\n\n Copyright (c) 2014 Hewl"
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{
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"chars": 70385,
"preview": "/** @file\n ACPI 5.1 definitions from the ACPI Specification Revision 5.1 Errata B January, 2016.\n\n Copyright (c) 2014 "
},
{
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"chars": 81458,
"preview": "/** @file\n ACPI 6.0 definitions from the ACPI Specification Revision 6.0 Errata A January, 2016.\n\n Copyright (c) 2015 "
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"preview": "/** @file\n ACPI 6.3 definitions from the ACPI Specification Revision 6.3 Jan, 2019.\n\n Copyright (c) 2017 - 2022, Intel"
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"preview": "/** @file\n ACPI 6.4 definitions from the ACPI Specification Revision 6.4 Jan, 2021.\n\n Copyright (c) 2017 - 2022, Intel"
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"preview": "/** @file\n ACPI 6.5 definitions from the ACPI Specification Revision 6.5 Aug, 2022.\n\n Copyright (c) 2017 - 2022, Intel"
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"preview": "/** @file\n This file contains AML code definition in the latest ACPI spec.\n\n Copyright (c) 2011, Intel Corporation. Al"
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{
"path": "src/edk2/Coreboot.h",
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"preview": "/** @file\n Coreboot PEI module include file.\n\n Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\n"
},
{
"path": "src/edk2/E820.h",
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"preview": "/** @file\n\nCopyright (c) 2013, Citrix Systems UK Ltd.\nCopyright (c) 2006 - 2013, Intel Corporation. All rights reserved."
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{
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"preview": "#ifndef _EDK2_COMPAT_H_\n#define _EDK2_COMPAT_H_\n\n#include <efi.h>\n\n/* Packed is already handled by pragmas */\n#define PA"
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{
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"preview": "/** @file\n The EFI Legacy BIOS Protocol is used to abstract legacy Option ROM usage\n under EFI and Legacy OS boot. Th"
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{
"path": "src/edk2/LegacyRegion2.h",
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"preview": "/** @file\n Support for PCI 2.3 standard.\n\n Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\n SP"
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{
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"preview": "/** @file\n Support for PCI 3.0 standard.\n\n Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\n SP"
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{
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"preview": "/** @file\n The file lists the PCI class codes only defined in PCI code and ID assignment specification\n revision 1.3.\n"
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{
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"preview": "/** @file\n Support for the latest PCI standard.\n\n Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<B"
},
{
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"chars": 2826,
"preview": "/** @file\n Support for the PCI Express 3.0 standard.\n\n This header file may not define all structures. Please extend "
},
{
"path": "src/edk2/PciExpress31.h",
"chars": 3235,
"preview": "/** @file\nSupport for the PCI Express 3.1 standard.\n\nThis header file may not define all structures. Please extend as r"
},
{
"path": "src/edk2/PciExpress40.h",
"chars": 8574,
"preview": "/** @file\nSupport for the PCI Express 4.0 standard.\n\nThis header file may not define all structures. Please extend as r"
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{
"path": "src/edk2/PciExpress50.h",
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"preview": "/** @file\nSupport for the PCI Express 5.0 standard.\n\nThis header file may not define all structures. Please extend as r"
},
{
"path": "src/edk2/PciExpress60.h",
"chars": 7104,
"preview": "/** @file\nSupport for the PCI Express 6.0 standard.\n\nThis header file may not define all structures. Please extend as r"
},
{
"path": "src/intel_workarounds.c",
"chars": 6782,
"preview": "#include <efi.h>\n#include \"csmwrap.h\"\n\n#include \"io.h\"\n\n#define PCI_DEVICE_NUMBER_PCH_P2SB 31\n#define PC"
},
{
"path": "src/io.h",
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"preview": "#ifndef _IO_H\n#define _IO_H\n\n#include <efi.h>\n#include <printf.h>\n#include <stdbool.h>\n\n#define barrier() __asm__ __vola"
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{
"path": "src/iommu.c",
"chars": 9674,
"preview": "#include <efi.h>\n#include <printf.h>\n\n#include \"csmwrap.h\"\n#include \"io.h\"\n#include \"iommu.h\"\n\n#include <uacpi/acpi.h>\n#"
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{
"path": "src/iommu.h",
"chars": 506,
"preview": "#ifndef IOMMU_H\n#define IOMMU_H\n\n#include <stdbool.h>\n\n/*\n * Disable all IOMMUs (Intel VT-d and AMD-Vi) to allow legacy "
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{
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"preview": "#include <stdint.h>\n#include <stddef.h>\n#include <libc.h>\n\n#ifdef memcpy\n# undef memcpy\n#endif\nvoid *memcpy(void *restr"
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"preview": "#ifndef LIBC_H\n#define LIBC_H\n\n#include <stddef.h>\n\nvoid *memcpy(void *restrict dest, const void *restrict src, size_t n"
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{
"path": "src/mptable.c",
"chars": 32706,
"preview": "/*\n * MP Table Generation from ACPI\n *\n * Generates Intel MultiProcessor Specification tables from ACPI MADT\n * for lega"
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{
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{
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"preview": "#include <efi.h>\n#include <csmwrap.h>\n#include <oprom.h>\n#include <pci.h>\n#include <video.h>\n#include <config.h>\n#includ"
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{
"path": "src/oprom.h",
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{
"path": "src/pci.c",
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{
"path": "src/pci.h",
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"preview": "#include <efi.h>\n#include <csmwrap.h>\n#include <io.h>\n#include <time.h>\n\nuint64_t tsc_freq; /* TSC ticks per se"
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{
"path": "src/time.h",
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{
"path": "src/uacpi_config.h",
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{
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"path": "src/video.c",
"chars": 27449,
"preview": "#include <efi.h>\n#include <video.h>\n#include <csmwrap.h>\n#include <oprom.h>\n#include <config.h>\n#include <io.h>\n\n// Gene"
},
{
"path": "src/video.h",
"chars": 339,
"preview": "#ifndef VIDEO_H\n#define VIDEO_H\n\n#include <stdint.h>\n#include <efi.h>\n#include <csmwrap.h>\n\nextern void *vbios_loc;\nexte"
},
{
"path": "src/x86thunk.c",
"chars": 19075,
"preview": "/*\n * Real Mode Thunk Functions for IA32 and x64.\n *\n * Based on EDK2: MdePkg/Library/BaseLib/X86Thunk.c\n *\n * Which is:"
},
{
"path": "src/x86thunk.h",
"chars": 8055,
"preview": "/*\n * Real Mode Thunk Functions for IA32 and x64.\n *\n * Based on various EDK2 headers\n *\n * Which is:\n * Copyright (c) 2"
}
]
About this extraction
This page contains the full source code of the FlyGoat/CSMWrap GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 80 files (1.4 MB), approximately 382.3k tokens, and a symbol index with 1703 extracted functions, classes, methods, constants, and types. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.
Extracted by GitExtract — free GitHub repo to text converter for AI. Built by Nikandr Surkov.