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Repository: Ttl/vna2
Branch: master
Commit: 2cf0efb22da5
Files: 142
Total size: 3.3 MB
Directory structure:
gitextract_0z82hq_s/
├── README
├── couplers/
│ ├── README
│ └── gerbers/
│ ├── rf_bridge_Bottom.gbl
│ ├── rf_bridge_In1.g2l
│ ├── rf_bridge_In2.g3l
│ ├── rf_bridge_Mask.gts
│ ├── rf_bridge_Mask_bottom.gbs
│ ├── rf_bridge_Outline.gko
│ ├── rf_bridge_Top.gtl
│ └── rf_bridge_drill.drl
├── fpga/
│ ├── vna/
│ │ ├── vna.hw/
│ │ │ └── vna.lpr
│ │ ├── vna.srcs/
│ │ │ ├── constrs_1/
│ │ │ │ └── new/
│ │ │ │ └── vna_constraints.xdc
│ │ │ ├── sim_1/
│ │ │ │ └── new/
│ │ │ │ ├── comm_tb.vhd
│ │ │ │ ├── ft2232_behavioral.vhd
│ │ │ │ ├── io_bank_tb.vhd
│ │ │ │ ├── iq_packer_tb.vhd
│ │ │ │ ├── lo_sim.vhd
│ │ │ │ ├── mixer_sim.vhd
│ │ │ │ ├── receiver_tb.vhd
│ │ │ │ ├── spi3_tb.vhd
│ │ │ │ ├── spi_write_tb.vhd
│ │ │ │ ├── vna_tb.vhd
│ │ │ │ └── vna_top_tb.vhd
│ │ │ └── sources_1/
│ │ │ ├── imports/
│ │ │ │ └── new/
│ │ │ │ ├── downconvert.vhd
│ │ │ │ ├── port_switch.vhd
│ │ │ │ ├── sample_packer.vhd
│ │ │ │ ├── spi3.vhd
│ │ │ │ └── vna_top.vhd
│ │ │ └── new/
│ │ │ ├── acc_control.vhd
│ │ │ ├── accumulator.vhd
│ │ │ ├── comm.vhd
│ │ │ ├── dither.vhd
│ │ │ ├── file_adc.vhd
│ │ │ ├── io_bank.vhd
│ │ │ ├── iq_packer.vhd
│ │ │ ├── lfsr.vhd
│ │ │ ├── lo.vhd
│ │ │ ├── mixer.vhd
│ │ │ ├── pwr_sync_gen.vhd
│ │ │ ├── receiver.vhd
│ │ │ ├── receiver_control.vhd
│ │ │ ├── rx_sw_mux.vhd
│ │ │ ├── rx_switch.vhd
│ │ │ ├── source_agc.vhd
│ │ │ ├── spi_write.vhd
│ │ │ ├── tx_mux.vhd
│ │ │ └── vna_pkg.vhd
│ │ └── vna.xpr
│ └── vna_top.bit
├── hw/
│ ├── adc.sch
│ ├── filter_bank.sch
│ ├── fpga.sch
│ ├── fpga_power.sch
│ ├── if_amp.sch
│ ├── lib/
│ │ └── vna.lib
│ ├── lmz30602.sch
│ ├── microcontroller.sch
│ ├── port_switch.sch
│ ├── power.sch
│ ├── receiver.sch
│ ├── rx_lna.sch
│ ├── rx_switch.sch
│ ├── transmitter.sch
│ ├── tx_amp.sch
│ ├── usb.sch
│ ├── vna.pretty/
│ │ ├── 1748LP18A075.kicad_mod
│ │ ├── 3550LP14A300.kicad_mod
│ │ ├── 5400BL15B050E.kicad_mod
│ │ ├── 5515LP15A730.kicad_mod
│ │ ├── ABMM.kicad_mod
│ │ ├── ASTRX-12.kicad_mod
│ │ ├── CNC-3220-10-0300-00.kicad_mod
│ │ ├── CONSMA003.062.kicad_mod
│ │ ├── CTX520.kicad_mod
│ │ ├── C_0402b.kicad_mod
│ │ ├── C_0603b.kicad_mod
│ │ ├── C_0805b.kicad_mod
│ │ ├── DFN-8-1EP_2x2mm_Pitch0.5mm.kicad_mod
│ │ ├── DFN-8.kicad_mod
│ │ ├── EJ508A.kicad_mod
│ │ ├── EVP-AWBA2A.kicad_mod
│ │ ├── FTG256.kicad_mod
│ │ ├── KT2520K.kicad_mod
│ │ ├── LED_0603.kicad_mod
│ │ ├── LP0603A0902.kicad_mod
│ │ ├── MLPD-10.kicad_mod
│ │ ├── MSOP-8.kicad_mod
│ │ ├── MountingHole_3.2mm_M3_Pad_Via_mod.kicad_mod
│ │ ├── PAT1220.kicad_mod
│ │ ├── RF_via.kicad_mod
│ │ ├── R_0402b.kicad_mod
│ │ ├── R_0603b.kicad_mod
│ │ ├── S2711-46R.kicad_mod
│ │ ├── SC-70-6.kicad_mod
│ │ ├── SG-210STF.kicad_mod
│ │ ├── SOD-123F.kicad_mod
│ │ ├── SOT-23-5.kicad_mod
│ │ ├── SOT-23-5L.kicad_mod
│ │ ├── SOT-23-6.kicad_mod
│ │ ├── SOT-416.kicad_mod
│ │ ├── SRN4018.kicad_mod
│ │ ├── SRR6040A.kicad_mod
│ │ ├── SSOP-16.kicad_mod
│ │ ├── SSOT-6.kicad_mod
│ │ ├── TCM1-63AX+.kicad_mod
│ │ ├── TFBGA-100.kicad_mod
│ │ ├── TFLGA-20.kicad_mod
│ │ ├── TP_1.00.kicad_mod
│ │ ├── TQFN-32.kicad_mod
│ │ ├── TSOT-23.kicad_mod
│ │ ├── USB_MICRO.kicad_mod
│ │ ├── VFQFN-16.kicad_mod
│ │ ├── VFQFN-24.kicad_mod
│ │ ├── VFQFN-32.kicad_mod
│ │ ├── VQFN-16.kicad_mod
│ │ ├── VQFN-24.kicad_mod
│ │ ├── WFBGA-6.kicad_mod
│ │ ├── WFDFN-8.kicad_mod
│ │ ├── XDFN-2.kicad_mod
│ │ ├── XFDFN-6.kicad_mod
│ │ ├── XTAL_3.2x2.5.kicad_mod
│ │ ├── coupler4.kicad_mod
│ │ ├── uwmiter_0.34_0.17_45.kicad_mod
│ │ └── uwmiter_0.34_0.17_90.kicad_mod
│ ├── vna2-cache.lib
│ ├── vna2.kicad_pcb
│ ├── vna2.pro
│ └── vna2.sch
├── openocd/
│ ├── interface.cfg
│ ├── program_flash.cfg
│ ├── program_fpga.cfg
│ └── xc7_bscan_spi.bit
└── software/
├── cal_kit/
│ ├── load.s1p
│ ├── open.s1p
│ └── short.s1p
├── max2871.py
├── monitor_rx.py
├── monitor_sparam.py
├── oneport/
│ └── calibrate.py
├── sparam.py
├── twoport/
│ └── calibrate.py
└── vna.py
================================================
FILE CONTENTS
================================================
================================================
FILE: README
================================================
Second version of the homemade 30 MHZ - 6 GHz single receiver VNA design files.
First version: https://github.com/Ttl/vna
For more information see: http://hforsten.com/improved-homemade-vna.html
FPGA can be programmed with Openocd (http://openocd.org/). Scripts for programming the FPGA and SPI flash are in the "openocd" folder. Copy the bit file to openocd folder and use the command "openocd -f <script.cfg>" to program the board.
Before communication is possible with the board through USB, FT2232D EEPROM needs to be programmed. Port B needs to be changed in FIFO 245 mode. This can be done using FTDIs "ft-prog" tool.
================================================
FILE: couplers/README
================================================
Resistive bridge coupler design files.
PCB Stackup: OSH park 4 layer process.
BOM:
3, http://www.mouser.fi/ProductDetail/Linx-Technologies/CONSMA003062/?qs=sGAEpiMZZMsgSGrx0WqTbDECK3OTA0n%2f
1, http://www.mouser.fi/ProductDetail/EPCOS-TDK/B64290P0687X046/?qs=sGAEpiMZZMs2JV%252bnT%2fvX8Df1W1GtRs01w38yswv%252b9W0%3d
3, http://www.mouser.fi/ProductDetail/Fair-Rite/5943000911/?qs=sGAEpiMZZMsuct6UGZJC7QQ6ZlEn2BkEKxrVH5WSvu8%3d
2, http://www.mouser.fi/ProductDetail/Fair-Rite/5977000101/?qs=sGAEpiMZZMs2JV%252bnT%2fvX8PSq2BULPkJLFoDtc8BHtvw%3d
Resistors (See coupler_layout.png for positions):
R1: 270
R2: 50
R3, R5: 36
R4, R6: 39
Mount the resistors upside down to minimize parasitics.
Coaxial cable:
RG405
================================================
FILE: couplers/gerbers/rf_bridge_Bottom.gbl
================================================
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FILE: couplers/gerbers/rf_bridge_In1.g2l
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FILE: couplers/gerbers/rf_bridge_In2.g3l
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FILE: couplers/gerbers/rf_bridge_Mask.gts
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FILE: couplers/gerbers/rf_bridge_Mask_bottom.gbs
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FILE: couplers/gerbers/rf_bridge_Outline.gko
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FILE: couplers/gerbers/rf_bridge_Top.gtl
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FILE: couplers/gerbers/rf_bridge_drill.drl
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X-027225Y-003350
X-027225Y-007850
X-027225Y-008950
X-026425Y-002050
X-026425Y-003350
X-026425Y-007850
X-026425Y-008950
X-025625Y-002050
X-025625Y-003350
X-025625Y-007850
X-025625Y-008950
X-024825Y-002050
X-024825Y-003450
X-024825Y-007750
X-024825Y-008950
X-024025Y-002050
X-024025Y-008950
X-023925Y-003850
X-023925Y-007550
X-023225Y-002050
X-023225Y-008950
X-022900Y-003895
X-022900Y-007305
X-021700Y-003695
X-021700Y-007605
X-020900Y-003695
X-020900Y-007605
X-020100Y-003695
X-020100Y-007605
X-019300Y-003695
X-019300Y-007605
X000700Y001200
X000700Y000100
X000700Y-000800
X000700Y-001700
X000700Y-002600
X000700Y-008600
X000700Y-009600
X001300Y-010800
X001300Y-012300
X001500Y001200
X001500Y000100
X001500Y-000800
X001500Y-001700
X001500Y-002600
X001500Y-008600
X001500Y-009600
X002300Y001200
X002300Y000100
X002300Y-000800
X002300Y-001700
X002300Y-002600
X002300Y-008600
X002300Y-009600
X002800Y-010800
X002800Y-012300
X003400Y-008600
X004200Y-009300
X004200Y-010800
X004200Y-012300
X004900Y-007800
X005900Y-007800
X005900Y-009300
X005900Y-010800
X005900Y-012300
X006200Y001100
X006200Y-000400
X006200Y-001900
X006200Y-003400
X007400Y-007800
X007400Y-009300
X007400Y-010800
X007400Y-012300
X007700Y001100
X007700Y-000400
X007700Y-001900
X007700Y-003400
X008900Y-007800
X008900Y-009300
X008900Y-010800
X008900Y-012300
X009100Y001100
X009100Y-000400
X009100Y-001900
X009100Y-003400
X010400Y001100
X010400Y-000400
X010400Y-001900
X010400Y-003400
X010400Y-007800
X010400Y-009300
X010400Y-010800
X010400Y-012300
T00
M30
================================================
FILE: fpga/vna/vna.hw/vna.lpr
================================================
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2016.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
================================================
FILE: fpga/vna/vna.srcs/constrs_1/new/vna_constraints.xdc
================================================
create_clock -period 25.000 -name clk -waveform {0.000 12.500} [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_in[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports {ft2232_data[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ft2232_data[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ft2232_data[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ft2232_data[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ft2232_data[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ft2232_data[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ft2232_data[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ft2232_data[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tx_filter[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tx_filter[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tx_filter[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {tx_filter[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {port_sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {port_sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rx_sw[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rx_sw[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rx_sw[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rx_sw[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rx_sw[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rx_sw[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports dither]
set_property IOSTANDARD LVCMOS33 [get_ports rxf]
set_property IOSTANDARD LVCMOS33 [get_ports txe]
set_property IOSTANDARD LVCMOS33 [get_ports wr]
set_property IOSTANDARD LVCMOS33 [get_ports si_wu]
set_property IOSTANDARD LVCMOS33 [get_ports spi_clk]
set_property IOSTANDARD LVCMOS33 [get_ports lo_spi_data]
set_property IOSTANDARD LVCMOS33 [get_ports source_spi_data]
set_property IOSTANDARD LVCMOS33 [get_ports lo_le]
set_property IOSTANDARD LVCMOS33 [get_ports lo_ce]
set_property IOSTANDARD LVCMOS33 [get_ports source_le]
set_property IOSTANDARD LVCMOS33 [get_ports source_ce]
set_property IOSTANDARD LVCMOS33 [get_ports rd]
set_property IOSTANDARD LVCMOS33 [get_ports lo_rf_enable]
set_property IOSTANDARD LVCMOS33 [get_ports source_rf_enable]
set_property IOSTANDARD LVCMOS33 [get_ports atten_spi_data]
set_property IOSTANDARD LVCMOS33 [get_ports atten_le]
set_property IOSTANDARD LVCMOS33 [get_ports mixer_enable]
set_property IOSTANDARD LVCMOS33 [get_ports amp_pwdn]
set_property IOSTANDARD LVCMOS33 [get_ports lo_ld]
set_property IOSTANDARD LVCMOS33 [get_ports source_ld]
set_property IOSTANDARD LVCMOS33 [get_ports source_muxout]
set_property IOSTANDARD LVCMOS33 [get_ports lo_muxout]
set_property IOSTANDARD LVCMOS33 [get_ports led]
set_property IOSTANDARD LVCMOS33 [get_ports adc_of]
set_property IOSTANDARD LVCMOS33 [get_ports adc_oe]
set_property IOSTANDARD LVCMOS33 [get_ports adc_shdn]
set_property IOSTANDARD LVCMOS33 [get_ports xadc_vp]
set_property IOSTANDARD LVCMOS33 [get_ports xadc_vn]
set_property PACKAGE_PIN N11 [get_ports clk]
set_property PACKAGE_PIN T10 [get_ports {adc_in[0]}]
set_property PACKAGE_PIN T9 [get_ports {adc_in[1]}]
set_property PACKAGE_PIN P9 [get_ports {adc_in[2]}]
set_property PACKAGE_PIN P8 [get_ports {adc_in[3]}]
set_property PACKAGE_PIN R8 [get_ports {adc_in[4]}]
set_property PACKAGE_PIN T8 [get_ports {adc_in[5]}]
set_property PACKAGE_PIN R7 [get_ports {adc_in[6]}]
set_property PACKAGE_PIN T7 [get_ports {adc_in[7]}]
set_property PACKAGE_PIN R6 [get_ports {adc_in[8]}]
set_property PACKAGE_PIN T5 [get_ports {adc_in[9]}]
set_property PACKAGE_PIN R5 [get_ports {adc_in[10]}]
set_property PACKAGE_PIN T4 [get_ports {adc_in[11]}]
set_property PACKAGE_PIN T3 [get_ports {adc_in[12]}]
set_property PACKAGE_PIN R3 [get_ports {adc_in[13]}]
set_property PACKAGE_PIN T2 [get_ports adc_of]
set_property PACKAGE_PIN T12 [get_ports adc_oe]
set_property PACKAGE_PIN T13 [get_ports adc_shdn]
set_property PACKAGE_PIN A13 [get_ports {tx_filter[3]}]
set_property PACKAGE_PIN A14 [get_ports {tx_filter[2]}]
set_property PACKAGE_PIN B16 [get_ports {tx_filter[1]}]
set_property PACKAGE_PIN A15 [get_ports {tx_filter[0]}]
set_property PACKAGE_PIN D16 [get_ports {port_sw[1]}]
set_property PACKAGE_PIN E16 [get_ports {port_sw[0]}]
#set_property PACKAGE_PIN H8 [get_ports {xadc_vp}]
#set_property PACKAGE_PIN J7 [get_ports {xadc_vn}]
set_property PACKAGE_PIN G1 [get_ports {rx_sw[5]}]
set_property PACKAGE_PIN H1 [get_ports {rx_sw[4]}]
set_property PACKAGE_PIN G2 [get_ports {rx_sw[3]}]
set_property PACKAGE_PIN H2 [get_ports {rx_sw[2]}]
set_property PACKAGE_PIN J1 [get_ports {rx_sw[1]}]
set_property PACKAGE_PIN K1 [get_ports {rx_sw[0]}]
set_property PACKAGE_PIN A8 [get_ports {ft2232_data[7]}]
set_property PACKAGE_PIN A9 [get_ports {ft2232_data[6]}]
set_property PACKAGE_PIN A10 [get_ports {ft2232_data[5]}]
set_property PACKAGE_PIN B9 [get_ports {ft2232_data[4]}]
set_property PACKAGE_PIN B10 [get_ports {ft2232_data[3]}]
set_property PACKAGE_PIN B11 [get_ports {ft2232_data[2]}]
set_property PACKAGE_PIN B12 [get_ports {ft2232_data[1]}]
set_property PACKAGE_PIN A12 [get_ports {ft2232_data[0]}]
set_property PACKAGE_PIN A2 [get_ports rxf]
set_property PACKAGE_PIN A3 [get_ports txe]
set_property PACKAGE_PIN A4 [get_ports wr]
set_property PACKAGE_PIN A5 [get_ports si_wu]
set_property PACKAGE_PIN B4 [get_ports rd]
set_property PACKAGE_PIN K16 [get_ports dither]
set_property PACKAGE_PIN K2 [get_ports mixer_enable]
set_property PACKAGE_PIN L3 [get_ports amp_pwdn]
set_property PACKAGE_PIN N14 [get_ports spi_clk]
set_property PACKAGE_PIN M14 [get_ports lo_spi_data]
set_property PACKAGE_PIN K15 [get_ports source_spi_data]
set_property PACKAGE_PIN G14 [get_ports lo_le]
set_property PACKAGE_PIN F14 [get_ports lo_ce]
set_property PACKAGE_PIN F12 [get_ports source_le]
set_property PACKAGE_PIN F13 [get_ports source_ce]
set_property PACKAGE_PIN C16 [get_ports atten_le]
set_property PACKAGE_PIN B15 [get_ports atten_spi_data]
set_property PACKAGE_PIN P16 [get_ports lo_ld]
set_property PACKAGE_PIN R16 [get_ports source_ld]
set_property PACKAGE_PIN H16 [get_ports source_muxout]
set_property PACKAGE_PIN J16 [get_ports lo_muxout]
set_property PACKAGE_PIN T14 [get_ports lo_rf_enable]
set_property PACKAGE_PIN T15 [get_ports source_rf_enable]
set_property PACKAGE_PIN D1 [get_ports led]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports {adc_in[*]}]
set_input_delay -clock [get_clocks clk] -max -add_delay 1.400 [get_ports {adc_in[*]}]
set_input_delay -clock [get_clocks clk] -add_delay 0.500 [get_ports {ft2232_data[*]}]
set_input_delay -clock [get_clocks clk] -add_delay 0.500 [get_ports rxf]
set_input_delay -clock [get_clocks clk] -add_delay 0.500 [get_ports txe]
set_input_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports lo_ld]
set_input_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports source_ld]
set_output_delay -clock [get_clocks clk] -add_delay 0.500 [get_ports {ft2232_data[*]}]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports spi_clk]
set_output_delay -clock [get_clocks clk] -add_delay 0.500 [get_ports wr]
set_output_delay -clock [get_clocks clk] -add_delay 0.500 [get_ports rd]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports {rx_sw[*]}]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports {port_sw[*]}]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports {tx_filter[*]}]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports lo_ce]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports source_ce]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports source_rf_enable]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports lo_rf_enable]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports mixer_enable]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports adc_oe]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports adc_shdn]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports amp_pwdn]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports dither]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports atten_le]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports lo_le]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports source_le]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports lo_spi_data]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports source_spi_data]
set_output_delay -clock [get_clocks clk] -add_delay 1.000 [get_ports atten_spi_data]
================================================
FILE: fpga/vna/vna.srcs/sim_1/new/comm_tb.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01.12.2016 19:38:11
-- Design Name:
-- Module Name: comm_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity comm_tb is
-- Port ( );
end comm_tb;
architecture Behavioral of comm_tb is
signal clk, rst : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 25 ns;
signal ft2232_data, data_out, data_in : std_logic_vector(7 downto 0) := (others => '0');
signal data_in_valid : std_logic := '0';
signal data_out_valid : std_logic;
signal data_in_ack, data_out_ack : std_logic := '0';
signal rxf, txe, rd, wr, si_wu : std_logic := '0';
signal read_done : std_logic := '0';
begin
comm : entity work.comm
Port map ( clk => clk,
rst => rst,
ft2232_data => ft2232_data,
data_in_valid => data_in_valid,
data_out => data_out,
data_out_valid => data_out_valid,
data_in => data_in,
data_in_ack => data_in_ack,
data_out_ack => data_out_ack,
rxf => rxf,
txe => txe,
rd => rd,
wr => wr,
si_wu => si_wu);
rst_process : process
begin
rst <= '1';
wait for clk_period;
rst <= '0';
wait;
end process;
-- Clock process definitions
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Clock process definitions
read_process : process
begin
rxf <= '1';
wait for 10*clk_period;
rxf <= '0';
wait until rd = '0';
wait for 50 ns;
ft2232_data <= "10101010";
wait until rd = '1';
ft2232_data <= "ZZZZZZZZ";
wait for 25 ns;
rxf <= '1';
wait for 10*clk_period;
assert data_out = "10101010" severity failure;
data_out_ack <= '1';
wait for clk_period;
data_out_ack <= '0';
wait for clk_period;
assert data_out_valid = '0' severity failure;
read_done <= '1';
report "Read done";
wait;
end process;
-- Clock process definitions
write_process : process
begin
wait until read_done = '1';
data_in <= "11110000";
data_in_valid <= '1';
wait until wr = '0';
wait for 25 ns;
txe <= '1';
assert ft2232_data = "11110000" severity failure;
wait until data_in_ack = '1';
data_in_valid <= '0';
assert ft2232_data = "ZZZZZZZZ" severity failure;
report "Write done";
wait for 5*clk_period;
txe <= '0';
wait;
end process;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sim_1/new/ft2232_behavioral.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.12.2016 21:22:37
-- Design Name:
-- Module Name: ft2232_rx - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ft2232_rx is
Port ( data : in STD_LOGIC_VECTOR (7 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0);
rxf : out STD_LOGIC;
txe : out STD_LOGIC;
rd : out STD_LOGIC;
wr : in STD_LOGIC;
si_wu : in STD_LOGIC);
end ft2232_rx;
architecture Behavioral of ft2232_rx is
begin
rxf <= '1';
rd <= '1';
write_process : process
begin
txe <= '0';
wait until wr = '0';
wait for 25 ns;
txe <= '1';
data_out <= data;
wait for 200 ns;
end process;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sim_1/new/io_bank_tb.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01.12.2016 20:52:12
-- Design Name:
-- Module Name: io_bank_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.vna_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity io_bank_tb is
-- Port ( );
end io_bank_tb;
architecture Behavioral of io_bank_tb is
signal clk, rst : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 25 ns;
signal ft2232_data, data_out, data_in : std_logic_vector(7 downto 0) := (others => '0');
signal data_in_valid : std_logic := '0';
signal data_out_valid : std_logic;
signal data_in_ack, data_out_ack : std_logic := '0';
signal rxf, txe, rd, wr, si_wu : std_logic := '0';
signal io_data_out : std_logic_vector(7 downto 0);
signal io_data_out_valid, io_data_out_ack : std_logic := '0';
signal tx_filter, port_sw, rx_sw : std_logic_vector(1 downto 0);
signal port_sw_term, rx_term : std_logic;
signal lo_spi_data : STD_LOGIC_VECTOR(31 downto 0);
signal lo_spi_write : std_logic;
signal source_spi_data : STD_LOGIC_VECTOR(31 downto 0);
signal source_spi_write : std_logic;
constant TEST_DATA_LENGTH : integer := 11;
type test_data_type is array(TEST_DATA_LENGTH-1 downto 0) of std_logic_vector(7 downto 0);
signal test_data : test_data_type := (
0 => COMM_START,
1 => "00000001", -- Set switches
2 => "00000001",
3 => "11111111",
4 => COMM_START,
5 => "00000100", -- Set LO
6 => "00000011",
7 => "11111111",
8 => "10101010",
9 => "01010101",
10 => "00000000"
);
begin
comm : entity work.comm
Port map ( clk => clk,
rst => rst,
ft2232_data => ft2232_data,
data_in_valid => data_in_valid,
data_out => data_out,
data_out_valid => data_out_valid,
data_in => data_in,
data_in_ack => data_in_ack,
data_out_ack => data_out_ack,
rxf => rxf,
txe => txe,
rd => rd,
wr => wr,
si_wu => si_wu);
io_bank : entity work.io_bank
Port map ( clk => clk,
rst => rst,
data_in => data_out,
data_valid => data_out_valid,
data_in_ack => data_out_ack,
data_out => io_data_out,
data_out_valid => io_data_out_valid,
data_out_ack => io_data_out_ack,
tx_filter => tx_filter,
port_sw => port_sw,
rx_sw => rx_sw,
lo_spi_data => lo_spi_data,
lo_spi_write => lo_spi_write,
source_spi_data => source_spi_data,
source_spi_write => source_spi_write,
led => open);
rst_process : process
begin
rst <= '1';
wait for clk_period;
rst <= '0';
wait;
end process;
-- Clock process definitions
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
read_process : process
variable i : integer := 0;
begin
if i = TEST_DATA_LENGTH then
report "End of data";
wait;
end if;
rxf <= '1';
wait for 10*clk_period;
rxf <= '0';
wait until rd = '0';
wait for 50 ns;
ft2232_data <= test_data(i);
wait until rd = '1';
ft2232_data <= "ZZZZZZZZ";
wait for 25 ns;
rxf <= '1';
wait for 10*clk_period;
assert data_out = test_data(i) severity failure;
i := i + 1;
end process;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sim_1/new/iq_packer_tb.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.12.2016 20:11:24
-- Design Name:
-- Module Name: iq_packer_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.vna_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity iq_packer_tb is
-- Port ( );
end iq_packer_tb;
architecture Behavioral of iq_packer_tb is
signal clk, rst : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 25 ns;
signal ft2232_data, data_out, iq_data : std_logic_vector(7 downto 0) := (others => '0');
signal data_out_valid : std_logic;
signal data_in_ack, data_out_ack : std_logic := '0';
signal rxf, txe, rd, wr, si_wu : std_logic := '1';
signal start : std_logic := '0';
signal done : std_logic;
signal iq_data_valid, iq_data_ack : std_logic;
signal i_acc, q_acc, cycles : STD_LOGIC_VECTOR (IQ_ACC_WIDTH-1 downto 0) := (1 => '1', 2 => '1', 4 => '1', others => '0');
begin
iq_packer : entity work.iq_packer
Port map ( clk => clk,
rst => rst,
start => start,
done => done,
i_acc => i_acc,
q_acc => q_acc,
cycles => cycles,
data_out => iq_data,
data_valid => iq_data_valid,
data_ack => iq_data_ack);
comm : entity work.comm
Port map ( clk => clk,
rst => rst,
ft2232_data => ft2232_data,
data_in_valid => iq_data_valid,
data_out => data_out,
data_out_valid => data_out_valid,
data_in => iq_data,
data_in_ack => iq_data_ack,
data_out_ack => data_out_ack,
rxf => rxf,
txe => txe,
rd => rd,
wr => wr,
si_wu => si_wu);
rst_process : process
begin
rst <= '1';
wait for clk_period;
rst <= '0';
wait;
end process;
start_process : process
begin
start <= '0';
wait for 10*clk_period;
start <= '1';
wait for clk_period;
start <= '0';
wait;
end process;
-- Clock process definitions
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
write_process : process
begin
txe <= '0';
wait until wr = '0';
wait for 25 ns;
txe <= '1';
wait for 5*clk_period;
end process;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sim_1/new/lo_sim.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 27.11.2016 12:35:22
-- Design Name:
-- Module Name: lo_sim - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lo_sim is
-- Port ( );
end lo_sim;
architecture Behavioral of lo_sim is
constant BIT_WIDTH : integer := 14;
signal clk, rst : std_logic := '0';
signal lo_out : std_logic_vector(BIT_WIDTH-1 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
lo : entity work.lo
Generic map(
BIT_WIDTH => BIT_WIDTH,
TABLE_SIZE => 5,
TABLE_WIDTH => 3,
COS => false
)
Port map(
rst => rst,
clk => clk,
lo_out => lo_out
);
rst_process :process
begin
rst <= '1';
wait for clk_period;
rst <= '0';
wait;
end process;
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sim_1/new/mixer_sim.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 27.11.2016 10:10:56
-- Design Name:
-- Module Name: mixer_sim - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mixer_sim is
-- Port ( );
end mixer_sim;
architecture Behavioral of mixer_sim is
signal clk : std_logic := '0';
signal rf : std_logic_vector(13 downto 0) := (others => '0');
signal lo : std_logic_vector(15 downto 0) := (0 => '1', others => '0');
signal if_out : std_logic_vector(15 downto 0) := (others => '0');
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
mixer : entity work.mixer
Generic map(
RF_WIDTH => 14,
LO_WIDTH => 16,
IF_WIDTH => 16
)
Port map( clk => clk,
rf => rf,
lo => lo,
if_out => if_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Clock process definitions
rf_process :process(clk, rf)
begin
if rising_edge(clk) then
rf <= std_logic_vector(unsigned(rf)+1);
end if;
end process;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sim_1/new/receiver_tb.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 27.11.2016 20:14:33
-- Design Name:
-- Module Name: receiver_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.vna_pkg.all;
use std.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity receiver_tb is
-- Port ( );
end receiver_tb;
architecture Behavioral of receiver_tb is
signal clk, rst, rst_adc, start : std_logic := '0';
signal adc : std_logic_vector(ADC_WIDTH-1 downto 0) := (others => '0');
signal i_acc, q_acc, cycles : std_logic_vector(IQ_ACC_WIDTH-1 downto 0) := (others => '0');
signal sample_time : std_logic_vector(31 downto 0) := (others => '0');
signal sample_time_valid : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 10 ns;
signal i, q : Real := 0.0;
signal i_int, q_int : integer;
begin
--adc_source : entity work.lo
-- Generic map(
-- BIT_WIDTH => ADC_WIDTH,
-- TABLE_SIZE => 5,
-- TABLE_WIDTH => 3,
-- COS => false
-- )
-- Port map(
-- rst => rst,
-- clk => clk,
-- lo_out => adc
--);
file_adc : entity work.file_adc
Generic map (in_file => "/home/henrik/koodi/vna2/software/samples_no_signal.txt")
Port map ( clk => clk,
rst => rst,
adc_out => adc);
rx : entity work.receiver
Port map ( clk => clk,
rst => rst,
adc => adc,
i_acc => i_acc,
q_acc => q_acc,
cycles => cycles,
start => start,
if_output => open,
cic_output => open,
cic_valid => open);
rx_control : entity work.receiver_control
Port map( clk => clk,
rst => rst,
start_early => open,
start => start,
sample_time => sample_time,
sample_time_valid => sample_time_valid);
rst_process :process
begin
-- rst <= '1';
-- rst_adc <= '1';
-- wait for 2*clk_period;
-- rst_adc <= '0';
-- rst <= '0';
wait for 1000*clk_period;
report "I:" & real'image(i);
report "Q:" & real'image(q);
end process;
-- Clock process definitions
clk_process :process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
iq_divide : process(clk)
begin
if rising_edge(clk) then
i <= Real(to_integer(signed(i_acc)))/(to_integer(unsigned(cycles)))/Real(32768000);
q <= Real(to_integer(signed(q_acc)))/(to_integer(unsigned(cycles)))/Real(32768000);
end if;
end process;
iq_int : process(clk)
begin
if rising_edge(clk) then
i_int <= integer(i*Real(327680));
q_int <= integer(q*Real(327680));
end if;
end process;
--write process
writing : process
file outfile : text is out "receiver_tb_out.txt"; --declare output file
variable outline : line; --line number declaration
begin
wait until clk = '0' and clk'event;
--write(linenumber,value(real type),justified(side),field(width),digits(natural));
write(outline, integer'image(to_integer(signed(i_acc)))&", "&integer'image(to_integer(signed(q_acc)))&", "&integer'image(to_integer(unsigned(cycles))));
-- write line to external file.
writeline(outfile, outline);
end process writing;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sim_1/new/spi3_tb.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12.02.2017 12:24:22
-- Design Name:
-- Module Name: spi3_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity spi3_tb is
-- Port ( );
end spi3_tb;
architecture Behavioral of spi3_tb is
signal clk, rst : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 25 ns;
signal lo_data_in, source_data_in : std_logic_vector(31 downto 0);
signal att_data_in : std_logic_vector(7 downto 0);
signal lo_write, source_write, att_write : std_logic := '0';
signal busy : std_logic;
signal spi_clk, spi_data_lo, spi_data_source, spi_data_att : std_logic;
signal spi_le_lo, spi_le_source, spi_le_att : std_logic;
begin
spi3 : entity work.spi3
Generic map ( SPI_CLK_DIVIDER => 1)
Port map ( clk => clk,
rst => rst,
lo_data_in => lo_data_in,
source_data_in => source_data_in,
att_data_in => att_data_in,
lo_write => lo_write,
source_write => source_write,
att_write => att_write,
busy => busy,
spi_clk => spi_clk,
spi_data_lo => spi_data_lo,
spi_data_source => spi_data_source,
spi_data_att => spi_data_att,
spi_le_lo => spi_le_lo,
spi_le_source => spi_le_source,
spi_le_att => spi_le_att);
-- Clock process definitions
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
test_process : process
begin
wait for 100 ns;
wait until rising_edge(clk);
lo_data_in <= "10101010101010101010101010101010";
lo_write <= '1';
wait for 2*clk_period;
lo_write <= '0';
wait for 5*clk_period;
att_data_in <= "01010101";
att_write <= '1';
wait for 2*clk_period;
att_write <= '0';
wait for 5*clk_period;
source_data_in <= "01010101010101010101010101010101";
source_write <= '1';
wait for 2*clk_period;
source_write <= '0';
wait;
end process;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sim_1/new/spi_write_tb.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01.12.2016 18:23:00
-- Design Name:
-- Module Name: spi_write_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity spi_write_tb is
-- Port ( );
end spi_write_tb;
architecture Behavioral of spi_write_tb is
constant DATA_LENGTH : integer := 16;
signal clk, rst : std_logic := '0';
signal data : std_logic_vector(DATA_LENGTH-1 downto 0) := "1010110111011110";
signal spi_clk, spi_data, spi_cs : std_logic;
signal data_ack : std_logic;
signal data_in_valid : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
spi_write : entity work.spi_write
Generic map (SPI_CLK_DIVIDER => 2,
DATA_LENGTH => DATA_LENGTH)
Port map ( clk => clk,
rst => rst,
spi_clk => spi_clk,
spi_data => spi_data,
spi_cs => spi_cs,
data_in => data,
data_in_valid => data_in_valid,
data_in_ack => data_ack);
rst_process : process
begin
rst <= '1';
wait for clk_period;
rst <= '0';
wait;
end process;
-- Clock process definitions
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
write_process : process
begin
wait for 10*clk_period;
data_in_valid <= '1';
wait until data_ack = '1';
data_in_valid <= '0';
end process;
assert_process : process(spi_clk)
variable i : integer := DATA_LENGTH-1;
begin
if rising_edge(spi_clk) then
assert spi_data = data(i) severity failure;
i := i - 1;
if i = 0 then
i := DATA_LENGTH-1;
end if;
end if;
end process;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sim_1/new/vna_tb.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 27.11.2016 13:44:10
-- Design Name:
-- Module Name: vna_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.vna_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity vna_tb is
-- Port ( );
end vna_tb;
architecture Behavioral of vna_tb is
component lo is
Generic (
BIT_WIDTH : integer;
TABLE_SIZE : integer;
TABLE_WIDTH : integer;
COS : boolean
);
Port ( rst : in std_logic;
clk : in STD_LOGIC;
lo_out : out STD_LOGIC_VECTOR (BIT_WIDTH-1 downto 0));
end component;
constant LO_BIT_WIDTH : integer := 14;
constant ADC_BIT_WIDTH : integer := 14;
signal clk, rst : std_logic := '0';
signal rf : std_logic_vector(ADC_BIT_WIDTH-1 downto 0);
signal if_i_out, if_q_out : std_logic_vector(15 downto 0) := (others => '0');
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
downconvert : entity work.downconvert
-- Generic map (
-- ADC_WIDTH => ADC_WIDTH,
-- IF_WIDTH => IF_WIDTH)
Port map ( clk => clk,
rst => rst,
adc => rf,
if_i_out => if_i_out,
if_q_out => if_q_out);
adc_source : lo
Generic map(
BIT_WIDTH => ADC_BIT_WIDTH,
TABLE_SIZE => 5,
TABLE_WIDTH => 3,
COS => true
)
Port map(
rst => rst,
clk => clk,
lo_out => rf
);
rst_process :process
begin
rst <= '1';
wait for clk_period;
rst <= '0';
wait;
end process;
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sim_1/new/vna_top_tb.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.12.2016 21:00:18
-- Design Name:
-- Module Name: vna_top_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.vna_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity vna_top_tb is
-- Port ( );
end vna_top_tb;
architecture Behavioral of vna_top_tb is
signal clk, rst : std_logic := '0';
signal adc : std_logic_vector(ADC_WIDTH-1 downto 0) := (others => '0');
signal i_acc, q_acc, cycles : std_logic_vector(IQ_ACC_WIDTH-1 downto 0) := (others => '0');
-- Clock period definitions
constant clk_period : time := 25 ns;
signal ft2232_data: std_logic_vector(7 downto 0) := (others => 'Z');
signal rxf, txe, rd, wr, si_wu : std_logic := '1';
signal led : std_logic;
signal adc_oe, adc_shdn : std_logic;
signal adc_of : std_logic := '0';
signal tx_filter : std_logic_vector(3 downto 0);
signal port_sw : std_logic_vector(1 downto 0);
signal rx_sw : std_logic_vector(5 downto 0);
signal lo_muxout, source_muxout: std_logic;
signal spi_clk, lo_spi_data, lo_le, lo_ce, lo_rf_enable : std_logic;
signal source_spi_data, source_le, source_ce, source_rf_enable : std_logic;
signal atten_spi_data, atten_le : std_logic;
signal lo_ld, source_ld : std_logic := '0';
signal mixer_enable, amp_pwdn, dither : std_logic;
signal read_data : std_logic_vector(7 downto 0);
signal new_data : std_logic := '0';
signal i_data, q_data, cycles_data : signed(8*IQ_BYTES-1 downto 0);
signal sw_data : std_logic_vector(7 downto 0);
signal read_done : std_logic := '0';
signal source_q, lo_q : std_logic_vector(31 downto 0) := (others => 'U');
signal atten_q : std_logic_vector(7 downto 0) := (others => 'U');
constant TEST_DATA_LENGTH : integer := 39;
type test_data_type is array(TEST_DATA_LENGTH-1 downto 0) of std_logic_vector(7 downto 0);
signal test_data : test_data_type := (
--0 => COMM_START,
--1 => "00000100", -- Write Source
--2 => "00000100",
--3 => "11111111",
--4 => "00000000",
--5 => "10101010",
--6 => "00110011",
--7 => COMM_START,
--8 => "00000100", -- Write Source
--9 => "00000100",
--10 => "11111111",
--11 => "00000000",
--12 => "10101010",
--13 => "00110011",
--14 => COMM_START,
--15 => "00000100", -- Write Source
--16 => "00000100",
--17 => "11111111",
--18 => "00000000",
--19 => "10101010",
--20 => "00110011",
--21 => COMM_START,
--22 => "00000100", -- Write LO
--23 => "00000011",
--24 => "11111111",
--25 => "00000000",
--26 => "10101010",
--27 => "00110011",
--28 => COMM_START,
--29 => "00000100", -- Write LO
--30 => "00000011",
--31 => "11111111",
--32 => "00000000",
--33 => "10101010",
--34 => "00110011",
--35 => COMM_START, -- Echo
--36 => "00000001",
--37 => "00001010",
--38 => "11111111",
--39 => COMM_START,
--40 => "00000001",
--41 => "00001000",
--42 => "00000000",
--others => (others => 'U')
0 => COMM_START,
1 => "00000010", -- Set switches
2 => "00000001",
3 => "11111111",
4 => "00111111",
5 => COMM_START,
6 => "00000001", -- Set IO
7 => "00000010",
8 => "11111111",
9 => COMM_START,
10 => "00000100", -- Write Source
11 => "00000100",
12 => "11111111",
13 => "00000000",
14 => "10101010",
15 => "00110011",
16 => COMM_START,
17 => "00000001", -- Write Atten
18 => "00000110",
19 => "10101010",
20 => COMM_START,
21 => "00000001", -- Write Atten again
22 => "00000110",
23 => "10101010",
24 => COMM_START,
25 => "00000001", -- Write PLL IO
26 => "00000111",
27 => "00001111",
28 => COMM_START,
29 => "00000100", -- Write sample time
30 => "00000101",
31 => "00000000",
32 => "00000000",
33 => "00010000",
34 => "00000000",
35 => COMM_START,
36 => "00000001", -- Write tag
37 => "00001011",
38 => "00001010",
others => (others => 'U')
);
begin
adc_source : entity work.lo
Generic map(
BIT_WIDTH => ADC_WIDTH,
TABLE_SIZE => 5,
TABLE_WIDTH => 3,
COS => false
)
Port map(
rst => rst,
clk => clk,
lo_out => adc
);
vna_top : entity work.vna_top
Port map ( clk => clk,
adc_in => adc,
adc_of => adc_of,
adc_oe => adc_oe,
adc_shdn => adc_shdn,
ft2232_data => ft2232_data,
rxf => rxf,
txe => txe,
rd => rd,
wr => wr,
si_wu => si_wu,
tx_filter => tx_filter,
port_sw => port_sw,
rx_sw => rx_sw,
spi_clk => spi_clk,
lo_spi_data => lo_spi_data,
lo_le => lo_le,
lo_ce => lo_ce,
lo_rf_enable => lo_rf_enable,
lo_muxout => lo_muxout,
source_muxout => source_muxout,
source_spi_data => source_spi_data,
source_le => source_le,
source_ce => source_ce,
source_rf_enable => source_rf_enable,
atten_spi_data => atten_spi_data,
atten_le => atten_le,
lo_ld => lo_ld,
source_ld => source_ld,
mixer_enable => mixer_enable,
amp_pwdn => amp_pwdn,
dither => dither,
xadc_vp => '0',
xadc_vn => '0',
led => led);
--ft2232_rx : entity work.ft2232_rx
--Port map( data => ft2232_data,
-- data_out => read_data,
-- rxf => rxf,
-- txe => txe,
-- rd => rd,
-- wr => wr,
-- si_wu => si_wu);
rst_process :process
begin
rst <= '1';
wait for 2*clk_period;
rst <= '0';
wait;
end process;
ld_process : process
begin
wait for 100*clk_period;
lo_ld <= '1';
wait for 10*clk_period;
source_ld <= '1';
wait;
end process;
-- Clock process definitions
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
read_process : process
variable i : integer := 0;
begin
wait for 10*clk_period;
if i = TEST_DATA_LENGTH then
i := 0;
read_done <= '1';
report "End of data";
wait;
end if;
rxf <= '1';
wait for 81 ns;
rxf <= '0';
wait until rd = '0';
ft2232_data <= (others => 'X');
wait for 49 ns;
ft2232_data <= test_data(i);
wait until rd = '1';
ft2232_data <= "ZZZZZZZZ";
wait for 26 ns;
rxf <= '1';
i := i + 1;
end process;
write_process : process
variable i : integer := 0;
begin
--if read_done = '0' then
-- wait until read_done = '1';
--end if;
assert wr = '1' severity error;
txe <= '0';
wait for 100 ns;
wait until wr = '0';
wait for 50 ns;
txe <= '1';
read_data <= ft2232_data;
new_data <= '1';
--if read_data = COMM_START then
-- wait for 10 ms;
--end if;
wait for clk_period;
new_data <= '0';
wait for 100 ns;
i := i + 1;
end process;
report_process : process(clk, new_data, read_data)
variable state, count : integer := 0;
variable i, q, cycles : std_logic_vector(IQ_ACC_WIDTH-1 downto 0) := (others => '0');
variable sw : std_logic_vector(7 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if new_data = '1' then
case state is
when 0 =>
if read_data = COMM_START then
state := 1;
end if;
when 1 =>
if read_data = "00011000" then
state := 2;
end if;
when 2 =>
if read_data = "00000001" then
state := 3;
count := 0;
end if;
when 6 => -- SW
sw := read_data;
state := 0;
i_data <= signed(i);
q_data <= signed(q);
cycles_data <= signed(cycles);
sw_data <= sw;
when others =>
-- 3, i
-- 4, q
-- 5, cycles
-- 6, sw
if state = 3 then
i(8*(count+1)-1 downto 8*count) := read_data;
elsif state = 4 then
q(8*(count+1)-1 downto 8*count) := read_data;
elsif state = 5 then
cycles(8*(count+1)-1 downto 8*count) := read_data;
end if;
if count = IQ_BYTES-1 then
state := state + 1;
count := 0;
else
count := count + 1;
end if;
end case;
end if;
end if;
end process;
spi_process : process(clk, spi_clk, source_spi_data, source_le)
variable atten_le_prev, source_le_prev, lo_le_prev : std_logic := '0';
variable source_q_int, lo_q_int : std_logic_vector(31 downto 0);
variable atten_q_int : std_logic_vector(7 downto 0);
begin
if rising_edge(spi_clk) then
if source_le = '0' then
source_q_int := source_spi_data&source_q_int(31 downto 1);
end if;
if lo_le = '0' then
lo_q_int := lo_spi_data&lo_q_int(31 downto 1);
end if;
if atten_le = '0' then
atten_q_int := atten_spi_data&atten_q_int(7 downto 1);
end if;
end if;
if rising_edge(clk) then
if source_le_prev = '0' and source_le = '1' then
source_q <= source_q_int;
end if;
if lo_le_prev = '0' and lo_le = '1' then
lo_q <= lo_q_int;
end if;
if atten_le_prev = '0' and atten_le = '1' then
atten_q <= atten_q_int;
end if;
atten_le_prev := atten_le;
source_le_prev := source_le;
lo_le_prev := lo_le;
end if;
end process;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/imports/new/downconvert.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 27.11.2016 13:58:22
-- Design Name:
-- Module Name: downconvert - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.vna_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity downconvert is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
adc : in STD_LOGIC_VECTOR (ADC_WIDTH-1 downto 0);
if_i_out : out STD_LOGIC_VECTOR (IF_WIDTH-1 downto 0);
if_q_out : out STD_LOGIC_VECTOR (IF_WIDTH-1 downto 0));
end downconvert;
architecture Behavioral of downconvert is
signal lo_i_out, lo_q_out : std_logic_vector(LO_WIDTH-1 downto 0) := (others => '0');
begin
lo_i : entity work.lo
Generic map(
BIT_WIDTH => LO_WIDTH,
TABLE_SIZE => 5,
TABLE_WIDTH => 3,
COS => true
)
Port map(
rst => rst,
clk => clk,
lo_out => lo_i_out
);
lo_q : entity work.lo
Generic map(
BIT_WIDTH => LO_WIDTH,
TABLE_SIZE => 5,
TABLE_WIDTH => 3,
COS => false
)
Port map(
rst => rst,
clk => clk,
lo_out => lo_q_out
);
mixer_i : entity work.mixer
Generic map(
RF_WIDTH => ADC_WIDTH,
LO_WIDTH => LO_WIDTH,
IF_WIDTH => IF_WIDTH
)
Port map( clk => clk,
rf => adc,
lo => lo_i_out,
if_out => if_i_out
);
mixer_q : entity work.mixer
Generic map(
RF_WIDTH => ADC_WIDTH,
LO_WIDTH => LO_WIDTH,
IF_WIDTH => IF_WIDTH
)
Port map( clk => clk,
rf => adc,
lo => lo_q_out,
if_out => if_q_out
);
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/imports/new/port_switch.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 27.11.2016 15:33:21
-- Design Name:
-- Module Name: port_switch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity port_switch is
Port ( direction : in STD_LOGIC;
term : in STD_LOGIC;
swa_ctrl : out STD_LOGIC_VECTOR (1 downto 0);
swb_ctrl : out STD_LOGIC_VECTOR (1 downto 0);
swc_ctrl : out STD_LOGIC_VECTOR (1 downto 0));
end port_switch;
architecture Behavioral of port_switch is
begin
process(direction, term)
begin
if term = '1' then
swa_ctrl <= "00";
swb_ctrl <= "00";
swc_ctrl <= "00";
else
if direction = '1' then
swa_ctrl <= "10";
swb_ctrl <= "10";
swc_ctrl <= "01";
else
swa_ctrl <= "01";
swb_ctrl <= "01";
swc_ctrl <= "10";
end if;
end if;
end process;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/imports/new/sample_packer.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12.02.2017 19:54:50
-- Design Name:
-- Module Name: sample_packer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.vna_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sample_packer is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
adc_in : in STD_LOGIC_VECTOR(13 downto 0);
if_output : in STD_LOGIC_VECTOR(IF_WIDTH-1 downto 0);
i_acc : in STD_LOGIC_VECTOR(IQ_ACC_WIDTH-1 downto 0);
data_out : out STD_LOGIC_VECTOR(7 downto 0);
data_valid : out STD_LOGIC;
data_ack : in STD_LOGIC;
sample_mux_ctrl : in STD_LOGIC_VECTOR(1 downto 0));
end sample_packer;
architecture Behavioral of sample_packer is
constant packet_size : integer := 10003;
type memory_type is array (0 to packet_size-1) of std_logic_vector(15 downto 0);
signal packet_memory : memory_type := (0 => COMM_START&std_logic_vector(to_unsigned(packet_size-1, 8)), 1 => "0000001000000000", others => (others => '0'));
signal queue_full : std_logic := '0';
signal start_delay : std_logic := '0';
begin
process(clk, rst, adc_in, if_output, i_acc, data_ack, sample_mux_ctrl)
variable pointer : unsigned(15 downto 0) := to_unsigned(2, 16);
variable word : std_logic := '0';
variable sample_buffer : STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
variable wait_start : std_logic := '0';
begin
if rising_edge(clk) then
if wait_start = '1' then
if start = '1' then
wait_start := '0';
end if;
elsif queue_full = '0' then
data_valid <= '0';
packet_memory(to_integer(pointer)) <= sample_buffer;
if pointer = packet_size-1 then
queue_full <= '1';
pointer := to_unsigned(0, 16);
else
pointer := pointer + to_unsigned(1, 16);
end if;
else
if word = '0' then
data_out <= packet_memory(to_integer(pointer))(15 downto 8);
else
data_out <= packet_memory(to_integer(pointer))(7 downto 0);
end if;
data_valid <= '1';
if data_ack = '1' then
if pointer = packet_size-1 then
queue_full <= '0';
wait_start := '1';
data_valid <= '0';
pointer := to_unsigned(2, 16);
else
if word = '0' then
word := '1';
else
pointer := pointer + to_unsigned(1, 16);
word := '0';
end if;
end if;
end if;
end if;
if sample_mux_ctrl = "00" then
sample_buffer := adc_in(13)&adc_in(13)&adc_in;
elsif sample_mux_ctrl = "01" then
sample_buffer := if_output(23 downto 8);
elsif sample_mux_ctrl = "10" then
sample_buffer := i_acc(25 downto 10);
else
sample_buffer := (others => '0');
end if;
end if;
end process;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/imports/new/spi3.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12.02.2017 11:46:15
-- Design Name:
-- Module Name: spi3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity spi3 is
Generic (SPI_CLK_DIVIDER : integer := 1);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
lo_data_in : in STD_LOGIC_VECTOR (31 downto 0);
source_data_in : in STD_LOGIC_VECTOR (31 downto 0);
att_data_in : in STD_LOGIC_VECTOR (7 downto 0);
lo_write : in STD_LOGIC;
source_write : in STD_LOGIC;
att_write : in STD_LOGIC;
busy : out STD_LOGIC;
spi_clk : out STD_LOGIC;
spi_data_lo : out STD_LOGIC;
spi_data_source : out STD_LOGIC;
spi_data_att : out STD_LOGIC;
spi_le_lo : out STD_LOGIC;
spi_le_source : out STD_LOGIC;
spi_le_att : out STD_LOGIC;
source_ack : out STD_LOGIC;
lo_ack : out STD_LOGIC;
att_ack : out STD_LOGIC);
end spi3;
architecture Behavioral of spi3 is
signal lo_reg, source_reg : std_logic_vector(31 downto 0) := (others => '0');
signal att_reg : std_logic_vector(7 downto 0) := (others => '0');
signal spi_clk_int : std_logic := '0';
signal spi_clk_en : std_logic := '0';
signal spi_le_lo_int, spi_le_source_int, spi_le_att_int : std_logic := '1';
signal lo_write_buffer, source_write_buffer, att_write_buffer : std_logic := '0';
constant LE_LENGTHEN : integer := 10;
constant NEXT_DELAY : integer := 50;
-- LE lengthen
signal pipe_source, pipe_lo, pipe_att : std_logic_vector(LE_LENGTHEN-1 downto 0) := (others => '0');
begin
spi_clk_process : process(clk, rst, lo_data_in, source_data_in, att_data_in, lo_write, source_write, att_write)
variable count : unsigned(7 downto 0) := to_unsigned(0, 8);
variable lo_bits, source_bits, att_bits : unsigned(5 downto 0) := to_unsigned(0, 6);
variable lo_bits_prev, source_bits_prev, att_bits_prev : unsigned(5 downto 0) := to_unsigned(0, 6);
variable source_data_in_buffer, lo_data_in_buffer : std_logic_vector(31 downto 0);
variable att_data_in_buffer : std_logic_vector(7 downto 0);
variable lo_done, source_done, att_done : std_logic := '1';
variable source_delay, lo_delay, att_delay : unsigned(7 downto 0) := to_unsigned(0, 8);
begin
if rst = '1' then
count := to_unsigned(0, 8);
elsif rising_edge(clk) then
-- Default LE values
spi_le_lo_int <= '0';
spi_le_source_int <= '0';
spi_le_att_int <= '0';
lo_ack <= '0';
source_ack <= '0';
att_ack <= '0';
if source_delay /= to_unsigned(0, 8) then
source_delay := source_delay - 1;
end if;
if lo_delay /= to_unsigned(0, 8) then
lo_delay := lo_delay - 1;
end if;
if att_delay /= to_unsigned(0, 8) then
att_delay := att_delay - 1;
end if;
-- Buffer write requests
-- Write must begin on correct SPI clock phase
if lo_write = '1' and lo_done = '1' and lo_delay = to_unsigned(0, 8) then
lo_data_in_buffer := lo_data_in;
lo_write_buffer <= '1';
lo_ack <= '1';
end if;
if source_write = '1' and source_done = '1' and source_delay = to_unsigned(0, 8) then
source_data_in_buffer := source_data_in;
source_write_buffer <= '1';
source_ack <= '1';
end if;
if att_write = '1' and att_done = '1' and att_delay = to_unsigned(0, 8) then
att_data_in_buffer := att_data_in;
att_write_buffer <= '1';
att_ack <= '1';
end if;
if lo_done = '1' and source_done = '1' and att_done = '1' then
spi_clk_en <= '0';
else
spi_clk_en <= '1';
end if;
if count = SPI_CLK_DIVIDER then
count := to_unsigned(0, 8);
if spi_clk_en = '1' then
spi_clk_int <= not spi_clk_int;
else
spi_clk_int <= '0';
end if;
if spi_clk_int = '1' then
-- Shift new bit
if lo_write_buffer = '0' then
lo_reg <= lo_reg(30 downto 0)&'0';
end if;
if source_write_buffer = '0' then
source_reg <= source_reg(30 downto 0)&'0';
end if;
if att_write_buffer = '0' then
att_reg <= att_reg(6 downto 0)&'0';
end if;
lo_bits_prev := lo_bits;
source_bits_prev := source_bits;
att_bits_prev := att_bits;
if lo_bits /= to_unsigned(0, 6) then
lo_bits := lo_bits - to_unsigned(1, 6);
end if;
if source_bits /= to_unsigned(0, 6) then
source_bits := source_bits - to_unsigned(1, 6);
end if;
if att_bits /= to_unsigned(0, 6) then
att_bits := att_bits - to_unsigned(1, 6);
end if;
if lo_bits_prev = to_unsigned(1, 5) and lo_bits = to_unsigned(0, 5) then
spi_le_lo_int <= '1';
lo_done := '1';
lo_delay := to_unsigned(NEXT_DELAY, 8);
end if;
if source_bits_prev = to_unsigned(1, 5) and source_bits = to_unsigned(0, 5) then
spi_le_source_int <= '1';
source_done := '1';
source_delay := to_unsigned(NEXT_DELAY, 8);
end if;
if att_bits_prev = to_unsigned(1, 5) and att_bits = to_unsigned(0, 5) then
spi_le_att_int <= '1';
att_done := '1';
att_delay := to_unsigned(NEXT_DELAY, 8);
end if;
end if;
-- Start a new write on falling SPI clock edge
if spi_clk_en = '0' or (spi_clk_en = '1' and spi_clk_int = '1') then
if lo_write_buffer = '1' then
lo_write_buffer <= '0';
lo_bits := to_unsigned(32, 6);
lo_reg <= lo_data_in_buffer;
lo_done := '0';
end if;
if source_write_buffer = '1' then
source_write_buffer <= '0';
source_bits := to_unsigned(32, 6);
source_reg <= source_data_in_buffer;
source_done := '0';
end if;
if att_write_buffer = '1' then
att_write_buffer <= '0';
att_bits := to_unsigned(8, 6);
att_reg <= att_data_in_buffer;
att_done := '0';
end if;
end if;
else
count := count + to_unsigned(1, 8);
end if;
end if;
end process;
busy <= spi_clk_en;
spi_clk <= spi_clk_int;
spi_data_lo <= lo_reg(31);
spi_data_source <= source_reg(31);
spi_data_att <= att_reg(7);
-- Lengthen the LE pulse
le_process : process(clk, spi_le_lo_int, spi_le_source_int, spi_le_att_int, pipe_lo, pipe_source, pipe_att)
variable le_lo_or, le_source_or, le_att_or : std_logic := '0';
begin
if rising_edge(clk) then
pipe_source(0) <= spi_le_source_int;
pipe_lo(0) <= spi_le_lo_int;
pipe_att(0) <= spi_le_att_int;
le_lo_or := '0';
le_source_or := '0';
le_att_or := '0';
for i in 1 to LE_LENGTHEN-1 loop
pipe_source(i) <= pipe_source(i-1);
pipe_lo(i) <= pipe_lo(i-1);
pipe_att(i) <= pipe_att(i-1);
le_lo_or := le_lo_or or pipe_lo(i);
le_source_or := le_source_or or pipe_source(i);
le_att_or := le_att_or or pipe_att(i);
end loop;
spi_le_lo <= le_lo_or;
spi_le_source <= le_source_or;
spi_le_att <= le_att_or;
end if;
end process;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/imports/new/vna_top.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03.12.2016 10:06:15
-- Design Name:
-- Module Name: vna_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.vna_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity vna_top is
Port ( clk : in STD_LOGIC;
adc_in : in STD_LOGIC_VECTOR (13 downto 0);
adc_of : in STD_LOGIC;
adc_oe : out STD_LOGIC;
adc_shdn : out STD_LOGIC;
ft2232_data : inout STD_LOGIC_VECTOR (7 downto 0);
rxf : in STD_LOGIC;
txe : in STD_LOGIC;
rd : out STD_LOGIC;
wr : out STD_LOGIC;
si_wu : out STD_LOGIC;
tx_filter : out STD_LOGIC_VECTOR(3 downto 0);
port_sw : out STD_LOGIC_VECTOR (1 downto 0);
rx_sw : out STD_LOGIC_VECTOR (5 downto 0);
spi_clk : out STD_LOGIC;
lo_spi_data : out STD_LOGIC;
lo_le : out STD_LOGIC;
lo_ce : out STD_LOGIC;
lo_rf_enable : out STD_LOGIC;
lo_muxout : in STD_LOGIC;
source_muxout : in STD_LOGIC;
source_spi_data : out STD_LOGIC;
source_le : out STD_LOGIC;
source_ce : out STD_LOGIC;
source_rf_enable : out STD_LOGIC;
atten_spi_data : out STD_LOGIC;
atten_le : out STD_LOGIC;
lo_ld : in STD_LOGIC;
source_ld : in STD_LOGIC;
mixer_enable : out STD_LOGIC;
amp_pwdn : out STD_LOGIC;
dither : out STD_LOGIC;
xadc_vp : in STD_LOGIC;
xadc_vn : in STD_LOGIC;
led : out STD_LOGIC);
end vna_top;
architecture Behavioral of vna_top is
signal rst : std_logic := '0';
-- Receiver
signal i_acc, q_acc, cycles : STD_LOGIC_VECTOR(IQ_ACC_WIDTH-1 downto 0);
-- Early signal comes one clock cycle before
signal rx_start, rx_start_early : std_logic := '0';
-- Receiver control
signal rx_sample_time : std_logic_vector(31 downto 0);
signal rx_sample_time_valid : std_logic;
--FT2232
signal comm_data_out, comm_data_in : std_logic_vector(7 downto 0);
signal comm_data_in_valid : std_logic := '0';
signal comm_data_out_valid : std_logic;
signal comm_data_in_ack, comm_data_out_ack : std_logic := '0';
-- IO
signal lo_data, source_data : std_logic_vector(31 downto 0);
signal atten_data : std_logic_vector(7 downto 0);
signal lo_write, source_write, atten_write : std_logic := '0';
-- IQ packer
signal iq_tx_done : std_logic;
signal tx_mux_ctrl : std_logic_vector(1 downto 0);
signal samples_data_out : std_logic_vector(7 downto 0);
signal samples_data_valid, samples_data_ack : std_logic;
signal iq_data_out : std_logic_vector(7 downto 0);
signal iq_data_valid, iq_data_ack : std_logic;
signal dither_rst : std_logic;
signal sample_mux_ctrl : std_logic_vector(1 downto 0);
signal if_output : std_logic_vector(IF_WIDTH-1 downto 0);
signal receiver_hold : std_logic;
signal rx_sw_select : rx_sw_type;
signal rx_sw_mux_ctrl : std_logic;
signal rx_sw_io : std_logic_vector(5 downto 0);
signal lo_spi_ack, source_spi_ack, att_spi_ack : std_logic;
signal io_data_out : std_logic_vector(7 downto 0);
signal io_data_valid, io_data_ack : std_logic;
signal iq_tag : std_logic_vector(7 downto 0);
signal iq_tag_valid : std_logic;
signal last_byte_iq, last_byte : std_logic;
begin
receiver : entity work.receiver
Port map ( clk => clk,
rst => rst,
adc => adc_in,
i_acc => i_acc,
q_acc => q_acc,
cycles => cycles,
start => rx_start,
if_output => if_output,
receiver_hold => receiver_hold);
receiver_control : entity work.receiver_control
Port map ( clk => clk,
rst => rst,
start_early => rx_start_early,
start => rx_start,
sample_time => rx_sample_time,
sample_time_valid => rx_sample_time_valid,
receiver_hold => receiver_hold,
lo_ld => lo_ld,
source_ld => source_ld,
rx_sw => rx_sw_select,
tx_ready => iq_tx_done);
comm : entity work.comm
Port map ( clk => clk,
rst => rst,
ft2232_data => ft2232_data,
data_in_valid => comm_data_in_valid,
data_out => comm_data_out,
data_out_valid => comm_data_out_valid,
data_in => comm_data_in,
data_in_ack => comm_data_in_ack,
data_out_ack => comm_data_out_ack,
rxf => rxf,
txe => txe,
rd => rd,
wr => wr,
si_wu => si_wu,
last_byte => last_byte);
led <= lo_ld;
iq_packer : entity work.iq_packer
Port map ( clk => clk,
rst => rst,
start => rx_start_early,
done => iq_tx_done,
i_acc => i_acc,
q_acc => q_acc,
cycles => cycles,
data_out => iq_data_out,
data_valid => iq_data_valid,
data_ack => iq_data_ack,
rx_sw => rx_sw_select,
iq_tag_in => iq_tag,
iq_tag_valid => iq_tag_valid,
last_byte => last_byte_iq);
sample_packer : entity work.sample_packer
Port map (clk => clk,
rst => rst,
start => rx_start_early,
adc_in => adc_in,
if_output => if_output,
i_acc => i_acc,
data_out => samples_data_out,
data_valid => samples_data_valid,
data_ack => samples_data_ack,
sample_mux_ctrl => sample_mux_ctrl);
tx_mux : entity work.tx_mux
Port map (mux => tx_mux_ctrl,
data_out => comm_data_in,
data_valid => comm_data_in_valid,
data_ack => comm_data_in_ack,
samples_data => samples_data_out,
samples_data_valid => samples_data_valid,
samples_data_ack => samples_data_ack,
iq_data => iq_data_out,
iq_data_valid => iq_data_valid,
iq_data_ack => iq_data_ack,
io_data => io_data_out,
io_data_valid => io_data_valid,
io_data_ack => io_data_ack,
last_byte_iq => last_byte_iq,
last_byte => last_byte);
io_bank : entity work.io_bank
Port map ( clk => clk,
rst => rst,
data_in => comm_data_out,
data_valid => comm_data_out_valid,
data_in_ack => comm_data_out_ack,
data_out => io_data_out,
data_out_valid => io_data_valid,
data_out_ack => io_data_ack,
rx_sample_time => rx_sample_time,
rx_sample_time_valid => rx_sample_time_valid,
tx_filter => tx_filter,
port_sw => port_sw,
rx_sw => rx_sw_io,
rx_sw_mux_ctrl => rx_sw_mux_ctrl,
lo_spi_data => lo_data,
lo_spi_write => lo_write,
source_spi_data => source_data,
source_spi_write => source_write,
atten_spi_data => atten_data,
atten_spi_write => atten_write,
amp_pwdn => amp_pwdn,
mixer_enable => mixer_enable,
lo_ce => lo_ce,
source_ce => source_ce,
led => open,
adc_shdn => adc_shdn,
adc_oe => adc_oe,
source_rf_enable => source_rf_enable,
lo_rf_enable => lo_rf_enable,
tx_mux_ctrl => tx_mux_ctrl,
dither_rst => dither_rst,
sample_mux_ctrl => sample_mux_ctrl,
lo_spi_ack => lo_spi_ack,
source_spi_ack => source_spi_ack,
att_spi_ack => att_spi_ack,
iq_tag_out => iq_tag,
iq_tag_valid => iq_tag_valid);
rx_sw_mux : entity work.rx_sw_mux
Port map ( rx_sw_receiver => rx_sw_select,
rx_sw_io => rx_sw_io,
rx_sw => rx_sw,
ctrl => rx_sw_mux_ctrl);
spi3 : entity work.spi3
Generic map ( SPI_CLK_DIVIDER => 5)
Port map ( clk => clk,
rst => rst,
lo_data_in => lo_data,
source_data_in => source_data,
att_data_in => atten_data,
lo_write => lo_write,
source_write => source_write,
att_write => atten_write,
busy => open,
spi_clk => spi_clk,
spi_data_lo => lo_spi_data,
spi_data_source => source_spi_data,
spi_data_att => atten_spi_data,
spi_le_lo => lo_le,
spi_le_source => source_le,
spi_le_att => atten_le,
lo_ack => lo_spi_ack,
source_ack => source_spi_ack,
att_ack => att_spi_ack);
dither_generator : entity work.dither
Port map ( clk => clk,
rst => dither_rst,
q => dither);
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/acc_control.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.12.2016 18:31:48
-- Design Name:
-- Module Name: acc_control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.vna_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity acc_control is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
acc_reset : out STD_LOGIC;
receiver_hold : in STD_LOGIC);
end acc_control;
architecture Behavioral of acc_control is
begin
process(clk, rst)
variable i : unsigned(11 downto 0) := to_unsigned(0, 12);
begin
if rst = '1' then
i := to_unsigned(0, 12);
acc_reset <= '1';
elsif rising_edge(clk) then
acc_reset <= '1';
if i = SKIP_SAMPLES then
acc_reset <= receiver_hold;
else
if receiver_hold = '0' then
i := i + 1;
end if;
end if;
end if;
end process;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/accumulator.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 27.11.2016 19:47:49
-- Design Name:
-- Module Name: average - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity accumulator is
Generic (
IN_WIDTH : integer := 14;
OUT_WIDTH : integer := 32
);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
valid : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (IN_WIDTH-1 downto 0);
average : out STD_LOGIC_VECTOR (OUT_WIDTH-1 downto 0));
end accumulator;
architecture Behavioral of accumulator is
signal accum : signed(OUT_WIDTH-1 downto 0) := to_signed(0, OUT_WIDTH);
begin
process(clk, rst, valid, data)
begin
if rst = '1' then
accum <= to_signed(0, OUT_WIDTH);
elsif rising_edge(clk) then
average <= std_logic_vector(accum);
if valid = '1' then
accum <= accum + signed(data);
end if;
end if;
end process;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/comm.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 28.11.2016 20:21:11
-- Design Name:
-- Module Name: comm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity comm is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
ft2232_data : inout STD_LOGIC_VECTOR (7 downto 0);
data_in_valid : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0);
data_out_valid : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(7 downto 0);
data_in_ack : out STD_LOGIC;
data_out_ack : in STD_LOGIC;
rxf : in STD_LOGIC;
txe : in STD_LOGIC;
rd : out STD_LOGIC;
wr : out STD_LOGIC;
si_wu : out STD_LOGIC;
last_byte : in STD_LOGIC);
end comm;
architecture Behavioral of comm is
constant WRITE_WR_LENGTH : integer := 4; -- Clock cycles
constant READ_RD_LENGTH : integer := 4; -- Clock cycles
constant SI_WU_DELAY : integer := 2; -- Clock cycles
constant SI_WU_LENGTH : integer := 4; -- Clock cycles
signal reading : std_logic := '0';
signal ft2232_data_write : STD_LOGIC_VECTOR(7 downto 0) := (others => '1');
signal data_out_int : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal rxf_sync, txe_sync : std_logic := '1';
signal last_byte_int : std_logic := '0';
signal si_wu_out : std_logic := '1';
signal si_wu_pipe : std_logic_vector(SI_WU_DELAY - 1 downto 0) := (others => '1');
signal si_wu_lengthen : std_logic_vector(SI_WU_LENGTH - 1 downto 0) := (others => '1');
begin
sync_process : process(clk, rxf, txe)
variable rxf_sync2, txe_sync2 : std_logic := '1';
begin
if rising_edge(clk) then
txe_sync <= txe_sync2;
rxf_sync <= rxf_sync2;
txe_sync2 := txe;
rxf_sync2 := rxf;
end if;
end process;
process(clk, rst, data_out_ack, txe_sync, rxf_sync)
type ft_state_type is (S_START, S_TX_WR, S_TX_HOLD, S_RX_RD, S_RX_READ, S_RX_SEND, S_RX_WAIT);
variable state : ft_state_type := S_START;
variable pulse_count : unsigned(4 downto 0) := to_unsigned(0, 5);
begin
if rst = '1' then
ft2232_data_write <= (others => '1');
state := S_START;
pulse_count := to_unsigned(0, 5);
wr <= '1';
data_in_ack <= '0';
elsif rising_edge(clk) then
-- Default values
wr <= '1';
rd <= '1';
si_wu_out <= '1';
data_in_ack <= '0';
ft2232_data_write <= (others => '1');
if (state = S_TX_WR or state = S_TX_HOLD) then
reading <= '0';
else
reading <= '1';
end if;
case state is
when S_START =>
-- Priorize reading
if rxf_sync = '0' then
state := S_RX_RD;
rd <= '0';
pulse_count := to_unsigned(READ_RD_LENGTH, 5);
elsif data_in_valid = '1' and txe_sync = '0' then
state := S_TX_WR;
wr <= '1';
ft2232_data_write <= data_in;
last_byte_int <= last_byte;
pulse_count := to_unsigned(WRITE_WR_LENGTH, 5);
end if;
when S_TX_WR =>
-- Holds WR signal high
ft2232_data_write <= data_in;
if pulse_count = to_unsigned(0, 5) then
state := S_TX_HOLD;
wr <= '0'; -- Strobe WR to signal a write
pulse_count := to_unsigned(WRITE_WR_LENGTH, 5);
else
pulse_count := pulse_count - 1;
end if;
when S_TX_HOLD =>
-- Wait for TXE to rise
wr <= '0';
ft2232_data_write <= data_in;
if txe_sync = '1' then
data_in_ack <= '1';
state := S_START;
si_wu_out <= not last_byte_int;
end if;
when S_RX_RD =>
-- Holds RD signal low
rd <= '0';
if pulse_count = to_unsigned(0, 5) then
state := S_RX_READ;
else
pulse_count := pulse_count - 1;
end if;
when S_RX_READ =>
-- Read the data
rd <= '1';
data_out_int <= ft2232_data;
data_out_valid <= '1';
state := S_RX_SEND;
when S_RX_SEND =>
rd <= '1';
data_out_valid <= '1';
if data_out_ack = '1' then
data_out_valid <= '0';
state := S_RX_WAIT;
pulse_count := to_unsigned(READ_RD_LENGTH, 5);
end if;
when S_RX_WAIT =>
if rxf_sync = '1' or pulse_count = to_unsigned(0, 5) then
state := S_START;
else
pulse_count := pulse_count - 1;
end if;
when others =>
state := S_START;
end case;
end if;
end process;
si_wu_process : process(clk, si_wu_out)
variable si_wu_and : std_logic := '1';
begin
if rising_edge(clk) then
si_wu_pipe(0) <= si_wu_out;
si_wu_lengthen(0) <= si_wu_pipe(SI_WU_DELAY - 1);
for i in 1 to SI_WU_DELAY-1 loop
si_wu_pipe(i) <= si_wu_pipe(i-1);
end loop;
si_wu_and := si_wu_lengthen(0);
for i in 1 to SI_WU_LENGTH-1 loop
si_wu_lengthen(i) <= si_wu_lengthen(i-1);
si_wu_and := si_wu_and and si_wu_lengthen(i);
end loop;
end if;
si_wu <= si_wu_and;
end process;
data_out <= data_out_int;
ft2232_data <= (others => 'Z') when reading = '1' else ft2232_data_write;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/dither.vhd
================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dither is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : out STD_LOGIC);
end dither;
architecture Behavioral of dither is
constant OUT_WIDTH : integer := 8;
component lfsr is
generic ( SEED : STD_LOGIC_VECTOR(30 downto 0);
OUT_WIDTH : integer);
port(
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (OUT_WIDTH-1 downto 0);
rst : in STD_LOGIC);
end component;
signal uniform1 : std_logic_vector(OUT_WIDTH-1 downto 0);
begin
unif1: lfsr
generic map (SEED => std_logic_vector(to_unsigned(697757461,31)),
OUT_WIDTH => OUT_WIDTH)
port map(
clk => clk,
q => uniform1,
rst => rst
);
q <= uniform1(0);
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/file_adc.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14.02.2017 21:18:56
-- Design Name:
-- Module Name: file_adc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use std.textio.all; --include package textio.vhd
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity file_adc is
Generic (in_file : string := "samples.txt");
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
adc_out : out STD_LOGIC_VECTOR (13 downto 0));
end file_adc;
architecture Behavioral of file_adc is
constant DEPTH : integer := 5000;
subtype word_t is std_logic_vector(13 downto 0);
type ram_t is array(0 to DEPTH-1) of word_t;
-- Read a *.hex file
impure function ocram_ReadMemFile(FileName : STRING) return ram_t is
file infile : text is in FileName;
variable inline : line; --line number declaration
variable dataread1 : integer;
variable Result : ram_t := (others => (others => '0'));
begin
for i in 0 to DEPTH - 1 loop
exit when endfile(infile);
readline(infile, inline);
read(inline, dataread1);
Result(i) := std_logic_vector(to_signed(dataread1, 14));
end loop;
return Result;
end function;
signal ram : ram_t := ocram_ReadMemFile(in_file);
signal pointer : integer := 0;
begin
process(clk, rst)
begin
if rst = '1' then
pointer <= 0;
elsif rising_edge(clk) then
if pointer < DEPTH - 1 then
pointer <= pointer + 1;
else
pointer <= 0;
end if;
end if;
end process;
adc_out <= ram(pointer);
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/io_bank.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 28.11.2016 20:46:04
-- Design Name:
-- Module Name: io_bank - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.vna_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity io_bank is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (7 downto 0);
data_valid : in STD_LOGIC;
data_in_ack : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0);
data_out_valid : out STD_LOGIC;
data_out_ack : in STD_LOGIC;
rx_sample_time : out STD_LOGIC_VECTOR(31 downto 0);
rx_sample_time_valid : out STD_LOGIC;
tx_filter : out STD_LOGIC_VECTOR(3 downto 0);
port_sw : out STD_LOGIC_VECTOR (1 downto 0);
rx_sw : out STD_LOGIC_VECTOR (5 downto 0);
rx_sw_mux_ctrl : out STD_LOGIC;
lo_spi_data : out STD_LOGIC_VECTOR(31 downto 0);
lo_spi_write : out std_logic;
source_spi_data : out STD_LOGIC_VECTOR(31 downto 0);
source_spi_write : out STD_LOGIC;
atten_spi_data : out STD_LOGIC_VECTOR(7 downto 0);
atten_spi_write : out STD_LOGIC;
amp_pwdn : out STD_LOGIC;
mixer_enable : out STD_LOGIC;
lo_ce : out STD_LOGIC;
source_ce : out STD_LOGIC;
led : out STD_LOGIC;
adc_shdn : out STD_LOGIC;
adc_oe : out STD_LOGIC;
source_rf_enable : out STD_LOGIC;
lo_rf_enable : out STD_LOGIC;
tx_mux_ctrl : out STD_LOGIC_VECTOR(1 downto 0);
dither_rst : out STD_LOGIC;
sample_mux_ctrl : out STD_LOGIC_VECTOR(1 downto 0);
lo_spi_ack : in STD_LOGIC;
source_spi_ack : in STD_LOGIC;
att_spi_ack : in STD_LOGIC;
iq_tag_out : out STD_LOGIC_VECTOR(7 downto 0);
iq_tag_valid : out STD_LOGIC);
end io_bank;
architecture Behavioral of io_bank is
constant MAX_PACKET_LENGTH : integer := 8;
type memory_type is array (0 to MAX_PACKET_LENGTH-1) of std_logic_vector(7 downto 0);
signal memory : memory_type := (others => (others => '0'));
signal port_sw_int: std_logic_vector(1 downto 0) := "00";
signal tx_filter_int : std_logic_vector(3 downto 0) := "0000";
signal rx_sw_int : std_logic_vector(5 downto 0) := "000000";
signal amp_pwdn_int, mixer_enable_int, led_int : std_logic := '0';
signal adc_oe_int, adc_shdn_int : std_logic := '1';
signal source_rf_enable_int, lo_rf_enable_int : std_logic := '0';
signal lo_ce_int, source_ce_int : std_logic := '0';
signal rx_sample_time_int : std_logic_vector(31 downto 0) := (others => '0');
signal rx_sample_time_valid_int : std_logic := '0';
signal tx_mux_ctrl_int : std_logic_vector(1 downto 0) := "00";
signal dither_rst_int : std_logic := '0';
signal sample_mux_ctrl_int : std_logic_vector(1 downto 0) := "00";
signal rx_sw_mux_ctrl_int : std_logic := '0';
signal iq_tag_out_int : std_logic_vector(7 downto 0) := (others => '0');
signal valid_prev : std_logic := '0';
signal write_word : std_logic_vector(7 downto 0);
signal new_write, writing : std_logic := '0';
begin
process(clk, rst, data_in, data_valid, data_out_ack)
type comm_state_type is (S_START, S_LENGTH, S_ID, S_DATA, S_PROCESS_DATA);
variable state : comm_state_type := S_START;
variable data_length : unsigned(7 downto 0) := to_unsigned(0, 8);
variable data_counter : unsigned(7 downto 0) := to_unsigned(0, 8);
variable ready : std_logic := '1';
variable data_id : unsigned(7 downto 0) := to_unsigned(0, 8);
begin
if rst = '1' then
state := S_START;
data_length := to_unsigned(0, 8);
ready := '1';
data_id := to_unsigned(0, 8);
valid_prev <= '0';
amp_pwdn_int <= '0';
mixer_enable_int <= '0';
led_int <= '0';
tx_filter_int <= (others => '0');
adc_oe_int <= '1';
adc_shdn_int <= '1';
source_rf_enable_int <= '0';
lo_rf_enable_int <= '0';
elsif rising_edge(clk) then
lo_spi_write <= '0';
source_spi_write <= '0';
atten_spi_write <= '0';
data_in_ack <= '0';
rx_sample_time_valid_int <= '0';
valid_prev <= '0';
new_write <= '0';
iq_tag_valid <= '0';
if new_write = '1' then
data_out <= write_word;
data_out_valid <= '1';
writing <= '1';
elsif writing = '1' then
data_out_valid <= '1';
if data_out_ack = '1' then
writing <= '0';
data_out_valid <= '0';
end if;
else
data_out_valid <= '0';
end if;
-- data_valid is high for 2 clock cycles, so we need to make
-- sure that data is loaded only at first cycle with valid_prev signal
if ready = '1' and data_valid = '1' and valid_prev = '0' then
data_in_ack <= '1';
valid_prev <= '1';
case state is
when S_START =>
if data_in = COMM_START then
state := S_LENGTH;
end if;
when S_LENGTH =>
data_length := unsigned(data_in);
data_counter := to_unsigned(0, 8);
state := S_ID;
when S_ID =>
data_id := unsigned(data_in);
state := S_DATA;
when S_DATA =>
memory(to_integer(data_counter)) <= data_in;
if data_counter /= MAX_PACKET_LENGTH-1 then
data_counter := data_counter + 1;
end if;
if data_counter = data_length then
state := S_PROCESS_DATA;
ready := '0';
end if;
when others =>
state := S_START;
end case;
elsif ready = '0' then
case state is
when S_PROCESS_DATA =>
-- Do the stuff
case data_id is
when to_unsigned(0, 8) =>
-- Invalid
ready := '1';
state := S_START;
when to_unsigned(1, 8) =>
if data_length = to_unsigned(2, 8) then
tx_filter_int <= memory(0)(3 downto 0);
port_sw_int <= memory(0)(5 downto 4);
rx_sw_int <= memory(1)(5 downto 0);
rx_sw_mux_ctrl_int <= memory(1)(6);
end if;
ready := '1';
state := S_START;
when to_unsigned(2, 8) =>
if data_length = to_unsigned(1, 8) then
amp_pwdn_int <= memory(0)(0);
mixer_enable_int <= memory(0)(1);
led_int <= memory(0)(2);
adc_oe_int <= memory(0)(3);
adc_shdn_int <= memory(0)(4);
end if;
ready := '1';
state := S_START;
when to_unsigned(3, 8) =>
if data_length = to_unsigned(4, 8) then
lo_spi_data <= memory(0)&memory(1)&memory(2)&memory(3);
lo_spi_write <= '1';
else
ready := '1';
state := S_START;
end if;
if lo_spi_ack = '1' then
ready := '1';
state := S_START;
end if;
when to_unsigned(4, 8) =>
if data_length = to_unsigned(4, 8) then
source_spi_data <= memory(0)&memory(1)&memory(2)&memory(3);
source_spi_write <= '1';
else
ready := '1';
state := S_START;
end if;
if source_spi_ack = '1' then
ready := '1';
state := S_START;
end if;
when to_unsigned(5, 8) =>
if data_length = to_unsigned(4, 8) then
rx_sample_time_int <= memory(0)&memory(1)&memory(2)&memory(3);
rx_sample_time_valid_int <= '1';
end if;
ready := '1';
state := S_START;
when to_unsigned(6, 8) =>
if data_length = to_unsigned(1, 8) then
atten_spi_data <= memory(0);
atten_spi_write <= '1';
else
ready := '1';
state := S_START;
end if;
if att_spi_ack = '1' then
ready := '1';
state := S_START;
end if;
when to_unsigned(7, 8) =>
if data_length = to_unsigned(1, 8) then
lo_ce_int <= memory(0)(0);
source_ce_int <= memory(0)(1);
source_rf_enable_int <= memory(0)(2);
lo_rf_enable_int <= memory(0)(3);
end if;
ready := '1';
state := S_START;
when to_unsigned(8, 8) =>
if data_length = to_unsigned(1, 8) then
tx_mux_ctrl_int <= memory(0)(1 downto 0);
sample_mux_ctrl_int <= memory(0)(3 downto 2);
end if;
ready := '1';
state := S_START;
when to_unsigned(9, 8) =>
if data_length = to_unsigned(1, 8) then
dither_rst_int <= memory(0)(0);
end if;
ready := '1';
state := S_START;
when to_unsigned(10, 8) =>
if writing = '0' then
new_write <= '1';
write_word <= memory(0);
end if;
ready := '1';
state := S_START;
when to_unsigned(11, 8) =>
iq_tag_out_int <= memory(0);
iq_tag_valid <= '1';
ready := '1';
state := S_START;
when others =>
ready := '1';
state := S_START;
end case;
when others =>
-- Shouldn't be here
state := S_START;
ready := '1';
end case;
end if;
end if;
end process;
tx_filter <= tx_filter_int;
port_sw <= port_sw_int;
rx_sw <= rx_sw_int;
amp_pwdn <= amp_pwdn_int;
mixer_enable <= mixer_enable_int;
led <= led_int;
adc_oe <= adc_oe_int;
adc_shdn <= adc_shdn_int;
source_rf_enable <= source_rf_enable_int;
lo_rf_enable <= lo_rf_enable_int;
lo_ce <= lo_ce_int;
source_ce <= source_ce_int;
rx_sample_time <= rx_sample_time_int;
rx_sample_time_valid <= rx_sample_time_valid_int;
tx_mux_ctrl <= tx_mux_ctrl_int;
dither_rst <= dither_rst_int;
sample_mux_ctrl <= sample_mux_ctrl_int;
rx_sw_mux_ctrl <= rx_sw_mux_ctrl_int;
iq_tag_out <= iq_tag_out_int;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/iq_packer.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.12.2016 19:46:05
-- Design Name:
-- Module Name: iq_packer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.vna_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity iq_packer is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
start : in STD_LOGIC;
done : out STD_LOGIC;
i_acc : in STD_LOGIC_VECTOR (IQ_ACC_WIDTH-1 downto 0);
q_acc : in STD_LOGIC_VECTOR (IQ_ACC_WIDTH-1 downto 0);
cycles : in STD_LOGIC_VECTOR (IQ_ACC_WIDTH-1 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0);
data_valid : out STD_LOGIC;
data_ack : in STD_LOGIC;
rx_sw : in rx_sw_type;
iq_tag_in : in STD_LOGIC_VECTOR(7 downto 0);
iq_tag_valid : in STD_LOGIC;
last_byte : out STD_LOGIC);
end iq_packer;
architecture Behavioral of iq_packer is
-- Start, Length, id = 3
-- I, Q, cycles 7 bytes = 21
-- RX_SW, tag 2
constant packet_size : integer := 3+3*IQ_BYTES+2;
type memory_type is array (0 to packet_size-1) of std_logic_vector(7 downto 0);
signal packet_memory : memory_type := (0 => COMM_START, 1 => std_logic_vector(to_unsigned(packet_size-1, 8)), 2 => "00000001", others => (others => '0'));
signal queue_full : std_logic := '0';
signal start_delay : std_logic := '0';
signal iq_tag : std_logic_vector(7 downto 0) := (others => '0');
begin
queue_fill_process : process(clk, start, i_acc, q_acc, cycles, queue_full, start_delay)
variable rx_sw_delay : rx_sw_type;
variable rx_sw_write : std_logic_vector(2 downto 0);
variable sent : unsigned(7 downto 0) := to_unsigned(0, 8);
begin
if rising_edge(clk) then
last_byte <= '0';
if iq_tag_valid = '1' then
packet_memory(3+3*IQ_BYTES+1) <= iq_tag_in;
end if;
data_out <= packet_memory(to_integer(sent));
data_valid <= '0';
start_delay <= start;
-- Don't write new values if still sending the old ones
if start = '1' and queue_full = '0' then
for i in 0 to IQ_BYTES-1 loop
packet_memory(3+i) <= i_acc(8*(i+1)-1 downto 8*i);
packet_memory(3+IQ_BYTES+i) <= q_acc(8*(i+1)-1 downto 8*i);
packet_memory(3+2*IQ_BYTES+i) <= cycles(8*(i+1)-1 downto 8*i);
end loop;
case rx_sw_delay is
when SW_RX1 =>
rx_sw_write := "001";
when SW_A =>
rx_sw_write := "010";
when SW_RX2 =>
rx_sw_write := "011";
when SW_B =>
rx_sw_write := "100";
when others =>
rx_sw_write := (others => '0');
end case;
packet_memory(3+3*IQ_BYTES) <= "00000"&rx_sw_write;
end if;
rx_sw_delay := rx_sw;
if start_delay = '1' or queue_full = '1' then
queue_full <= '1';
data_valid <= '1';
if sent = to_unsigned(packet_size-1, 8) then
last_byte <= '1';
end if;
if sent = to_unsigned(packet_size-1, 8) and data_ack = '1' then
queue_full <= '0';
sent := to_unsigned(0, 8);
elsif data_ack = '1' then
sent := sent + 1;
end if;
end if;
end if;
end process;
done <= not queue_full;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/lfsr.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11.02.2017 15:57:28
-- Design Name:
-- Module Name: lfsr - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lfsr is
generic ( SEED : STD_LOGIC_VECTOR(30 downto 0):= (others => '0');
OUT_WIDTH : integer := 11);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (OUT_WIDTH-1 downto 0));
end lfsr;
architecture Behavioral of lfsr is
signal rand : std_logic_vector(30 downto 0) := SEED;
signal feedback : std_logic;
begin
feedback <= not((rand(0) xor rand(3)));
process(clk,rst)
begin
if rst = '1' then
rand <= SEED;
elsif rising_edge(clk) then
rand <= feedback&rand(30 downto 1);
end if;
end process;
q <= rand(OUT_WIDTH-1 downto 0);
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/lo.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 27.11.2016 12:23:09
-- Design Name:
-- Module Name: lo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lo is
Generic (
BIT_WIDTH : integer := 14;
TABLE_SIZE : integer := 5;
TABLE_WIDTH : integer := 3;
COS : boolean := false
);
Port ( rst : in std_logic;
clk : in STD_LOGIC;
lo_out : out STD_LOGIC_VECTOR (BIT_WIDTH-1 downto 0));
end lo;
architecture Behavioral of lo is
type table_type is array (0 to TABLE_SIZE) of std_logic_vector(BIT_WIDTH-1 downto 0);
signal table : table_type := (
0 => std_logic_vector(to_signed(0, BIT_WIDTH)),
1 => std_logic_vector(to_signed(2531, BIT_WIDTH)),
2 => std_logic_vector(to_signed(4814, BIT_WIDTH)),
3 => std_logic_vector(to_signed(6626, BIT_WIDTH)),
4 => std_logic_vector(to_signed(7790, BIT_WIDTH)),
5 => std_logic_vector(to_signed(8191, BIT_WIDTH)),
others => (others => '0')
);
function init_i(cos : in boolean) return unsigned is
begin
if cos then
return to_unsigned(TABLE_SIZE, TABLE_WIDTH);
end if;
return to_unsigned(0, TABLE_WIDTH);
end function;
function init_dir(cos : in boolean) return std_logic is
begin
if cos then
return '1';
end if;
return '0';
end function;
signal index : unsigned(TABLE_WIDTH-1 downto 0) := init_i(COS);
signal sign: std_logic := '0';
begin
process(clk, rst)
variable direction : std_logic := init_dir(COS);
begin
if rst = '1' then
if COS then
index <= to_unsigned(TABLE_SIZE, TABLE_WIDTH);
sign <= '0';
direction := '1';
else
index <= to_unsigned(0, TABLE_WIDTH);
sign <= '0';
direction := '0';
end if;
elsif rising_edge(clk) then
if index = TABLE_SIZE then
direction := '1';
end if;
if index = 0 then
direction := '0';
sign <= not sign;
end if;
if direction = '0' then
index <= index+1;
else
index <= index-1;
end if;
end if;
end process;
lo_out <= table(to_integer(index)) when sign = '0' else std_logic_vector(-signed(table(to_integer(index))));
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/mixer.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 27.11.2016 10:07:32
-- Design Name:
-- Module Name: mixer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mixer is
Generic (
RF_WIDTH : integer := 14;
LO_WIDTH : integer := 16;
IF_WIDTH : integer := 16
);
Port ( clk : in std_logic;
rf : in STD_LOGIC_VECTOR (RF_WIDTH-1 downto 0);
lo : in STD_LOGIC_VECTOR (LO_WIDTH-1 downto 0);
if_out : out STD_LOGIC_VECTOR (IF_WIDTH-1 downto 0));
end mixer;
architecture Behavioral of mixer is
constant level : integer := 2;
type pipeline_type is array (level-1 downto 0) of std_logic_vector(RF_WIDTH+LO_WIDTH-1 downto 0);
signal pipe : pipeline_type := (others => (others => '0'));
signal a : std_logic_vector(RF_WIDTH-1 downto 0) := (others => '0');
signal b : std_logic_vector(LO_WIDTH-1 downto 0) := (others => '0');
signal non_rounded, rounded : std_logic_vector(IF_WIDTH-1 downto 0) := (others => '0');
begin
process(clk, rf, lo)
variable m : std_logic_vector(RF_WIDTH+LO_WIDTH-1 downto 0);
begin
if rising_edge(clk) then
a <= rf;
b <= lo;
m := std_logic_vector(signed(a)*signed(b));
pipe(0) <= m;
for i in 1 to level-1 loop
pipe(i) <= pipe(i-1);
end loop;
end if;
end process;
round_towards_zero : process(clk, pipe)
variable pipe_if : std_logic_vector(IF_WIDTH-1 downto 0);
begin
if rising_edge(clk) then
pipe_if := pipe(level-1)(RF_WIDTH+LO_WIDTH-1 downto RF_WIDTH+LO_WIDTH-IF_WIDTH);
non_rounded <= pipe_if;
rounded <= std_logic_vector(signed(pipe_if) + 1);
end if;
end process;
if_out <= rounded when non_rounded(IF_WIDTH-1) = '1' else non_rounded;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/pwr_sync_gen.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10.01.2017 21:00:45
-- Design Name:
-- Module Name: pwr_sync_gen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pwr_sync_gen is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
sync1 : out STD_LOGIC);
end pwr_sync_gen;
architecture Behavioral of pwr_sync_gen is
begin
pwr_sync_process : process(clk)
variable count : unsigned(7 downto 0) := to_unsigned(0, 8);
begin
end process;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/receiver.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 27.11.2016 20:03:05
-- Design Name:
-- Module Name: receiver - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.vna_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity receiver is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
adc : in STD_LOGIC_VECTOR (13 downto 0);
i_acc : out STD_LOGIC_VECTOR(IQ_ACC_WIDTH-1 downto 0);
q_acc : out STD_LOGIC_VECTOR(IQ_ACC_WIDTH-1 downto 0);
cycles : out STD_LOGIC_VECTOR(IQ_ACC_WIDTH-1 downto 0);
start : in STD_LOGIC;
if_output : out STD_LOGIC_VECTOR(IF_WIDTH-1 downto 0);
receiver_hold : in STD_LOGIC);
end receiver;
architecture Behavioral of receiver is
signal acc_rst : std_logic;
signal if_i, if_q : std_logic_vector(IF_WIDTH-1 downto 0);
signal acc_control_rst : std_logic;
begin
downconverter_0 : entity work.downconvert
Port map( clk => clk,
rst => rst,
adc => adc,
if_i_out => if_i,
if_q_out => if_q);
accumulator_i : entity work.accumulator
Generic map (
IN_WIDTH => IF_WIDTH,
OUT_WIDTH => IQ_ACC_WIDTH
)
Port map ( clk => clk,
rst => acc_rst,
valid => '1',
data => if_i,
average => i_acc
);
accumulator_q : entity work.accumulator
Generic map (
IN_WIDTH => IF_WIDTH,
OUT_WIDTH => IQ_ACC_WIDTH
)
Port map ( clk => clk,
rst => acc_rst,
valid => '1',
data => if_q,
average => q_acc
);
accumulator_cycles : entity work.accumulator
Generic map (
IN_WIDTH => 2,
OUT_WIDTH => IQ_ACC_WIDTH
)
Port map ( clk => clk,
rst => acc_rst,
valid => '1',
data => "01",
average => cycles
);
acc_control : entity work.acc_control
Port map ( clk => clk,
rst => acc_control_rst,
receiver_hold => receiver_hold,
acc_reset => acc_rst
);
acc_control_rst <= start or rst;
if_output <= if_i;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/receiver_control.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05.12.2016 20:44:41
-- Design Name:
-- Module Name: receiver_control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.vna_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity receiver_control is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
start_early : out STD_LOGIC;
start : out STD_LOGIC;
sample_time : in STD_LOGIC_VECTOR (31 downto 0);
sample_time_valid : in STD_LOGIC;
receiver_hold : out STD_LOGIC;
lo_ld : in STD_LOGIC;
source_ld : in STD_LOGIC;
rx_sw : out rx_sw_type;
tx_ready : in STD_LOGIC);
end receiver_control;
architecture Behavioral of receiver_control is
signal sample_time_int, sample_time_int_next : STD_LOGIC_VECTOR (31 downto 0) := (15 => '1', others => '0');
signal start_int : std_logic := '0';
signal rx_sw_int : rx_sw_type := SW_RX1;
signal lo_ld_sync, source_ld_sync : std_logic := '0';
begin
sample_time_update : process(clk, sample_time, sample_time_valid)
begin
if rising_edge(clk) then
if sample_time_valid = '1' then
sample_time_int_next <= sample_time;
end if;
end if;
end process;
start_generator : process(clk, rst, sample_time_int, rx_sw_int, lo_ld_sync, source_ld_sync, tx_ready)
variable counter : unsigned(31 downto 0) := to_unsigned(0, 32);
variable locked_cycles : unsigned(15 downto 0) := to_unsigned(0, 16);
begin
if rst = '1' then
counter := to_unsigned(0, 32);
elsif rising_edge(clk) then
start_int <= '0';
receiver_hold <= '1';
if lo_ld_sync = '0' or source_ld_sync = '0' then
-- No lock: reset receiver
locked_cycles := to_unsigned(0, 16);
counter := to_unsigned(0, 32);
end if;
if locked_cycles = LOCK_CYCLES then
receiver_hold <= '0';
if std_logic_vector(counter) >= sample_time_int and tx_ready = '1' then
start_int <= '1';
counter := to_unsigned(0, 32);
sample_time_int <= sample_time_int_next;
-- Next receiver channel
case rx_sw_int is
when SW_RX1 =>
rx_sw_int <= SW_A;
when SW_A =>
rx_sw_int <= SW_RX2;
when SW_RX2 =>
rx_sw_int <= SW_B;
when SW_B =>
rx_sw_int <= SW_RX1;
when others =>
rx_sw_int <= SW_RX1;
end case;
else
counter := counter + 1;
end if;
else
locked_cycles := locked_cycles + to_unsigned(1, 16);
end if;
end if;
end process;
late_start : process(clk, start_int)
begin
if rising_edge(clk) then
start <= start_int;
end if;
end process;
sync_process : process(clk, lo_ld, source_ld)
variable lo_sync2, source_sync2 : std_logic := '0';
begin
if rising_edge(clk) then
lo_ld_sync <= lo_sync2;
source_ld_sync <= source_sync2;
lo_sync2 := lo_ld;
source_sync2 := source_ld;
end if;
end process;
start_early <= start_int;
rx_sw <= rx_sw_int;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/rx_sw_mux.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16.02.2017 19:01:41
-- Design Name:
-- Module Name: rx_sw_mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.vna_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rx_sw_mux is
Port ( rx_sw_receiver : in rx_sw_type;
rx_sw_io : in STD_LOGIC_VECTOR(5 downto 0);
rx_sw : out STD_LOGIC_VECTOR(5 downto 0);
ctrl : in STD_LOGIC);
end rx_sw_mux;
architecture Behavioral of rx_sw_mux is
signal rx_sw_receiver_vector : std_logic_vector(5 downto 0);
begin
rx_sw_receiver_vector <= "100010" when rx_sw_receiver = SW_RX1 else
"100001" when rx_sw_receiver = SW_A else
"011000" when rx_sw_receiver = SW_B else
"010100" when rx_sw_receiver = SW_RX2 else
"000000";
rx_sw <= rx_sw_io when ctrl = '1' else rx_sw_receiver_vector;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/rx_switch.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 27.11.2016 18:43:45
-- Design Name:
-- Module Name: rx_switch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rx_switch is
-- Port ( );
end rx_switch;
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 27.11.2016 15:33:21
-- Design Name:
-- Module Name: port_switch - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.vna_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rx_switch is
Port ( rx_port : in rx_port_type;
term : in STD_LOGIC;
swa_ctrl : out STD_LOGIC_VECTOR (1 downto 0);
swb_ctrl : out STD_LOGIC_VECTOR (1 downto 0);
swc_ctrl : out STD_LOGIC_VECTOR (1 downto 0));
end rx_switch;
architecture Behavioral of rx_switch is
begin
process(rx_port, term)
begin
if term = '1' then
swa_ctrl <= "00";
swb_ctrl <= "00";
swc_ctrl <= "00";
else
if rx_port = P_A then
swa_ctrl <= "10";
swb_ctrl <= "10";
swc_ctrl <= "01";
else
swa_ctrl <= "01";
swb_ctrl <= "01";
swc_ctrl <= "10";
end if;
end if;
end process;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/source_agc.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.12.2016 18:29:18
-- Design Name:
-- Module Name: source_agc - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.vna_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity source_agc is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
locked : in STD_LOGIC;
target : in STD_LOGIC_VECTOR (15 downto 0);
xadc_vp : in STD_LOGIC;
xadc_vn : in STD_LOGIC;
adc_result : out STD_LOGIC_VECTOR (15 downto 0);
att_data : out STD_LOGIC_VECTOR(9 downto 0);
att_write : out STD_LOGIC;
set_target : in STD_LOGIC);
end source_agc;
architecture Behavioral of source_agc is
COMPONENT xadc_wiz_0
PORT (
di_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
daddr_in : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
den_in : IN STD_LOGIC;
dwe_in : IN STD_LOGIC;
drdy_out : OUT STD_LOGIC;
do_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
dclk_in : IN STD_LOGIC;
reset_in : IN STD_LOGIC;
vp_in : IN STD_LOGIC;
vn_in : IN STD_LOGIC;
user_temp_alarm_out : OUT STD_LOGIC;
vccint_alarm_out : OUT STD_LOGIC;
vccaux_alarm_out : OUT STD_LOGIC;
ot_out : OUT STD_LOGIC;
channel_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
eoc_out : OUT STD_LOGIC;
alarm_out : OUT STD_LOGIC;
eos_out : OUT STD_LOGIC;
busy_out : OUT STD_LOGIC
);
END COMPONENT;
signal di_in, do_out : std_logic_vector(15 downto 0);
signal daddr_in : std_logic_vector(6 downto 0);
signal den_in, dwe_in : std_logic := '0';
signal drdy_out : std_logic;
signal user_temp_alarm_out, vccint_alarm_out, vccaux_alarm_out, ot_out : std_logic;
signal channel_out : std_logic_vector(4 downto 0);
signal eoc_out, alarm_out, eos_out, busy_out : std_logic;
signal target_int : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(AGC_TARGET, 16));
begin
xadc : xadc_wiz_0
PORT MAP (
di_in => di_in,
daddr_in => daddr_in,
den_in => den_in,
dwe_in => dwe_in,
drdy_out => drdy_out,
do_out => do_out,
dclk_in => clk,
reset_in => rst,
vp_in => xadc_vp,
vn_in => xadc_vn,
user_temp_alarm_out => user_temp_alarm_out,
vccint_alarm_out => vccint_alarm_out,
vccaux_alarm_out => vccaux_alarm_out,
ot_out => ot_out,
channel_out => channel_out,
eoc_out => eoc_out,
alarm_out => alarm_out,
eos_out => eos_out,
busy_out => busy_out
);
process(clk, rst, target, set_target)
begin
if rst = '1' then
target_int <= std_logic_vector(to_unsigned(AGC_TARGET, 16));
elsif rising_edge(clk) then
if set_target = '1' then
target_int <= target;
end if;
end if;
end process;
process(clk, rst)
begin
if rst = '1' then
--
elsif rising_edge(clk) then
-- TODO: Intelligent calculation
if drdy_out = '1' then
end if;
end if;
end process;
adc_result <= do_out;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/spi_write.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01.12.2016 18:06:25
-- Design Name:
-- Module Name: spi_write - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity spi_write is
Generic (SPI_CLK_DIVIDER : integer := 1;
DATA_LENGTH : integer := 8);
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
spi_clk : out STD_LOGIC;
spi_data : out STD_LOGIC;
spi_cs : out STD_LOGIC;
data_in : in STD_LOGIC_VECTOR (DATA_LENGTH-1 downto 0);
data_in_valid : in STD_LOGIC;
data_in_ack : out STD_LOGIC);
end spi_write;
architecture Behavioral of spi_write is
constant SPI_CLOCK : unsigned(7 downto 0) := to_unsigned(SPI_CLK_DIVIDER, 8);
signal spi_clk_int : std_logic := '0';
begin
write_process : process(clk, rst, data_in, data_in_valid)
variable bit_counter : unsigned(7 downto 0) := to_unsigned(DATA_LENGTH-1, 8);
variable clk_counter : unsigned(7 downto 0) := to_unsigned(0, 8);
variable done : std_logic := '0';
type spi_state is (S_START, S_CS, S_WRITE);
variable state : spi_state := S_START;
variable data_in_valid_prev : std_logic := '0';
begin
if rst = '1' then
bit_counter := to_unsigned(DATA_LENGTH-1, 8);
spi_cs <= '1';
spi_clk_int <= '0';
data_in_ack <= '0';
spi_data <= '0';
done := '0';
state := S_START;
data_in_valid_prev := '0';
elsif rising_edge(clk) then
data_in_ack <= '0';
done := '0';
case state is
when S_START =>
bit_counter := to_unsigned(DATA_LENGTH-1, 8);
if data_in_valid = '1' then
spi_cs <= '0';
state := S_CS;
spi_data <= data_in(to_integer(unsigned(bit_counter)));
end if;
when S_WRITE =>
if data_in_valid = '1' then
spi_cs <= '0';
spi_data <= data_in(to_integer(unsigned(bit_counter)));
if clk_counter = to_unsigned(SPI_CLK_DIVIDER, 8) then
if spi_clk_int = '0' then
if bit_counter = to_unsigned(0, 8) then
data_in_ack <= '1';
spi_cs <= '1';
done := '1';
state := S_START;
else
bit_counter := bit_counter - 1;
end if;
end if;
if done = '0' then
spi_clk_int <= not spi_clk_int;
end if;
else
clk_counter := clk_counter + 1;
end if;
else
spi_cs <= '1';
bit_counter := to_unsigned(DATA_LENGTH-1, 8);
end if;
when S_CS =>
-- Hold CS for one clock
spi_cs <= '0';
spi_data <= data_in(to_integer(unsigned(bit_counter)));
state := S_WRITE;
when others =>
state := S_START;
end case;
end if;
end process;
spi_clk <= spi_clk_int;
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/tx_mux.vhd
================================================
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12.02.2017 21:13:49
-- Design Name:
-- Module Name: tx_mux - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tx_mux is
Port ( mux : in STD_LOGIC_VECTOR(1 downto 0);
data_out : out STD_LOGIC_VECTOR (7 downto 0);
data_valid : out STD_LOGIC;
data_ack : in STD_LOGIC;
samples_data :in STD_LOGIC_VECTOR (7 downto 0);
samples_data_valid : in STD_LOGIC;
samples_data_ack : out STD_LOGIC;
iq_data :in STD_LOGIC_VECTOR (7 downto 0);
iq_data_valid : in STD_LOGIC;
iq_data_ack : out STD_LOGIC;
io_data : in STD_LOGIC_VECTOR(7 downto 0);
io_data_valid : in STD_LOGIC;
io_data_ack : out STD_LOGIC;
last_byte_iq : in STD_LOGIC;
last_byte : out STD_LOGIC);
end tx_mux;
architecture Behavioral of tx_mux is
begin
data_out <= iq_data when mux = "00" else
samples_data when mux = "01" else
io_data;
data_valid <= iq_data_valid when mux = "00" else
samples_data_valid when mux = "01" else
io_data_valid;
last_byte <= last_byte_iq when mux = "00" else '0';
iq_data_ack <= data_ack when mux = "00" else '0';
samples_data_ack <= data_ack when mux = "01" else '0';
io_data_ack <= data_ack when mux = "10" else '0';
end Behavioral;
================================================
FILE: fpga/vna/vna.srcs/sources_1/new/vna_pkg.vhd
================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package vna_pkg is
type rx_sw_type is (SW_NONE, SW_RX1, SW_A, SW_RX2, SW_B);
subtype byte is std_logic_vector(7 downto 0);
constant ADC_WIDTH : natural := 14;
constant IF_WIDTH : natural := 24;
constant LO_WIDTH : integer := 14;
constant IQ_ACC_WIDTH : natural := 56;
constant CIC_OUT_WIDTH : natural := 32;
constant IQ_BYTES : natural := IQ_ACC_WIDTH/8;
constant COMM_START : std_logic_vector(7 downto 0) := "10101010";
-- Number of clock cycles to skip after reset
-- Determined by the switch settling time
constant SKIP_SAMPLES : integer := 30;
constant AGC_TARGET : integer := 200;
constant LOCK_CYCLES : integer := 12000;
end vna_pkg;
package body vna_pkg is
end vna_pkg;
================================================
FILE: fpga/vna/vna.xpr
================================================
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2016.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="17" Path="/media/sdb1/vna2/fpga/vna/vna.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="40dace754488472f89a19aefe4b884c5"/>
<Option Name="Part" Val="xc7a15tftg256-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PPRDIR/vna.ip_user_files"/>
<Option Name="IPStaticSourceDir" Val="$PPRDIR/vna.ip_user_files/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSANumComputeUnits" Val="16"/>
<Option Name="WTXSimLaunchSim" Val="561"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="8"/>
<Option Name="WTModelSimExportSim" Val="8"/>
<Option Name="WTQuestaExportSim" Val="8"/>
<Option Name="WTIesExportSim" Val="8"/>
<Option Name="WTVcsExportSim" Val="8"/>
<Option Name="WTRivieraExportSim" Val="8"/>
<Option Name="WTActivehdlExportSim" Val="8"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="64"/>
<Option Name="XSimTraceLimit" Val="65536"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/mixer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/lo.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/vna_pkg.vhd">
<FileInfo>
<Attr Name="Library" Val="xil_defaultlib"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/lfsr.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/new/downconvert.vhd">
<FileInfo>
<Attr Name="ImportPath" Val="$PSRCDIR/sim_1/new/downconvert.vhd"/>
<Attr Name="ImportTime" Val="1480247902"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/acc_control.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/accumulator.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
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</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/rx_sw_mux.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
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</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/tx_mux.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
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</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/receiver.vhd">
<FileInfo>
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</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/dither.vhd">
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</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/comm.vhd">
<FileInfo>
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</FileInfo>
</File>
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<Attr Name="UsedIn" Val="synthesis"/>
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</FileInfo>
</File>
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<FileInfo>
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</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/new/sample_packer.vhd">
<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/iq_packer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
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</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/receiver_control.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
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</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/new/vna_top.vhd">
<FileInfo>
<Attr Name="ImportPath" Val="$PSRCDIR/sim_1/new/vna_top.vhd"/>
<Attr Name="ImportTime" Val="1480752375"/>
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</FileInfo>
</File>
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<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/source_agc.vhd">
<FileInfo>
<Attr Name="UserDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/rx_switch.vhd">
<FileInfo>
<Attr Name="UserDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/pwr_sync_gen.vhd">
<FileInfo>
<Attr Name="UserDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
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</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/new/port_switch.vhd">
<FileInfo>
<Attr Name="UserDisabled" Val="1"/>
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<Attr Name="ImportTime" Val="1480253601"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/file_adc.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="vna_top"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/new/vna_constraints.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/vna_constraints.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sim_1/new/vna_top_tb.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/spi3_tb.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/receiver_tb.vhd">
<FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/ft2232_behavioral.vhd">
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<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
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<FileInfo>
<Attr Name="UserDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
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<FileInfo>
<Attr Name="UserDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
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<FileInfo>
<Attr Name="UserDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sim_1/new/spi_write_tb.vhd">
<FileInfo>
<Attr Name="UserDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
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</File>
<File Path="$PSRCDIR/sim_1/new/mixer_sim.vhd">
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<Attr Name="UserDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</File>
<File Path="$PSRCDIR/sim_1/new/lo_sim.vhd">
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</File>
<File Path="$PPRDIR/vna_tb_behav.wcfg">
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<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="vna_top_tb"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/lo_sim_behav.wcfg"/>
<Option Name="XSimWcfgFile" Val="$PPRDIR/vna_tb_behav.wcfg"/>
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</FileSet>
<FileSet Name="xadc_wiz_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xadc_wiz_0">
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<Attr Name="UsedIn" Val="implementation"/>
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</File>
<Config>
<Option Name="TopModule" Val="xadc_wiz_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
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<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
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<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
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<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
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<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
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<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
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</Simulators>
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<Step Id="synth_design"/>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a15tftg256-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
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<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
</Project>
================================================
FILE: hw/adc.sch
================================================
EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:vna
LIBS:vna2-cache
EELAYER 26 0
EELAYER END
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D2
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D3
Text HLabel 5600 3750 2 60 Output ~ 0
D4
Text HLabel 5600 3850 2 60 Output ~ 0
D5
Text HLabel 5600 3950 2 60 Output ~ 0
D6
Text HLabel 5600 4050 2 60 Output ~ 0
D7
Text HLabel 5600 4150 2 60 Output ~ 0
D8
Text HLabel 5600 4250 2 60 Output ~ 0
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Text HLabel 5600 4350 2 60 Output ~ 0
D10
Text HLabel 5600 4450 2 60 Output ~ 0
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Text HLabel 5600 4550 2 60 Output ~ 0
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Text HLabel 5600 4650 2 60 Output ~ 0
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1 5500 5300
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1 2650 4450
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1 2350 4450
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1 2650 4650
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1 2350 4650
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Wire Wire Line
2800 3450 3700 3450
Wire Wire Line
2800 3550 3700 3550
Wire Wire Line
4500 3000 4500 2500
Wire Wire Line
4650 2100 4650 3000
Wire Wire Line
4500 2500 4650 2500
Wire Wire Line
3350 1600 4950 1600
Wire Wire Line
4950 1600 4950 2100
Wire Wire Line
4650 2100 5250 2100
Wire Wire Line
4400 1650 4400 1600
Connection ~ 4400 1600
Wire Wire Line
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Connection ~ 4650 2500
Connection ~ 4950 2100
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
3700 3850 3650 3850
Wire Wire Line
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Wire Wire Line
3600 3950 3600 4050
Wire Wire Line
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Connection ~ 3600 4050
Connection ~ 3300 3750
Connection ~ 3300 4050
Connection ~ 3050 3750
Connection ~ 3050 4050
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
5400 3450 5600 3450
Wire Wire Line
5600 3550 5400 3550
Wire Wire Line
5400 3650 5600 3650
Wire Wire Line
5600 3750 5400 3750
Wire Wire Line
5400 3850 5600 3850
Wire Wire Line
5600 3950 5400 3950
Wire Wire Line
5400 4050 5600 4050
Wire Wire Line
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Wire Wire Line
5400 4550 5600 4550
Wire Wire Line
5600 4650 5400 4650
Wire Wire Line
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Wire Wire Line
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Connection ~ 5500 4900
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
3400 4450 3700 4450
Wire Wire Line
3400 4550 3700 4550
Wire Wire Line
3700 4850 3650 4850
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2900 5150 2900 5200
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2900 4850 2900 4750
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3950 2000 3950 1950
Wire Wire Line
3950 1650 3950 1600
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================================================
FILE: hw/filter_bank.sch
================================================
EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
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$EndSCHEMATC
================================================
FILE: hw/fpga.sch
================================================
EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:vna
LIBS:vna2-cache
EELAYER 26 0
EELAYER END
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gitextract_0z82hq_s/
├── README
├── couplers/
│ ├── README
│ └── gerbers/
│ ├── rf_bridge_Bottom.gbl
│ ├── rf_bridge_In1.g2l
│ ├── rf_bridge_In2.g3l
│ ├── rf_bridge_Mask.gts
│ ├── rf_bridge_Mask_bottom.gbs
│ ├── rf_bridge_Outline.gko
│ ├── rf_bridge_Top.gtl
│ └── rf_bridge_drill.drl
├── fpga/
│ ├── vna/
│ │ ├── vna.hw/
│ │ │ └── vna.lpr
│ │ ├── vna.srcs/
│ │ │ ├── constrs_1/
│ │ │ │ └── new/
│ │ │ │ └── vna_constraints.xdc
│ │ │ ├── sim_1/
│ │ │ │ └── new/
│ │ │ │ ├── comm_tb.vhd
│ │ │ │ ├── ft2232_behavioral.vhd
│ │ │ │ ├── io_bank_tb.vhd
│ │ │ │ ├── iq_packer_tb.vhd
│ │ │ │ ├── lo_sim.vhd
│ │ │ │ ├── mixer_sim.vhd
│ │ │ │ ├── receiver_tb.vhd
│ │ │ │ ├── spi3_tb.vhd
│ │ │ │ ├── spi_write_tb.vhd
│ │ │ │ ├── vna_tb.vhd
│ │ │ │ └── vna_top_tb.vhd
│ │ │ └── sources_1/
│ │ │ ├── imports/
│ │ │ │ └── new/
│ │ │ │ ├── downconvert.vhd
│ │ │ │ ├── port_switch.vhd
│ │ │ │ ├── sample_packer.vhd
│ │ │ │ ├── spi3.vhd
│ │ │ │ └── vna_top.vhd
│ │ │ └── new/
│ │ │ ├── acc_control.vhd
│ │ │ ├── accumulator.vhd
│ │ │ ├── comm.vhd
│ │ │ ├── dither.vhd
│ │ │ ├── file_adc.vhd
│ │ │ ├── io_bank.vhd
│ │ │ ├── iq_packer.vhd
│ │ │ ├── lfsr.vhd
│ │ │ ├── lo.vhd
│ │ │ ├── mixer.vhd
│ │ │ ├── pwr_sync_gen.vhd
│ │ │ ├── receiver.vhd
│ │ │ ├── receiver_control.vhd
│ │ │ ├── rx_sw_mux.vhd
│ │ │ ├── rx_switch.vhd
│ │ │ ├── source_agc.vhd
│ │ │ ├── spi_write.vhd
│ │ │ ├── tx_mux.vhd
│ │ │ └── vna_pkg.vhd
│ │ └── vna.xpr
│ └── vna_top.bit
├── hw/
│ ├── adc.sch
│ ├── filter_bank.sch
│ ├── fpga.sch
│ ├── fpga_power.sch
│ ├── if_amp.sch
│ ├── lib/
│ │ └── vna.lib
│ ├── lmz30602.sch
│ ├── microcontroller.sch
│ ├── port_switch.sch
│ ├── power.sch
│ ├── receiver.sch
│ ├── rx_lna.sch
│ ├── rx_switch.sch
│ ├── transmitter.sch
│ ├── tx_amp.sch
│ ├── usb.sch
│ ├── vna.pretty/
│ │ ├── 1748LP18A075.kicad_mod
│ │ ├── 3550LP14A300.kicad_mod
│ │ ├── 5400BL15B050E.kicad_mod
│ │ ├── 5515LP15A730.kicad_mod
│ │ ├── ABMM.kicad_mod
│ │ ├── ASTRX-12.kicad_mod
│ │ ├── CNC-3220-10-0300-00.kicad_mod
│ │ ├── CONSMA003.062.kicad_mod
│ │ ├── CTX520.kicad_mod
│ │ ├── C_0402b.kicad_mod
│ │ ├── C_0603b.kicad_mod
│ │ ├── C_0805b.kicad_mod
│ │ ├── DFN-8-1EP_2x2mm_Pitch0.5mm.kicad_mod
│ │ ├── DFN-8.kicad_mod
│ │ ├── EJ508A.kicad_mod
│ │ ├── EVP-AWBA2A.kicad_mod
│ │ ├── FTG256.kicad_mod
│ │ ├── KT2520K.kicad_mod
│ │ ├── LED_0603.kicad_mod
│ │ ├── LP0603A0902.kicad_mod
│ │ ├── MLPD-10.kicad_mod
│ │ ├── MSOP-8.kicad_mod
│ │ ├── MountingHole_3.2mm_M3_Pad_Via_mod.kicad_mod
│ │ ├── PAT1220.kicad_mod
│ │ ├── RF_via.kicad_mod
│ │ ├── R_0402b.kicad_mod
│ │ ├── R_0603b.kicad_mod
│ │ ├── S2711-46R.kicad_mod
│ │ ├── SC-70-6.kicad_mod
│ │ ├── SG-210STF.kicad_mod
│ │ ├── SOD-123F.kicad_mod
│ │ ├── SOT-23-5.kicad_mod
│ │ ├── SOT-23-5L.kicad_mod
│ │ ├── SOT-23-6.kicad_mod
│ │ ├── SOT-416.kicad_mod
│ │ ├── SRN4018.kicad_mod
│ │ ├── SRR6040A.kicad_mod
│ │ ├── SSOP-16.kicad_mod
│ │ ├── SSOT-6.kicad_mod
│ │ ├── TCM1-63AX+.kicad_mod
│ │ ├── TFBGA-100.kicad_mod
│ │ ├── TFLGA-20.kicad_mod
│ │ ├── TP_1.00.kicad_mod
│ │ ├── TQFN-32.kicad_mod
│ │ ├── TSOT-23.kicad_mod
│ │ ├── USB_MICRO.kicad_mod
│ │ ├── VFQFN-16.kicad_mod
│ │ ├── VFQFN-24.kicad_mod
│ │ ├── VFQFN-32.kicad_mod
│ │ ├── VQFN-16.kicad_mod
│ │ ├── VQFN-24.kicad_mod
│ │ ├── WFBGA-6.kicad_mod
│ │ ├── WFDFN-8.kicad_mod
│ │ ├── XDFN-2.kicad_mod
│ │ ├── XFDFN-6.kicad_mod
│ │ ├── XTAL_3.2x2.5.kicad_mod
│ │ ├── coupler4.kicad_mod
│ │ ├── uwmiter_0.34_0.17_45.kicad_mod
│ │ └── uwmiter_0.34_0.17_90.kicad_mod
│ ├── vna2-cache.lib
│ ├── vna2.kicad_pcb
│ ├── vna2.pro
│ └── vna2.sch
├── openocd/
│ ├── interface.cfg
│ ├── program_flash.cfg
│ ├── program_fpga.cfg
│ └── xc7_bscan_spi.bit
└── software/
├── cal_kit/
│ ├── load.s1p
│ ├── open.s1p
│ └── short.s1p
├── max2871.py
├── monitor_rx.py
├── monitor_sparam.py
├── oneport/
│ └── calibrate.py
├── sparam.py
├── twoport/
│ └── calibrate.py
└── vna.py
SYMBOL INDEX (35 symbols across 6 files)
FILE: software/max2871.py
class MAX2871 (line 4) | class MAX2871():
method __init__ (line 5) | def __init__(self):
method freq_to_regs (line 38) | def freq_to_regs(self, fout, fpd, m=4095, fb=1, apwr=0, rfa_en=1):
method find_reg (line 223) | def find_reg(self, reg):
method write_value (line 230) | def write_value(self, **kw):
FILE: software/monitor_rx.py
function init_vna (line 11) | def init_vna():
function update (line 68) | def update():
FILE: software/monitor_sparam.py
function init_vna (line 11) | def init_vna():
function update (line 63) | def update():
FILE: software/oneport/calibrate.py
function tline_input (line 7) | def tline_input(zl, z0, t, f):
function gamma (line 14) | def gamma(zl, z0):
function make_open (line 17) | def make_open(freqs, c0, c1, c2, c3, offset_t, offset_z0):
function make_short (line 32) | def make_short(freqs, l0, l1, l2, l3, offset_t, offset_z0):
function make_load (line 47) | def make_load(freqs, r0, l0, l1, l2, l3, offset_t, offset_z0):
FILE: software/sparam.py
function iq_to_sparam (line 9) | def iq_to_sparam(iqs, freqs, ports, sw_correction=True):
function sw_terms (line 44) | def sw_terms(iqs, freqs):
FILE: software/vna.py
class VNA (line 10) | class VNA():
method __init__ (line 11) | def __init__(self):
method array_to_int (line 23) | def array_to_int(self, a, reverse=False):
method read_samples (line 33) | def read_samples(self):
method read_iq (line 68) | def read_iq(self):
method write_att (line 119) | def write_att(self, att):
method write_switches (line 138) | def write_switches(self, tx_filter, port, rx_sw, rx_sw_force=False):
method write_io (line 187) | def write_io(self, pwdn, mixer_enable, led, adc_oe, adc_shdn):
method write_tag (line 192) | def write_tag(self, tag):
method write_pll (line 195) | def write_pll(self, pll):
method write_sample_time (line 203) | def write_sample_time(self, samples):
method write_echo (line 210) | def write_echo(self, word):
method read_echo (line 213) | def read_echo(self):
method set_tx_mux (line 220) | def set_tx_mux(self, mux, sample_input='adc'):
method write_pll_reg (line 250) | def write_pll_reg(self, pll, reg):
method write_pll_io (line 263) | def write_pll_io(self, lo_ce, source_ce, lo_rf, source_rf):
method dither_en (line 267) | def dither_en(self, enable):
method to_device (line 271) | def to_device(self, cmd, packet):
method program_sources (line 282) | def program_sources(self, source_freq, if_freq=2e6):
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{
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{
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{
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},
{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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"path": "hw/vna.pretty/USB_MICRO.kicad_mod",
"chars": 1489,
"preview": "(module USB_MICRO (layer F.Cu) (tedit 53F64203)\n (fp_text reference U13 (at 0.1 -1.9) (layer F.SilkS)\n (effects (fon"
},
{
"path": "hw/vna.pretty/VFQFN-16.kicad_mod",
"chars": 2585,
"preview": "(module VFQFN-16 (layer F.Cu) (tedit 584D6891)\n (fp_text reference REF** (at 0 2.7) (layer F.SilkS)\n (effects (font "
},
{
"path": "hw/vna.pretty/VFQFN-24.kicad_mod",
"chars": 3756,
"preview": "(module VFQFN-24 (layer F.Cu) (tedit 55A67B47)\n (fp_text reference U2 (at 0.095 5.025 90) (layer F.SilkS)\n (effects "
},
{
"path": "hw/vna.pretty/VFQFN-32.kicad_mod",
"chars": 4393,
"preview": "(module VFQFN-32 (layer F.Cu) (tedit 56489F4B)\n (fp_text reference REF** (at 0.115 3.55) (layer F.SilkS)\n (effects ("
},
{
"path": "hw/vna.pretty/VQFN-16.kicad_mod",
"chars": 2694,
"preview": "(module VQFN-16 (layer F.Cu) (tedit 564A388D)\n (fp_text reference VQFN-16 (at 0 -3.3) (layer F.SilkS)\n (effects (fon"
},
{
"path": "hw/vna.pretty/VQFN-24.kicad_mod",
"chars": 4204,
"preview": "(module VQFN-24 (layer F.Cu) (tedit 5648A4F4)\n (fp_text reference VQFN-24 (at 0 -3.3) (layer F.SilkS)\n (effects (fon"
},
{
"path": "hw/vna.pretty/WFBGA-6.kicad_mod",
"chars": 1319,
"preview": "(module WFBGA-6 (layer F.Cu) (tedit 56AC6684)\n (fp_text reference REF** (at 0 1.35) (layer F.SilkS)\n (effects (font "
},
{
"path": "hw/vna.pretty/WFDFN-8.kicad_mod",
"chars": 1389,
"preview": "(module WFDFN-8 (layer F.Cu) (tedit 55A927D3)\n (fp_text reference REF** (at 0.025 1.775) (layer F.SilkS)\n (effects ("
},
{
"path": "hw/vna.pretty/XDFN-2.kicad_mod",
"chars": 710,
"preview": "(module XDFN-2 (layer F.Cu) (tedit 55A40369)\n (fp_text reference REF** (at 0.475 1) (layer F.SilkS)\n (effects (font "
},
{
"path": "hw/vna.pretty/XFDFN-6.kicad_mod",
"chars": 1435,
"preview": "(module XFDFN-6 (layer F.Cu) (tedit 551FA82D)\n (fp_text reference XFDFN-6 (at -0.1 -5.4) (layer F.SilkS)\n (effects ("
},
{
"path": "hw/vna.pretty/XTAL_3.2x2.5.kicad_mod",
"chars": 869,
"preview": "(module XTAL_3.2x2.5 (layer F.Cu) (tedit 5579B9EE)\n (fp_text reference REF** (at 0 2.4) (layer F.SilkS)\n (effects (f"
},
{
"path": "hw/vna.pretty/coupler4.kicad_mod",
"chars": 2975,
"preview": "(module coupler4 (layer F.Cu) (tedit 564B55DF)\n (fp_text reference F1 (at 0.1 3) (layer F.SilkS) hide\n (effects (fon"
},
{
"path": "hw/vna.pretty/uwmiter_0.34_0.17_45.kicad_mod",
"chars": 675,
"preview": "(module uwmiter_0.34_0.17_45 (layer F.Cu) (tedit 569FDDF6)\n (fp_text reference uwmiter_0.34_0.17_45 (at 0 1.34) (layer "
},
{
"path": "hw/vna.pretty/uwmiter_0.34_0.17_90.kicad_mod",
"chars": 645,
"preview": "(module uwmiter_0.34_0.17_90 (layer F.Cu) (tedit 0)\n (fp_text reference uwmiter_0.34_0.17_90 (at 0 1.34) (layer F.SilkS"
},
{
"path": "hw/vna2-cache.lib",
"chars": 34703,
"preview": "EESchema-LIBRARY Version 2.3\n#encoding utf-8\n#\n# 3550LP14A300\n#\nDEF 3550LP14A300 U 0 40 Y Y 1 F N\nF0 \"U\" 200 -300 60 H V"
},
{
"path": "hw/vna2.kicad_pcb",
"chars": 2643199,
"preview": "(kicad_pcb (version 20170123) (host pcbnew \"(2017-07-25 revision 161045f)-master\")\n\n (general\n (thickness 1.6)\n ("
},
{
"path": "hw/vna2.pro",
"chars": 1407,
"preview": "update=ke 8. maaliskuuta 2017 19.36.10\nversion=1\nlast_client=kicad\n[pcbnew]\nversion=1\nLastNetListRead=\nUseCmpFile=1\nPad"
},
{
"path": "hw/vna2.sch",
"chars": 27599,
"preview": "EESchema Schematic File Version 2\nLIBS:power\nLIBS:device\nLIBS:transistors\nLIBS:conn\nLIBS:linear\nLIBS:regul\nLIBS:74xx\nLIB"
},
{
"path": "openocd/interface.cfg",
"chars": 187,
"preview": "interface ftdi\nftdi_device_desc \"VNA\"\nftdi_vid_pid 0x0403 0x6010\nftdi_layout_init 0x0c08 0x0f1b\nreset_config none\nadapte"
},
{
"path": "openocd/program_flash.cfg",
"chars": 1635,
"preview": "# xilinx series 7 (artix, kintex, virtex)\n# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config"
},
{
"path": "openocd/program_fpga.cfg",
"chars": 88,
"preview": "source [find cpld/xilinx-xc7.cfg]\n\ninit\nxc7_program xc7.tap\npld load 0 vna_top.bit\nexit\n"
},
{
"path": "software/cal_kit/load.s1p",
"chars": 35758,
"preview": "!Agilent Technologies,N5230A,MY45001695,A.07.50.67\r\n!Agilent N5230A: A.07.50.67\r\n!Date: Thursday, August 18, 2016 06:57:"
},
{
"path": "software/cal_kit/open.s1p",
"chars": 35850,
"preview": "!Agilent Technologies,N5230A,MY45001695,A.07.50.67\r\n!Agilent N5230A: A.07.50.67\r\n!Date: Thursday, August 18, 2016 06:59:"
},
{
"path": "software/cal_kit/short.s1p",
"chars": 35436,
"preview": "!Agilent Technologies,N5230A,MY45001695,A.07.50.67\r\n!Agilent N5230A: A.07.50.67\r\n!Date: Thursday, August 18, 2016 06:58:"
},
{
"path": "software/max2871.py",
"chars": 9425,
"preview": "\nfrom fractions import Fraction\n\nclass MAX2871():\n def __init__(self):\n #Register definitions:\n # (Regi"
},
{
"path": "software/monitor_rx.py",
"chars": 2737,
"preview": "# -*- coding: utf-8 -*-\n\nfrom vna import VNA\nimport matplotlib.pyplot as plt\nimport numpy as np\nfrom pyqtgraph.Qt import"
},
{
"path": "software/monitor_sparam.py",
"chars": 2658,
"preview": "# -*- coding: utf-8 -*-\n\nfrom vna import VNA\nimport matplotlib.pyplot as plt\nimport numpy as np\nfrom pyqtgraph.Qt import"
},
{
"path": "software/oneport/calibrate.py",
"chars": 2692,
"preview": "import sys\nimport skrf\nimport matplotlib.pyplot as plt\nimport numpy as np\nskrf.stylely()\n\ndef tline_input(zl, z0, t, f):"
},
{
"path": "software/sparam.py",
"chars": 3670,
"preview": "\nfrom vna import VNA\nimport matplotlib.pyplot as plt\nimport numpy as np\nimport time\nimport skrf\nimport pickle\n\ndef iq_to"
},
{
"path": "software/twoport/calibrate.py",
"chars": 2502,
"preview": "#!/usr/bin/env python\nimport skrf\nimport matplotlib.pyplot as plt\nimport numpy as np\nimport sys\nskrf.stylely()\n\n# Calibr"
},
{
"path": "software/vna.py",
"chars": 9208,
"preview": "\nimport pylibftdi as ftdi\nfrom max2871 import MAX2871\nimport time\nimport matplotlib.pyplot as plt\nimport numpy as np\n\nre"
}
]
// ... and 2 more files (download for full content)
About this extraction
This page contains the full source code of the Ttl/vna2 GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 142 files (3.3 MB), approximately 885.2k tokens, and a symbol index with 35 extracted functions, classes, methods, constants, and types. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.
Extracted by GitExtract — free GitHub repo to text converter for AI. Built by Nikandr Surkov.