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Repository: bluespec/Toooba
Branch: master
Commit: 81f926f863a5
Files: 1476
Total size: 179.1 MB
Directory structure:
gitextract_wf1zodea/
├── .gitignore
├── .gitmodules
├── LICENSE
├── README.md
├── Tests/
│ ├── Makefile
│ ├── README.txt
│ ├── Run_regression.py
│ └── isa/
│ ├── rv32mi-p-breakpoint
│ ├── rv32mi-p-breakpoint.dump
│ ├── rv32mi-p-csr
│ ├── rv32mi-p-csr.dump
│ ├── rv32mi-p-illegal
│ ├── rv32mi-p-illegal.dump
│ ├── rv32mi-p-ma_addr
│ ├── rv32mi-p-ma_addr.dump
│ ├── rv32mi-p-ma_fetch
│ ├── rv32mi-p-ma_fetch.dump
│ ├── rv32mi-p-mcsr
│ ├── rv32mi-p-mcsr.dump
│ ├── rv32mi-p-sbreak
│ ├── rv32mi-p-sbreak.dump
│ ├── rv32mi-p-scall
│ ├── rv32mi-p-scall.dump
│ ├── rv32mi-p-shamt
│ ├── rv32mi-p-shamt.dump
│ ├── rv32si-p-csr
│ ├── rv32si-p-csr.dump
│ ├── rv32si-p-dirty
│ ├── rv32si-p-dirty.dump
│ ├── rv32si-p-ma_fetch
│ ├── rv32si-p-ma_fetch.dump
│ ├── rv32si-p-sbreak
│ ├── rv32si-p-sbreak.dump
│ ├── rv32si-p-scall
│ ├── rv32si-p-scall.dump
│ ├── rv32si-p-wfi
│ ├── rv32si-p-wfi.dump
│ ├── rv32ua-p-amoadd_w
│ ├── rv32ua-p-amoadd_w.dump
│ ├── rv32ua-p-amoand_w
│ ├── rv32ua-p-amoand_w.dump
│ ├── rv32ua-p-amomax_w
│ ├── rv32ua-p-amomax_w.dump
│ ├── rv32ua-p-amomaxu_w
│ ├── rv32ua-p-amomaxu_w.dump
│ ├── rv32ua-p-amomin_w
│ ├── rv32ua-p-amomin_w.dump
│ ├── rv32ua-p-amominu_w
│ ├── rv32ua-p-amominu_w.dump
│ ├── rv32ua-p-amoor_w
│ ├── rv32ua-p-amoor_w.dump
│ ├── rv32ua-p-amoswap_w
│ ├── rv32ua-p-amoswap_w.dump
│ ├── rv32ua-p-amoxor_w
│ ├── rv32ua-p-amoxor_w.dump
│ ├── rv32ua-p-lrsc
│ ├── rv32ua-p-lrsc.dump
│ ├── rv32ua-v-amoadd_w
│ ├── rv32ua-v-amoadd_w.dump
│ ├── rv32ua-v-amoand_w
│ ├── rv32ua-v-amoand_w.dump
│ ├── rv32ua-v-amomax_w
│ ├── rv32ua-v-amomax_w.dump
│ ├── rv32ua-v-amomaxu_w
│ ├── rv32ua-v-amomaxu_w.dump
│ ├── rv32ua-v-amomin_w
│ ├── rv32ua-v-amomin_w.dump
│ ├── rv32ua-v-amominu_w
│ ├── rv32ua-v-amominu_w.dump
│ ├── rv32ua-v-amoor_w
│ ├── rv32ua-v-amoor_w.dump
│ ├── rv32ua-v-amoswap_w
│ ├── rv32ua-v-amoswap_w.dump
│ ├── rv32ua-v-amoxor_w
│ ├── rv32ua-v-amoxor_w.dump
│ ├── rv32ua-v-lrsc
│ ├── rv32ua-v-lrsc.dump
│ ├── rv32uc-p-rvc
│ ├── rv32uc-p-rvc.dump
│ ├── rv32uc-v-rvc
│ ├── rv32uc-v-rvc.dump
│ ├── rv32ud-p-fadd
│ ├── rv32ud-p-fadd.dump
│ ├── rv32ud-p-fclass
│ ├── rv32ud-p-fclass.dump
│ ├── rv32ud-p-fcmp
│ ├── rv32ud-p-fcmp.dump
│ ├── rv32ud-p-fcvt
│ ├── rv32ud-p-fcvt.dump
│ ├── rv32ud-p-fcvt_w
│ ├── rv32ud-p-fcvt_w.dump
│ ├── rv32ud-p-fdiv
│ ├── rv32ud-p-fdiv.dump
│ ├── rv32ud-p-fmadd
│ ├── rv32ud-p-fmadd.dump
│ ├── rv32ud-p-fmin
│ ├── rv32ud-p-fmin.dump
│ ├── rv32ud-p-ldst
│ ├── rv32ud-p-ldst.dump
│ ├── rv32ud-p-recoding
│ ├── rv32ud-p-recoding.dump
│ ├── rv32ud-v-fadd
│ ├── rv32ud-v-fadd.dump
│ ├── rv32ud-v-fclass
│ ├── rv32ud-v-fclass.dump
│ ├── rv32ud-v-fcmp
│ ├── rv32ud-v-fcmp.dump
│ ├── rv32ud-v-fcvt
│ ├── rv32ud-v-fcvt.dump
│ ├── rv32ud-v-fcvt_w
│ ├── rv32ud-v-fcvt_w.dump
│ ├── rv32ud-v-fdiv
│ ├── rv32ud-v-fdiv.dump
│ ├── rv32ud-v-fmadd
│ ├── rv32ud-v-fmadd.dump
│ ├── rv32ud-v-fmin
│ ├── rv32ud-v-fmin.dump
│ ├── rv32ud-v-ldst
│ ├── rv32ud-v-ldst.dump
│ ├── rv32ud-v-recoding
│ ├── rv32ud-v-recoding.dump
│ ├── rv32uf-p-fadd
│ ├── rv32uf-p-fadd.dump
│ ├── rv32uf-p-fclass
│ ├── rv32uf-p-fclass.dump
│ ├── rv32uf-p-fcmp
│ ├── rv32uf-p-fcmp.dump
│ ├── rv32uf-p-fcvt
│ ├── rv32uf-p-fcvt.dump
│ ├── rv32uf-p-fcvt_w
│ ├── rv32uf-p-fcvt_w.dump
│ ├── rv32uf-p-fdiv
│ ├── rv32uf-p-fdiv.dump
│ ├── rv32uf-p-fmadd
│ ├── rv32uf-p-fmadd.dump
│ ├── rv32uf-p-fmin
│ ├── rv32uf-p-fmin.dump
│ ├── rv32uf-p-ldst
│ ├── rv32uf-p-ldst.dump
│ ├── rv32uf-p-move
│ ├── rv32uf-p-move.dump
│ ├── rv32uf-p-recoding
│ ├── rv32uf-p-recoding.dump
│ ├── rv32uf-v-fadd
│ ├── rv32uf-v-fadd.dump
│ ├── rv32uf-v-fclass
│ ├── rv32uf-v-fclass.dump
│ ├── rv32uf-v-fcmp
│ ├── rv32uf-v-fcmp.dump
│ ├── rv32uf-v-fcvt
│ ├── rv32uf-v-fcvt.dump
│ ├── rv32uf-v-fcvt_w
│ ├── rv32uf-v-fcvt_w.dump
│ ├── rv32uf-v-fdiv
│ ├── rv32uf-v-fdiv.dump
│ ├── rv32uf-v-fmadd
│ ├── rv32uf-v-fmadd.dump
│ ├── rv32uf-v-fmin
│ ├── rv32uf-v-fmin.dump
│ ├── rv32uf-v-ldst
│ ├── rv32uf-v-ldst.dump
│ ├── rv32uf-v-move
│ ├── rv32uf-v-move.dump
│ ├── rv32uf-v-recoding
│ ├── rv32uf-v-recoding.dump
│ ├── rv32ui-p-add
│ ├── rv32ui-p-add.dump
│ ├── rv32ui-p-addi
│ ├── rv32ui-p-addi.dump
│ ├── rv32ui-p-and
│ ├── rv32ui-p-and.dump
│ ├── rv32ui-p-andi
│ ├── rv32ui-p-andi.dump
│ ├── rv32ui-p-auipc
│ ├── rv32ui-p-auipc.dump
│ ├── rv32ui-p-beq
│ ├── rv32ui-p-beq.dump
│ ├── rv32ui-p-bge
│ ├── rv32ui-p-bge.dump
│ ├── rv32ui-p-bgeu
│ ├── rv32ui-p-bgeu.dump
│ ├── rv32ui-p-blt
│ ├── rv32ui-p-blt.dump
│ ├── rv32ui-p-bltu
│ ├── rv32ui-p-bltu.dump
│ ├── rv32ui-p-bne
│ ├── rv32ui-p-bne.dump
│ ├── rv32ui-p-fence_i
│ ├── rv32ui-p-fence_i.dump
│ ├── rv32ui-p-jal
│ ├── rv32ui-p-jal.dump
│ ├── rv32ui-p-jalr
│ ├── rv32ui-p-jalr.dump
│ ├── rv32ui-p-lb
│ ├── rv32ui-p-lb.dump
│ ├── rv32ui-p-lbu
│ ├── rv32ui-p-lbu.dump
│ ├── rv32ui-p-lh
│ ├── rv32ui-p-lh.dump
│ ├── rv32ui-p-lhu
│ ├── rv32ui-p-lhu.dump
│ ├── rv32ui-p-lui
│ ├── rv32ui-p-lui.dump
│ ├── rv32ui-p-lw
│ ├── rv32ui-p-lw.dump
│ ├── rv32ui-p-or
│ ├── rv32ui-p-or.dump
│ ├── rv32ui-p-ori
│ ├── rv32ui-p-ori.dump
│ ├── rv32ui-p-sb
│ ├── rv32ui-p-sb.dump
│ ├── rv32ui-p-sh
│ ├── rv32ui-p-sh.dump
│ ├── rv32ui-p-simple
│ ├── rv32ui-p-simple.dump
│ ├── rv32ui-p-sll
│ ├── rv32ui-p-sll.dump
│ ├── rv32ui-p-slli
│ ├── rv32ui-p-slli.dump
│ ├── rv32ui-p-slt
│ ├── rv32ui-p-slt.dump
│ ├── rv32ui-p-slti
│ ├── rv32ui-p-slti.dump
│ ├── rv32ui-p-sltiu
│ ├── rv32ui-p-sltiu.dump
│ ├── rv32ui-p-sltu
│ ├── rv32ui-p-sltu.dump
│ ├── rv32ui-p-sra
│ ├── rv32ui-p-sra.dump
│ ├── rv32ui-p-srai
│ ├── rv32ui-p-srai.dump
│ ├── rv32ui-p-srl
│ ├── rv32ui-p-srl.dump
│ ├── rv32ui-p-srli
│ ├── rv32ui-p-srli.dump
│ ├── rv32ui-p-sub
│ ├── rv32ui-p-sub.dump
│ ├── rv32ui-p-sw
│ ├── rv32ui-p-sw.dump
│ ├── rv32ui-p-xor
│ ├── rv32ui-p-xor.dump
│ ├── rv32ui-p-xori
│ ├── rv32ui-p-xori.dump
│ ├── rv32ui-v-add
│ ├── rv32ui-v-add.dump
│ ├── rv32ui-v-addi
│ ├── rv32ui-v-addi.dump
│ ├── rv32ui-v-and
│ ├── rv32ui-v-and.dump
│ ├── rv32ui-v-andi
│ ├── rv32ui-v-andi.dump
│ ├── rv32ui-v-auipc
│ ├── rv32ui-v-auipc.dump
│ ├── rv32ui-v-beq
│ ├── rv32ui-v-beq.dump
│ ├── rv32ui-v-bge
│ ├── rv32ui-v-bge.dump
│ ├── rv32ui-v-bgeu
│ ├── rv32ui-v-bgeu.dump
│ ├── rv32ui-v-blt
│ ├── rv32ui-v-blt.dump
│ ├── rv32ui-v-bltu
│ ├── rv32ui-v-bltu.dump
│ ├── rv32ui-v-bne
│ ├── rv32ui-v-bne.dump
│ ├── rv32ui-v-fence_i
│ ├── rv32ui-v-fence_i.dump
│ ├── rv32ui-v-jal
│ ├── rv32ui-v-jal.dump
│ ├── rv32ui-v-jalr
│ ├── rv32ui-v-jalr.dump
│ ├── rv32ui-v-lb
│ ├── rv32ui-v-lb.dump
│ ├── rv32ui-v-lbu
│ ├── rv32ui-v-lbu.dump
│ ├── rv32ui-v-lh
│ ├── rv32ui-v-lh.dump
│ ├── rv32ui-v-lhu
│ ├── rv32ui-v-lhu.dump
│ ├── rv32ui-v-lui
│ ├── rv32ui-v-lui.dump
│ ├── rv32ui-v-lw
│ ├── rv32ui-v-lw.dump
│ ├── rv32ui-v-or
│ ├── rv32ui-v-or.dump
│ ├── rv32ui-v-ori
│ ├── rv32ui-v-ori.dump
│ ├── rv32ui-v-sb
│ ├── rv32ui-v-sb.dump
│ ├── rv32ui-v-sh
│ ├── rv32ui-v-sh.dump
│ ├── rv32ui-v-simple
│ ├── rv32ui-v-simple.dump
│ ├── rv32ui-v-sll
│ ├── rv32ui-v-sll.dump
│ ├── rv32ui-v-slli
│ ├── rv32ui-v-slli.dump
│ ├── rv32ui-v-slt
│ ├── rv32ui-v-slt.dump
│ ├── rv32ui-v-slti
│ ├── rv32ui-v-slti.dump
│ ├── rv32ui-v-sltiu
│ ├── rv32ui-v-sltiu.dump
│ ├── rv32ui-v-sltu
│ ├── rv32ui-v-sltu.dump
│ ├── rv32ui-v-sra
│ ├── rv32ui-v-sra.dump
│ ├── rv32ui-v-srai
│ ├── rv32ui-v-srai.dump
│ ├── rv32ui-v-srl
│ ├── rv32ui-v-srl.dump
│ ├── rv32ui-v-srli
│ ├── rv32ui-v-srli.dump
│ ├── rv32ui-v-sub
│ ├── rv32ui-v-sub.dump
│ ├── rv32ui-v-sw
│ ├── rv32ui-v-sw.dump
│ ├── rv32ui-v-xor
│ ├── rv32ui-v-xor.dump
│ ├── rv32ui-v-xori
│ ├── rv32ui-v-xori.dump
│ ├── rv32um-p-div
│ ├── rv32um-p-div.dump
│ ├── rv32um-p-divu
│ ├── rv32um-p-divu.dump
│ ├── rv32um-p-mul
│ ├── rv32um-p-mul.dump
│ ├── rv32um-p-mulh
│ ├── rv32um-p-mulh.dump
│ ├── rv32um-p-mulhsu
│ ├── rv32um-p-mulhsu.dump
│ ├── rv32um-p-mulhu
│ ├── rv32um-p-mulhu.dump
│ ├── rv32um-p-rem
│ ├── rv32um-p-rem.dump
│ ├── rv32um-p-remu
│ ├── rv32um-p-remu.dump
│ ├── rv32um-v-div
│ ├── rv32um-v-div.dump
│ ├── rv32um-v-divu
│ ├── rv32um-v-divu.dump
│ ├── rv32um-v-mul
│ ├── rv32um-v-mul.dump
│ ├── rv32um-v-mulh
│ ├── rv32um-v-mulh.dump
│ ├── rv32um-v-mulhsu
│ ├── rv32um-v-mulhsu.dump
│ ├── rv32um-v-mulhu
│ ├── rv32um-v-mulhu.dump
│ ├── rv32um-v-rem
│ ├── rv32um-v-rem.dump
│ ├── rv32um-v-remu
│ ├── rv32um-v-remu.dump
│ ├── rv64mi-p-access
│ ├── rv64mi-p-access.dump
│ ├── rv64mi-p-breakpoint
│ ├── rv64mi-p-breakpoint.dump
│ ├── rv64mi-p-csr
│ ├── rv64mi-p-csr.dump
│ ├── rv64mi-p-illegal
│ ├── rv64mi-p-illegal.dump
│ ├── rv64mi-p-ma_addr
│ ├── rv64mi-p-ma_addr.dump
│ ├── rv64mi-p-ma_fetch
│ ├── rv64mi-p-ma_fetch.dump
│ ├── rv64mi-p-mcsr
│ ├── rv64mi-p-mcsr.dump
│ ├── rv64mi-p-sbreak
│ ├── rv64mi-p-sbreak.dump
│ ├── rv64mi-p-scall
│ ├── rv64mi-p-scall.dump
│ ├── rv64si-p-csr
│ ├── rv64si-p-csr.dump
│ ├── rv64si-p-dirty
│ ├── rv64si-p-dirty.dump
│ ├── rv64si-p-ma_fetch
│ ├── rv64si-p-ma_fetch.dump
│ ├── rv64si-p-sbreak
│ ├── rv64si-p-sbreak.dump
│ ├── rv64si-p-scall
│ ├── rv64si-p-scall.dump
│ ├── rv64si-p-wfi
│ ├── rv64si-p-wfi.dump
│ ├── rv64ua-p-amoadd_d
│ ├── rv64ua-p-amoadd_d.dump
│ ├── rv64ua-p-amoadd_w
│ ├── rv64ua-p-amoadd_w.dump
│ ├── rv64ua-p-amoand_d
│ ├── rv64ua-p-amoand_d.dump
│ ├── rv64ua-p-amoand_w
│ ├── rv64ua-p-amoand_w.dump
│ ├── rv64ua-p-amomax_d
│ ├── rv64ua-p-amomax_d.dump
│ ├── rv64ua-p-amomax_w
│ ├── rv64ua-p-amomax_w.dump
│ ├── rv64ua-p-amomaxu_d
│ ├── rv64ua-p-amomaxu_d.dump
│ ├── rv64ua-p-amomaxu_w
│ ├── rv64ua-p-amomaxu_w.dump
│ ├── rv64ua-p-amomin_d
│ ├── rv64ua-p-amomin_d.dump
│ ├── rv64ua-p-amomin_w
│ ├── rv64ua-p-amomin_w.dump
│ ├── rv64ua-p-amominu_d
│ ├── rv64ua-p-amominu_d.dump
│ ├── rv64ua-p-amominu_w
│ ├── rv64ua-p-amominu_w.dump
│ ├── rv64ua-p-amoor_d
│ ├── rv64ua-p-amoor_d.dump
│ ├── rv64ua-p-amoor_w
│ ├── rv64ua-p-amoor_w.dump
│ ├── rv64ua-p-amoswap_d
│ ├── rv64ua-p-amoswap_d.dump
│ ├── rv64ua-p-amoswap_w
│ ├── rv64ua-p-amoswap_w.dump
│ ├── rv64ua-p-amoxor_d
│ ├── rv64ua-p-amoxor_d.dump
│ ├── rv64ua-p-amoxor_w
│ ├── rv64ua-p-amoxor_w.dump
│ ├── rv64ua-p-lrsc
│ ├── rv64ua-p-lrsc.dump
│ ├── rv64ua-v-amoadd_d
│ ├── rv64ua-v-amoadd_d.dump
│ ├── rv64ua-v-amoadd_w
│ ├── rv64ua-v-amoadd_w.dump
│ ├── rv64ua-v-amoand_d
│ ├── rv64ua-v-amoand_d.dump
│ ├── rv64ua-v-amoand_w
│ ├── rv64ua-v-amoand_w.dump
│ ├── rv64ua-v-amomax_d
│ ├── rv64ua-v-amomax_d.dump
│ ├── rv64ua-v-amomax_w
│ ├── rv64ua-v-amomax_w.dump
│ ├── rv64ua-v-amomaxu_d
│ ├── rv64ua-v-amomaxu_d.dump
│ ├── rv64ua-v-amomaxu_w
│ ├── rv64ua-v-amomaxu_w.dump
│ ├── rv64ua-v-amomin_d
│ ├── rv64ua-v-amomin_d.dump
│ ├── rv64ua-v-amomin_w
│ ├── rv64ua-v-amomin_w.dump
│ ├── rv64ua-v-amominu_d
│ ├── rv64ua-v-amominu_d.dump
│ ├── rv64ua-v-amominu_w
│ ├── rv64ua-v-amominu_w.dump
│ ├── rv64ua-v-amoor_d
│ ├── rv64ua-v-amoor_d.dump
│ ├── rv64ua-v-amoor_w
│ ├── rv64ua-v-amoor_w.dump
│ ├── rv64ua-v-amoswap_d
│ ├── rv64ua-v-amoswap_d.dump
│ ├── rv64ua-v-amoswap_w
│ ├── rv64ua-v-amoswap_w.dump
│ ├── rv64ua-v-amoxor_d
│ ├── rv64ua-v-amoxor_d.dump
│ ├── rv64ua-v-amoxor_w
│ ├── rv64ua-v-amoxor_w.dump
│ ├── rv64ua-v-lrsc
│ ├── rv64ua-v-lrsc.dump
│ ├── rv64uc-p-rvc
│ ├── rv64uc-p-rvc.dump
│ ├── rv64uc-v-rvc
│ ├── rv64uc-v-rvc.dump
│ ├── rv64ud-p-fadd
│ ├── rv64ud-p-fadd.dump
│ ├── rv64ud-p-fclass
│ ├── rv64ud-p-fclass.dump
│ ├── rv64ud-p-fcmp
│ ├── rv64ud-p-fcmp.dump
│ ├── rv64ud-p-fcvt
│ ├── rv64ud-p-fcvt.dump
│ ├── rv64ud-p-fcvt_w
│ ├── rv64ud-p-fcvt_w.dump
│ ├── rv64ud-p-fdiv
│ ├── rv64ud-p-fdiv.dump
│ ├── rv64ud-p-fmadd
│ ├── rv64ud-p-fmadd.dump
│ ├── rv64ud-p-fmin
│ ├── rv64ud-p-fmin.dump
│ ├── rv64ud-p-ldst
│ ├── rv64ud-p-ldst.dump
│ ├── rv64ud-p-move
│ ├── rv64ud-p-move.dump
│ ├── rv64ud-p-recoding
│ ├── rv64ud-p-recoding.dump
│ ├── rv64ud-p-structural
│ ├── rv64ud-p-structural.dump
│ ├── rv64ud-v-fadd
│ ├── rv64ud-v-fadd.dump
│ ├── rv64ud-v-fclass
│ ├── rv64ud-v-fclass.dump
│ ├── rv64ud-v-fcmp
│ ├── rv64ud-v-fcmp.dump
│ ├── rv64ud-v-fcvt
│ ├── rv64ud-v-fcvt.dump
│ ├── rv64ud-v-fcvt_w
│ ├── rv64ud-v-fcvt_w.dump
│ ├── rv64ud-v-fdiv
│ ├── rv64ud-v-fdiv.dump
│ ├── rv64ud-v-fmadd
│ ├── rv64ud-v-fmadd.dump
│ ├── rv64ud-v-fmin
│ ├── rv64ud-v-fmin.dump
│ ├── rv64ud-v-ldst
│ ├── rv64ud-v-ldst.dump
│ ├── rv64ud-v-move
│ ├── rv64ud-v-move.dump
│ ├── rv64ud-v-recoding
│ ├── rv64ud-v-recoding.dump
│ ├── rv64ud-v-structural
│ ├── rv64ud-v-structural.dump
│ ├── rv64uf-p-fadd
│ ├── rv64uf-p-fadd.dump
│ ├── rv64uf-p-fclass
│ ├── rv64uf-p-fclass.dump
│ ├── rv64uf-p-fcmp
│ ├── rv64uf-p-fcmp.dump
│ ├── rv64uf-p-fcvt
│ ├── rv64uf-p-fcvt.dump
│ ├── rv64uf-p-fcvt_w
│ ├── rv64uf-p-fcvt_w.dump
│ ├── rv64uf-p-fdiv
│ ├── rv64uf-p-fdiv.dump
│ ├── rv64uf-p-fmadd
│ ├── rv64uf-p-fmadd.dump
│ ├── rv64uf-p-fmin
│ ├── rv64uf-p-fmin.dump
│ ├── rv64uf-p-ldst
│ ├── rv64uf-p-ldst.dump
│ ├── rv64uf-p-move
│ ├── rv64uf-p-move.dump
│ ├── rv64uf-p-recoding
│ ├── rv64uf-p-recoding.dump
│ ├── rv64uf-v-fadd
│ ├── rv64uf-v-fadd.dump
│ ├── rv64uf-v-fclass
│ ├── rv64uf-v-fclass.dump
│ ├── rv64uf-v-fcmp
│ ├── rv64uf-v-fcmp.dump
│ ├── rv64uf-v-fcvt
│ ├── rv64uf-v-fcvt.dump
│ ├── rv64uf-v-fcvt_w
│ ├── rv64uf-v-fcvt_w.dump
│ ├── rv64uf-v-fdiv
│ ├── rv64uf-v-fdiv.dump
│ ├── rv64uf-v-fmadd
│ ├── rv64uf-v-fmadd.dump
│ ├── rv64uf-v-fmin
│ ├── rv64uf-v-fmin.dump
│ ├── rv64uf-v-ldst
│ ├── rv64uf-v-ldst.dump
│ ├── rv64uf-v-move
│ ├── rv64uf-v-move.dump
│ ├── rv64uf-v-recoding
│ ├── rv64uf-v-recoding.dump
│ ├── rv64ui-p-add
│ ├── rv64ui-p-add.dump
│ ├── rv64ui-p-addi
│ ├── rv64ui-p-addi.dump
│ ├── rv64ui-p-addiw
│ ├── rv64ui-p-addiw.dump
│ ├── rv64ui-p-addw
│ ├── rv64ui-p-addw.dump
│ ├── rv64ui-p-and
│ ├── rv64ui-p-and.dump
│ ├── rv64ui-p-andi
│ ├── rv64ui-p-andi.dump
│ ├── rv64ui-p-auipc
│ ├── rv64ui-p-auipc.dump
│ ├── rv64ui-p-beq
│ ├── rv64ui-p-beq.dump
│ ├── rv64ui-p-bge
│ ├── rv64ui-p-bge.dump
│ ├── rv64ui-p-bgeu
│ ├── rv64ui-p-bgeu.dump
│ ├── rv64ui-p-blt
│ ├── rv64ui-p-blt.dump
│ ├── rv64ui-p-bltu
│ ├── rv64ui-p-bltu.dump
│ ├── rv64ui-p-bne
│ ├── rv64ui-p-bne.dump
│ ├── rv64ui-p-fence_i
│ ├── rv64ui-p-fence_i.dump
│ ├── rv64ui-p-jal
│ ├── rv64ui-p-jal.dump
│ ├── rv64ui-p-jalr
│ ├── rv64ui-p-jalr.dump
│ ├── rv64ui-p-lb
│ ├── rv64ui-p-lb.dump
│ ├── rv64ui-p-lbu
│ ├── rv64ui-p-lbu.dump
│ ├── rv64ui-p-ld
│ ├── rv64ui-p-ld.dump
│ ├── rv64ui-p-lh
│ ├── rv64ui-p-lh.dump
│ ├── rv64ui-p-lhu
│ ├── rv64ui-p-lhu.dump
│ ├── rv64ui-p-lui
│ ├── rv64ui-p-lui.dump
│ ├── rv64ui-p-lw
│ ├── rv64ui-p-lw.dump
│ ├── rv64ui-p-lwu
│ ├── rv64ui-p-lwu.dump
│ ├── rv64ui-p-or
│ ├── rv64ui-p-or.dump
│ ├── rv64ui-p-ori
│ ├── rv64ui-p-ori.dump
│ ├── rv64ui-p-sb
│ ├── rv64ui-p-sb.dump
│ ├── rv64ui-p-sd
│ ├── rv64ui-p-sd.dump
│ ├── rv64ui-p-sh
│ ├── rv64ui-p-sh.dump
│ ├── rv64ui-p-simple
│ ├── rv64ui-p-simple.dump
│ ├── rv64ui-p-sll
│ ├── rv64ui-p-sll.dump
│ ├── rv64ui-p-slli
│ ├── rv64ui-p-slli.dump
│ ├── rv64ui-p-slliw
│ ├── rv64ui-p-slliw.dump
│ ├── rv64ui-p-sllw
│ ├── rv64ui-p-sllw.dump
│ ├── rv64ui-p-slt
│ ├── rv64ui-p-slt.dump
│ ├── rv64ui-p-slti
│ ├── rv64ui-p-slti.dump
│ ├── rv64ui-p-sltiu
│ ├── rv64ui-p-sltiu.dump
│ ├── rv64ui-p-sltu
│ ├── rv64ui-p-sltu.dump
│ ├── rv64ui-p-sra
│ ├── rv64ui-p-sra.dump
│ ├── rv64ui-p-srai
│ ├── rv64ui-p-srai.dump
│ ├── rv64ui-p-sraiw
│ ├── rv64ui-p-sraiw.dump
│ ├── rv64ui-p-sraw
│ ├── rv64ui-p-sraw.dump
│ ├── rv64ui-p-srl
│ ├── rv64ui-p-srl.dump
│ ├── rv64ui-p-srli
│ ├── rv64ui-p-srli.dump
│ ├── rv64ui-p-srliw
│ ├── rv64ui-p-srliw.dump
│ ├── rv64ui-p-srlw
│ ├── rv64ui-p-srlw.dump
│ ├── rv64ui-p-sub
│ ├── rv64ui-p-sub.dump
│ ├── rv64ui-p-subw
│ ├── rv64ui-p-subw.dump
│ ├── rv64ui-p-sw
│ ├── rv64ui-p-sw.dump
│ ├── rv64ui-p-xor
│ ├── rv64ui-p-xor.dump
│ ├── rv64ui-p-xori
│ ├── rv64ui-p-xori.dump
│ ├── rv64ui-v-add
│ ├── rv64ui-v-add.dump
│ ├── rv64ui-v-addi
│ ├── rv64ui-v-addi.dump
│ ├── rv64ui-v-addiw
│ ├── rv64ui-v-addiw.dump
│ ├── rv64ui-v-addw
│ ├── rv64ui-v-addw.dump
│ ├── rv64ui-v-and
│ ├── rv64ui-v-and.dump
│ ├── rv64ui-v-andi
│ ├── rv64ui-v-andi.dump
│ ├── rv64ui-v-auipc
│ ├── rv64ui-v-auipc.dump
│ ├── rv64ui-v-beq
│ ├── rv64ui-v-beq.dump
│ ├── rv64ui-v-bge
│ ├── rv64ui-v-bge.dump
│ ├── rv64ui-v-bgeu
│ ├── rv64ui-v-bgeu.dump
│ ├── rv64ui-v-blt
│ ├── rv64ui-v-blt.dump
│ ├── rv64ui-v-bltu
│ ├── rv64ui-v-bltu.dump
│ ├── rv64ui-v-bne
│ ├── rv64ui-v-bne.dump
│ ├── rv64ui-v-fence_i
│ ├── rv64ui-v-fence_i.dump
│ ├── rv64ui-v-jal
│ ├── rv64ui-v-jal.dump
│ ├── rv64ui-v-jalr
│ ├── rv64ui-v-jalr.dump
│ ├── rv64ui-v-lb
│ ├── rv64ui-v-lb.dump
│ ├── rv64ui-v-lbu
│ ├── rv64ui-v-lbu.dump
│ ├── rv64ui-v-ld
│ ├── rv64ui-v-ld.dump
│ ├── rv64ui-v-lh
│ ├── rv64ui-v-lh.dump
│ ├── rv64ui-v-lhu
│ ├── rv64ui-v-lhu.dump
│ ├── rv64ui-v-lui
│ ├── rv64ui-v-lui.dump
│ ├── rv64ui-v-lw
│ ├── rv64ui-v-lw.dump
│ ├── rv64ui-v-lwu
│ ├── rv64ui-v-lwu.dump
│ ├── rv64ui-v-or
│ ├── rv64ui-v-or.dump
│ ├── rv64ui-v-ori
│ ├── rv64ui-v-ori.dump
│ ├── rv64ui-v-sb
│ ├── rv64ui-v-sb.dump
│ ├── rv64ui-v-sd
│ ├── rv64ui-v-sd.dump
│ ├── rv64ui-v-sh
│ ├── rv64ui-v-sh.dump
│ ├── rv64ui-v-simple
│ ├── rv64ui-v-simple.dump
│ ├── rv64ui-v-sll
│ ├── rv64ui-v-sll.dump
│ ├── rv64ui-v-slli
│ ├── rv64ui-v-slli.dump
│ ├── rv64ui-v-slliw
│ ├── rv64ui-v-slliw.dump
│ ├── rv64ui-v-sllw
│ ├── rv64ui-v-sllw.dump
│ ├── rv64ui-v-slt
│ ├── rv64ui-v-slt.dump
│ ├── rv64ui-v-slti
│ ├── rv64ui-v-slti.dump
│ ├── rv64ui-v-sltiu
│ ├── rv64ui-v-sltiu.dump
│ ├── rv64ui-v-sltu
│ ├── rv64ui-v-sltu.dump
│ ├── rv64ui-v-sra
│ ├── rv64ui-v-sra.dump
│ ├── rv64ui-v-srai
│ ├── rv64ui-v-srai.dump
│ ├── rv64ui-v-sraiw
│ ├── rv64ui-v-sraiw.dump
│ ├── rv64ui-v-sraw
│ ├── rv64ui-v-sraw.dump
│ ├── rv64ui-v-srl
│ ├── rv64ui-v-srl.dump
│ ├── rv64ui-v-srli
│ ├── rv64ui-v-srli.dump
│ ├── rv64ui-v-srliw
│ ├── rv64ui-v-srliw.dump
│ ├── rv64ui-v-srlw
│ ├── rv64ui-v-srlw.dump
│ ├── rv64ui-v-sub
│ ├── rv64ui-v-sub.dump
│ ├── rv64ui-v-subw
│ ├── rv64ui-v-subw.dump
│ ├── rv64ui-v-sw
│ ├── rv64ui-v-sw.dump
│ ├── rv64ui-v-xor
│ ├── rv64ui-v-xor.dump
│ ├── rv64ui-v-xori
│ ├── rv64ui-v-xori.dump
│ ├── rv64um-p-div
│ ├── rv64um-p-div.dump
│ ├── rv64um-p-divu
│ ├── rv64um-p-divu.dump
│ ├── rv64um-p-divuw
│ ├── rv64um-p-divuw.dump
│ ├── rv64um-p-divw
│ ├── rv64um-p-divw.dump
│ ├── rv64um-p-mul
│ ├── rv64um-p-mul.dump
│ ├── rv64um-p-mulh
│ ├── rv64um-p-mulh.dump
│ ├── rv64um-p-mulhsu
│ ├── rv64um-p-mulhsu.dump
│ ├── rv64um-p-mulhu
│ ├── rv64um-p-mulhu.dump
│ ├── rv64um-p-mulw
│ ├── rv64um-p-mulw.dump
│ ├── rv64um-p-rem
│ ├── rv64um-p-rem.dump
│ ├── rv64um-p-remu
│ ├── rv64um-p-remu.dump
│ ├── rv64um-p-remuw
│ ├── rv64um-p-remuw.dump
│ ├── rv64um-p-remw
│ ├── rv64um-p-remw.dump
│ ├── rv64um-v-div
│ ├── rv64um-v-div.dump
│ ├── rv64um-v-divu
│ ├── rv64um-v-divu.dump
│ ├── rv64um-v-divuw
│ ├── rv64um-v-divuw.dump
│ ├── rv64um-v-divw
│ ├── rv64um-v-divw.dump
│ ├── rv64um-v-mul
│ ├── rv64um-v-mul.dump
│ ├── rv64um-v-mulh
│ ├── rv64um-v-mulh.dump
│ ├── rv64um-v-mulhsu
│ ├── rv64um-v-mulhsu.dump
│ ├── rv64um-v-mulhu
│ ├── rv64um-v-mulhu.dump
│ ├── rv64um-v-mulw
│ ├── rv64um-v-mulw.dump
│ ├── rv64um-v-rem
│ ├── rv64um-v-rem.dump
│ ├── rv64um-v-remu
│ ├── rv64um-v-remu.dump
│ ├── rv64um-v-remuw
│ ├── rv64um-v-remuw.dump
│ ├── rv64um-v-remw
│ └── rv64um-v-remw.dump
├── builds/
│ ├── RV64ACDFIMSU_Toooba_bluesim/
│ │ └── Makefile
│ ├── RV64ACDFIMSU_Toooba_verilator/
│ │ ├── Makefile
│ │ └── Verilog_RTL/
│ │ ├── mkAXI4_Deburster_A.v
│ │ ├── mkAluDispToRegFifo.v
│ │ ├── mkAluExeToFinFifo.v
│ │ ├── mkAluRegToExeFifo.v
│ │ ├── mkBht.v
│ │ ├── mkBoot_ROM.v
│ │ ├── mkCore.v
│ │ ├── mkCoreW.v
│ │ ├── mkDCRqMshrWrapper.v
│ │ ├── mkDPRqMshrWrapper.v
│ │ ├── mkDPipeline.v
│ │ ├── mkDTlbSynth.v
│ │ ├── mkDirPredictor.v
│ │ ├── mkDivExecQ.v
│ │ ├── mkDoubleDiv.v
│ │ ├── mkDoubleFMA.v
│ │ ├── mkDoubleSqrt.v
│ │ ├── mkDummyStoreBuffer.v
│ │ ├── mkEpochManager.v
│ │ ├── mkFabric.v
│ │ ├── mkFabric_2x3.v
│ │ ├── mkFabric_AXI4.v
│ │ ├── mkFetchStage.v
│ │ ├── mkFmaExecQ.v
│ │ ├── mkFpuMulDivDispToRegFifo.v
│ │ ├── mkFpuMulDivRegToExeFifo.v
│ │ ├── mkGSelectGHistReg.v
│ │ ├── mkGSelectPred.v
│ │ ├── mkGShareGHistReg.v
│ │ ├── mkGSharePred.v
│ │ ├── mkIBankWrapper.v
│ │ ├── mkICRqMshrWrapper.v
│ │ ├── mkICoCache.v
│ │ ├── mkIPRqMshrWrapper.v
│ │ ├── mkIPipeline.v
│ │ ├── mkITlb.v
│ │ ├── mkL2Tlb.v
│ │ ├── mkLLCache.v
│ │ ├── mkLLPipeline.v
│ │ ├── mkLSQIssueLdQ.v
│ │ ├── mkLastLvCRqMshr.v
│ │ ├── mkMMIOInst.v
│ │ ├── mkMemDispToRegFifo.v
│ │ ├── mkMemLoader.v
│ │ ├── mkMemRegToExeFifo.v
│ │ ├── mkMem_Controller.v
│ │ ├── mkMem_Model.v
│ │ ├── mkMinimumExecQ.v
│ │ ├── mkMulExecQ.v
│ │ ├── mkNullTransCache.v
│ │ ├── mkPLIC_16_2_7.v
│ │ ├── mkProc.v
│ │ ├── mkRFileSynth.v
│ │ ├── mkRas.v
│ │ ├── mkRegRenamingTable.v
│ │ ├── mkReorderBufferSynth.v
│ │ ├── mkReservationStationAlu.v
│ │ ├── mkReservationStationFpuMulDiv.v
│ │ ├── mkReservationStationMem.v
│ │ ├── mkRobRowSynth.v
│ │ ├── mkScoreboardAggr.v
│ │ ├── mkScoreboardCons.v
│ │ ├── mkSimpleRespQ.v
│ │ ├── mkSoC_Map.v
│ │ ├── mkSoC_Top.v
│ │ ├── mkSpecTagManager.v
│ │ ├── mkSplitLSQ.v
│ │ ├── mkSplitTransCache.v
│ │ ├── mkStoreBufferEhr.v
│ │ ├── mkSyncBramFifo_w36_d512.v
│ │ ├── mkSyncFifo_w32_d16.v
│ │ ├── mkTop_HW_Side.v
│ │ ├── mkTourGHistReg.v
│ │ ├── mkTourPred.v
│ │ ├── mkTourPredSecure.v
│ │ ├── mkUART.v
│ │ ├── mkXilinxFpDiv.v
│ │ ├── mkXilinxFpDivIP.v
│ │ ├── mkXilinxFpDivSim.v
│ │ ├── mkXilinxFpFma.v
│ │ ├── mkXilinxFpFmaIP.v
│ │ ├── mkXilinxFpFmaSim.v
│ │ ├── mkXilinxFpSqrt.v
│ │ ├── mkXilinxFpSqrtIP.v
│ │ ├── mkXilinxFpSqrtSim.v
│ │ ├── module_alu.v
│ │ ├── module_aluBr.v
│ │ ├── module_amoExec.v
│ │ ├── module_basicExec.v
│ │ ├── module_brAddrCalc.v
│ │ ├── module_checkForException.v
│ │ ├── module_decode.v
│ │ ├── module_decodeBrPred.v
│ │ ├── module_execFpuSimple.v
│ │ └── module_getControlFlow.v
│ └── Resources/
│ ├── Include_Common.mk
│ ├── Include_RISCY_Config.mk
│ ├── Include_bluesim.mk
│ ├── Include_verilator.mk
│ └── Verilator_resources/
│ ├── import_DPI_C_decls.v
│ ├── sed_script.txt
│ ├── sim_main.cpp
│ └── verilator_config.vlt
├── src_Core/
│ ├── BSV_Additional_Libs/
│ │ ├── AXI4_Stream.bsv
│ │ ├── ByteLane.bsv
│ │ ├── CreditCounter.bsv
│ │ ├── Cur_Cycle.bsv
│ │ ├── EdgeFIFOFs.bsv
│ │ ├── GetPut_Aux.bsv
│ │ └── Semi_FIFOF.bsv
│ ├── CPU/
│ │ ├── CPU_Decode_C.bsv
│ │ ├── Core.bsv
│ │ ├── CsrFile.bsv
│ │ ├── LLC_AXI4_Adapter.bsv
│ │ ├── MMIOPlatform.bsv
│ │ ├── MMIO_AXI4_Adapter.bsv
│ │ ├── Proc.bsv
│ │ └── Proc_IFC.bsv
│ ├── Core/
│ │ ├── CoreW.bsv
│ │ ├── CoreW_IFC.bsv
│ │ ├── Fabric_Defs.bsv
│ │ ├── TV_Encode.bsv
│ │ ├── TV_Taps.bsv
│ │ ├── Trace_Data2.bsv
│ │ └── Trace_Data2_to_Trace_Data.bsv
│ ├── Debug_Module/
│ │ ├── DM_Abstract_Commands.bsv
│ │ ├── DM_CPU_Req_Rsp.bsv
│ │ ├── DM_Common.bsv
│ │ ├── DM_Run_Control.bsv
│ │ ├── DM_System_Bus.bsv
│ │ ├── Debug_Module.bsv
│ │ ├── README.txt
│ │ └── Test/
│ │ ├── Makefile
│ │ └── Testbench.bsv
│ ├── ISA/
│ │ ├── ISA_Decls.bsv
│ │ ├── ISA_Decls_C.bsv
│ │ ├── ISA_Decls_Priv_M.bsv
│ │ ├── ISA_Decls_Priv_S.bsv
│ │ └── TV_Info.bsv
│ ├── PLIC/
│ │ ├── Makefile
│ │ ├── PLIC.bsv
│ │ ├── PLIC_16_CoreNumX2_7.bsv
│ │ ├── README_PLIC.txt
│ │ └── Test_PLIC.bsv
│ └── RISCY_OOO/
│ ├── LICENSE_RISCY-OOO
│ ├── Makefile
│ ├── coherence/
│ │ └── src/
│ │ ├── CCPipe.bsv
│ │ ├── CCTypes.bsv
│ │ ├── CrossBar.bsv
│ │ ├── IBank.bsv
│ │ ├── ICRqMshr.bsv
│ │ ├── IPRqMshr.bsv
│ │ ├── L1Bank.bsv
│ │ ├── L1CRqMshr.bsv
│ │ ├── L1PRqMshr.bsv
│ │ ├── L1Pipe.bsv
│ │ ├── LLBank.bsv
│ │ ├── LLCRqMshr.bsv
│ │ ├── LLPipe.bsv
│ │ ├── MshrDeadlockChecker.bsv
│ │ ├── Prefetcher.bsv
│ │ ├── RWBramCore.bsv
│ │ ├── RandomReplace.bsv
│ │ ├── SelfInvIBank.bsv
│ │ ├── SelfInvIPipe.bsv
│ │ ├── SelfInvL1Bank.bsv
│ │ ├── SelfInvL1Pipe.bsv
│ │ ├── SelfInvLLBank.bsv
│ │ └── SelfInvLLPipe.bsv
│ ├── connectal/
│ │ ├── bsv/
│ │ │ ├── ConnectalBramFifo.bsv
│ │ │ └── ConnectalClocks.bsv
│ │ ├── lib/
│ │ │ └── bsv/
│ │ │ └── Arith.bsv
│ │ └── tests/
│ │ └── spi/
│ │ └── ConnectalProjectConfig.bsv
│ ├── fpgautils/
│ │ ├── lib/
│ │ │ ├── DramCommon.bsv
│ │ │ ├── ResetGuard.bsv
│ │ │ ├── SyncFifo.bsv
│ │ │ ├── WaitAutoReset.bsv
│ │ │ ├── XilinxFpu.bsv
│ │ │ ├── XilinxIntDiv.bsv
│ │ │ ├── XilinxIntMul.bsv
│ │ │ └── XilinxSyncFifo.bsv
│ │ └── xilinx/
│ │ ├── fpu/
│ │ │ ├── fp_div_sim.v
│ │ │ ├── fp_fma_sim.v
│ │ │ └── fp_sqrt_sim.v
│ │ └── reset_regs/
│ │ └── reset_guard.v
│ └── procs/
│ ├── RV64G_OOO/
│ │ ├── AluExePipeline.bsv
│ │ ├── CommitStage.bsv
│ │ ├── FetchStage.bsv
│ │ ├── FpuMulDivExePipeline.bsv
│ │ ├── MemExePipeline.bsv
│ │ ├── ProcConfig.bsv
│ │ ├── RFileSynth.bsv
│ │ ├── RenameStage.bsv
│ │ ├── ReorderBufferSynth.bsv
│ │ ├── ReservationStationAlu.bsv
│ │ ├── ReservationStationFpuMulDiv.bsv
│ │ ├── ReservationStationMem.bsv
│ │ ├── ScoreboardSynth.bsv
│ │ └── SynthParam.bsv
│ └── lib/
│ ├── Amo.bsv
│ ├── Bht.bsv
│ ├── BrPred.bsv
│ ├── Btb.bsv
│ ├── Bypass.bsv
│ ├── CacheUtils.bsv
│ ├── ConcatReg.bsv
│ ├── DTlb.bsv
│ ├── Decode.bsv
│ ├── DirPredictor.bsv
│ ├── Ehr.bsv
│ ├── EpochManager.bsv
│ ├── Exec.bsv
│ ├── FP_Utils.bsv
│ ├── Fifos.bsv
│ ├── Fpu.bsv
│ ├── FullAssocTlb.bsv
│ ├── GSelectPred.bsv
│ ├── GSharePred.bsv
│ ├── GlobalBrHistReg.bsv
│ ├── GlobalSpecUpdate.bsv
│ ├── HasSpecBits.bsv
│ ├── ITlb.bsv
│ ├── IndexedMultiset.bsv
│ ├── L1CoCache.bsv
│ ├── L1LLConnect.bsv
│ ├── L2SetAssocTlb.bsv
│ ├── L2Tlb.bsv
│ ├── LLCDmaConnect.bsv
│ ├── LLCRqMshrSecureModel.bsv
│ ├── LLCache.bsv
│ ├── LatencyTimer.bsv
│ ├── MMIOAddrs.bsv
│ ├── MMIOCore.bsv
│ ├── MMIOInst.bsv
│ ├── Map.bsv
│ ├── MemLoader.bsv
│ ├── MemLoaderIF.bsv
│ ├── MemoryTypes.bsv
│ ├── MsgFifo.bsv
│ ├── MulDiv.bsv
│ ├── Performance.bsv
│ ├── PhysRFile.bsv
│ ├── ProcTypes.bsv
│ ├── Ras.bsv
│ ├── RenameDebugIF.bsv
│ ├── RenamingTable.bsv
│ ├── ReorderBuffer.bsv
│ ├── ReservationStationEhr.bsv
│ ├── SafeCounter.bsv
│ ├── Scoreboard.bsv
│ ├── SetAssocTlb.bsv
│ ├── SpecFifo.bsv
│ ├── SpecPoisonFifo.bsv
│ ├── SpecTagManager.bsv
│ ├── SplitLSQ.bsv
│ ├── StoreBuffer.bsv
│ ├── TlbConnect.bsv
│ ├── TlbTypes.bsv
│ ├── TourPred.bsv
│ ├── TourPredSecure.bsv
│ ├── TranslationCache.bsv
│ ├── Types.bsv
│ └── VerificationPacket.bsv
├── src_SSITH_P3/
│ ├── Makefile
│ ├── README.txt
│ ├── Verilog_RTL/
│ │ ├── mkAluDispToRegFifo.v
│ │ ├── mkAluExeToFinFifo.v
│ │ ├── mkAluRegToExeFifo.v
│ │ ├── mkBht.v
│ │ ├── mkCore.v
│ │ ├── mkCoreW.v
│ │ ├── mkDCRqMshrWrapper.v
│ │ ├── mkDM_Abstract_Commands.v
│ │ ├── mkDM_CSR_Tap.v
│ │ ├── mkDM_GPR_Tap.v
│ │ ├── mkDM_Mem_Tap.v
│ │ ├── mkDM_Run_Control.v
│ │ ├── mkDM_System_Bus.v
│ │ ├── mkDPRqMshrWrapper.v
│ │ ├── mkDPipeline.v
│ │ ├── mkDTlbSynth.v
│ │ ├── mkDebug_Module.v
│ │ ├── mkDirPredictor.v
│ │ ├── mkDivExecQ.v
│ │ ├── mkDoubleDiv.v
│ │ ├── mkDoubleFMA.v
│ │ ├── mkDoubleSqrt.v
│ │ ├── mkDummyStoreBuffer.v
│ │ ├── mkEpochManager.v
│ │ ├── mkFabric_2x3.v
│ │ ├── mkFetchStage.v
│ │ ├── mkFmaExecQ.v
│ │ ├── mkFpuMulDivDispToRegFifo.v
│ │ ├── mkFpuMulDivRegToExeFifo.v
│ │ ├── mkGSelectGHistReg.v
│ │ ├── mkGSelectPred.v
│ │ ├── mkGShareGHistReg.v
│ │ ├── mkGSharePred.v
│ │ ├── mkIBankWrapper.v
│ │ ├── mkICRqMshrWrapper.v
│ │ ├── mkICoCache.v
│ │ ├── mkIPRqMshrWrapper.v
│ │ ├── mkIPipeline.v
│ │ ├── mkITlb.v
│ │ ├── mkJtagTap.v
│ │ ├── mkL2Tlb.v
│ │ ├── mkLLCache.v
│ │ ├── mkLLPipeline.v
│ │ ├── mkLSQIssueLdQ.v
│ │ ├── mkLastLvCRqMshr.v
│ │ ├── mkMMIOInst.v
│ │ ├── mkMemDispToRegFifo.v
│ │ ├── mkMemLoader.v
│ │ ├── mkMemRegToExeFifo.v
│ │ ├── mkMinimumExecQ.v
│ │ ├── mkMulExecQ.v
│ │ ├── mkNullTransCache.v
│ │ ├── mkP3_Core.v
│ │ ├── mkPLIC_16_2_7.v
│ │ ├── mkPowerOnReset.v
│ │ ├── mkProc.v
│ │ ├── mkRFileSynth.v
│ │ ├── mkRas.v
│ │ ├── mkRegRenamingTable.v
│ │ ├── mkReorderBufferSynth.v
│ │ ├── mkReservationStationAlu.v
│ │ ├── mkReservationStationFpuMulDiv.v
│ │ ├── mkReservationStationMem.v
│ │ ├── mkRobRowSynth.v
│ │ ├── mkScoreboardAggr.v
│ │ ├── mkScoreboardCons.v
│ │ ├── mkSimpleRespQ.v
│ │ ├── mkSoC_Map.v
│ │ ├── mkSpecTagManager.v
│ │ ├── mkSplitLSQ.v
│ │ ├── mkSplitTransCache.v
│ │ ├── mkStoreBufferEhr.v
│ │ ├── mkSyncBramFifo_w36_d512.v
│ │ ├── mkSyncFifo_w32_d16.v
│ │ ├── mkTV_Encode.v
│ │ ├── mkTV_Xactor.v
│ │ ├── mkTourGHistReg.v
│ │ ├── mkTourPred.v
│ │ ├── mkTourPredSecure.v
│ │ ├── mkTrace_Data2_to_Trace_Data.v
│ │ ├── mkXilinxFpDiv.v
│ │ ├── mkXilinxFpDivIP.v
│ │ ├── mkXilinxFpDivSim.v
│ │ ├── mkXilinxFpFma.v
│ │ ├── mkXilinxFpFmaIP.v
│ │ ├── mkXilinxFpFmaSim.v
│ │ ├── mkXilinxFpSqrt.v
│ │ ├── mkXilinxFpSqrtIP.v
│ │ ├── mkXilinxFpSqrtSim.v
│ │ ├── module_alu.v
│ │ ├── module_aluBr.v
│ │ ├── module_amoExec.v
│ │ ├── module_basicExec.v
│ │ ├── module_brAddrCalc.v
│ │ ├── module_checkForException.v
│ │ ├── module_decode.v
│ │ ├── module_decodeBrPred.v
│ │ ├── module_execFpuSimple.v
│ │ └── module_getControlFlow.v
│ ├── Verilog_RTL_sim/
│ │ ├── ASSIGN1.v
│ │ ├── MakeReset0.v
│ │ ├── RegUNInit.v
│ │ ├── SyncWire.v
│ │ ├── mkAluDispToRegFifo.v
│ │ ├── mkAluExeToFinFifo.v
│ │ ├── mkAluRegToExeFifo.v
│ │ ├── mkBht.v
│ │ ├── mkCore.v
│ │ ├── mkCoreW.v
│ │ ├── mkDCRqMshrWrapper.v
│ │ ├── mkDM_Abstract_Commands.v
│ │ ├── mkDM_CSR_Tap.v
│ │ ├── mkDM_GPR_Tap.v
│ │ ├── mkDM_Mem_Tap.v
│ │ ├── mkDM_Run_Control.v
│ │ ├── mkDM_System_Bus.v
│ │ ├── mkDPRqMshrWrapper.v
│ │ ├── mkDPipeline.v
│ │ ├── mkDTlbSynth.v
│ │ ├── mkDebug_Module.v
│ │ ├── mkDirPredictor.v
│ │ ├── mkDivExecQ.v
│ │ ├── mkDoubleDiv.v
│ │ ├── mkDoubleFMA.v
│ │ ├── mkDoubleSqrt.v
│ │ ├── mkDummyStoreBuffer.v
│ │ ├── mkEpochManager.v
│ │ ├── mkFabric_2x3.v
│ │ ├── mkFetchStage.v
│ │ ├── mkFmaExecQ.v
│ │ ├── mkFpuMulDivDispToRegFifo.v
│ │ ├── mkFpuMulDivRegToExeFifo.v
│ │ ├── mkGSelectGHistReg.v
│ │ ├── mkGSelectPred.v
│ │ ├── mkGShareGHistReg.v
│ │ ├── mkGSharePred.v
│ │ ├── mkIBankWrapper.v
│ │ ├── mkICRqMshrWrapper.v
│ │ ├── mkICoCache.v
│ │ ├── mkIPRqMshrWrapper.v
│ │ ├── mkIPipeline.v
│ │ ├── mkITlb.v
│ │ ├── mkJtagTap.v
│ │ ├── mkL2Tlb.v
│ │ ├── mkLLCache.v
│ │ ├── mkLLPipeline.v
│ │ ├── mkLSQIssueLdQ.v
│ │ ├── mkLastLvCRqMshr.v
│ │ ├── mkMMIOInst.v
│ │ ├── mkMemDispToRegFifo.v
│ │ ├── mkMemLoader.v
│ │ ├── mkMemRegToExeFifo.v
│ │ ├── mkMinimumExecQ.v
│ │ ├── mkMulExecQ.v
│ │ ├── mkNullTransCache.v
│ │ ├── mkP3_Core.v
│ │ ├── mkPLIC_16_2_7.v
│ │ ├── mkPowerOnReset.v
│ │ ├── mkProc.v
│ │ ├── mkRFileSynth.v
│ │ ├── mkRas.v
│ │ ├── mkRegRenamingTable.v
│ │ ├── mkReorderBufferSynth.v
│ │ ├── mkReservationStationAlu.v
│ │ ├── mkReservationStationFpuMulDiv.v
│ │ ├── mkReservationStationMem.v
│ │ ├── mkRobRowSynth.v
│ │ ├── mkScoreboardAggr.v
│ │ ├── mkScoreboardCons.v
│ │ ├── mkSimpleRespQ.v
│ │ ├── mkSoC_Map.v
│ │ ├── mkSpecTagManager.v
│ │ ├── mkSplitLSQ.v
│ │ ├── mkSplitTransCache.v
│ │ ├── mkStoreBufferEhr.v
│ │ ├── mkSyncBramFifo_w36_d512.v
│ │ ├── mkSyncFifo_w32_d16.v
│ │ ├── mkTV_Encode.v
│ │ ├── mkTV_Xactor.v
│ │ ├── mkTourGHistReg.v
│ │ ├── mkTourPred.v
│ │ ├── mkTourPredSecure.v
│ │ ├── mkTrace_Data2_to_Trace_Data.v
│ │ ├── mkXilinxFpDiv.v
│ │ ├── mkXilinxFpDivIP.v
│ │ ├── mkXilinxFpDivSim.v
│ │ ├── mkXilinxFpFma.v
│ │ ├── mkXilinxFpFmaIP.v
│ │ ├── mkXilinxFpFmaSim.v
│ │ ├── mkXilinxFpSqrt.v
│ │ ├── mkXilinxFpSqrtIP.v
│ │ ├── mkXilinxFpSqrtSim.v
│ │ ├── module_alu.v
│ │ ├── module_aluBr.v
│ │ ├── module_amoExec.v
│ │ ├── module_basicExec.v
│ │ ├── module_brAddrCalc.v
│ │ ├── module_checkForException.v
│ │ ├── module_decode.v
│ │ ├── module_decodeBrPred.v
│ │ ├── module_execFpuSimple.v
│ │ └── module_getControlFlow.v
│ ├── src_BSV/
│ │ ├── ClockHacks.bsv
│ │ ├── Giraffe.defines
│ │ ├── Giraffe_IFC.bsv
│ │ ├── JtagTap.bsv
│ │ ├── P3_Core.bsv
│ │ ├── PowerOnReset.bsv
│ │ └── SoC_Map.bsv
│ └── xilinx_ip/
│ ├── component.xml
│ ├── hdl/
│ │ ├── ASSIGN1.v
│ │ ├── BRAM2.v
│ │ ├── Counter.v
│ │ ├── FIFO1.v
│ │ ├── FIFO10.v
│ │ ├── FIFO2.v
│ │ ├── FIFO20.v
│ │ ├── FIFOL1.v
│ │ ├── MakeClock.v
│ │ ├── MakeReset0.v
│ │ ├── MakeResetA.v
│ │ ├── RegFile.v
│ │ ├── RegUNInit.v
│ │ ├── ResetEither.v
│ │ ├── RevertReg.v
│ │ ├── SizedFIFO.v
│ │ ├── SizedFIFO0.v
│ │ ├── SyncFIFOLevel.v
│ │ ├── SyncHandshake.v
│ │ ├── SyncReset0.v
│ │ ├── SyncResetA.v
│ │ ├── SyncWire.v
│ │ ├── mkAluDispToRegFifo.v
│ │ ├── mkAluExeToFinFifo.v
│ │ ├── mkAluRegToExeFifo.v
│ │ ├── mkBht.v
│ │ ├── mkCore.v
│ │ ├── mkCoreW.v
│ │ ├── mkDCRqMshrWrapper.v
│ │ ├── mkDM_Abstract_Commands.v
│ │ ├── mkDM_CSR_Tap.v
│ │ ├── mkDM_GPR_Tap.v
│ │ ├── mkDM_Mem_Tap.v
│ │ ├── mkDM_Run_Control.v
│ │ ├── mkDM_System_Bus.v
│ │ ├── mkDPRqMshrWrapper.v
│ │ ├── mkDPipeline.v
│ │ ├── mkDTlbSynth.v
│ │ ├── mkDebug_Module.v
│ │ ├── mkDirPredictor.v
│ │ ├── mkDivExecQ.v
│ │ ├── mkDoubleDiv.v
│ │ ├── mkDoubleFMA.v
│ │ ├── mkDoubleSqrt.v
│ │ ├── mkDummyStoreBuffer.v
│ │ ├── mkEpochManager.v
│ │ ├── mkFabric_2x3.v
│ │ ├── mkFetchStage.v
│ │ ├── mkFmaExecQ.v
│ │ ├── mkFpuMulDivDispToRegFifo.v
│ │ ├── mkFpuMulDivRegToExeFifo.v
│ │ ├── mkGSelectGHistReg.v
│ │ ├── mkGSelectPred.v
│ │ ├── mkGShareGHistReg.v
│ │ ├── mkGSharePred.v
│ │ ├── mkIBankWrapper.v
│ │ ├── mkICRqMshrWrapper.v
│ │ ├── mkICoCache.v
│ │ ├── mkIPRqMshrWrapper.v
│ │ ├── mkIPipeline.v
│ │ ├── mkITlb.v
│ │ ├── mkJtagTap.v
│ │ ├── mkL2Tlb.v
│ │ ├── mkLLCache.v
│ │ ├── mkLLPipeline.v
│ │ ├── mkLSQIssueLdQ.v
│ │ ├── mkLastLvCRqMshr.v
│ │ ├── mkMMIOInst.v
│ │ ├── mkMemDispToRegFifo.v
│ │ ├── mkMemLoader.v
│ │ ├── mkMemRegToExeFifo.v
│ │ ├── mkMinimumExecQ.v
│ │ ├── mkMulExecQ.v
│ │ ├── mkNullTransCache.v
│ │ ├── mkP3_Core.v
│ │ ├── mkPLIC_16_2_7.v
│ │ ├── mkPowerOnReset.v
│ │ ├── mkProc.v
│ │ ├── mkRFileSynth.v
│ │ ├── mkRas.v
│ │ ├── mkRegRenamingTable.v
│ │ ├── mkReorderBufferSynth.v
│ │ ├── mkReservationStationAlu.v
│ │ ├── mkReservationStationFpuMulDiv.v
│ │ ├── mkReservationStationMem.v
│ │ ├── mkRobRowSynth.v
│ │ ├── mkScoreboardAggr.v
│ │ ├── mkScoreboardCons.v
│ │ ├── mkSimpleRespQ.v
│ │ ├── mkSoC_Map.v
│ │ ├── mkSpecTagManager.v
│ │ ├── mkSplitLSQ.v
│ │ ├── mkSplitTransCache.v
│ │ ├── mkStoreBufferEhr.v
│ │ ├── mkSyncBramFifo_w36_d512.v
│ │ ├── mkSyncFifo_w32_d16.v
│ │ ├── mkTV_Encode.v
│ │ ├── mkTV_Xactor.v
│ │ ├── mkTourGHistReg.v
│ │ ├── mkTourPred.v
│ │ ├── mkTourPredSecure.v
│ │ ├── mkTrace_Data2_to_Trace_Data.v
│ │ ├── mkXilinxFpDiv.v
│ │ ├── mkXilinxFpDivIP.v
│ │ ├── mkXilinxFpDivSim.v
│ │ ├── mkXilinxFpFma.v
│ │ ├── mkXilinxFpFmaIP.v
│ │ ├── mkXilinxFpFmaSim.v
│ │ ├── mkXilinxFpSqrt.v
│ │ ├── mkXilinxFpSqrtIP.v
│ │ ├── mkXilinxFpSqrtSim.v
│ │ ├── module_alu.v
│ │ ├── module_aluBr.v
│ │ ├── module_amoExec.v
│ │ ├── module_basicExec.v
│ │ ├── module_brAddrCalc.v
│ │ ├── module_checkForException.v
│ │ ├── module_decode.v
│ │ ├── module_decodeBrPred.v
│ │ ├── module_execFpuSimple.v
│ │ ├── module_getControlFlow.v
│ │ └── reset_guard.v
│ ├── src/
│ │ ├── fp_div/
│ │ │ ├── fp_div.xci
│ │ │ └── fp_div.xml
│ │ ├── fp_fma/
│ │ │ ├── fp_fma.xci
│ │ │ └── fp_fma.xml
│ │ ├── fp_sqrt/
│ │ │ ├── fp_sqrt.xci
│ │ │ └── fp_sqrt.xml
│ │ ├── int_div_unsigned/
│ │ │ ├── int_div_unsigned.xci
│ │ │ └── int_div_unsigned.xml
│ │ ├── int_mul_signed/
│ │ │ ├── int_mul_signed.xci
│ │ │ └── int_mul_signed.xml
│ │ ├── int_mul_signed_unsigned/
│ │ │ ├── int_mul_signed_unsigned.xci
│ │ │ └── int_mul_signed_unsigned.xml
│ │ ├── int_mul_unsigned/
│ │ │ ├── int_mul_unsigned.xci
│ │ │ └── int_mul_unsigned.xml
│ │ └── p3_constraints.xdc
│ └── xgui/
│ ├── mkP3_Core_v1_0.tcl
│ └── ssith_processor_v1_0.tcl
├── src_Testbench/
│ ├── Fabrics/
│ │ ├── AXI4/
│ │ │ ├── AXI4_Deburster.bsv
│ │ │ ├── AXI4_Fabric.bsv
│ │ │ ├── AXI4_Mem_Model.bsv
│ │ │ ├── AXI4_Types.bsv
│ │ │ └── Unit_Test/
│ │ │ ├── Makefile
│ │ │ └── Unit_Test_Deburster.bsv
│ │ ├── AXI4_Lite/
│ │ │ ├── AXI4_Lite_Fabric.bsv
│ │ │ └── AXI4_Lite_Types.bsv
│ │ └── Adapters/
│ │ └── AXI4_AXI4_Lite_Adapters.bsv
│ ├── SoC/
│ │ ├── Boot_ROM.bsv
│ │ ├── Boot_ROM_Generator/
│ │ │ ├── .gitignore
│ │ │ ├── Gen_BSV_fn_read_ROM.py
│ │ │ ├── Makefile
│ │ │ └── gen_bootrom.cc
│ │ ├── External_Control.bsv
│ │ ├── Mem_Controller.bsv
│ │ ├── SoC_Fabric.bsv
│ │ ├── SoC_Map.bsv
│ │ ├── SoC_Top.bsv
│ │ ├── Timer.bsv
│ │ ├── UART_Model.bsv
│ │ ├── fn_read_ROM_RV32.bsvi
│ │ └── fn_read_ROM_RV64.bsvi
│ ├── Top/
│ │ ├── C_Imported_Functions.c
│ │ ├── C_Imported_Functions.h
│ │ ├── C_Imports.bsv
│ │ ├── Makefile
│ │ ├── Mem_Model.bsv
│ │ └── Top_HW_Side.bsv
│ └── Unit/
│ └── Prefetcher_test.bsv
└── src_bsc_lib_RTL/
├── BRAM2.v
├── FIFO1.v
├── FIFO10.v
├── FIFO2.v
├── FIFO20.v
├── FIFOL1.v
├── MakeClock.v
├── MakeResetA.v
├── README.txt
├── RegFile.v
├── RegFileLoad.v
├── ResetEither.v
├── RevertReg.v
├── SizedFIFO.v
├── SizedFIFO0.v
├── SyncFIFOLevel.v
├── SyncHandshake.v
├── SyncResetA.v
└── main.v
================================================
FILE CONTENTS
================================================
================================================
FILE: .gitignore
================================================
*~
README.html
build_dir
*.bo
*.ba
*.o
obj_dir
elf_to_hex
Mem.hex
exe*
*.log
Tests/Logs
*_edited.v
*.trace_mem_load
AA_*
symbol_table.txt
vpi_wrapper_*
================================================
FILE: .gitmodules
================================================
[submodule "src_Core/BSV_Additional_Libs/BlueStuff"]
path = src_Core/BSV_Additional_Libs/BlueStuff
url = https://github.com/CTSRD-CHERI/BlueStuff.git
================================================
FILE: LICENSE
================================================
This repository contains code with two licenses.
1. See: src_Core/RISCY_OOO/LICENSE_RISCY-OOO
The code in src_Core/RISCY_OOO is mostly a copy of MIT's
'riscy-ooo' processor, free and open-source under
LICENSE_RISC-OOO.
That code has been slightly modified by Bluespec, Inc. (see README for details).
2. Bluespec's modifications in src_Core/RISCY_OOO and the rest of this
repository are licensed under the license shown below.
>================================================================
Apache License
Version 2.0, January 2004
http://www.apache.org/licenses/
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
1. Definitions.
"License" shall mean the terms and conditions for use, reproduction,
and distribution as defined by Sections 1 through 9 of this document.
"Licensor" shall mean the copyright owner or entity authorized by
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APPENDIX: How to apply the Apache License to your work.
To apply the Apache License to your work, attach the following
boilerplate notice, with the fields enclosed by brackets "[]"
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See the License for the specific language governing permissions and
limitations under the License.
================================================
FILE: README.md
================================================
# Open-source RISC-V CPUs from Bluespec, Inc.
This is one of a family of free, open-source RISC-V CPUs created by Bluespec, Inc.
- [Piccolo](https://github.com/bluespec/Piccolo): 3-stage, in-order pipeline
Piccolo is intended for low-end applications (Embedded Systems, IoT, microcontrollers, etc.).
- [Flute](https://github.com/bluespec/Flute): 5-stage, in-order pipeline
Flute is intended for low-end to medium applications that require
64-bit operation, an MMU (Virtual Memory) and more performance than
Piccolo-class processors.
- [Toooba](https://github.com/bluespec/Toooba): superscalar, out-of-order
pipeline, slight variation on MIT's RISCY-OOO
Toooba is intended as a high-end application processor.
The three repo structures are nearly identical, and the ways to build
and run are identical.
----------------------------------------------------------------
### Note re. distribution of MIT RISCY-OOO sources.
The directory `src_Core/RISCY_OOO` contains sources copied from MIT's
`riscy-OOO` repository. See `LICENSE_RISCY-OOO` for MIT's license.
[Note: MIT's repository is on an MIT git server, which can only be
accessed with credentials; hence the local copy in of these files.]
Bluespec's modifications to files in src_Core/RISCY_OOO are relatively
small and mostly additive:
- To add the RISC-V 'C' extension (compressed instructions)
- To add support for Bluespec's Tandem Verification
- To add support for Bluespec's Debug Module.
- To fix about bugs leading to about half a dozen failures of standard RISC-V ISA tests
----------------------------------------------------------------
### About the source codes (in BSV and Verilog)
The BSV source code in this repository, from which the synthesizable
Verilog RTL in this repository is generated, is highly parameterized
to allow generating many possible configurations, some of which are
adequate to boot a Linux kernel.
The pre-generated synthesizable Verilog RTL source files in this
repository are for one specific configuration:
1. RV64ACDFIMSU (a.k.a. RV64GC)
- RV64I: base RV64 integer instructions
- 'A' extension: atomic memory ops
- 'C' extension: compressed instructions
- 'D' extension: double-precision floating point instructions
- 'F' extension: single-precision floating point instructions
- 'M' extension: integer multiply/divide instructions
- Privilege levels M (machine), S (Supervisor) and U (user)
- Supports external, timer, software and non-maskable interrupts
- Passes all riscv-isa tests for RV64ACDFIMSU
- Boots the Linux kernel
If you want to generate other Verilog variants, you'll need a Bluespec
`bsc` compiler [Note: Bluespec, Inc. provides free licenses to
academia and for non-profit research].
### Testbench included
This repository contains a simple testbench (a small SoC) with which
one can run RISC-V binaries in simulation by loading standard mem hex
files and executing in Bluespec's Bluesim, Verilator simulation or
iVerilog simulation. The testbench contains an AXI4 interconnect
fabric that connects the CPU to models of a boot ROM, a memory, a
timer and a UART for console I/O.
[Note: **iverilog functionality is currently limited** because we are
still working out robust mechanisms to import C code, which is used in
parts of the testbench.]
This repository contains one sample build directory, to build
an RV64ACDFIMSU simulator, using Verilator Verilog simulation.
The generated Verilog is synthesizable. Bluespec tests all this code
on Xilinx FPGAs.
#### Plans
- Ongoing continuous micro-architectural improvements for performance and hardware area.
----------------------------------------------------------------
## Source codes
This repository contains two levels of source code: Verilog and BSV.
**Verilog RTL** can be found in directories with names suffixed in
'_verilator' or '_iverilog' in the 'builds' directory:
builds/..._<verilator or iverilog>/Verilog_RTL/
[There is no difference between Verilog in a Verilator directory
vs. the corresponding iverilog directory. ]
The Verilog RTL is _synthesizable_ (and hence acceptable to
Verilator). It can be simulated in any Verilog simulator (we provide
Makefiles to build simulation executables for Verilator and for Icarus
Verilog (iverilog)).
The RTL represents RISC-V CPU RTL, plus a rudimentary surrounding SoC
enabling immediate simulation here, and which is rich enough to enable
booting a Linux kernel. Users are free to use the CPU RTL in their
own Verilog system designs. The top-level module for the CPU RTL is
`Verilog_RTL/mkProc.v`. The top-level module for the surrounding
SoC is `Verilog_RTL/mkTop_HW_Side.v`. The SoC has an AXI4
fabric, a timer, a software-interrupt device, and a UART. Additional
library RTL can be found in the directory `src_bsc_lib_RTL`.
**Bluespec BSV** source code (which was used to generate the Verilog RTL) can be found in:
- `src_Core/`, for the CPU core, with sub-directories:
- `Core/`: the top-level of the CPU Core (specifically, the files CoreW_IFC.bsv and CoreW.bsv)
- 'CPU/': more CPU core sources
- 'RISCY_OOO': the bulk of the code, taken from MIT's riscy-ooo design, with local modifications.
- `ISA/`: generic types/constants/functions for the RISC-V ISA (not CPU-implementation-specific)
- 'PLIC/': Platform-Level Interrupt Controller (standard RISC-V spec)
- `BSV_Additional_Libs/`: generic utilities (not CPU-specific)
- `Debug_Module/`: RISC-V Debug Module to debug the CPU from GDB or other debuggers
- `src_Testbench/`, for the surrounding testbench, with sub-directories:
- `Top/`: The system top-level (`Top_HW_Side.bsv`), a memory model
that loads from a memory hex file, and some imported C
functions for polled reads from the console tty (not currently
available for Icarus Verilog).
- `SoC/`: An interconnect, a boot ROM, a memory controller, a timer
and software-interrupt device, and a UART for console tty I/O.
- `Fabrics/`: Generic AXI4 code for the SoC fabric.
The BSV source code has a rich set of parameters. The provided RTL
source has been generated from the BSV source automatically using
Bluespec's `bsc` compiler, with certain particular sets of choices for
the various parameters. The generated RTL is not parameterized.
To generate Verilog variants with other parameter choices, the user
will need Bluespec's `bsc` compiler. See the next section for
examples of how the build is configured for different ISA features.
`BSV_Additional_Libs` contains a submodule, `BlueStuff`, which must be checked out using:
```sh
$ git submodule update --init --recursive
```
This command may need to be repeated when this parent repository
is updated to point to newer versions of the `BlueStuff` repository.
In fact the CPU also supports a "Tandem Verifier" that produces an
instruction-by-instruction trace that can be checked for correctness
against a RISC-V Golden Reference Model. Please contact Bluespec,
Inc. for more information.
----------------------------------------------------------------
### Building and running from the Verilog sources, out of the box
In the Verilog-build directory:
builds/RV64ACDFIMSU_Toooba_verilator/
- `$ make simulator` will create a Verilog simulation executable using Verilator
- `$ make test` will run the executable on the standard RISC-V ISA
test `rv32ui-p-add` or `rv64ui-p-add`, which is one of the
tests in the `Tests/isa/` directory. Examining the `test:`
target in `Makefile`, we see that it first runs the program
`Tests/elf_to_hex/elf_to_hex` on the `rv32ui-p-add` or
`rv64ui-p-add` ELF file to create a `Mem.hex` file, and then
runs the simulation executable which loads this `Mem.hex` file
into its memory.
- `$ make TEST=<isa_test_name> test` will run the executable on the
standard RISC-V ISA test whose name is supplied.
The full set of standard isa tests are in the `Tests/isa/` directory.
- `$ make isa_tests` will run the executable on
all the standard RISC-V ISA tests relevant for RV64ACDFIMSU (regression testing).
This uses the Python script `Tests/Run_regression.py`.
Please see the documentation at the top of that program for details.
#### Tool dependencies:
We test our builds with the following versions
Verilator. Later versions are probably ok; we have observed some
problems with earlier versions.
$ verilator --version
Verilator 3.922 2018-03-17 rev verilator_3_920-32-gdf3d1a4
----------------------------------------------------------------
### What you can build and run if you have Bluespec's `bsc` compiler
[Note: Bluespec, Inc. provides free licenses to academia and for non-profit research].
Note: even without Bluespec's `bsc` compiler, you can use the Verilog
sources in any of the `builds/<ARCH>_<CPU>_verilator/Verilog_RTL`
directories-- build and run Verilog simulations, incorporate the
Verilog CPU into your own SoC, etc. This section describes additional
things you can do with a `bsc` compiler.
#### Building a Bluesim simulator
In any of the following directories:
builds/<ARCH>_<CPU>_bluesim
- `$ make compile simulator`
will compile and link a Bluesim executable. Then, you can `make test`
or `make isa_tests` as described above to run an individual ISA test
or run regressions on the full suite of relevant ISA tests.
#### Re-generating Verilog RTL
You can regenerate the Verilog RTL in any of the
`build/<ARCH>_<CPU>_verilator/` or `build/<ARCH>_<CPU>_iverilog/`
directories. Example:
$ cd builds/RV32ACIMU_<CPU>_verilator
$ make compile
#### Creating a new architecture configuration
[This documentation needs to be fleshed out.] The `builds/Resources`
directory contains some "include" files for Makefiles, and illustrate
the compile-time flags that determine the micro-architectural
configuration.
In addition, MIT's riscy-ooo code provides further configuration
controls, which can be found in:
Toooba/src_Core/RISCY_OOO/procs/RV64G_OOO/ProcConfig.bsv
----------------------------------------------------------------
================================================
FILE: Tests/Makefile
================================================
### -*-Makefile-*-
# Copyright (c) 2018 Bluespec, Inc. All Rights Reserved
# ================================================================
# Regression: run all ISA tests relevant for the chosen simulator
# ----------------
# Choose a prefix for the simulation executable dir
ARCH ?= RV32IMU
# ARCH ?= RV32ACIMSU
# ARCH ?= RV64IMU
# ARCH ?= RV64ACIMSU
# ----------------
# Choose a simulation engine
SIM ?= Bluesim
# SIM ?= iverilog
# SIM ?= verilator
# ----------------
# Optionally choose an architecture explicitly,
# overriding the simulation executable path
OPTARCH ?=
# ----------------
SIM_DIR = ../builds/$(ARCH)_$(SIM)
# ================================================================
.PHONY: test
test:
@echo "Running regressions; saving logs in Logs/"
./Run_regression.py \
$(SIM_DIR)/exe_HW_sim \
./isa ./Logs $(OPTARCH)
@echo "Finished running regressions; saved logs in Logs/"
# ================================================================
.PHONY: clean
clean:
rm *~
.PHONY: full_clean
full_clean:
rm -r -f *~ Logs *.log
================================================
FILE: Tests/README.txt
================================================
Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved
>================================================================
The './isa' sub-directory contains pre-built ELF and objdump files
(.dump) for all the standard RISC-V ISA tests. For example, the
files:
./isa/rv32ui-p-add
./isa/rv32ui-p-add.dump
are an ELF file and its objdump (disassembly) that tests the RISC-V
user-level integer ADD instruction for RV32. The tests are built when
one clones the following GitHub repository:
https://github.com/riscv/riscv-tools.git
and follows the build directions therein, resulting in all the ISA
tests being built, such as this:
<riscv-tools build dir>/riscv64-unknown-elf/share/riscv-tests/isa/rv32ui-p-add
>================================================================
The Makefile has a command to run regressions on ISA tests.
$ make test
In the Makefile, you will see definitions for ARCH (such as `RV32IMU`)
and SIM (such as `verilator`), which together specify which simulator
will be run (`builds/<ARCH>_SIM/exe_HW_sim`). You can change the ARCH
and SIM definitions in the Makefile for a different simulator, or
redefine them on the `make` command line.
It will run the the Python program 'Run_regression.py', described
below, to run the simulator on all the ISA tests relevant to the
architecture ARCH. A per-ISA-test log is captured in the 'Logs/'
directory.
>================================================================
With the Python program './Run_regression.py' you can run a regression
on all the standard RISC-V ISA tests that are relevant to your RISC-V
simulation executable (i.e., for the RISC-V features and extensions
supported by your simulation executable).
Please do:
$ ./Run_regression.py --help
for usage information.
Example:
$ ./Run_regression.py ../RV32IMU_verilator/exe_HW_sim ./isa ./Logs v1
will run the verilator simulation executable on the all RISC-V ISA
tests that match the following:
./isa/rv32ui-p*
./isa/rv32mi-p*
./isa/rv32um-p*
and leave a transcript of each test's simulation output in files like
./Logs/rv32ui-p-add.log
Each log will contain an instruction trace.
Example:
$ ./Run_regression.py ../RV64AIMSU_verilator/exe_HW_sim ./isa ./Logs v1
will run the verilator simulation executable on the all RISC-V ISA
tests that match the following:
./isa/rv64ui-p*
./isa/rv64um-p*
./isa/rv64ua-p*
./isa/rv64mi-p*
./isa/rv64si-p*
./isa/rv64ui-v*
./isa/rv64um-v*
./isa/rv64ua-v*
>================================================================
================================================
FILE: Tests/Run_regression.py
================================================
#!/usr/bin/python3
# Copyright (c) 2018-2019 Bluespec, Inc.
# See LICENSE for license details
usage_line = (
" Usage:\n"
" $ <this_prog> <simulation_executable> <repo_dir> <logs_dir> <arch> <opt verbosity> <opt parallelism>\n"
"\n"
" Runs the RISC-V <simulation_executable>\n"
" on ISA tests: ELF files taken from <repo-dir>/isa and its sub-directories.\n"
"\n"
" Runs it only on those ELF files that are relevant to architecture <arch>.\n"
"\n"
" For each ELF file FOO, saves simulation output in <logs_dir>/FOO.log. \n"
"\n"
" If <opt verbosity> is given, it must be one of the following:\n"
" v1: Print instruction trace during simulation\n"
" v2: Print pipeline stage state during simulation\n"
"\n"
" If <opt parallelism> is given, it must be an integer\n"
" Specifies the number of parallel processes used\n"
" (creates temporary separate working directories worker_0, worker_1, ...)\n"
" By default uses the number of CPUs listed in /proc/cpuinfo - 4.\n"
" In any case, limits it to 8.\n"
"\n"
" Example:\n"
" $ <this_prog> .exe_HW_sim ~somebody/GitHub/Piccolo ./Logs RV32IMU v1 4\n"
" will run the verilator simulation executable on the following RISC-V ISA tests:\n"
" ~somebody/GitHub/Tests/isa/rv32ui-p*\n"
" ~somebody/GitHub/Tests/isa/rv32mi-p*\n"
" ~somebody/GitHub/Tests/isa/rv32um-p*\n"
" which are relevant for architecture RV32IMU\n"
" and will leave a transcript of each test's simulation output in files like\n"
" ./Logs/rv32ui-p-add.log\n"
" Each log will contain an instruction trace (because of the 'v1' arg).\n"
" It will use 4 processes in parallel to run the regressions.\n"
" (creating temporary working directories worker_0, ..., worker_4)\n"
)
import sys
import os
import stat
import subprocess
import multiprocessing
# ================================================================
# DEBUGGING ONLY: This exclude list allows skipping some specific test
exclude_list = []
n_workers_max = 8
# ================================================================
def main (argv = None):
print ("Use flag --help or --h for a help message")
if ((len (argv) <= 1) or
(argv [1] == '-h') or (argv [1] == '--help') or
(len (argv) < 5)):
sys.stdout.write (usage_line)
sys.stdout.write ("\n")
return 0
# Simulation executable
if not (os.path.exists (argv [1])):
sys.stderr.write ("ERROR: The given simulation path does not seem to exist?\n")
sys.stderr.write (" Simulation path: " + sim_path + "\n")
sys.exit (1)
args_dict = {'sim_path': os.path.abspath (os.path.normpath (argv [1]))}
# Repo in which to find ELFs and elf_to_hex executable
if (not os.path.exists (argv [2])):
sys.stderr.write ("ERROR: repo directory ({0}) does not exist?\n".format (argv [2]))
sys.stdout.write ("\n")
sys.stdout.write (usage_line)
sys.stdout.write ("\n")
return 1
repo = os.path.abspath (os.path.normpath (argv [2]))
elfs_path = os.path.join (repo, "Tests", "isa")
if (not os.path.exists (elfs_path)):
sys.stderr.write ("ERROR: ELFs directory ({0}) does not exist?\n".format (elfs_path))
sys.stdout.write ("\n")
sys.stdout.write (usage_line)
sys.stdout.write ("\n")
return 1
args_dict ['elfs_path'] = elfs_path
# Logs directory
logs_path = os.path.abspath (os.path.normpath (argv [3]))
if not (os.path.exists (logs_path) and os.path.isdir (logs_path)):
print ("Creating dir: " + logs_path)
os.mkdir (logs_path)
args_dict ['logs_path'] = logs_path
# Architecture string and implied ISA test families
arch_string = extract_arch_string (argv [4])
if (arch_string == None):
sys.stderr.write ("ERROR: no architecture specified?\n")
sys.stdout.write ("\n")
sys.stdout.write (usage_line)
sys.stdout.write ("\n")
return 1
args_dict ['arch_string'] = arch_string
test_families = select_test_families (arch_string)
print ("Testing the following families of ISA tests")
for tf in test_families:
print (" " + tf)
args_dict ['test_families'] = test_families
# Optional verbosity
verbosity = 0
j = 5
if len (argv) >= 6:
if argv [5] == "v1":
verbosity = 1
j = 6
elif argv [5] == "v2":
verbosity = 2
j = 6
args_dict ['verbosity'] = verbosity
# Optional parallelism; limit it to 8
if len (argv [j:]) != 0 and isdecimal (argv [j]):
n_workers = int (argv [j])
else:
n_workers = multiprocessing.cpu_count () - 4
n_workers = min (n_workers_max, n_workers)
sys.stdout.write ("Using {0} worker processes\n".format (n_workers))
# End of command-line arg processing
# ================================================================
# elf_to_hex executable
elf_to_hex_exe = os.path.join (repo, "Tests", "elf_to_hex", "elf_to_hex")
if (not os.path.exists (elf_to_hex_exe)):
sys.stderr.write ("ERROR: elf_to_hex executable does not exist?\n")
sys.stderr.write (" at {0}\n".format (elf_to_hex_exe))
sys.stdout.write ("\n")
sys.stdout.write (usage_line)
sys.stdout.write ("\n")
return 1
args_dict ['elf_to_hex_exe'] = elf_to_hex_exe
sys.stdout.write ("Parameters:\n")
for key in iter (args_dict):
sys.stdout.write (" {0:<16}: {1}\n".format (key, args_dict [key]))
def fn_filter_regular_file (level, filename):
(dirname, basename) = os.path.split (filename)
# Ignore filename if has any extension (heuristic that it's not an ELF file)
if "." in basename: return False
# TEMPORARY FILTER WHILE DEBUGGING:
if basename in exclude_list:
sys.stdout.write ("WARNING: TEMPORARY FILTER IN EFFECT; REMOVE AFTER DEBUGGING\n")
sys.stdout.write (" This test is in exclude_list: {0}\n".format (basename))
return False
# Ignore filename if does not match test_families
for x in args_dict ['test_families']:
if basename.find (x) != -1: return True
return False
def fn_filter_dir (level, filename):
return True
# Traverse the elfs_path and collect filenames of relevant isa tests
filenames = traverse (fn_filter_dir, fn_filter_regular_file, 0, elfs_path)
n_tests = len (filenames)
sys.stdout.write ("{0} relevant isa tests found under {1}\n".format (n_tests, elfs_path))
if n_tests == 0:
return 0
args_dict ['filenames'] = filenames
args_dict ['n_tests'] = n_tests
# Create a shared counter to index into the list of filenames
index = multiprocessing.Value ('L', 0) # Unsigned long (4 bytes)
args_dict ['index'] = index
# Create a shared array for each worker's (n_executed, n_passed) results
results = multiprocessing.Array ('L', [ 0 for j in range (2 * n_workers) ])
args_dict ['results'] = results
# Create n workers
sys.stdout.write ("Creating {0} workers (sub-processes)\n".format (n_workers))
workers = [multiprocessing.Process (target = do_worker,
args = (w, args_dict))
for w in range (n_workers)]
# Start the workers
for worker in workers: worker.start ()
# Wait for all workers to finish
for worker in workers: worker.join ()
# Collect all results
num_executed = 0
num_passed = 0
with results.get_lock ():
for w in range (n_workers):
n_e = results [2 * w]
n_p = results [2 * w + 1]
sys.stdout.write ("Worker {0} executed {1} tests, of which {2} passed\n"
.format (w, n_e, n_p))
num_executed = num_executed + n_e
num_passed = num_passed + n_p
# Write final statistics
sys.stdout.write ("Total tests: {0} tests\n".format (n_tests))
sys.stdout.write ("Executed: {0} tests\n".format (num_executed))
sys.stdout.write ("PASS: {0} tests\n".format (num_passed))
sys.stdout.write ("FAIL: {0} tests\n".format (num_executed - num_passed))
return 0
# ================================================================
# Extract the architecture string (e.g., RV64AIMSU) from the string s
def extract_arch_string (s):
s1 = s.upper()
j_rv32 = s1.find ("RV32")
j_rv64 = s1.find ("RV64")
if (j_rv32 >= 0):
j = j_rv32
elif (j_rv64 >= 0):
j = j_rv64
else:
sys.stderr.write ("ERROR: cannot find architecture string beginning with RV32 or RV64 in: \n")
sys.stderr.write (" '" + s + "'\n")
sys.exit (1)
k = j + 4
rv = s1 [j:k]
extns = ""
while (k < len (s)):
ch = s [k]
if (ch < "A") or (ch > "Z"): break
extns = extns + s [k]
k = k + 1
arch = rv + extns
return arch
# ================================================================
# Select ISA test families based on provided arch string
def select_test_families (arch):
arch = arch.lower ()
families = []
if arch.find ("32") != -1:
rv = 32
families = ["rv32ui-p", "rv32mi-p"]
else:
rv = 64
families = ["rv64ui-p", "rv64mi-p"]
if (arch.find ("s") != -1):
s = True
if rv == 32:
families.extend (["rv32ui-v", "rv32si-p"])
else:
families.extend (["rv64ui-v", "rv64si-p"])
else:
s = False
def add_family (extension):
if (arch.find (extension) != -1):
if rv == 32:
families.append ("rv32u" + extension + "-p")
if s:
families.append ("rv32u" + extension + "-v")
else:
families.append ("rv64u" + extension + "-p")
if s:
families.append ("rv64u" + extension + "-v")
add_family ("m")
add_family ("a")
add_family ("f")
add_family ("d")
add_family ("c")
return families
# ================================================================
# Recursively traverse the dir tree below path and collect filenames
# that pass the given filter functions
def traverse (fn_filter_dir, fn_filter_regular_file, level, path):
st = os.stat (path)
is_dir = stat.S_ISDIR (st.st_mode)
is_regular = stat.S_ISREG (st.st_mode)
if is_dir and fn_filter_dir (level, path):
files = []
for entry in os.listdir (path):
path1 = os.path.join (path, entry)
files.extend (traverse (fn_filter_dir, fn_filter_regular_file, level + 1, path1))
return files
elif is_regular and fn_filter_regular_file (level, path):
return [path]
else:
return []
# ================================================================
# For each ELF file, execute it in the RISC-V simulator
def do_worker (worker_num, args_dict):
tmpdir = "./worker_" + "{0}".format (worker_num)
if not os.path.exists (tmpdir):
os.mkdir (tmpdir)
elif not os.path.isdir (tmpdir):
sys.stdout.write ("ERROR: Worker {0}: {1} exists but is not a dir".format (worker_num, tmpdir))
return
os.chdir (tmpdir)
sys.stdout.write ("Worker {0} using dir: {1}\n".format (worker_num, tmpdir))
n_tests = args_dict ['n_tests']
filenames = args_dict ['filenames']
index = args_dict ['index']
results = args_dict ['results']
num_executed = 0
num_passed = 0
while True:
# Get a unique index into the filenames, and get the filename
with index.get_lock():
my_index = index.value
index.value = my_index + 1
if my_index >= n_tests:
# All done
with results.get_lock():
results [2 * worker_num] = num_executed
results [2 * worker_num + 1] = num_passed
return
filename = filenames [my_index]
(message, passed) = do_isa_test (args_dict, filename)
num_executed = num_executed + 1
if passed:
num_passed = num_passed + 1
pass_fail = "PASS"
else:
pass_fail = "FAIL"
message = message + ("Worker {0}: Test: {1} {2} [So far: total {3}, executed {4}, PASS {5}, FAIL {6}]\n"
.format (worker_num,
os.path.basename (filename),
pass_fail,
n_tests,
num_executed,
num_passed,
num_executed - num_passed))
sys.stdout.write (message)
# ================================================================
# For each ELF file, execute it in the RISC-V simulator
def do_isa_test (args_dict, full_filename):
message = ""
(dirname, basename) = os.path.split (full_filename)
# Construct the commands for sub-process execution
command1 = [args_dict ['elf_to_hex_exe'], full_filename, "Mem.hex"]
command2 = [args_dict ['sim_path'], "+tohost"]
if (args_dict ['verbosity'] == 1): command2.append ("+v1")
elif (args_dict ['verbosity'] == 2): command2.append ("+v2")
message = message + " Exec:"
for x in command1:
message = message + (" {0}".format (x))
message = message + "\n"
message = message + (" Exec:")
for x in command2:
message = message + (" {0}".format (x))
message = message + ("\n")
# Run command as a sub-process
completed_process1 = run_command (command1)
completed_process2 = run_command (command2)
passed = completed_process2.stdout.find ("PASS") != -1
# Save stdouts in log file
log_filename = os.path.join (args_dict ['logs_path'], basename + ".log")
message = message + (" Writing log: {0}\n".format (log_filename))
fd = open (log_filename, 'w')
fd.write (completed_process1.stdout)
fd.write (completed_process2.stdout)
fd.close ()
# If Tandem Verification trace file was created, save it as well
if os.path.exists ("./trace_out.dat"):
trace_filename = os.path.join (args_dict ['logs_path'], basename + ".trace_data")
os.rename ("./trace_out.dat", trace_filename)
message = message + (" Trace output saved in: {0}\n".format (trace_filename))
return (message, passed)
# ================================================================
# This is a wrapper around 'subprocess.run' because of an annoying
# incompatible change in moving from Python 3.5 to 3.6
def run_command (command):
python_minor_version = sys.version_info [1]
if python_minor_version < 6:
# Python 3.5 and earlier
result = subprocess.run (args = command,
bufsize = 0,
stdout = subprocess.PIPE,
stderr = subprocess.STDOUT,
universal_newlines = True)
else:
# Python 3.6 and later
result = subprocess.run (args = command,
bufsize = 0,
stdout = subprocess.PIPE,
stderr = subprocess.STDOUT,
encoding='utf-8')
return result
# ================================================================
# For non-interactive invocations, call main() and use its return value
# as the exit code.
if __name__ == '__main__':
sys.exit (main (sys.argv))
================================================
FILE: Tests/isa/rv32mi-p-breakpoint.dump
================================================
rv32mi-p-breakpoint: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 00000f17 auipc t5,0x0
80000024: 1f8f0f13 addi t5,t5,504 # 80000218 <mtvec_handler>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfef>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 80000297 auipc t0,0x80000
800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00002537 lui a0,0x2
800000f0: 80050513 addi a0,a0,-2048 # 1800 <_start-0x7fffe800>
800000f4: 30052073 csrs mstatus,a0
800000f8: 00000297 auipc t0,0x0
800000fc: 01428293 addi t0,t0,20 # 8000010c <reset_vector+0xc0>
80000100: 34129073 csrw mepc,t0
80000104: f1402573 csrr a0,mhartid
80000108: 30200073 mret
8000010c: 00200193 li gp,2
80000110: 7a001073 csrw tselect,zero
80000114: 7a0025f3 csrr a1,tselect
80000118: 0eb01a63 bne zero,a1,8000020c <pass>
8000011c: 00000617 auipc a2,0x0
80000120: 02060613 addi a2,a2,32 # 8000013c <reset_vector+0xf0>
80000124: 7a261073 csrw tdata2,a2
80000128: 20000537 lui a0,0x20000
8000012c: 04450513 addi a0,a0,68 # 20000044 <_start-0x5fffffbc>
80000130: 7a151073 csrw tdata1,a0
80000134: 7a1025f3 csrr a1,tdata1
80000138: 00b51863 bne a0,a1,80000148 <reset_vector+0xfc>
8000013c: 0a000e63 beqz zero,800001f8 <fail>
80000140: 00300193 li gp,3
80000144: 00062503 lw a0,0(a2)
80000148: 00400193 li gp,4
8000014c: 20000537 lui a0,0x20000
80000150: 04150513 addi a0,a0,65 # 20000041 <_start-0x5fffffbf>
80000154: 7a151073 csrw tdata1,a0
80000158: 7a1025f3 csrr a1,tdata1
8000015c: 02b51063 bne a0,a1,8000017c <reset_vector+0x130>
80000160: 00002617 auipc a2,0x2
80000164: ea060613 addi a2,a2,-352 # 80002000 <begin_signature>
80000168: 7a261073 csrw tdata2,a2
8000016c: 00062603 lw a2,0(a2)
80000170: 08060463 beqz a2,800001f8 <fail>
80000174: 00500193 li gp,5
80000178: 00062023 sw zero,0(a2)
8000017c: 00600193 li gp,6
80000180: 20000537 lui a0,0x20000
80000184: 04250513 addi a0,a0,66 # 20000042 <_start-0x5fffffbe>
80000188: 7a151073 csrw tdata1,a0
8000018c: 7a1025f3 csrr a1,tdata1
80000190: 06b51263 bne a0,a1,800001f4 <reset_vector+0x1a8>
80000194: 00c62023 sw a2,0(a2)
80000198: 00700193 li gp,7
8000019c: 00062603 lw a2,0(a2)
800001a0: 04061c63 bnez a2,800001f8 <fail>
800001a4: 00100513 li a0,1
800001a8: 7a051073 csrw tselect,a0
800001ac: 7a0025f3 csrr a1,tselect
800001b0: 04b51e63 bne a0,a1,8000020c <pass>
800001b4: 20000537 lui a0,0x20000
800001b8: 04150513 addi a0,a0,65 # 20000041 <_start-0x5fffffbf>
800001bc: 7a151073 csrw tdata1,a0
800001c0: 00002697 auipc a3,0x2
800001c4: e4468693 addi a3,a3,-444 # 80002004 <data2>
800001c8: 7a269073 csrw tdata2,a3
800001cc: 00800193 li gp,8
800001d0: 0006a683 lw a3,0(a3)
800001d4: 02068263 beqz a3,800001f8 <fail>
800001d8: 00a00193 li gp,10
800001dc: 00002617 auipc a2,0x2
800001e0: e2460613 addi a2,a2,-476 # 80002000 <begin_signature>
800001e4: 00c62023 sw a2,0(a2)
800001e8: 00b00193 li gp,11
800001ec: 00062603 lw a2,0(a2)
800001f0: 00061463 bnez a2,800001f8 <fail>
800001f4: 00301c63 bne zero,gp,8000020c <pass>
800001f8 <fail>:
800001f8: 0ff0000f fence
800001fc: 00018063 beqz gp,800001fc <fail+0x4>
80000200: 00119193 slli gp,gp,0x1
80000204: 0011e193 ori gp,gp,1
80000208: 00000073 ecall
8000020c <pass>:
8000020c: 0ff0000f fence
80000210: 00100193 li gp,1
80000214: 00000073 ecall
80000218 <mtvec_handler>:
80000218: 0011f293 andi t0,gp,1
8000021c: fc029ee3 bnez t0,800001f8 <fail>
80000220: 00300293 li t0,3
80000224: 34202373 csrr t1,mcause
80000228: fc6298e3 bne t0,t1,800001f8 <fail>
8000022c: 341022f3 csrr t0,mepc
80000230: 00428293 addi t0,t0,4
80000234: 34129073 csrw mepc,t0
80000238: 30200073 mret
8000023c: c0001073 unimp
80000240: 0000 unimp
80000242: 0000 unimp
Disassembly of section .data:
80002000 <begin_signature>:
80002000: 0000 unimp
80002002: 0000 unimp
80002004 <data2>:
80002004: 0000 unimp
80002006: 0000 unimp
80002008: 0000 unimp
8000200a: 0000 unimp
8000200c: 0000 unimp
8000200e: 0000 unimp
================================================
FILE: Tests/isa/rv32mi-p-csr.dump
================================================
rv32mi-p-csr: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 00000f17 auipc t5,0x0
80000024: 24cf0f13 addi t5,t5,588 # 8000026c <mtvec_handler>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfef>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 80000297 auipc t0,0x80000
800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00002537 lui a0,0x2
800000f0: 80050513 addi a0,a0,-2048 # 1800 <_start-0x7fffe800>
800000f4: 30052073 csrs mstatus,a0
800000f8: 00000297 auipc t0,0x0
800000fc: 01428293 addi t0,t0,20 # 8000010c <reset_vector+0xc0>
80000100: 34129073 csrw mepc,t0
80000104: f1402573 csrr a0,mhartid
80000108: 30200073 mret
8000010c: 3401d073 csrwi mscratch,3
80000110 <test_2>:
80000110: 34002573 csrr a0,mscratch
80000114: 00300e93 li t4,3
80000118: 00200193 li gp,2
8000011c: 13d51863 bne a0,t4,8000024c <fail>
80000120 <test_3>:
80000120: 3400f5f3 csrrci a1,mscratch,1
80000124: 00300e93 li t4,3
80000128: 00300193 li gp,3
8000012c: 13d59063 bne a1,t4,8000024c <fail>
80000130 <test_4>:
80000130: 34026673 csrrsi a2,mscratch,4
80000134: 00200e93 li t4,2
80000138: 00400193 li gp,4
8000013c: 11d61863 bne a2,t4,8000024c <fail>
80000140 <test_5>:
80000140: 340156f3 csrrwi a3,mscratch,2
80000144: 00600e93 li t4,6
80000148: 00500193 li gp,5
8000014c: 11d69063 bne a3,t4,8000024c <fail>
80000150 <test_6>:
80000150: 0bad2537 lui a0,0xbad2
80000154: dea50513 addi a0,a0,-534 # bad1dea <_start-0x7452e216>
80000158: 340515f3 csrrw a1,mscratch,a0
8000015c: 00200e93 li t4,2
80000160: 00600193 li gp,6
80000164: 0fd59463 bne a1,t4,8000024c <fail>
80000168 <test_7>:
80000168: 00002537 lui a0,0x2
8000016c: dea50513 addi a0,a0,-534 # 1dea <_start-0x7fffe216>
80000170: 34053573 csrrc a0,mscratch,a0
80000174: 0bad2eb7 lui t4,0xbad2
80000178: deae8e93 addi t4,t4,-534 # bad1dea <_start-0x7452e216>
8000017c: 00700193 li gp,7
80000180: 0dd51663 bne a0,t4,8000024c <fail>
80000184 <test_8>:
80000184: 0000c537 lui a0,0xc
80000188: eef50513 addi a0,a0,-273 # beef <_start-0x7fff4111>
8000018c: 34052573 csrrs a0,mscratch,a0
80000190: 0bad0eb7 lui t4,0xbad0
80000194: 00800193 li gp,8
80000198: 0bd51a63 bne a0,t4,8000024c <fail>
8000019c <test_9>:
8000019c: 34002573 csrr a0,mscratch
800001a0: 0badceb7 lui t4,0xbadc
800001a4: eefe8e93 addi t4,t4,-273 # badbeef <_start-0x74524111>
800001a8: 00900193 li gp,9
800001ac: 0bd51063 bne a0,t4,8000024c <fail>
800001b0: 30102573 csrr a0,misa
800001b4: 02057513 andi a0,a0,32
800001b8: 02050863 beqz a0,800001e8 <test_10+0x14>
800001bc: 000065b7 lui a1,0x6
800001c0: 3005a073 csrs mstatus,a1
800001c4: f0000053 fmv.w.x ft0,zero
800001c8: 3005b073 csrc mstatus,a1
800001cc: 00002597 auipc a1,0x2
800001d0: e3458593 addi a1,a1,-460 # 80002000 <begin_signature>
800001d4 <test_10>:
800001d4: 0005a027 fsw ft0,0(a1)
800001d8: 0005a503 lw a0,0(a1)
800001dc: 00100e93 li t4,1
800001e0: 00a00193 li gp,10
800001e4: 07d51463 bne a0,t4,8000024c <fail>
800001e8: 30102573 csrr a0,misa
800001ec: 01455513 srli a0,a0,0x14
800001f0: 00157513 andi a0,a0,1
800001f4: 04050463 beqz a0,8000023c <finish>
800001f8: 000022b7 lui t0,0x2
800001fc: 80028293 addi t0,t0,-2048 # 1800 <_start-0x7fffe800>
80000200: 3002b073 csrc mstatus,t0
80000204: 00000297 auipc t0,0x0
80000208: 01028293 addi t0,t0,16 # 80000214 <test_11>
8000020c: 34129073 csrw mepc,t0
80000210: 30200073 mret
80000214 <test_11>:
80000214: 0ff00513 li a0,255
80000218: c0001573 csrrw a0,cycle,zero
8000021c: 0ff00e93 li t4,255
80000220: 00b00193 li gp,11
80000224: 03d51463 bne a0,t4,8000024c <fail>
80000228 <test_12>:
80000228: 0ff00513 li a0,255
8000022c: 30002573 csrr a0,mstatus
80000230: 0ff00e93 li t4,255
80000234: 00c00193 li gp,12
80000238: 01d51a63 bne a0,t4,8000024c <fail>
8000023c <finish>:
8000023c: 0ff0000f fence
80000240: 00100193 li gp,1
80000244: 00000073 ecall
80000248: 00301c63 bne zero,gp,80000260 <pass>
8000024c <fail>:
8000024c: 0ff0000f fence
80000250: 00018063 beqz gp,80000250 <fail+0x4>
80000254: 00119193 slli gp,gp,0x1
80000258: 0011e193 ori gp,gp,1
8000025c: 00000073 ecall
80000260 <pass>:
80000260: 0ff0000f fence
80000264: 00100193 li gp,1
80000268: 00000073 ecall
8000026c <mtvec_handler>:
8000026c: 00900293 li t0,9
80000270: 0051e663 bltu gp,t0,8000027c <mtvec_handler+0x10>
80000274: 00b00293 li t0,11
80000278: 0032fe63 bgeu t0,gp,80000294 <privileged>
8000027c: 342022f3 csrr t0,mcause
80000280: 00800313 li t1,8
80000284: fc6294e3 bne t0,t1,8000024c <fail>
80000288: 0ff0000f fence
8000028c: 00100193 li gp,1
80000290: 00000073 ecall
80000294 <privileged>:
80000294: 342022f3 csrr t0,mcause
80000298: 00200313 li t1,2
8000029c: fa6298e3 bne t0,t1,8000024c <fail>
800002a0: 341022f3 csrr t0,mepc
800002a4: 00428293 addi t0,t0,4
800002a8: 34129073 csrw mepc,t0
800002ac: 30200073 mret
800002b0: c0001073 unimp
800002b4: 0000 unimp
800002b6: 0000 unimp
800002b8: 0000 unimp
800002ba: 0000 unimp
800002bc: 0000 unimp
800002be: 0000 unimp
800002c0: 0000 unimp
800002c2: 0000 unimp
Disassembly of section .data:
80002000 <begin_signature>:
80002000: 0001 nop
80002002: 0000 unimp
80002004: 0000 unimp
80002006: 0000 unimp
80002008: 0000 unimp
8000200a: 0000 unimp
8000200c: 0000 unimp
8000200e: 0000 unimp
================================================
FILE: Tests/isa/rv32mi-p-illegal.dump
================================================
rv32mi-p-illegal: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 00000f17 auipc t5,0x0
80000024: 2e0f0f13 addi t5,t5,736 # 80000300 <mtvec_handler>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 80000297 auipc t0,0x80000
800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00002537 lui a0,0x2
800000f0: 80050513 addi a0,a0,-2048 # 1800 <_start-0x7fffe800>
800000f4: 30052073 csrs mstatus,a0
800000f8: 00000297 auipc t0,0x0
800000fc: 01428293 addi t0,t0,20 # 8000010c <reset_vector+0xc0>
80000100: 34129073 csrw mepc,t0
80000104: f1402573 csrr a0,mhartid
80000108: 30200073 mret
8000010c: 00200193 li gp,2
80000110 <bad2>:
80000110: 0000 unimp
80000112: 0000 unimp
80000114: 0f40006f j 80000208 <fail>
80000118: 000022b7 lui t0,0x2
8000011c: 80028293 addi t0,t0,-2048 # 1800 <_start-0x7fffe800>
80000120: 3002b073 csrc mstatus,t0
80000124: 00001337 lui t1,0x1
80000128: 80030313 addi t1,t1,-2048 # 800 <_start-0x7ffff800>
8000012c: 30032073 csrs mstatus,t1
80000130: 300023f3 csrr t2,mstatus
80000134: 0053f3b3 and t2,t2,t0
80000138: 0e731263 bne t1,t2,8000021c <pass>
8000013c <test_vectored_interrupts>:
8000013c: 34415073 csrwi mip,2
80000140: 30415073 csrwi mie,2
80000144: 00000297 auipc t0,0x0
80000148: 1bd28293 addi t0,t0,445 # 80000301 <mtvec_handler+0x1>
8000014c: 30529473 csrrw s0,mtvec,t0
80000150: 305022f3 csrr t0,mtvec
80000154: 0012f293 andi t0,t0,1
80000158: 00028663 beqz t0,80000164 <msip>
8000015c: 30046073 csrsi mstatus,8
80000160: 0000006f j 80000160 <test_vectored_interrupts+0x24>
80000164 <msip>:
80000164: 30541073 csrw mtvec,s0
80000168: 30315073 csrwi mideleg,2
8000016c: 00000297 auipc t0,0x0
80000170: 02828293 addi t0,t0,40 # 80000194 <msip+0x30>
80000174: 34129073 csrw mepc,t0
80000178: 000022b7 lui t0,0x2
8000017c: 80028293 addi t0,t0,-2048 # 1800 <_start-0x7fffe800>
80000180: 3002b073 csrc mstatus,t0
80000184: 00001337 lui t1,0x1
80000188: 80030313 addi t1,t1,-2048 # 800 <_start-0x7ffff800>
8000018c: 30032073 csrs mstatus,t1
80000190: 30200073 mret
80000194: 10500073 wfi
80000198 <bad3>:
80000198: 0000 unimp
8000019a: 0000 unimp
8000019c: 06c0006f j 80000208 <fail>
800001a0 <bad4>:
800001a0: 10500073 wfi
800001a4: 0640006f j 80000208 <fail>
800001a8: 12000073 sfence.vma
800001ac: 180022f3 csrr t0,satp
800001b0 <bad5>:
800001b0: 0000 unimp
800001b2: 0000 unimp
800001b4: 0540006f j 80000208 <fail>
800001b8 <bad6>:
800001b8: 12000073 sfence.vma
800001bc: 04c0006f j 80000208 <fail>
800001c0 <bad7>:
800001c0: 180022f3 csrr t0,satp
800001c4: 0440006f j 80000208 <fail>
800001c8: 00000297 auipc t0,0x0
800001cc: 02028293 addi t0,t0,32 # 800001e8 <bad8>
800001d0: 14129073 csrw sepc,t0
800001d4: 10000293 li t0,256
800001d8: 1002a073 csrs sstatus,t0
800001dc: 02000293 li t0,32
800001e0: 1002b073 csrc sstatus,t0
800001e4: 10200073 sret
800001e8 <bad8>:
800001e8: 0000 unimp
800001ea: 0000 unimp
800001ec: 01c0006f j 80000208 <fail>
800001f0: 00000297 auipc t0,0x0
800001f4: 01028293 addi t0,t0,16 # 80000200 <bad9+0x4>
800001f8: 14129073 csrw sepc,t0
800001fc <bad9>:
800001fc: 10200073 sret
80000200: 0080006f j 80000208 <fail>
80000204: 00301c63 bne zero,gp,8000021c <pass>
80000208 <fail>:
80000208: 0ff0000f fence
8000020c: 00018063 beqz gp,8000020c <fail+0x4>
80000210: 00119193 slli gp,gp,0x1
80000214: 0011e193 ori gp,gp,1
80000218: 00000073 ecall
8000021c <pass>:
8000021c: 0ff0000f fence
80000220: 00100193 li gp,1
80000224: 00000073 ecall
80000228: 00000013 nop
8000022c: 00000013 nop
80000230: 00000013 nop
80000234: 00000013 nop
80000238: 00000013 nop
8000023c: 00000013 nop
80000240: 00000013 nop
80000244: 00000013 nop
80000248: 00000013 nop
8000024c: 00000013 nop
80000250: 00000013 nop
80000254: 00000013 nop
80000258: 00000013 nop
8000025c: 00000013 nop
80000260: 00000013 nop
80000264: 00000013 nop
80000268: 00000013 nop
8000026c: 00000013 nop
80000270: 00000013 nop
80000274: 00000013 nop
80000278: 00000013 nop
8000027c: 00000013 nop
80000280: 00000013 nop
80000284: 00000013 nop
80000288: 00000013 nop
8000028c: 00000013 nop
80000290: 00000013 nop
80000294: 00000013 nop
80000298: 00000013 nop
8000029c: 00000013 nop
800002a0: 00000013 nop
800002a4: 00000013 nop
800002a8: 00000013 nop
800002ac: 00000013 nop
800002b0: 00000013 nop
800002b4: 00000013 nop
800002b8: 00000013 nop
800002bc: 00000013 nop
800002c0: 00000013 nop
800002c4: 00000013 nop
800002c8: 00000013 nop
800002cc: 00000013 nop
800002d0: 00000013 nop
800002d4: 00000013 nop
800002d8: 00000013 nop
800002dc: 00000013 nop
800002e0: 00000013 nop
800002e4: 00000013 nop
800002e8: 00000013 nop
800002ec: 00000013 nop
800002f0: 00000013 nop
800002f4: 00000013 nop
800002f8: 00000013 nop
800002fc: 00000013 nop
80000300 <mtvec_handler>:
80000300: 0400006f j 80000340 <synchronous_exception>
80000304: e61ff06f j 80000164 <msip>
80000308: f01ff06f j 80000208 <fail>
8000030c: efdff06f j 80000208 <fail>
80000310: ef9ff06f j 80000208 <fail>
80000314: ef5ff06f j 80000208 <fail>
80000318: ef1ff06f j 80000208 <fail>
8000031c: eedff06f j 80000208 <fail>
80000320: ee9ff06f j 80000208 <fail>
80000324: ee5ff06f j 80000208 <fail>
80000328: ee1ff06f j 80000208 <fail>
8000032c: eddff06f j 80000208 <fail>
80000330: ed9ff06f j 80000208 <fail>
80000334: ed5ff06f j 80000208 <fail>
80000338: ed1ff06f j 80000208 <fail>
8000033c: ecdff06f j 80000208 <fail>
80000340 <synchronous_exception>:
80000340: 00200313 li t1,2
80000344: 342022f3 csrr t0,mcause
80000348: ec6290e3 bne t0,t1,80000208 <fail>
8000034c: 341022f3 csrr t0,mepc
80000350: 343023f3 csrr t2,mtval
80000354: 00038e63 beqz t2,80000370 <synchronous_exception+0x30>
80000358: 0002d303 lhu t1,0(t0)
8000035c: 0063c3b3 xor t2,t2,t1
80000360: 0022d303 lhu t1,2(t0)
80000364: 01031313 slli t1,t1,0x10
80000368: 0063c3b3 xor t2,t2,t1
8000036c: e8039ee3 bnez t2,80000208 <fail>
80000370: 00000317 auipc t1,0x0
80000374: da030313 addi t1,t1,-608 # 80000110 <bad2>
80000378: 04628e63 beq t0,t1,800003d4 <synchronous_exception+0x94>
8000037c: 00000317 auipc t1,0x0
80000380: e1c30313 addi t1,t1,-484 # 80000198 <bad3>
80000384: 04628e63 beq t0,t1,800003e0 <synchronous_exception+0xa0>
80000388: 00000317 auipc t1,0x0
8000038c: e1830313 addi t1,t1,-488 # 800001a0 <bad4>
80000390: 04628263 beq t0,t1,800003d4 <synchronous_exception+0x94>
80000394: 00000317 auipc t1,0x0
80000398: e1c30313 addi t1,t1,-484 # 800001b0 <bad5>
8000039c: 04628863 beq t0,t1,800003ec <synchronous_exception+0xac>
800003a0: 00000317 auipc t1,0x0
800003a4: e1830313 addi t1,t1,-488 # 800001b8 <bad6>
800003a8: 02628663 beq t0,t1,800003d4 <synchronous_exception+0x94>
800003ac: 00000317 auipc t1,0x0
800003b0: e1430313 addi t1,t1,-492 # 800001c0 <bad7>
800003b4: 02628063 beq t0,t1,800003d4 <synchronous_exception+0x94>
800003b8: 00000317 auipc t1,0x0
800003bc: e3030313 addi t1,t1,-464 # 800001e8 <bad8>
800003c0: 02628c63 beq t0,t1,800003f8 <synchronous_exception+0xb8>
800003c4: 00000317 auipc t1,0x0
800003c8: e3830313 addi t1,t1,-456 # 800001fc <bad9>
800003cc: 02628c63 beq t0,t1,80000404 <synchronous_exception+0xc4>
800003d0: e39ff06f j 80000208 <fail>
800003d4: 00828293 addi t0,t0,8
800003d8: 34129073 csrw mepc,t0
800003dc: 30200073 mret
800003e0: 00200337 lui t1,0x200
800003e4: 30032073 csrs mstatus,t1
800003e8: fedff06f j 800003d4 <synchronous_exception+0x94>
800003ec: 00100337 lui t1,0x100
800003f0: 30032073 csrs mstatus,t1
800003f4: fe1ff06f j 800003d4 <synchronous_exception+0x94>
800003f8: 00400337 lui t1,0x400
800003fc: 30032073 csrs mstatus,t1
80000400: fd5ff06f j 800003d4 <synchronous_exception+0x94>
80000404: fd1ff06f j 800003d4 <synchronous_exception+0x94>
80000408: c0001073 unimp
8000040c: 0000 unimp
8000040e: 0000 unimp
80000410: 0000 unimp
80000412: 0000 unimp
80000414: 0000 unimp
80000416: 0000 unimp
80000418: 0000 unimp
8000041a: 0000 unimp
8000041c: 0000 unimp
8000041e: 0000 unimp
80000420: 0000 unimp
80000422: 0000 unimp
80000424: 0000 unimp
80000426: 0000 unimp
80000428: 0000 unimp
8000042a: 0000 unimp
8000042c: 0000 unimp
8000042e: 0000 unimp
80000430: 0000 unimp
80000432: 0000 unimp
80000434: 0000 unimp
80000436: 0000 unimp
80000438: 0000 unimp
8000043a: 0000 unimp
8000043c: 0000 unimp
8000043e: 0000 unimp
80000440: 0000 unimp
80000442: 0000 unimp
80000444: 0000 unimp
80000446: 0000 unimp
80000448: 0000 unimp
8000044a: 0000 unimp
8000044c: 0000 unimp
8000044e: 0000 unimp
80000450: 0000 unimp
80000452: 0000 unimp
80000454: 0000 unimp
80000456: 0000 unimp
80000458: 0000 unimp
8000045a: 0000 unimp
8000045c: 0000 unimp
8000045e: 0000 unimp
80000460: 0000 unimp
80000462: 0000 unimp
80000464: 0000 unimp
80000466: 0000 unimp
80000468: 0000 unimp
8000046a: 0000 unimp
8000046c: 0000 unimp
8000046e: 0000 unimp
80000470: 0000 unimp
80000472: 0000 unimp
80000474: 0000 unimp
80000476: 0000 unimp
80000478: 0000 unimp
8000047a: 0000 unimp
8000047c: 0000 unimp
8000047e: 0000 unimp
80000480: 0000 unimp
80000482: 0000 unimp
80000484: 0000 unimp
80000486: 0000 unimp
80000488: 0000 unimp
8000048a: 0000 unimp
8000048c: 0000 unimp
8000048e: 0000 unimp
80000490: 0000 unimp
80000492: 0000 unimp
80000494: 0000 unimp
80000496: 0000 unimp
80000498: 0000 unimp
8000049a: 0000 unimp
8000049c: 0000 unimp
8000049e: 0000 unimp
================================================
FILE: Tests/isa/rv32mi-p-ma_addr.dump
================================================
rv32mi-p-ma_addr: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 00000f17 auipc t5,0x0
80000024: 290f0f13 addi t5,t5,656 # 800002b0 <mtvec_handler>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdeef>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 80000297 auipc t0,0x80000
800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00002537 lui a0,0x2
800000f0: 80050513 addi a0,a0,-2048 # 1800 <_start-0x7fffe800>
800000f4: 30052073 csrs mstatus,a0
800000f8: 00000297 auipc t0,0x0
800000fc: 01428293 addi t0,t0,20 # 8000010c <reset_vector+0xc0>
80000100: 34129073 csrw mepc,t0
80000104: f1402573 csrr a0,mhartid
80000108: 30200073 mret
8000010c: 00002417 auipc s0,0x2
80000110: ef440413 addi s0,s0,-268 # 80002000 <begin_signature>
80000114: 00400493 li s1,4
80000118: 00200193 li gp,2
8000011c: 00000397 auipc t2,0x0
80000120: 01c38393 addi t2,t2,28 # 80000138 <reset_vector+0xec>
80000124: 00140313 addi t1,s0,1
80000128: 00141303 lh t1,1(s0)
8000012c: ffffc3b7 lui t2,0xffffc
80000130: bcc38393 addi t2,t2,-1076 # ffffbbcc <_end+0x7fff9abc>
80000134: 14731e63 bne t1,t2,80000290 <fail>
80000138: 00300193 li gp,3
8000013c: 00000397 auipc t2,0x0
80000140: 01c38393 addi t2,t2,28 # 80000158 <reset_vector+0x10c>
80000144: 00140313 addi t1,s0,1
80000148: 00145303 lhu t1,1(s0)
8000014c: 0000c3b7 lui t2,0xc
80000150: bcc38393 addi t2,t2,-1076 # bbcc <_start-0x7fff4434>
80000154: 12731e63 bne t1,t2,80000290 <fail>
80000158: 00400193 li gp,4
8000015c: 00000397 auipc t2,0x0
80000160: 01c38393 addi t2,t2,28 # 80000178 <reset_vector+0x12c>
80000164: 00140313 addi t1,s0,1
80000168: 00142303 lw t1,1(s0)
8000016c: 99aac3b7 lui t2,0x99aac
80000170: bcc38393 addi t2,t2,-1076 # 99aabbcc <_end+0x19aa9abc>
80000174: 10731e63 bne t1,t2,80000290 <fail>
80000178: 00500193 li gp,5
8000017c: 00000397 auipc t2,0x0
80000180: 01c38393 addi t2,t2,28 # 80000198 <reset_vector+0x14c>
80000184: 00240313 addi t1,s0,2
80000188: 00242303 lw t1,2(s0)
8000018c: 8899b3b7 lui t2,0x8899b
80000190: abb38393 addi t2,t2,-1349 # 8899aabb <_end+0x89989ab>
80000194: 0e731e63 bne t1,t2,80000290 <fail>
80000198: 00600193 li gp,6
8000019c: 00000397 auipc t2,0x0
800001a0: 01c38393 addi t2,t2,28 # 800001b8 <reset_vector+0x16c>
800001a4: 00340313 addi t1,s0,3
800001a8: 00342303 lw t1,3(s0)
800001ac: 7788a3b7 lui t2,0x7788a
800001b0: 9aa38393 addi t2,t2,-1622 # 778899aa <_start-0x8776656>
800001b4: 0c731e63 bne t1,t2,80000290 <fail>
800001b8: 00600493 li s1,6
800001bc: 01600193 li gp,22
800001c0: 00000397 auipc t2,0x0
800001c4: 03038393 addi t2,t2,48 # 800001f0 <reset_vector+0x1a4>
800001c8: 00140313 addi t1,s0,1
800001cc: 000410a3 sh zero,1(s0)
800001d0: 00040303 lb t1,0(s0)
800001d4: 0a030e63 beqz t1,80000290 <fail>
800001d8: 00340303 lb t1,3(s0)
800001dc: 0a030a63 beqz t1,80000290 <fail>
800001e0: 00140303 lb t1,1(s0)
800001e4: 0a031663 bnez t1,80000290 <fail>
800001e8: 00240303 lb t1,2(s0)
800001ec: 0a031263 bnez t1,80000290 <fail>
800001f0: 01700193 li gp,23
800001f4: 00000397 auipc t2,0x0
800001f8: 03038393 addi t2,t2,48 # 80000224 <reset_vector+0x1d8>
800001fc: 00540313 addi t1,s0,5
80000200: 000422a3 sw zero,5(s0)
80000204: 00440303 lb t1,4(s0)
80000208: 08030463 beqz t1,80000290 <fail>
8000020c: 00940303 lb t1,9(s0)
80000210: 08030063 beqz t1,80000290 <fail>
80000214: 00540303 lb t1,5(s0)
80000218: 06031c63 bnez t1,80000290 <fail>
8000021c: 00840303 lb t1,8(s0)
80000220: 06031863 bnez t1,80000290 <fail>
80000224: 01800193 li gp,24
80000228: 00000397 auipc t2,0x0
8000022c: 03038393 addi t2,t2,48 # 80000258 <reset_vector+0x20c>
80000230: 00a40313 addi t1,s0,10
80000234: 00042523 sw zero,10(s0)
80000238: 00940303 lb t1,9(s0)
8000023c: 04030a63 beqz t1,80000290 <fail>
80000240: 00e40303 lb t1,14(s0)
80000244: 04030663 beqz t1,80000290 <fail>
80000248: 00a40303 lb t1,10(s0)
8000024c: 04031263 bnez t1,80000290 <fail>
80000250: 00d40303 lb t1,13(s0)
80000254: 02031e63 bnez t1,80000290 <fail>
80000258: 01900193 li gp,25
8000025c: 00000397 auipc t2,0x0
80000260: 03038393 addi t2,t2,48 # 8000028c <reset_vector+0x240>
80000264: 00f40313 addi t1,s0,15
80000268: 000427a3 sw zero,15(s0)
8000026c: 00e40303 lb t1,14(s0)
80000270: 02030063 beqz t1,80000290 <fail>
80000274: 01340303 lb t1,19(s0)
80000278: 00030c63 beqz t1,80000290 <fail>
8000027c: 00f40303 lb t1,15(s0)
80000280: 00031863 bnez t1,80000290 <fail>
80000284: 01240303 lb t1,18(s0)
80000288: 00031463 bnez t1,80000290 <fail>
8000028c: 00301c63 bne zero,gp,800002a4 <pass>
80000290 <fail>:
80000290: 0ff0000f fence
80000294: 00018063 beqz gp,80000294 <fail+0x4>
80000298: 00119193 slli gp,gp,0x1
8000029c: 0011e193 ori gp,gp,1
800002a0: 00000073 ecall
800002a4 <pass>:
800002a4: 0ff0000f fence
800002a8: 00100193 li gp,1
800002ac: 00000073 ecall
800002b0 <mtvec_handler>:
800002b0: 342022f3 csrr t0,mcause
800002b4: fc929ee3 bne t0,s1,80000290 <fail>
800002b8: 343022f3 csrr t0,mtval
800002bc: fc629ae3 bne t0,t1,80000290 <fail>
800002c0: 00028283 lb t0,0(t0)
800002c4: fc0286e3 beqz t0,80000290 <fail>
800002c8: 34139073 csrw mepc,t2
800002cc: 30200073 mret
800002d0: c0001073 unimp
800002d4: 0000 unimp
800002d6: 0000 unimp
800002d8: 0000 unimp
800002da: 0000 unimp
800002dc: 0000 unimp
800002de: 0000 unimp
800002e0: 0000 unimp
800002e2: 0000 unimp
800002e4: 0000 unimp
800002e6: 0000 unimp
800002e8: 0000 unimp
800002ea: 0000 unimp
800002ec: 0000 unimp
800002ee: 0000 unimp
800002f0: 0000 unimp
800002f2: 0000 unimp
800002f4: 0000 unimp
800002f6: 0000 unimp
800002f8: 0000 unimp
800002fa: 0000 unimp
800002fc: 0000 unimp
800002fe: 0000 unimp
Disassembly of section .data:
80002000 <begin_signature>:
80002000: ccdd beqz s1,800020be <begin_signature+0xbe>
80002002: 8899aabb 0x8899aabb
80002006: 44556677 0x44556677
8000200a: ee112233 0xee112233
8000200e: eeff 0xeeff
80002010: 5050 lw a2,36(s0)
80002012: 5050 lw a2,36(s0)
80002014: 5050 lw a2,36(s0)
80002016: 5050 lw a2,36(s0)
80002018: 5050 lw a2,36(s0)
8000201a: 5050 lw a2,36(s0)
8000201c: 5050 lw a2,36(s0)
8000201e: 5050 lw a2,36(s0)
80002020: 5050 lw a2,36(s0)
80002022: 5050 lw a2,36(s0)
80002024: 5050 lw a2,36(s0)
80002026: 5050 lw a2,36(s0)
80002028: 5050 lw a2,36(s0)
8000202a: 5050 lw a2,36(s0)
8000202c: 5050 lw a2,36(s0)
8000202e: 5050 lw a2,36(s0)
80002030: 5050 lw a2,36(s0)
80002032: 5050 lw a2,36(s0)
80002034: 5050 lw a2,36(s0)
80002036: 5050 lw a2,36(s0)
80002038: 5050 lw a2,36(s0)
8000203a: 5050 lw a2,36(s0)
8000203c: 5050 lw a2,36(s0)
8000203e: 5050 lw a2,36(s0)
80002040: 5050 lw a2,36(s0)
80002042: 5050 lw a2,36(s0)
80002044: 5050 lw a2,36(s0)
80002046: 5050 lw a2,36(s0)
80002048: 5050 lw a2,36(s0)
8000204a: 5050 lw a2,36(s0)
8000204c: 5050 lw a2,36(s0)
8000204e: 5050 lw a2,36(s0)
80002050: 5050 lw a2,36(s0)
80002052: 5050 lw a2,36(s0)
80002054: 5050 lw a2,36(s0)
80002056: 5050 lw a2,36(s0)
80002058: 5050 lw a2,36(s0)
8000205a: 5050 lw a2,36(s0)
8000205c: 5050 lw a2,36(s0)
8000205e: 5050 lw a2,36(s0)
80002060: 5050 lw a2,36(s0)
80002062: 5050 lw a2,36(s0)
80002064: 5050 lw a2,36(s0)
80002066: 5050 lw a2,36(s0)
80002068: 5050 lw a2,36(s0)
8000206a: 5050 lw a2,36(s0)
8000206c: 5050 lw a2,36(s0)
8000206e: 5050 lw a2,36(s0)
80002070: 5050 lw a2,36(s0)
80002072: 5050 lw a2,36(s0)
80002074: 5050 lw a2,36(s0)
80002076: 5050 lw a2,36(s0)
80002078: 5050 lw a2,36(s0)
8000207a: 5050 lw a2,36(s0)
8000207c: 5050 lw a2,36(s0)
8000207e: 5050 lw a2,36(s0)
80002080: 5050 lw a2,36(s0)
80002082: 5050 lw a2,36(s0)
80002084: 5050 lw a2,36(s0)
80002086: 5050 lw a2,36(s0)
80002088: 5050 lw a2,36(s0)
8000208a: 5050 lw a2,36(s0)
8000208c: 5050 lw a2,36(s0)
8000208e: 5050 lw a2,36(s0)
80002090: 5050 lw a2,36(s0)
80002092: 5050 lw a2,36(s0)
80002094: 5050 lw a2,36(s0)
80002096: 5050 lw a2,36(s0)
80002098: 5050 lw a2,36(s0)
8000209a: 5050 lw a2,36(s0)
8000209c: 5050 lw a2,36(s0)
8000209e: 5050 lw a2,36(s0)
800020a0: 5050 lw a2,36(s0)
800020a2: 5050 lw a2,36(s0)
800020a4: 5050 lw a2,36(s0)
800020a6: 5050 lw a2,36(s0)
800020a8: 5050 lw a2,36(s0)
800020aa: 5050 lw a2,36(s0)
800020ac: 5050 lw a2,36(s0)
800020ae: 5050 lw a2,36(s0)
800020b0: 5050 lw a2,36(s0)
800020b2: 5050 lw a2,36(s0)
800020b4: 5050 lw a2,36(s0)
800020b6: 5050 lw a2,36(s0)
800020b8: 5050 lw a2,36(s0)
800020ba: 5050 lw a2,36(s0)
800020bc: 5050 lw a2,36(s0)
800020be: 5050 lw a2,36(s0)
800020c0: 5050 lw a2,36(s0)
800020c2: 5050 lw a2,36(s0)
800020c4: 5050 lw a2,36(s0)
800020c6: 5050 lw a2,36(s0)
800020c8: 5050 lw a2,36(s0)
800020ca: 5050 lw a2,36(s0)
800020cc: 5050 lw a2,36(s0)
800020ce: 5050 lw a2,36(s0)
800020d0: 5050 lw a2,36(s0)
800020d2: 5050 lw a2,36(s0)
800020d4: 5050 lw a2,36(s0)
800020d6: 5050 lw a2,36(s0)
800020d8: 5050 lw a2,36(s0)
800020da: 5050 lw a2,36(s0)
800020dc: 5050 lw a2,36(s0)
800020de: 5050 lw a2,36(s0)
800020e0: 5050 lw a2,36(s0)
800020e2: 5050 lw a2,36(s0)
800020e4: 5050 lw a2,36(s0)
800020e6: 5050 lw a2,36(s0)
800020e8: 5050 lw a2,36(s0)
800020ea: 5050 lw a2,36(s0)
800020ec: 5050 lw a2,36(s0)
800020ee: 5050 lw a2,36(s0)
800020f0: 5050 lw a2,36(s0)
800020f2: 5050 lw a2,36(s0)
800020f4: 5050 lw a2,36(s0)
800020f6: 5050 lw a2,36(s0)
800020f8: 5050 lw a2,36(s0)
800020fa: 5050 lw a2,36(s0)
800020fc: 5050 lw a2,36(s0)
800020fe: 5050 lw a2,36(s0)
80002100: 5050 lw a2,36(s0)
80002102: 5050 lw a2,36(s0)
80002104: 5050 lw a2,36(s0)
80002106: 5050 lw a2,36(s0)
80002108: 5050 lw a2,36(s0)
8000210a: 5050 lw a2,36(s0)
8000210c: 5050 lw a2,36(s0)
8000210e: 0050 addi a2,sp,4
================================================
FILE: Tests/isa/rv32mi-p-ma_fetch.dump
================================================
rv32mi-p-ma_fetch: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 00000f17 auipc t5,0x0
80000024: 20cf0f13 addi t5,t5,524 # 8000022c <mtvec_handler>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 80000297 auipc t0,0x80000
800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00002537 lui a0,0x2
800000f0: 80050513 addi a0,a0,-2048 # 1800 <_start-0x7fffe800>
800000f4: 30052073 csrs mstatus,a0
800000f8: 00000297 auipc t0,0x0
800000fc: 01428293 addi t0,t0,20 # 8000010c <reset_vector+0xc0>
80000100: 34129073 csrw mepc,t0
80000104: f1402573 csrr a0,mhartid
80000108: 30200073 mret
8000010c: 00200193 li gp,2
80000110: 00000313 li t1,0
80000114: 00000297 auipc t0,0x0
80000118: 00c28293 addi t0,t0,12 # 80000120 <reset_vector+0xd4>
8000011c: 00228367 jalr t1,2(t0)
80000120: a011 j 80000124 <reset_vector+0xd8>
80000122: a019 j 80000128 <reset_vector+0xdc>
80000124: 0e80006f j 8000020c <fail>
80000128: 00300193 li gp,3
8000012c: 00000297 auipc t0,0x0
80000130: 00c28293 addi t0,t0,12 # 80000138 <reset_vector+0xec>
80000134: 00128367 jalr t1,1(t0)
80000138: 0080006f j 80000140 <reset_vector+0xf4>
8000013c: 0d00006f j 8000020c <fail>
80000140: 00400193 li gp,4
80000144: 00000313 li t1,0
80000148: 00000297 auipc t0,0x0
8000014c: 00c28293 addi t0,t0,12 # 80000154 <reset_vector+0x108>
80000150: 00328367 jalr t1,3(t0)
80000154: a011 j 80000158 <reset_vector+0x10c>
80000156: a019 j 8000015c <reset_vector+0x110>
80000158: 0b40006f j 8000020c <fail>
8000015c: 00500193 li gp,5
80000160: 00000313 li t1,0
80000164: 00000297 auipc t0,0x0
80000168: 00c28293 addi t0,t0,12 # 80000170 <reset_vector+0x124>
8000016c: 0060036f jal t1,80000172 <reset_vector+0x126>
80000170: a011 j 80000174 <reset_vector+0x128>
80000172: a019 j 80000178 <reset_vector+0x12c>
80000174: 0980006f j 8000020c <fail>
80000178: 00600193 li gp,6
8000017c: 00000313 li t1,0
80000180: 00000297 auipc t0,0x0
80000184: 00c28293 addi t0,t0,12 # 8000018c <reset_vector+0x140>
80000188: 00000363 beqz zero,8000018e <reset_vector+0x142>
8000018c: a011 j 80000190 <reset_vector+0x144>
8000018e: a019 j 80000194 <reset_vector+0x148>
80000190: 07c0006f j 8000020c <fail>
80000194: 00700193 li gp,7
80000198: 00001563 bnez zero,800001a2 <reset_vector+0x156>
8000019c: 00c0006f j 800001a8 <reset_vector+0x15c>
800001a0: a009 j 800001a2 <reset_vector+0x156>
800001a2: a009 j 800001a4 <reset_vector+0x158>
800001a4: 0680006f j 8000020c <fail>
800001a8: 00800193 li gp,8
800001ac: 301023f3 csrr t2,misa
800001b0: 0043f393 andi t2,t2,4
800001b4: 04038863 beqz t2,80000204 <reset_vector+0x1b8>
800001b8: 0001 nop
800001ba: 30127073 csrci misa,4
800001be: 0001 nop
800001c0: 301023f3 csrr t2,misa
800001c4: 0043f393 andi t2,t2,4
800001c8: 04038263 beqz t2,8000020c <fail>
800001cc: 00000297 auipc t0,0x0
800001d0: 03428293 addi t0,t0,52 # 80000200 <reset_vector+0x1b4>
800001d4: ffe28293 addi t0,t0,-2
800001d8: 34129073 csrw mepc,t0
800001dc: 30127073 csrci misa,4
800001e0: 301023f3 csrr t2,misa
800001e4: 0043f393 andi t2,t2,4
800001e8: 00039e63 bnez t2,80000204 <reset_vector+0x1b8>
800001ec: 000023b7 lui t2,0x2
800001f0: 80038393 addi t2,t2,-2048 # 1800 <_start-0x7fffe800>
800001f4: 3003a073 csrs mstatus,t2
800001f8: 30200073 mret
800001fc: 00000263 beqz zero,80000200 <reset_vector+0x1b4>
80000200: 30126073 csrsi misa,4
80000204: 01c0006f j 80000220 <pass>
80000208: 00301c63 bne zero,gp,80000220 <pass>
8000020c <fail>:
8000020c: 0ff0000f fence
80000210: 00018063 beqz gp,80000210 <fail+0x4>
80000214: 00119193 slli gp,gp,0x1
80000218: 0011e193 ori gp,gp,1
8000021c: 00000073 ecall
80000220 <pass>:
80000220: 0ff0000f fence
80000224: 00100193 li gp,1
80000228: 00000073 ecall
8000022c <mtvec_handler>:
8000022c: 00200513 li a0,2
80000230: 02a18063 beq gp,a0,80000250 <mtvec_handler+0x24>
80000234: 00400513 li a0,4
80000238: 00a18c63 beq gp,a0,80000250 <mtvec_handler+0x24>
8000023c: 00500513 li a0,5
80000240: 00a18863 beq gp,a0,80000250 <mtvec_handler+0x24>
80000244: 00600513 li a0,6
80000248: 00a18463 beq gp,a0,80000250 <mtvec_handler+0x24>
8000024c: fc1ff06f j 8000020c <fail>
80000250: fa031ee3 bnez t1,8000020c <fail>
80000254: 00000593 li a1,0
80000258: 34202573 csrr a0,mcause
8000025c: fab518e3 bne a0,a1,8000020c <fail>
80000260: 341025f3 csrr a1,mepc
80000264: 00458593 addi a1,a1,4
80000268: fab292e3 bne t0,a1,8000020c <fail>
8000026c: 34302573 csrr a0,mtval
80000270: 00050663 beqz a0,8000027c <mtvec_handler+0x50>
80000274: ffe50513 addi a0,a0,-2
80000278: f8551ae3 bne a0,t0,8000020c <fail>
8000027c: 00c58593 addi a1,a1,12
80000280: 34159073 csrw mepc,a1
80000284: 30200073 mret
80000288: c0001073 unimp
8000028c: 0000 unimp
8000028e: 0000 unimp
80000290: 0000 unimp
80000292: 0000 unimp
80000294: 0000 unimp
80000296: 0000 unimp
80000298: 0000 unimp
8000029a: 0000 unimp
8000029c: 0000 unimp
8000029e: 0000 unimp
800002a0: 0000 unimp
800002a2: 0000 unimp
800002a4: 0000 unimp
800002a6: 0000 unimp
800002a8: 0000 unimp
800002aa: 0000 unimp
800002ac: 0000 unimp
800002ae: 0000 unimp
800002b0: 0000 unimp
800002b2: 0000 unimp
800002b4: 0000 unimp
800002b6: 0000 unimp
800002b8: 0000 unimp
800002ba: 0000 unimp
800002bc: 0000 unimp
800002be: 0000 unimp
800002c0: 0000 unimp
800002c2: 0000 unimp
================================================
FILE: Tests/isa/rv32mi-p-mcsr.dump
================================================
rv32mi-p-mcsr: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 80000f17 auipc t5,0x80000
80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 80000297 auipc t0,0x80000
800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00002537 lui a0,0x2
800000f0: 80050513 addi a0,a0,-2048 # 1800 <_start-0x7fffe800>
800000f4: 30052073 csrs mstatus,a0
800000f8: 00000297 auipc t0,0x0
800000fc: 01428293 addi t0,t0,20 # 8000010c <test_2>
80000100: 34129073 csrw mepc,t0
80000104: f1402573 csrr a0,mhartid
80000108: 30200073 mret
8000010c <test_2>:
8000010c: 30102573 csrr a0,misa
80000110: 01e55513 srli a0,a0,0x1e
80000114: 00100e93 li t4,1
80000118: 00200193 li gp,2
8000011c: 03d51863 bne a0,t4,8000014c <fail>
80000120 <test_3>:
80000120: f1402573 csrr a0,mhartid
80000124: 00000e93 li t4,0
80000128: 00300193 li gp,3
8000012c: 03d51063 bne a0,t4,8000014c <fail>
80000130: f1302573 csrr a0,mimpid
80000134: f1202573 csrr a0,marchid
80000138: f1102573 csrr a0,mvendorid
8000013c: 00000293 li t0,0
80000140: 3052a073 csrs mtvec,t0
80000144: 3412a073 csrs mepc,t0
80000148: 00301c63 bne zero,gp,80000160 <pass>
8000014c <fail>:
8000014c: 0ff0000f fence
80000150: 00018063 beqz gp,80000150 <fail+0x4>
80000154: 00119193 slli gp,gp,0x1
80000158: 0011e193 ori gp,gp,1
8000015c: 00000073 ecall
80000160 <pass>:
80000160: 0ff0000f fence
80000164: 00100193 li gp,1
80000168: 00000073 ecall
8000016c: c0001073 unimp
80000170: 0000 unimp
80000172: 0000 unimp
80000174: 0000 unimp
80000176: 0000 unimp
80000178: 0000 unimp
8000017a: 0000 unimp
8000017c: 0000 unimp
8000017e: 0000 unimp
80000180: 0000 unimp
80000182: 0000 unimp
================================================
FILE: Tests/isa/rv32mi-p-sbreak.dump
================================================
rv32mi-p-sbreak: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 00000f17 auipc t5,0x0
80000024: 11cf0f13 addi t5,t5,284 # 8000013c <mtvec_handler>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 80000297 auipc t0,0x80000
800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00002537 lui a0,0x2
800000f0: 80050513 addi a0,a0,-2048 # 1800 <_start-0x7fffe800>
800000f4: 30052073 csrs mstatus,a0
800000f8: 00000297 auipc t0,0x0
800000fc: 01428293 addi t0,t0,20 # 8000010c <reset_vector+0xc0>
80000100: 34129073 csrw mepc,t0
80000104: f1402573 csrr a0,mhartid
80000108: 30200073 mret
8000010c: 00200193 li gp,2
80000110 <do_break>:
80000110: 00100073 ebreak
80000114: 0080006f j 8000011c <fail>
80000118: 00301c63 bne zero,gp,80000130 <pass>
8000011c <fail>:
8000011c: 0ff0000f fence
80000120: 00018063 beqz gp,80000120 <fail+0x4>
80000124: 00119193 slli gp,gp,0x1
80000128: 0011e193 ori gp,gp,1
8000012c: 00000073 ecall
80000130 <pass>:
80000130: 0ff0000f fence
80000134: 00100193 li gp,1
80000138: 00000073 ecall
8000013c <mtvec_handler>:
8000013c: 00300313 li t1,3
80000140: 342022f3 csrr t0,mcause
80000144: fc629ce3 bne t0,t1,8000011c <fail>
80000148: 00000317 auipc t1,0x0
8000014c: fc830313 addi t1,t1,-56 # 80000110 <do_break>
80000150: 341022f3 csrr t0,mepc
80000154: fc6294e3 bne t0,t1,8000011c <fail>
80000158: fd9ff06f j 80000130 <pass>
8000015c: c0001073 unimp
80000160: 0000 unimp
80000162: 0000 unimp
80000164: 0000 unimp
80000166: 0000 unimp
80000168: 0000 unimp
8000016a: 0000 unimp
8000016c: 0000 unimp
8000016e: 0000 unimp
80000170: 0000 unimp
80000172: 0000 unimp
80000174: 0000 unimp
80000176: 0000 unimp
80000178: 0000 unimp
8000017a: 0000 unimp
8000017c: 0000 unimp
8000017e: 0000 unimp
80000180: 0000 unimp
80000182: 0000 unimp
================================================
FILE: Tests/isa/rv32mi-p-scall.dump
================================================
rv32mi-p-scall: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 00000f17 auipc t5,0x0
80000024: 15cf0f13 addi t5,t5,348 # 8000017c <mtvec_handler>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 80000297 auipc t0,0x80000
800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00002537 lui a0,0x2
800000f0: 80050513 addi a0,a0,-2048 # 1800 <_start-0x7fffe800>
800000f4: 30052073 csrs mstatus,a0
800000f8: 00000297 auipc t0,0x0
800000fc: 01428293 addi t0,t0,20 # 8000010c <reset_vector+0xc0>
80000100: 34129073 csrw mepc,t0
80000104: f1402573 csrr a0,mhartid
80000108: 30200073 mret
8000010c: 00200193 li gp,2
80000110: 00800313 li t1,8
80000114: 000022b7 lui t0,0x2
80000118: 80028293 addi t0,t0,-2048 # 1800 <_start-0x7fffe800>
8000011c: 3002b073 csrc mstatus,t0
80000120: 300023f3 csrr t2,mstatus
80000124: 0072f2b3 and t0,t0,t2
80000128: 00028463 beqz t0,80000130 <reset_vector+0xe4>
8000012c: 00b00313 li t1,11
80000130: 000022b7 lui t0,0x2
80000134: 80028293 addi t0,t0,-2048 # 1800 <_start-0x7fffe800>
80000138: 3002b073 csrc mstatus,t0
8000013c: 00000297 auipc t0,0x0
80000140: 01028293 addi t0,t0,16 # 8000014c <reset_vector+0x100>
80000144: 34129073 csrw mepc,t0
80000148: 30200073 mret
8000014c: 00100193 li gp,1
80000150 <do_scall>:
80000150: 00000073 ecall
80000154: 0080006f j 8000015c <fail>
80000158: 00301c63 bne zero,gp,80000170 <pass>
8000015c <fail>:
8000015c: 0ff0000f fence
80000160: 00018063 beqz gp,80000160 <fail+0x4>
80000164: 00119193 slli gp,gp,0x1
80000168: 0011e193 ori gp,gp,1
8000016c: 00000073 ecall
80000170 <pass>:
80000170: 0ff0000f fence
80000174: 00100193 li gp,1
80000178: 00000073 ecall
8000017c <mtvec_handler>:
8000017c: 342022f3 csrr t0,mcause
80000180: fc629ee3 bne t0,t1,8000015c <fail>
80000184: 00000397 auipc t2,0x0
80000188: fcc38393 addi t2,t2,-52 # 80000150 <do_scall>
8000018c: 341022f3 csrr t0,mepc
80000190: fc7296e3 bne t0,t2,8000015c <fail>
80000194: fddff06f j 80000170 <pass>
80000198: c0001073 unimp
8000019c: 0000 unimp
8000019e: 0000 unimp
800001a0: 0000 unimp
800001a2: 0000 unimp
800001a4: 0000 unimp
800001a6: 0000 unimp
800001a8: 0000 unimp
800001aa: 0000 unimp
800001ac: 0000 unimp
800001ae: 0000 unimp
800001b0: 0000 unimp
800001b2: 0000 unimp
800001b4: 0000 unimp
800001b6: 0000 unimp
800001b8: 0000 unimp
800001ba: 0000 unimp
800001bc: 0000 unimp
800001be: 0000 unimp
800001c0: 0000 unimp
800001c2: 0000 unimp
================================================
FILE: Tests/isa/rv32mi-p-shamt.dump
================================================
rv32mi-p-shamt: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 00000f17 auipc t5,0x0
80000024: 134f0f13 addi t5,t5,308 # 80000154 <mtvec_handler>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 80000297 auipc t0,0x80000
800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00002537 lui a0,0x2
800000f0: 80050513 addi a0,a0,-2048 # 1800 <_start-0x7fffe800>
800000f4: 30052073 csrs mstatus,a0
800000f8: 00000297 auipc t0,0x0
800000fc: 01428293 addi t0,t0,20 # 8000010c <test_2>
80000100: 34129073 csrw mepc,t0
80000104: f1402573 csrr a0,mhartid
80000108: 30200073 mret
8000010c <test_2>:
8000010c: 00100513 li a0,1
80000110: 01051513 slli a0,a0,0x10
80000114: 00010eb7 lui t4,0x10
80000118: 00200193 li gp,2
8000011c: 01d51c63 bne a0,t4,80000134 <fail>
80000120 <test_3>:
80000120: 02051513 slli a0,a0,0x20
80000124: 00100e93 li t4,1
80000128: 00300193 li gp,3
8000012c: 01d01463 bne zero,t4,80000134 <fail>
80000130: 00301c63 bne zero,gp,80000148 <pass>
80000134 <fail>:
80000134: 0ff0000f fence
80000138: 00018063 beqz gp,80000138 <fail+0x4>
8000013c: 00119193 slli gp,gp,0x1
80000140: 0011e193 ori gp,gp,1
80000144: 00000073 ecall
80000148 <pass>:
80000148: 0ff0000f fence
8000014c: 00100193 li gp,1
80000150: 00000073 ecall
80000154 <mtvec_handler>:
80000154: 00200293 li t0,2
80000158: fc519ee3 bne gp,t0,80000134 <fail>
8000015c: 342022f3 csrr t0,mcause
80000160: 00200313 li t1,2
80000164: fc6298e3 bne t0,t1,80000134 <fail>
80000168: fe1ff06f j 80000148 <pass>
8000016c: c0001073 unimp
80000170: 0000 unimp
80000172: 0000 unimp
80000174: 0000 unimp
80000176: 0000 unimp
80000178: 0000 unimp
8000017a: 0000 unimp
8000017c: 0000 unimp
8000017e: 0000 unimp
80000180: 0000 unimp
80000182: 0000 unimp
================================================
FILE: Tests/isa/rv32si-p-csr.dump
================================================
rv32si-p-csr: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 80000f17 auipc t5,0x80000
80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfef>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 00000297 auipc t0,0x0
800000c8: 14c28293 addi t0,t0,332 # 80000210 <stvec_handler>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00001537 lui a0,0x1
800000f0: 80050513 addi a0,a0,-2048 # 800 <_start-0x7ffff800>
800000f4: 30052073 csrs mstatus,a0
800000f8: 02200513 li a0,34
800000fc: 30352073 csrs mideleg,a0
80000100: 00000297 auipc t0,0x0
80000104: 01428293 addi t0,t0,20 # 80000114 <reset_vector+0xc8>
80000108: 34129073 csrw mepc,t0
8000010c: f1402573 csrr a0,mhartid
80000110: 30200073 mret
80000114: 1401d073 csrwi sscratch,3
80000118 <test_2>:
80000118: 14002573 csrr a0,sscratch
8000011c: 00300e93 li t4,3
80000120: 00200193 li gp,2
80000124: 0dd51663 bne a0,t4,800001f0 <fail>
80000128 <test_3>:
80000128: 1400f5f3 csrrci a1,sscratch,1
8000012c: 00300e93 li t4,3
80000130: 00300193 li gp,3
80000134: 0bd59e63 bne a1,t4,800001f0 <fail>
80000138 <test_4>:
80000138: 14026673 csrrsi a2,sscratch,4
8000013c: 00200e93 li t4,2
80000140: 00400193 li gp,4
80000144: 0bd61663 bne a2,t4,800001f0 <fail>
80000148 <test_5>:
80000148: 140156f3 csrrwi a3,sscratch,2
8000014c: 00600e93 li t4,6
80000150: 00500193 li gp,5
80000154: 09d69e63 bne a3,t4,800001f0 <fail>
80000158 <test_6>:
80000158: 0bad2537 lui a0,0xbad2
8000015c: dea50513 addi a0,a0,-534 # bad1dea <_start-0x7452e216>
80000160: 140515f3 csrrw a1,sscratch,a0
80000164: 00200e93 li t4,2
80000168: 00600193 li gp,6
8000016c: 09d59263 bne a1,t4,800001f0 <fail>
80000170 <test_7>:
80000170: 00002537 lui a0,0x2
80000174: dea50513 addi a0,a0,-534 # 1dea <_start-0x7fffe216>
80000178: 14053573 csrrc a0,sscratch,a0
8000017c: 0bad2eb7 lui t4,0xbad2
80000180: deae8e93 addi t4,t4,-534 # bad1dea <_start-0x7452e216>
80000184: 00700193 li gp,7
80000188: 07d51463 bne a0,t4,800001f0 <fail>
8000018c <test_8>:
8000018c: 0000c537 lui a0,0xc
80000190: eef50513 addi a0,a0,-273 # beef <_start-0x7fff4111>
80000194: 14052573 csrrs a0,sscratch,a0
80000198: 0bad0eb7 lui t4,0xbad0
8000019c: 00800193 li gp,8
800001a0: 05d51863 bne a0,t4,800001f0 <fail>
800001a4 <test_9>:
800001a4: 14002573 csrr a0,sscratch
800001a8: 0badceb7 lui t4,0xbadc
800001ac: eefe8e93 addi t4,t4,-273 # badbeef <_start-0x74524111>
800001b0: 00900193 li gp,9
800001b4: 03d51e63 bne a0,t4,800001f0 <fail>
800001b8: 10000293 li t0,256
800001bc: 1002b073 csrc sstatus,t0
800001c0: 00000297 auipc t0,0x0
800001c4: 01028293 addi t0,t0,16 # 800001d0 <test_12>
800001c8: 14129073 csrw sepc,t0
800001cc: 10200073 sret
800001d0 <test_12>:
800001d0: 00000013 nop
800001d4: 00000e93 li t4,0
800001d8: 00c00193 li gp,12
800001dc: 01d01a63 bne zero,t4,800001f0 <fail>
800001e0 <finish>:
800001e0: 0ff0000f fence
800001e4: 00100193 li gp,1
800001e8: 00000073 ecall
800001ec: 00301c63 bne zero,gp,80000204 <pass>
800001f0 <fail>:
800001f0: 0ff0000f fence
800001f4: 00018063 beqz gp,800001f4 <fail+0x4>
800001f8: 00119193 slli gp,gp,0x1
800001fc: 0011e193 ori gp,gp,1
80000200: 00000073 ecall
80000204 <pass>:
80000204: 0ff0000f fence
80000208: 00100193 li gp,1
8000020c: 00000073 ecall
80000210 <stvec_handler>:
80000210: 00900293 li t0,9
80000214: 0051e663 bltu gp,t0,80000220 <stvec_handler+0x10>
80000218: 00b00293 li t0,11
8000021c: 0032fe63 bgeu t0,gp,80000238 <privileged>
80000220: 142022f3 csrr t0,scause
80000224: 00800313 li t1,8
80000228: fc6294e3 bne t0,t1,800001f0 <fail>
8000022c: 0ff0000f fence
80000230: 00100193 li gp,1
80000234: 00000073 ecall
80000238 <privileged>:
80000238: 142022f3 csrr t0,scause
8000023c: 00200313 li t1,2
80000240: fa6298e3 bne t0,t1,800001f0 <fail>
80000244: 141022f3 csrr t0,sepc
80000248: 00428293 addi t0,t0,4
8000024c: 14129073 csrw sepc,t0
80000250: 10200073 sret
80000254: c0001073 unimp
80000258: 0000 unimp
8000025a: 0000 unimp
8000025c: 0000 unimp
8000025e: 0000 unimp
80000260: 0000 unimp
80000262: 0000 unimp
80000264: 0000 unimp
80000266: 0000 unimp
80000268: 0000 unimp
8000026a: 0000 unimp
8000026c: 0000 unimp
8000026e: 0000 unimp
80000270: 0000 unimp
80000272: 0000 unimp
80000274: 0000 unimp
80000276: 0000 unimp
80000278: 0000 unimp
8000027a: 0000 unimp
8000027c: 0000 unimp
8000027e: 0000 unimp
80000280: 0000 unimp
80000282: 0000 unimp
Disassembly of section .data:
80002000 <begin_signature>:
80002000: 0001 nop
80002002: 0000 unimp
80002004: 0000 unimp
80002006: 0000 unimp
80002008: 0000 unimp
8000200a: 0000 unimp
8000200c: 0000 unimp
8000200e: 0000 unimp
================================================
FILE: Tests/isa/rv32si-p-dirty.dump
================================================
rv32si-p-dirty: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 00000f17 auipc t5,0x0
80000024: 1d0f0f13 addi t5,t5,464 # 800001f0 <mtvec_handler>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfef>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 80000297 auipc t0,0x80000
800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00002537 lui a0,0x2
800000f0: 80050513 addi a0,a0,-2048 # 1800 <_start-0x7fffe800>
800000f4: 30052073 csrs mstatus,a0
800000f8: 00000297 auipc t0,0x0
800000fc: 01428293 addi t0,t0,20 # 8000010c <reset_vector+0xc0>
80000100: 34129073 csrw mepc,t0
80000104: f1402573 csrr a0,mhartid
80000108: 30200073 mret
8000010c: 80000537 lui a0,0x80000
80000110: 00002597 auipc a1,0x2
80000114: ef058593 addi a1,a1,-272 # 80002000 <begin_signature>
80000118: 00c5d593 srli a1,a1,0xc
8000011c: 00a5e5b3 or a1,a1,a0
80000120: 18059073 csrw satp,a1
80000124: 12000073 sfence.vma
80000128: 000215b7 lui a1,0x21
8000012c: 80058593 addi a1,a1,-2048 # 20800 <_start-0x7ffdf800>
80000130: 3005a073 csrs mstatus,a1
80000134: 00200193 li gp,2
80000138: 00100393 li t2,1
8000013c: 80002517 auipc a0,0x80002
80000140: ec752623 sw t2,-308(a0) # 2008 <_start-0x7fffdff8>
80000144: 00300193 li gp,3
80000148: 000415b7 lui a1,0x41
8000014c: 80058593 addi a1,a1,-2048 # 40800 <_start-0x7ffbf800>
80000150: 3005a073 csrs mstatus,a1
80000154: 80002297 auipc t0,0x80002
80000158: eb42a283 lw t0,-332(t0) # 2008 <_start-0x7fffdff8>
8000015c: 10029063 bnez t0,8000025c <die>
80000160: 80002517 auipc a0,0x80002
80000164: ea752423 sw t2,-344(a0) # 2008 <_start-0x7fffdff8>
80000168: 80002297 auipc t0,0x80002
8000016c: ea02a283 lw t0,-352(t0) # 2008 <_start-0x7fffdff8>
80000170: 0e729663 bne t0,t2,8000025c <die>
80000174: 000202b7 lui t0,0x20
80000178: 3002b073 csrc mstatus,t0
8000017c: 00002297 auipc t0,0x2
80000180: e842a283 lw t0,-380(t0) # 80002000 <begin_signature>
80000184: 0c000513 li a0,192
80000188: 00a2f2b3 and t0,t0,a0
8000018c: 0ca29863 bne t0,a0,8000025c <die>
80000190: 000202b7 lui t0,0x20
80000194: 3002a073 csrs mstatus,t0
80000198: 00400193 li gp,4
8000019c: 80002517 auipc a0,0x80002
800001a0: e6452503 lw a0,-412(a0) # 2000 <_start-0x7fffe000>
800001a4: 40056513 ori a0,a0,1024
800001a8: 80002297 auipc t0,0x80002
800001ac: e4a2ac23 sw a0,-424(t0) # 2000 <_start-0x7fffe000>
800001b0: 12000073 sfence.vma
800001b4: 80002297 auipc t0,0x80002
800001b8: e4a2a623 sw a0,-436(t0) # 2000 <_start-0x7fffe000>
800001bc: 0a00006f j 8000025c <die>
800001c0: 0ff0000f fence
800001c4: 00100193 li gp,1
800001c8: 00000073 ecall
800001cc: 00301c63 bne zero,gp,800001e4 <pass>
800001d0 <fail>:
800001d0: 0ff0000f fence
800001d4: 00018063 beqz gp,800001d4 <fail+0x4>
800001d8: 00119193 slli gp,gp,0x1
800001dc: 0011e193 ori gp,gp,1
800001e0: 00000073 ecall
800001e4 <pass>:
800001e4: 0ff0000f fence
800001e8: 00100193 li gp,1
800001ec: 00000073 ecall
800001f0 <mtvec_handler>:
800001f0: 342022f3 csrr t0,mcause
800001f4: ff128293 addi t0,t0,-15
800001f8: 06029263 bnez t0,8000025c <die>
800001fc: 00200313 li t1,2
80000200: 02619263 bne gp,t1,80000224 <skip+0x10>
80000204: 00002297 auipc t0,0x2
80000208: dfc2a283 lw t0,-516(t0) # 80002000 <begin_signature>
8000020c: 0802f313 andi t1,t0,128
80000210: 04031663 bnez t1,8000025c <die>
80000214 <skip>:
80000214: 341022f3 csrr t0,mepc
80000218: 00428293 addi t0,t0,4
8000021c: 34129073 csrw mepc,t0
80000220: 30200073 mret
80000224: 00300313 li t1,3
80000228: 02619463 bne gp,t1,80000250 <skip+0x3c>
8000022c: 00002297 auipc t0,0x2
80000230: dd42a283 lw t0,-556(t0) # 80002000 <begin_signature>
80000234: 0802f313 andi t1,t0,128
80000238: 02031263 bnez t1,8000025c <die>
8000023c: 0802e293 ori t0,t0,128
80000240: 00002317 auipc t1,0x2
80000244: dc532023 sw t0,-576(t1) # 80002000 <begin_signature>
80000248: 12000073 sfence.vma
8000024c: 30200073 mret
80000250: 00400313 li t1,4
80000254: 00619463 bne gp,t1,8000025c <die>
80000258: f8dff06f j 800001e4 <pass>
8000025c <die>:
8000025c: 0ff0000f fence
80000260: 00018063 beqz gp,80000260 <die+0x4>
80000264: 00119193 slli gp,gp,0x1
80000268: 0011e193 ori gp,gp,1
8000026c: 00000073 ecall
80000270: c0001073 unimp
80000274: 0000 unimp
80000276: 0000 unimp
80000278: 0000 unimp
8000027a: 0000 unimp
8000027c: 0000 unimp
8000027e: 0000 unimp
80000280: 0000 unimp
80000282: 0000 unimp
Disassembly of section .data:
80002000 <begin_signature>:
80002000: 005f 2000 0000 0x2000005f
80002006: 0000 unimp
80002008 <dummy>:
80002008: 0000 unimp
8000200a: 0000 unimp
8000200c: 0000 unimp
8000200e: 0000 unimp
================================================
FILE: Tests/isa/rv32si-p-ma_fetch.dump
================================================
rv32si-p-ma_fetch: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 80000f17 auipc t5,0x80000
80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 00000297 auipc t0,0x0
800000c8: 11428293 addi t0,t0,276 # 800001d8 <stvec_handler>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00001537 lui a0,0x1
800000f0: 80050513 addi a0,a0,-2048 # 800 <_start-0x7ffff800>
800000f4: 30052073 csrs mstatus,a0
800000f8: 02200513 li a0,34
800000fc: 30352073 csrs mideleg,a0
80000100: 00000297 auipc t0,0x0
80000104: 01428293 addi t0,t0,20 # 80000114 <reset_vector+0xc8>
80000108: 34129073 csrw mepc,t0
8000010c: f1402573 csrr a0,mhartid
80000110: 30200073 mret
80000114: 00200193 li gp,2
80000118: 00000313 li t1,0
8000011c: 00000297 auipc t0,0x0
80000120: 00c28293 addi t0,t0,12 # 80000128 <reset_vector+0xdc>
80000124: 00228367 jalr t1,2(t0)
80000128: a011 j 8000012c <reset_vector+0xe0>
8000012a: a019 j 80000130 <reset_vector+0xe4>
8000012c: 08c0006f j 800001b8 <fail>
80000130: 00300193 li gp,3
80000134: 00000297 auipc t0,0x0
80000138: 00c28293 addi t0,t0,12 # 80000140 <reset_vector+0xf4>
8000013c: 00128367 jalr t1,1(t0)
80000140: 0080006f j 80000148 <reset_vector+0xfc>
80000144: 0740006f j 800001b8 <fail>
80000148: 00400193 li gp,4
8000014c: 00000313 li t1,0
80000150: 00000297 auipc t0,0x0
80000154: 00c28293 addi t0,t0,12 # 8000015c <reset_vector+0x110>
80000158: 00328367 jalr t1,3(t0)
8000015c: a011 j 80000160 <reset_vector+0x114>
8000015e: a019 j 80000164 <reset_vector+0x118>
80000160: 0580006f j 800001b8 <fail>
80000164: 00500193 li gp,5
80000168: 00000313 li t1,0
8000016c: 00000297 auipc t0,0x0
80000170: 00c28293 addi t0,t0,12 # 80000178 <reset_vector+0x12c>
80000174: 0060036f jal t1,8000017a <reset_vector+0x12e>
80000178: a011 j 8000017c <reset_vector+0x130>
8000017a: a019 j 80000180 <reset_vector+0x134>
8000017c: 03c0006f j 800001b8 <fail>
80000180: 00600193 li gp,6
80000184: 00000313 li t1,0
80000188: 00000297 auipc t0,0x0
8000018c: 00c28293 addi t0,t0,12 # 80000194 <reset_vector+0x148>
80000190: 00000363 beqz zero,80000196 <reset_vector+0x14a>
80000194: a011 j 80000198 <reset_vector+0x14c>
80000196: a019 j 8000019c <reset_vector+0x150>
80000198: 0200006f j 800001b8 <fail>
8000019c: 00700193 li gp,7
800001a0: 00001563 bnez zero,800001aa <reset_vector+0x15e>
800001a4: 00c0006f j 800001b0 <reset_vector+0x164>
800001a8: a009 j 800001aa <reset_vector+0x15e>
800001aa: a009 j 800001ac <reset_vector+0x160>
800001ac: 00c0006f j 800001b8 <fail>
800001b0: 01c0006f j 800001cc <pass>
800001b4: 00301c63 bne zero,gp,800001cc <pass>
800001b8 <fail>:
800001b8: 0ff0000f fence
800001bc: 00018063 beqz gp,800001bc <fail+0x4>
800001c0: 00119193 slli gp,gp,0x1
800001c4: 0011e193 ori gp,gp,1
800001c8: 00000073 ecall
800001cc <pass>:
800001cc: 0ff0000f fence
800001d0: 00100193 li gp,1
800001d4: 00000073 ecall
800001d8 <stvec_handler>:
800001d8: 00200513 li a0,2
800001dc: 02a18063 beq gp,a0,800001fc <stvec_handler+0x24>
800001e0: 00400513 li a0,4
800001e4: 00a18c63 beq gp,a0,800001fc <stvec_handler+0x24>
800001e8: 00500513 li a0,5
800001ec: 00a18863 beq gp,a0,800001fc <stvec_handler+0x24>
800001f0: 00600513 li a0,6
800001f4: 00a18463 beq gp,a0,800001fc <stvec_handler+0x24>
800001f8: fc1ff06f j 800001b8 <fail>
800001fc: fa031ee3 bnez t1,800001b8 <fail>
80000200: 00000593 li a1,0
80000204: 14202573 csrr a0,scause
80000208: fab518e3 bne a0,a1,800001b8 <fail>
8000020c: 141025f3 csrr a1,sepc
80000210: 00458593 addi a1,a1,4
80000214: fab292e3 bne t0,a1,800001b8 <fail>
80000218: 14302573 csrr a0,stval
8000021c: 00050663 beqz a0,80000228 <stvec_handler+0x50>
80000220: ffe50513 addi a0,a0,-2
80000224: f8551ae3 bne a0,t0,800001b8 <fail>
80000228: 00c58593 addi a1,a1,12
8000022c: 14159073 csrw sepc,a1
80000230: 10200073 sret
80000234: c0001073 unimp
80000238: 0000 unimp
8000023a: 0000 unimp
8000023c: 0000 unimp
8000023e: 0000 unimp
80000240: 0000 unimp
80000242: 0000 unimp
================================================
FILE: Tests/isa/rv32si-p-sbreak.dump
================================================
rv32si-p-sbreak: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 80000f17 auipc t5,0x80000
80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 00000297 auipc t0,0x0
800000c8: 08028293 addi t0,t0,128 # 80000144 <stvec_handler>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00001537 lui a0,0x1
800000f0: 80050513 addi a0,a0,-2048 # 800 <_start-0x7ffff800>
800000f4: 30052073 csrs mstatus,a0
800000f8: 02200513 li a0,34
800000fc: 30352073 csrs mideleg,a0
80000100: 00000297 auipc t0,0x0
80000104: 01428293 addi t0,t0,20 # 80000114 <reset_vector+0xc8>
80000108: 34129073 csrw mepc,t0
8000010c: f1402573 csrr a0,mhartid
80000110: 30200073 mret
80000114: 00200193 li gp,2
80000118 <do_break>:
80000118: 00100073 ebreak
8000011c: 0080006f j 80000124 <fail>
80000120: 00301c63 bne zero,gp,80000138 <pass>
80000124 <fail>:
80000124: 0ff0000f fence
80000128: 00018063 beqz gp,80000128 <fail+0x4>
8000012c: 00119193 slli gp,gp,0x1
80000130: 0011e193 ori gp,gp,1
80000134: 00000073 ecall
80000138 <pass>:
80000138: 0ff0000f fence
8000013c: 00100193 li gp,1
80000140: 00000073 ecall
80000144 <stvec_handler>:
80000144: 00300313 li t1,3
80000148: 142022f3 csrr t0,scause
8000014c: fc629ce3 bne t0,t1,80000124 <fail>
80000150: 00000317 auipc t1,0x0
80000154: fc830313 addi t1,t1,-56 # 80000118 <do_break>
80000158: 141022f3 csrr t0,sepc
8000015c: fc6294e3 bne t0,t1,80000124 <fail>
80000160: fd9ff06f j 80000138 <pass>
80000164: c0001073 unimp
80000168: 0000 unimp
8000016a: 0000 unimp
8000016c: 0000 unimp
8000016e: 0000 unimp
80000170: 0000 unimp
80000172: 0000 unimp
80000174: 0000 unimp
80000176: 0000 unimp
80000178: 0000 unimp
8000017a: 0000 unimp
8000017c: 0000 unimp
8000017e: 0000 unimp
80000180: 0000 unimp
80000182: 0000 unimp
================================================
FILE: Tests/isa/rv32si-p-scall.dump
================================================
rv32si-p-scall: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 80000f17 auipc t5,0x80000
80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 00000297 auipc t0,0x0
800000c8: 0a028293 addi t0,t0,160 # 80000164 <stvec_handler>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00001537 lui a0,0x1
800000f0: 80050513 addi a0,a0,-2048 # 800 <_start-0x7ffff800>
800000f4: 30052073 csrs mstatus,a0
800000f8: 02200513 li a0,34
800000fc: 30352073 csrs mideleg,a0
80000100: 00000297 auipc t0,0x0
80000104: 01428293 addi t0,t0,20 # 80000114 <reset_vector+0xc8>
80000108: 34129073 csrw mepc,t0
8000010c: f1402573 csrr a0,mhartid
80000110: 30200073 mret
80000114: 00200193 li gp,2
80000118: 00800313 li t1,8
8000011c: 10000293 li t0,256
80000120: 1002b073 csrc sstatus,t0
80000124: 00000297 auipc t0,0x0
80000128: 01028293 addi t0,t0,16 # 80000134 <reset_vector+0xe8>
8000012c: 14129073 csrw sepc,t0
80000130: 10200073 sret
80000134: 00100193 li gp,1
80000138 <do_scall>:
80000138: 00000073 ecall
8000013c: 0080006f j 80000144 <fail>
80000140: 00301c63 bne zero,gp,80000158 <pass>
80000144 <fail>:
80000144: 0ff0000f fence
80000148: 00018063 beqz gp,80000148 <fail+0x4>
8000014c: 00119193 slli gp,gp,0x1
80000150: 0011e193 ori gp,gp,1
80000154: 00000073 ecall
80000158 <pass>:
80000158: 0ff0000f fence
8000015c: 00100193 li gp,1
80000160: 00000073 ecall
80000164 <stvec_handler>:
80000164: 142022f3 csrr t0,scause
80000168: fc629ee3 bne t0,t1,80000144 <fail>
8000016c: 00000397 auipc t2,0x0
80000170: fcc38393 addi t2,t2,-52 # 80000138 <do_scall>
80000174: 141022f3 csrr t0,sepc
80000178: fc7296e3 bne t0,t2,80000144 <fail>
8000017c: fddff06f j 80000158 <pass>
80000180: c0001073 unimp
================================================
FILE: Tests/isa/rv32si-p-wfi.dump
================================================
rv32si-p-wfi: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 80000f17 auipc t5,0x80000
80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdfff>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 80000297 auipc t0,0x80000
800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00001537 lui a0,0x1
800000f0: 80050513 addi a0,a0,-2048 # 800 <_start-0x7ffff800>
800000f4: 30052073 csrs mstatus,a0
800000f8: 02200513 li a0,34
800000fc: 30352073 csrs mideleg,a0
80000100: 00000297 auipc t0,0x0
80000104: 01428293 addi t0,t0,20 # 80000114 <reset_vector+0xc8>
80000108: 34129073 csrw mepc,t0
8000010c: f1402573 csrr a0,mhartid
80000110: 30200073 mret
80000114: 10017073 csrci sstatus,2
80000118: 10416073 csrsi sie,2
8000011c: 14416073 csrsi sip,2
80000120: 10500073 wfi
80000124: 0ff0000f fence
80000128: 00100193 li gp,1
8000012c: 00000073 ecall
80000130: 00301c63 bne zero,gp,80000148 <pass>
80000134 <fail>:
80000134: 0ff0000f fence
80000138: 00018063 beqz gp,80000138 <fail+0x4>
8000013c: 00119193 slli gp,gp,0x1
80000140: 0011e193 ori gp,gp,1
80000144: 00000073 ecall
80000148 <pass>:
80000148: 0ff0000f fence
8000014c: 00100193 li gp,1
80000150: 00000073 ecall
80000154: c0001073 unimp
80000158: 0000 unimp
8000015a: 0000 unimp
8000015c: 0000 unimp
8000015e: 0000 unimp
80000160: 0000 unimp
80000162: 0000 unimp
80000164: 0000 unimp
80000166: 0000 unimp
80000168: 0000 unimp
8000016a: 0000 unimp
8000016c: 0000 unimp
8000016e: 0000 unimp
80000170: 0000 unimp
80000172: 0000 unimp
80000174: 0000 unimp
80000176: 0000 unimp
80000178: 0000 unimp
8000017a: 0000 unimp
8000017c: 0000 unimp
8000017e: 0000 unimp
80000180: 0000 unimp
80000182: 0000 unimp
================================================
FILE: Tests/isa/rv32ua-p-amoadd_w.dump
================================================
rv32ua-p-amoadd_w: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 80000f17 auipc t5,0x80000
80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdff7>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 80000297 auipc t0,0x80000
800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00000297 auipc t0,0x0
800000f0: 01428293 addi t0,t0,20 # 80000100 <test_2>
800000f4: 34129073 csrw mepc,t0
800000f8: f1402573 csrr a0,mhartid
800000fc: 30200073 mret
80000100 <test_2>:
80000100: 80000537 lui a0,0x80000
80000104: 80000593 li a1,-2048
80000108: 00002697 auipc a3,0x2
8000010c: ef868693 addi a3,a3,-264 # 80002000 <begin_signature>
80000110: 00a6a023 sw a0,0(a3)
80000114: 00b6a72f amoadd.w a4,a1,(a3)
80000118: 80000eb7 lui t4,0x80000
8000011c: 00200193 li gp,2
80000120: 05d71263 bne a4,t4,80000164 <fail>
80000124 <test_3>:
80000124: 0006a783 lw a5,0(a3)
80000128: 80000eb7 lui t4,0x80000
8000012c: 800e8e93 addi t4,t4,-2048 # 7ffff800 <_end+0xffffd7f8>
80000130: 00300193 li gp,3
80000134: 03d79863 bne a5,t4,80000164 <fail>
80000138 <test_4>:
80000138: 800005b7 lui a1,0x80000
8000013c: 00b6a72f amoadd.w a4,a1,(a3)
80000140: 80000eb7 lui t4,0x80000
80000144: 800e8e93 addi t4,t4,-2048 # 7ffff800 <_end+0xffffd7f8>
80000148: 00400193 li gp,4
8000014c: 01d71c63 bne a4,t4,80000164 <fail>
80000150 <test_5>:
80000150: 0006a783 lw a5,0(a3)
80000154: 80000e93 li t4,-2048
80000158: 00500193 li gp,5
8000015c: 01d79463 bne a5,t4,80000164 <fail>
80000160: 00301c63 bne zero,gp,80000178 <pass>
80000164 <fail>:
80000164: 0ff0000f fence
80000168: 00018063 beqz gp,80000168 <fail+0x4>
8000016c: 00119193 slli gp,gp,0x1
80000170: 0011e193 ori gp,gp,1
80000174: 00000073 ecall
80000178 <pass>:
80000178: 0ff0000f fence
8000017c: 00100193 li gp,1
80000180: 00000073 ecall
80000184: c0001073 unimp
80000188: 0000 unimp
8000018a: 0000 unimp
8000018c: 0000 unimp
8000018e: 0000 unimp
80000190: 0000 unimp
80000192: 0000 unimp
80000194: 0000 unimp
80000196: 0000 unimp
80000198: 0000 unimp
8000019a: 0000 unimp
8000019c: 0000 unimp
8000019e: 0000 unimp
800001a0: 0000 unimp
800001a2: 0000 unimp
800001a4: 0000 unimp
800001a6: 0000 unimp
800001a8: 0000 unimp
800001aa: 0000 unimp
800001ac: 0000 unimp
800001ae: 0000 unimp
800001b0: 0000 unimp
800001b2: 0000 unimp
800001b4: 0000 unimp
800001b6: 0000 unimp
800001b8: 0000 unimp
800001ba: 0000 unimp
800001bc: 0000 unimp
800001be: 0000 unimp
800001c0: 0000 unimp
800001c2: 0000 unimp
================================================
FILE: Tests/isa/rv32ua-p-amoand_w.dump
================================================
rv32ua-p-amoand_w: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 80000f17 auipc t5,0x80000
80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdff7>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 80000297 auipc t0,0x80000
800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00000297 auipc t0,0x0
800000f0: 01428293 addi t0,t0,20 # 80000100 <test_2>
800000f4: 34129073 csrw mepc,t0
800000f8: f1402573 csrr a0,mhartid
800000fc: 30200073 mret
80000100 <test_2>:
80000100: 80000537 lui a0,0x80000
80000104: 80000593 li a1,-2048
80000108: 00002697 auipc a3,0x2
8000010c: ef868693 addi a3,a3,-264 # 80002000 <begin_signature>
80000110: 00a6a023 sw a0,0(a3)
80000114: 60b6a72f amoand.w a4,a1,(a3)
80000118: 80000eb7 lui t4,0x80000
8000011c: 00200193 li gp,2
80000120: 03d71e63 bne a4,t4,8000015c <fail>
80000124 <test_3>:
80000124: 0006a783 lw a5,0(a3)
80000128: 80000eb7 lui t4,0x80000
8000012c: 00300193 li gp,3
80000130: 03d79663 bne a5,t4,8000015c <fail>
80000134 <test_4>:
80000134: 800005b7 lui a1,0x80000
80000138: 60b6a72f amoand.w a4,a1,(a3)
8000013c: 80000eb7 lui t4,0x80000
80000140: 00400193 li gp,4
80000144: 01d71c63 bne a4,t4,8000015c <fail>
80000148 <test_5>:
80000148: 0006a783 lw a5,0(a3)
8000014c: 80000eb7 lui t4,0x80000
80000150: 00500193 li gp,5
80000154: 01d79463 bne a5,t4,8000015c <fail>
80000158: 00301c63 bne zero,gp,80000170 <pass>
8000015c <fail>:
8000015c: 0ff0000f fence
80000160: 00018063 beqz gp,80000160 <fail+0x4>
80000164: 00119193 slli gp,gp,0x1
80000168: 0011e193 ori gp,gp,1
8000016c: 00000073 ecall
80000170 <pass>:
80000170: 0ff0000f fence
80000174: 00100193 li gp,1
80000178: 00000073 ecall
8000017c: c0001073 unimp
80000180: 0000 unimp
80000182: 0000 unimp
================================================
FILE: Tests/isa/rv32ua-p-amomax_w.dump
================================================
rv32ua-p-amomax_w: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 80000f17 auipc t5,0x80000
80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdff7>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 80000297 auipc t0,0x80000
800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00000297 auipc t0,0x0
800000f0: 01428293 addi t0,t0,20 # 80000100 <test_2>
800000f4: 34129073 csrw mepc,t0
800000f8: f1402573 csrr a0,mhartid
800000fc: 30200073 mret
80000100 <test_2>:
80000100: 80000537 lui a0,0x80000
80000104: 80000593 li a1,-2048
80000108: 00002697 auipc a3,0x2
8000010c: ef868693 addi a3,a3,-264 # 80002000 <begin_signature>
80000110: 00a6a023 sw a0,0(a3)
80000114: a0b6a72f amomax.w a4,a1,(a3)
80000118: 80000eb7 lui t4,0x80000
8000011c: 00200193 li gp,2
80000120: 05d71063 bne a4,t4,80000160 <fail>
80000124 <test_3>:
80000124: 0006a783 lw a5,0(a3)
80000128: 80000e93 li t4,-2048
8000012c: 00300193 li gp,3
80000130: 03d79863 bne a5,t4,80000160 <fail>
80000134 <test_4>:
80000134: 00100593 li a1,1
80000138: 0006a023 sw zero,0(a3)
8000013c: a0b6a72f amomax.w a4,a1,(a3)
80000140: 00000e93 li t4,0
80000144: 00400193 li gp,4
80000148: 01d71c63 bne a4,t4,80000160 <fail>
8000014c <test_5>:
8000014c: 0006a783 lw a5,0(a3)
80000150: 00100e93 li t4,1
80000154: 00500193 li gp,5
80000158: 01d79463 bne a5,t4,80000160 <fail>
8000015c: 00301c63 bne zero,gp,80000174 <pass>
80000160 <fail>:
80000160: 0ff0000f fence
80000164: 00018063 beqz gp,80000164 <fail+0x4>
80000168: 00119193 slli gp,gp,0x1
8000016c: 0011e193 ori gp,gp,1
80000170: 00000073 ecall
80000174 <pass>:
80000174: 0ff0000f fence
80000178: 00100193 li gp,1
8000017c: 00000073 ecall
80000180: c0001073 unimp
================================================
FILE: Tests/isa/rv32ua-p-amomaxu_w.dump
================================================
rv32ua-p-amomaxu_w: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 80000f17 auipc t5,0x80000
80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdff7>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 80000297 auipc t0,0x80000
800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00000297 auipc t0,0x0
800000f0: 01428293 addi t0,t0,20 # 80000100 <test_2>
800000f4: 34129073 csrw mepc,t0
800000f8: f1402573 csrr a0,mhartid
800000fc: 30200073 mret
80000100 <test_2>:
80000100: 80000537 lui a0,0x80000
80000104: 80000593 li a1,-2048
80000108: 00002697 auipc a3,0x2
8000010c: ef868693 addi a3,a3,-264 # 80002000 <begin_signature>
80000110: 00a6a023 sw a0,0(a3)
80000114: e0b6a72f amomaxu.w a4,a1,(a3)
80000118: 80000eb7 lui t4,0x80000
8000011c: 00200193 li gp,2
80000120: 05d71063 bne a4,t4,80000160 <fail>
80000124 <test_3>:
80000124: 0006a783 lw a5,0(a3)
80000128: 80000e93 li t4,-2048
8000012c: 00300193 li gp,3
80000130: 03d79863 bne a5,t4,80000160 <fail>
80000134 <test_4>:
80000134: fff00593 li a1,-1
80000138: 0006a023 sw zero,0(a3)
8000013c: e0b6a72f amomaxu.w a4,a1,(a3)
80000140: 00000e93 li t4,0
80000144: 00400193 li gp,4
80000148: 01d71c63 bne a4,t4,80000160 <fail>
8000014c <test_5>:
8000014c: 0006a783 lw a5,0(a3)
80000150: fff00e93 li t4,-1
80000154: 00500193 li gp,5
80000158: 01d79463 bne a5,t4,80000160 <fail>
8000015c: 00301c63 bne zero,gp,80000174 <pass>
80000160 <fail>:
80000160: 0ff0000f fence
80000164: 00018063 beqz gp,80000164 <fail+0x4>
80000168: 00119193 slli gp,gp,0x1
8000016c: 0011e193 ori gp,gp,1
80000170: 00000073 ecall
80000174 <pass>:
80000174: 0ff0000f fence
80000178: 00100193 li gp,1
8000017c: 00000073 ecall
80000180: c0001073 unimp
================================================
FILE: Tests/isa/rv32ua-p-amomin_w.dump
================================================
rv32ua-p-amomin_w: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 80000f17 auipc t5,0x80000
80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdff7>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 80000297 auipc t0,0x80000
800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00000297 auipc t0,0x0
800000f0: 01428293 addi t0,t0,20 # 80000100 <test_2>
800000f4: 34129073 csrw mepc,t0
800000f8: f1402573 csrr a0,mhartid
800000fc: 30200073 mret
80000100 <test_2>:
80000100: 80000537 lui a0,0x80000
80000104: 80000593 li a1,-2048
80000108: 00002697 auipc a3,0x2
8000010c: ef868693 addi a3,a3,-264 # 80002000 <begin_signature>
80000110: 00a6a023 sw a0,0(a3)
80000114: 80b6a72f amomin.w a4,a1,(a3)
80000118: 80000eb7 lui t4,0x80000
8000011c: 00200193 li gp,2
80000120: 05d71063 bne a4,t4,80000160 <fail>
80000124 <test_3>:
80000124: 0006a783 lw a5,0(a3)
80000128: 80000eb7 lui t4,0x80000
8000012c: 00300193 li gp,3
80000130: 03d79863 bne a5,t4,80000160 <fail>
80000134 <test_4>:
80000134: fff00593 li a1,-1
80000138: 0006a023 sw zero,0(a3)
8000013c: 80b6a72f amomin.w a4,a1,(a3)
80000140: 00000e93 li t4,0
80000144: 00400193 li gp,4
80000148: 01d71c63 bne a4,t4,80000160 <fail>
8000014c <test_5>:
8000014c: 0006a783 lw a5,0(a3)
80000150: fff00e93 li t4,-1
80000154: 00500193 li gp,5
80000158: 01d79463 bne a5,t4,80000160 <fail>
8000015c: 00301c63 bne zero,gp,80000174 <pass>
80000160 <fail>:
80000160: 0ff0000f fence
80000164: 00018063 beqz gp,80000164 <fail+0x4>
80000168: 00119193 slli gp,gp,0x1
8000016c: 0011e193 ori gp,gp,1
80000170: 00000073 ecall
80000174 <pass>:
80000174: 0ff0000f fence
80000178: 00100193 li gp,1
8000017c: 00000073 ecall
80000180: c0001073 unimp
================================================
FILE: Tests/isa/rv32ua-p-amominu_w.dump
================================================
rv32ua-p-amominu_w: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 80000f17 auipc t5,0x80000
80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdff7>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 80000297 auipc t0,0x80000
800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000>
800000cc: 00028e63 beqz t0,800000e8 <reset_vector+0x9c>
800000d0: 10529073 csrw stvec,t0
800000d4: 0000b2b7 lui t0,0xb
800000d8: 10928293 addi t0,t0,265 # b109 <_start-0x7fff4ef7>
800000dc: 30229073 csrw medeleg,t0
800000e0: 30202373 csrr t1,medeleg
800000e4: f4629ce3 bne t0,t1,8000003c <handle_exception>
800000e8: 30005073 csrwi mstatus,0
800000ec: 00000297 auipc t0,0x0
800000f0: 01428293 addi t0,t0,20 # 80000100 <test_2>
800000f4: 34129073 csrw mepc,t0
800000f8: f1402573 csrr a0,mhartid
800000fc: 30200073 mret
80000100 <test_2>:
80000100: 80000537 lui a0,0x80000
80000104: 80000593 li a1,-2048
80000108: 00002697 auipc a3,0x2
8000010c: ef868693 addi a3,a3,-264 # 80002000 <begin_signature>
80000110: 00a6a023 sw a0,0(a3)
80000114: c0b6a72f amominu.w a4,a1,(a3)
80000118: 80000eb7 lui t4,0x80000
8000011c: 00200193 li gp,2
80000120: 05d71063 bne a4,t4,80000160 <fail>
80000124 <test_3>:
80000124: 0006a783 lw a5,0(a3)
80000128: 80000eb7 lui t4,0x80000
8000012c: 00300193 li gp,3
80000130: 03d79863 bne a5,t4,80000160 <fail>
80000134 <test_4>:
80000134: fff00593 li a1,-1
80000138: 0006a023 sw zero,0(a3)
8000013c: c0b6a72f amominu.w a4,a1,(a3)
80000140: 00000e93 li t4,0
80000144: 00400193 li gp,4
80000148: 01d71c63 bne a4,t4,80000160 <fail>
8000014c <test_5>:
8000014c: 0006a783 lw a5,0(a3)
80000150: 00000e93 li t4,0
80000154: 00500193 li gp,5
80000158: 01d79463 bne a5,t4,80000160 <fail>
8000015c: 00301c63 bne zero,gp,80000174 <pass>
80000160 <fail>:
80000160: 0ff0000f fence
80000164: 00018063 beqz gp,80000164 <fail+0x4>
80000168: 00119193 slli gp,gp,0x1
8000016c: 0011e193 ori gp,gp,1
80000170: 00000073 ecall
80000174 <pass>:
80000174: 0ff0000f fence
80000178: 00100193 li gp,1
8000017c: 00000073 ecall
80000180: c0001073 unimp
================================================
FILE: Tests/isa/rv32ua-p-amoor_w.dump
================================================
rv32ua-p-amoor_w: file format elf32-littleriscv
Disassembly of section .text.init:
80000000 <_start>:
80000000: 04c0006f j 8000004c <reset_vector>
80000004 <trap_vector>:
80000004: 34202f73 csrr t5,mcause
80000008: 00800f93 li t6,8
8000000c: 03ff0a63 beq t5,t6,80000040 <write_tohost>
80000010: 00900f93 li t6,9
80000014: 03ff0663 beq t5,t6,80000040 <write_tohost>
80000018: 00b00f93 li t6,11
8000001c: 03ff0263 beq t5,t6,80000040 <write_tohost>
80000020: 80000f17 auipc t5,0x80000
80000024: fe0f0f13 addi t5,t5,-32 # 0 <_start-0x80000000>
80000028: 000f0463 beqz t5,80000030 <trap_vector+0x2c>
8000002c: 000f0067 jr t5
80000030: 34202f73 csrr t5,mcause
80000034: 000f5463 bgez t5,8000003c <handle_exception>
80000038: 0040006f j 8000003c <handle_exception>
8000003c <handle_exception>:
8000003c: 5391e193 ori gp,gp,1337
80000040 <write_tohost>:
80000040: 00001f17 auipc t5,0x1
80000044: fc3f2023 sw gp,-64(t5) # 80001000 <tohost>
80000048: ff9ff06f j 80000040 <write_tohost>
8000004c <reset_vector>:
8000004c: f1402573 csrr a0,mhartid
80000050: 00051063 bnez a0,80000050 <reset_vector+0x4>
80000054: 00000297 auipc t0,0x0
80000058: 01028293 addi t0,t0,16 # 80000064 <reset_vector+0x18>
8000005c: 30529073 csrw mtvec,t0
80000060: 18005073 csrwi satp,0
80000064: 00000297 auipc t0,0x0
80000068: 02028293 addi t0,t0,32 # 80000084 <reset_vector+0x38>
8000006c: 30529073 csrw mtvec,t0
80000070: 800002b7 lui t0,0x80000
80000074: fff28293 addi t0,t0,-1 # 7fffffff <_end+0xffffdff7>
80000078: 3b029073 csrw pmpaddr0,t0
8000007c: 01f00293 li t0,31
80000080: 3a029073 csrw pmpcfg0,t0
80000084: 00000297 auipc t0,0x0
80000088: 01828293 addi t0,t0,24 # 8000009c <reset_vector+0x50>
8000008c: 30529073 csrw mtvec,t0
80000090: 30205073 csrwi medeleg,0
80000094: 30305073 csrwi mideleg,0
80000098: 30405073 csrwi mie,0
8000009c: 00000193 li gp,0
800000a0: 00000297 auipc t0,0x0
800000a4: f6428293 addi t0,t0,-156 # 80000004 <trap_vector>
800000a8: 30529073 csrw mtvec,t0
800000ac: 00100513 li a0,1
800000b0: 01f51513 slli a0,a0,0x1f
800000b4: 00054863 bltz a0,800000c4 <reset_vector+0x78>
800000b8: 0ff0000f fence
800000bc: 00100193 li gp,1
800000c0: 00000073 ecall
800000c4: 80000297 auipc t0,0x80000
800000c8: f3c28293 addi t0,t0,-196 # 0 <_start-0x80000000>
800000cc: 00028e63 beqz t0,800000e8 <reset_ve
gitextract_wf1zodea/
├── .gitignore
├── .gitmodules
├── LICENSE
├── README.md
├── Tests/
│ ├── Makefile
│ ├── README.txt
│ ├── Run_regression.py
│ └── isa/
│ ├── rv32mi-p-breakpoint
│ ├── rv32mi-p-breakpoint.dump
│ ├── rv32mi-p-csr
│ ├── rv32mi-p-csr.dump
│ ├── rv32mi-p-illegal
│ ├── rv32mi-p-illegal.dump
│ ├── rv32mi-p-ma_addr
│ ├── rv32mi-p-ma_addr.dump
│ ├── rv32mi-p-ma_fetch
│ ├── rv32mi-p-ma_fetch.dump
│ ├── rv32mi-p-mcsr
│ ├── rv32mi-p-mcsr.dump
│ ├── rv32mi-p-sbreak
│ ├── rv32mi-p-sbreak.dump
│ ├── rv32mi-p-scall
│ ├── rv32mi-p-scall.dump
│ ├── rv32mi-p-shamt
│ ├── rv32mi-p-shamt.dump
│ ├── rv32si-p-csr
│ ├── rv32si-p-csr.dump
│ ├── rv32si-p-dirty
│ ├── rv32si-p-dirty.dump
│ ├── rv32si-p-ma_fetch
│ ├── rv32si-p-ma_fetch.dump
│ ├── rv32si-p-sbreak
│ ├── rv32si-p-sbreak.dump
│ ├── rv32si-p-scall
│ ├── rv32si-p-scall.dump
│ ├── rv32si-p-wfi
│ ├── rv32si-p-wfi.dump
│ ├── rv32ua-p-amoadd_w
│ ├── rv32ua-p-amoadd_w.dump
│ ├── rv32ua-p-amoand_w
│ ├── rv32ua-p-amoand_w.dump
│ ├── rv32ua-p-amomax_w
│ ├── rv32ua-p-amomax_w.dump
│ ├── rv32ua-p-amomaxu_w
│ ├── rv32ua-p-amomaxu_w.dump
│ ├── rv32ua-p-amomin_w
│ ├── rv32ua-p-amomin_w.dump
│ ├── rv32ua-p-amominu_w
│ ├── rv32ua-p-amominu_w.dump
│ ├── rv32ua-p-amoor_w
│ ├── rv32ua-p-amoor_w.dump
│ ├── rv32ua-p-amoswap_w
│ ├── rv32ua-p-amoswap_w.dump
│ ├── rv32ua-p-amoxor_w
│ ├── rv32ua-p-amoxor_w.dump
│ ├── rv32ua-p-lrsc
│ ├── rv32ua-p-lrsc.dump
│ ├── rv32ua-v-amoadd_w
│ ├── rv32ua-v-amoadd_w.dump
│ ├── rv32ua-v-amoand_w
│ ├── rv32ua-v-amoand_w.dump
│ ├── rv32ua-v-amomax_w
│ ├── rv32ua-v-amomax_w.dump
│ ├── rv32ua-v-amomaxu_w
│ ├── rv32ua-v-amomaxu_w.dump
│ ├── rv32ua-v-amomin_w
│ ├── rv32ua-v-amomin_w.dump
│ ├── rv32ua-v-amominu_w
│ ├── rv32ua-v-amominu_w.dump
│ ├── rv32ua-v-amoor_w
│ ├── rv32ua-v-amoor_w.dump
│ ├── rv32ua-v-amoswap_w
│ ├── rv32ua-v-amoswap_w.dump
│ ├── rv32ua-v-amoxor_w
│ ├── rv32ua-v-amoxor_w.dump
│ ├── rv32ua-v-lrsc
│ ├── rv32ua-v-lrsc.dump
│ ├── rv32uc-p-rvc
│ ├── rv32uc-p-rvc.dump
│ ├── rv32uc-v-rvc
│ ├── rv32uc-v-rvc.dump
│ ├── rv32ud-p-fadd
│ ├── rv32ud-p-fadd.dump
│ ├── rv32ud-p-fclass
│ ├── rv32ud-p-fclass.dump
│ ├── rv32ud-p-fcmp
│ ├── rv32ud-p-fcmp.dump
│ ├── rv32ud-p-fcvt
│ ├── rv32ud-p-fcvt.dump
│ ├── rv32ud-p-fcvt_w
│ ├── rv32ud-p-fcvt_w.dump
│ ├── rv32ud-p-fdiv
│ ├── rv32ud-p-fdiv.dump
│ ├── rv32ud-p-fmadd
│ ├── rv32ud-p-fmadd.dump
│ ├── rv32ud-p-fmin
│ ├── rv32ud-p-fmin.dump
│ ├── rv32ud-p-ldst
│ ├── rv32ud-p-ldst.dump
│ ├── rv32ud-p-recoding
│ ├── rv32ud-p-recoding.dump
│ ├── rv32ud-v-fadd
│ ├── rv32ud-v-fadd.dump
│ ├── rv32ud-v-fclass
│ ├── rv32ud-v-fclass.dump
│ ├── rv32ud-v-fcmp
│ ├── rv32ud-v-fcmp.dump
│ ├── rv32ud-v-fcvt
│ ├── rv32ud-v-fcvt.dump
│ ├── rv32ud-v-fcvt_w
│ ├── rv32ud-v-fcvt_w.dump
│ ├── rv32ud-v-fdiv
│ ├── rv32ud-v-fdiv.dump
│ ├── rv32ud-v-fmadd
│ ├── rv32ud-v-fmadd.dump
│ ├── rv32ud-v-fmin
│ ├── rv32ud-v-fmin.dump
│ ├── rv32ud-v-ldst
│ ├── rv32ud-v-ldst.dump
│ ├── rv32ud-v-recoding
│ ├── rv32ud-v-recoding.dump
│ ├── rv32uf-p-fadd
│ ├── rv32uf-p-fadd.dump
│ ├── rv32uf-p-fclass
│ ├── rv32uf-p-fclass.dump
│ ├── rv32uf-p-fcmp
│ ├── rv32uf-p-fcmp.dump
│ ├── rv32uf-p-fcvt
│ ├── rv32uf-p-fcvt.dump
│ ├── rv32uf-p-fcvt_w
│ ├── rv32uf-p-fcvt_w.dump
│ ├── rv32uf-p-fdiv
│ ├── rv32uf-p-fdiv.dump
│ ├── rv32uf-p-fmadd
│ ├── rv32uf-p-fmadd.dump
│ ├── rv32uf-p-fmin
│ ├── rv32uf-p-fmin.dump
│ ├── rv32uf-p-ldst
│ ├── rv32uf-p-ldst.dump
│ ├── rv32uf-p-move
│ ├── rv32uf-p-move.dump
│ ├── rv32uf-p-recoding
│ ├── rv32uf-p-recoding.dump
│ ├── rv32uf-v-fadd
│ ├── rv32uf-v-fadd.dump
│ ├── rv32uf-v-fclass
│ ├── rv32uf-v-fclass.dump
│ ├── rv32uf-v-fcmp
│ ├── rv32uf-v-fcmp.dump
│ ├── rv32uf-v-fcvt
│ ├── rv32uf-v-fcvt.dump
│ ├── rv32uf-v-fcvt_w
│ ├── rv32uf-v-fcvt_w.dump
│ ├── rv32uf-v-fdiv
│ ├── rv32uf-v-fdiv.dump
│ ├── rv32uf-v-fmadd
│ ├── rv32uf-v-fmadd.dump
│ ├── rv32uf-v-fmin
│ ├── rv32uf-v-fmin.dump
│ ├── rv32uf-v-ldst
│ ├── rv32uf-v-ldst.dump
│ ├── rv32uf-v-move
│ ├── rv32uf-v-move.dump
│ ├── rv32uf-v-recoding
│ ├── rv32uf-v-recoding.dump
│ ├── rv32ui-p-add
│ ├── rv32ui-p-add.dump
│ ├── rv32ui-p-addi
│ ├── rv32ui-p-addi.dump
│ ├── rv32ui-p-and
│ ├── rv32ui-p-and.dump
│ ├── rv32ui-p-andi
│ ├── rv32ui-p-andi.dump
│ ├── rv32ui-p-auipc
│ ├── rv32ui-p-auipc.dump
│ ├── rv32ui-p-beq
│ ├── rv32ui-p-beq.dump
│ ├── rv32ui-p-bge
│ ├── rv32ui-p-bge.dump
│ ├── rv32ui-p-bgeu
│ ├── rv32ui-p-bgeu.dump
│ ├── rv32ui-p-blt
│ ├── rv32ui-p-blt.dump
│ ├── rv32ui-p-bltu
│ ├── rv32ui-p-bltu.dump
│ ├── rv32ui-p-bne
│ ├── rv32ui-p-bne.dump
│ ├── rv32ui-p-fence_i
│ ├── rv32ui-p-fence_i.dump
│ ├── rv32ui-p-jal
│ ├── rv32ui-p-jal.dump
│ ├── rv32ui-p-jalr
│ ├── rv32ui-p-jalr.dump
│ ├── rv32ui-p-lb
│ ├── rv32ui-p-lb.dump
│ ├── rv32ui-p-lbu
│ ├── rv32ui-p-lbu.dump
│ ├── rv32ui-p-lh
│ ├── rv32ui-p-lh.dump
│ ├── rv32ui-p-lhu
│ ├── rv32ui-p-lhu.dump
│ ├── rv32ui-p-lui
│ ├── rv32ui-p-lui.dump
│ ├── rv32ui-p-lw
│ ├── rv32ui-p-lw.dump
│ ├── rv32ui-p-or
│ ├── rv32ui-p-or.dump
│ ├── rv32ui-p-ori
│ ├── rv32ui-p-ori.dump
│ ├── rv32ui-p-sb
│ ├── rv32ui-p-sb.dump
│ ├── rv32ui-p-sh
│ ├── rv32ui-p-sh.dump
│ ├── rv32ui-p-simple
│ ├── rv32ui-p-simple.dump
│ ├── rv32ui-p-sll
│ ├── rv32ui-p-sll.dump
│ ├── rv32ui-p-slli
│ ├── rv32ui-p-slli.dump
│ ├── rv32ui-p-slt
│ ├── rv32ui-p-slt.dump
│ ├── rv32ui-p-slti
│ ├── rv32ui-p-slti.dump
│ ├── rv32ui-p-sltiu
│ ├── rv32ui-p-sltiu.dump
│ ├── rv32ui-p-sltu
│ ├── rv32ui-p-sltu.dump
│ ├── rv32ui-p-sra
│ ├── rv32ui-p-sra.dump
│ ├── rv32ui-p-srai
│ ├── rv32ui-p-srai.dump
│ ├── rv32ui-p-srl
│ ├── rv32ui-p-srl.dump
│ ├── rv32ui-p-srli
│ ├── rv32ui-p-srli.dump
│ ├── rv32ui-p-sub
│ ├── rv32ui-p-sub.dump
│ ├── rv32ui-p-sw
│ ├── rv32ui-p-sw.dump
│ ├── rv32ui-p-xor
│ ├── rv32ui-p-xor.dump
│ ├── rv32ui-p-xori
│ ├── rv32ui-p-xori.dump
│ ├── rv32ui-v-add
│ ├── rv32ui-v-add.dump
│ ├── rv32ui-v-addi
│ ├── rv32ui-v-addi.dump
│ ├── rv32ui-v-and
│ ├── rv32ui-v-and.dump
│ ├── rv32ui-v-andi
│ ├── rv32ui-v-andi.dump
│ ├── rv32ui-v-auipc
│ ├── rv32ui-v-auipc.dump
│ ├── rv32ui-v-beq
│ ├── rv32ui-v-beq.dump
│ ├── rv32ui-v-bge
│ ├── rv32ui-v-bge.dump
│ ├── rv32ui-v-bgeu
│ ├── rv32ui-v-bgeu.dump
│ ├── rv32ui-v-blt
│ ├── rv32ui-v-blt.dump
│ ├── rv32ui-v-bltu
│ ├── rv32ui-v-bltu.dump
│ ├── rv32ui-v-bne
│ ├── rv32ui-v-bne.dump
│ ├── rv32ui-v-fence_i
│ ├── rv32ui-v-fence_i.dump
│ ├── rv32ui-v-jal
│ ├── rv32ui-v-jal.dump
│ ├── rv32ui-v-jalr
│ ├── rv32ui-v-jalr.dump
│ ├── rv32ui-v-lb
│ ├── rv32ui-v-lb.dump
│ ├── rv32ui-v-lbu
│ ├── rv32ui-v-lbu.dump
│ ├── rv32ui-v-lh
│ ├── rv32ui-v-lh.dump
│ ├── rv32ui-v-lhu
│ ├── rv32ui-v-lhu.dump
│ ├── rv32ui-v-lui
│ ├── rv32ui-v-lui.dump
│ ├── rv32ui-v-lw
│ ├── rv32ui-v-lw.dump
│ ├── rv32ui-v-or
│ ├── rv32ui-v-or.dump
│ ├── rv32ui-v-ori
│ ├── rv32ui-v-ori.dump
│ ├── rv32ui-v-sb
│ ├── rv32ui-v-sb.dump
│ ├── rv32ui-v-sh
│ ├── rv32ui-v-sh.dump
│ ├── rv32ui-v-simple
│ ├── rv32ui-v-simple.dump
│ ├── rv32ui-v-sll
│ ├── rv32ui-v-sll.dump
│ ├── rv32ui-v-slli
│ ├── rv32ui-v-slli.dump
│ ├── rv32ui-v-slt
│ ├── rv32ui-v-slt.dump
│ ├── rv32ui-v-slti
│ ├── rv32ui-v-slti.dump
│ ├── rv32ui-v-sltiu
│ ├── rv32ui-v-sltiu.dump
│ ├── rv32ui-v-sltu
│ ├── rv32ui-v-sltu.dump
│ ├── rv32ui-v-sra
│ ├── rv32ui-v-sra.dump
│ ├── rv32ui-v-srai
│ ├── rv32ui-v-srai.dump
│ ├── rv32ui-v-srl
│ ├── rv32ui-v-srl.dump
│ ├── rv32ui-v-srli
│ ├── rv32ui-v-srli.dump
│ ├── rv32ui-v-sub
│ ├── rv32ui-v-sub.dump
│ ├── rv32ui-v-sw
│ ├── rv32ui-v-sw.dump
│ ├── rv32ui-v-xor
│ ├── rv32ui-v-xor.dump
│ ├── rv32ui-v-xori
│ ├── rv32ui-v-xori.dump
│ ├── rv32um-p-div
│ ├── rv32um-p-div.dump
│ ├── rv32um-p-divu
│ ├── rv32um-p-divu.dump
│ ├── rv32um-p-mul
│ ├── rv32um-p-mul.dump
│ ├── rv32um-p-mulh
│ ├── rv32um-p-mulh.dump
│ ├── rv32um-p-mulhsu
│ ├── rv32um-p-mulhsu.dump
│ ├── rv32um-p-mulhu
│ ├── rv32um-p-mulhu.dump
│ ├── rv32um-p-rem
│ ├── rv32um-p-rem.dump
│ ├── rv32um-p-remu
│ ├── rv32um-p-remu.dump
│ ├── rv32um-v-div
│ ├── rv32um-v-div.dump
│ ├── rv32um-v-divu
│ ├── rv32um-v-divu.dump
│ ├── rv32um-v-mul
│ ├── rv32um-v-mul.dump
│ ├── rv32um-v-mulh
│ ├── rv32um-v-mulh.dump
│ ├── rv32um-v-mulhsu
│ ├── rv32um-v-mulhsu.dump
│ ├── rv32um-v-mulhu
│ ├── rv32um-v-mulhu.dump
│ ├── rv32um-v-rem
│ ├── rv32um-v-rem.dump
│ ├── rv32um-v-remu
│ ├── rv32um-v-remu.dump
│ ├── rv64mi-p-access
│ ├── rv64mi-p-access.dump
│ ├── rv64mi-p-breakpoint
│ ├── rv64mi-p-breakpoint.dump
│ ├── rv64mi-p-csr
│ ├── rv64mi-p-csr.dump
│ ├── rv64mi-p-illegal
│ ├── rv64mi-p-illegal.dump
│ ├── rv64mi-p-ma_addr
│ ├── rv64mi-p-ma_addr.dump
│ ├── rv64mi-p-ma_fetch
│ ├── rv64mi-p-ma_fetch.dump
│ ├── rv64mi-p-mcsr
│ ├── rv64mi-p-mcsr.dump
│ ├── rv64mi-p-sbreak
│ ├── rv64mi-p-sbreak.dump
│ ├── rv64mi-p-scall
│ ├── rv64mi-p-scall.dump
│ ├── rv64si-p-csr
│ ├── rv64si-p-csr.dump
│ ├── rv64si-p-dirty
│ ├── rv64si-p-dirty.dump
│ ├── rv64si-p-ma_fetch
│ ├── rv64si-p-ma_fetch.dump
│ ├── rv64si-p-sbreak
│ ├── rv64si-p-sbreak.dump
│ ├── rv64si-p-scall
│ ├── rv64si-p-scall.dump
│ ├── rv64si-p-wfi
│ ├── rv64si-p-wfi.dump
│ ├── rv64ua-p-amoadd_d
│ ├── rv64ua-p-amoadd_d.dump
│ ├── rv64ua-p-amoadd_w
│ ├── rv64ua-p-amoadd_w.dump
│ ├── rv64ua-p-amoand_d
│ ├── rv64ua-p-amoand_d.dump
│ ├── rv64ua-p-amoand_w
│ ├── rv64ua-p-amoand_w.dump
│ ├── rv64ua-p-amomax_d
│ ├── rv64ua-p-amomax_d.dump
│ ├── rv64ua-p-amomax_w
│ ├── rv64ua-p-amomax_w.dump
│ ├── rv64ua-p-amomaxu_d
│ ├── rv64ua-p-amomaxu_d.dump
│ ├── rv64ua-p-amomaxu_w
│ ├── rv64ua-p-amomaxu_w.dump
│ ├── rv64ua-p-amomin_d
│ ├── rv64ua-p-amomin_d.dump
│ ├── rv64ua-p-amomin_w
│ ├── rv64ua-p-amomin_w.dump
│ ├── rv64ua-p-amominu_d
│ ├── rv64ua-p-amominu_d.dump
│ ├── rv64ua-p-amominu_w
│ ├── rv64ua-p-amominu_w.dump
│ ├── rv64ua-p-amoor_d
│ ├── rv64ua-p-amoor_d.dump
│ ├── rv64ua-p-amoor_w
│ ├── rv64ua-p-amoor_w.dump
│ ├── rv64ua-p-amoswap_d
│ ├── rv64ua-p-amoswap_d.dump
│ ├── rv64ua-p-amoswap_w
│ ├── rv64ua-p-amoswap_w.dump
│ ├── rv64ua-p-amoxor_d
│ ├── rv64ua-p-amoxor_d.dump
│ ├── rv64ua-p-amoxor_w
│ ├── rv64ua-p-amoxor_w.dump
│ ├── rv64ua-p-lrsc
│ ├── rv64ua-p-lrsc.dump
│ ├── rv64ua-v-amoadd_d
│ ├── rv64ua-v-amoadd_d.dump
│ ├── rv64ua-v-amoadd_w
│ ├── rv64ua-v-amoadd_w.dump
│ ├── rv64ua-v-amoand_d
│ ├── rv64ua-v-amoand_d.dump
│ ├── rv64ua-v-amoand_w
│ ├── rv64ua-v-amoand_w.dump
│ ├── rv64ua-v-amomax_d
│ ├── rv64ua-v-amomax_d.dump
│ ├── rv64ua-v-amomax_w
│ ├── rv64ua-v-amomax_w.dump
│ ├── rv64ua-v-amomaxu_d
│ ├── rv64ua-v-amomaxu_d.dump
│ ├── rv64ua-v-amomaxu_w
│ ├── rv64ua-v-amomaxu_w.dump
│ ├── rv64ua-v-amomin_d
│ ├── rv64ua-v-amomin_d.dump
│ ├── rv64ua-v-amomin_w
│ ├── rv64ua-v-amomin_w.dump
│ ├── rv64ua-v-amominu_d
│ ├── rv64ua-v-amominu_d.dump
│ ├── rv64ua-v-amominu_w
│ ├── rv64ua-v-amominu_w.dump
│ ├── rv64ua-v-amoor_d
│ ├── rv64ua-v-amoor_d.dump
│ ├── rv64ua-v-amoor_w
│ ├── rv64ua-v-amoor_w.dump
│ ├── rv64ua-v-amoswap_d
│ ├── rv64ua-v-amoswap_d.dump
│ ├── rv64ua-v-amoswap_w
│ ├── rv64ua-v-amoswap_w.dump
│ ├── rv64ua-v-amoxor_d
│ ├── rv64ua-v-amoxor_d.dump
│ ├── rv64ua-v-amoxor_w
│ ├── rv64ua-v-amoxor_w.dump
│ ├── rv64ua-v-lrsc
│ ├── rv64ua-v-lrsc.dump
│ ├── rv64uc-p-rvc
│ ├── rv64uc-p-rvc.dump
│ ├── rv64uc-v-rvc
│ ├── rv64uc-v-rvc.dump
│ ├── rv64ud-p-fadd
│ ├── rv64ud-p-fadd.dump
│ ├── rv64ud-p-fclass
│ ├── rv64ud-p-fclass.dump
│ ├── rv64ud-p-fcmp
│ ├── rv64ud-p-fcmp.dump
│ ├── rv64ud-p-fcvt
│ ├── rv64ud-p-fcvt.dump
│ ├── rv64ud-p-fcvt_w
│ ├── rv64ud-p-fcvt_w.dump
│ ├── rv64ud-p-fdiv
│ ├── rv64ud-p-fdiv.dump
│ ├── rv64ud-p-fmadd
│ ├── rv64ud-p-fmadd.dump
│ ├── rv64ud-p-fmin
│ ├── rv64ud-p-fmin.dump
│ ├── rv64ud-p-ldst
│ ├── rv64ud-p-ldst.dump
│ ├── rv64ud-p-move
│ ├── rv64ud-p-move.dump
│ ├── rv64ud-p-recoding
│ ├── rv64ud-p-recoding.dump
│ ├── rv64ud-p-structural
│ ├── rv64ud-p-structural.dump
│ ├── rv64ud-v-fadd
│ ├── rv64ud-v-fadd.dump
│ ├── rv64ud-v-fclass
│ ├── rv64ud-v-fclass.dump
│ ├── rv64ud-v-fcmp
│ ├── rv64ud-v-fcmp.dump
│ ├── rv64ud-v-fcvt
│ ├── rv64ud-v-fcvt.dump
│ ├── rv64ud-v-fcvt_w
│ ├── rv64ud-v-fcvt_w.dump
│ ├── rv64ud-v-fdiv
│ ├── rv64ud-v-fdiv.dump
│ ├── rv64ud-v-fmadd
│ ├── rv64ud-v-fmadd.dump
│ ├── rv64ud-v-fmin
│ ├── rv64ud-v-fmin.dump
│ ├── rv64ud-v-ldst
│ ├── rv64ud-v-ldst.dump
│ ├── rv64ud-v-move
│ ├── rv64ud-v-move.dump
│ ├── rv64ud-v-recoding
│ ├── rv64ud-v-recoding.dump
│ ├── rv64ud-v-structural
│ ├── rv64ud-v-structural.dump
│ ├── rv64uf-p-fadd
│ ├── rv64uf-p-fadd.dump
│ ├── rv64uf-p-fclass
│ ├── rv64uf-p-fclass.dump
│ ├── rv64uf-p-fcmp
│ ├── rv64uf-p-fcmp.dump
│ ├── rv64uf-p-fcvt
│ ├── rv64uf-p-fcvt.dump
│ ├── rv64uf-p-fcvt_w
│ ├── rv64uf-p-fcvt_w.dump
│ ├── rv64uf-p-fdiv
│ ├── rv64uf-p-fdiv.dump
│ ├── rv64uf-p-fmadd
│ ├── rv64uf-p-fmadd.dump
│ ├── rv64uf-p-fmin
│ ├── rv64uf-p-fmin.dump
│ ├── rv64uf-p-ldst
│ ├── rv64uf-p-ldst.dump
│ ├── rv64uf-p-move
│ ├── rv64uf-p-move.dump
│ ├── rv64uf-p-recoding
│ ├── rv64uf-p-recoding.dump
│ ├── rv64uf-v-fadd
│ ├── rv64uf-v-fadd.dump
│ ├── rv64uf-v-fclass
│ ├── rv64uf-v-fclass.dump
│ ├── rv64uf-v-fcmp
│ ├── rv64uf-v-fcmp.dump
│ ├── rv64uf-v-fcvt
│ ├── rv64uf-v-fcvt.dump
│ ├── rv64uf-v-fcvt_w
│ ├── rv64uf-v-fcvt_w.dump
│ ├── rv64uf-v-fdiv
│ ├── rv64uf-v-fdiv.dump
│ ├── rv64uf-v-fmadd
│ ├── rv64uf-v-fmadd.dump
│ ├── rv64uf-v-fmin
│ ├── rv64uf-v-fmin.dump
│ ├── rv64uf-v-ldst
│ ├── rv64uf-v-ldst.dump
│ ├── rv64uf-v-move
│ ├── rv64uf-v-move.dump
│ ├── rv64uf-v-recoding
│ ├── rv64uf-v-recoding.dump
│ ├── rv64ui-p-add
│ ├── rv64ui-p-add.dump
│ ├── rv64ui-p-addi
│ ├── rv64ui-p-addi.dump
│ ├── rv64ui-p-addiw
│ ├── rv64ui-p-addiw.dump
│ ├── rv64ui-p-addw
│ ├── rv64ui-p-addw.dump
│ ├── rv64ui-p-and
│ ├── rv64ui-p-and.dump
│ ├── rv64ui-p-andi
│ ├── rv64ui-p-andi.dump
│ ├── rv64ui-p-auipc
│ ├── rv64ui-p-auipc.dump
│ ├── rv64ui-p-beq
│ ├── rv64ui-p-beq.dump
│ ├── rv64ui-p-bge
│ ├── rv64ui-p-bge.dump
│ ├── rv64ui-p-bgeu
│ ├── rv64ui-p-bgeu.dump
│ ├── rv64ui-p-blt
│ ├── rv64ui-p-blt.dump
│ ├── rv64ui-p-bltu
│ ├── rv64ui-p-bltu.dump
│ ├── rv64ui-p-bne
│ ├── rv64ui-p-bne.dump
│ ├── rv64ui-p-fence_i
│ ├── rv64ui-p-fence_i.dump
│ ├── rv64ui-p-jal
│ ├── rv64ui-p-jal.dump
│ ├── rv64ui-p-jalr
│ ├── rv64ui-p-jalr.dump
│ ├── rv64ui-p-lb
│ ├── rv64ui-p-lb.dump
│ ├── rv64ui-p-lbu
│ ├── rv64ui-p-lbu.dump
│ ├── rv64ui-p-ld
│ ├── rv64ui-p-ld.dump
│ ├── rv64ui-p-lh
│ ├── rv64ui-p-lh.dump
│ ├── rv64ui-p-lhu
│ ├── rv64ui-p-lhu.dump
│ ├── rv64ui-p-lui
│ ├── rv64ui-p-lui.dump
│ ├── rv64ui-p-lw
│ ├── rv64ui-p-lw.dump
│ ├── rv64ui-p-lwu
│ ├── rv64ui-p-lwu.dump
│ ├── rv64ui-p-or
│ ├── rv64ui-p-or.dump
│ ├── rv64ui-p-ori
│ ├── rv64ui-p-ori.dump
│ ├── rv64ui-p-sb
│ ├── rv64ui-p-sb.dump
│ ├── rv64ui-p-sd
│ ├── rv64ui-p-sd.dump
│ ├── rv64ui-p-sh
│ ├── rv64ui-p-sh.dump
│ ├── rv64ui-p-simple
│ ├── rv64ui-p-simple.dump
│ ├── rv64ui-p-sll
│ ├── rv64ui-p-sll.dump
│ ├── rv64ui-p-slli
│ ├── rv64ui-p-slli.dump
│ ├── rv64ui-p-slliw
│ ├── rv64ui-p-slliw.dump
│ ├── rv64ui-p-sllw
│ ├── rv64ui-p-sllw.dump
│ ├── rv64ui-p-slt
│ ├── rv64ui-p-slt.dump
│ ├── rv64ui-p-slti
│ ├── rv64ui-p-slti.dump
│ ├── rv64ui-p-sltiu
│ ├── rv64ui-p-sltiu.dump
│ ├── rv64ui-p-sltu
│ ├── rv64ui-p-sltu.dump
│ ├── rv64ui-p-sra
│ ├── rv64ui-p-sra.dump
│ ├── rv64ui-p-srai
│ ├── rv64ui-p-srai.dump
│ ├── rv64ui-p-sraiw
│ ├── rv64ui-p-sraiw.dump
│ ├── rv64ui-p-sraw
│ ├── rv64ui-p-sraw.dump
│ ├── rv64ui-p-srl
│ ├── rv64ui-p-srl.dump
│ ├── rv64ui-p-srli
│ ├── rv64ui-p-srli.dump
│ ├── rv64ui-p-srliw
│ ├── rv64ui-p-srliw.dump
│ ├── rv64ui-p-srlw
│ ├── rv64ui-p-srlw.dump
│ ├── rv64ui-p-sub
│ ├── rv64ui-p-sub.dump
│ ├── rv64ui-p-subw
│ ├── rv64ui-p-subw.dump
│ ├── rv64ui-p-sw
│ ├── rv64ui-p-sw.dump
│ ├── rv64ui-p-xor
│ ├── rv64ui-p-xor.dump
│ ├── rv64ui-p-xori
│ ├── rv64ui-p-xori.dump
│ ├── rv64ui-v-add
│ ├── rv64ui-v-add.dump
│ ├── rv64ui-v-addi
│ ├── rv64ui-v-addi.dump
│ ├── rv64ui-v-addiw
│ ├── rv64ui-v-addiw.dump
│ ├── rv64ui-v-addw
│ ├── rv64ui-v-addw.dump
│ ├── rv64ui-v-and
│ ├── rv64ui-v-and.dump
│ ├── rv64ui-v-andi
│ ├── rv64ui-v-andi.dump
│ ├── rv64ui-v-auipc
│ ├── rv64ui-v-auipc.dump
│ ├── rv64ui-v-beq
│ ├── rv64ui-v-beq.dump
│ ├── rv64ui-v-bge
│ ├── rv64ui-v-bge.dump
│ ├── rv64ui-v-bgeu
│ ├── rv64ui-v-bgeu.dump
│ ├── rv64ui-v-blt
│ ├── rv64ui-v-blt.dump
│ ├── rv64ui-v-bltu
│ ├── rv64ui-v-bltu.dump
│ ├── rv64ui-v-bne
│ ├── rv64ui-v-bne.dump
│ ├── rv64ui-v-fence_i
│ ├── rv64ui-v-fence_i.dump
│ ├── rv64ui-v-jal
│ ├── rv64ui-v-jal.dump
│ ├── rv64ui-v-jalr
│ ├── rv64ui-v-jalr.dump
│ ├── rv64ui-v-lb
│ ├── rv64ui-v-lb.dump
│ ├── rv64ui-v-lbu
│ ├── rv64ui-v-lbu.dump
│ ├── rv64ui-v-ld
│ ├── rv64ui-v-ld.dump
│ ├── rv64ui-v-lh
│ ├── rv64ui-v-lh.dump
│ ├── rv64ui-v-lhu
│ ├── rv64ui-v-lhu.dump
│ ├── rv64ui-v-lui
│ ├── rv64ui-v-lui.dump
│ ├── rv64ui-v-lw
│ ├── rv64ui-v-lw.dump
│ ├── rv64ui-v-lwu
│ ├── rv64ui-v-lwu.dump
│ ├── rv64ui-v-or
│ ├── rv64ui-v-or.dump
│ ├── rv64ui-v-ori
│ ├── rv64ui-v-ori.dump
│ ├── rv64ui-v-sb
│ ├── rv64ui-v-sb.dump
│ ├── rv64ui-v-sd
│ ├── rv64ui-v-sd.dump
│ ├── rv64ui-v-sh
│ ├── rv64ui-v-sh.dump
│ ├── rv64ui-v-simple
│ ├── rv64ui-v-simple.dump
│ ├── rv64ui-v-sll
│ ├── rv64ui-v-sll.dump
│ ├── rv64ui-v-slli
│ ├── rv64ui-v-slli.dump
│ ├── rv64ui-v-slliw
│ ├── rv64ui-v-slliw.dump
│ ├── rv64ui-v-sllw
│ ├── rv64ui-v-sllw.dump
│ ├── rv64ui-v-slt
│ ├── rv64ui-v-slt.dump
│ ├── rv64ui-v-slti
│ ├── rv64ui-v-slti.dump
│ ├── rv64ui-v-sltiu
│ ├── rv64ui-v-sltiu.dump
│ ├── rv64ui-v-sltu
│ ├── rv64ui-v-sltu.dump
│ ├── rv64ui-v-sra
│ ├── rv64ui-v-sra.dump
│ ├── rv64ui-v-srai
│ ├── rv64ui-v-srai.dump
│ ├── rv64ui-v-sraiw
│ ├── rv64ui-v-sraiw.dump
│ ├── rv64ui-v-sraw
│ ├── rv64ui-v-sraw.dump
│ ├── rv64ui-v-srl
│ ├── rv64ui-v-srl.dump
│ ├── rv64ui-v-srli
│ ├── rv64ui-v-srli.dump
│ ├── rv64ui-v-srliw
│ ├── rv64ui-v-srliw.dump
│ ├── rv64ui-v-srlw
│ ├── rv64ui-v-srlw.dump
│ ├── rv64ui-v-sub
│ ├── rv64ui-v-sub.dump
│ ├── rv64ui-v-subw
│ ├── rv64ui-v-subw.dump
│ ├── rv64ui-v-sw
│ ├── rv64ui-v-sw.dump
│ ├── rv64ui-v-xor
│ ├── rv64ui-v-xor.dump
│ ├── rv64ui-v-xori
│ ├── rv64ui-v-xori.dump
│ ├── rv64um-p-div
│ ├── rv64um-p-div.dump
│ ├── rv64um-p-divu
│ ├── rv64um-p-divu.dump
│ ├── rv64um-p-divuw
│ ├── rv64um-p-divuw.dump
│ ├── rv64um-p-divw
│ ├── rv64um-p-divw.dump
│ ├── rv64um-p-mul
│ ├── rv64um-p-mul.dump
│ ├── rv64um-p-mulh
│ ├── rv64um-p-mulh.dump
│ ├── rv64um-p-mulhsu
│ ├── rv64um-p-mulhsu.dump
│ ├── rv64um-p-mulhu
│ ├── rv64um-p-mulhu.dump
│ ├── rv64um-p-mulw
│ ├── rv64um-p-mulw.dump
│ ├── rv64um-p-rem
│ ├── rv64um-p-rem.dump
│ ├── rv64um-p-remu
│ ├── rv64um-p-remu.dump
│ ├── rv64um-p-remuw
│ ├── rv64um-p-remuw.dump
│ ├── rv64um-p-remw
│ ├── rv64um-p-remw.dump
│ ├── rv64um-v-div
│ ├── rv64um-v-div.dump
│ ├── rv64um-v-divu
│ ├── rv64um-v-divu.dump
│ ├── rv64um-v-divuw
│ ├── rv64um-v-divuw.dump
│ ├── rv64um-v-divw
│ ├── rv64um-v-divw.dump
│ ├── rv64um-v-mul
│ ├── rv64um-v-mul.dump
│ ├── rv64um-v-mulh
│ ├── rv64um-v-mulh.dump
│ ├── rv64um-v-mulhsu
│ ├── rv64um-v-mulhsu.dump
│ ├── rv64um-v-mulhu
│ ├── rv64um-v-mulhu.dump
│ ├── rv64um-v-mulw
│ ├── rv64um-v-mulw.dump
│ ├── rv64um-v-rem
│ ├── rv64um-v-rem.dump
│ ├── rv64um-v-remu
│ ├── rv64um-v-remu.dump
│ ├── rv64um-v-remuw
│ ├── rv64um-v-remuw.dump
│ ├── rv64um-v-remw
│ └── rv64um-v-remw.dump
├── builds/
│ ├── RV64ACDFIMSU_Toooba_bluesim/
│ │ └── Makefile
│ ├── RV64ACDFIMSU_Toooba_verilator/
│ │ ├── Makefile
│ │ └── Verilog_RTL/
│ │ ├── mkAXI4_Deburster_A.v
│ │ ├── mkAluDispToRegFifo.v
│ │ ├── mkAluExeToFinFifo.v
│ │ ├── mkAluRegToExeFifo.v
│ │ ├── mkBht.v
│ │ ├── mkBoot_ROM.v
│ │ ├── mkCore.v
│ │ ├── mkCoreW.v
│ │ ├── mkDCRqMshrWrapper.v
│ │ ├── mkDPRqMshrWrapper.v
│ │ ├── mkDPipeline.v
│ │ ├── mkDTlbSynth.v
│ │ ├── mkDirPredictor.v
│ │ ├── mkDivExecQ.v
│ │ ├── mkDoubleDiv.v
│ │ ├── mkDoubleFMA.v
│ │ ├── mkDoubleSqrt.v
│ │ ├── mkDummyStoreBuffer.v
│ │ ├── mkEpochManager.v
│ │ ├── mkFabric.v
│ │ ├── mkFabric_2x3.v
│ │ ├── mkFabric_AXI4.v
│ │ ├── mkFetchStage.v
│ │ ├── mkFmaExecQ.v
│ │ ├── mkFpuMulDivDispToRegFifo.v
│ │ ├── mkFpuMulDivRegToExeFifo.v
│ │ ├── mkGSelectGHistReg.v
│ │ ├── mkGSelectPred.v
│ │ ├── mkGShareGHistReg.v
│ │ ├── mkGSharePred.v
│ │ ├── mkIBankWrapper.v
│ │ ├── mkICRqMshrWrapper.v
│ │ ├── mkICoCache.v
│ │ ├── mkIPRqMshrWrapper.v
│ │ ├── mkIPipeline.v
│ │ ├── mkITlb.v
│ │ ├── mkL2Tlb.v
│ │ ├── mkLLCache.v
│ │ ├── mkLLPipeline.v
│ │ ├── mkLSQIssueLdQ.v
│ │ ├── mkLastLvCRqMshr.v
│ │ ├── mkMMIOInst.v
│ │ ├── mkMemDispToRegFifo.v
│ │ ├── mkMemLoader.v
│ │ ├── mkMemRegToExeFifo.v
│ │ ├── mkMem_Controller.v
│ │ ├── mkMem_Model.v
│ │ ├── mkMinimumExecQ.v
│ │ ├── mkMulExecQ.v
│ │ ├── mkNullTransCache.v
│ │ ├── mkPLIC_16_2_7.v
│ │ ├── mkProc.v
│ │ ├── mkRFileSynth.v
│ │ ├── mkRas.v
│ │ ├── mkRegRenamingTable.v
│ │ ├── mkReorderBufferSynth.v
│ │ ├── mkReservationStationAlu.v
│ │ ├── mkReservationStationFpuMulDiv.v
│ │ ├── mkReservationStationMem.v
│ │ ├── mkRobRowSynth.v
│ │ ├── mkScoreboardAggr.v
│ │ ├── mkScoreboardCons.v
│ │ ├── mkSimpleRespQ.v
│ │ ├── mkSoC_Map.v
│ │ ├── mkSoC_Top.v
│ │ ├── mkSpecTagManager.v
│ │ ├── mkSplitLSQ.v
│ │ ├── mkSplitTransCache.v
│ │ ├── mkStoreBufferEhr.v
│ │ ├── mkSyncBramFifo_w36_d512.v
│ │ ├── mkSyncFifo_w32_d16.v
│ │ ├── mkTop_HW_Side.v
│ │ ├── mkTourGHistReg.v
│ │ ├── mkTourPred.v
│ │ ├── mkTourPredSecure.v
│ │ ├── mkUART.v
│ │ ├── mkXilinxFpDiv.v
│ │ ├── mkXilinxFpDivIP.v
│ │ ├── mkXilinxFpDivSim.v
│ │ ├── mkXilinxFpFma.v
│ │ ├── mkXilinxFpFmaIP.v
│ │ ├── mkXilinxFpFmaSim.v
│ │ ├── mkXilinxFpSqrt.v
│ │ ├── mkXilinxFpSqrtIP.v
│ │ ├── mkXilinxFpSqrtSim.v
│ │ ├── module_alu.v
│ │ ├── module_aluBr.v
│ │ ├── module_amoExec.v
│ │ ├── module_basicExec.v
│ │ ├── module_brAddrCalc.v
│ │ ├── module_checkForException.v
│ │ ├── module_decode.v
│ │ ├── module_decodeBrPred.v
│ │ ├── module_execFpuSimple.v
│ │ └── module_getControlFlow.v
│ └── Resources/
│ ├── Include_Common.mk
│ ├── Include_RISCY_Config.mk
│ ├── Include_bluesim.mk
│ ├── Include_verilator.mk
│ └── Verilator_resources/
│ ├── import_DPI_C_decls.v
│ ├── sed_script.txt
│ ├── sim_main.cpp
│ └── verilator_config.vlt
├── src_Core/
│ ├── BSV_Additional_Libs/
│ │ ├── AXI4_Stream.bsv
│ │ ├── ByteLane.bsv
│ │ ├── CreditCounter.bsv
│ │ ├── Cur_Cycle.bsv
│ │ ├── EdgeFIFOFs.bsv
│ │ ├── GetPut_Aux.bsv
│ │ └── Semi_FIFOF.bsv
│ ├── CPU/
│ │ ├── CPU_Decode_C.bsv
│ │ ├── Core.bsv
│ │ ├── CsrFile.bsv
│ │ ├── LLC_AXI4_Adapter.bsv
│ │ ├── MMIOPlatform.bsv
│ │ ├── MMIO_AXI4_Adapter.bsv
│ │ ├── Proc.bsv
│ │ └── Proc_IFC.bsv
│ ├── Core/
│ │ ├── CoreW.bsv
│ │ ├── CoreW_IFC.bsv
│ │ ├── Fabric_Defs.bsv
│ │ ├── TV_Encode.bsv
│ │ ├── TV_Taps.bsv
│ │ ├── Trace_Data2.bsv
│ │ └── Trace_Data2_to_Trace_Data.bsv
│ ├── Debug_Module/
│ │ ├── DM_Abstract_Commands.bsv
│ │ ├── DM_CPU_Req_Rsp.bsv
│ │ ├── DM_Common.bsv
│ │ ├── DM_Run_Control.bsv
│ │ ├── DM_System_Bus.bsv
│ │ ├── Debug_Module.bsv
│ │ ├── README.txt
│ │ └── Test/
│ │ ├── Makefile
│ │ └── Testbench.bsv
│ ├── ISA/
│ │ ├── ISA_Decls.bsv
│ │ ├── ISA_Decls_C.bsv
│ │ ├── ISA_Decls_Priv_M.bsv
│ │ ├── ISA_Decls_Priv_S.bsv
│ │ └── TV_Info.bsv
│ ├── PLIC/
│ │ ├── Makefile
│ │ ├── PLIC.bsv
│ │ ├── PLIC_16_CoreNumX2_7.bsv
│ │ ├── README_PLIC.txt
│ │ └── Test_PLIC.bsv
│ └── RISCY_OOO/
│ ├── LICENSE_RISCY-OOO
│ ├── Makefile
│ ├── coherence/
│ │ └── src/
│ │ ├── CCPipe.bsv
│ │ ├── CCTypes.bsv
│ │ ├── CrossBar.bsv
│ │ ├── IBank.bsv
│ │ ├── ICRqMshr.bsv
│ │ ├── IPRqMshr.bsv
│ │ ├── L1Bank.bsv
│ │ ├── L1CRqMshr.bsv
│ │ ├── L1PRqMshr.bsv
│ │ ├── L1Pipe.bsv
│ │ ├── LLBank.bsv
│ │ ├── LLCRqMshr.bsv
│ │ ├── LLPipe.bsv
│ │ ├── MshrDeadlockChecker.bsv
│ │ ├── Prefetcher.bsv
│ │ ├── RWBramCore.bsv
│ │ ├── RandomReplace.bsv
│ │ ├── SelfInvIBank.bsv
│ │ ├── SelfInvIPipe.bsv
│ │ ├── SelfInvL1Bank.bsv
│ │ ├── SelfInvL1Pipe.bsv
│ │ ├── SelfInvLLBank.bsv
│ │ └── SelfInvLLPipe.bsv
│ ├── connectal/
│ │ ├── bsv/
│ │ │ ├── ConnectalBramFifo.bsv
│ │ │ └── ConnectalClocks.bsv
│ │ ├── lib/
│ │ │ └── bsv/
│ │ │ └── Arith.bsv
│ │ └── tests/
│ │ └── spi/
│ │ └── ConnectalProjectConfig.bsv
│ ├── fpgautils/
│ │ ├── lib/
│ │ │ ├── DramCommon.bsv
│ │ │ ├── ResetGuard.bsv
│ │ │ ├── SyncFifo.bsv
│ │ │ ├── WaitAutoReset.bsv
│ │ │ ├── XilinxFpu.bsv
│ │ │ ├── XilinxIntDiv.bsv
│ │ │ ├── XilinxIntMul.bsv
│ │ │ └── XilinxSyncFifo.bsv
│ │ └── xilinx/
│ │ ├── fpu/
│ │ │ ├── fp_div_sim.v
│ │ │ ├── fp_fma_sim.v
│ │ │ └── fp_sqrt_sim.v
│ │ └── reset_regs/
│ │ └── reset_guard.v
│ └── procs/
│ ├── RV64G_OOO/
│ │ ├── AluExePipeline.bsv
│ │ ├── CommitStage.bsv
│ │ ├── FetchStage.bsv
│ │ ├── FpuMulDivExePipeline.bsv
│ │ ├── MemExePipeline.bsv
│ │ ├── ProcConfig.bsv
│ │ ├── RFileSynth.bsv
│ │ ├── RenameStage.bsv
│ │ ├── ReorderBufferSynth.bsv
│ │ ├── ReservationStationAlu.bsv
│ │ ├── ReservationStationFpuMulDiv.bsv
│ │ ├── ReservationStationMem.bsv
│ │ ├── ScoreboardSynth.bsv
│ │ └── SynthParam.bsv
│ └── lib/
│ ├── Amo.bsv
│ ├── Bht.bsv
│ ├── BrPred.bsv
│ ├── Btb.bsv
│ ├── Bypass.bsv
│ ├── CacheUtils.bsv
│ ├── ConcatReg.bsv
│ ├── DTlb.bsv
│ ├── Decode.bsv
│ ├── DirPredictor.bsv
│ ├── Ehr.bsv
│ ├── EpochManager.bsv
│ ├── Exec.bsv
│ ├── FP_Utils.bsv
│ ├── Fifos.bsv
│ ├── Fpu.bsv
│ ├── FullAssocTlb.bsv
│ ├── GSelectPred.bsv
│ ├── GSharePred.bsv
│ ├── GlobalBrHistReg.bsv
│ ├── GlobalSpecUpdate.bsv
│ ├── HasSpecBits.bsv
│ ├── ITlb.bsv
│ ├── IndexedMultiset.bsv
│ ├── L1CoCache.bsv
│ ├── L1LLConnect.bsv
│ ├── L2SetAssocTlb.bsv
│ ├── L2Tlb.bsv
│ ├── LLCDmaConnect.bsv
│ ├── LLCRqMshrSecureModel.bsv
│ ├── LLCache.bsv
│ ├── LatencyTimer.bsv
│ ├── MMIOAddrs.bsv
│ ├── MMIOCore.bsv
│ ├── MMIOInst.bsv
│ ├── Map.bsv
│ ├── MemLoader.bsv
│ ├── MemLoaderIF.bsv
│ ├── MemoryTypes.bsv
│ ├── MsgFifo.bsv
│ ├── MulDiv.bsv
│ ├── Performance.bsv
│ ├── PhysRFile.bsv
│ ├── ProcTypes.bsv
│ ├── Ras.bsv
│ ├── RenameDebugIF.bsv
│ ├── RenamingTable.bsv
│ ├── ReorderBuffer.bsv
│ ├── ReservationStationEhr.bsv
│ ├── SafeCounter.bsv
│ ├── Scoreboard.bsv
│ ├── SetAssocTlb.bsv
│ ├── SpecFifo.bsv
│ ├── SpecPoisonFifo.bsv
│ ├── SpecTagManager.bsv
│ ├── SplitLSQ.bsv
│ ├── StoreBuffer.bsv
│ ├── TlbConnect.bsv
│ ├── TlbTypes.bsv
│ ├── TourPred.bsv
│ ├── TourPredSecure.bsv
│ ├── TranslationCache.bsv
│ ├── Types.bsv
│ └── VerificationPacket.bsv
├── src_SSITH_P3/
│ ├── Makefile
│ ├── README.txt
│ ├── Verilog_RTL/
│ │ ├── mkAluDispToRegFifo.v
│ │ ├── mkAluExeToFinFifo.v
│ │ ├── mkAluRegToExeFifo.v
│ │ ├── mkBht.v
│ │ ├── mkCore.v
│ │ ├── mkCoreW.v
│ │ ├── mkDCRqMshrWrapper.v
│ │ ├── mkDM_Abstract_Commands.v
│ │ ├── mkDM_CSR_Tap.v
│ │ ├── mkDM_GPR_Tap.v
│ │ ├── mkDM_Mem_Tap.v
│ │ ├── mkDM_Run_Control.v
│ │ ├── mkDM_System_Bus.v
│ │ ├── mkDPRqMshrWrapper.v
│ │ ├── mkDPipeline.v
│ │ ├── mkDTlbSynth.v
│ │ ├── mkDebug_Module.v
│ │ ├── mkDirPredictor.v
│ │ ├── mkDivExecQ.v
│ │ ├── mkDoubleDiv.v
│ │ ├── mkDoubleFMA.v
│ │ ├── mkDoubleSqrt.v
│ │ ├── mkDummyStoreBuffer.v
│ │ ├── mkEpochManager.v
│ │ ├── mkFabric_2x3.v
│ │ ├── mkFetchStage.v
│ │ ├── mkFmaExecQ.v
│ │ ├── mkFpuMulDivDispToRegFifo.v
│ │ ├── mkFpuMulDivRegToExeFifo.v
│ │ ├── mkGSelectGHistReg.v
│ │ ├── mkGSelectPred.v
│ │ ├── mkGShareGHistReg.v
│ │ ├── mkGSharePred.v
│ │ ├── mkIBankWrapper.v
│ │ ├── mkICRqMshrWrapper.v
│ │ ├── mkICoCache.v
│ │ ├── mkIPRqMshrWrapper.v
│ │ ├── mkIPipeline.v
│ │ ├── mkITlb.v
│ │ ├── mkJtagTap.v
│ │ ├── mkL2Tlb.v
│ │ ├── mkLLCache.v
│ │ ├── mkLLPipeline.v
│ │ ├── mkLSQIssueLdQ.v
│ │ ├── mkLastLvCRqMshr.v
│ │ ├── mkMMIOInst.v
│ │ ├── mkMemDispToRegFifo.v
│ │ ├── mkMemLoader.v
│ │ ├── mkMemRegToExeFifo.v
│ │ ├── mkMinimumExecQ.v
│ │ ├── mkMulExecQ.v
│ │ ├── mkNullTransCache.v
│ │ ├── mkP3_Core.v
│ │ ├── mkPLIC_16_2_7.v
│ │ ├── mkPowerOnReset.v
│ │ ├── mkProc.v
│ │ ├── mkRFileSynth.v
│ │ ├── mkRas.v
│ │ ├── mkRegRenamingTable.v
│ │ ├── mkReorderBufferSynth.v
│ │ ├── mkReservationStationAlu.v
│ │ ├── mkReservationStationFpuMulDiv.v
│ │ ├── mkReservationStationMem.v
│ │ ├── mkRobRowSynth.v
│ │ ├── mkScoreboardAggr.v
│ │ ├── mkScoreboardCons.v
│ │ ├── mkSimpleRespQ.v
│ │ ├── mkSoC_Map.v
│ │ ├── mkSpecTagManager.v
│ │ ├── mkSplitLSQ.v
│ │ ├── mkSplitTransCache.v
│ │ ├── mkStoreBufferEhr.v
│ │ ├── mkSyncBramFifo_w36_d512.v
│ │ ├── mkSyncFifo_w32_d16.v
│ │ ├── mkTV_Encode.v
│ │ ├── mkTV_Xactor.v
│ │ ├── mkTourGHistReg.v
│ │ ├── mkTourPred.v
│ │ ├── mkTourPredSecure.v
│ │ ├── mkTrace_Data2_to_Trace_Data.v
│ │ ├── mkXilinxFpDiv.v
│ │ ├── mkXilinxFpDivIP.v
│ │ ├── mkXilinxFpDivSim.v
│ │ ├── mkXilinxFpFma.v
│ │ ├── mkXilinxFpFmaIP.v
│ │ ├── mkXilinxFpFmaSim.v
│ │ ├── mkXilinxFpSqrt.v
│ │ ├── mkXilinxFpSqrtIP.v
│ │ ├── mkXilinxFpSqrtSim.v
│ │ ├── module_alu.v
│ │ ├── module_aluBr.v
│ │ ├── module_amoExec.v
│ │ ├── module_basicExec.v
│ │ ├── module_brAddrCalc.v
│ │ ├── module_checkForException.v
│ │ ├── module_decode.v
│ │ ├── module_decodeBrPred.v
│ │ ├── module_execFpuSimple.v
│ │ └── module_getControlFlow.v
│ ├── Verilog_RTL_sim/
│ │ ├── ASSIGN1.v
│ │ ├── MakeReset0.v
│ │ ├── RegUNInit.v
│ │ ├── SyncWire.v
│ │ ├── mkAluDispToRegFifo.v
│ │ ├── mkAluExeToFinFifo.v
│ │ ├── mkAluRegToExeFifo.v
│ │ ├── mkBht.v
│ │ ├── mkCore.v
│ │ ├── mkCoreW.v
│ │ ├── mkDCRqMshrWrapper.v
│ │ ├── mkDM_Abstract_Commands.v
│ │ ├── mkDM_CSR_Tap.v
│ │ ├── mkDM_GPR_Tap.v
│ │ ├── mkDM_Mem_Tap.v
│ │ ├── mkDM_Run_Control.v
│ │ ├── mkDM_System_Bus.v
│ │ ├── mkDPRqMshrWrapper.v
│ │ ├── mkDPipeline.v
│ │ ├── mkDTlbSynth.v
│ │ ├── mkDebug_Module.v
│ │ ├── mkDirPredictor.v
│ │ ├── mkDivExecQ.v
│ │ ├── mkDoubleDiv.v
│ │ ├── mkDoubleFMA.v
│ │ ├── mkDoubleSqrt.v
│ │ ├── mkDummyStoreBuffer.v
│ │ ├── mkEpochManager.v
│ │ ├── mkFabric_2x3.v
│ │ ├── mkFetchStage.v
│ │ ├── mkFmaExecQ.v
│ │ ├── mkFpuMulDivDispToRegFifo.v
│ │ ├── mkFpuMulDivRegToExeFifo.v
│ │ ├── mkGSelectGHistReg.v
│ │ ├── mkGSelectPred.v
│ │ ├── mkGShareGHistReg.v
│ │ ├── mkGSharePred.v
│ │ ├── mkIBankWrapper.v
│ │ ├── mkICRqMshrWrapper.v
│ │ ├── mkICoCache.v
│ │ ├── mkIPRqMshrWrapper.v
│ │ ├── mkIPipeline.v
│ │ ├── mkITlb.v
│ │ ├── mkJtagTap.v
│ │ ├── mkL2Tlb.v
│ │ ├── mkLLCache.v
│ │ ├── mkLLPipeline.v
│ │ ├── mkLSQIssueLdQ.v
│ │ ├── mkLastLvCRqMshr.v
│ │ ├── mkMMIOInst.v
│ │ ├── mkMemDispToRegFifo.v
│ │ ├── mkMemLoader.v
│ │ ├── mkMemRegToExeFifo.v
│ │ ├── mkMinimumExecQ.v
│ │ ├── mkMulExecQ.v
│ │ ├── mkNullTransCache.v
│ │ ├── mkP3_Core.v
│ │ ├── mkPLIC_16_2_7.v
│ │ ├── mkPowerOnReset.v
│ │ ├── mkProc.v
│ │ ├── mkRFileSynth.v
│ │ ├── mkRas.v
│ │ ├── mkRegRenamingTable.v
│ │ ├── mkReorderBufferSynth.v
│ │ ├── mkReservationStationAlu.v
│ │ ├── mkReservationStationFpuMulDiv.v
│ │ ├── mkReservationStationMem.v
│ │ ├── mkRobRowSynth.v
│ │ ├── mkScoreboardAggr.v
│ │ ├── mkScoreboardCons.v
│ │ ├── mkSimpleRespQ.v
│ │ ├── mkSoC_Map.v
│ │ ├── mkSpecTagManager.v
│ │ ├── mkSplitLSQ.v
│ │ ├── mkSplitTransCache.v
│ │ ├── mkStoreBufferEhr.v
│ │ ├── mkSyncBramFifo_w36_d512.v
│ │ ├── mkSyncFifo_w32_d16.v
│ │ ├── mkTV_Encode.v
│ │ ├── mkTV_Xactor.v
│ │ ├── mkTourGHistReg.v
│ │ ├── mkTourPred.v
│ │ ├── mkTourPredSecure.v
│ │ ├── mkTrace_Data2_to_Trace_Data.v
│ │ ├── mkXilinxFpDiv.v
│ │ ├── mkXilinxFpDivIP.v
│ │ ├── mkXilinxFpDivSim.v
│ │ ├── mkXilinxFpFma.v
│ │ ├── mkXilinxFpFmaIP.v
│ │ ├── mkXilinxFpFmaSim.v
│ │ ├── mkXilinxFpSqrt.v
│ │ ├── mkXilinxFpSqrtIP.v
│ │ ├── mkXilinxFpSqrtSim.v
│ │ ├── module_alu.v
│ │ ├── module_aluBr.v
│ │ ├── module_amoExec.v
│ │ ├── module_basicExec.v
│ │ ├── module_brAddrCalc.v
│ │ ├── module_checkForException.v
│ │ ├── module_decode.v
│ │ ├── module_decodeBrPred.v
│ │ ├── module_execFpuSimple.v
│ │ └── module_getControlFlow.v
│ ├── src_BSV/
│ │ ├── ClockHacks.bsv
│ │ ├── Giraffe.defines
│ │ ├── Giraffe_IFC.bsv
│ │ ├── JtagTap.bsv
│ │ ├── P3_Core.bsv
│ │ ├── PowerOnReset.bsv
│ │ └── SoC_Map.bsv
│ └── xilinx_ip/
│ ├── component.xml
│ ├── hdl/
│ │ ├── ASSIGN1.v
│ │ ├── BRAM2.v
│ │ ├── Counter.v
│ │ ├── FIFO1.v
│ │ ├── FIFO10.v
│ │ ├── FIFO2.v
│ │ ├── FIFO20.v
│ │ ├── FIFOL1.v
│ │ ├── MakeClock.v
│ │ ├── MakeReset0.v
│ │ ├── MakeResetA.v
│ │ ├── RegFile.v
│ │ ├── RegUNInit.v
│ │ ├── ResetEither.v
│ │ ├── RevertReg.v
│ │ ├── SizedFIFO.v
│ │ ├── SizedFIFO0.v
│ │ ├── SyncFIFOLevel.v
│ │ ├── SyncHandshake.v
│ │ ├── SyncReset0.v
│ │ ├── SyncResetA.v
│ │ ├── SyncWire.v
│ │ ├── mkAluDispToRegFifo.v
│ │ ├── mkAluExeToFinFifo.v
│ │ ├── mkAluRegToExeFifo.v
│ │ ├── mkBht.v
│ │ ├── mkCore.v
│ │ ├── mkCoreW.v
│ │ ├── mkDCRqMshrWrapper.v
│ │ ├── mkDM_Abstract_Commands.v
│ │ ├── mkDM_CSR_Tap.v
│ │ ├── mkDM_GPR_Tap.v
│ │ ├── mkDM_Mem_Tap.v
│ │ ├── mkDM_Run_Control.v
│ │ ├── mkDM_System_Bus.v
│ │ ├── mkDPRqMshrWrapper.v
│ │ ├── mkDPipeline.v
│ │ ├── mkDTlbSynth.v
│ │ ├── mkDebug_Module.v
│ │ ├── mkDirPredictor.v
│ │ ├── mkDivExecQ.v
│ │ ├── mkDoubleDiv.v
│ │ ├── mkDoubleFMA.v
│ │ ├── mkDoubleSqrt.v
│ │ ├── mkDummyStoreBuffer.v
│ │ ├── mkEpochManager.v
│ │ ├── mkFabric_2x3.v
│ │ ├── mkFetchStage.v
│ │ ├── mkFmaExecQ.v
│ │ ├── mkFpuMulDivDispToRegFifo.v
│ │ ├── mkFpuMulDivRegToExeFifo.v
│ │ ├── mkGSelectGHistReg.v
│ │ ├── mkGSelectPred.v
│ │ ├── mkGShareGHistReg.v
│ │ ├── mkGSharePred.v
│ │ ├── mkIBankWrapper.v
│ │ ├── mkICRqMshrWrapper.v
│ │ ├── mkICoCache.v
│ │ ├── mkIPRqMshrWrapper.v
│ │ ├── mkIPipeline.v
│ │ ├── mkITlb.v
│ │ ├── mkJtagTap.v
│ │ ├── mkL2Tlb.v
│ │ ├── mkLLCache.v
│ │ ├── mkLLPipeline.v
│ │ ├── mkLSQIssueLdQ.v
│ │ ├── mkLastLvCRqMshr.v
│ │ ├── mkMMIOInst.v
│ │ ├── mkMemDispToRegFifo.v
│ │ ├── mkMemLoader.v
│ │ ├── mkMemRegToExeFifo.v
│ │ ├── mkMinimumExecQ.v
│ │ ├── mkMulExecQ.v
│ │ ├── mkNullTransCache.v
│ │ ├── mkP3_Core.v
│ │ ├── mkPLIC_16_2_7.v
│ │ ├── mkPowerOnReset.v
│ │ ├── mkProc.v
│ │ ├── mkRFileSynth.v
│ │ ├── mkRas.v
│ │ ├── mkRegRenamingTable.v
│ │ ├── mkReorderBufferSynth.v
│ │ ├── mkReservationStationAlu.v
│ │ ├── mkReservationStationFpuMulDiv.v
│ │ ├── mkReservationStationMem.v
│ │ ├── mkRobRowSynth.v
│ │ ├── mkScoreboardAggr.v
│ │ ├── mkScoreboardCons.v
│ │ ├── mkSimpleRespQ.v
│ │ ├── mkSoC_Map.v
│ │ ├── mkSpecTagManager.v
│ │ ├── mkSplitLSQ.v
│ │ ├── mkSplitTransCache.v
│ │ ├── mkStoreBufferEhr.v
│ │ ├── mkSyncBramFifo_w36_d512.v
│ │ ├── mkSyncFifo_w32_d16.v
│ │ ├── mkTV_Encode.v
│ │ ├── mkTV_Xactor.v
│ │ ├── mkTourGHistReg.v
│ │ ├── mkTourPred.v
│ │ ├── mkTourPredSecure.v
│ │ ├── mkTrace_Data2_to_Trace_Data.v
│ │ ├── mkXilinxFpDiv.v
│ │ ├── mkXilinxFpDivIP.v
│ │ ├── mkXilinxFpDivSim.v
│ │ ├── mkXilinxFpFma.v
│ │ ├── mkXilinxFpFmaIP.v
│ │ ├── mkXilinxFpFmaSim.v
│ │ ├── mkXilinxFpSqrt.v
│ │ ├── mkXilinxFpSqrtIP.v
│ │ ├── mkXilinxFpSqrtSim.v
│ │ ├── module_alu.v
│ │ ├── module_aluBr.v
│ │ ├── module_amoExec.v
│ │ ├── module_basicExec.v
│ │ ├── module_brAddrCalc.v
│ │ ├── module_checkForException.v
│ │ ├── module_decode.v
│ │ ├── module_decodeBrPred.v
│ │ ├── module_execFpuSimple.v
│ │ ├── module_getControlFlow.v
│ │ └── reset_guard.v
│ ├── src/
│ │ ├── fp_div/
│ │ │ ├── fp_div.xci
│ │ │ └── fp_div.xml
│ │ ├── fp_fma/
│ │ │ ├── fp_fma.xci
│ │ │ └── fp_fma.xml
│ │ ├── fp_sqrt/
│ │ │ ├── fp_sqrt.xci
│ │ │ └── fp_sqrt.xml
│ │ ├── int_div_unsigned/
│ │ │ ├── int_div_unsigned.xci
│ │ │ └── int_div_unsigned.xml
│ │ ├── int_mul_signed/
│ │ │ ├── int_mul_signed.xci
│ │ │ └── int_mul_signed.xml
│ │ ├── int_mul_signed_unsigned/
│ │ │ ├── int_mul_signed_unsigned.xci
│ │ │ └── int_mul_signed_unsigned.xml
│ │ ├── int_mul_unsigned/
│ │ │ ├── int_mul_unsigned.xci
│ │ │ └── int_mul_unsigned.xml
│ │ └── p3_constraints.xdc
│ └── xgui/
│ ├── mkP3_Core_v1_0.tcl
│ └── ssith_processor_v1_0.tcl
├── src_Testbench/
│ ├── Fabrics/
│ │ ├── AXI4/
│ │ │ ├── AXI4_Deburster.bsv
│ │ │ ├── AXI4_Fabric.bsv
│ │ │ ├── AXI4_Mem_Model.bsv
│ │ │ ├── AXI4_Types.bsv
│ │ │ └── Unit_Test/
│ │ │ ├── Makefile
│ │ │ └── Unit_Test_Deburster.bsv
│ │ ├── AXI4_Lite/
│ │ │ ├── AXI4_Lite_Fabric.bsv
│ │ │ └── AXI4_Lite_Types.bsv
│ │ └── Adapters/
│ │ └── AXI4_AXI4_Lite_Adapters.bsv
│ ├── SoC/
│ │ ├── Boot_ROM.bsv
│ │ ├── Boot_ROM_Generator/
│ │ │ ├── .gitignore
│ │ │ ├── Gen_BSV_fn_read_ROM.py
│ │ │ ├── Makefile
│ │ │ └── gen_bootrom.cc
│ │ ├── External_Control.bsv
│ │ ├── Mem_Controller.bsv
│ │ ├── SoC_Fabric.bsv
│ │ ├── SoC_Map.bsv
│ │ ├── SoC_Top.bsv
│ │ ├── Timer.bsv
│ │ ├── UART_Model.bsv
│ │ ├── fn_read_ROM_RV32.bsvi
│ │ └── fn_read_ROM_RV64.bsvi
│ ├── Top/
│ │ ├── C_Imported_Functions.c
│ │ ├── C_Imported_Functions.h
│ │ ├── C_Imports.bsv
│ │ ├── Makefile
│ │ ├── Mem_Model.bsv
│ │ └── Top_HW_Side.bsv
│ └── Unit/
│ └── Prefetcher_test.bsv
└── src_bsc_lib_RTL/
├── BRAM2.v
├── FIFO1.v
├── FIFO10.v
├── FIFO2.v
├── FIFO20.v
├── FIFOL1.v
├── MakeClock.v
├── MakeResetA.v
├── README.txt
├── RegFile.v
├── RegFileLoad.v
├── ResetEither.v
├── RevertReg.v
├── SizedFIFO.v
├── SizedFIFO0.v
├── SyncFIFOLevel.v
├── SyncHandshake.v
├── SyncResetA.v
└── main.v
SYMBOL INDEX (9 symbols across 2 files)
FILE: Tests/Run_regression.py
function main (line 57) | def main (argv = None):
function extract_arch_string (line 223) | def extract_arch_string (s):
function select_test_families (line 253) | def select_test_families (arch):
function traverse (line 296) | def traverse (fn_filter_dir, fn_filter_regular_file, level, path):
function do_worker (line 317) | def do_worker (worker_num, args_dict):
function do_isa_test (line 371) | def do_isa_test (args_dict, full_filename):
function run_command (line 419) | def run_command (command):
FILE: builds/Resources/Verilator_resources/sim_main.cpp
function sc_time_stamp (line 18) | double sc_time_stamp () { // Called by $time in Verilog
function main (line 22) | int main (int argc, char **argv, char **env) {
Copy disabled (too large)
Download .json
Condensed preview — 1476 files, each showing path, character count, and a content snippet. Download the .json file for the full structured content (110,647K chars).
[
{
"path": ".gitignore",
"chars": 152,
"preview": "*~\nREADME.html\nbuild_dir\n*.bo\n*.ba\n*.o\nobj_dir\nelf_to_hex\nMem.hex\nexe*\n*.log\nTests/Logs\n*_edited.v\n*.trace_mem_load\nAA_*"
},
{
"path": ".gitmodules",
"chars": 152,
"preview": "[submodule \"src_Core/BSV_Additional_Libs/BlueStuff\"]\n\tpath = src_Core/BSV_Additional_Libs/BlueStuff\n\turl = https://githu"
},
{
"path": "LICENSE",
"chars": 11862,
"preview": "This repository contains code with two licenses.\n\n1. See: src_Core/RISCY_OOO/LICENSE_RISCY-OOO\n\n The code in src_Core"
},
{
"path": "README.md",
"chars": 10217,
"preview": "# Open-source RISC-V CPUs from Bluespec, Inc.\n\nThis is one of a family of free, open-source RISC-V CPUs created by Blues"
},
{
"path": "Tests/Makefile",
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"preview": "### -*-Makefile-*-\n\n# Copyright (c) 2018 Bluespec, Inc. All Rights Reserved\n\n# ========================================"
},
{
"path": "Tests/README.txt",
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"preview": "Copyright (c) 2018-2019 Bluespec, Inc. All Rights Reserved\n\n>==========================================================="
},
{
"path": "Tests/Run_regression.py",
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"preview": "#!/usr/bin/python3\n\n# Copyright (c) 2018-2019 Bluespec, Inc.\n# See LICENSE for license details\n\nusage_line = (\n \" Us"
},
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},
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"chars": 9418,
"preview": "\nrv32mi-p-csr: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
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"preview": "\nrv32mi-p-ma_fetch: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:"
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"preview": "\nrv32mi-p-mcsr: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
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"preview": "\nrv32mi-p-sbreak: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t0"
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"preview": "\nrv32mi-p-scall: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04"
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"preview": "\nrv32mi-p-shamt: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04"
},
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"chars": 8794,
"preview": "\nrv32si-p-csr: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32si-p-dirty.dump",
"chars": 8571,
"preview": "\nrv32si-p-dirty: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04"
},
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"path": "Tests/isa/rv32si-p-ma_fetch.dump",
"chars": 7854,
"preview": "\nrv32si-p-ma_fetch: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:"
},
{
"path": "Tests/isa/rv32si-p-sbreak.dump",
"chars": 5188,
"preview": "\nrv32si-p-sbreak: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t0"
},
{
"path": "Tests/isa/rv32si-p-scall.dump",
"chars": 4981,
"preview": "\nrv32si-p-scall: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04"
},
{
"path": "Tests/isa/rv32si-p-wfi.dump",
"chars": 5193,
"preview": "\nrv32si-p-wfi: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
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"chars": 6213,
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},
{
"path": "Tests/isa/rv32ua-p-amoand_w.dump",
"chars": 5030,
"preview": "\nrv32ua-p-amoand_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:"
},
{
"path": "Tests/isa/rv32ua-p-amomax_w.dump",
"chars": 4975,
"preview": "\nrv32ua-p-amomax_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:"
},
{
"path": "Tests/isa/rv32ua-p-amomaxu_w.dump",
"chars": 4980,
"preview": "\nrv32ua-p-amomaxu_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000"
},
{
"path": "Tests/isa/rv32ua-p-amomin_w.dump",
"chars": 4980,
"preview": "\nrv32ua-p-amomin_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:"
},
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"path": "Tests/isa/rv32ua-p-amominu_w.dump",
"chars": 4982,
"preview": "\nrv32ua-p-amominu_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000"
},
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"chars": 5011,
"preview": "\nrv32ua-p-amoor_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t"
},
{
"path": "Tests/isa/rv32ua-p-amoswap_w.dump",
"chars": 5027,
"preview": "\nrv32ua-p-amoswap_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000"
},
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"path": "Tests/isa/rv32ua-p-amoxor_w.dump",
"chars": 6214,
"preview": "\nrv32ua-p-amoxor_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:"
},
{
"path": "Tests/isa/rv32ua-p-lrsc.dump",
"chars": 26911,
"preview": "\nrv32ua-p-lrsc: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
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"path": "Tests/isa/rv32ua-v-amoadd_w.dump",
"chars": 42143,
"preview": "\nrv32ua-v-amoadd_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:"
},
{
"path": "Tests/isa/rv32ua-v-amoand_w.dump",
"chars": 41994,
"preview": "\nrv32ua-v-amoand_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:"
},
{
"path": "Tests/isa/rv32ua-v-amomax_w.dump",
"chars": 42015,
"preview": "\nrv32ua-v-amomax_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:"
},
{
"path": "Tests/isa/rv32ua-v-amomaxu_w.dump",
"chars": 42018,
"preview": "\nrv32ua-v-amomaxu_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000"
},
{
"path": "Tests/isa/rv32ua-v-amomin_w.dump",
"chars": 42016,
"preview": "\nrv32ua-v-amomin_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:"
},
{
"path": "Tests/isa/rv32ua-v-amominu_w.dump",
"chars": 42020,
"preview": "\nrv32ua-v-amominu_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000"
},
{
"path": "Tests/isa/rv32ua-v-amoor_w.dump",
"chars": 41976,
"preview": "\nrv32ua-v-amoor_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t"
},
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"chars": 41993,
"preview": "\nrv32ua-v-amoswap_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000"
},
{
"path": "Tests/isa/rv32ua-v-amoxor_w.dump",
"chars": 42289,
"preview": "\nrv32ua-v-amoxor_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:"
},
{
"path": "Tests/isa/rv32ua-v-lrsc.dump",
"chars": 63535,
"preview": "\nrv32ua-v-lrsc: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32uc-p-rvc.dump",
"chars": 178456,
"preview": "\nrv32uc-p-rvc: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32uc-v-rvc.dump",
"chars": 242860,
"preview": "\nrv32uc-v-rvc: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32ud-p-fadd.dump",
"chars": 19280,
"preview": "\nrv32ud-p-fadd: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
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"chars": 10357,
"preview": "\nrv32ud-p-fclass: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t0"
},
{
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"chars": 23877,
"preview": "\nrv32ud-p-fcmp: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
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"chars": 11183,
"preview": "\nrv32ud-p-fcvt: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
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"chars": 23552,
"preview": "\nrv32ud-p-fcvt_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t0"
},
{
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"chars": 16335,
"preview": "\nrv32ud-p-fdiv: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
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"chars": 22224,
"preview": "\nrv32ud-p-fmadd: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04"
},
{
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"chars": 30432,
"preview": "\nrv32ud-p-fmin: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
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"chars": 9405,
"preview": "\nrv32ud-p-ldst: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
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"chars": 6235,
"preview": "\nrv32ud-p-recoding: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:"
},
{
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"chars": 55508,
"preview": "\nrv32ud-v-fadd: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
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"chars": 46288,
"preview": "\nrv32ud-v-fclass: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t0"
},
{
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"chars": 60621,
"preview": "\nrv32ud-v-fcmp: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
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"chars": 47929,
"preview": "\nrv32ud-v-fcvt: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
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"chars": 59844,
"preview": "\nrv32ud-v-fcvt_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t0"
},
{
"path": "Tests/isa/rv32ud-v-fdiv.dump",
"chars": 52444,
"preview": "\nrv32ud-v-fdiv: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32ud-v-fmadd.dump",
"chars": 58599,
"preview": "\nrv32ud-v-fmadd: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00"
},
{
"path": "Tests/isa/rv32ud-v-fmin.dump",
"chars": 67233,
"preview": "\nrv32ud-v-fmin: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32ud-v-ldst.dump",
"chars": 45555,
"preview": "\nrv32ud-v-ldst: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32ud-v-recoding.dump",
"chars": 42826,
"preview": "\nrv32ud-v-recoding: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:"
},
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"chars": 13537,
"preview": "\nrv32uf-p-fadd: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32uf-p-fclass.dump",
"chars": 7398,
"preview": "\nrv32uf-p-fclass: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t0"
},
{
"path": "Tests/isa/rv32uf-p-fcmp.dump",
"chars": 17307,
"preview": "\nrv32uf-p-fcmp: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32uf-p-fcvt.dump",
"chars": 6177,
"preview": "\nrv32uf-p-fcvt: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32uf-p-fcvt_w.dump",
"chars": 23552,
"preview": "\nrv32uf-p-fcvt_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t0"
},
{
"path": "Tests/isa/rv32uf-p-fdiv.dump",
"chars": 11524,
"preview": "\nrv32uf-p-fdiv: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32uf-p-fmadd.dump",
"chars": 16345,
"preview": "\nrv32uf-p-fmadd: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04"
},
{
"path": "Tests/isa/rv32uf-p-fmin.dump",
"chars": 21621,
"preview": "\nrv32uf-p-fmin: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32uf-p-ldst.dump",
"chars": 5824,
"preview": "\nrv32uf-p-ldst: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32uf-p-move.dump",
"chars": 12397,
"preview": "\nrv32uf-p-move: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32uf-p-recoding.dump",
"chars": 6235,
"preview": "\nrv32uf-p-recoding: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:"
},
{
"path": "Tests/isa/rv32uf-v-fadd.dump",
"chars": 50396,
"preview": "\nrv32uf-v-fadd: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32uf-v-fclass.dump",
"chars": 44079,
"preview": "\nrv32uf-v-fclass: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t0"
},
{
"path": "Tests/isa/rv32uf-v-fcmp.dump",
"chars": 54271,
"preview": "\nrv32uf-v-fcmp: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32uf-v-fcvt.dump",
"chars": 43144,
"preview": "\nrv32uf-v-fcvt: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32uf-v-fcvt_w.dump",
"chars": 59843,
"preview": "\nrv32uf-v-fcvt_w: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t0"
},
{
"path": "Tests/isa/rv32uf-v-fdiv.dump",
"chars": 47824,
"preview": "\nrv32uf-v-fdiv: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32uf-v-fmadd.dump",
"chars": 52763,
"preview": "\nrv32uf-v-fmadd: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00"
},
{
"path": "Tests/isa/rv32uf-v-fmin.dump",
"chars": 57888,
"preview": "\nrv32uf-v-fmin: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32uf-v-ldst.dump",
"chars": 42505,
"preview": "\nrv32uf-v-ldst: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32uf-v-move.dump",
"chars": 49377,
"preview": "\nrv32uf-v-move: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32uf-v-recoding.dump",
"chars": 42825,
"preview": "\nrv32uf-v-recoding: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:"
},
{
"path": "Tests/isa/rv32ui-p-add.dump",
"chars": 18372,
"preview": "\nrv32ui-p-add: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32ui-p-addi.dump",
"chars": 12152,
"preview": "\nrv32ui-p-addi: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32ui-p-and.dump",
"chars": 20546,
"preview": "\nrv32ui-p-and: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32ui-p-andi.dump",
"chars": 10076,
"preview": "\nrv32ui-p-andi: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32ui-p-auipc.dump",
"chars": 5118,
"preview": "\nrv32ui-p-auipc: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04"
},
{
"path": "Tests/isa/rv32ui-p-beq.dump",
"chars": 12965,
"preview": "\nrv32ui-p-beq: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32ui-p-bge.dump",
"chars": 13673,
"preview": "\nrv32ui-p-bge: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32ui-p-bgeu.dump",
"chars": 15038,
"preview": "\nrv32ui-p-bgeu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32ui-p-blt.dump",
"chars": 12966,
"preview": "\nrv32ui-p-blt: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32ui-p-bltu.dump",
"chars": 14354,
"preview": "\nrv32ui-p-bltu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32ui-p-bne.dump",
"chars": 12929,
"preview": "\nrv32ui-p-bne: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32ui-p-fence_i.dump",
"chars": 7384,
"preview": "\nrv32ui-p-fence_i: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t"
},
{
"path": "Tests/isa/rv32ui-p-jal.dump",
"chars": 5049,
"preview": "\nrv32ui-p-jal: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32ui-p-jalr.dump",
"chars": 6663,
"preview": "\nrv32ui-p-jalr: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32ui-p-lb.dump",
"chars": 11920,
"preview": "\nrv32ui-p-lb: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c00"
},
{
"path": "Tests/isa/rv32ui-p-lbu.dump",
"chars": 11942,
"preview": "\nrv32ui-p-lbu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32ui-p-lh.dump",
"chars": 13013,
"preview": "\nrv32ui-p-lh: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c00"
},
{
"path": "Tests/isa/rv32ui-p-lhu.dump",
"chars": 13003,
"preview": "\nrv32ui-p-lhu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32ui-p-lui.dump",
"chars": 4971,
"preview": "\nrv32ui-p-lui: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32ui-p-lw.dump",
"chars": 13090,
"preview": "\nrv32ui-p-lw: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c00"
},
{
"path": "Tests/isa/rv32ui-p-or.dump",
"chars": 20570,
"preview": "\nrv32ui-p-or: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c00"
},
{
"path": "Tests/isa/rv32ui-p-ori.dump",
"chars": 10092,
"preview": "\nrv32ui-p-ori: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32ui-p-sb.dump",
"chars": 17714,
"preview": "\nrv32ui-p-sb: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c00"
},
{
"path": "Tests/isa/rv32ui-p-sh.dump",
"chars": 20297,
"preview": "\nrv32ui-p-sh: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c00"
},
{
"path": "Tests/isa/rv32ui-p-simple.dump",
"chars": 4532,
"preview": "\nrv32ui-p-simple: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t0"
},
{
"path": "Tests/isa/rv32ui-p-sll.dump",
"chars": 20141,
"preview": "\nrv32ui-p-sll: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32ui-p-slli.dump",
"chars": 12163,
"preview": "\nrv32ui-p-slli: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32ui-p-slt.dump",
"chars": 18291,
"preview": "\nrv32ui-p-slt: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32ui-p-slti.dump",
"chars": 12048,
"preview": "\nrv32ui-p-slti: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32ui-p-sltiu.dump",
"chars": 12067,
"preview": "\nrv32ui-p-sltiu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04"
},
{
"path": "Tests/isa/rv32ui-p-sltu.dump",
"chars": 18331,
"preview": "\nrv32ui-p-sltu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32ui-p-sra.dump",
"chars": 21321,
"preview": "\nrv32ui-p-sra: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32ui-p-srai.dump",
"chars": 13426,
"preview": "\nrv32ui-p-srai: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32ui-p-srl.dump",
"chars": 21284,
"preview": "\nrv32ui-p-srl: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32ui-p-srli.dump",
"chars": 12226,
"preview": "\nrv32ui-p-srli: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32ui-p-sub.dump",
"chars": 18515,
"preview": "\nrv32ui-p-sub: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32ui-p-sw.dump",
"chars": 20583,
"preview": "\nrv32ui-p-sw: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c00"
},
{
"path": "Tests/isa/rv32ui-p-xor.dump",
"chars": 20584,
"preview": "\nrv32ui-p-xor: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32ui-p-xori.dump",
"chars": 11295,
"preview": "\nrv32ui-p-xori: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32ui-v-add.dump",
"chars": 55498,
"preview": "\nrv32ui-v-add: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32ui-v-addi.dump",
"chars": 48831,
"preview": "\nrv32ui-v-addi: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32ui-v-and.dump",
"chars": 56931,
"preview": "\nrv32ui-v-and: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32ui-v-andi.dump",
"chars": 46607,
"preview": "\nrv32ui-v-andi: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32ui-v-auipc.dump",
"chars": 41987,
"preview": "\nrv32ui-v-auipc: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00"
},
{
"path": "Tests/isa/rv32ui-v-beq.dump",
"chars": 49501,
"preview": "\nrv32ui-v-beq: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32ui-v-bge.dump",
"chars": 50803,
"preview": "\nrv32ui-v-bge: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32ui-v-bgeu.dump",
"chars": 51946,
"preview": "\nrv32ui-v-bgeu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32ui-v-blt.dump",
"chars": 49504,
"preview": "\nrv32ui-v-blt: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32ui-v-bltu.dump",
"chars": 50669,
"preview": "\nrv32ui-v-bltu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32ui-v-bne.dump",
"chars": 49542,
"preview": "\nrv32ui-v-bne: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32ui-v-fence_i.dump",
"chars": 44499,
"preview": "\nrv32ui-v-fence_i: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t"
},
{
"path": "Tests/isa/rv32ui-v-jal.dump",
"chars": 41945,
"preview": "\nrv32ui-v-jal: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32ui-v-jalr.dump",
"chars": 43560,
"preview": "\nrv32ui-v-jalr: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32ui-v-lb.dump",
"chars": 48383,
"preview": "\nrv32ui-v-lb: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c00"
},
{
"path": "Tests/isa/rv32ui-v-lbu.dump",
"chars": 48404,
"preview": "\nrv32ui-v-lbu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32ui-v-lh.dump",
"chars": 48960,
"preview": "\nrv32ui-v-lh: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c00"
},
{
"path": "Tests/isa/rv32ui-v-lhu.dump",
"chars": 49322,
"preview": "\nrv32ui-v-lhu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32ui-v-lui.dump",
"chars": 42088,
"preview": "\nrv32ui-v-lui: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32ui-v-lw.dump",
"chars": 49750,
"preview": "\nrv32ui-v-lw: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c00"
},
{
"path": "Tests/isa/rv32ui-v-or.dump",
"chars": 57175,
"preview": "\nrv32ui-v-or: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c00"
},
{
"path": "Tests/isa/rv32ui-v-ori.dump",
"chars": 47142,
"preview": "\nrv32ui-v-ori: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32ui-v-sb.dump",
"chars": 53869,
"preview": "\nrv32ui-v-sb: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c00"
},
{
"path": "Tests/isa/rv32ui-v-sh.dump",
"chars": 56371,
"preview": "\nrv32ui-v-sh: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c00"
},
{
"path": "Tests/isa/rv32ui-v-simple.dump",
"chars": 40774,
"preview": "\nrv32ui-v-simple: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t0"
},
{
"path": "Tests/isa/rv32ui-v-sll.dump",
"chars": 56969,
"preview": "\nrv32ui-v-sll: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32ui-v-slli.dump",
"chars": 48769,
"preview": "\nrv32ui-v-slli: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32ui-v-slt.dump",
"chars": 54971,
"preview": "\nrv32ui-v-slt: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32ui-v-slti.dump",
"chars": 48357,
"preview": "\nrv32ui-v-slti: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32ui-v-sltiu.dump",
"chars": 48377,
"preview": "\nrv32ui-v-sltiu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00"
},
{
"path": "Tests/isa/rv32ui-v-sltu.dump",
"chars": 55012,
"preview": "\nrv32ui-v-sltu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32ui-v-sra.dump",
"chars": 58368,
"preview": "\nrv32ui-v-sra: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32ui-v-srai.dump",
"chars": 49810,
"preview": "\nrv32ui-v-srai: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32ui-v-srl.dump",
"chars": 57891,
"preview": "\nrv32ui-v-srl: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32ui-v-srli.dump",
"chars": 49350,
"preview": "\nrv32ui-v-srli: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32ui-v-sub.dump",
"chars": 55048,
"preview": "\nrv32ui-v-sub: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32ui-v-sw.dump",
"chars": 56932,
"preview": "\nrv32ui-v-sw: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c00"
},
{
"path": "Tests/isa/rv32ui-v-xor.dump",
"chars": 57115,
"preview": "\nrv32ui-v-xor: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32ui-v-xori.dump",
"chars": 47307,
"preview": "\nrv32ui-v-xori: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32um-p-div.dump",
"chars": 6371,
"preview": "\nrv32um-p-div: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32um-p-divu.dump",
"chars": 6382,
"preview": "\nrv32um-p-divu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32um-p-mul.dump",
"chars": 18553,
"preview": "\nrv32um-p-mul: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32um-p-mulh.dump",
"chars": 19081,
"preview": "\nrv32um-p-mulh: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32um-p-mulhsu.dump",
"chars": 19165,
"preview": "\nrv32um-p-mulhsu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t0"
},
{
"path": "Tests/isa/rv32um-p-mulhu.dump",
"chars": 19126,
"preview": "\nrv32um-p-mulhu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04"
},
{
"path": "Tests/isa/rv32um-p-rem.dump",
"chars": 6361,
"preview": "\nrv32um-p-rem: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c0"
},
{
"path": "Tests/isa/rv32um-p-remu.dump",
"chars": 6379,
"preview": "\nrv32um-p-remu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t04c"
},
{
"path": "Tests/isa/rv32um-v-div.dump",
"chars": 43413,
"preview": "\nrv32um-v-div: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32um-v-divu.dump",
"chars": 43501,
"preview": "\nrv32um-v-divu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32um-v-mul.dump",
"chars": 55230,
"preview": "\nrv32um-v-mul: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32um-v-mulh.dump",
"chars": 55764,
"preview": "\nrv32um-v-mulh: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv32um-v-mulhsu.dump",
"chars": 55845,
"preview": "\nrv32um-v-mulhsu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t0"
},
{
"path": "Tests/isa/rv32um-v-mulhu.dump",
"chars": 55808,
"preview": "\nrv32um-v-mulhu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00"
},
{
"path": "Tests/isa/rv32um-v-rem.dump",
"chars": 43405,
"preview": "\nrv32um-v-rem: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c0"
},
{
"path": "Tests/isa/rv32um-v-remu.dump",
"chars": 43424,
"preview": "\nrv32um-v-remu: file format elf32-littleriscv\n\n\nDisassembly of section .text.init:\n\n80000000 <_start>:\n80000000:\t00c"
},
{
"path": "Tests/isa/rv64mi-p-access.dump",
"chars": 6364,
"preview": "\nrv64mi-p-access: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n "
},
{
"path": "Tests/isa/rv64mi-p-breakpoint.dump",
"chars": 9409,
"preview": "\nrv64mi-p-breakpoint: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:"
},
{
"path": "Tests/isa/rv64mi-p-csr.dump",
"chars": 12035,
"preview": "\nrv64mi-p-csr: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n 80"
},
{
"path": "Tests/isa/rv64mi-p-illegal.dump",
"chars": 16565,
"preview": "\nrv64mi-p-illegal: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n "
},
{
"path": "Tests/isa/rv64mi-p-ma_addr.dump",
"chars": 27759,
"preview": "\nrv64mi-p-ma_addr: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n "
},
{
"path": "Tests/isa/rv64mi-p-ma_fetch.dump",
"chars": 10462,
"preview": "\nrv64mi-p-ma_fetch: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n "
},
{
"path": "Tests/isa/rv64mi-p-mcsr.dump",
"chars": 5445,
"preview": "\nrv64mi-p-mcsr: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n 8"
},
{
"path": "Tests/isa/rv64mi-p-sbreak.dump",
"chars": 5638,
"preview": "\nrv64mi-p-sbreak: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n "
},
{
"path": "Tests/isa/rv64mi-p-scall.dump",
"chars": 6463,
"preview": "\nrv64mi-p-scall: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n "
},
{
"path": "Tests/isa/rv64si-p-csr.dump",
"chars": 9178,
"preview": "\nrv64si-p-csr: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n 80"
},
{
"path": "Tests/isa/rv64si-p-dirty.dump",
"chars": 9153,
"preview": "\nrv64si-p-dirty: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n "
},
{
"path": "Tests/isa/rv64si-p-ma_fetch.dump",
"chars": 8445,
"preview": "\nrv64si-p-ma_fetch: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n "
},
{
"path": "Tests/isa/rv64si-p-sbreak.dump",
"chars": 5564,
"preview": "\nrv64si-p-sbreak: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n "
},
{
"path": "Tests/isa/rv64si-p-scall.dump",
"chars": 6641,
"preview": "\nrv64si-p-scall: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n "
},
{
"path": "Tests/isa/rv64si-p-wfi.dump",
"chars": 5569,
"preview": "\nrv64si-p-wfi: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n 80"
},
{
"path": "Tests/isa/rv64ua-p-amoadd_d.dump",
"chars": 6620,
"preview": "\nrv64ua-p-amoadd_d: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n "
},
{
"path": "Tests/isa/rv64ua-p-amoadd_w.dump",
"chars": 6670,
"preview": "\nrv64ua-p-amoadd_w: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n "
},
{
"path": "Tests/isa/rv64ua-p-amoand_d.dump",
"chars": 6671,
"preview": "\nrv64ua-p-amoand_d: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n "
},
{
"path": "Tests/isa/rv64ua-p-amoand_w.dump",
"chars": 6703,
"preview": "\nrv64ua-p-amoand_w: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n "
},
{
"path": "Tests/isa/rv64ua-p-amomax_d.dump",
"chars": 6676,
"preview": "\nrv64ua-p-amomax_d: file format elf64-littleriscv\n\n\nDisassembly of section .text.init:\n\n0000000080000000 <_start>:\n "
}
]
// ... and 1276 more files (download for full content)
About this extraction
This page contains the full source code of the bluespec/Toooba GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 1476 files (179.1 MB), approximately 26.4M tokens, and a symbol index with 9 extracted functions, classes, methods, constants, and types. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.
Extracted by GitExtract — free GitHub repo to text converter for AI. Built by Nikandr Surkov.