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Repository: chipsalliance/Cores-SweRV-EL2
Branch: main
Commit: 5b10fd96a60d
Files: 603
Total size: 5.2 MB
Directory structure:
gitextract_0gg5endz/
├── .github/
│ ├── scripts/
│ │ ├── breakpoint.sh
│ │ ├── common.inc.sh
│ │ ├── convert_dat.sh
│ │ ├── create_merged_package.sh
│ │ ├── gdb_test.sh
│ │ ├── gdb_test_golden.txt
│ │ ├── get_code_hash.sh
│ │ ├── indexgen/
│ │ │ ├── .gitignore
│ │ │ ├── Makefile
│ │ │ ├── dashboard-styles/
│ │ │ │ ├── gcov.css
│ │ │ │ └── main.css
│ │ │ ├── generate.py
│ │ │ ├── index_redirect/
│ │ │ │ └── index.html
│ │ │ ├── requirements.txt
│ │ │ ├── source.template/
│ │ │ │ ├── conf.py
│ │ │ │ ├── coverage_dashboard.md
│ │ │ │ ├── dev.md
│ │ │ │ ├── index.md
│ │ │ │ ├── main.md
│ │ │ │ └── verification_dashboard.md
│ │ │ └── update_styles.sh
│ │ ├── info_process_setup.sh
│ │ ├── mapfile
│ │ ├── openocd/
│ │ │ ├── board/
│ │ │ │ ├── caliptra-verilator-rst.cfg
│ │ │ │ └── caliptra-verilator.cfg
│ │ │ ├── sim-jtagdpi.cfg
│ │ │ ├── veer-el2-rst.cfg
│ │ │ └── veer-el2.cfg
│ │ ├── openocd_test.sh
│ │ ├── peripheral_access.tcl
│ │ ├── prepare_coverage_data.sh
│ │ ├── pytest/
│ │ │ ├── bar.html
│ │ │ ├── css/
│ │ │ │ └── styles.css
│ │ │ ├── script/
│ │ │ │ └── script.js
│ │ │ └── style_pytest_report.sh
│ │ ├── requirements-coverage.txt
│ │ ├── riscv_dv_matrix_include.py
│ │ ├── riscv_dv_parse_testlist.py
│ │ ├── run_regression_test.sh
│ │ ├── run_regression_tests.sh
│ │ ├── secrets_version
│ │ ├── test.gdb
│ │ └── utils.sh
│ └── workflows/
│ ├── build-docs.yml
│ ├── ci.yml
│ ├── custom-lint.yml
│ ├── gh-pages-pr-closed.yml
│ ├── gh-pages-pr-comment.yml
│ ├── gh-pages-pr-remove.yml
│ ├── publish-webpage.yml
│ ├── report-coverage.yml
│ ├── test-openocd.yml
│ ├── test-regression-cache-waypack.yml
│ ├── test-regression-dcls.yml
│ ├── test-regression-exceptions.yml
│ ├── test-renode.yml
│ ├── test-riscof.yml
│ ├── test-riscv-dv.yml
│ ├── test-uarch.yml
│ ├── test-uvm.yml
│ ├── test-verification.yml
│ ├── verible-format.yml
│ └── verible-lint.yml
├── .gitignore
├── .gitmodules
├── LICENSE
├── MAINTAINERS.md
├── README.md
├── cm.cfg
├── configs/
│ ├── README.md
│ ├── veer.config
│ └── veer_config_gen.py
├── design/
│ ├── dbg/
│ │ └── el2_dbg.sv
│ ├── dec/
│ │ ├── cdecode
│ │ ├── csrdecode_m
│ │ ├── csrdecode_mu
│ │ ├── decode
│ │ ├── el2_dec.sv
│ │ ├── el2_dec_decode_ctl.sv
│ │ ├── el2_dec_gpr_ctl.sv
│ │ ├── el2_dec_ib_ctl.sv
│ │ ├── el2_dec_pmp_ctl.sv
│ │ ├── el2_dec_tlu_ctl.sv
│ │ └── el2_dec_trigger.sv
│ ├── dmi/
│ │ ├── dmi_jtag_to_core_sync.v
│ │ ├── dmi_mux.v
│ │ ├── dmi_wrapper.v
│ │ └── rvjtag_tap.v
│ ├── el2_dma_ctrl.sv
│ ├── el2_mem.sv
│ ├── el2_pic_ctrl.sv
│ ├── el2_pmp.sv
│ ├── el2_veer.sv
│ ├── el2_veer_lockstep.sv
│ ├── el2_veer_wrapper.sv
│ ├── exu/
│ │ ├── el2_exu.sv
│ │ ├── el2_exu_alu_ctl.sv
│ │ ├── el2_exu_div_ctl.sv
│ │ └── el2_exu_mul_ctl.sv
│ ├── flist
│ ├── flist.formal
│ ├── flist.lint
│ ├── flist.questa
│ ├── ifu/
│ │ ├── el2_ifu.sv
│ │ ├── el2_ifu_aln_ctl.sv
│ │ ├── el2_ifu_bp_ctl.sv
│ │ ├── el2_ifu_compress_ctl.sv
│ │ ├── el2_ifu_ic_mem.sv
│ │ ├── el2_ifu_iccm_mem.sv
│ │ ├── el2_ifu_ifc_ctl.sv
│ │ ├── el2_ifu_mem_ctl.sv
│ │ └── el2_ifu_tb_memread.sv
│ ├── include/
│ │ ├── el2_dec_csr_equ_m.svh
│ │ ├── el2_dec_csr_equ_mu.svh
│ │ └── el2_def.sv
│ ├── lib/
│ │ ├── ahb_to_axi4.sv
│ │ ├── axi4_to_ahb.sv
│ │ ├── beh_lib.sv
│ │ ├── el2_lib.sv
│ │ ├── el2_mem_if.sv
│ │ ├── el2_regfile_if.sv
│ │ └── mem_lib.sv
│ └── lsu/
│ ├── el2_lsu.sv
│ ├── el2_lsu_addrcheck.sv
│ ├── el2_lsu_bus_buffer.sv
│ ├── el2_lsu_bus_intf.sv
│ ├── el2_lsu_clkdomain.sv
│ ├── el2_lsu_dccm_ctl.sv
│ ├── el2_lsu_dccm_mem.sv
│ ├── el2_lsu_ecc.sv
│ ├── el2_lsu_lsc_ctl.sv
│ ├── el2_lsu_stbuf.sv
│ └── el2_lsu_trigger.sv
├── docs/
│ ├── Makefile
│ ├── dashboard-styles/
│ │ ├── gcov.css
│ │ └── main.css
│ ├── requirements.txt
│ ├── source/
│ │ ├── adaptations.md
│ │ ├── build-args.md
│ │ ├── cache.md
│ │ ├── clocks.md
│ │ ├── complex-ports.md
│ │ ├── conf.py
│ │ ├── core-control.md
│ │ ├── csrs.md
│ │ ├── debugging.md
│ │ ├── dual-core-lock-step.md
│ │ ├── errata.md
│ │ ├── error-protection.md
│ │ ├── index.md
│ │ ├── interrupt-priority.md
│ │ ├── interrupts.md
│ │ ├── intro.md
│ │ ├── memory-map.md
│ │ ├── overview.md
│ │ ├── performance.md
│ │ ├── physical-memory-protection.md
│ │ ├── power.md
│ │ ├── simulation-debugging.md
│ │ ├── tests.md
│ │ ├── timers.md
│ │ ├── tock.md
│ │ ├── user-mode.md
│ │ └── verification.md
│ └── update_styles.sh
├── release-notes.md
├── requirements.txt
├── testbench/
│ ├── ahb_lite_2to1_mux.sv
│ ├── ahb_lsu_dma_bridge.sv
│ ├── ahb_sif.sv
│ ├── asm/
│ │ ├── bitmanip.s
│ │ ├── cmark.c
│ │ ├── cmark.mki
│ │ ├── cmark_iccm.ld
│ │ ├── cmark_iccm.mki
│ │ ├── common.s
│ │ ├── crt0.s
│ │ ├── dbus_nonblocking_load_error.s
│ │ ├── dbus_store_error.s
│ │ ├── dside_access_across_region_boundary.s
│ │ ├── dside_access_region_prediction_error.s
│ │ ├── dside_core_local_access_unmapped_address_error.s
│ │ ├── dside_pic_access_error.s
│ │ ├── dside_size_misaligned_access_to_non_idempotent_address.s
│ │ ├── ebreak_ecall.s
│ │ ├── hello_world.ld
│ │ ├── hello_world.s
│ │ ├── hello_world_dccm.ld
│ │ ├── hello_world_iccm.ld
│ │ ├── hello_world_iccm.s
│ │ ├── icache.ld
│ │ ├── icache.s
│ │ ├── illegal_instruction.s
│ │ ├── infinite_loop.ld
│ │ ├── infinite_loop.s
│ │ ├── internal_timer_ints.s
│ │ ├── iside_core_local_unmapped_address_error.s
│ │ ├── iside_fetch_precise_bus_error.s
│ │ ├── lsu_trigger_hit.s
│ │ ├── machine_external_ints.s
│ │ ├── machine_external_vec_ints.s
│ │ ├── nmi_pin_assertion.s
│ │ ├── printf.c
│ │ ├── read_after_read.ld
│ │ ├── read_after_read.mki
│ │ ├── read_after_read.s
│ │ └── tb.h
│ ├── axi4_mux/
│ │ ├── arbiter.v
│ │ ├── axi_crossbar.v
│ │ ├── axi_crossbar_addr.v
│ │ ├── axi_crossbar_rd.v
│ │ ├── axi_crossbar_wr.v
│ │ ├── axi_crossbar_wrap_2x1.v
│ │ ├── axi_register_rd.v
│ │ ├── axi_register_wr.v
│ │ └── priority_encoder.v
│ ├── axi_lsu_dma_bridge.sv
│ ├── dasm.svi
│ ├── flist
│ ├── hex/
│ │ ├── user_mode0/
│ │ │ ├── bitmanip.hex
│ │ │ ├── clk_override.hex
│ │ │ ├── cmark.hex
│ │ │ ├── cmark_dccm.hex
│ │ │ ├── cmark_iccm.hex
│ │ │ ├── core_pause.hex
│ │ │ ├── csr_access.hex
│ │ │ ├── csr_misa.hex
│ │ │ ├── csr_mstatus.hex
│ │ │ ├── dbus_nonblocking_load_error.hex
│ │ │ ├── dbus_store_error.hex
│ │ │ ├── dhry.hex
│ │ │ ├── dside_access_across_region_boundary.hex
│ │ │ ├── dside_access_region_prediction_error.hex
│ │ │ ├── dside_core_local_access_unmapped_address_error.hex
│ │ │ ├── dside_pic_access_error.hex
│ │ │ ├── dside_size_misaligned_access_to_non_idempotent_address.hex
│ │ │ ├── ebreak_ecall.hex
│ │ │ ├── ecc.hex
│ │ │ ├── hello_world.hex
│ │ │ ├── hello_world_dccm.hex
│ │ │ ├── hello_world_iccm.hex
│ │ │ ├── icache.hex
│ │ │ ├── illegal_instruction.hex
│ │ │ ├── infinite_loop.hex
│ │ │ ├── insns.hex
│ │ │ ├── internal_timer_ints.hex
│ │ │ ├── irq.hex
│ │ │ ├── iside_core_local_unmapped_address_error.hex
│ │ │ ├── iside_fetch_precise_bus_error.hex
│ │ │ ├── lsu_trigger_hit.hex
│ │ │ ├── machine_external_ints.hex
│ │ │ ├── machine_external_vec_ints.hex
│ │ │ ├── modesw.hex
│ │ │ ├── nmi_pin_assertion.hex
│ │ │ ├── perf_counters.hex
│ │ │ ├── pmp.hex
│ │ │ ├── pmp_random.hex
│ │ │ └── write_unaligned.hex
│ │ └── user_mode1/
│ │ ├── bitmanip.hex
│ │ ├── clk_override.hex
│ │ ├── cmark.hex
│ │ ├── cmark_dccm.hex
│ │ ├── cmark_iccm.hex
│ │ ├── core_pause.hex
│ │ ├── csr_access.hex
│ │ ├── csr_misa.hex
│ │ ├── csr_mseccfg.hex
│ │ ├── csr_mstatus.hex
│ │ ├── dbus_nonblocking_load_error.hex
│ │ ├── dbus_store_error.hex
│ │ ├── dhry.hex
│ │ ├── dside_access_across_region_boundary.hex
│ │ ├── dside_access_region_prediction_error.hex
│ │ ├── dside_core_local_access_unmapped_address_error.hex
│ │ ├── dside_pic_access_error.hex
│ │ ├── dside_size_misaligned_access_to_non_idempotent_address.hex
│ │ ├── ebreak_ecall.hex
│ │ ├── ecc.hex
│ │ ├── hello_world.hex
│ │ ├── hello_world_dccm.hex
│ │ ├── hello_world_iccm.hex
│ │ ├── icache.hex
│ │ ├── illegal_instruction.hex
│ │ ├── infinite_loop.hex
│ │ ├── insns.hex
│ │ ├── internal_timer_ints.hex
│ │ ├── irq.hex
│ │ ├── iside_core_local_unmapped_address_error.hex
│ │ ├── iside_fetch_precise_bus_error.hex
│ │ ├── lsu_trigger_hit.hex
│ │ ├── machine_external_ints.hex
│ │ ├── machine_external_vec_ints.hex
│ │ ├── modesw.hex
│ │ ├── nmi_pin_assertion.hex
│ │ ├── perf_counters.hex
│ │ ├── pmp.hex
│ │ ├── pmp_random.hex
│ │ └── write_unaligned.hex
│ ├── icache_macros.svh
│ ├── input.tcl
│ ├── jtagdpi/
│ │ ├── README.md
│ │ ├── jtagdpi.c
│ │ ├── jtagdpi.h
│ │ └── jtagdpi.sv
│ ├── link.ld
│ ├── openocd_scripts/
│ │ ├── common.tcl
│ │ ├── jtag_cg.tcl
│ │ ├── sim-jtagdpi.cfg
│ │ ├── veer-el2-rst.cfg
│ │ └── verilator-rst.cfg
│ ├── tb_top.sv
│ ├── tb_top_pkg.sv
│ ├── tcp_server/
│ │ ├── tcp_server.c
│ │ └── tcp_server.h
│ ├── test_tb_top.cpp
│ ├── tests/
│ │ ├── clk_override/
│ │ │ ├── clk_override.c
│ │ │ ├── clk_override.ld
│ │ │ ├── clk_override.mki
│ │ │ └── crt0.s
│ │ ├── core_pause/
│ │ │ ├── core_pause.c
│ │ │ ├── core_pause.ld
│ │ │ ├── core_pause.mki
│ │ │ └── crt0.s
│ │ ├── csr_access/
│ │ │ ├── crt0.s
│ │ │ ├── csr_access.c
│ │ │ ├── csr_access.ld
│ │ │ ├── csr_access.mki
│ │ │ └── veer.c
│ │ ├── csr_misa/
│ │ │ ├── crt0.s
│ │ │ ├── csr_misa.c
│ │ │ ├── csr_misa.ld
│ │ │ └── csr_misa.mki
│ │ ├── csr_mseccfg/
│ │ │ ├── crt0.s
│ │ │ ├── csr_mseccfg.c
│ │ │ ├── csr_mseccfg.ld
│ │ │ └── csr_mseccfg.mki
│ │ ├── csr_mstatus/
│ │ │ ├── crt0.s
│ │ │ ├── csr_mstatus.c
│ │ │ ├── csr_mstatus.ld
│ │ │ └── csr_mstatus.mki
│ │ ├── dhry/
│ │ │ ├── dhry.h
│ │ │ ├── dhry.mki
│ │ │ ├── dhry_1.c
│ │ │ └── dhry_2.c
│ │ ├── ecc/
│ │ │ ├── crt0.s
│ │ │ ├── ecc.c
│ │ │ ├── ecc.ld
│ │ │ └── ecc.mki
│ │ ├── insns/
│ │ │ ├── crt0.s
│ │ │ ├── insns.c
│ │ │ ├── insns.ld
│ │ │ └── insns.mki
│ │ ├── irq/
│ │ │ ├── crt0.s
│ │ │ ├── irq.c
│ │ │ ├── irq.ld
│ │ │ └── irq.mki
│ │ ├── modesw/
│ │ │ ├── README.md
│ │ │ ├── crt0.s
│ │ │ ├── modesw.c
│ │ │ ├── modesw.ld
│ │ │ └── modesw.mki
│ │ ├── perf_counters/
│ │ │ ├── crt0.s
│ │ │ ├── perf_counters.c
│ │ │ ├── perf_counters.ld
│ │ │ ├── perf_counters.mki
│ │ │ └── veer.c
│ │ ├── pmp/
│ │ │ ├── crt0.s
│ │ │ ├── fault.c
│ │ │ ├── fault.h
│ │ │ ├── main.c
│ │ │ ├── pmp.c
│ │ │ ├── pmp.h
│ │ │ ├── pmp.ld
│ │ │ ├── pmp.mki
│ │ │ ├── trap.h
│ │ │ ├── veer.c
│ │ │ └── veer.h
│ │ ├── pmp_random/
│ │ │ ├── generate_random.sh
│ │ │ ├── main.c
│ │ │ ├── pmp_random.mki
│ │ │ └── random_data.h
│ │ └── write_unaligned/
│ │ ├── crt0.s
│ │ ├── write_unaligned.c
│ │ ├── write_unaligned.ld
│ │ └── write_unaligned.mki
│ ├── user_cells.sv
│ └── veer_wrapper.sv
├── tools/
│ ├── JSON.pm
│ ├── Makefile
│ ├── addassign
│ ├── coredecode
│ ├── hex_canned_update.sh
│ ├── picmap
│ ├── picolibc.mk
│ ├── prefix_macros.sh
│ ├── renode/
│ │ ├── README.md
│ │ ├── build-all-tests.sh
│ │ ├── veer.repl
│ │ ├── veer.resc
│ │ ├── veer.robot
│ │ └── veer_smepmp.repl
│ ├── riscof/
│ │ ├── README.md
│ │ ├── config.ini
│ │ ├── spike/
│ │ │ ├── env/
│ │ │ │ ├── link.ld
│ │ │ │ └── model_test.h
│ │ │ ├── riscof_spike.py
│ │ │ ├── spike_isa.yaml
│ │ │ └── spike_platform.yaml
│ │ └── veer/
│ │ ├── env/
│ │ │ ├── link.ld
│ │ │ └── model_test.h
│ │ ├── riscof_veer.py
│ │ ├── veer_isa.yaml
│ │ └── veer_platform.yaml
│ ├── riscv-dv/
│ │ ├── Makefile
│ │ ├── README.md
│ │ ├── code_fixup.py
│ │ ├── riscv_core_setting.py
│ │ ├── riscv_core_setting.sv
│ │ ├── testlist.yaml
│ │ ├── user_extension.svh
│ │ ├── veer_directed_instr_lib.sv
│ │ └── veer_log_to_trace_csv.py
│ ├── smalldiv
│ ├── unrollforverilator
│ └── vivado.tcl
├── verification/
│ ├── block/
│ │ ├── .flake8
│ │ ├── __init__.py
│ │ ├── common/
│ │ │ ├── axi.py
│ │ │ ├── csrs.py
│ │ │ └── utils.py
│ │ ├── common.mk
│ │ ├── config.vlt
│ │ ├── dccm/
│ │ │ ├── Makefile
│ │ │ ├── config.vlt
│ │ │ ├── el2_lsu_dccm_mem_wrapper.sv
│ │ │ ├── test_readwrite.py
│ │ │ └── testbench.py
│ │ ├── dcls/
│ │ │ ├── Makefile
│ │ │ ├── cm.cfg
│ │ │ ├── el2_veer_lockstep_wrapper.sv
│ │ │ ├── test_lockstep.py
│ │ │ └── testbench.py
│ │ ├── dec/
│ │ │ ├── Makefile
│ │ │ ├── cm.cfg
│ │ │ ├── el2_dec_wrapper.sv
│ │ │ ├── test_dec.py
│ │ │ └── testbench.py
│ │ ├── dec_ib/
│ │ │ ├── Makefile
│ │ │ ├── config.vlt
│ │ │ ├── el2_dec_ib_ctl_wrapper.sv
│ │ │ ├── test_dec_ib.py
│ │ │ └── testbench.py
│ │ ├── dec_pmp_ctl/
│ │ │ ├── Makefile
│ │ │ ├── cm.cfg
│ │ │ ├── test_dec_pmp_ctl.py
│ │ │ └── testbench.py
│ │ ├── dec_tl/
│ │ │ ├── Makefile
│ │ │ ├── config.vlt
│ │ │ ├── el2_dec_trigger_wrapper.sv
│ │ │ ├── test_dec_tl.py
│ │ │ └── testbench.py
│ │ ├── dec_tlu_ctl/
│ │ │ ├── Makefile
│ │ │ ├── cm.cfg
│ │ │ ├── common.py
│ │ │ ├── el2_tlu_ctl_wrapper.sv
│ │ │ ├── test_dec_tl.py
│ │ │ └── testbench.py
│ │ ├── dma/
│ │ │ ├── Makefile
│ │ │ ├── cm.cfg
│ │ │ ├── scoreboards.py
│ │ │ ├── sequences.py
│ │ │ ├── test_address.py
│ │ │ ├── test_debug_address.py
│ │ │ ├── test_debug_read.py
│ │ │ ├── test_debug_write.py
│ │ │ ├── test_ecc.py
│ │ │ ├── test_read.py
│ │ │ ├── test_reset.py
│ │ │ ├── test_write.py
│ │ │ └── testbench.py
│ │ ├── dmi/
│ │ │ ├── Makefile
│ │ │ ├── cm.cfg
│ │ │ ├── common.py
│ │ │ ├── config.vlt
│ │ │ ├── dmi_agent.py
│ │ │ ├── dmi_bfm.py
│ │ │ ├── dmi_seq.py
│ │ │ ├── dmi_test_wrapper.sv
│ │ │ ├── jtag_agent.py
│ │ │ ├── jtag_bfm.py
│ │ │ ├── jtag_pkg.py
│ │ │ ├── jtag_predictor.py
│ │ │ ├── jtag_seq.py
│ │ │ ├── test_dmi_read_write.py
│ │ │ ├── test_dmi_tap_fsm.py
│ │ │ ├── test_jtag_ir.py
│ │ │ └── testbench.py
│ │ ├── exu_alu/
│ │ │ ├── Makefile
│ │ │ ├── config.vlt
│ │ │ ├── el2_exu_alu_ctl_wrapper.sv
│ │ │ ├── test_arith.py
│ │ │ ├── test_logic.py
│ │ │ ├── test_zba.py
│ │ │ ├── test_zbb.py
│ │ │ ├── test_zbp.py
│ │ │ ├── test_zbs.py
│ │ │ └── testbench.py
│ │ ├── exu_div/
│ │ │ ├── Makefile
│ │ │ ├── config.vlt
│ │ │ ├── el2_exu_div_ctl_wrapper.sv
│ │ │ ├── test_div.py
│ │ │ └── testbench.py
│ │ ├── exu_mul/
│ │ │ ├── Makefile
│ │ │ ├── cm.cfg
│ │ │ ├── config.vlt
│ │ │ ├── el2_exu_mul_ctl_wrapper.sv
│ │ │ ├── test_mul.py
│ │ │ └── testbench.py
│ │ ├── iccm/
│ │ │ ├── Makefile
│ │ │ ├── config.vlt
│ │ │ ├── el2_ifu_iccm_mem_wrapper.sv
│ │ │ ├── test_readwrite.py
│ │ │ └── testbench.py
│ │ ├── ifu_compress/
│ │ │ ├── Makefile
│ │ │ ├── cm.cfg
│ │ │ ├── test_compress.py
│ │ │ └── testbench.py
│ │ ├── ifu_mem_ctl/
│ │ │ ├── Makefile
│ │ │ ├── cm.cfg
│ │ │ ├── common.py
│ │ │ ├── el2_ifu_mem_ctl_wrapper.sv
│ │ │ ├── test_err.py
│ │ │ ├── test_err_stop.py
│ │ │ └── test_miss.py
│ │ ├── lib_ahb_to_axi4/
│ │ │ ├── Makefile
│ │ │ ├── ahb_to_axi4_wrapper.sv
│ │ │ ├── test_read.py
│ │ │ ├── test_write.py
│ │ │ ├── testbench.py
│ │ │ └── ucli.key
│ │ ├── lib_axi4_to_ahb/
│ │ │ ├── Makefile
│ │ │ ├── ahb_lite_agent.py
│ │ │ ├── ahb_lite_bfm.py
│ │ │ ├── ahb_lite_pkg.py
│ │ │ ├── ahb_lite_seq.py
│ │ │ ├── axi_pkg.py
│ │ │ ├── axi_r_agent.py
│ │ │ ├── axi_r_bfm.py
│ │ │ ├── axi_r_seq.py
│ │ │ ├── axi_w_agent.py
│ │ │ ├── axi_w_bfm.py
│ │ │ ├── axi_w_seq.py
│ │ │ ├── cm.cfg
│ │ │ ├── common.py
│ │ │ ├── coordinator_seq.py
│ │ │ ├── test_axi.py
│ │ │ ├── test_axi_read_channel.py
│ │ │ ├── test_axi_write_channel.py
│ │ │ ├── testbench.py
│ │ │ └── ucli.key
│ │ ├── lsu_tl/
│ │ │ ├── Makefile
│ │ │ ├── config.vlt
│ │ │ ├── el2_lsu_trigger_wrapper.sv
│ │ │ ├── test_lsu_tl.py
│ │ │ └── testbench.py
│ │ ├── noxfile.py
│ │ ├── pic/
│ │ │ ├── Makefile
│ │ │ ├── test_clken.py
│ │ │ ├── test_config.py
│ │ │ ├── test_pending.py
│ │ │ ├── test_prioritization.py
│ │ │ ├── test_reset.py
│ │ │ ├── test_servicing.py
│ │ │ └── testbench.py
│ │ ├── pic_gw/
│ │ │ ├── Makefile
│ │ │ └── test_gateway.py
│ │ ├── pmp/
│ │ │ ├── Makefile
│ │ │ ├── common.py
│ │ │ ├── config.vlt
│ │ │ ├── el2_pmp_wrapper.sv
│ │ │ ├── test_address_matching.py
│ │ │ ├── test_multiple_configs.py
│ │ │ ├── test_xwr_access.py
│ │ │ └── testbench.py
│ │ ├── pmp_random/
│ │ │ ├── Makefile
│ │ │ ├── config.vlt
│ │ │ ├── el2_pmp_wrapper.sv
│ │ │ ├── test_pmp_random.py
│ │ │ └── testbench.py
│ │ ├── pyproject.toml
│ │ └── requirements.txt
│ ├── test_debug/
│ │ └── test_debug.py
│ └── top/
│ ├── README.md
│ ├── requirements.txt
│ └── test_pyuvm/
│ ├── Makefile
│ ├── __init__.py
│ ├── cm.cfg
│ ├── conftest.py
│ ├── test_irq/
│ │ ├── irq_utils.py
│ │ ├── irq_uvm.py
│ │ └── test_irq.py
│ └── test_pyuvm.py
└── violations.waiver
================================================
FILE CONTENTS
================================================
================================================
FILE: .github/scripts/breakpoint.sh
================================================
#!/bin/bash
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
set -ex
# Invoke GDB
${GCC_PREFIX}-gdb -n --batch -x breakpoint.gdb >gdb.log
# Parse the log
cat gdb.log | grep 'Breakpoint 1,' >breakpoint.txt
# Compare the dumps
diff -E -y breakpoint.txt breakpoint_golden.txt || true
================================================
FILE: .github/scripts/common.inc.sh
================================================
#!/bin/bash
set -e -u -o pipefail
COLOR_CLEAR="\033[0m"
COLOR_RED="\033[0;31m"
COLOR_GREEN="\033[1;32m"
COLOR_YELLOW="\033[1;33m"
COLOR_WHITE="\033[1;37m"
check_args_count(){
# Check argument count function is meant to be used to check if
# the number of received arguments is equal to the expected.
# If they are unequal, the function returns with error
# Args:
# argc_got - Number of received arguments, e.g.: $#
# argc_expected - Number of expected arguments, e.g.: 2
argc_got=$1
argc_expected=$2
if [ ${argc_got} -ne ${argc_expected} ]; then
echo -e "${COLOR_WHITE}Expected ${argc_expected} arguments, but received ${argc_got} ${COLOR_RED}FAIL${COLOR_CLEAR}"
echo -e "${COLOR_WHITE}Caller:${COLOR_CLEAR}" `caller`
exit 1
fi
}
================================================
FILE: .github/scripts/convert_dat.sh
================================================
#!/bin/bash
DAT_FILE="${1}"
INFO_FILE="${2}"
verilator_coverage --skip-toggle --write-info "${INFO_FILE}_branch.info" "${DAT_FILE}"
verilator_coverage --toggle-only --write-info "${INFO_FILE}_toggle.info" "${DAT_FILE}"
================================================
FILE: .github/scripts/create_merged_package.sh
================================================
#!/bin/bash
set -eux
set -o pipefail
# The script needs to be run with V package prepared in data_v
# and Verilator package prepared in data_verilator.
# Note that config.json will contain output of this script.
# It will be basically data_v/config.json with "datasets" key removed
# so that it's regenerated by info-process with minor other modifications.
python3 <<END >config.json
import json
with open('data_v/config.json') as f:
config = json.load(f)
with open('data_verilator/config.json') as f:
verilator_config = json.load(f)
db_count_v = config['additional'].pop('db_count')
config['additional']['db_count_verilator'] = verilator_config['additional']['db_count']
config['additional']['db_count_v'] = db_count_v
config['timestamp'] = '`date +"%Y-%m-%dT%H:%M:%S.%3N%z"`'
del config['datasets']
print(json.dumps(config, indent=2))
END
_out_dir=data_both
# The order of INFO files influences order of datasets that will be
# generated based on passed INFO files and added to config.json.
info-process pack --output $_out_dir --config config.json \
--coverage-files data_v/*.info data_verilator/*.info \
--description-files data_verilator/*.desc data_v/*.desc \
--extra-files data_v/logo.svg
cat $_out_dir/config.json
echo "Merged coverage data ready to be packaged in $PWD/$_out_dir"
================================================
FILE: .github/scripts/gdb_test.sh
================================================
#!/bin/bash
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# This script runs Verilator RTL simulation and OpenOCD in background, invokes
# the supplied test command and shuts everything down.
SIM_LOG=`realpath sim.log`
OPENOCD_LOG=`realpath openocd.log`
GDB_LOG=`realpath gdb.log`
if [ -z $GCC_PREFIX ]; then
GCC_PREFIX=riscv64-unknown-elf
fi
# Ensure that RISC-V toolchain is installed
if ! which ${GCC_PREFIX}-gcc >/dev/null; then
GCC_PREFIX=riscv32-unknown-elf
fi
if ! which ${GCC_PREFIX}-gcc >/dev/null; then
echo "RISC-V toolchain not found, please refer to https://github.com/chipsalliance/caliptra-rtl?tab=readme-ov-file#riscv-toolchain-installation for more details."
exit 1
fi
export GCC_PREFIX
set +e
# Utils
source `dirname ${BASH_SOURCE[0]}`/utils.sh
terminate_all () {
terminate ${OPENOCD_PID}
echo "waiting for the simulation to end: $SIM_PID"
wait ${SIM_PID}
# terminate ${SIM_PID}
}
print_logs () {
echo -e "${COLOR_WHITE}======== OpenOCD log ========${COLOR_OFF}"
cat ${OPENOCD_LOG} || true
echo -e "${COLOR_WHITE}======== Simulation log ========${COLOR_OFF}"
cat ${SIM_LOG} || true
echo -e "${COLOR_WHITE}======== GDB log ========${COLOR_OFF}"
cat ${GDB_LOG} || true
}
echo -e "${COLOR_WHITE}======== Launching interactive simulation ========${COLOR_OFF}"
# Start the simulation
echo -e "Starting simulation..."
if [ -f obj_dir/Vtb_top ]; then
SIM_START_STRING="VerilatorTB: Start of sim"
obj_dir/Vtb_top >"${SIM_LOG}" 2>&1 &
elif [ -f ./simv ]; then
SIM_START_STRING=" remote_bitbang_port 5000"
./simv +vcs+lic+wait -cm line+cond+fsm+tgl+branch >"${SIM_LOG}" 2>&1 &
else
echo "No simulation binary found, exiting"
exit 1
fi
SIM_PID=$!
# Wait
wait_for_phrase "${SIM_LOG}" "${SIM_START_STRING}"
sleep 1s
retcode=$?
if [ $retcode -ne 0 ]; then
echo -e "${COLOR_RED}Failed to start the simulation: $retcode ${COLOR_OFF}"
print_logs
terminate_all; exit -1
fi
echo -e "Simulation running and ready (pid=${SIM_PID})"
# Launch OpenOCD
echo -e "Launching OpenOCD..."
WORKDIR=$PWD
cd ${RV_ROOT}/.github/scripts/openocd
openocd -d2 --file board/caliptra-verilator.cfg > ${OPENOCD_LOG} 2>&1 &
OPENOCD_PID=$!
cd $WORKDIR
# Wait
wait_for_phrase "${OPENOCD_LOG}" "Listening on port 3333 for gdb connections"
if [ $? -ne 0 ]; then
echo -e "${COLOR_RED}Failed to start OpenOCD!${COLOR_OFF}"
print_logs
terminate_all; exit -1
fi
echo -e "OpenOCD running and ready (pid=${OPENOCD_PID})"
# Wait a bit
sleep 1s
# Run the test
echo -e "${COLOR_WHITE}======== Running GDB script test.gdb ========${COLOR_OFF}"
${GCC_PREFIX}-gdb -n --batch -x ${RV_ROOT}/.github/scripts/test.gdb > "${GDB_LOG}" &
GDB_PID=$!
# The simulation must end naturally in order to produce coverage data.
wait ${SIM_PID}
# OpenOCD waits endlessly for the target (Vtb_top) to reconnect.
# Kill OpenoCD and GDB in case they're stuck
kill -s SIGKILL ${OPENOCD_PID} || true
kill -s SIGKILL ${GDB_PID} || true
# Display logs
print_logs
# Parse the log, extract register values. Skip those which change as the
# program executes since we don't know at which point we tap in.
grep -E '^ra |^sp |^gp |^tp |^t[01256] |^s[0-9]+ |^a[0-9]+ |^\$[0-9]+ |^\$ |^Hardware |^Breakpoint' "${GDB_LOG}" > gdb_test_dump.txt
gdb_output_golden=${RV_ROOT}/.github/scripts/gdb_test_golden.txt
grep -q "TEST_PASSED" "${SIM_LOG}"
tb_passed=$?
# Compare the dumps
diff -E -y ${gdb_output_golden} gdb_test_dump.txt
gdb_output_match=$?
if [ "$tb_passed" -ne 0 ]; then
echo "Testbench failed. The test did not write 0xff to the mailbox to indicate success."
exit 1
fi
echo "Testbench passed."
if [ "$gdb_output_match" -ne 0 ]; then
echo "The output from GDB doesn't match the golden reference. See ${gdb_output_golden}"
exit 1
fi
echo "The output from GDB matches the golden reference."
echo "TEST PASSED"
================================================
FILE: .github/scripts/gdb_test_golden.txt
================================================
ra 0x5f555555 0x5f555555
sp 0x0 0x0
gp 0x4 0x4
tp 0x0 0x0
t0 0x0 0
t1 0x0 0
t2 0x0 0
s1 0x0 0
a0 0x0 0
a1 0x0 0
a2 0x0 0
a3 0x0 0
a4 0x0 0
a5 0x0 0
a6 0x0 0
a7 0x0 0
s2 0x0 0
s3 0x0 0
s4 0x0 0
s5 0x0 0
s6 0x0 0
s7 0x0 0
s8 0x0 0
s9 0x0 0
s10 0x0 0
s11 0x0 0
t5 0x0 0
t6 0x0 0
$1 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}
$2 = 0x55555555
$3 = 0xaaaaaaaa
$4 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}
$5 = 0x55555555
$6 = 0xaaaaaaaa
$7 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}
$8 = 0x55555555
$9 = 0xaaaaaaaa
$10 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}
$11 = 0x55555555
$12 = 0xaaaaaaaa
$13 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}
$14 = 0x55555555
$15 = 0xaaaaaaaa
$16 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}
$17 = 0x55555555
$18 = 0xaaaaaaaa
$19 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}
$20 = 0x55555555
$21 = 0xaaaaaaaa
$22 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}
$23 = 0x55555555
$24 = 0xaaaaaaaa
$25 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}
$26 = 0x55555555
$27 = 0xaaaaaaaa
$28 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}
$29 = 0x55555555
$30 = 0xaaaaaaaa
$31 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}
$32 = 0x55555555
$33 = 0xaaaaaaaa
$34 = {0x1234567, 0x89abcdef, 0x55555555, 0xaaaaaaaa}
$35 = 0x55555555
$36 = 0xaaaaaaaa
Hardware assisted breakpoint 1 at 0x1c
Breakpoint 1, 0x0000001c in ?? ()
================================================
FILE: .github/scripts/get_code_hash.sh
================================================
#!/bin/bash
# This script is responsible for computing hash for RISCV-DV generated programs
# cache.
HASHES=()
HASHES+=($(git submodule status third_party/riscv-dv | cut -d\ -f2))
HASHES+=($(sha256sum tools/riscv-dv/code_fixup.py | cut -d\ -f1))
HASHES+=($(sha256sum tools/riscv-dv/testlist.yaml | cut -d\ -f1))
HASHES+=($(sha256sum tools/riscv-dv/riscv_core_setting.sv | cut -d\ -f1))
HASHES+=($(sha256sum tools/riscv-dv/Makefile | cut -d\ -f1))
HASHES+=($(sha256sum tools/riscv-dv/user_extension.svh | cut -d\ -f1))
HASHES+=($(sha256sum tools/riscv-dv/veer_directed_instr_lib.sv | cut -d\ -f1))
echo ${HASHES[@]} | sha256sum | cut -d\ -f1
================================================
FILE: .github/scripts/indexgen/.gitignore
================================================
build
source
================================================
FILE: .github/scripts/indexgen/Makefile
================================================
SPHINXOPTS ?=
SPHINXBUILD ?= sphinx-build
SOURCEDIR = source.template
GENDIR = source
BUILDDIR ?= build
ROOTDIR ?= work
all: clean html
# Sources
SOURCES = $(wildcard $(SOURCEDIR)/*.md)
# Generate sources
$(GENDIR):
@mkdir -p $@
$(GENDIR)/index.md: $(SOURCES) generate.py | $(GENDIR)
@rm -rf $(GENDIR)/*
@python3 generate.py --template "$(SOURCEDIR)" --root "$(ROOTDIR)/html" --output "$(GENDIR)"
# Build the final webpage. Pass the 'html' target to sphinx, copy report pages
html: Makefile $(GENDIR)/index.md
@$(SPHINXBUILD) -M $@ "$(GENDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
@rsync -avrm --include="*/" --include="coverage_dashboard/***" --include="verification_dashboard/***" --include="docs_rendered/***" --exclude="*" "$(ROOTDIR)/" "$(BUILDDIR)/"
@bash update_styles.sh "$(BUILDDIR)"
clean:
@rm -rf $(BUILDDIR)
@rm -rf $(GENDIR)
.PHONY: all clean html
================================================
FILE: .github/scripts/indexgen/dashboard-styles/gcov.css
================================================
/* All views: initial background and text color */
@import url('https://fonts.googleapis.com/css2?family=Roboto:wght@400;700&display=swap');
body
{
color: #E9EBFA;
background-color: #0E1116;
padding: 0;
margin: 0;
font-family: 'Roboto', sans-serif;
box-sizing: border-box;
}
/* * {
} */
/* All views: standard link format*/
a:link
{
color: #00D0C9;
text-decoration: underline;
font-family: 'Roboto', sans-serif;
}
/* All views: standard link - visited format */
a:visited
{
color: #E9EBFA;
text-decoration: underline;
}
/* All views: standard link - activated format */
a:active
{
color: #00D0C9;
color: #E9EBFA;
text-decoration: underline;
}
th {
border: 1px solid;
}
td {
color: #E9EBFA;
}
body > table:nth-child(1) > tbody > tr:nth-child(3)
{
height: 300px;
}
body > center > table td:not(.coverBarOutline){
border: 1px solid #31363C;
}
body > center > table > tbody > tr:nth-child(1) {
display: none;
}
body>table:nth-child(1)>tbody>tr:nth-child(3) {
display: flex;
}
body > table:nth-child(1) > tbody > tr:nth-child(3) > td {
align-self: center;
padding: 0 95px;
}
body > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(1) > td.headerValue {
font-size: 35px;
}
body>table:nth-child(1)>tbody>tr:nth-child(3)>td>table>tbody>tr:nth-child(1)>td.headerItem {
font-weight: 300;
font-size: 35px;
}
body > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(1) > td.headerValue {
font-size: 35px;
}
body > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(2) > td.headerItem {
font-size: 22px;
font-weight: 300;
}
body > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(2) > td.headerValue {
font-size: 22px;
}
body > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(3) > td.headerItem {
font-size: 22px;
font-weight: 300;
}
body > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(3) > td.headerValue {
font-size: 22px;
}
body > table:nth-child(1) > tbody > tr:nth-child(1) {
position: relative;
}
body > table:nth-child(1) > tbody > tr:nth-child(1) > td::before {
content: url(../../../_static/white.svg);
position: absolute;
left: 95px;
transform: translateY(-15%);
}
table {
border-collapse: collapse;
width: 100%;
}
body > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody {
padding: 0 50px;
}
body > center > table > tbody tr {
width: 19px;
}
/* All views: main title format */
td.title
{
background-color: #25292E;
color: #DFE1F1;
text-align: center;
padding-bottom: 10px;
font-size: 20px;
font-weight: bold;
padding: 20px 0;
}
/* All views: header item format */
td.headerItem
{
text-align: right;
padding-right: 6px;
font-weight: bold;
white-space: nowrap;
}
/* All views: header item value format */
td.headerValue
{
text-align: left;
color: #00D0C9;
font-weight: bold;
white-space: nowrap;
}
body > table:nth-child(1) > tbody > tr:nth-child(3) > td > table > tbody > tr:nth-child(1) > td:nth-child(5)::after {
content: ' ';
width: 10px;
}
/* All views: header item coverage table heading */
td.headerCovTableHead
{
color: #DFE1F1;
text-align: center;
padding-right: 6px;
padding-left: 6px;
padding-bottom: 0px;
font-size: 14px;
white-space: nowrap;
}
/* All views: header item coverage table entry */
td.headerCovTableEntry
{
text-align: right;
color: #DFE1F1;
text-align: center;
background-color: #31363C;
font-weight: bold;
white-space: nowrap;
padding-left: 12px;
padding-right: 4px;
}
/* All views: header item coverage table entry for high coverage rate */
td.headerCovTableEntryHi
{
text-align: right;
color: #000000;
font-weight: bold;
white-space: nowrap;
padding-left: 12px;
padding-right: 4px;
background-color: #2FC36E;
}
/* All views: header item coverage table entry for medium coverage rate */
td.headerCovTableEntryMed
{
text-align: right;
color: #000000;
font-weight: bold;
white-space: nowrap;
padding-left: 12px;
padding-right: 4px;
background-color: #EFAC0A;
}
/* All views: header item coverage table entry for ow coverage rate */
td.headerCovTableEntryLo
{
text-align: right;
color: #DFE1F1;
text-align: center;
font-weight: bold;
white-space: nowrap;
padding-left: 12px;
padding-right: 4px;
background-color: #F21E08;
}
/* All views: header legend value for legend entry */
td.headerValueLeg
{
text-align: left;
color: #000000;
font-size: 80%;
white-space: nowrap;
padding-top: 4px;
}
body>table:nth-child(1)>tbody>tr:nth-child(2)>td {
display: none;
}
/* All views: color of horizontal ruler */
td.ruler > img
{
height: 1px ;
width: 100% ;
background-color: rgba(255, 255, 255, 0.3);
aspect-ratio: 1 / 1;
}
/* All views: version string format */
td.versionInfo
{
text-align: center;
padding-top: 35px;
font-style: italic;
}
td.versionInfo > a
{
color: #00D0C9;
}
/* Directory view/File view (all)/Test case descriptions:
table headline format */
td.tableHead
{
text-align: center;
color: #ffffff;
background-color: #0E1116;
font-size: 16px;
font-weight: bold;
white-space: nowrap;
padding-left: 4px;
padding-right: 4px;
}
span.tableHeadSort
{
padding-right: 4px;
}
td
{
align-items: center;
}
center {
padding: 95px;
}
/* Directory view/File view (all): filename entry format */
td.coverFile
{
text-align: left;
padding-left: 10px;
padding-right: 20px;
color: #E9EBFA;
background-color: #0E1116;
font-family: monospace;
}
/* Directory view/File view (all): bar-graph entry format*/
td.coverBar
{
background-color: #0E1116;
}
/* Directory view/File view (all): bar-graph outline color */
td.coverBarOutline
{
background-color: #0E1116;
display: flex;
justify-content: center;
}
/* Directory view/File view (all): percentage entry for files with
high coverage rate */
td.coverPerHi
{
text-align: right;
padding-left: 10px;
padding-right: 10px;
background-color: #0E1116;
color: #2FC36E;
font-weight: bold;
}
/* Directory view/File view (all): line count entry for files with
high coverage rate */
td.coverNumHi
{
text-align: right;
padding-left: 10px;
padding-right: 10px;
background-color: #0E1116;
white-space: nowrap;
}
/* Directory view/File view (all): percentage entry for files with
medium coverage rate */
td.coverPerMed
{
text-align: right;
padding-left: 10px;
padding-right: 10px;
color: #EFAC0A;
background-color: #0E1116;
font-weight: bold;
}
/* Directory view/File view (all): line count entry for files with
medium coverage rate */
td.coverNumMed
{
text-align: right;
padding-left: 10px;
padding-right: 10px;
background-color: #0E1116;
white-space: nowrap;
}
/* Directory view/File view (all): percentage entry for files with
low coverage rate */
td.coverPerLo
{
text-align: right;
padding-left: 10px;
padding-right: 10px;
color: #F21E08;
background-color: #0E1116;
font-weight: bold;
}
/* Directory view/File view (all): line count entry for files with
low coverage rate */
td.coverNumLo
{
text-align: right;
padding-left: 10px;
padding-right: 10px;
background-color: #0E1116;
white-space: nowrap;
}
/* File view (all): "show/hide details" link format */
a.detail:link
{
color: #B8D0FF;
font-size:80%;
}
/* File view (all): "show/hide details" link - visited format */
a.detail:visited
{
color: #B8D0FF;
font-size:80%;
}
/* File view (all): "show/hide details" link - activated format */
a.detail:active
{
color: #ffffff;
font-size:80%;
}
/* File view (detail): test name entry */
td.testName
{
text-align: right;
padding-right: 10px;
background-color: #dae7fe;
}
/* File view (detail): test percentage entry */
td.testPer
{
text-align: right;
padding-left: 10px;
padding-right: 10px;
background-color: #dae7fe;
}
/* File view (detail): test lines count entry */
td.testNum
{
text-align: right;
padding-left: 10px;
padding-right: 10px;
background-color: #dae7fe;
}
/* Test case descriptions: test name format*/
dt
{
font-weight: bold;
}
/* Test case descriptions: description table body */
td.testDescription
{
padding-top: 10px;
padding-left: 30px;
padding-bottom: 10px;
padding-right: 30px;
background-color: #dae7fe;
}
/* Source code view: function entry */
td.coverFn
{
text-align: left;
padding-left: 10px;
padding-right: 20px;
color: #284fa8;
background-color: #dae7fe;
font-family: monospace;
}
/* Source code view: function entry zero count*/
td.coverFnLo
{
text-align: right;
padding-left: 10px;
padding-right: 10px;
background-color: #ff0000;
font-weight: bold;
}
/* Source code view: function entry nonzero count*/
td.coverFnHi
{
text-align: right;
padding-left: 10px;
padding-right: 10px;
background-color: #dae7fe;
font-weight: bold;
}
/* Source code view: source code format */
pre.source
{
font-family: monospace;
white-space: pre;
margin-top: 2px;
}
/* Source code view: line number format */
span.lineNum
{
background-color: #efe383;
}
/* Source code view: format for lines which were executed */
td.lineCov,
span.lineCov
{
background-color: #cad7fe;
}
/* Source code view: format for Cov legend */
span.coverLegendCov
{
padding-left: 10px;
padding-right: 10px;
padding-bottom: 2px;
background-color: #cad7fe;
}
/* Source code view: format for lines which were not executed */
td.lineNoCov,
span.lineNoCov
{
background-color: #ff6230;
}
/* Source code view: format for NoCov legend */
span.coverLegendNoCov
{
padding-left: 10px;
padding-right: 10px;
padding-bottom: 2px;
background-color: #ff6230;
}
/* Source code view (function table): standard link - visited format */
td.lineNoCov > a:visited,
td.lineCov > a:visited
{
color: #000000;
text-decoration: underline;
}
/* Source code view: format for lines which were executed only in a
previous version */
span.lineDiffCov
{
background-color: #b5f7af;
}
/* Source code view: format for branches which were executed
* and taken */
span.branchCov
{
background-color: #cad7fe;
}
/* Source code view: format for branches which were executed
* but not taken */
span.branchNoCov
{
background-color: #ff6230;
}
/* Source code view: format for branches which were not executed */
span.branchNoExec
{
background-color: #ff6230;
}
/* Source code view: format for the source code heading line */
pre.sourceHeading
{
white-space: pre;
font-family: monospace;
font-weight: bold;
margin: 0px;
}
/* All views: header legend value for low rate */
td.headerValueLegL
{
text-align: center;
white-space: nowrap;
padding-left: 4px;
padding-right: 2px;
background-color: #ff0000;
font-size: 80%;
}
/* All views: header legend value for med rate */
td.headerValueLegM
{
text-align: center;
white-space: nowrap;
padding-left: 2px;
padding-right: 2px;
background-color: #ffea20;
font-size: 80%;
}
/* All views: header legend value for hi rate */
td.headerValueLegH
{
text-align: center;
white-space: nowrap;
padding-left: 2px;
padding-right: 4px;
background-color: #a7fc9d;
font-size: 80%;
}
/* All views except source code view: legend format for low coverage */
span.coverLegendCovLo
{
padding-left: 10px;
padding-right: 10px;
padding-top: 2px;
background-color: #ff0000;
}
/* All views except source code view: legend format for med coverage */
span.coverLegendCovMed
{
padding-left: 10px;
padding-right: 10px;
padding-top: 2px;
background-color: #ffea20;
}
/* All views except source code view: legend format for hi coverage */
span.coverLegendCovHi
{
padding-left: 10px;
padding-right: 10px;
padding-top: 2px;
background-color: #a7fc9d;
}
================================================
FILE: .github/scripts/indexgen/dashboard-styles/main.css
================================================
[data-md-color-scheme="slate"] {
--md-hue: 218;
--md-default-bg-color: hsla(var(--md-hue), 22%, 7%, 1);
}
[data-md-color-primary="teal"] {
--md-primary-fg-color: #25292e;
}
[data-md-color-scheme="slate"][data-md-color-primary="teal"] {
--md-typeset-a-color: #00d0c9;
}
.md-social {
display: none;
}
.md-header__option {
display: none;
}
================================================
FILE: .github/scripts/indexgen/generate.py
================================================
#!/usr/bin/env python3
import argparse
import os
import shutil
import logging
import jinja2
# ==============================================================================
def render_template(src, dst, **kwargs):
"""
Renders a jinja2 template file to another file
"""
with open(src, "r") as fp:
tpl = jinja2.Template(fp.read())
with open(dst, "w") as fp:
fp.write(tpl.render(**kwargs))
# ==============================================================================
def make_coverage_report_index(branch, root, output, templates):
"""
Prepares coverage report index page
"""
logging.debug("=== make_coverage_report_index")
logging.debug(f"branch = {branch}")
logging.debug(f"root = {root}")
logging.debug(f"output = {output}")
logging.debug(f"templates = {templates}")
logging.debug("===")
keys = ["all", "branch", "toggle", "functional"]
path = os.path.join(root, "coverage_dashboard")
# Collect summary reports
summary = {k: None for k in keys}
for key in keys:
file = key
fname = os.path.join(path, file)
if os.path.isdir(fname):
summary[key] = file
# Collect individual test reports
individual = {k: dict() for k in keys}
for key in keys:
pfx = key + "_"
if not os.path.isdir(path):
continue
for file in sorted(os.listdir(path)):
fname = os.path.join(path, file)
if not os.path.isdir(fname):
continue
if not file.startswith(pfx):
continue
# Extract test name
test_name = file[len(pfx):]
# Append the report
individual[key][test_name] = file
# Render the template
params = {
"ref": branch + "_coverage_dashboard",
"summary": summary,
"individual": individual,
}
os.makedirs(output, exist_ok=True)
render_template(
os.path.join(templates, "coverage_dashboard.md"),
os.path.join(output, "coverage_dashboard.md"),
**params
)
def make_verification_report_index(branch, root, output, templates):
"""
Prepares verification tests report index page
"""
logging.debug("=== make_verification_report_index")
logging.debug(f"branch = {branch}")
logging.debug(f"root = {root}")
logging.debug(f"output = {output}")
logging.debug(f"templates = {templates}")
logging.debug("===")
path = os.path.join(root, "verification_dashboard")
# Collect tests
tests = set()
if os.path.isdir(path):
for file in sorted(os.listdir(path)):
if not file.startswith("webpage_"):
continue
test_name = file.replace("webpage_", "")
tests.add(test_name)
# Render the template
params = {
"ref": branch + "_verification_dashboard",
"tests": tests,
}
os.makedirs(output, exist_ok=True)
render_template(
os.path.join(templates, "verification_dashboard.md"),
os.path.join(output, "verification_dashboard.md"),
**params
)
def make_dev_index(branches, output, templates):
"""
Prepares the branch/pr index page
"""
logging.debug("=== make_dev_index")
logging.debug(f"branches = {branches}")
logging.debug(f"output = {output}")
logging.debug(f"templates = {templates}")
logging.debug("===")
params = {
"branches": branches,
}
render_template(
os.path.join(templates, "dev.md"),
os.path.join(output, "dev.md"),
**params
)
# ==============================================================================
def main():
logging.basicConfig(encoding="utf-8", level=logging.DEBUG)
# Parse args
parser = argparse.ArgumentParser()
parser.add_argument(
"--template",
type=str,
required=True,
help="Templates path",
)
parser.add_argument(
"--root",
type=str,
default=None,
help="Existing webpage root path",
)
parser.add_argument(
"--output",
type=str,
required=True,
help="Output path",
)
args = parser.parse_args()
# Check
if os.path.abspath(args.root) == os.path.abspath(args.output):
print("Error: Existing webpage root and output paths mustn't be the same")
exit(-1)
# Reports for the main branch
make_coverage_report_index(
"main",
os.path.join(args.root, "main"),
os.path.join(args.output, "main"),
args.template
)
make_verification_report_index(
"main",
os.path.join(args.root, "main"),
os.path.join(args.output, "main"),
args.template
)
# Reports for development branches / pull requests
branches = []
path = os.path.join(args.root, "dev")
if os.path.isdir(path):
for file in os.listdir(path):
if not os.path.isdir(os.path.join(path, file)):
continue
branches.append(file)
make_coverage_report_index(
file,
os.path.join(args.root, "dev", file),
os.path.join(args.output, "dev", file),
args.template
)
make_verification_report_index(
file,
os.path.join(args.root, "dev", file),
os.path.join(args.output, "dev", file),
args.template
)
# Prepare the branch/pr index page
make_dev_index(branches, args.output, args.template)
# Copy other files/pages
files = [
"conf.py",
"main.md",
"index.md",
]
for file in files:
shutil.copy(
os.path.join(args.template, file),
os.path.join(args.output, file),
)
if __name__ == "__main__":
main()
================================================
FILE: .github/scripts/indexgen/index_redirect/index.html
================================================
<!DOCTYPE html>
<html>
<head>
<meta http-equiv="refresh" content="0; url='https://chipsalliance.github.io/Cores-VeeR-EL2/html/index.html'" />
</head>
<body>
</body>
</html>
================================================
FILE: .github/scripts/indexgen/requirements.txt
================================================
myst-parser
sphinx
sphinx_tabs
sphinxcontrib-mermaid
https://github.com/antmicro/sphinx-immaterial/releases/download/tip/sphinx_immaterial-0.0.post1.tip-py3-none-any.whl
https://github.com/antmicro/antmicro-sphinx-utils/archive/main.zip
jinja2
================================================
FILE: .github/scripts/indexgen/source.template/conf.py
================================================
# -*- coding: utf-8 -*-
#
# This file is execfile()d with the current directory set to its containing dir.
#
# Note that not all possible configuration values are present in this file.
#
# All configuration values have a default; values that are commented out
# serve to show the default.
#
# Updated documentation of the configuration options is available at
# https://www.sphinx-doc.org/en/master/usage/configuration.html
from datetime import datetime
from antmicro_sphinx_utils.defaults import (
numfig_format,
extensions as default_extensions,
myst_enable_extensions as default_myst_enable_extensions,
antmicro_html,
)
# If extensions (or modules to document with autodoc) are in another directory,
# add these directories to sys.path here. If the directory is relative to the
# documentation root, use os.path.abspath to make it absolute, like shown here.
#sys.path.insert(0, os.path.abspath('.'))
# -- General configuration -----------------------------------------------------
# General information about the project.
project = u'RISC-V VeeR-EL2 Core'
basic_filename = u'veer-test-reports'
authors = u'CHIPS Alliance'
copyright = f'{authors}, {datetime.now().year}'
# The short X.Y version.
version = ''
# The full version, including alpha/beta/rc tags.
release = ''
# This is temporary before the clash between myst-parser and immaterial is fixed
sphinx_immaterial_override_builtin_admonitions = False
numfig = True
# If you need to add extensions just add to those lists
extensions = default_extensions
myst_enable_extensions = default_myst_enable_extensions
myst_substitutions = {
"project": project
}
myst_url_schemes = {
"http": None,
"https": None,
"external": "{{path}}",
}
today_fmt = '%Y-%m-%d'
todo_include_todos=False
# -- Options for HTML output ---------------------------------------------------
html_theme = 'sphinx_immaterial'
html_last_updated_fmt = today_fmt
html_show_sphinx = False
(
html_logo,
html_theme_options,
html_context
) = antmicro_html()
html_theme_options["palette"][0].update({
"scheme": "slate",
"primary": "teal",
"accent": "white",
})
# # Disable toggle theme button
# html_theme_options = {
# "palette": []
# }
html_title = project
def setup(app):
app.add_css_file('main.css')
================================================
FILE: .github/scripts/indexgen/source.template/coverage_dashboard.md
================================================
({{ ref }})=
# Coverage dashboard
## Summary reports (all tests)
{%- for coverage in summary %}
{%- if summary[coverage] %}
* [{{ coverage }} coverage](external:coverage_dashboard/{{ summary[coverage] }}/index.html)
{%- else %}
* {{ coverage }} coverage (no data)
{%- endif %}
{%- endfor %}
## Individual test reports
{%- for coverage in individual %}
### {{ coverage }} coverage
{%- if individual[coverage] %}
{%- for test in individual[coverage] %}
* [{{ test }}](external:coverage_dashboard/{{ individual[coverage][test] }}/index.html)
{%- endfor %}
{%- else %}
no data
{%- endif %}
{%- endfor %}
================================================
FILE: .github/scripts/indexgen/source.template/dev.md
================================================
# Active pull requests
{%- for branch in branches %}
* {{ branch }}
* [Coverage]({{ branch }}_coverage_dashboard)
* [Verification tests]({{ branch }}_verification_dashboard)
* [Documentation](external:dev/{{ branch }}/docs_rendered/html/index.html)
{%- endfor %}
================================================
FILE: .github/scripts/indexgen/source.template/index.md
================================================
# {{ project }}
```{toctree}
:maxdepth: 2
main
dev
```
================================================
FILE: .github/scripts/indexgen/source.template/main.md
================================================
# Main branch
* [Coverage](main_coverage_dashboard)
* [Verification tests](main_verification_dashboard)
* [Documentation](external:main/docs_rendered/html/index.html)
================================================
FILE: .github/scripts/indexgen/source.template/verification_dashboard.md
================================================
({{ ref }})=
# Verification tests dashboard
## Test reports
{%- for test in tests %}
* [{{ test }}](external:verification_dashboard/webpage_{{ test }}/{{ test }}.html)
{%- endfor %}
* [RISCOF tests report](external:verification_dashboard/riscof/report.html)
================================================
FILE: .github/scripts/indexgen/update_styles.sh
================================================
#!/bin/bash
SELF_DIR="$(dirname $(readlink -f ${BASH_SOURCE[0]}))"
. ${SELF_DIR}/../common.inc.sh
update_styles(){
# Update styles for sphinx theme and LCOV reports
# Args:
# BUILDDIR - path to where the webpage is made
BUILD_DIR=$1
echo -e "${COLOR_WHITE}========== Update styles =========${COLOR_CLEAR}"
echo -e "${COLOR_WHITE} BUILD_DIR = ${BUILD_DIR}${COLOR_CLEAR}"
# Replace styles for sphinx build
cp dashboard-styles/main.css ${BUILD_DIR}/html/_static/
# Add CHIPs logo
cp dashboard-styles/assets/chips-alliance-logo-mono.svg ${BUILD_DIR}/html/_static/white.svg
# Replace undesired CSS and progress bar sprites with desired style for LCOV reports
copy_files(){
check_args_count $# 2
SOURCE=$1
SEARCH=$2
FILES=`find ${BUILD_DIR}/ -name ${SEARCH}`
for FILE in ${FILES}; do
echo "Copy ${SOURCE} to ${FILE}"
cp $SOURCE $FILE
done
}
CHIPS_GCOV_CSS=dashboard-styles/gcov.css
AMBER=dashboard-styles/assets/amber.png
RUBY=dashboard-styles/assets/ruby.png
SNOW=dashboard-styles/assets/snow.png
EMERALD=dashboard-styles/assets/emerald.png
for ASSET in $CHIPS_GCOV_CSS $AMBER $RUBY $SNOW $EMERALD; do
echo -e "${COLOR_WHITE}========== $ASSET =========${COLOR_CLEAR}"
copy_files $ASSET $(basename "$ASSET")
done
echo -e "${COLOR_WHITE}Update styles ${COLOR_GREEN}SUCCEEDED${COLOR_CLEAR}"
echo -e "${COLOR_WHITE}==========================${COLOR_CLEAR}"
}
# Example usage
# BUILD_DIR=./build
# update_styles.sh $BUILD_DIR
check_args_count $# 1
update_styles "$@"
================================================
FILE: .github/scripts/info_process_setup.sh
================================================
#!/bin/bash
set -ex
apt update
apt install -y git pipx
# By default pipx uses `/root/.local/bin` which isn't in PATH.
export PIPX_BIN_DIR=/usr/local/bin
pipx install git+https://github.com/antmicro/info-process@1d1fa64f
================================================
FILE: .github/scripts/mapfile
================================================
map el2_exu_alu_ctl el2_exu_alu_ctl_wrapper.alu tb_top.rvtop_wrapper.rvtop.veer.exu.i_alu
map el2_exu_mul_ctl el2_exu_mul_ctl_wrapper.mul tb_top.rvtop_wrapper.rvtop.veer.exu.i_mul
map el2_exu_div_ctl el2_exu_div_ctl_wrapper.div tb_top.rvtop_wrapper.rvtop.veer.exu.i_div
map dmi_jtag_to_core_sync dmi_test_wrapper.wrapper.i_dmi_jtag_to_core_sync tb_top.rvtop_wrapper.rvtop.dmi_wrapper.i_dmi_jtag_to_core_sync
map rvjtag_tap dmi_test_wrapper.wrapper.i_jtag_tap tb_top.rvtop_wrapper.rvtop.dmi_wrapper.i_jtag_tap
map el2_ifu_iccm_mem el2_ifu_iccm_mem_wrapper.mem tb_top.rvtop_wrapper.rvtop.mem.iccm.iccm
map el2_lsu_dccm_mem el2_lsu_dccm_mem_wrapper.mem tb_top.rvtop_wrapper.rvtop.mem.Gen_dccm_enable.dccm
map el2_ifu_compress_ctl el2_ifu_compress_ctl tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0
map el2_pic_ctrl el2_pic_ctrl tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst
map el2_pmp el2_pmp_wrapper.pmp tb_top.rvtop_wrapper.rvtop.veer.pmp
map el2_dec_ib_ctl el2_dec_ib_ctl_wrapper.tu tb_top.rvtop_wrapper.rvtop.veer.dec.instbuff
map el2_dec_trigger el2_dec_trigger_wrapper.tu tb_top.rvtop_wrapper.rvtop.veer.dec.dec_trigger
map el2_dma_ctrl el2_dma_ctrl tb_top.rvtop_wrapper.rvtop.veer.dma_ctrl
map dmi_mux dmi_test_wrapper.mux tb_top.rvtop_wrapper.rvtop.dmi_mux
map dmi_wrapper dmi_test_wrapper.wrapper tb_top.rvtop_wrapper.rvtop.dmi_wrapper
map el2_configurable_gw 'el2_pic_ctrl.IO_CLK_GRP[0].GW[1].gw_inst' 'tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst.IO_CLK_GRP[0].GW[1].gw_inst'
map el2_configurable_gw 'el2_pic_ctrl.IO_CLK_GRP[0].GW[2].gw_inst' 'tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst.IO_CLK_GRP[0].GW[2].gw_inst'
map el2_configurable_gw 'el2_pic_ctrl.IO_CLK_GRP[0].GW[3].gw_inst' 'tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst.IO_CLK_GRP[0].GW[3].gw_inst'
map el2_configurable_gw 'el2_pic_ctrl.IO_CLK_GRP[1].GW[0].gw_inst' 'tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst.IO_CLK_GRP[1].GW[0].gw_inst'
map el2_configurable_gw 'el2_pic_ctrl.IO_CLK_GRP[1].GW[1].gw_inst' 'tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst.IO_CLK_GRP[1].GW[1].gw_inst'
map el2_configurable_gw 'el2_pic_ctrl.IO_CLK_GRP[1].GW[2].gw_inst' 'tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst.IO_CLK_GRP[1].GW[2].gw_inst'
map el2_configurable_gw 'el2_pic_ctrl.IO_CLK_GRP[1].GW[3].gw_inst' 'tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst.IO_CLK_GRP[1].GW[3].gw_inst'
map el2_cmp_and_mux 'el2_pic_ctrl.genblock.LEVEL[0].COMPARE[0].cmp_l1' 'tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst.genblock.LEVEL[0].COMPARE[0].cmp_l1'
map el2_cmp_and_mux 'el2_pic_ctrl.genblock.LEVEL[0].COMPARE[1].cmp_l1' 'tb_top.rvtop_wrapper.rvtop.veer.pic_ctrl_inst.genblock.LEVEL[0].COMPARE[1].cmp_l1'
================================================
FILE: .github/scripts/openocd/board/caliptra-verilator-rst.cfg
================================================
source [find sim-jtagdpi.cfg]
source [find veer-el2-rst.cfg]
# Increase timeouts in simulation
riscv set_command_timeout_sec 300
================================================
FILE: .github/scripts/openocd/board/caliptra-verilator.cfg
================================================
source [find sim-jtagdpi.cfg]
source [find veer-el2.cfg]
# Increase timeouts in simulation
riscv set_command_timeout_sec 300
================================================
FILE: .github/scripts/openocd/sim-jtagdpi.cfg
================================================
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
# "JTAG adapter" for simulation, exposed to OpenOCD through a TCP socket
# speaking the remote_bitbang protocol. The adapter is implemented as
# SystemVerilog DPI module.
adapter driver remote_bitbang
remote_bitbang port 5000
remote_bitbang host localhost
================================================
FILE: .github/scripts/openocd/veer-el2-rst.cfg
================================================
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME riscv
}
jtag newtap $_CHIPNAME tap -irlen 5
set _TARGETNAME $_CHIPNAME.tap
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread
# Configure work area in on-chip SRAM
$_TARGETNAME.0 configure -work-area-phys 0x50001000 -work-area-size 0x1000 -work-area-backup 0
# Mem access mode
riscv set_mem_access sysbus
# The following commands disable target examination and set explicitly the
# core parameters read from CSRs. These required a modified version of
# OpenOCD from https://github.com/antmicro/openocd/tree/riscv-nohalt
riscv set_nohalt on
riscv set_xlen 32
riscv set_misa 0x40001104
# Be verbose about GDB errors
gdb_report_data_abort enable
gdb_report_register_access_error enable
# Always use hardware breakpoints.
gdb_breakpoint_override hard
================================================
FILE: .github/scripts/openocd/veer-el2.cfg
================================================
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME riscv
}
jtag newtap $_CHIPNAME tap -irlen 5
set _TARGETNAME $_CHIPNAME.tap
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME -rtos hwthread
# Configure work area in on-chip SRAM
$_TARGETNAME.0 configure -work-area-phys 0x50001000 -work-area-size 0x1000 -work-area-backup 0
$_TARGETNAME.0 configure -event gdb-detach {
resume
}
$_TARGETNAME.0 riscv expose_csrs 1968=dcsr
$_TARGETNAME.0 riscv expose_csrs 1969=dpc
$_TARGETNAME.0 riscv expose_csrs 1988=dmst
$_TARGETNAME.0 riscv expose_csrs 1992=dicawics
$_TARGETNAME.0 riscv expose_csrs 1996=dicad0h
$_TARGETNAME.0 riscv expose_csrs 1993=dicad0
$_TARGETNAME.0 riscv expose_csrs 1994=dicad1
$_TARGETNAME.0 riscv expose_csrs 1995=dicago
proc write_icache_line {dicawics_ dicad0_ dicad0h_ dicad1_} {
# 1. Write dicawics
reg csr_dicawics $dicawics_
# 2. Write instruction data to dicad0 and dicad0h, and parity to dicad1
reg csr_dicad0 $dicad0_
reg csr_dicad0h $dicad0h_
reg csr_dicad1 $dicad1_
# 3. Write 1 to dicago to trigger Icache write operation
reg csr_dicago 1
}
proc read_icache_line {dicawics_} {
# 1. Write dicawics
reg csr_dicawics $dicawics_
# 2. Read to dicago to trigger Icache read operation
reg csr_dicago
# 3. get line chunk from dicad0 and dicad0h, and parity from dicad1
reg csr_dicad0
reg csr_dicad0h
reg csr_dicad1
}
proc write_icache_tag {dicawics_ dicad0_ dicad1_} {
# 1. Write dicawics
reg csr_dicawics $dicawics_
# 2. Write tag, valid, LRU information to dicad0, and parity to dicad1
reg csr_dicad0 $dicad0_
reg csr_dicad1 $dicad1_
# 3. Write 1 to dicago to trigger Icache write operation
reg csr_dicago 1
}
proc read_icache_tag {dicawics_} {
# 1. Write dicawics
reg csr_dicawics $dicawics_
# 2. Read to dicago to trigger Icache read operation
reg csr_dicago
# 3. get tag from dicad0, and parity from dicad1
reg csr_dicad0
reg csr_dicad1
}
$_TARGETNAME.0 configure -event halted {
echo "Starting ICache line read"
# dicawics: array=0 way=1 index=1
set dicawics_value [expr {(0 << 24) | (1 << 20) | (1 << 5)}]
read_icache_line $dicawics_value
echo "Starting ICache line write"
# Write instruction data to dicad0 and dicad0h
set dicad0_value 0x30c00
set dicad0h_value 0xc00c0
# Write wrong parity to trigger error
set dicad1_value 0xffffaaaa
# iterate to perform write for many values of index
for {set index 0} {$index < 5} {incr index} {
# dicawics: array=0 way=1
set dicawics_value [expr {(0 << 24) | (1 << 20) | ($index << 5)}]
write_icache_line $dicawics_value $dicad0_value $dicad0h_value $dicad1_value
}
echo "Starting ICache tag and status read"
read_icache_tag $dicawics_value
echo "Starting ICache tag and status write"
# Write tag, valid, LRU information are in dicad0, parity is in dicad1
set dicad0_value 0xfcb
set dicad1_value 0xffffffff
for {set index 0} {$index < 5} {incr index} {
# dicawics: array=1 way=1
set dicawics_value [expr {(1 << 24) | (1 << 20) | ($index << 5)}]
write_icache_tag $dicawics_value $dicad0_value $dicad1_value
}
echo "ICache test done."
}
# Mem access mode
riscv set_mem_access abstract
# Be verbose about GDB errors
gdb_report_data_abort enable
gdb_report_register_access_error enable
# Always use hardware breakpoints.
gdb_breakpoint_override hard
================================================
FILE: .github/scripts/openocd_test.sh
================================================
#!/bin/bash
# SPDX-License-Identifier: Apache-2.0
# Copyright 2024 Antmicro <www.antmicro.com>
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# This script runs Verilator RTL simulation in background and invokes OpenOCD
# to perform JTAG access test
SIM_LOG=`realpath sim.log`
OPENOCD_LOG=`realpath openocd.log`
set +e
if [ "$#" -lt 1 ]; then
echo "Usage: openocd_test.sh [openocd args ...]"
exit 1
fi
OPENOCD_ARGS=$@
# Utils
source `dirname ${BASH_SOURCE[0]}`/utils.sh
print_logs () {
echo -e "${COLOR_WHITE}======== Simulation log ========${COLOR_OFF}"
cat ${SIM_LOG} || true
echo -e "${COLOR_WHITE}======== OpenOCD log ========${COLOR_OFF}"
cat ${OPENOCD_LOG} || true
}
echo -e "${COLOR_WHITE}======== Launching interactive simulation ========${COLOR_OFF}"
# Start the simulation
echo -e "Starting simulation..."
if [ -f obj_dir/Vtb_top ]; then
SIM_START_STRING="VerilatorTB: Start of sim"
obj_dir/Vtb_top >"${SIM_LOG}" 2>&1 &
elif [ -f ./simv ]; then
SIM_START_STRING=" remote_bitbang_port 5000"
./simv +vcs+lic+wait -cm line+cond+fsm+tgl+branch >"${SIM_LOG}" 2>&1 &
else
echo "No simulation binary found, exiting"
exit 1
fi
SIM_PID=$!
# Wait
wait_for_phrase "${SIM_LOG}" "${SIM_START_STRING}"
if [ $? -ne 0 ]; then
echo -e "${COLOR_RED}Failed to start the simulation!${COLOR_OFF}"
print_logs
terminate ${SIM_PID}; exit -1
fi
echo -e "Simulation running and ready (pid=${SIM_PID})"
# Wait a bit
sleep 2s
# Run the test
echo -e "${COLOR_WHITE}======== Running OpenOCD test '$@' ========${COLOR_OFF}"
cd ${RV_ROOT}/testbench/openocd_scripts && openocd -d2 ${OPENOCD_ARGS} >"${OPENOCD_LOG}" 2>&1
EXITCODE=$?
if [ ${EXITCODE} -eq 0 ]; then
echo -e "${COLOR_GREEN}[PASSED]${COLOR_OFF}"
else
echo -e "${COLOR_RED}[FAILED]${COLOR_OFF}"
fi
# Display logs
print_logs
wait $SIM_PID
# Honor the exitcode
exit ${EXITCODE}
================================================
FILE: .github/scripts/peripheral_access.tcl
================================================
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
init
set script_dir [file dirname [info script]]
source [file join $script_dir common.tcl]
# Manually read dmstatus and check if the core is actually held in external
# reset. In the expected state bits anyunavail allrunning anyrunning allhalted
# and anyhalted should be cleared.
set val [riscv dmi_read $dmstatus_addr]
puts "dmstatus: $val"
if { ($val & 0x00000F00) != 0 } {
echo "The core is not held in reset!"
shutdown error
}
echo "Accessing ECC..."
set golden { 0x63707365 0x38342d33 0x3030312e 0x0 }
set actual [ read_memory 0x10008000 32 4 phys ]
if {[compare $actual $golden] != 0} {
shutdown error
}
echo "Accessing HMAC..."
set golden { 0x6163686d 0x61327368 0x3030322e 0x0 }
set actual [ read_memory 0x10010000 32 4 phys ]
if {[compare $actual $golden] != 0} {
shutdown error
}
echo "Accessing SHA512..."
set golden { 0x61327368 0x31322d35 0x3830302e 0x0 }
set actual [ read_memory 0x10020000 32 4 phys ]
if {[compare $actual $golden] != 0} {
shutdown error
}
echo "Accessing SHA256..."
set golden { 0x61327368 0x35362d32 0x3830312e 0x0 }
set actual [ read_memory 0x10028000 32 4 phys ]
if {[compare $actual $golden] != 0} {
shutdown error
}
echo "Writing and reading DOE IV..."
set golden { 0xCAFEBABA 0xDEADBEEF 0xD0ED0E00 }
write_memory 0x10000000 32 $golden phys
set actual [ read_memory 0x10000000 32 3 phys ]
if {[compare $actual $golden] != 0} {
shutdown error
}
# Success
shutdown
================================================
FILE: .github/scripts/prepare_coverage_data.sh
================================================
#!/bin/bash
set -eu
set -o pipefail
if [ -v CI ]
then
set -x
apt update
apt install -y xz-utils
# XZ compresses .info files A LOT better than GZIP, e.g., 9.4MB vs 175MB.
tar acf ${SIM}_coverage_single_data.tar.xz info_files_$SIM
ls info_files_$SIM
fi
DB_COUNT=`ls info_files_$SIM | sed 's#_[^_]*.info##' | sort | uniq | wc -l`
# Filter out lockstep and el2_regfile_if modules if DCLS tests are not enabled
if [ -v DCLS_ENABLE ]
then
_filter_out=''
else
_filter_out='--filter-out (lockstep|el2_regfile_if)'
fi
# Source path transformations are needed before merging to have matching paths in `.desc` files.
find info_files_$SIM -name '*.info' -exec info-process transform \
--strip-file-prefix '.*Cores-VeeR-EL2/' \
--filter 'design/' $_filter_out \
{} \;
if [ $SIM = verilator ]
then
# Split branch and line before merging to have correct data in `.desc` files.
for FILE in info_files_$SIM/*_branch.info
do
info-process extract --coverage-type line --output ${FILE%%_branch.info}_line.info $FILE
info-process extract --coverage-type cond --output ${FILE%%_branch.info}_cond.info $FILE
# Extract branch coverage last, so that it can happen in-place
info-process extract --coverage-type branch --output $FILE $FILE
done
fi
for TYPE in branch line toggle cond
do
_sort_opt=''
_transform_extra_opts=''
if [ $SIM = verilator ] && [ $TYPE = toggle ]
then
_sort_opt=--sort-brda-names
_transform_extra_opts='--set-block-ids --add-two-way-toggles --add-missing-brda-entries'
fi
info-process merge --output coverage_${TYPE}_$SIM.info $_sort_opt \
--test-list tests_${TYPE}_$SIM.desc --test-list-strip coverage_,_$TYPE.info \
info_files_$SIM/*_$TYPE.info
info-process transform --normalize-hit-counts $_transform_extra_opts coverage_${TYPE}_$SIM.info
done
rm -rf info_files_$SIM
if [ -z "${GITHUB_HEAD_REF}" ]; then
# We're in merge triggered run
export BRANCH=$GITHUB_REF_NAME
else
# We're in PR triggered run
export BRANCH=$GITHUB_HEAD_REF
fi
export COMMIT=$GITHUB_SHA
# Add config.json template, "datasets" will be generated by info-process.
cat <<END >config.json
{
"title": "VeeR EL2 coverage dashboard",
"commit": "$COMMIT",
"branch": "$BRANCH",
"repo": "cores-veer-el2",
"timestamp": "`date +"%Y-%m-%dT%H:%M:%S.%3N%z"`",
"additional": {
"db_count": "$DB_COUNT",
"run_id": "$GITHUB_RUN_ID"
}
}
END
_out_dir=data_$SIM
info-process pack --output $_out_dir --config config.json \
--coverage-files *_$SIM.info --description-files *_$SIM.desc
rm config.json *_$SIM.info *_$SIM.desc
# add logo
cp docs/dashboard-styles/assets/chips-alliance-logo-mono.svg $_out_dir/logo.svg
cat $_out_dir/config.json
echo "Coverage data ready to be packaged in $PWD/$_out_dir"
================================================
FILE: .github/scripts/pytest/bar.html
================================================
<script src="script/script.js"></script>
<div class="bar">
<a onclick="previousPage()" class="arrow">
<img src="./assets/arrow.svg" alt="back" />
</a>
<a class="chip-alliance-link" href="https://chipsalliance.github.io/Cores-VeeR-EL2/html/index.html">
<img src="./assets/chips-alliance-logo-mono.svg" alt="chips-alliance-logo" />
</a>
<span class="title">test_pyuvm_branch.html</span>
</div>
================================================
FILE: .github/scripts/pytest/css/styles.css
================================================
@import url("https://fonts.googleapis.com/css2?family=Roboto:wght@400;500;700&display=swap");
body {
background-color: #0e1116;
font-family: "Roboto", sans-serif;
margin: 0;
padding: 0;
}
body > *:not(:nth-child(3)) {
max-width: 1520px;
margin-left: auto;
margin-right: auto;
}
body > input:first-of-type {
margin-left: max(0px, (100% - 1520px) / 2);
}
h1,
h2,
span,
p {
color: #dfe1f1;
font-size: 16px;
}
h1,
h2 {
font-size: 24px;
font-weight: 500;
margin-top: 75px;
}
a {
color: #00d0c9;
}
.passed {
color: #2fc36e;
font-size: 14px;
margin-left: 5px !important;
}
.xfailed,
.skipped {
color: #efac0a;
font-size: 14px;
margin-left: 5px !important;
}
.failed,
.error,
.xpassed {
color: #f21e08;
font-size: 14px;
margin-left: 5px !important;
}
.col-name,
.col-duration {
color: #dfe1f1;
font-size: 14px;
}
.sortable {
color: #dfe1f1;
font-size: 16px;
}
.log {
background-color: #31363c;
color: #dfe1f1;
overflow: auto;
}
.bar {
display: inline-flex;
width: 100%;
padding: 20px;
align-items: center;
background-color: #25292e;
box-sizing: border-box;
}
.bar > .arrow {
width: 30px;
height: 30px;
cursor: pointer;
}
.bar > .chip-alliance-link {
position: absolute;
left: max(150px, (100% - 1520px) / 2);
}
.bar > .title {
position: absolute;
left: 50%;
transform: translateX(-50%);
font-size: 20px;
font-weight: 700;
}
#environment {
color: #dfe1f1;
width: 100%;
}
#environment tr:nth-child(odd) {
background: none;
}
#environment td:first-child {
width: 25%;
}
#results-table {
color: #dfe1f1;
}
#yaml-table {
color: #dfe1f1;
}
================================================
FILE: .github/scripts/pytest/script/script.js
================================================
function previousPage() {
window.history.back()
}
================================================
FILE: .github/scripts/pytest/style_pytest_report.sh
================================================
#!/bin/bash
SELF_DIR="$(dirname $(readlink -f ${BASH_SOURCE[0]}))"
. ${SELF_DIR}/../common.inc.sh
style_pytest_report(){
check_args_count $# 3
SRC_DIR=$1
DST_DIR=$2
HTML_FILE=$3
echo -e "${COLOR_WHITE}========== style_pytest_report =========${COLOR_CLEAR}"
echo -e "${COLOR_WHITE} SRC_DIR = ${SRC_DIR}${COLOR_CLEAR}"
echo -e "${COLOR_WHITE} DST_DIR = ${DST_DIR}${COLOR_CLEAR}"
echo -e "${COLOR_WHITE} HTML_FILE = ${HTML_FILE}${COLOR_CLEAR}"
# Copy assets
mkdir -p ${DST_DIR}/assets
cp ${SRC_DIR}/assets/* ${DST_DIR}/assets/
# Add bar above h1.title
SEARCH="<h1>"
REPLACE=`cat ${SRC_DIR}/bar.html | tr '\n' ' '`
REPLACE="$REPLACE $SEARCH"
filename="${DST_DIR}/${HTML_FILE}"
sed -i "s@$SEARCH@$REPLACE@" $filename
# Copy JS script to build dir
mkdir -p ${DST_DIR}/script
cp -r ${SRC_DIR}/script/* ${DST_DIR}/script/
echo -e "${COLOR_WHITE}Style pytest report ${COLOR_GREEN}SUCCEEDED${COLOR_CLEAR}"
echo -e "${COLOR_WHITE}========== style_pytest_report =========${COLOR_CLEAR}"
}
check_args_count $# 3
style_pytest_report "$@"
================================================
FILE: .github/scripts/requirements-coverage.txt
================================================
git+https://github.com/antmicro/sitespawner@abff708256a15a5db7c498ff7f484c78cf18d4e3
================================================
FILE: .github/scripts/riscv_dv_matrix_include.py
================================================
from yaml import load, Loader
from json import dumps
from itertools import product
import sys
RISCV_DV_TESTS = ['riscv_arithmetic_basic_test']
if __name__ == "__main__":
arg1 = sys.argv[1].strip()
# Entries with pyflow for every RISCV_DV_TESTS.
# These are included in `generate` job matrix but it's also a base for `run*` jobs.
entries = [{
"test": test,
"version": "pyflow",
} for test in RISCV_DV_TESTS]
# The argument passed needs to match the job name as variants are generated based on its matrix.
if arg1.startswith('run'):
with open('.github/workflows/test-riscv-dv.yml', 'rb') as fd:
run_tests = load(fd, Loader=Loader)['jobs'][arg1]
job_matrix = run_tests['strategy']['matrix']
# Replicate matrix entries for all variants based on the job's matrix keys and values.
#
# For example, if the matrix only has `test`, `version` and `iss` keys, and `iss` values
# are `renode` and `spike`, then `entries` will be doubled after `key=iss` iteration as
# each entry will be replaced by two entries: one with additional `iss: renode` argument
# and the other with additional `iss: spike`.
for key in job_matrix.keys():
if key in ['test', 'version', 'include', 'exclude']:
continue
entries = [{**entry, key: value} for entry, value in product(entries, job_matrix[key])]
print(dumps(entries))
elif arg1 == 'generate':
print(dumps(entries))
else:
exit(1)
================================================
FILE: .github/scripts/riscv_dv_parse_testlist.py
================================================
import sys
import os
from json import dumps
from yaml import load, Loader
from typing import Generator
RISCV_DV_HOME = "third_party/riscv-dv/"
def parse_yaml(path: str) -> Generator[str, None, None]:
with open(path, 'rb') as fd:
tests = load(fd, Loader=Loader)
for test in tests:
if 'import' in test:
import_path = test['import'].split('/', 1)[1]
yield from parse_yaml(RISCV_DV_HOME + import_path)
elif 'test' in test:
yield test['test']
if __name__ == "__main__":
if len(sys.argv) == 2:
testlist = RISCV_DV_HOME + f'target/{sys.argv[1]}/testlist.yaml'
# check if testlist.yaml is provided by RISCV-DV; if not - it's a
# custom testlist file not provided by RISCV-DV by default; treat the
# script argument as full a path
if not os.path.isdir(testlist):
testlist = sys.argv[1]
testlist = parse_yaml(testlist)
else:
testlist = parse_yaml(RISCV_DV_HOME + 'yaml/base_testlist.yaml')
testlist = list(testlist)
# remove, will cause incomplete sim, need customized RTL
testlist.remove("riscv_csr_test")
print(dumps(testlist))
================================================
FILE: .github/scripts/run_regression_test.sh
================================================
#!/bin/bash
SELF_DIR="$(dirname $(readlink -f ${BASH_SOURCE[0]}))"
. ${SELF_DIR}/common.inc.sh
trap report_status EXIT
report_status(){
rc=$?
if [ $rc != 0 ]; then
echo -e "${COLOR_WHITE}Test '${NAME}' ${COLOR_RED}FAILED${COLOR_CLEAR}"
else
mv ${DIR}/coverage.dat ${RESULTS_DIR}/
echo -e "${COLOR_WHITE}Test '${NAME}' ${COLOR_GREEN}SUCCEEDED${COLOR_CLEAR}"
fi
exit $rc
}
run_regression_test(){
# Run a regression test with coverage collection enabled
# Args:
# RESULTS_DIR -
# BUS -
# NAME -
# COVERAGE -
# USER_MODE - '1' for user mode, '0' for without user mode
# CACHE WAYPACK -
check_args_count $# 6
RESULTS_DIR=$1
BUS=$2
NAME=$3
COVERAGE=$4
USER_MODE=$5
ICACHE_WAYPACK=$6
echo -e "${COLOR_WHITE}========== running test '${NAME}' =========${COLOR_CLEAR}"
echo -e "${COLOR_WHITE} RESULTS_DIR = ${RESULTS_DIR}${COLOR_CLEAR}"
echo -e "${COLOR_WHITE} SYSTEM BUS = ${BUS}${COLOR_CLEAR}"
echo -e "${COLOR_WHITE} NAME = ${NAME}${COLOR_CLEAR}"
echo -e "${COLOR_WHITE} COVERAGE = ${COVERAGE}${COLOR_CLEAR}"
echo -e "${COLOR_WHITE} USER_MODE = ${USER_MODE}${COLOR_CLEAR}"
echo -e "${COLOR_WHITE} ICACHE_WAYPACK = ${ICACHE_WAYPACK}${COLOR_CLEAR}"
COMMON_PARAMS="-set bitmanip_zba -set bitmanip_zbb -set bitmanip_zbc -set bitmanip_zbe -set bitmanip_zbf -set bitmanip_zbp -set bitmanip_zbr -set bitmanip_zbs -set=fpga_optimize=0"
if [[ "${USER_MODE}" == "1" ]]; then
COMMON_PARAMS="-set=user_mode=1 -set=smepmp=1 ${COMMON_PARAMS}"
fi
# DLCS_ENABLE may not be set
set +u
if [[ -z "${DCLS_ENABLE}" ]]; then
DCLS_ENABLE="0"
fi
set -u
if [[ "${DCLS_ENABLE}" == "1" ]]; then
COMMON_PARAMS="-set lockstep_enable=1 -set lockstep_regfile_enable=1 ${COMMON_PARAMS}"
fi
COMMON_PARAMS="-set=icache_waypack=${ICACHE_WAYPACK} ${COMMON_PARAMS}"
if [[ "${BUS}" == "axi" ]]; then
PARAMS="-set build_axi4 ${COMMON_PARAMS}"
elif [[ "${BUS}" == "ahb" ]]; then
PARAMS="-set build_ahb_lite ${COMMON_PARAMS}"
else
echo -e "${COLOR_RED}Unknown system bus type '${BUS}'${COLOR_CLEAR}"
exit 1
fi
echo -e "${COLOR_WHITE} CONF PARAMS = ${PARAMS}${COLOR_CLEAR}"
mkdir -p ${RESULTS_DIR}
LOG="${RESULTS_DIR}/test_${NAME}_${COVERAGE}_${USER_MODE}.log"
touch ${LOG}
DIR="run_${NAME}_${COVERAGE}_${USER_MODE}"
if [ "$NAME" = "pmp_random" ]; then
EXTRA_ARGS='TB_MAX_CYCLES=8000000'
else
EXTRA_ARGS=
fi
# Run the test
mkdir -p ${DIR}
make -j`nproc` -C ${DIR} -f $RV_ROOT/tools/Makefile verilator $EXTRA_ARGS CONF_PARAMS="${PARAMS}" TEST=${NAME} COVERAGE=${COVERAGE} 2>&1 | tee ${LOG}
}
# Example usage
# RESULTS_DIR=results
# BUS=axi
# NAME=hello_world
# COVERAGE=branch
# USER_MODE=1
# run_regression_test.sh $RESULTS_DIR $BUS $NAME $COVERAGE $USER_MODE
check_args_count $# 6
run_regression_test "$@"
================================================
FILE: .github/scripts/run_regression_tests.sh
================================================
#!/bin/bash
COLOR_CLEAR="\033[0m"
COLOR_WHITE="\033[1;37m"
COLOR_RED="\033[0;31m"
COLOR_GREEN="\033[1;32m"
RESULTS_DIR="results"
mkdir -p ${RESULTS_DIR}
# Configure VeeR
echo -e "${COLOR_WHITE}==================== Configuring VeeR-EL2 core ====================${COLOR_CLEAR}"
$RV_ROOT/configs/veer.config
if [ $? -ne 0 ]; then
echo "Failed to configure VeeR-EL2 core"
exit -1
fi
# Run regression tests with coverage collection enabled
EXITCODE=0
TESTS=($TESTS)
for NAME in ${TESTS[@]}; do
echo -e "${COLOR_WHITE}==================== running test '${NAME}' ====================${COLOR_CLEAR}"
for COVERAGE in branch toggle functional; do
echo -e "${COLOR_WHITE}========== ${COVERAGE} coverage ==========${COLOR_CLEAR}"
LOG="${RESULTS_DIR}/test_${NAME}_${COVERAGE}.log"
DIR="run_${NAME}_${COVERAGE}"
# Run the test
mkdir -p ${DIR}
make -j`nproc` -C ${DIR} -f $RV_ROOT/tools/Makefile verilator TEST=${NAME} COVERAGE=${COVERAGE} 2>&1 | tee ${LOG}
RES=${PIPESTATUS[0]}
if [ ${RES} -ne 0 ] || ! [ -f "${DIR}/coverage.dat" ]; then
EXITCODE=-1
echo -e "${COLOR_WHITE}Test '${NAME}' ${COLOR_RED}FAILED${COLOR_CLEAR}"
else
# Copy and convert coverage data
cp ${DIR}/coverage.dat ${RESULTS_DIR}/coverage_${NAME}_${COVERAGE}.dat
verilator_coverage --write-info ${RESULTS_DIR}/coverage_${NAME}_${COVERAGE}.info ${RESULTS_DIR}/coverage_${NAME}_${COVERAGE}.dat
echo -e "${COLOR_WHITE}Test '${NAME}' ${COLOR_GREEN}SUCCEEDED${COLOR_CLEAR}"
fi
done
done
exit ${EXITCODE}
================================================
FILE: .github/scripts/secrets_version
================================================
3
================================================
FILE: .github/scripts/test.gdb
================================================
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
echo Connecting to OpenOCD...\n
set architecture riscv:rv32
set remotetimeout 360
target extended-remote :3333
echo Dumping registers...\n
info registers
echo Accessing region at 0x20000000...\n
set *(0x20000000) = 0x01234567
set *(0x20000004) = 0x89ABCDEF
set *(0x20000008) = 0x55555555
set *(0x2000000C) = 0xAAAAAAAA
set *(0x25555550) = 0x55555555
set *(0x2aaaaaa0) = 0xAAAAAAAA
print/x *0x20000000@4
print/x *0x25555550
print/x *0x2aaaaaa0
echo Accessing region at 0x30000000...\n
set *(0x30000000) = 0x01234567
set *(0x30000004) = 0x89ABCDEF
set *(0x30000008) = 0x55555555
set *(0x3000000C) = 0xAAAAAAAA
set *(0x35555550) = 0x55555555
set *(0x3aaaaaa0) = 0xAAAAAAAA
print/x *0x30000000@4
print/x *0x35555550
print/x *0x3aaaaaa0
echo Accessing region at 0x40000000...\n
set *(0x40000000) = 0x01234567
set *(0x40000004) = 0x89ABCDEF
set *(0x40000008) = 0x55555555
set *(0x4000000C) = 0xAAAAAAAA
set *(0x45555550) = 0x55555555
set *(0x4aaaaaa0) = 0xAAAAAAAA
print/x *0x40000000@4
print/x *0x45555550
print/x *0x4aaaaaa0
echo Accessing region at 0x50000000...\n
set *(0x50000000) = 0x01234567
set *(0x50000004) = 0x89ABCDEF
set *(0x50000008) = 0x55555555
set *(0x5000000C) = 0xAAAAAAAA
set *(0x55555550) = 0x55555555
set *(0x5aaaaaa0) = 0xAAAAAAAA
print/x *0x50000000@4
print/x *0x55555550
print/x *0x5aaaaaa0
echo Accessing region at 0x60000000...\n
set *(0x60000000) = 0x01234567
set *(0x60000004) = 0x89ABCDEF
set *(0x60000008) = 0x55555555
set *(0x6000000C) = 0xAAAAAAAA
set *(0x65555550) = 0x55555555
set *(0x6aaaaaa0) = 0xAAAAAAAA
print/x *0x60000000@4
print/x *0x65555550
print/x *0x6aaaaaa0
echo Accessing region at 0x70000000...\n
set *(0x70000000) = 0x01234567
set *(0x70000004) = 0x89ABCDEF
set *(0x70000008) = 0x55555555
set *(0x7000000C) = 0xAAAAAAAA
set *(0x75555550) = 0x55555555
set *(0x7aaaaaa0) = 0xAAAAAAAA
print/x *0x70000000@4
print/x *0x75555550
print/x *0x7aaaaaa0
echo Accessing region at 0x80000000...\n
set *(0x80000000) = 0x01234567
set *(0x80000004) = 0x89ABCDEF
set *(0x80000008) = 0x55555555
set *(0x8000000C) = 0xAAAAAAAA
set *(0x85555550) = 0x55555555
set *(0x8aaaaaa0) = 0xAAAAAAAA
print/x *0x80000000@4
print/x *0x85555550
print/x *0x8aaaaaa0
echo Accessing region at 0x90000000...\n
set *(0x90000000) = 0x01234567
set *(0x90000004) = 0x89ABCDEF
set *(0x90000008) = 0x55555555
set *(0x9000000C) = 0xAAAAAAAA
set *(0x95555550) = 0x55555555
set *(0x9aaaaaa0) = 0xAAAAAAAA
print/x *0x90000000@4
print/x *0x95555550
print/x *0x9aaaaaa0
echo Accessing region at 0xa0000000...\n
set *(0xa0000000) = 0x01234567
set *(0xa0000004) = 0x89ABCDEF
set *(0xa0000008) = 0x55555555
set *(0xa000000C) = 0xAAAAAAAA
set *(0xa5555550) = 0x55555555
set *(0xaaaaaaa0) = 0xAAAAAAAA
print/x *0xa0000000@4
print/x *0xa5555550
print/x *0xaaaaaaa0
echo Accessing region at 0xb0000000...\n
set *(0xb0000000) = 0x01234567
set *(0xb0000004) = 0x89ABCDEF
set *(0xb0000008) = 0x55555555
set *(0xb000000C) = 0xAAAAAAAA
set *(0xb5555550) = 0x55555555
set *(0xbaaaaaa0) = 0xAAAAAAAA
print/x *0xb0000000@4
print/x *0xb5555550
print/x *0xbaaaaaa0
echo Accessing region at 0xc0000000...\n
set *(0xc0000000) = 0x01234567
set *(0xc0000004) = 0x89ABCDEF
set *(0xc0000008) = 0x55555555
set *(0xc000000C) = 0xAAAAAAAA
set *(0xc5555550) = 0x55555555
set *(0xcaaaaaa0) = 0xAAAAAAAA
print/x *0xc0000000@4
print/x *0xc5555550
print/x *0xcaaaaaa0
echo Accessing region at 0xd0000000...\n
set *(0xd0000000) = 0x01234567
set *(0xd0000004) = 0x89ABCDEF
set *(0xd0000008) = 0x55555555
set *(0xd000000C) = 0xAAAAAAAA
set *(0xd5555550) = 0x55555555
set *(0xdaaaaaa0) = 0xAAAAAAAA
print/x *0xd0000000@4
print/x *0xd5555550
print/x *0xdaaaaaa0
echo Setting Breakpoint 1...\n
hbreak *0x1c
echo Continuing...\n
continue
delete
# end the simulation gracefully
set *(volatile unsigned char*)0xd0580000 = 0xff
================================================
FILE: .github/scripts/utils.sh
================================================
#!/bin/bash
# SPDX-License-Identifier: Apache-2.0
# Copyright 2024 Antmicro <www.antmicro.com>
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# Colors
COLOR_OFF='\033[0m'
COLOR_RED='\033[31m'
COLOR_GREEN='\033[32m'
COLOR_WHITE='\033[1;37m'
# Waits until the given phrase appears in a log file (actively written to)
# Usage: wait_for_phrase <log_file> <phrase>
wait_for_phrase () {
# Check if the log exists
sleep 1s
if ! [ -f "$1" ]; then
echo -e "${COLOR_RED}Log file '$1' not found!${COLOR_OFF}"
return -1
fi
# Wait for the phrase
DEADLINE=$(($(date +%s) + 30))
while [ $(date +%s) -lt ${DEADLINE} ]
do
# Check for the phrase
grep "$2" "$1" >/dev/null
if [ $? -eq 0 ]; then
return 0
fi
# Sleep and retry
sleep 1s
done
# Timeout
return -1
}
# Terminates a process. First via SIGINT and if this doesn't work after 10s
# retries with SIGKILL
# Usage: terminate <pid>
terminate () {
local PID=$1
# Gently interrupt, wait some time and then kill
/bin/kill -s SIGINT ${PID} || true
sleep 10s
/bin/kill -s SIGKILL ${PID} || true
}
================================================
FILE: .github/workflows/build-docs.yml
================================================
name: Documentation build
on:
workflow_call:
jobs:
build:
name: Build
runs-on: ubuntu-24.04
env:
DEBIAN_FRONTEND: "noninteractive"
steps:
- name: Install dependencies
run: |
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
python3 python3-pip
- name: Setup repository
uses: actions/checkout@v4
- name: Build Docs
run: |
pushd docs
pip3 install -r requirements.txt
TZ=UTC make html
popd
ls -lah docs/build
- name: Pack artifacts
if: always()
uses: actions/upload-artifact@v4
with:
name: docs
path: ./docs/build
================================================
FILE: .github/workflows/ci.yml
================================================
name: VeeR-EL2 CI
on:
push:
branches: ["main"]
pull_request:
workflow_dispatch:
schedule:
- cron: '0 2 * * *' # run daily at 02:00 am (UTC)
jobs:
Test-DCLS:
name: Test-DCLS-Regression
uses: ./.github/workflows/test-regression-dcls.yml
Test-Regression-Cache-Waypack-0-num-ways-2:
name: Test-Regression Cache Waypack 0 Num Ways 2
uses: ./.github/workflows/test-regression-cache-waypack.yml
with:
waypack: 0
num_ways: 2
Test-Regression-Cache-Waypack-0-num-ways-4:
name: Test-Regression Cache Waypack 0 Num Ways 4
uses: ./.github/workflows/test-regression-cache-waypack.yml
with:
waypack: 0
num_ways: 4
Test-Regression-Cache-Waypack-1-num-ways-2:
name: Test-Regression Cache Waypack 1 Num Ways 2
uses: ./.github/workflows/test-regression-cache-waypack.yml
with:
waypack: 1
num_ways: 2
Test-Regression-Cache-Waypack-1-num-ways-4:
name: Test-Regression Cache Waypack 1 Num Ways 4
uses: ./.github/workflows/test-regression-cache-waypack.yml
with:
waypack: 1
num_ways: 4
Test-Exceptions-Regression:
name: Test-Exceptions-Regression
uses: ./.github/workflows/test-regression-exceptions.yml
Test-Verification:
name: Test-Verification
uses: ./.github/workflows/test-verification.yml
Test-Microarchitectural:
name: Test-Microarchitectural
uses: ./.github/workflows/test-uarch.yml
Test-RISCV-DV:
name: Test-RISCV-DV
uses: ./.github/workflows/test-riscv-dv.yml
Test-RISCOF:
name: Test-RISCOF
uses: ./.github/workflows/test-riscof.yml
Test-UVM:
name: Test-UVM
uses: ./.github/workflows/test-uvm.yml
Test-Renode:
name: Test-Renode
uses: ./.github/workflows/test-renode.yml
Test-OpenOCD:
name: Test-OpenOCD
uses: ./.github/workflows/test-openocd.yml
Report-Coverage:
name: Report-Coverage
needs: [
Test-DCLS,
Test-Regression-Cache-Waypack-0-num-ways-2,
Test-Regression-Cache-Waypack-0-num-ways-4,
Test-Regression-Cache-Waypack-1-num-ways-2,
Test-Regression-Cache-Waypack-1-num-ways-4,
Test-Exceptions-Regression,
Test-Verification,
Test-Microarchitectural,
Test-RISCV-DV,
Test-RISCOF,
Test-OpenOCD
]
uses: ./.github/workflows/report-coverage.yml
Build-Docs:
name: Build-Docs
uses: ./.github/workflows/build-docs.yml
Publish-to-GH-Pages:
concurrency:
group: concurrency-group-${{ github.repository }}-publish
cancel-in-progress: false
permissions:
actions: write
contents: write
name: Publish-to-GH-Pages
needs: [Report-Coverage, Build-Docs]
uses: ./.github/workflows/publish-webpage.yml
================================================
FILE: .github/workflows/custom-lint.yml
================================================
name: Custom lint
on:
push:
branches:
- main
pull_request:
jobs:
run-lint:
name: Run lint
runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]
container: centos:8
env:
GHA_EXTERNAL_DISK: additional-tools-all
GHA_SA: gh-sa-veer-uploader
steps:
- uses: actions/checkout@v4
with:
submodules: recursive
- name: Set secrets version
run: echo "SECRETS_VERSION=`cat .github/scripts/secrets_version`" >> $GITHUB_ENV
- name: Run lint
run: _secret_combined_${{ env.SECRETS_VERSION }}
env:
SECRET_NAME: _secret_lint
================================================
FILE: .github/workflows/gh-pages-pr-closed.yml
================================================
name: GH-Pages PR Remove
on:
pull_request:
types:
- closed
jobs:
build:
name: PR Remove
concurrency:
group: gh-pages
runs-on: ubuntu-24.04
permissions:
contents: write
steps:
- name: Save PR number
run: |
echo "number=${{ github.event.number }}" >> delete_pr_number.txt
- name: Upload artifacts
uses: actions/upload-artifact@v4
with:
name: delete_pr_number
path: ./delete_pr_number.txt
================================================
FILE: .github/workflows/gh-pages-pr-comment.yml
================================================
name: GH-Pages PR Comment
on:
workflow_run:
workflows: ["VeeR-EL2 CI"]
types:
- completed
env:
WEB_URL: 'https://chipsalliance.github.io/Cores-VeeR-EL2/'
jobs:
comment:
name: PR Comment
runs-on: ubuntu-24.04
permissions:
pull-requests: write
if: ${{ github.event.workflow_run.event == 'pull_request' && github.event.workflow_run.conclusion == 'success' }}
steps:
- name: Download artifact
id: download-artifact
uses: dawidd6/action-download-artifact@v6
with:
name: pr_number
path: ./
run_id: ${{ github.event.workflow_run.id }}
- name: Extract PR number
id: PR
run: |
cat pr_number.txt | tee "$GITHUB_OUTPUT"
- uses: actions/github-script@v6
with:
script: |
github.rest.issues.createComment({
issue_number: ${{ steps.PR.outputs.number }},
owner: context.repo.owner,
repo: context.repo.repo,
body: 'Coverage report for this PR is available at ${{ env.WEB_URL }}/html/dev/${{ steps.PR.outputs.number }}/coverage_dashboard/all, documentation is available at ${{ env.WEB_URL }}/html/dev/${{ steps.PR.outputs.number }}/docs_rendered/html'
})
================================================
FILE: .github/workflows/gh-pages-pr-remove.yml
================================================
name: GH-Pages PR Remove Deploy
on:
workflow_run:
workflows: ["GH-Pages PR Remove"]
types:
- completed
env:
ROOT_DIR: './public.new'
jobs:
remove:
name: PR Remove Deploy
concurrency:
group: gh-pages
runs-on: ubuntu-24.04
permissions:
contents: write
steps:
- name: Setup repository
uses: actions/checkout@v4
- name: Install coverage dependencies
run: |
python3 -m venv .venv
source .venv/bin/activate
pip install -r .github/scripts/requirements-coverage.txt
echo "PATH=$PATH" >> $GITHUB_ENV
- name: Download deployment
uses: actions/checkout@v4
with:
ref: gh-pages
path: ${{ env.ROOT_DIR }}
- name: Download artifact
id: download-artifact
uses: dawidd6/action-download-artifact@v6
with:
name: delete_pr_number
path: ./
run_id: ${{ github.event.workflow_run.id }}
- name: Extract PR number
id: PR
run: |
cat delete_pr_number.txt | tee "$GITHUB_OUTPUT"
rm -rf delete_pr_number.txt
- name: Update the webpage
run: |
rm -rf ${{ env.ROOT_DIR }}/html/dev/${{ steps.PR.outputs.number }}
rm -rf ${{ env.ROOT_DIR }}/doctrees/dev/${{ steps.PR.outputs.number }}
- name: Add redirect index page
run: |
cp .github/scripts/indexgen/index_redirect/index.html ./public.new/
- name: Deploy
uses: peaceiris/actions-gh-pages@v4
with:
github_token: ${{ secrets.GITHUB_TOKEN }}
publish_dir: ./public.new
commit_message: "Remove reports from PR#${{ steps.PR.outputs.number }}"
force_orphan: true
================================================
FILE: .github/workflows/publish-webpage.yml
================================================
name: GH-Pages Build and Main Deploy
on:
workflow_call:
jobs:
build:
name: Build and Main Deploy
concurrency:
group: gh-pages
runs-on: ubuntu-24.04
container:
image: debian:trixie
permissions:
contents: write
steps:
- name: Setup repository
uses: actions/checkout@v4
- name: Print metadata
run: |
run_information="Repository: ${{ github.repository }} Commit SHA:${{ github.sha }} Workflow: ${{ github.workflow }} Run:${{ github.run_id }}"
echo $run_information
- name: Download coverage reports
uses: actions/download-artifact@v4
with:
name: data_verilator
path: data_verilator/
- name: Download coverage reports merged
uses: actions/download-artifact@v4
with:
name: data_both
path: data_both/
- name: Download docs
uses: actions/download-artifact@v4
with:
name: docs
path: ./docs_rendered
- name: Download verification reports
uses: actions/download-artifact@v4
with:
pattern: verification_dashboard*
merge-multiple: true
path: ./verification_dashboard
- name: Download RISCOF report
uses: actions/download-artifact@v4
with:
pattern: riscof-report*
merge-multiple: true
path: ./riscof_dashboard
- name: Checkout gh-pages
uses: actions/checkout@v4
with:
ref: gh-pages
path: ./public.checkout
- name: Preserve only valid items
run: |
mkdir -p ./public.new
mv ./public.checkout/doctrees ./public.new/ | true
mv ./public.checkout/html ./public.new/ | true
- name: Update webpage
run: |
set -eux
set -o pipefail
apt -y update
apt -y install nodejs npm python3 zip git
echo "Event: $GITHUB_EVENT_NAME, ref: $GITHUB_REF_NAME)"
if [ "$GITHUB_EVENT_NAME" = pull_request ]
then
TARGET_DIR="${PWD}/public.new/html/dev/${{ github.event.number }}"
elif [ "$GITHUB_REF_NAME" = main ]
then
TARGET_DIR="${PWD}/public.new/html/main"
else
# Currently deploying is only possible in PRs and on main but let's
# better keep things safe in case that's changed in the future by
# using another target dir in other cases.
TARGET_DIR="${PWD}/public.new/html/other"
fi
mkdir -p $TARGET_DIR
# data
cd data_verilator
zip $TARGET_DIR/data.zip *
cd ../data_both
zip $TARGET_DIR/data_both.zip *
cd ..
# get coverview
git clone https://github.com/antmicro/coverview
cd coverview
npm install
npm run build
python3 embed.py --inject-data $TARGET_DIR/data_both.zip
cd ..
# dashboard
rm -rf $TARGET_DIR/coverage_dashboard*
mkdir -p $TARGET_DIR/coverage_dashboard/all
cp -a coverview/dist/* $TARGET_DIR/coverage_dashboard/all
# docs
rm -rf $TARGET_DIR/docs_rendered
mkdir -p $TARGET_DIR/docs_rendered
mv ./docs_rendered/* $TARGET_DIR/docs_rendered
echo ${GITHUB_RUN_ID} > $TARGET_DIR/run_id
tar -acf webpage.tar.gz public.new
- name: Add redirect index page
run: |
cp .github/scripts/indexgen/index_redirect/index.html ./public.new/
- name: Deploy
uses: peaceiris/actions-gh-pages@v4
if: ${{ github.ref == 'refs/heads/main' || github.event_name == 'pull_request' }}
with:
github_token: ${{ secrets.GITHUB_TOKEN }}
publish_dir: ./public.new
force_orphan: true
- name: Save PR number
if: github.event_name == 'pull_request'
run: |
echo "number=${{ github.event.number }}" >> pr_number.txt
- name: Upload artifacts
uses: actions/upload-artifact@v4
if: github.event_name == 'pull_request'
with:
name: pr_number
path: ./pr_number.txt
- name: Pack webpage as an artifact
if: always()
uses: actions/upload-artifact@v4
with:
name: webpage
path: ./webpage.tar.gz
================================================
FILE: .github/workflows/report-coverage.yml
================================================
name: Coverage report
on:
workflow_call:
defaults:
run:
shell: bash
jobs:
merge-verilator-reports:
name: Merge Verilator info data
runs-on: ubuntu-24.04
container: ghcr.io/antmicro/cores-veer-el2:20250411084921
env:
DEBIAN_FRONTEND: "noninteractive"
steps:
- uses: actions/checkout@v4
with:
submodules: recursive
- name: Download coverage reports
uses: actions/download-artifact@v4
with:
pattern: "*coverage_data*"
merge-multiple: true
path: ./
- name: Setup info-process
run: .github/scripts/info_process_setup.sh
- name: Merge data
run: |
mkdir info_files_verilator
mv *.info info_files_verilator/
export SIM=verilator
.github/scripts/prepare_coverage_data.sh
- name: Pack artifacts
if: always()
uses: actions/upload-artifact@v4
with:
name: verilator_coverage_single_data
path: verilator_coverage_single_data.tar.xz
- name: Pack artifacts
if: always()
uses: actions/upload-artifact@v4
with:
name: data_verilator
path: data_verilator/*
custom-coverage-reports:
name: Custom coverage reports
runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]
container: centos:8
env:
GHA_EXTERNAL_DISK: additional-tools
GHA_SA: gh-sa-veer-uploader
steps:
- uses: actions/checkout@v4
with:
submodules: recursive
- name: Set secrets version
run: echo "SECRETS_VERSION=`cat .github/scripts/secrets_version`" >> $GITHUB_ENV
- name: Prepare Environment
run: _secret_combined_${{ env.SECRETS_VERSION }}
env:
SECRET_NAME: _secret_prepare_env
- name: Generate custom reports
run: _secret_combined_${{ env.SECRETS_VERSION }}
env:
SECRET_NAME: _secret_custom_report
- name: Pack artifacts
uses: actions/upload-artifact@v4
with:
name: info_files_v_mapped
path: info_files_v/*
both-coverage-reports:
name: Coverage reports merger
runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]
container: debian:trixie
needs: [merge-verilator-reports, custom-coverage-reports]
env:
DEBIAN_FRONTEND: noninteractive
GHA_EXTERNAL_DISK: additional-tools
GHA_SA: gh-sa-veer-uploader
steps:
- uses: actions/checkout@v4
with:
submodules: recursive
- name: Set secrets version
run: echo "SECRETS_VERSION=`cat .github/scripts/secrets_version`" >> $GITHUB_ENV
- name: Extract custom coverage
run: _secret_combined_${{ env.SECRETS_VERSION }}
env:
SECRET_NAME: _secret_extract_custom_coverage
- name: Setup info-process
run: .github/scripts/info_process_setup.sh
- name: Prepare custom coverage
run: |
export SIM=v
.github/scripts/prepare_coverage_data.sh
# info_files_v_mapped uses the same dir.
rm -rf info_files_v
- name: Pack artifacts
uses: actions/upload-artifact@v4
with:
name: v_coverage_single_data
path: v_coverage_single_data.tar.xz
- name: Pack artifacts
uses: actions/upload-artifact@v4
with:
name: data_v
path: data_v/*
- name: Download Verilator data
uses: actions/download-artifact@v4
with:
name: data_verilator
path: data_verilator/
- name: Compare tests
run: |
cat data_v/*.desc | grep '^TEST:' | sed 's#.*,##' | sed 's#;#\n#g' | sort | uniq >tests_v
cat data_verilator/*.desc | grep '^TEST:' | sed 's#.*,##' | sed 's#;#\n#g' | sort | uniq >tests_verilator
# `|| true` because it's only needed for informational purposes, a difference is not a reason to fail.
diff -yt tests_v tests_verilator || true
- name: Create merged package
run: |
.github/scripts/create_merged_package.sh
rm -rf data_verilator
rm -rf data_v
- name: Pack artifacts
uses: actions/upload-artifact@v4
with:
name: data_both
path: data_both/*
- name: Download V mapped info files
uses: actions/download-artifact@v4
with:
name: info_files_v_mapped
path: info_files_v
- name: Prepare custom coverage
run: |
export SIM=v
.github/scripts/prepare_coverage_data.sh
- name: Pack artifacts
uses: actions/upload-artifact@v4
with:
name: data_v_mapped
path: data_v/*
================================================
FILE: .github/workflows/test-openocd.yml
================================================
name: Test-OpenOCD
on:
workflow_call:
defaults:
run:
shell: bash
jobs:
tests:
name: Run OpenOCD tests
runs-on: ubuntu-24.04
container: ghcr.io/antmicro/cores-veer-el2:20250411084921
strategy:
fail-fast: false
matrix:
coverage: ["all"]
bus: ["axi4", "ahb_lite"]
env:
DEBIAN_FRONTEND: "noninteractive"
CCACHE_DIR: "/opt/openocd-tests/.cache/"
steps:
- name: Install utils
run: |
echo "deb http://archive.ubuntu.com/ubuntu/ noble main universe" | sudo tee -a /etc/apt/sources.list > /dev/null
echo "debconf debconf/frontend select Noninteractive" | sudo debconf-set-selections
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
ccache ninja-build gcc-riscv64-unknown-elf
pip3 install meson
wget https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.09.03/riscv64-elf-ubuntu-22.04-gcc-nightly-2024.09.03-nightly.tar.gz
tar -xzf riscv64-elf-ubuntu-22.04-gcc-nightly-2024.09.03-nightly.tar.gz
mv riscv /opt/
- name: Setup Cache Metadata
id: cache_metadata
run: |
date=$(date +"%Y_%m_%d")
time=$(date +"%Y%m%d_%H%M%S_%N")
cache_test_restore_key=${{ matrix.coverage }}_
cache_test_key=${cache_test_restore_key}${time}
echo "date=$date" | tee -a "$GITHUB_ENV"
echo "time=$time" | tee -a "$GITHUB_ENV"
echo "cache_test_restore_key=$cache_test_restore_key" | tee -a "$GITHUB_ENV"
echo "cache_test_key=$cache_test_key" | tee -a "$GITHUB_ENV"
- name: Setup repository
uses: actions/checkout@v4
with:
submodules: recursive
- name: Install coverage dependencies
run: |
python3 -m venv .venv
source .venv/bin/activate
pip install -r .github/scripts/requirements-coverage.txt
echo "PATH=$PATH" >> $GITHUB_ENV
- name: Build verilated simulation
run: |
export PATH=/opt/verilator/bin:/opt/openocd/bin:$PATH
export RV_ROOT=$(pwd)
mkdir run
make -C run -f ${RV_ROOT}/tools/Makefile verilator-build program.hex TEST=infinite_loop \
CONF_PARAMS="-set build_${{ matrix.bus }} -set openocd_test" COVERAGE=${{ matrix.coverage }} -j$(nproc)
cd run
${RV_ROOT}/.github/scripts/openocd_test.sh \
-f ${RV_ROOT}/testbench/openocd_scripts/verilator-rst.cfg \
-f ${RV_ROOT}/testbench/openocd_scripts/jtag_cg.tcl
pkill openocd || true
- name: Test with GDB-test (register access, memory access, breakpoints)
run: |
# TODO GDB is in /opt/riscv and a separate toolchain is installed with apt. Make this better.
export PATH=/opt/riscv/bin:/opt/verilator/bin:/opt/openocd/bin:$PATH
export RV_ROOT=$(pwd)
mkdir gdb_test
make -C gdb_test -f ${RV_ROOT}/tools/Makefile verilator-build program.hex TEST=infinite_loop \
CONF_PARAMS="-set build_${{ matrix.bus }} -set openocd_test" COVERAGE=${{ matrix.coverage }} -j$(nproc)
cd gdb_test
${RV_ROOT}/.github/scripts/gdb_test.sh
pkill openocd || true
- name: Prepare coverage data
run: |
export PATH=/opt/verilator/bin:$PATH
export RV_ROOT=$(pwd)
mkdir -p results
if [ ${{ matrix.bus }} = axi4 ]; then
BUS_NAME=axi
elif [ ${{ matrix.bus }} = ahb_lite ]; then
BUS_NAME=ahb
fi
.github/scripts/convert_dat.sh ${RV_ROOT}/run/coverage.dat \
results/coverage_${BUS_NAME}-openocd
.github/scripts/convert_dat.sh ${RV_ROOT}/gdb_test/coverage.dat \
results/coverage_${BUS_NAME}-openocd-gdb
- name: Pack artifacts
if: always()
uses: actions/upload-artifact@v4
with:
name: openocd_coverage_data_${{ matrix.bus }}_${{ matrix.coverage }}
path: results/*.info
custom-openocd-tests:
name: Run Custom OpenOCD tests
runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]
container: centos:8
strategy:
fail-fast: false
matrix:
bus: ["axi4"]
env:
GHA_EXTERNAL_DISK: additional-tools
GHA_SA: gh-sa-veer-uploader
steps:
- uses: actions/checkout@v4
with:
submodules: recursive
- name: Set secrets version
run: echo "SECRETS_VERSION=`cat .github/scripts/secrets_version`" >> $GITHUB_ENV
- name: Run tests
run: _secret_combined_${{ env.SECRETS_VERSION }}
env:
SECRET_NAME: _secret_custom_openocd_tests
BUS: ${{ matrix.bus }}
================================================
FILE: .github/workflows/test-regression-cache-waypack.yml
================================================
name: Regression tests cache waypack
on:
workflow_call:
inputs:
waypack:
required: true
type: number
num_ways:
required: true
type: number
defaults:
run:
shell: bash
env:
WAYPACK: ${{ inputs.waypack }}
NUM_WAYS: ${{ inputs.num_ways }}
jobs:
regression-tests:
name: Regression tests
runs-on: ubuntu-24.04
container: ghcr.io/antmicro/cores-veer-el2:20250411084921
strategy:
matrix:
bus: ["axi", "ahb"]
test: ["hello_world", "hello_world_dccm", "hello_world_iccm", "cmark", "cmark_dccm", "cmark_iccm", "dhry", "ecc",
"csr_misa", "csr_access", "csr_mstatus", "csr_mseccfg", "modesw", "insns", "irq", "perf_counters",
"pmp", "pmp_random", "write_unaligned", "icache", "bitmanip", "read_after_read"]
coverage: ["all"]
priv: ["0", "1"]
tb_extra_args: ["--test-halt"] # hello_world_iccm will also have --test-lsu-clk-ratio
exclude:
# These tests require user mode
- priv: "0"
test: "csr_mseccfg"
- priv: "0"
test: "csr_access"
- priv: "0"
test: "csr_mstatus"
- priv: "0"
test: "modesw"
- priv: "0"
test: "insns"
- priv: "0"
test: "perf_counters"
# end tests which require user mode
env:
DEBIAN_FRONTEND: "noninteractive"
CCACHE_DIR: "/opt/regression/.cache/"
steps:
- name: Install utils
run: |
echo "deb http://archive.ubuntu.com/ubuntu/ noble main universe" | sudo tee -a /etc/apt/sources.list > /dev/null
echo "debconf debconf/frontend select Noninteractive" | sudo debconf-set-selections
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
git python3 python3-pip build-essential ninja-build ccache \
gcc-riscv64-unknown-elf
pip3 install meson --break-system-packages
- name: Setup repository
uses: actions/checkout@v4
with:
submodules: recursive
- name: Install coverage dependencies
run: |
python3 -m venv .venv
source .venv/bin/activate
pip install -r .github/scripts/requirements-coverage.txt
echo "PATH=$PATH" >> $GITHUB_ENV
- name: Setup environment
run: |
echo "/opt/verilator/bin" >> $GITHUB_PATH
RV_ROOT=`pwd`
echo "RV_ROOT=$RV_ROOT" >> $GITHUB_ENV
PYTHONUNBUFFERED=1
echo "PYTHONUNBUFFERED=$PYTHONUNBUFFERED" >> $GITHUB_ENV
TEST_PATH=$RV_ROOT/test_results
echo "TEST_PATH=$TEST_PATH" >> $GITHUB_ENV
echo "FULL_NAME=${{ matrix.bus }}-${{ matrix.test }}-${{ matrix.priv == 0 && 'm' || 'mu' }}-waypack${WAYPACK}-num-ways${NUM_WAYS}" >> $GITHUB_ENV
- name: Run tests
run: |
export PATH=/opt/verilator/bin:$PATH
export RV_ROOT=`pwd`
export TB_EXTRA_ARGS="${{ matrix.tb_extra_args }}"
# Use hello_world_iccm for testing '--test-lsu-clk-ratio'
if [ ${{ matrix.test }} = hello_world_iccm ]; then
export TB_EXTRA_ARGS="$TB_EXTRA_ARGS --test-lsu-clk-ratio"
fi
.github/scripts/run_regression_test.sh $TEST_PATH ${{ matrix.bus }} ${{ matrix.test}} ${{ matrix.coverage }} ${{ matrix.priv }} $WAYPACK
- name: Prepare coverage data
run: |
source .venv/bin/activate
mkdir -p results
.github/scripts/convert_dat.sh ${TEST_PATH}/coverage.dat results/coverage_${FULL_NAME}
- name: Pack artifacts
if: always()
uses: actions/upload-artifact@v4
with:
name: regression_tests_coverage_data_cache_waypack_${{ env.FULL_NAME }}_${{ matrix.coverage }}
path: results/*.info
custom-regression-tests:
name: Custom regression tests
runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]
container: centos:8
strategy:
matrix:
bus: ["axi", "ahb"]
test: ["hello_world", "hello_world_dccm", "hello_world_iccm", "cmark", "cmark_dccm", "cmark_iccm", "dhry", "ecc",
"csr_misa", "csr_access", "csr_mstatus", "csr_mseccfg", "modesw", "insns", "irq", "perf_counters", "pmp", "write_unaligned",
"icache", "bitmanip", "read_after_read"]
priv: ["0", "1"]
ecc: ["0", "1"]
exclude:
# These tests require user mode
- priv: "0"
test: "csr_mseccfg"
- priv: "0"
test: "csr_access"
- priv: "0"
test: "csr_mstatus"
- priv: "0"
test: "modesw"
- priv: "0"
test: "insns"
- priv: "0"
test: "perf_counters"
# end tests which require user mode
# These tests require AHB bus
- bus: "axi"
test: "read_after_read"
# end tests which require AHB bus
env:
GHA_EXTERNAL_DISK: additional-tools
GHA_SA: gh-sa-veer-uploader
steps:
- uses: actions/checkout@v4
with:
submodules: recursive
- name: Set secrets version
run: echo "SECRETS_VERSION=`cat .github/scripts/secrets_version`" >> $GITHUB_ENV
- name: Run tests
run: _secret_combined_${{ env.SECRETS_VERSION }}
env:
SECRET_NAME: _secret_custom_regression_tests_waypack
TEST: ${{ matrix.test }}
BUS: ${{ matrix.bus }}
PRIV: ${{ matrix.priv }}
ECC: ${{ matrix.ecc }}
================================================
FILE: .github/workflows/test-regression-dcls.yml
================================================
name: Regression tests DCLS
on:
workflow_call:
defaults:
run:
shell: bash
jobs:
regression-tests:
name: Regression tests
runs-on: ubuntu-latest
container: ghcr.io/antmicro/cores-veer-el2:20250411084921
strategy:
matrix:
bus: ["axi", "ahb"]
# run some subset of regression tests on DCLS configutation
test: ["hello_world", "hello_world_dccm", "dhry", "ecc",
"csr_misa", "csr_access", "csr_mstatus", "csr_mseccfg", "perf_counters",
"icache", "bitmanip"]
coverage: ["branch"]
priv: ["0", "1"]
tb_extra_args: ["--test-halt"]
exclude:
# These tests require user mode
- priv: "0"
test: "csr_mseccfg"
- priv: "0"
test: "csr_access"
- priv: "0"
test: "csr_mstatus"
- priv: "0"
test: "modesw"
- priv: "0"
test: "insns"
- priv: "0"
test: "perf_counters"
# end tests which require user mode
include:
# Use hello_world_iccm for testing '--test-lsu-clk-ratio'
- test: "hello_world_iccm"
bus: "axi"
coverage: "branch"
priv: "0"
tb_extra_args: "--test-halt --test-lsu-clk-ratio"
env:
DEBIAN_FRONTEND: "noninteractive"
CCACHE_DIR: "/opt/regression/.cache/"
DCLS_ENABLE: "1"
steps:
- name: Install utils
run: |
echo "deb http://archive.ubuntu.com/ubuntu/ noble main universe" | sudo tee -a /etc/apt/sources.list > /dev/null
echo "debconf debconf/frontend select Noninteractive" | sudo debconf-set-selections
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
git python3 python3-pip build-essential ninja-build ccache \
gcc-riscv64-unknown-elf
pip3 install meson --break-system-packages
- name: Setup repository
uses: actions/checkout@v4
with:
submodules: recursive
- name: Install coverage dependencies
run: |
python3 -m venv .venv
source .venv/bin/activate
pip install -r .github/scripts/requirements-coverage.txt
echo "PATH=$PATH" >> $GITHUB_ENV
- name: Setup environment
run: |
echo "/opt/verilator/bin" >> $GITHUB_PATH
RV_ROOT=`pwd`
echo "RV_ROOT=$RV_ROOT" >> $GITHUB_ENV
PYTHONUNBUFFERED=1
echo "PYTHONUNBUFFERED=$PYTHONUNBUFFERED" >> $GITHUB_ENV
TEST_PATH=$RV_ROOT/test_results
echo "TEST_PATH=$TEST_PATH" >> $GITHUB_ENV
- name: Run tests
run: |
export PATH=/opt/verilator/bin:$PATH
export RV_ROOT=`pwd`
export TB_EXTRA_ARGS="${{ matrix.tb_extra_args }}"
.github/scripts/run_regression_test.sh $TEST_PATH ${{ matrix.bus }} ${{ matrix.test}} ${{ matrix.coverage }} ${{ matrix.priv }} 0
custom-regression-tests:
name: Custom regression tests
runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]
container: centos:8
strategy:
matrix:
bus: ["axi", "ahb"]
# run some subset of regression tests on DCLS configutation
test: ["hello_world", "hello_world_dccm", "dhry", "ecc",
"csr_misa", "csr_access", "csr_mstatus", "csr_mseccfg", "perf_counters",
"icache", "bitmanip"]
priv: ["0", "1"]
exclude:
# These tests require user mode
- priv: "0"
test: "csr_mseccfg"
- priv: "0"
test: "csr_access"
- priv: "0"
test: "csr_mstatus"
- priv: "0"
test: "modesw"
- priv: "0"
test: "insns"
- priv: "0"
test: "perf_counters"
# end tests which require user mode
env:
GHA_EXTERNAL_DISK: additional-tools
GHA_SA: gh-sa-veer-uploader
steps:
- uses: actions/checkout@v4
with:
submodules: recursive
- name: Set secrets version
run: echo "SECRETS_VERSION=`cat .github/scripts/secrets_version`" >> $GITHUB_ENV
- name: Run tests
run: _secret_combined_${{ env.SECRETS_VERSION }}
env:
SECRET_NAME: _secret_dcls_regression
DCLS_ENABLE: "1"
TEST: ${{ matrix.test }}
BUS: ${{ matrix.bus }}
PRIV: ${{ matrix.priv }}
================================================
FILE: .github/workflows/test-regression-exceptions.yml
================================================
name: Regression exceptions tests
on:
workflow_call:
defaults:
run:
shell: bash
jobs:
regression-tests:
name: Regression exceptions tests
runs-on: ubuntu-24.04
container: ghcr.io/antmicro/cores-veer-el2:20250411084921
strategy:
matrix:
bus: ["axi"]
test: ["machine_external_ints", "dbus_store_error", "lsu_trigger_hit", "machine_external_vec_ints", "dside_pic_access_error",
"iside_fetch_precise_bus_error", "dside_access_region_prediction_error", "cmark", "iside_core_local_unmapped_address_error",
"dside_access_across_region_boundary", "nmi_pin_assertion", "dside_size_misaligned_access_to_non_idempotent_address",
"dside_core_local_access_unmapped_address_error", "dbus_nonblocking_load_error", "internal_timer_ints", "ebreak_ecall", "illegal_instruction",
"clk_override", "core_pause"]
coverage: ["all"]
cache_waypack: ["0", "1"]
priv: ["0"]
env:
DEBIAN_FRONTEND: "noninteractive"
CCACHE_DIR: "/opt/regression/.cache/"
steps:
- name: Install utils
run: |
echo "deb http://archive.ubuntu.com/ubuntu/ noble main universe" | sudo tee -a /etc/apt/sources.list > /dev/null
echo "debconf debconf/frontend select Noninteractive" | sudo debconf-set-selections
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
git python3 python3-pip build-essential ninja-build ccache \
gcc-riscv64-unknown-elf
pip3 install meson --break-system-packages
- name: Setup repository
uses: actions/checkout@v4
with:
submodules: recursive
- name: Install coverage dependencies
run: |
python3 -m venv .venv
source .venv/bin/activate
pip install -r .github/scripts/requirements-coverage.txt
echo "PATH=$PATH" >> $GITHUB_ENV
- name: Setup environment
run: |
echo "/opt/verilator/bin" >> $GITHUB_PATH
RV_ROOT=`pwd`
echo "RV_ROOT=$RV_ROOT" >> $GITHUB_ENV
PYTHONUNBUFFERED=1
echo "PYTHONUNBUFFERED=$PYTHONUNBUFFERED" >> $GITHUB_ENV
TEST_PATH=$RV_ROOT/test_results
echo "TEST_PATH=$TEST_PATH" >> $GITHUB_ENV
echo "FULL_NAME=${{ matrix.bus }}-exceptions-${{ matrix.test }}-waypack${{ matrix.cache_waypack }}" >> $GITHUB_ENV
- name: Run tests
run: |
export PATH=/opt/verilator/bin:$PATH
export RV_ROOT=`pwd`
.github/scripts/run_regression_test.sh $TEST_PATH ${{ matrix.bus }} ${{ matrix.test}} ${{ matrix.coverage }} ${{ matrix.priv }} ${{ matrix.cache_waypack }}
- name: Prepare coverage data
run: |
source .venv/bin/activate
mkdir -p results
.github/scripts/convert_dat.sh ${TEST_PATH}/coverage.dat \
results/coverage_${FULL_NAME}
- name: Pack artifacts
if: always()
uses: actions/upload-artifact@v4
with:
name: regression_tests_coverage_data-${{ env.FULL_NAME }}_${{ matrix.coverage }}
path: results/*.info
custom-regression-exceptions-tests:
name: Custom regression exceptions tests
runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]
container: centos:8
env:
GHA_EXTERNAL_DISK: additional-tools
GHA_SA: gh-sa-veer-uploader
steps:
- uses: actions/checkout@v4
with:
submodules: recursive
- name: Set secrets version
run: echo "SECRETS_VERSION=`cat .github/scripts/secrets_version`" >> $GITHUB_ENV
- name: Run tests
run: _secret_combined_${{ env.SECRETS_VERSION }}
env:
SECRET_NAME: _secret_custom_regression_exceptions_tests
================================================
FILE: .github/workflows/test-renode.yml
================================================
name: Renode tests
on:
workflow_call:
jobs:
tests:
runs-on: ubuntu-24.04
container: ghcr.io/antmicro/cores-veer-el2:20250411084921
strategy:
fail-fast: false
env:
DEBIAN_FRONTEND: "noninteractive"
steps:
- name: Clone repository
uses: actions/checkout@v4
with:
submodules: recursive
- name: Install dependencies
run: |
echo "deb http://archive.ubuntu.com/ubuntu/ noble main universe" | sudo tee -a /etc/apt/sources.list > /dev/null
echo "debconf debconf/frontend select Noninteractive" | sudo debconf-set-selections
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
git python3 python3-dev python3-pip build-essential ninja-build ccache \
gcc-riscv64-unknown-elf
pip3 install meson --break-system-packages
- name: Build tests
run: |
export RV_ROOT=`pwd`
cd ./tools/renode
./build-all-tests.sh
- name: Run tests
run: |
cd ./tools/renode
pip3 install -r /opt/renode/tests/requirements.txt --break-system-packages
/opt/renode/renode-test veer.robot
- name: Upload artifacts
if: always()
uses: actions/upload-artifact@v4
with:
name: renode_results
path: |
tools/renode/log.html
tools/renode/report.html
tools/renode/robot_output.xml
================================================
FILE: .github/workflows/test-riscof.yml
================================================
name: RISCOF tests
on:
workflow_call:
defaults:
run:
shell: bash
jobs:
tests:
name: Run RISCOF tests
runs-on: ubuntu-24.04
container: ghcr.io/antmicro/cores-veer-el2:20250411084921
strategy:
fail-fast: false
matrix:
coverage: ["all"]
env:
DEBIAN_FRONTEND: "noninteractive"
CCACHE_DIR: "/opt/riscof/.cache/"
steps:
- name: Install utils
run: |
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
git ccache python3-minimal python3-pip device-tree-compiler \
build-essential ninja-build
# ghcr.io/antmicro/cores-veer-el2:20250411084921 is ubuntu-22.04.5 which has a riscv toolchain
# without the support for the Zicsr extension
- name: Install cross-compiler
run: |
echo "deb http://archive.ubuntu.com/ubuntu/ noble main universe" | sudo tee -a /etc/apt/sources.list > /dev/null
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
gcc-riscv64-unknown-elf
riscv64-unknown-elf-gcc --version
- name: Setup repository
uses: actions/checkout@v4
with:
submodules: recursive
- name: Install coverage dependencies
run: |
python3 -m venv .venv
source .venv/bin/activate
pip install -r .github/scripts/requirements-coverage.txt
echo "PATH=$PATH" >> $GITHUB_ENV
- name: Install RISCOF
run: |
pip3 install git+https://github.com/riscv/riscof@a25e315
- name: Clone tests
run: |
mkdir -p riscof
pushd riscof
riscof --verbose info arch-test --clone
popd
- name: Skip tests
run: |
pushd riscof/riscv-arch-test/riscv-test-suite
# This test accesses memory at address 0x0.
# These accesses fail on Spike because it has a debug module in range [0x0; 0x1000).
# VeeR doesn't have such restrictions, so they don't fail, which results in a test failure.
rm -f rv32i_m/pmp/src/pmpm_cfg_A_tor_zero.S
rm -f rv32i_m/pmp/src/pmpzca_misaligned_na4.S
popd
- name: Configure RISCOF
run: |
pushd riscof
# Copy RISCOF configuration
cp ../tools/riscof/config.ini ./
cp -r ../tools/riscof/spike ./
cp -r ../tools/riscof/veer ./
# Build the test list
riscof testlist --config=config.ini --suite=riscv-arch-test/riscv-test-suite/ --env=riscv-arch-test/riscv-test-suite/env
popd
- name: Build VeeR model
run: |
export PATH=/opt/verilator/bin:$PATH
export RV_ROOT=`pwd`
pushd riscof
VEER_OPTS="-set=user_mode=1 -set=smepmp=1"
make -f $RV_ROOT/tools/Makefile verilator-build CONF_PARAMS="-set build_axi4 $VEER_OPTS" COVERAGE=${{ matrix.coverage }}
popd
- name: Run tests, collect coverage
run: |
export PATH=/opt/verilator/bin:/opt/spike/bin:$PATH
pushd riscof
riscof run --no-browser --config=config.ini --suite=riscv-arch-test/riscv-test-suite/ --env=riscv-arch-test/riscv-test-suite/env
mkdir -p coverage
verilator_coverage -write ./coverage/coverage.dat `find ./riscof_work/ -type f -name "coverage.dat"`
popd
- name: Prepare coverage data
run: |
export PATH=/opt/verilator/bin:$PATH
.github/scripts/convert_dat.sh riscof/coverage/coverage.dat \
riscof/coverage/coverage_riscof-m
- name: Prepare report
run: |
PYTEST_STYLE_SRC_DIR=$(pwd)/.github/scripts/pytest/
PYTEST_CSS=${PYTEST_STYLE_SRC_DIR}/css/styles.css
pushd riscof/riscof_work
bash ${PYTEST_STYLE_SRC_DIR}/style_pytest_report.sh ${PYTEST_STYLE_SRC_DIR} . report.html
echo "/* Custom CSS */" >>style.css
cat ${PYTEST_CSS} >>style.css
popd
- name: Pack artifacts
if: always()
uses: actions/upload-artifact@v4
with:
name: riscof_coverage_data_m_${{ matrix.coverage }}
path: riscof/coverage/*.info
- name: Pack artifacts
if: always()
uses: actions/upload-artifact@v4
with:
name: riscof-report_m_${{ matrix.coverage }}
path: |
riscof/riscof_work/report.html
riscof/riscof_work/style.css
riscof/riscof_work/assets
riscof/riscof_work/script
riscof/riscof_work/rv*
!riscof/riscof_work/**/coverage.dat
- name: Check failure
run: |
if res=$(grep -no riscof/riscof_work/report.html -e "<tbody.*failed"); then
echo "Number of failed RISCOF tests: $(wc -l <<< "$res")" >&2
echo "Check the report in artifacts for details." >&2
exit 1
fi
================================================
FILE: .github/workflows/test-riscv-dv.yml
================================================
name: RISCV-DV tests
on:
workflow_call:
defaults:
run:
shell: bash
env:
ITERATIONS: 3
SEED: 999
jobs:
generate-config:
name: Generate configs
runs-on: ubuntu-24.04
outputs:
test-types: ${{ steps.test-types.outputs.tests }}
test-include-generate: ${{ steps.test-types.outputs.include-generate }}
test-include-run: ${{ steps.test-types.outputs.include-run }}
test-include-run-custom: ${{ steps.test-types.outputs.include-run-custom }}
# The same exclude can be used in both `run-tests` and `run-custom-tests` jobs cause they
# exclude all matrix entries with matching keys regardless of other keys so it doesn't matter
# that matrix in `run-tests` has twice the entries from `run-tests-custom` due to `coverage`.
test-exclude-run: ${{ steps.test-types.outputs.exclude-run }}
hash: ${{ steps.hash.outputs.files-hash }}
steps:
- uses: actions/checkout@v4
with:
submodules: recursive
- id: test-types
run: |
python3 -m pip install pyyaml
echo "tests=$(python3 .github/scripts/riscv_dv_parse_testlist.py tools/riscv-dv/testlist.yaml)" | tee -a $GITHUB_OUTPUT
echo "include-generate=$(python3 .github/scripts/riscv_dv_matrix_include.py generate)" | tee -a $GITHUB_OUTPUT
echo "include-run=$(python3 .github/scripts/riscv_dv_matrix_include.py run-tests)" | tee -a $GITHUB_OUTPUT
echo "include-run-custom=$(python3 .github/scripts/riscv_dv_matrix_include.py run-custom-tests)" | tee -a $GITHUB_OUTPUT
echo "exclude-run=[ \
{'iss': 'renode', 'test': 'riscv_bitmanip_full_test_veer'}, \
{'iss': 'renode', 'test': 'riscv_bitmanip_balanced_test_veer'}, \
{'iss': 'renode', 'test': 'riscv_illegal_instr_test'}, \
{'iss': 'renode', 'test': 'riscv_hint_instr_test'}, \
{'iss': 'renode', 'test': 'riscv_ebreak_test', 'priv': 'mu'}, \
{'iss': 'renode', 'test': 'riscv_ebreak_debug_mode_test', 'priv': 'mu'} \
]" | tee -a $GITHUB_OUTPUT
- id: hash
run: |
echo "files-hash=$(.github/scripts/get_code_hash.sh)" | tee -a $GITHUB_OUTPUT
generate-code:
name: Generate code for tests
runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]
container: centos:8
needs: generate-config
strategy:
fail-fast: false
matrix:
test: ${{ fromJSON(needs.generate-config.outputs.test-types) }}
version: [ uvm ]
include: ${{ fromJSON(needs.generate-config.outputs.test-include-generate) }}
env:
GHA_EXTERNAL_DISK: additional-tools
CACHE_HASH: ${{ needs.generate-config.outputs.hash }}
steps:
- uses: actions/checkout@v4
with:
submodules: recursive
- name: Set secrets version
run: echo "SECRETS_VERSION=`cat .github/scripts/secrets_version`" >> $GITHUB_ENV
- name: Prepare Environment
run: _secret_combined_${{ env.SECRETS_VERSION }}
env:
SECRET_NAME: _secret_prepare_env
- name: Generate code
if: matrix.version == 'uvm'
run: _secret_combined_${{ env.SECRETS_VERSION }}
env:
SECRET_NAME: _secret_generate_code
RISCV_DV_TEST: ${{ matrix.test }}
RISCV_DV_ITER: ${{ env.ITERATIONS }}
RISCV_DV_SEED: ${{ env.SEED }}
- name: Generate code (pyflow)
if: matrix.version == 'pyflow'
run: |
export RV_ROOT=`realpath .`
pushd tools/riscv-dv
make -j`nproc` \
RISCV_DV_TEST=${{ matrix.test }} \
RISCV_DV_ITER=$ITERATIONS \
RISCV_DV_SEED=$SEED \
generate
popd
- name: Pack artifacts
if: always()
uses: actions/upload-artifact@v4
with:
name: riscv-dv_generated_code_${{ matrix.test }}_${{ matrix.version }}
path: tools/riscv-dv/work/**/asm_test/*.S
run-tests:
name: Run RISC-V DV tests
runs-on: ubuntu-24.04
container: ghcr.io/antmicro/cores-veer-el2:20250411084921
needs: [ generate-config, generate-code ]
strategy:
fail-fast: false
matrix:
test: ${{ fromJSON(needs.generate-config.outputs.test-types) }}
iss:
- spike
- renode
coverage: ["all"]
version: [ uvm ]
priv: ["m", "mu"]
include: ${{ fromJSON(needs.generate-config.outputs.test-include-run) }}
exclude: ${{ fromJSON(needs.generate-config.outputs.test-exclude-run) }}
env:
DEBIAN_FRONTEND: "noninteractive"
CCACHE_DIR: "/opt/riscv-dv/.cache/"
CACHE_HASH: ${{ needs.generate-config.outputs.hash }}
steps:
- name: Install utils
run: |
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
git ccache device-tree-compiler python3-minimal python3-pip \
libboost-all-dev
# As of July 9th, 2024 `ubuntu:latest` comes with riscv64-unknown-elf-gcc
# 10.0.2. We need a newer version for bitmanip extension support.
- name: Install cross-compiler
run: |
echo "deb http://archive.ubuntu.com/ubuntu/ noble main universe" | sudo tee -a /etc/apt/sources.list > /dev/null
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
gcc-riscv64-unknown-elf
riscv64-unknown-elf-gcc --version
- name: Setup repository
uses: actions/checkout@v4
with:
submodules: recursive
- name: Install coverage dependencies
run: |
python3 -m venv .venv
source .venv/bin/activate
pip install -r .github/scripts/requirements-coverage.txt
echo "PATH=$PATH" >> $GITHUB_ENV
- name: Install Python deps
run: |
pip install -r third_party/riscv-dv/requirements.txt
- name: Download Code Artifact
uses: actions/download-artifact@v4
with:
name: riscv-dv_generated_code_${{ matrix.test }}_${{ matrix.version }}
path: tools/riscv-dv/work/
- name: Run test
run: |
ls tools/riscv-dv/work
export FULL_NAME=riscv_dv-${{ matrix.test }}-${{ matrix.priv }}-${{ matrix.iss }}-${{ matrix.version }}
export PATH=/opt/verilator/bin:$PATH
export RV_ROOT=`realpath .`
export RISCV_GCC=riscv64-unknown-elf-gcc
export RISCV_OBJCOPY=riscv64-unknown-elf-objcopy
export RISCV_NM=riscv64-unknown-elf-nm
export SPIKE_PATH=/opt/spike/bin
export RENODE_PATH=/opt/renode/renode
echo "FULL_NAME=${FULL_NAME}" >> $GITHUB_ENV
echo "RV_ROOT=${RV_ROOT}" >> ${GITHUB_ENV}
echo "PATH=${PATH}" >> ${GITHUB_ENV}
${RISCV_GCC} --version
pushd tools/riscv-dv
make -j`nproc` \
RISCV_DV_TEST=${{ matrix.test }} \
RISCV_DV_ISS=${{ matrix.iss }} \
RISCV_DV_ITER=$ITERATIONS \
RISCV_DV_SEED=$SEED \
COVERAGE=${{ matrix.coverage }} \
RISCV_DV_PRIV=${{ matrix.priv }} \
run
popd
- name: Prepare coverage data
run: |
mkdir -p results
for ((i=0; i<ITERATIONS; i++)); do
.github/scripts/convert_dat.sh ${RV_ROOT}/tools/riscv-dv/work/*/hdl_sim/*_$i/coverage.dat \
results/coverage_${FULL_NAME}-iter${i}
done
- name: Pack artifacts
if: always()
uses: actions/upload-artifact@v4
with:
name: coverage_data-${{ env.FULL_NAME }}-${{ matrix.coverage }}
path: results/*.info
- name: Pack artifacts
if: always()
uses: actions/upload-artifact@v4
with:
name: artifacts-${{ env.FULL_NAME }}-${{ matrix.coverage }}
path: tools/riscv-dv/work/test_*
run-custom-tests:
name: Run custom RISC-V DV tests
runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]
container: centos:8
needs: [ generate-config, run-tests ]
strategy:
fail-fast: false
matrix:
test: ${{ fromJSON(needs.generate-config.outputs.test-types) }}
iss:
- spike
- renode
version: [ uvm ]
priv: ["m", "mu"]
include: ${{ fromJSON(needs.generate-config.outputs.test-include-run-custom) }}
exclude: ${{ fromJSON(needs.generate-config.outputs.test-exclude-run) }}
env:
DEBIAN_FRONTEND: "noninteractive"
CCACHE_DIR: "/opt/riscv-dv/.cache/"
GHA_EXTERNAL_DISK: additional-tools
GHA_SA: gh-sa-veer-uploader
CACHE_HASH: ${{ needs.generate-config.outputs.hash }}
steps:
- uses: actions/checkout@v4
with:
submodules: recursive
- run: echo "FULL_NAME=riscv_dv-${{ matrix.test }}-${{ matrix.priv }}-${{ matrix.iss }}-${{ matrix.version }}" >> $GITHUB_ENV
# To avoid compiling code and running ISS on CentOS, let's just get
# compiled code and ISS logs from the artifacts of Verilator tests.
- name: Download Code and ISS logs
uses: actions/download-artifact@v4
with:
name: artifacts-${{ env.FULL_NAME }}-all
path: verilator-artifacts
- name: Move Code and ISS logs to workdir
run: |
SRC_DIR=verilator-artifacts/test_${{ matrix.test }}
TEST_DIR=tools/riscv-dv/work/test_${{ matrix.test }}
mkdir -p $TEST_DIR/asm_test
cp $SRC_DIR/asm_test/*.hex $TEST_DIR/asm_test/
cp -r $SRC_DIR/${{ matrix.iss }}_sim $TEST_DIR/
rm -rf verilator-artifacts
- name: Set secrets version
run: echo "SECRETS_VERSION=`cat .github/scripts/secrets_version`" >> $GITHUB_ENV
- name: Prepare Environment
run: _secret_combined_${{ env.SECRETS_VERSION }}
env:
SECRET_NAME: _secret_prepare_env
- name: Perform custom tests
run: _secret_combined_${{ env.SECRETS_VERSION }}
env:
SECRET_NAME: _secret_custom_riscv_dv
RISCV_DV_ITER: ${{ env.ITERATIONS }}
RISCV_DV_TEST: ${{ matrix.test }}
RISCV_DV_PRIV: ${{ matrix.priv }}
RISCV_DV_ISS: ${{ matrix.iss }}
VERSION: ${{ matrix.version }}
================================================
FILE: .github/workflows/test-uarch.yml
================================================
name: VeeR-EL2 Microarchitectural tests
on:
workflow_call:
defaults:
run:
shell: bash
jobs:
lint:
name: Lint microarchitectural tests
runs-on: ubuntu-24.04
container: ghcr.io/antmicro/cores-veer-el2:20250411084921
steps:
- name: Setup repository
uses: actions/checkout@v4
with:
submodules: recursive
- name: Setup environment
run: |
RV_ROOT=`pwd`
echo "RV_ROOT=$RV_ROOT" >> $GITHUB_ENV
PYTHONUNBUFFERED=1
echo "PYTHONUNBUFFERED=$PYTHONUNBUFFERED" >> $GITHUB_ENV
TEST_PATH=$RV_ROOT/verification/block
echo "TEST_PATH=$TEST_PATH" >> $GITHUB_ENV
python3 -m venv .venv
source .venv/bin/activate
python3 -m pip install nox
- name: Lint
run: |
source .venv/bin/activate
pushd ${TEST_PATH}
nox -s test_lint
popd
tests:
name: Microarchitectural tests
runs-on: ubuntu-24.04
container: ghcr.io/antmicro/cores-veer-el2:20250411084921
strategy:
matrix:
include:
- test: "block/pic"
artifact: "block_pic"
- test: "block/pic_gw"
artifact: "block_pic_gw"
- test: "block/dma"
artifact: "block_dma"
- test: "block/ifu_compress"
artifact: "block_ifu_compress"
- test: "block/ifu_mem_ctl"
artifact: "block_ifu_mem_ctl"
- test: "block/dec_tl"
artifact: "block_dec_tl"
- test: "block/dec_ib"
artifact: "block_dec_ib"
- test: "block/exu_alu"
artifact: "block_exu_alu"
- test: "block/exu_mul"
artifact: "block_exu_mul"
- test: "block/exu_div"
artifact: "block_exu_div"
- test: "block/iccm"
artifact: "block_iccm"
- test: "block/dccm"
artifact: "block_dccm"
- test: "block/lib_axi4_to_ahb"
artifact: "block_lib_axi4_to_ahb"
- test: "block/lib_ahb_to_axi4"
artifact: "block_lib_ahb_to_axi4"
- test: "block/pmp"
artifact: "block_pmp"
- test: "block/pmp_random"
artifact: "block_pmp_random"
- test: "block/dec_pmp_ctl"
artifact: "block_dec_pmp_ctl"
- test: "block/dmi"
artifact: "block_dmi"
- test: "block/lsu_tl"
artifact: "block_lsu_tl"
- test: "block/dec_tlu_ctl"
artifact: "block_dec_tlu_ctl"
- test: "block/dec"
artifact: "block_dec"
- test: "block/dcls"
artifact: "block_dcls"
env:
CCACHE_DIR: "/opt/verification/.cache/"
DEBIAN_FRONTEND: "noninteractive"
steps:
- name: Setup repository
uses: actions/checkout@v4
with:
submodules: recursive
- name: Install prerequisites
run: |
echo "deb http://archive.ubuntu.com/ubuntu/ noble main universe" | sudo tee -a /etc/apt/sources.list > /dev/null
echo "debconf debconf/frontend select Noninteractive" | sudo debconf-set-selections
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
autoconf automake autotools-dev \
bc bison build-essential \
ccache curl \
flex \
gawk gcc-riscv64-unknown-elf git gperf \
help2man \
libexpat-dev libfl-dev libfl2 libgmp-dev \
libmpc-dev libmpfr-dev libpython3-all-dev libtool \
ninja-build \
patchutils python3 python3-dev python3-pip \
texinfo \
zip zlib1g zlib1g-dev \
libbit-vector-perl
- name: Install coverage dependencies
run: |
python3 -m venv .venv
source .venv/bin/activate
pip install -r .github/scripts/requirements-coverage.txt
python3 -m pip install meson nox
- name: Setup environment
run: |
echo "/opt/verilator/bin" >> $GITHUB_PATH
RV_ROOT=`pwd`
echo "RV_ROOT=$RV_ROOT" >> $GITHUB_ENV
PYTHONUNBUFFERED=1
echo "PYTHONUNBUFFERED=$PYTHONUNBUFFERED" >> $GITHUB_ENV
TEST_TYPE=`echo ${{ matrix.test }} | cut -d'/' -f1`
TEST_NAME=`echo ${{ matrix.test }} | cut -d'/' -f2`
TEST_PATH=$RV_ROOT/verification/${TEST_TYPE}
echo "TEST_TYPE=$TEST_TYPE" >> $GITHUB_ENV
echo "TEST_NAME=$TEST_NAME" >> $GITHUB_ENV
echo "TEST_PATH=$TEST_PATH" >> $GITHUB_ENV
# Fix random generator seed
echo "RANDOM_SEED=1377424946" >> $GITHUB_ENV
- name: Run ${{ matrix.test }}
run: |
source .venv/bin/activate
pushd ${TEST_PATH}
nox -s ${TEST_NAME}_verify
popd
zip verification/${{ matrix.test }}/dump.vcd.zip verification/${{ matrix.test }}/dump.vcd
- name: Prepare coverage data
run: |
shopt -s extglob
export PATH=/opt/verilator/bin:$PATH
source .venv/bin/activate
mkdir -p results
for FILE in ${TEST_PATH}/${TEST_NAME}/*.dat; do
.github/scripts/convert_dat.sh "${FILE}" "results/$(basename "${FILE%_@(all|branch|toggle).dat}")"
done
# Prefix coverage results
pushd results
for OLD_NAME in *.info; do
# e.g. coverage_uarch-dma-ecc_line.info instead of coverage_test_ecc_line.info
NEW_NAME=${OLD_NAME/coverage_/coverage_uarch-${TEST_NAME}-}
NEW_NAME=${NEW_NAME/test_/}
echo "renaming '${OLD_NAME}' to '${NEW_NAME}'"
mv ${OLD_NAME} ${NEW_NAME}
done
popd
- name: Upload coverage data artifacts
if: always()
uses: actions/upload-artifact@v4
with:
name: uarch_tests_coverage_data-${{ matrix.artifact }}
path: ./results/*.info
- name: Upload test logs
if: always()
uses: actions/upload-artifact@v4
with:
name: uarch_tests_logs-${{ matrix.artifact }}
path: |
verification/${{ matrix.test }}/*.log
verification/${{ matrix.test }}/*.vcd.zip
custom_tests:
name: Run custom Microarchitectural tests
runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]
container: centos:8
strategy:
matrix:
test:
- "block/pic"
- "block/pic_gw"
- "block/dma"
- "block/ifu_compress"
- "block/ifu_mem_ctl"
- "block/dec_tl"
- "block/dec_ib"
- "block/exu_alu"
- "block/exu_mul"
- "block/exu_div"
- "block/iccm"
- "block/dccm"
- "block/lib_axi4_to_ahb"
- "block/lib_ahb_to_axi4"
- "block/pmp"
- "block/pmp_random"
- "block/dec_pmp_ctl"
- "block/dmi"
- "block/lsu_tl"
- "block/dec_tlu_ctl"
- "block/dec"
env:
GHA_EXTERNAL_DISK: additional-tools
GHA_SA: gh-sa-veer-uploader
TEST: ${{ matrix.test }}
steps:
- uses: actions/checkout@v4
with:
submodules: recursive
- name: Set secrets version
run: echo "SECRETS_VERSION=`cat .github/scripts/secrets_version`" >> $GITHUB_ENV
- name: Perform custom tests
run: _secret_combined_${{ env.SECRETS_VERSION }}
env:
SECRET_NAME: _secret_custom_uarch
TEST: ${{ matrix.test }}
================================================
FILE: .github/workflows/test-uvm.yml
================================================
name: VeeR-EL2 verification
on:
workflow_call:
jobs:
tests:
name: UVM tests
runs-on: ubuntu-24.04
container: ghcr.io/antmicro/cores-veer-el2:20250411084921
env:
CCACHE_DIR: "/opt/uvm/.cache/"
DEBIAN_FRONTEND: "noninteractive"
steps:
- name: Setup repository
uses: actions/checkout@v4
with:
submodules: recursive
- name: Install prerequisities
run: |
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
git build-essential ccache
- name: Setup environment
run: |
echo "/opt/verilator/bin" >> $GITHUB_PATH
RV_ROOT=`pwd`
echo "RV_ROOT=$RV_ROOT" >> $GITHUB_ENV
PYTHONUNBUFFERED=1
echo "PYTHONUNBUFFERED=$PYTHONUNBUFFERED" >> $GITHUB_ENV
- name: Build UVM testbench
run: |
make -C testbench/uvm/mem build -j$(nproc)
- name: Run UVM testbench
run: |
make -C testbench/uvm/mem simulate | tee test.out
- name: Upload test output
if: always()
uses: actions/upload-artifact@v4
with:
name: uvm_test_output
path: test.out
================================================
FILE: .github/workflows/test-verification.yml
================================================
name: VeeR-EL2 verification
on:
workflow_call:
defaults:
run:
shell: bash
jobs:
tests:
name: Verification tests
runs-on: ubuntu-24.04
container: ghcr.io/antmicro/cores-veer-el2:20250411084921
strategy:
matrix:
bus: ["ahb", "axi"]
test: ["test_pyuvm"]
coverage: ["all"]
env:
DEBIAN_FRONTEND: "noninteractive"
CCACHE_DIR: "/opt/regression/.cache/"
FULL_NAME: "${{ matrix.bus }}-verification-${{ matrix.test }}"
steps:
- name: Setup repository
uses: actions/checkout@v4
with:
submodules: recursive
- name: Install prerequisities
run: |
echo "deb http://archive.ubuntu.com/ubuntu/ noble main universe" | sudo tee -a /etc/apt/sources.list > /dev/null
echo "debconf debconf/frontend select Noninteractive" | sudo debconf-set-selections
sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \
autoconf automake autotools-dev \
bc bison build-essential \
ccache curl \
flex \
gawk gcc-riscv64-unknown-elf git gperf \
help2man \
libexpat-dev libfl-dev libfl2 libgmp-dev \
libmpc-dev libmpfr-dev libpython3-all-dev libtool \
ninja-build \
patchutils python3 python3-dev python3-pip \
texinfo \
zlib1g zlib1g-dev \
libbit-vector-perl
- name: Install coverage dependencies
run: |
python3 -m venv .venv
source .venv/bin/activate
pip install -r .github/scripts/requirements-coverage.txt
- name: Setup environment
run: |
echo "/opt/verilator/bin" >> $GITHUB_PATH
RV_ROOT=`pwd`
echo "RV_ROOT=$RV_ROOT" >> $GITHUB_ENV
PYTHONUNBUFFERED=1
echo "PYTHONUNBUFFERED=$PYTHONUNBUFFERED" >> $GITHUB_ENV
TEST_PATH=$RV_ROOT/verification/top/${{ matrix.test }}
echo "TEST_PATH=$TEST_PATH" >> $GITHUB_ENV
echo "HTML_FILE=${FULL_NAME}_${{ matrix.coverage }}.html" >> $GITHUB_ENV
- name: Run ${{ matrix.test }}
run: |
source .venv/bin/activate
pip3 install meson
pip3 install -r $RV_ROOT/verification/top/requirements.txt
PYTEST_STYLE_SRC_DIR=$RV_ROOT/.github/scripts/pytest/
PYTEST_CSS=${PYTEST_STYLE_SRC_DIR}/css/styles.css
if [ ${{ matrix.bus }} = axi ]; then
CONF_PARAMS='-set build_axi4'
else
CONF_PARAMS='-set build_ahb_lite'
fi
pushd ${TEST_PATH}
python3 -m pytest ${{ matrix.test }}.py -sv --coverage=${{ matrix.coverage }} --html=$HTML_FILE --md=$GITHUB_STEP_SUMMARY --css=$PYTEST_CSS --conf_params="$CONF_PARAMS"
bash ${PYTEST_STYLE_SRC_DIR}/style_pytest_report.sh ${PYTEST_STYLE_SRC_DIR} ${TEST_PATH} ${HTML_FILE}
popd
- name: Prepare pytest-html data
run: |
source .venv/bin/activate
pushd $RV_ROOT
WEBPAGE_DIR=webpage_${FULL_NAME}_${{ matrix.coverage }}
mkdir -p $WEBPAGE_DIR
mv ${TEST_PATH}/$HTML_FILE $WEBPAGE_DIR
mv ${TEST_PATH}/assets $WEBPAGE_DIR
JS_SCRIPT_DIR=$RV_ROOT/.github/scripts/pytest/script
mv $JS_SCRIPT_DIR $WEBPAGE_DIR
popd
- name: Prepare coverage data
run: |
source .venv/bin/activate
export PATH=/opt/verilator/bin:$PATH
mkdir -p results
.github/scripts/convert_dat.sh ${TEST_PATH}/coverage.dat \
results/coverage_${FULL_NAME/test_/}
- name: Upload pytest-html artifacts
if: always()
uses: actions/upload-artifact@v4
with:
name: verification_dashboard_${{ env.FULL_NAME }}_${{ matrix.coverage }}
path: webpage_*
- name: Upload coverage artifacts
if: always()
uses: actions/upload-artifact@v4
with:
name: verification_tests_coverage_data_${{ env.FULL_NAME }}_${{ matrix.coverage }}
path: results/*.info
custom-verification-tests:
name: Custom verification tests
runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]
container: centos:8
strategy:
matrix:
bus: ["axi", "ahb"]
test: ["test_pyuvm"]
env:
GHA_EXTERNAL_DISK: additional-tools
GHA_SA: gh-sa-veer-uploader
steps:
- uses: actions/checkout@v4
with:
submodules: recursive
- name: Set secrets version
run: echo "SECRETS_VERSION=`cat .github/scripts/secrets_version`" >> $GITHUB_ENV
- name: Run tests
run: _secret_combined_${{ env.SECRETS_VERSION }}
env:
SECRET_NAME: _secret_custom_verification_tests
TEST: ${{ matrix.test }}
BUS: ${{ matrix.bus }}
================================================
FILE: .github/workflows/verible-format.yml
================================================
name: Verible formatter
on:
pull_request_target:
jobs:
format-review:
runs-on: ubuntu-24.04
permissions:
checks: write
contents: read
pull-requests: write
steps:
- uses: actions/checkout@v4
with:
ref: ${{ github.event.pull_request.head.sha }}
- uses: antmicro/verible-formatter-action@update-upload-action
with:
github_token: ${{ secrets.GITHUB_TOKEN }}
reviewdog_reporter: 'local'
fail_on_formatting_suggestions: ${{ github.event_name != 'pull_request_target' }}
================================================
FILE: .github/workflows/verible-lint.yml
================================================
name: Verible linter
on:
pull_request_target:
jobs:
lint-review:
runs-on: ubuntu-24.04
permissions:
checks: write
contents: read
pull-requests: write
steps:
- uses: actions/checkout@v4
with:
ref: ${{ github.event.pull_request.head.sha }}
- uses: chipsalliance/verible-linter-action@main
with:
github_token: ${{ secrets.GITHUB_TOKEN }}
reviewdog_reporter: 'local'
extra_args: '--waiver_files=./violations.waiver'
paths: |
./design
================================================
FILE: .gitignore
================================================
configs/snapshots
work
obj_dir
*.vcd
*.csv
*.log
*.exe
*.swp
*.sym
verilator-build
program.hex
snapshots
__pycache__
sim_build
sim-build*
venv
results.xml
verification/sim
verilator-cocotb-build
*.dat
*.xml
*.json
tools/renode/renode_run
tools/renode/build
tools/renode/*.elf
tools/renode/.venv
docs/build
================================================
FILE: .gitmodules
================================================
[submodule "third-party/picolibc"]
path = third_party/picolibc
url = https://github.com/picolibc/picolibc
[submodule "third_party/riscv-dv"]
path = third_party/riscv-dv
url = https://github.com/chipsalliance/riscv-dv
[submodule "third_party/cocotb"]
path = third_party/cocotb
url = https://github.com/cocotb/cocotb
================================================
FILE: LICENSE
================================================
Apache License
Version 2.0, January 2004
http://www.apache.org/licenses/
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Unless required by applicable law or agreed to in writing, Licensor provides the Work (and each Contributor provides its Contributions) on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied, including, without limitation, any warranties or conditions of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A PARTICULAR PURPOSE. You are solely responsible for determining the appropriateness of using or redistributing the Work and assume any risks associated with Your exercise of permissions under this License.
8. Limitation of Liability.
In no event and under no legal theory, whether in tort (including negligence), contract, or otherwise, unless required by applicable law (such as deliberate and grossly negligent acts) or agreed to in writing, shall any Contributor be liable to You for damages, including any direct, indirect, special, incidental, or consequential damages of any character arising as a result of this License or out of the use or inability to use the Work (including but not limited to damages for loss of goodwill, work stoppage, computer failure or malfunction, or any and all other commercial damages or losses), even if such Contributor has been advised of the possibility of such damages.
9. Accepting Warranty or Additional Liability.
While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability.
================================================
FILE: MAINTAINERS.md
================================================
# Maintainers
* [Maciej Kurc](https://github.com/mkurc-ant)
* [Tomasz Michalak](https://github.com/tmichalak)
* [Karol Gugala](https://github.com/kgugala)
================================================
FILE: README.md
================================================
<picture>
<!-- User prefers light mode: -->
<source srcset="docs/source/img/VeeR-logo-black-rgb.png" media="(prefers-color-scheme: light)"/>
<!-- User prefers dark mode: -->
<source srcset="/docs/source/img/VeeR-logo-white-rgb.png" media="(prefers-color-scheme: dark)"/>
<!-- User has no color preference: -->
<img src="/docs/source/img/VeeR-logo-black-rgb.png"/>
</picture>
# VeeR EL2 RISC-V Core
This repository contains the VeeR EL2 RISC-V Core design RTL.
## License
By contributing to this project, you agree that your contribution is governed by [Apache-2.0](LICENSE).
Files under the [tools](tools/) directory may be available under a different license. Please review individual files for details.
## Directory Structure
├── configs # Configurations Dir
│ └── snapshots # Where generated configuration files are created
├── design # Design root dir
│ ├── dbg # Debugger
│ ├── dec # Decode, Registers and Exceptions
│ ├── dmi # DMI block
│ ├── exu # EXU (ALU/MUL/DIV)
│ ├── ifu # Fetch & Branch Prediction
│ ├── include
│ ├── lib
│ └── lsu # Load/Store
├── docs
├── tools # Scripts/Makefiles
└── testbench # (Very) simple testbench
├── asm # Example assembly files
├── hex # Canned demo hex files
└── tests # Example tests
## Dependencies
- Verilator **(4.106 or later)** must be installed on the system if running with Verilator
- If adding/removing instructions, [`espresso`](https://github.com/chipsalliance/espresso/tree/master) must be installed (used by `tools/coredecode`). Remember to checkout on `3.x` branch.
- RISCV tool chain (based on gcc version 8.3 or higher) must be installed so that it can be used to prepare RISCV binaries to run.
- [**Verible**](https://github.com/chipsalliance/verible) is used for SystemVerilog linting and formatting.
- **Python 3.10+** is required for verification, documentation, and linting.
### Python Environment Setup
It is recommended to use a virtual environment (venv) or Conda to manage Python dependencies.
#### Using `venv`
```bash
# Create a virtual environment
python3 -m venv .venv
# Activate it
source .venv/bin/activate
# Install all project dependencies
pip install -r requirements.txt
```
#### Using `Conda`
```bash
# Create a conda environment
conda create -n veer-el2 python=3.12
# Activate it
conda activate veer-el2
# Install dependencies
pip install -r requirements.txt
```
## Quickstart guide
1. Clone the repository, clone submodules with `git submodule update --init --recursive`
1. Setup `RV_ROOT` to point to the path in your local filesystem
1. Determine your configuration (optional)
1. Run `make` with `tools/Makefile`
## Release Notes for this version
Please see [release notes](release-notes.md) for changes and bug fixes in this version of VeeR.
### Configurations
VeeR can be configured by running the `$RV_ROOT/configs/veer.config` script:
`% $RV_ROOT/configs/veer.config -h` for detailed help options
For example to build with a DCCM of size 64 Kb:
`% $RV_ROOT/configs/veer.config -dccm_size=64`
This will update the **default** snapshot in `./snapshots/default/` with parameters for a 64K DCCM.
Add `-snapshot=dccm64`, for example, if you wish to name your build snapshot `dccm64` and refer to it during the build.
There are 4 predefined target configurations: `default`, `default_ahb`, `typical_pd` and `high_perf` that can be selected via
the `-target=name` option to `veer.config`. **Note:** that the `typical_pd` target is what we base our published PPA numbers. It does not include an ICCM.
**Building an FPGA speed optimized model:**
Use ``-fpga_optimize=1`` option to ``veer.config`` to build a model that removes clock gating logic from flop model so that the FPGA builds can run at higher speeds. **This is now the default option for targets other than ``typical_pd``.**
**Building a Power optimized model (ASIC flows):**
Use ``-fpga_optimize=0`` option to ``veer.config`` to build a model that **enables** clock gating logic into the flop model so that the ASIC flows get a better power footprint. **This is now the default option for target``typical_pd``.**
This script derives the following consistent set of include files:
./snapshots/default
├── common_defines.vh # `defines for testbench or design
├── defines.h # #defines for C/assembly headers
├── el2_param.vh # Design parameters
├── el2_pdef.vh # Parameter structure
├── pd_defines.vh # `defines for physical design
├── perl_configs.pl # Perl %configs hash for scripting
├── pic_map_auto.h # PIC memory map based on configure size
└── whisper.json # JSON file for veer-iss
└── link.ld # default linker control file
### Building a model
While in a work directory:
1. Set the `RV_ROOT` environment variable to the root of the VeeR directory structure.
Example for bash shell: `export RV_ROOT=/path/to/veer`
Example for csh or its derivatives: `setenv RV_ROOT /path/to/veer`
1. Create your specific configuration
*(Skip if default is sufficient)*
*(Name your snapshot to distinguish it from the default. Without an explicit name, it will update/override the __default__ snapshot)*
For example if `mybuild` is the name for the snapshot:
`$RV_ROOT/configs/veer.config [configuration options..] -snapshot=mybuild`
Snapshots are placed in the `./snapshots` directory
1. Run a simple Hello World program (Verilator)
```shell
make -f $RV_ROOT/tools/Makefile
```
This command will build a Verilator model of VeeR EL2 with the AXI bus, and
execute a short sequence of instructions that writes out "HELLO WORLD"
to the bus.
The simulation produces output on the screen like:
```
VerilatorTB: Start of sim
-------------------------
Hello World from VeeR EL2
-------------------------
TEST_PASSED
Finished : minstret = 437, mcycle = 922
See "exec.log" for execution trace with register updates..
```
The simulation generates the following files:
* `console.log` contains what the cpu writes to the console address of 0xd0580000.
* `exec.log` shows instruction trace with GPR updates.
* `trace_port.csv` contains a log of the trace port.
When `debug=1` is provided, a vcd file `sim.vcd` is created and can be browsed by gtkwave or similar waveform viewers.
You can re-execute the simulation using:
```shell
make -f $RV_ROOT/tools/Makefile verilator
```
The simulation run/build command has following generic form:
```shell
make -f $RV_ROOT/tools/Makefile [<simulator>] [debug=1] [snapshot=mybuild] [target=<target>] [TEST=<test>] [TEST_DIR=<path_to_test_dir>]
```
where:
```
<simulator> - can be 'verilator' (by default) 'irun' - Cadence xrun, 'vcs' - Synopsys VCS, 'vlog' Mentor Questa
'riviera'- Aldec Riviera-PRO. if not provided, 'make' cleans work directory, builds verilator executable and runs a test.
debug=1 - allows VCD generation for verilator and VCS and SHM waves for irun option.
assert=1 - enables assertions in simulation runs (with simulators other than Verilator)
<target> - predefined CPU configurations 'default' ( by default), 'default_ahb', 'typical_pd', 'high_perf'
TEST - allows to run a C (<test>.c) or assembly (<test>.s) test, hello_world is run by default
TEST_DIR - alternative to test source directory testbench/asm or testbench/tests
<snapshot> - run and build executable model of custom CPU configuration, remember to provide 'snapshot' argument
for runs on custom configurations.
CONF_PARAMS - allows to provide -set options to veer.conf script to alter predefined EL2 targets parameters
```
Example:
```shell
make -f $RV_ROOT/tools/Makefile verilator TEST=cmark
```
will build and simulate the `testbench/asm/cmark.c` program with Verilator.
If you want to compile a test only, you can run:
```shell
make -f $RV_ROOT/tools/Makefile program.hex TEST=<test> [TEST_DIR=/path/to/dir]
```
The Makefile uses the `snapshot/<target>/link.ld` file, generated by the `veer.conf` script by default to build the test executable.
User can provide test specific linker file in form `<test_name>.ld` to build the test executable,
in the same directory with the test source.
User also can create a test-specific Makefile in `<test_name>.makefile`, containing building instructions
how to create the `program.hex` file used by simulation. The private Makefile should be in the same directory
as the test source. See examples in the `testbench/asm` directory.
Another way to alter test building process is to use `<test_name>.mki` file in test source directory. It may help to select multiple sources
to compile and/or alter compilation swiches. See examples in the `testbench/tests/` directory
*(the `program.hex` file is loaded to instruction and LSU bus memory slaves and optionally to DCCM/ICCM at the beginning of simulation)*.
User can build the `program.hex` file by any other means and then run simulation with the following command:
```shell
make -f $RV_ROOT/tools/Makefile <simulator>
```
Note: You may need to delete the `program.hex` file from the work directory, when running a new test.
The `$RV_ROOT/testbench/asm` directory contains the following tests ready to simulate:
```
hello_world - default test program to run, prints Hello World message to screen and console.log
hello_world_dccm - the same as above, but takes the string from preloaded DCCM.
hello_world_iccm - the same as hello_world, but loads the test code to ICCM via LSU to DMA bridge and then executes
it from there. Runs on EL2 with AXI4 buses only.
cmark - coremark benchmark running with code and data in external memories
cmark_dccm - the same as above, running data and stack from DCCM (faster)
cmark_iccm - the same as above with preloaded code to ICCM (slower, optimized for size to fit into default ICCM).
dhry - Run dhrystone. (Scale by 1757 to get DMIPS/MHZ)
```
The `$RV_ROOT/testbench/hex` directory contains precompiled hex files of the tests, ready for simulation in case RISC-V SW tools are not installed.
**Note**: The testbench has a simple synthesizable bridge that allows you to load the ICCM via load/store instructions. This is only supported for AXI4 builds.
================================================
FILE: cm.cfg
================================================
+tree tb_top.rvtop_wrapper.rvtop
////////////////////////////////// MAIN CORE //////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//////////////////////////////// rvrangecheck /////////////////////////////////
// 'start_addr' and 'region' are tied to module parameters
-node tb_top.rvtop_wrapper.rvtop.veer*rangecheck.start_addr
-node tb_top.rvtop_wrapper.rvtop.veer*rangecheck.region
////////////////////////////// el2_veer_wrapper ///////////////////////////////
-node tb_top.rvtop_wrapper.rvtop.unused_dmi_hard_reset
-node tb_top.rvtop_wrapper.rvtop.trace_rv_i_address_ip[0]
/////////////////////////////////// el2_veer //////////////////////////////////
-node tb_top.rvtop_wrapper.rvtop.veer.trace_rv_i_address_ip[0]
-node tb_top.rvtop_wrapper.rvtop.veer.trace_rv_trace_pkt.trace_rv_i_address_ip[0]
-node tb_top.rvtop_wrapper.rvtop.veer.*hprot[3:1] // Tied to 3'001
/////////////////////////////////// el2_dbg ///////////////////////////////////
// Tied to '0
-node tb_top.rvtop_wrapper.rvtop.veer.dbg.abstractcs_reg[31:13]
-node tb_top.rvtop_wrapper.rvtop.veer.dbg.abstractcs_reg[11]
-node tb_top.rvtop_wrapper.rvtop.veer.dbg.abstractcs_reg[7:4]
-node tb_top.rvtop_wrapper.rvtop.veer.dbg.dmcontrol_reg[29]
-node tb_top.rvtop_wrapper.rvtop.veer.dbg.dmcontrol_reg[27:2]
-node tb_top.rvtop_wrapper.rvtop.veer.dbg.dmstatus_reg[31:20]
-node tb_top.rvtop_wrapper.rvtop.veer.dbg.dmstatus_reg[15:14]
-node tb_top.rvtop_wrapper.rvtop.veer.dbg.dmstatus_reg[6:4]
-node tb_top.rvtop_wrapper.rvtop.veer.dbg.haltsum0_reg[31:1]
-node tb_top.rvtop_wrapper.rvtop.veer.dbg.sbcs_reg[31:30]
-node tb_top.rvtop_wrapper.rvtop.veer.dbg.sbcs_reg[28:23]
-node tb_top.rvtop_wrapper.rvtop.veer.dbg.dmstatus_reg[7] // Tied to '1
-node tb_top.rvtop_wrapper.rvtop.veer.dbg.dmstatus_reg[3:0] // Tied to 4'h2
-node tb_top.rvtop_wrapper.rvtop.veer.dbg.abstractcs_reg[3:0] // Tied to 4'h2
-node tb_top.rvtop_wrapper.rvtop.veer.dbg.sbcs_reg[29] // Tied to '1
-node tb_top.rvtop_wrapper.rvtop.veer.dbg.sbcs_reg[11:5] // Tied to 7'h20
-node tb_top.rvtop_wrapper.rvtop.veer.dbg.sbcs_reg[4:0] // Tied to 5'b01111
/////////////////////////////////// el2_exu ///////////////////////////////////
-node tb_top.rvtop_wrapper.rvtop.veer.exu.i_mul.crc32_poly_rev // Tied to 32'hEDB88320
-node tb_top.rvtop_wrapper.rvtop.veer.exu.i_mul.crc32c_poly_rev // Tied to 32'h82F63B78
////////////////////////////////// rvjtag_tap /////////////////////////////////
-node tb_top.rvtop_wrapper.rvtop.dmi_wrapper.i_jtag_tap.abits // Tied to AWID[5:0]
///////////////////////////////// dec_tlu_ctl /////////////////////////////////
// Tied to '0
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.dcsr[14]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.dcsr[9]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.dcsr[5:4]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.dcsr_ns[14]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.dcsr_ns[9]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.dcsr_ns[5:4]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.ifu_mscause[2]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mcgc[6]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mcgc_int[6]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mcgc_ns[6]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mcountinhibit[1]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mepc_rf[0]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mie_rf[31]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mie_rf[27:12]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mie_rf[10:8]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mie_rf[6:4]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mie_rf[2:0]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mip_rf[27:12]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mip_rf[10:8]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mip_rf[6:4]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mip_rf[2:0]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mstatus_rf[31:17]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mstatus_rf[15:12]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mstatus_rf[10:8]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mstatus_rf[6:4]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mstatus_rf[2:0]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mtdata1_tsel_out[26]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mtdata1_tsel_out[18:13]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mtdata1_tsel_out[10:8]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mtdata1_tsel_out[5:3]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.mtvec_rf[1]
/////////////////////////////// el2_dec_pmp_ctl ///////////////////////////////
// Tied to '0
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.pmp.*pmpcfg_ff.din[6:5]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.pmp.*pmpcfg_ff.dout[6:5]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.pmp.*csr_wdata[6:5]
// Aggregation of four 'el2_pmp_cfg_pkt_t' entries
// Each 'pmpcfg' entry has 'pmpcfg[6:5]' tied to '0
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.pmp.pmp_pmpcfg_rddata[30:29]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.pmp.pmp_pmpcfg_rddata[22:21]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.pmp.pmp_pmpcfg_rddata[14:13]
-node tb_top.rvtop_wrapper.rvtop.veer.dec.tlu.pmp.pmp_pmpcfg_rddata[6:5]
//////////////////////////// el2_ifu_compress_ctl /////////////////////////////
// Tied to '0
-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.o[31]
-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.o[29:21]
-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.o[19:15]
-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.o[11:7]
-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.o[1:0] // Tied to 2'b11
-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.l1[1:0] // Tied to o[1:0] (2'b11)
-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.l2[1:0] // Tied to l1[1:0] (2'b11)
-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.l3[1:0] // Tied to l2[1:0] (2'b11)
-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.l1[31] // Tied to o[31] ('0)
-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.l1[29:25] // Tied to o[29:25] ('0)
-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.rdpd[4:3] // Tied to 2'01
-node tb_top.rvtop_wrapper.rvtop.veer.ifu.aln.compress0.rs2pd[4:3] // Tied to 2'01
////////////////////////////////// LOCKSTEP ///////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//////////////////////////////// rvrangecheck /////////////////////////////////
// 'start_addr' and 'region' are tied to module parameters
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core*rangecheck.start_addr
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core*rangecheck.region
////////////////////////////// el2_veer_lockstep //////////////////////////////
-node tb_top.rvtop_wrapper.rvtop.lockstep.trace_rv_i_address_ip[0]
-node tb_top.rvtop_wrapper.rvtop.lockstep.*trace_rv_i_address_ip[0]
/////////////////////////////////// el2_veer //////////////////////////////////
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.trace_rv_i_address_ip[0]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.trace_rv_trace_pkt.trace_rv_i_address_ip[0]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.*hprot[3:1] // Tied to 3'001
/////////////////////////////////// el2_dbg ///////////////////////////////////
// Tied to '0
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.abstractcs_reg[31:13]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.abstractcs_reg[11]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.abstractcs_reg[7:4]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.dmcontrol_reg[29]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.dmcontrol_reg[27:2]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.dmstatus_reg[31:20]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.dmstatus_reg[15:14]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.dmstatus_reg[6:4]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.haltsum0_reg[31:1]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.sbcs_reg[31:30]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.sbcs_reg[28:23]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.dmstatus_reg[7] // Tied to '1
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.dmstatus_reg[3:0] // Tied to 4'h2
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.abstractcs_reg[3:0] // Tied to 4'h2
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.sbcs_reg[29] // Tied to '1
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.sbcs_reg[11:5] // Tied to 7'h20
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dbg.sbcs_reg[4:0] // Tied to 5'b01111
/////////////////////////////////// el2_exu ///////////////////////////////////
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.exu.i_mul.crc32_poly_rev // Tied to 32'hEDB88320
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.exu.i_mul.crc32c_poly_rev // Tied to 32'h82F63B78
///////////////////////////////// dec_tlu_ctl /////////////////////////////////
// Tied to '0
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.dcsr[14]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.dcsr[9]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.dcsr[5:4]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.dcsr_ns[14]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.dcsr_ns[9]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.dcsr_ns[5:4]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.ifu_mscause[2]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mcgc[6]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mcgc_int[6]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mcgc_ns[6]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mcountinhibit[1]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mepc_rf[0]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mie_rf[31]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mie_rf[27:12]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mie_rf[10:8]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mie_rf[6:4]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mie_rf[2:0]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mip_rf[27:12]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mip_rf[10:8]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mip_rf[6:4]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mip_rf[2:0]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mstatus_rf[31:17]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mstatus_rf[15:12]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mstatus_rf[10:8]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mstatus_rf[6:4]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mstatus_rf[2:0]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mtdata1_tsel_out[26]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mtdata1_tsel_out[18:13]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mtdata1_tsel_out[10:8]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mtdata1_tsel_out[5:3]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.mtvec_rf[1]
/////////////////////////////// el2_dec_pmp_ctl ///////////////////////////////
// Tied to '0
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.*pmpcfg_ff.din[6:5]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.*pmpcfg_ff.dout[6:5]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.*csr_wdata[6:5]
// Aggregation of four 'el2_pmp_cfg_pkt_t' entries
// Each 'pmpcfg' entry has 'pmpcfg[6:5]' tied to '0
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.pmp_pmpcfg_rddata[30:29]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.pmp_pmpcfg_rddata[22:21]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.pmp_pmpcfg_rddata[14:13]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.dec.tlu.pmp.pmp_pmpcfg_rddata[6:5]
//////////////////////////// el2_ifu_compress_ctl /////////////////////////////
// Tied to '0
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.o[31]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.o[29:21]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.o[19:15]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.o[11:7]
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.o[1:0] // Tied to 2'b11
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.l1[1:0] // Tied to o[1:0] (2'b11)
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.l2[1:0] // Tied to l1[1:0] (2'b11)
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.l3[1:0] // Tied to l2[1:0] (2'b11)
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.l1[31] // Tied to o[31] ('0)
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.l1[29:25] // Tied to o[29:25] ('0)
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.rdpd[4:3] // Tied to 2'01
-node tb_top.rvtop_wrapper.rvtop.lockstep.xshadow_core.ifu.aln.compress0.rs2pd[4:3] // Tied to 2'01
================================================
FILE: configs/README.md
================================================
# VeeR EL2 RISC-V Core
## Configuration
### Contents
Name | Description
---------------------- | ------------------------------
VeeR.config | Configuration script for VeeR-EL2
veer_config_gen.py | Python wrapper to run veer.config, used by VeeRVolf
This script will generate a consistent set of `defines/#defines/parameters` needed for the design and testbench.
A perl hash (*perl_configs.pl*) and a JSON format for VeeR-iss are also generated.
This set of include files :
./snapshots/<target>
├── common_defines.vh # `defines for testbench
├── defines.h # #defines for C/assembly headers
├── el2_param.vh # Actual Design parameters
├── el2_pdef.vh # Parameter structure definition
├── pd_defines.vh # `defines for physical design
├── perl_configs.pl # Perl %configs hash for scripting
├── pic_map_auto.h # PIC memory map based on configure size
├── whisper.json # JSON file for veer-iss
└── link.ld # Default linker file for tests
While the defines may be modified by hand, it is recommended that this script be used to generate a consistent set.
### Targets
There are 4 predefined target configurations: `default`, `default_ahb`, `typical_pd` and `high_perf` that can be selected via the `-target=name` option to veer.config.
Target | Description
---------------------- | ------------------------------
default | Default configuration. AXI4 bus interface
default_ahb | Default configuration, AHB-Lite bus interface
typical_pd | No ICCM, AXI4 bus interface
high_perf | Large BTB/BHT, AXI4 interface
`veer.config` may be edited to add additional target configurations, or new configurations may be created via the command line `-set` or `-unset` options.
**Run `$RV_ROOT/configs/veer.config -h` for options and settable parameters.**
================================================
FILE: configs/veer.config
================================================
#! /usr/bin/env perl
use strict; # Do not turn this off or else
use Data::Dumper;
use Getopt::Long;
use Bit::Vector;
use lib "$ENV{RV_ROOT}/tools";
use JSON;
my ($self) = $0 =~ m/.*\/(\w+)/o;
my @argv_orig = @ARGV;
# Master configuration file
#
# Configuration is perl hash
# Output are define files for various flows
# Verilog (`defines common to RTL/TB)
# Software (#defines)
# Whisper (JSON/#defines)
#
# Default values and valid ranges should be specified
# Can be overridden via the cmd line (-set=name=value-string)
#
# Format of the hash is
# name => VALUE | LIST | HASH
#
# Special name "inside" followed by list .. values must be one of provided list
# Special name "derive" followed by equation to derive
#
# Dump verilog/assembly macros in upper case
my $defines_case = "U";
# Include these macros in verilog (pattern matched)
my @verilog_vars = qw (xlen config_key reset_vec tec_rv_icg numiregs nmi_vec target protection.* testbench.* dccm.* retstack core.* iccm.* btb.* bht.* icache.* pic.* regwidth memmap bus.* tech_specific_.* user_.*);
# Include these macros in assembly (pattern matched)
my @asm_vars = qw (xlen reset_vec nmi_vec target dccm.* iccm.* pic.* memmap testbench.* protection.* core.*);
my @asm_overridable = qw (reset_vec nmi_vec serialio external_data) ;
# Include these macros in PD (pattern matched)
my @pd_vars = qw (physical retstack target btb.* bht.* dccm.* iccm.* icache.* pic.* bus.* reset_vec nmi_vec build_ahb_lite datawidth );
# Dump non-derived/settable vars/values for these vars in stdout :
my @dvars = qw(retstack btb bht core dccm iccm icache pic protection memmap bus);
# Prefix all macros with
my $prefix = "RV_";
# No prefix if keyword has
my $no_prefix = 'RV|TOP|tec_rv_icg|regwidth|clock_period|^datawidth|verilator|SDVT_AHB|tech_specific_.*|user_ec_rv_icg';
my $vlog_use__wh = 1;
my %regions_used = ();
# Cmd Line options#{{{
our %sets;
our %unsets;
my $help;
my @sets = ();
my @unsets = ();
#Configurations may be changed via the -set option
#
# -set=name=value : Change the default config parameter value (lowercase)\n";
# -unset=name : Remove the default config parameter (lowercase)\n";
# : Do not prepend RV_ prefex to -set/-unset variables\n";
# : multiple -set/-unset options accepted\n\n";
#
my $helpusage = "
Main configuration database for VeeR
This script documents, and generates the {`#} define/include files for verilog/assembly/backend flows
It is run by vsim (with defaults) every time the file changes, or when -config_set=VAR=value options are passed to vsim
This script can be run stand-alone by processes not running vsim
User options:
-target = {default, default_ahb, high_perf, typical_pd}
use default settings for one of the targets
-set=var=value
set arbitrary variable(parameter) to a value
-unset=var
unset any definitions for var
-snapshot=name
name the configuration (only if no -target specified)
Parameters that can be set by the end user:
-set=user_mode = {0,1}
enable, disable user mode support in the core
-set=ret_stack_size = {2, 3, 4, ... 8}
size of return stack
-set=btb_enable = {0,1}
BTB enabled
-set=btb_fullya = {0,1}
BTB Fully set-associative
-set=btb_size = { 8, 16, 32, 64, 128, 256, 512 }
size of branch target buffer
-set=bht_size = {32, 64, 128, 256, 512, 1024, 2048}
size of branch history buffer
-set=div_bit = {1,2,3,4}
number of bits to process each cycle
-set=div_new = {0,1}
new div algorithm
-set=dccm_enable = {0,1}
DCCM enabled
-set=dccm_num_banks = {2, 4}
DCCM number of banks
-set=dccm_region = { 0x0, 0x1, ... 0xf }
number of 256Mb memory region containig DCCM
-set=dccm_offset = hexadecimal
offset (in bytes) of DCCM witin dccm_region
dccm address will be: 256M * dccm_region + dccm_offset\", and that must be aligned
to the dccm size or the next larger power of 2 if size is not a power of 2
-set=dccm_size = { 4, 8, 16, 32, 48, 64, 128, 256, 512 } kB
size of DCCM
-set=dma_buf_depth = {2,4,5}
DMA buffer depth
-set=fast_interrupt_redirect = {0, 1}
Fast interrupt redirect mechanism
-set=iccm_enable = { 0, 1 }
whether or not ICCM is enabled
-set=icache_enable = { 0, 1 }
whether or not icache is enabled
-set=icache_waypack = { 0, 1 }
whether or not icache packing is enabled
-set=icache_ecc = { 0, 1 }
whether or not icache has ecc - EXPENSIVE 30% sram growth
default: icache_ecc==0 (parity)
-set=icache_size = { 8, 16, 32, 64, 128, 256 } kB
size of icache
-set=icache_2banks = {0,1}
Enable 2 banks for icache
-set=icache_num_ways { 2,4}
Number of ways in icache
-set=icache_bypass_enable = {0,1}
Enable Icache data bypass buffer
-set=icache_num_bypass = {1..8}
Number of entries in bypass buffer
-set=icache_num_tag_bypass = {1..8}
Number of entries in bypass buffer
-set=icache_tag_bypass_enable = {0,1}
Enable icache tag bypass buffer
-set=iccm_region = { 0x0, 0x1, ... 0xf }
number of 256Mb memory region containing ICCM
-set=iccm_offset = hexadecimal
offcet (in bytes) of ICCM within iccm_region
iccm address will be: \"256M * iccm_region + iccm_offset\", and that must be aligned
to the iccm size or the next larger power of 2 if size is not a power of 2
-set=iccm_size = { 4 , 8 , 16 , 32, 64, 128, 256, 512 } kB
size of ICCM
-set=iccm_num_banks = {2,4,8,16}
Number of ICCM banks
-set=iccm_ecc_width
Width of ICCM ECC [bits]
-set=lsu_stbuf_depth = {2,4,8 }
LSU stbuf depth
-set=lsu_num_nbload = {2,4,8 }
LSU number of outstanding Non Blocking loads
-set=load_to_use_plus1 = {0 1}
Load to use latency (fast or +1cycle)
-set=pic_2cycle = { 0, 1 }
whether or not 2-cycle PIC is enabled (2 cycle pic may result
in an overall smaller cycle time)
-set=pic_region = { 0x0, 0x1, ... 0xf }
number of 256Mb memory region containing PIC memory-mapped registers
-set=pic_offset = hexadecial
offset (in bytes) of PIC within pic_region
pic address will be: \"256M * pic_region + pic_offset\", and that must be aligned
to the pic size or the next larger power of 2 if size is not a power of 2
-set=pic_size = { 32, 64, 128, 256 } kB
size of PIC
-set=pic_total_int = { 1, 2, 3, ..., 255 }
number of interrupt sources in PIC
-set=dma_buf_depth = {2,4,5}
DMA buffer depth
-set=timer_legal_en = {0,1}
Internal timers legal/enabled
-set=bitmanip_zba = {0,1}
Bit manipulation extension ZBa enabled/legal
-set=bitmanip_zbb = {0,1}
Bit manipulation extension ZBb enabled/legal
-set=bitmanip_zbc = {0,1}
Bit manipulation extension ZBc enabled/legal
-set=bitmanip_zbe = {0,1}
Bit manipulation extension ZBe enabled/legal
-set=bitmanip_zbf = {0,1}
Bit manipulation extension ZBf enabled/legal
-set=bitmanip_zbp = {0,1}
Bit manipulation extension ZBp enabled/legal
-set=bitmanip_zbr = {0,1}
Bit manipulation extension ZBr enabled/legal
-set=bitmanip_zbs = {0,1}
Bit manipulation extension ZBs enabled/legal
-fpga_optimize = { 0, 1 }
if 1, minimize clock-gating to facilitate FPGA builds
-text_in_iccm = {0, 1}
Don't add ICCM preload code in generated link.ld
-set=pmp_entries = {0, 16, 64 }
number of PMP entries
-set=smepmp = {0, 1}
Enable Smepmp PMP extension
-set=lockstep_enable = {0, 1}
Enable Dual Core Lockstep (DCLS) in the core
-set=lockstep_regfile_enable = {0, 1}
Enable observing register file in the DCLS
-set=lockstep_delay = {2, 3, 4}
Set delay value for the Dual Core Lockstep
Additionally the following may be set for bus masters and slaves using the -set=var=value option:
{inst|data}_access_enable[0-7] : default 0
{inst|data}_access_addr[0-7] : default 0x00000000
{inst|data}_access_mask[0-7] : default 0xffffffff
";
my $user_mode;
my $ret_stack_size;
my $btb_size;
my $bht_size;
my $btb_fullya;
my $btb_toffset_size;
my $dccm_region;
my $dccm_offset;
my $dccm_size;
my $iccm_enable;
my $icache_enable;
my $icache_waypack;
my $icache_num_ways;
my $icache_banks_way;
my $icache_ln_sz;
my $icache_bank_width;
my $icache_ecc;
my $iccm_region;
my $iccm_offset;
my $iccm_size;
my $icache_size;
my $pic_2cycle;
my $pic_region;
my $pic_offset;
my $pic_size;
my $pic_total_int;
my $top_align_iccm = 0;
my $target = "default";
my $snapshot ;
my $build_path ;
my $verbose;
my $load_to_use_plus1;
my $btb_enable;
my $dccm_enable;
my $icache_2banks;
my $lsu_stbuf_depth;
my $dma_buf_depth;
my $lsu_num_nbload;
my $dccm_num_banks;
my $iccm_num_banks;
my $iccm_ecc_width;
my $verilator;
my $icache_bypass_enable=1;
my $icache_num_bypass=2;
my $icache_num_bypass_width;
my $icache_tag_bypass_enable=1;
my $icache_tag_num_bypass=2;
my $icache_tag_num_bypass_width;
my $fast_interrupt_redirect = 1; # ON by default
my $lsu_num_nbload=4;
my $ahb = 0;
my $axi = 1;
my $openocd_test = 0;
my $text_in_iccm = 0;
my $lsu2dma = 0;
my $pmp_entries=16;
my $smepmp=0;
my $lockstep_enable=0;
my $lockstep_regfile_enable=0;
my $lockstep_delay=3;
$user_mode=0;
$ret_stack_size=8;
$btb_enable=1;
$btb_fullya=0;
$btb_toffset_size=12;
$btb_size=512;
$bht_size=512;
$dccm_enable=1;
$dccm_region="0xf";
$dccm_offset="0x40000"; #1*256*1024
$dccm_size=64;
$dccm_num_banks=4;
$iccm_enable=1;
$iccm_region="0xe";
$top_align_iccm = 1;
$iccm_offset="0xe000000"; #0x380*256*1024
$iccm_size=64;
$iccm_num_banks=4;
$iccm_ecc_width=7;
$icache_enable=1;
$icache_waypack=1;
$icache_num_ways=2;
$icache_banks_way=2;
$icache_2banks=1;
$icache_bank_width=8;
$icache_ln_sz=64;
$icache_ecc=1;
$icache_size=16;
$pic_2cycle=0;
$pic_region="0xf";
$pic_offset="0xc0000"; # 3*256*1024
$pic_size=32;
$pic_total_int=31;
$load_to_use_plus1=0;
$lsu_stbuf_depth=4;
$dma_buf_depth=5;
my $div_bit=4; # number of bits to process each cycle for div
my $div_new=1; # old or new div algorithm
my $fpga_optimize = 1;
# Default bitmanip options
my $bitmanip_zba = 1;
my $bitmanip_zbb = 1;
my $bitmanip_zbc = 1;
my $bitmanip_zbe = 0;
my $bitmanip_zbf = 0;
my $bitmanip_zbp = 0;
my $bitmanip_zbr = 0;
my $bitmanip_zbs = 1;
GetOptions(
"help" => \$help,
"target=s" => \$target,
"snapshot=s" => \$snapshot,
"verbose" => \$verbose,
"load_to_use_plus1" => \$load_to_use_plus1,
"ret_stack_size=s" => \$ret_stack_size,
"btb_fullya" => \$btb_fullya,
"btb_enable=s" => \$btb_enable,
"btb_size=s" => \$btb_size,
"bht_size=s" => \$bht_size,
"dccm_enable=s" => \$dccm_enable,
"dccm_region=s" => \$dccm_region,
"dccm_offset=s" => \$dccm_offset,
"dccm_size=s" => \$dccm_size,
"dma_buf_depth" => \$dma_buf_depth,
"iccm_enable=s" => \$iccm_enable,
"icache_enable=s" => \$icache_enable,
"icache_waypack=s" => \$icache_waypack,
"icache_num_ways=s" => \$icache_num_ways,
"icache_ln_sz=s" => \$icache_ln_sz,
"icache_ecc=s" => \$icache_ecc,
"icache_2banks=s" => \$icache_2banks,
"iccm_region=s" => \$iccm_region,
"iccm_offset=s" => \$iccm_offset,
"iccm_size=s" => \$iccm_size,
"lsu_stbuf_depth" => \$lsu_stbuf_depth,
"lsu_num_nbload" => \$lsu_num_nbload,
"pic_2cycle=s" => \$pic_2cycle,
"pic_region=s" => \$pic_region,
"pic_offset=s" => \$pic_offset,
"pic_size=s" => \$pic_size,
"pic_total_int=s" => \$pic_total_int,
"icache_size=s" => \$icache_size,
"set=s@" => \@sets,
"unset=s@" => \@unsets,
"fpga_optimize=s" => \$fpga_optimize,
"text_in_iccm=s" => \$text_in_iccm,
) || die("$helpusage");
if ($help) {
print "$helpusage\n";
exit;
}
if (!defined $snapshot ) {
$snapshot = $target;
}
if (!defined $ENV{BUILD_PATH}) {
$build_path = "$ENV{PWD}/snapshots/$snapshot" ;
} else {
$build_path = $ENV{BUILD_PATH};
}
if (! -d "$build_path") {
system ("mkdir -p $build_path");
}
# Parameter file
my $tdfile = "$build_path/el2_pdef.vh";
my $paramfile = "$build_path/el2_param.vh";
# Verilog defines file path
my $vlogfile = "$build_path/common_defines.vh";
# Assembly defines file path
my $asmfile = "$build_path/defines.h";
# PD defines file path
my $pdfile = "$build_path/pd_defines.vh";
# Whisper config file path
my $whisperfile = "$build_path/whisper.json";
#
# Default linker file
my $linkerfile = "$build_path/link.ld";
# Perl defines file path
my $perlfile = "$build_path/perl_configs.pl";
my $opensource=0;
# IDEA: is ghr at 5b the right size for el2 core
if ($target eq "default") { }
elsif ($target eq "lsu2dma_axi") {
$lsu2dma = 1;
$iccm_enable = 1;
}
elsif ($target eq "typical_pd") {
print "$self: Using target \"typical_pd\"\n";
$fpga_optimize = 0;
$ret_stack_size=2;
$btb_size=32;
$bht_size=128;
$dccm_size=16;
$dccm_num_banks=2;
$iccm_enable=0;
}
elsif ($target eq "high_perf") {
print "$self: Using target \"high_perf\"\n";
$btb_size=512;
$bht_size=2048;
}
elsif ($target eq "default_ahb") {
print "$self: Using target \"default_ahb\"\n";
$axi = 0;
$ahb = 1;
}
else {
die "$self: ERROR! Unsupported target \"$target\". Supported are 'default', 'default_ahb', 'typical_pd', 'high_perf', 'lsu2dma_axi\n" ;
}
# Configure triggers
our @triggers = (#{{{
{
"reset" => ["0x23e00000", "0x00000000", "0x00000000"],
"mask" => ["0x081818c7", "0xffffffff", "0x00000000"],
"poke_mask" => ["0x081818c7", "0xffffffff", "0x00000000"]
},
{
"reset" => ["0x23e00000", "0x00000000", "0x00000000"],
"mask" => ["0x081810c7", "0xffffffff", "0x00000000"],
"poke_mask" => ["0x081810c7", "0xffffffff", "0x00000000"]
},
{
"reset" => ["0x23e00000", "0x00000000", "0x00000000"],
"mask" => ["0x081818c7", "0xffffffff", "0x00000000"],
"poke_mask" => ["0x081818c7", "0xffffffff", "0x00000000"]
},
{
"reset" => ["0x23e00000", "0x00000000", "0x00000000"],
"mask" => ["0x081810c7", "0xffffffff", "0x00000000"],
"poke_mask" => ["0x081810c7", "0xffffffff", "0x00000000"]
},
);#}}}
# Configure CSRs
our %csr = (#{{{
"mstatus" => {
"reset" => "0x1800", # MPP bits hard wired to binrary 11.
"mask" => "0x88", # Only mpie(7) & mie(3) bits writeable
"exists" => "true",
},
"mie" => {
"reset" => "0x0",
# Only external, timer, local, and software writeable
"mask" => "0x70000888",
"exists" => "true",
},
"mip" => {
"reset" => "0x0",
# None of the bits are writeable using CSR instructions
"mask" => "0x0",
# Bits corresponding to error overflow, external, timer and stoftware
# interrupts are modifiable
"poke_mask" => "0x70000888",
"exists" => "true",
},
"mcountinhibit" => {
"commnet" => "Performance counter inhibit. One bit per counter.",
"reset" => "0x0",
"mask" => "0x7d",
"poke_mask" => "0x7d",
"exists" => "true",
},
"mcounteren" => {
"exists" => "false",
},
"mvendorid" => {
"reset" => "0x45",
"mask" => "0x0",
"exists" => "true",
},
"marchid" => {
"reset" => "0x00000010",
"mask" => "0x0",
"exists" => "true",
},
"mimpid" => {
"reset" => "0x4",
"mask" => "0x0",
"exists" => "true",
},
"misa" => {
"reset" => "0x40001104",
"mask" => "0x0",
"exists" => "true",
},
"tselect" => {
"reset" => "0x0",
"mask" => "0x3", # Four triggers
"exists" => "true",
},
"mhartid" => {
"reset" => "0x0",
"mask" => "0x0",
"poke_mask" => "0xfffffff0",
"exists" => "true",
},
"dcsr" => {
"reset" => "0x40000003",
"mask" => "0x00008c04",
"poke_mask" => "0x00008dcc", # cause field modifiable, nmip modifiable
"exists" => "true",
"debug" => "true",
},
"cycle" => {
"exists" => "false",
},
"time" => {
"exists" => "false",
},
"instret" => {
"exists" => "false",
},
"mhpmcounter3" => {
"reset" => "0x0",
"mask" => "0xffffffff",
"exists" => "true",
},
"mhpmcounter4" => {
"reset" => "0x0",
"mask" => "0xffffffff",
"exists" => "true",
},
"mhpmcounter5" => {
"reset" => "0x0",
"mask" => "0xffffffff",
"exists" => "true",
},
"mhpmcounter6" => {
"reset" => "0x0",
"mask" => "0xffffffff",
"exists" => "true",
},
"mhpmcounter3h" => {
"reset" => "0x0",
"mask" => "0xffffffff",
"exists" => "true",
},
"mhpmcounter4h" => {
"reset" => "0x0",
"mask" => "0xffffffff",
"exists" => "true",
},
"mhpmcounter5h" => {
"reset" => "0x0",
"mask" => "0xffffffff",
"exists" => "true",
},
"mhpmcounter6h" => {
"reset" => "0x0",
"mask" => "0xffffffff",
"exists" => "true",
},
"mhpmevent3" => {
"reset" => "0x0",
"mask" => "0xffffffff",
"exists" => "true",
},
"mhpmevent4" => {
"reset" => "0x0",
"mask" => "0xffffffff",
"exists" => "true",
},
"mhpmevent5" => {
"reset" => "0x0",
"mask" => "0xffffffff",
"exists" => "true",
},
"mhpmevent6" => {
"reset" => "0x0",
"mask" => "0xffffffff",
"exists" => "true",
},
# Remaining CSRs are non-standard. These are specific to VeeR
"dicawics" => {
"number" => "0x7c8",
"reset" => "0x0",
"mask" => "0x0130fffc",
"exists" => "true",
},
"dicad0" => {
"number" => "0x7c9",
"reset" => "0x0",
"mask" => "0xffffffff",
gitextract_0gg5endz/ ├── .github/ │ ├── scripts/ │ │ ├── breakpoint.sh │ │ ├── common.inc.sh │ │ ├── convert_dat.sh │ │ ├── create_merged_package.sh │ │ ├── gdb_test.sh │ │ ├── gdb_test_golden.txt │ │ ├── get_code_hash.sh │ │ ├── indexgen/ │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── dashboard-styles/ │ │ │ │ ├── gcov.css │ │ │ │ └── main.css │ │ │ ├── generate.py │ │ │ ├── index_redirect/ │ │ │ │ └── index.html │ │ │ ├── requirements.txt │ │ │ ├── source.template/ │ │ │ │ ├── conf.py │ │ │ │ ├── coverage_dashboard.md │ │ │ │ ├── dev.md │ │ │ │ ├── index.md │ │ │ │ ├── main.md │ │ │ │ └── verification_dashboard.md │ │ │ └── update_styles.sh │ │ ├── info_process_setup.sh │ │ ├── mapfile │ │ ├── openocd/ │ │ │ ├── board/ │ │ │ │ ├── caliptra-verilator-rst.cfg │ │ │ │ └── caliptra-verilator.cfg │ │ │ ├── sim-jtagdpi.cfg │ │ │ ├── veer-el2-rst.cfg │ │ │ └── veer-el2.cfg │ │ ├── openocd_test.sh │ │ ├── peripheral_access.tcl │ │ ├── prepare_coverage_data.sh │ │ ├── pytest/ │ │ │ ├── bar.html │ │ │ ├── css/ │ │ │ │ └── styles.css │ │ │ ├── script/ │ │ │ │ └── script.js │ │ │ └── style_pytest_report.sh │ │ ├── requirements-coverage.txt │ │ ├── riscv_dv_matrix_include.py │ │ ├── riscv_dv_parse_testlist.py │ │ ├── run_regression_test.sh │ │ ├── run_regression_tests.sh │ │ ├── secrets_version │ │ ├── test.gdb │ │ └── utils.sh │ └── workflows/ │ ├── build-docs.yml │ ├── ci.yml │ ├── custom-lint.yml │ ├── gh-pages-pr-closed.yml │ ├── gh-pages-pr-comment.yml │ ├── gh-pages-pr-remove.yml │ ├── publish-webpage.yml │ ├── report-coverage.yml │ ├── test-openocd.yml │ ├── test-regression-cache-waypack.yml │ ├── test-regression-dcls.yml │ ├── test-regression-exceptions.yml │ ├── test-renode.yml │ ├── test-riscof.yml │ ├── test-riscv-dv.yml │ ├── test-uarch.yml │ ├── test-uvm.yml │ ├── test-verification.yml │ ├── verible-format.yml │ └── verible-lint.yml ├── .gitignore ├── .gitmodules ├── LICENSE ├── MAINTAINERS.md ├── README.md ├── cm.cfg ├── configs/ │ ├── README.md │ ├── veer.config │ └── veer_config_gen.py ├── design/ │ ├── dbg/ │ │ └── el2_dbg.sv │ ├── dec/ │ │ ├── cdecode │ │ ├── csrdecode_m │ │ ├── csrdecode_mu │ │ ├── decode │ │ ├── el2_dec.sv │ │ ├── el2_dec_decode_ctl.sv │ │ ├── el2_dec_gpr_ctl.sv │ │ ├── el2_dec_ib_ctl.sv │ │ ├── el2_dec_pmp_ctl.sv │ │ ├── el2_dec_tlu_ctl.sv │ │ └── el2_dec_trigger.sv │ ├── dmi/ │ │ ├── dmi_jtag_to_core_sync.v │ │ ├── dmi_mux.v │ │ ├── dmi_wrapper.v │ │ └── rvjtag_tap.v │ ├── el2_dma_ctrl.sv │ ├── el2_mem.sv │ ├── el2_pic_ctrl.sv │ ├── el2_pmp.sv │ ├── el2_veer.sv │ ├── el2_veer_lockstep.sv │ ├── el2_veer_wrapper.sv │ ├── exu/ │ │ ├── el2_exu.sv │ │ ├── el2_exu_alu_ctl.sv │ │ ├── el2_exu_div_ctl.sv │ │ └── el2_exu_mul_ctl.sv │ ├── flist │ ├── flist.formal │ ├── flist.lint │ ├── flist.questa │ ├── ifu/ │ │ ├── el2_ifu.sv │ │ ├── el2_ifu_aln_ctl.sv │ │ ├── el2_ifu_bp_ctl.sv │ │ ├── el2_ifu_compress_ctl.sv │ │ ├── el2_ifu_ic_mem.sv │ │ ├── el2_ifu_iccm_mem.sv │ │ ├── el2_ifu_ifc_ctl.sv │ │ ├── el2_ifu_mem_ctl.sv │ │ └── el2_ifu_tb_memread.sv │ ├── include/ │ │ ├── el2_dec_csr_equ_m.svh │ │ ├── el2_dec_csr_equ_mu.svh │ │ └── el2_def.sv │ ├── lib/ │ │ ├── ahb_to_axi4.sv │ │ ├── axi4_to_ahb.sv │ │ ├── beh_lib.sv │ │ ├── el2_lib.sv │ │ ├── el2_mem_if.sv │ │ ├── el2_regfile_if.sv │ │ └── mem_lib.sv │ └── lsu/ │ ├── el2_lsu.sv │ ├── el2_lsu_addrcheck.sv │ ├── el2_lsu_bus_buffer.sv │ ├── el2_lsu_bus_intf.sv │ ├── el2_lsu_clkdomain.sv │ ├── el2_lsu_dccm_ctl.sv │ ├── el2_lsu_dccm_mem.sv │ ├── el2_lsu_ecc.sv │ ├── el2_lsu_lsc_ctl.sv │ ├── el2_lsu_stbuf.sv │ └── el2_lsu_trigger.sv ├── docs/ │ ├── Makefile │ ├── dashboard-styles/ │ │ ├── gcov.css │ │ └── main.css │ ├── requirements.txt │ ├── source/ │ │ ├── adaptations.md │ │ ├── build-args.md │ │ ├── cache.md │ │ ├── clocks.md │ │ ├── complex-ports.md │ │ ├── conf.py │ │ ├── core-control.md │ │ ├── csrs.md │ │ ├── debugging.md │ │ ├── dual-core-lock-step.md │ │ ├── errata.md │ │ ├── error-protection.md │ │ ├── index.md │ │ ├── interrupt-priority.md │ │ ├── interrupts.md │ │ ├── intro.md │ │ ├── memory-map.md │ │ ├── overview.md │ │ ├── performance.md │ │ ├── physical-memory-protection.md │ │ ├── power.md │ │ ├── simulation-debugging.md │ │ ├── tests.md │ │ ├── timers.md │ │ ├── tock.md │ │ ├── user-mode.md │ │ └── verification.md │ └── update_styles.sh ├── release-notes.md ├── requirements.txt ├── testbench/ │ ├── ahb_lite_2to1_mux.sv │ ├── ahb_lsu_dma_bridge.sv │ ├── ahb_sif.sv │ ├── asm/ │ │ ├── bitmanip.s │ │ ├── cmark.c │ │ ├── cmark.mki │ │ ├── cmark_iccm.ld │ │ ├── cmark_iccm.mki │ │ ├── common.s │ │ ├── crt0.s │ │ ├── dbus_nonblocking_load_error.s │ │ ├── dbus_store_error.s │ │ ├── dside_access_across_region_boundary.s │ │ ├── dside_access_region_prediction_error.s │ │ ├── dside_core_local_access_unmapped_address_error.s │ │ ├── dside_pic_access_error.s │ │ ├── dside_size_misaligned_access_to_non_idempotent_address.s │ │ ├── ebreak_ecall.s │ │ ├── hello_world.ld │ │ ├── hello_world.s │ │ ├── hello_world_dccm.ld │ │ ├── hello_world_iccm.ld │ │ ├── hello_world_iccm.s │ │ ├── icache.ld │ │ ├── icache.s │ │ ├── illegal_instruction.s │ │ ├── infinite_loop.ld │ │ ├── infinite_loop.s │ │ ├── internal_timer_ints.s │ │ ├── iside_core_local_unmapped_address_error.s │ │ ├── iside_fetch_precise_bus_error.s │ │ ├── lsu_trigger_hit.s │ │ ├── machine_external_ints.s │ │ ├── machine_external_vec_ints.s │ │ ├── nmi_pin_assertion.s │ │ ├── printf.c │ │ ├── read_after_read.ld │ │ ├── read_after_read.mki │ │ ├── read_after_read.s │ │ └── tb.h │ ├── axi4_mux/ │ │ ├── arbiter.v │ │ ├── axi_crossbar.v │ │ ├── axi_crossbar_addr.v │ │ ├── axi_crossbar_rd.v │ │ ├── axi_crossbar_wr.v │ │ ├── axi_crossbar_wrap_2x1.v │ │ ├── axi_register_rd.v │ │ ├── axi_register_wr.v │ │ └── priority_encoder.v │ ├── axi_lsu_dma_bridge.sv │ ├── dasm.svi │ ├── flist │ ├── hex/ │ │ ├── user_mode0/ │ │ │ ├── bitmanip.hex │ │ │ ├── clk_override.hex │ │ │ ├── cmark.hex │ │ │ ├── cmark_dccm.hex │ │ │ ├── cmark_iccm.hex │ │ │ ├── core_pause.hex │ │ │ ├── csr_access.hex │ │ │ ├── csr_misa.hex │ │ │ ├── csr_mstatus.hex │ │ │ ├── dbus_nonblocking_load_error.hex │ │ │ ├── dbus_store_error.hex │ │ │ ├── dhry.hex │ │ │ ├── dside_access_across_region_boundary.hex │ │ │ ├── dside_access_region_prediction_error.hex │ │ │ ├── dside_core_local_access_unmapped_address_error.hex │ │ │ ├── dside_pic_access_error.hex │ │ │ ├── dside_size_misaligned_access_to_non_idempotent_address.hex │ │ │ ├── ebreak_ecall.hex │ │ │ ├── ecc.hex │ │ │ ├── hello_world.hex │ │ │ ├── hello_world_dccm.hex │ │ │ ├── hello_world_iccm.hex │ │ │ ├── icache.hex │ │ │ ├── illegal_instruction.hex │ │ │ ├── infinite_loop.hex │ │ │ ├── insns.hex │ │ │ ├── internal_timer_ints.hex │ │ │ ├── irq.hex │ │ │ ├── iside_core_local_unmapped_address_error.hex │ │ │ ├── iside_fetch_precise_bus_error.hex │ │ │ ├── lsu_trigger_hit.hex │ │ │ ├── machine_external_ints.hex │ │ │ ├── machine_external_vec_ints.hex │ │ │ ├── modesw.hex │ │ │ ├── nmi_pin_assertion.hex │ │ │ ├── perf_counters.hex │ │ │ ├── pmp.hex │ │ │ ├── pmp_random.hex │ │ │ └── write_unaligned.hex │ │ └── user_mode1/ │ │ ├── bitmanip.hex │ │ ├── clk_override.hex │ │ ├── cmark.hex │ │ ├── cmark_dccm.hex │ │ ├── cmark_iccm.hex │ │ ├── core_pause.hex │ │ ├── csr_access.hex │ │ ├── csr_misa.hex │ │ ├── csr_mseccfg.hex │ │ ├── csr_mstatus.hex │ │ ├── dbus_nonblocking_load_error.hex │ │ ├── dbus_store_error.hex │ │ ├── dhry.hex │ │ ├── dside_access_across_region_boundary.hex │ │ ├── dside_access_region_prediction_error.hex │ │ ├── dside_core_local_access_unmapped_address_error.hex │ │ ├── dside_pic_access_error.hex │ │ ├── dside_size_misaligned_access_to_non_idempotent_address.hex │ │ ├── ebreak_ecall.hex │ │ ├── ecc.hex │ │ ├── hello_world.hex │ │ ├── hello_world_dccm.hex │ │ ├── hello_world_iccm.hex │ │ ├── icache.hex │ │ ├── illegal_instruction.hex │ │ ├── infinite_loop.hex │ │ ├── insns.hex │ │ ├── internal_timer_ints.hex │ │ ├── irq.hex │ │ ├── iside_core_local_unmapped_address_error.hex │ │ ├── iside_fetch_precise_bus_error.hex │ │ ├── lsu_trigger_hit.hex │ │ ├── machine_external_ints.hex │ │ ├── machine_external_vec_ints.hex │ │ ├── modesw.hex │ │ ├── nmi_pin_assertion.hex │ │ ├── perf_counters.hex │ │ ├── pmp.hex │ │ ├── pmp_random.hex │ │ └── write_unaligned.hex │ ├── icache_macros.svh │ ├── input.tcl │ ├── jtagdpi/ │ │ ├── README.md │ │ ├── jtagdpi.c │ │ ├── jtagdpi.h │ │ └── jtagdpi.sv │ ├── link.ld │ ├── openocd_scripts/ │ │ ├── common.tcl │ │ ├── jtag_cg.tcl │ │ ├── sim-jtagdpi.cfg │ │ ├── veer-el2-rst.cfg │ │ └── verilator-rst.cfg │ ├── tb_top.sv │ ├── tb_top_pkg.sv │ ├── tcp_server/ │ │ ├── tcp_server.c │ │ └── tcp_server.h │ ├── test_tb_top.cpp │ ├── tests/ │ │ ├── clk_override/ │ │ │ ├── clk_override.c │ │ │ ├── clk_override.ld │ │ │ ├── clk_override.mki │ │ │ └── crt0.s │ │ ├── core_pause/ │ │ │ ├── core_pause.c │ │ │ ├── core_pause.ld │ │ │ ├── core_pause.mki │ │ │ └── crt0.s │ │ ├── csr_access/ │ │ │ ├── crt0.s │ │ │ ├── csr_access.c │ │ │ ├── csr_access.ld │ │ │ ├── csr_access.mki │ │ │ └── veer.c │ │ ├── csr_misa/ │ │ │ ├── crt0.s │ │ │ ├── csr_misa.c │ │ │ ├── csr_misa.ld │ │ │ └── csr_misa.mki │ │ ├── csr_mseccfg/ │ │ │ ├── crt0.s │ │ │ ├── csr_mseccfg.c │ │ │ ├── csr_mseccfg.ld │ │ │ └── csr_mseccfg.mki │ │ ├── csr_mstatus/ │ │ │ ├── crt0.s │ │ │ ├── csr_mstatus.c │ │ │ ├── csr_mstatus.ld │ │ │ └── csr_mstatus.mki │ │ ├── dhry/ │ │ │ ├── dhry.h │ │ │ ├── dhry.mki │ │ │ ├── dhry_1.c │ │ │ └── dhry_2.c │ │ ├── ecc/ │ │ │ ├── crt0.s │ │ │ ├── ecc.c │ │ │ ├── ecc.ld │ │ │ └── ecc.mki │ │ ├── insns/ │ │ │ ├── crt0.s │ │ │ ├── insns.c │ │ │ ├── insns.ld │ │ │ └── insns.mki │ │ ├── irq/ │ │ │ ├── crt0.s │ │ │ ├── irq.c │ │ │ ├── irq.ld │ │ │ └── irq.mki │ │ ├── modesw/ │ │ │ ├── README.md │ │ │ ├── crt0.s │ │ │ ├── modesw.c │ │ │ ├── modesw.ld │ │ │ └── modesw.mki │ │ ├── perf_counters/ │ │ │ ├── crt0.s │ │ │ ├── perf_counters.c │ │ │ ├── perf_counters.ld │ │ │ ├── perf_counters.mki │ │ │ └── veer.c │ │ ├── pmp/ │ │ │ ├── crt0.s │ │ │ ├── fault.c │ │ │ ├── fault.h │ │ │ ├── main.c │ │ │ ├── pmp.c │ │ │ ├── pmp.h │ │ │ ├── pmp.ld │ │ │ ├── pmp.mki │ │ │ ├── trap.h │ │ │ ├── veer.c │ │ │ └── veer.h │ │ ├── pmp_random/ │ │ │ ├── generate_random.sh │ │ │ ├── main.c │ │ │ ├── pmp_random.mki │ │ │ └── random_data.h │ │ └── write_unaligned/ │ │ ├── crt0.s │ │ ├── write_unaligned.c │ │ ├── write_unaligned.ld │ │ └── write_unaligned.mki │ ├── user_cells.sv │ └── veer_wrapper.sv ├── tools/ │ ├── JSON.pm │ ├── Makefile │ ├── addassign │ ├── coredecode │ ├── hex_canned_update.sh │ ├── picmap │ ├── picolibc.mk │ ├── prefix_macros.sh │ ├── renode/ │ │ ├── README.md │ │ ├── build-all-tests.sh │ │ ├── veer.repl │ │ ├── veer.resc │ │ ├── veer.robot │ │ └── veer_smepmp.repl │ ├── riscof/ │ │ ├── README.md │ │ ├── config.ini │ │ ├── spike/ │ │ │ ├── env/ │ │ │ │ ├── link.ld │ │ │ │ └── model_test.h │ │ │ ├── riscof_spike.py │ │ │ ├── spike_isa.yaml │ │ │ └── spike_platform.yaml │ │ └── veer/ │ │ ├── env/ │ │ │ ├── link.ld │ │ │ └── model_test.h │ │ ├── riscof_veer.py │ │ ├── veer_isa.yaml │ │ └── veer_platform.yaml │ ├── riscv-dv/ │ │ ├── Makefile │ │ ├── README.md │ │ ├── code_fixup.py │ │ ├── riscv_core_setting.py │ │ ├── riscv_core_setting.sv │ │ ├── testlist.yaml │ │ ├── user_extension.svh │ │ ├── veer_directed_instr_lib.sv │ │ └── veer_log_to_trace_csv.py │ ├── smalldiv │ ├── unrollforverilator │ └── vivado.tcl ├── verification/ │ ├── block/ │ │ ├── .flake8 │ │ ├── __init__.py │ │ ├── common/ │ │ │ ├── axi.py │ │ │ ├── csrs.py │ │ │ └── utils.py │ │ ├── common.mk │ │ ├── config.vlt │ │ ├── dccm/ │ │ │ ├── Makefile │ │ │ ├── config.vlt │ │ │ ├── el2_lsu_dccm_mem_wrapper.sv │ │ │ ├── test_readwrite.py │ │ │ └── testbench.py │ │ ├── dcls/ │ │ │ ├── Makefile │ │ │ ├── cm.cfg │ │ │ ├── el2_veer_lockstep_wrapper.sv │ │ │ ├── test_lockstep.py │ │ │ └── testbench.py │ │ ├── dec/ │ │ │ ├── Makefile │ │ │ ├── cm.cfg │ │ │ ├── el2_dec_wrapper.sv │ │ │ ├── test_dec.py │ │ │ └── testbench.py │ │ ├── dec_ib/ │ │ │ ├── Makefile │ │ │ ├── config.vlt │ │ │ ├── el2_dec_ib_ctl_wrapper.sv │ │ │ ├── test_dec_ib.py │ │ │ └── testbench.py │ │ ├── dec_pmp_ctl/ │ │ │ ├── Makefile │ │ │ ├── cm.cfg │ │ │ ├── test_dec_pmp_ctl.py │ │ │ └── testbench.py │ │ ├── dec_tl/ │ │ │ ├── Makefile │ │ │ ├── config.vlt │ │ │ ├── el2_dec_trigger_wrapper.sv │ │ │ ├── test_dec_tl.py │ │ │ └── testbench.py │ │ ├── dec_tlu_ctl/ │ │ │ ├── Makefile │ │ │ ├── cm.cfg │ │ │ ├── common.py │ │ │ ├── el2_tlu_ctl_wrapper.sv │ │ │ ├── test_dec_tl.py │ │ │ └── testbench.py │ │ ├── dma/ │ │ │ ├── Makefile │ │ │ ├── cm.cfg │ │ │ ├── scoreboards.py │ │ │ ├── sequences.py │ │ │ ├── test_address.py │ │ │ ├── test_debug_address.py │ │ │ ├── test_debug_read.py │ │ │ ├── test_debug_write.py │ │ │ ├── test_ecc.py │ │ │ ├── test_read.py │ │ │ ├── test_reset.py │ │ │ ├── test_write.py │ │ │ └── testbench.py │ │ ├── dmi/ │ │ │ ├── Makefile │ │ │ ├── cm.cfg │ │ │ ├── common.py │ │ │ ├── config.vlt │ │ │ ├── dmi_agent.py │ │ │ ├── dmi_bfm.py │ │ │ ├── dmi_seq.py │ │ │ ├── dmi_test_wrapper.sv │ │ │ ├── jtag_agent.py │ │ │ ├── jtag_bfm.py │ │ │ ├── jtag_pkg.py │ │ │ ├── jtag_predictor.py │ │ │ ├── jtag_seq.py │ │ │ ├── test_dmi_read_write.py │ │ │ ├── test_dmi_tap_fsm.py │ │ │ ├── test_jtag_ir.py │ │ │ └── testbench.py │ │ ├── exu_alu/ │ │ │ ├── Makefile │ │ │ ├── config.vlt │ │ │ ├── el2_exu_alu_ctl_wrapper.sv │ │ │ ├── test_arith.py │ │ │ ├── test_logic.py │ │ │ ├── test_zba.py │ │ │ ├── test_zbb.py │ │ │ ├── test_zbp.py │ │ │ ├── test_zbs.py │ │ │ └── testbench.py │ │ ├── exu_div/ │ │ │ ├── Makefile │ │ │ ├── config.vlt │ │ │ ├── el2_exu_div_ctl_wrapper.sv │ │ │ ├── test_div.py │ │ │ └── testbench.py │ │ ├── exu_mul/ │ │ │ ├── Makefile │ │ │ ├── cm.cfg │ │ │ ├── config.vlt │ │ │ ├── el2_exu_mul_ctl_wrapper.sv │ │ │ ├── test_mul.py │ │ │ └── testbench.py │ │ ├── iccm/ │ │ │ ├── Makefile │ │ │ ├── config.vlt │ │ │ ├── el2_ifu_iccm_mem_wrapper.sv │ │ │ ├── test_readwrite.py │ │ │ └── testbench.py │ │ ├── ifu_compress/ │ │ │ ├── Makefile │ │ │ ├── cm.cfg │ │ │ ├── test_compress.py │ │ │ └── testbench.py │ │ ├── ifu_mem_ctl/ │ │ │ ├── Makefile │ │ │ ├── cm.cfg │ │ │ ├── common.py │ │ │ ├── el2_ifu_mem_ctl_wrapper.sv │ │ │ ├── test_err.py │ │ │ ├── test_err_stop.py │ │ │ └── test_miss.py │ │ ├── lib_ahb_to_axi4/ │ │ │ ├── Makefile │ │ │ ├── ahb_to_axi4_wrapper.sv │ │ │ ├── test_read.py │ │ │ ├── test_write.py │ │ │ ├── testbench.py │ │ │ └── ucli.key │ │ ├── lib_axi4_to_ahb/ │ │ │ ├── Makefile │ │ │ ├── ahb_lite_agent.py │ │ │ ├── ahb_lite_bfm.py │ │ │ ├── ahb_lite_pkg.py │ │ │ ├── ahb_lite_seq.py │ │ │ ├── axi_pkg.py │ │ │ ├── axi_r_agent.py │ │ │ ├── axi_r_bfm.py │ │ │ ├── axi_r_seq.py │ │ │ ├── axi_w_agent.py │ │ │ ├── axi_w_bfm.py │ │ │ ├── axi_w_seq.py │ │ │ ├── cm.cfg │ │ │ ├── common.py │ │ │ ├── coordinator_seq.py │ │ │ ├── test_axi.py │ │ │ ├── test_axi_read_channel.py │ │ │ ├── test_axi_write_channel.py │ │ │ ├── testbench.py │ │ │ └── ucli.key │ │ ├── lsu_tl/ │ │ │ ├── Makefile │ │ │ ├── config.vlt │ │ │ ├── el2_lsu_trigger_wrapper.sv │ │ │ ├── test_lsu_tl.py │ │ │ └── testbench.py │ │ ├── noxfile.py │ │ ├── pic/ │ │ │ ├── Makefile │ │ │ ├── test_clken.py │ │ │ ├── test_config.py │ │ │ ├── test_pending.py │ │ │ ├── test_prioritization.py │ │ │ ├── test_reset.py │ │ │ ├── test_servicing.py │ │ │ └── testbench.py │ │ ├── pic_gw/ │ │ │ ├── Makefile │ │ │ └── test_gateway.py │ │ ├── pmp/ │ │ │ ├── Makefile │ │ │ ├── common.py │ │ │ ├── config.vlt │ │ │ ├── el2_pmp_wrapper.sv │ │ │ ├── test_address_matching.py │ │ │ ├── test_multiple_configs.py │ │ │ ├── test_xwr_access.py │ │ │ └── testbench.py │ │ ├── pmp_random/ │ │ │ ├── Makefile │ │ │ ├── config.vlt │ │ │ ├── el2_pmp_wrapper.sv │ │ │ ├── test_pmp_random.py │ │ │ └── testbench.py │ │ ├── pyproject.toml │ │ └── requirements.txt │ ├── test_debug/ │ │ └── test_debug.py │ └── top/ │ ├── README.md │ ├── requirements.txt │ └── test_pyuvm/ │ ├── Makefile │ ├── __init__.py │ ├── cm.cfg │ ├── conftest.py │ ├── test_irq/ │ │ ├── irq_utils.py │ │ ├── irq_uvm.py │ │ └── test_irq.py │ └── test_pyuvm.py └── violations.waiver
SYMBOL INDEX (1940 symbols across 149 files)
FILE: .github/scripts/indexgen/generate.py
function render_template (line 11) | def render_template(src, dst, **kwargs):
function make_coverage_report_index (line 23) | def make_coverage_report_index(branch, root, output, templates):
function make_verification_report_index (line 80) | def make_verification_report_index(branch, root, output, templates):
function make_dev_index (line 117) | def make_dev_index(branches, output, templates):
function main (line 139) | def main():
FILE: .github/scripts/indexgen/source.template/conf.py
function setup (line 91) | def setup(app):
FILE: .github/scripts/pytest/script/script.js
function previousPage (line 1) | function previousPage() {
FILE: .github/scripts/riscv_dv_parse_testlist.py
function parse_yaml (line 10) | def parse_yaml(path: str) -> Generator[str, None, None]:
FILE: configs/veer_config_gen.py
class VeerConfigGenerator (line 7) | class VeerConfigGenerator(Generator):
method run (line 8) | def run(self):
FILE: docs/source/conf.py
function setup (line 62) | def setup(app):
FILE: testbench/asm/cmark.c
type clock_t (line 117) | typedef clock_t CORE_TICKS;
type ee_s16 (line 144) | typedef signed short ee_s16;
type ee_u16 (line 145) | typedef unsigned short ee_u16;
type ee_s32 (line 146) | typedef signed int ee_s32;
type ee_f32 (line 147) | typedef double ee_f32;
type ee_u8 (line 148) | typedef unsigned char ee_u8;
type ee_u32 (line 149) | typedef unsigned int ee_u32;
type ee_u32 (line 150) | typedef ee_u32 ee_ptr_int;
type ee_size_t (line 151) | typedef size_t ee_size_t;
type core_portable (line 234) | typedef struct CORE_PORTABLE_S {
type secs_ret (line 272) | typedef double secs_ret;
type ee_u32 (line 274) | typedef ee_u32 secs_ret;
type list_data (line 308) | typedef struct list_data_s {
type list_head (line 313) | typedef struct list_head_s {
type ee_s16 (line 322) | typedef ee_s16 MATDAT;
type ee_s32 (line 323) | typedef ee_s32 MATRES;
type ee_f16 (line 325) | typedef ee_f16 MATDAT;
type ee_f32 (line 326) | typedef ee_f32 MATRES;
type mat_params (line 329) | typedef struct MAT_PARAMS_S {
type core_state_e (line 338) | typedef enum CORE_STATE {
type core_results (line 352) | typedef struct RESULTS_S {
type ee_s32 (line 435) | typedef ee_s32(*list_cmp)(list_data *a, list_data *b, core_results *res);
function ee_s16 (line 438) | ee_s16 calc_func(ee_s16 *pdata, core_results *res) {
function ee_s32 (line 476) | ee_s32 cmp_complex(list_data *a, list_data *b, core_results *res) {
function ee_s32 (line 487) | ee_s32 cmp_idx(list_data *a, list_data *b, core_results *res) {
function copy_info (line 495) | void copy_info(list_data *to,list_data *from) {
function ee_u16 (line 507) | ee_u16 core_bench_list(core_results *res, ee_s16 finder_idx) {
function list_head (line 588) | list_head *core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 se...
function list_head (line 657) | list_head *core_list_insert_new(list_head *insert_point, list_data *info...
function list_head (line 691) | list_head *core_list_remove(list_head *item) {
function list_head (line 720) | list_head *core_list_undo_remove(list_head *item_removed, list_head *ite...
function list_head (line 745) | list_head *core_list_find(list_head *list,list_data *info) {
function list_head (line 770) | list_head *core_list_reverse(list_head *list) {
function list_head (line 801) | list_head *core_list_mergesort(list_head *list, list_cmp cmp, core_resul...
function MAIN_RETURN_TYPE (line 960) | MAIN_RETURN_TYPE main(void) {
function core_init_state (line 1659) | void core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p) {
function ee_u8 (line 1711) | static ee_u8 ee_isdigit(ee_u8 c) {
function core_state_transition (line 1727) | enum CORE_STATE core_state_transition( ee_u8 **instr , ee_u32 *transitio...
function ee_s32 (line 1859) | ee_s32 get_seed_32(int i) {
function ee_s32 (line 1884) | ee_s32 parseval(char *valstring) {
function ee_s32 (line 1924) | ee_s32 get_seed_args(int i, int argc, char *argv[]) {
function ee_s32 (line 1932) | ee_s32 get_seed_32(int i) {
function ee_u16 (line 1962) | ee_u16 crcu8(ee_u8 data, ee_u16 crc )
function ee_u16 (line 1986) | ee_u16 crcu16(ee_u16 newval, ee_u16 crc) {
function ee_u16 (line 1991) | ee_u16 crcu32(ee_u32 newval, ee_u16 crc) {
function ee_u16 (line 1996) | ee_u16 crc16(ee_s16 newval, ee_u16 crc) {
function ee_u8 (line 2000) | ee_u8 check_data_types() {
function start_time (line 2091) | void start_time(void) {
function stop_time (line 2102) | void stop_time(void) {
function CORE_TICKS (line 2116) | CORE_TICKS get_time(void) {
function secs_ret (line 2126) | secs_ret time_in_secs(CORE_TICKS ticks) {
function portable_init (line 2137) | void portable_init(core_portable *p, int *argc, char *argv[])
function portable_fini (line 2150) | void portable_fini(core_portable *p)
FILE: testbench/asm/printf.c
function whisperPutc (line 21) | static int
function whisperPuts (line 29) | static int
function whisperPrintUnsigned (line 40) | static int
function whisperPrintDecimal (line 65) | static int
function whisperPrintInt (line 101) | static int
function whisperPrintfImpl (line 160) | int
function whisperPrintf (line 252) | int
function putchar (line 264) | int
type FILE (line 270) | struct FILE
function putc (line 272) | int
function puts (line 279) | int
function printf (line 285) | int
function get_mcycle (line 299) | uint64_t get_mcycle(){
FILE: testbench/jtagdpi/jtagdpi.c
type jtagdpi_signals (line 20) | struct jtagdpi_signals {
type jtagdpi_ctx (line 29) | struct jtagdpi_ctx {
function reset_jtag_signals (line 43) | static void reset_jtag_signals(struct jtagdpi_ctx *ctx) {
function update_jtag_signals (line 63) | static void update_jtag_signals(struct jtagdpi_ctx *ctx) {
type jtagdpi_ctx (line 124) | struct jtagdpi_ctx
type jtagdpi_ctx (line 125) | struct jtagdpi_ctx
type jtagdpi_ctx (line 125) | struct jtagdpi_ctx
function jtagdpi_close (line 148) | void jtagdpi_close(void *ctx_void) {
function jtagdpi_dbg (line 158) | static void jtagdpi_dbg(struct jtagdpi_ctx *ctx) {
function jtagdpi_tick (line 186) | void jtagdpi_tick(void *ctx_void, svBit *tck, svBit *tms, svBit *tdi,
FILE: testbench/jtagdpi/jtagdpi.h
type jtagdpi_ctx (line 15) | struct jtagdpi_ctx
FILE: testbench/tcp_server/tcp_server.c
type tcp_buf (line 28) | struct tcp_buf {
type tcp_server_ctx (line 37) | struct tcp_server_ctx {
function tcp_buffer_is_full (line 50) | static bool tcp_buffer_is_full(struct tcp_buf *buf) {
function tcp_buffer_is_empty (line 58) | static bool tcp_buffer_is_empty(struct tcp_buf *buf) {
function tcp_buffer_put_byte (line 62) | static void tcp_buffer_put_byte(struct tcp_buf *buf, char dat) {
function tcp_buffer_get_byte (line 73) | static bool tcp_buffer_get_byte(struct tcp_buf *buf, char *dat) {
type tcp_buf (line 82) | struct tcp_buf
type tcp_buf (line 83) | struct tcp_buf
type tcp_buf (line 84) | struct tcp_buf
type tcp_buf (line 84) | struct tcp_buf
function tcp_buffer_free (line 90) | static void tcp_buffer_free(struct tcp_buf **buf) {
function start (line 104) | static int start(struct tcp_server_ctx *ctx) {
function client_tryaccept (line 179) | static int client_tryaccept(struct tcp_server_ctx *ctx) {
function stop (line 217) | static void stop(struct tcp_server_ctx *ctx) {
function get_byte (line 233) | static bool get_byte(struct tcp_server_ctx *ctx, char *cmd) {
function put_byte (line 265) | static void put_byte(struct tcp_server_ctx *ctx, char cmd) {
function ctx_free (line 292) | static void ctx_free(struct tcp_server_ctx *ctx) {
type tcp_server_ctx (line 311) | struct tcp_server_ctx
type tcp_server_ctx (line 311) | struct tcp_server_ctx
type timeval (line 312) | struct timeval
type tcp_server_ctx (line 383) | struct tcp_server_ctx
type tcp_server_ctx (line 385) | struct tcp_server_ctx
type tcp_server_ctx (line 386) | struct tcp_server_ctx
type tcp_server_ctx (line 386) | struct tcp_server_ctx
type tcp_buf (line 390) | struct tcp_buf
type tcp_buf (line 391) | struct tcp_buf
function tcp_server_read (line 416) | bool tcp_server_read(struct tcp_server_ctx *ctx, char *dat) {
function tcp_server_write (line 420) | void tcp_server_write(struct tcp_server_ctx *ctx, char dat) {
function tcp_server_close (line 424) | void tcp_server_close(struct tcp_server_ctx *ctx) {
function tcp_server_client_close (line 431) | void tcp_server_client_close(struct tcp_server_ctx *ctx) {
FILE: testbench/tcp_server/tcp_server.h
type tcp_server_ctx (line 23) | struct tcp_server_ctx
type tcp_server_ctx (line 32) | struct tcp_server_ctx
type tcp_server_ctx (line 43) | struct tcp_server_ctx
type tcp_server_ctx (line 52) | struct tcp_server_ctx
type tcp_server_ctx (line 60) | struct tcp_server_ctx
type tcp_server_ctx (line 67) | struct tcp_server_ctx
FILE: testbench/test_tb_top.cpp
function sc_time_stamp (line 29) | double sc_time_stamp () {
function load_symbols (line 33) | std::map<std::string, uint64_t> load_symbols (const std::string& fileNam...
function main (line 64) | int main(int argc, char** argv) {
FILE: testbench/tests/clk_override/clk_override.c
function main (line 4) | int main () {
FILE: testbench/tests/core_pause/core_pause.c
function main (line 4) | int main () {
FILE: testbench/tests/csr_access/csr_access.c
type csr_t (line 19) | struct csr_t {
type csr_t (line 24) | struct csr_t
type csr_t (line 128) | struct csr_t
function read_csr (line 137) | unsigned long read_csr (uint32_t addr) {
function write_csr (line 251) | void write_csr (uint32_t addr, uint32_t val) {
function test_csr_read_access (line 276) | void test_csr_read_access (uint8_t user_mode) {
function test_csr_write_access (line 315) | void test_csr_write_access (uint8_t user_mode) {
function trap_handler (line 350) | void trap_handler () {
function main (line 367) | int main () {
function user_main (line 402) | __attribute__((noreturn)) void user_main () {
function machine_main (line 422) | __attribute__((noreturn)) void machine_main () {
FILE: testbench/tests/csr_access/veer.c
function _exit (line 23) | __attribute__((__noreturn__)) void _exit (int status)
function veer_tb_putc (line 30) | int veer_tb_putc(char c, FILE *stream)
FILE: testbench/tests/csr_misa/csr_misa.c
function main (line 10) | int main () {
FILE: testbench/tests/csr_mseccfg/csr_mseccfg.c
function main (line 58) | int main () {
FILE: testbench/tests/csr_mstatus/csr_mstatus.c
function main (line 15) | int main () {
FILE: testbench/tests/dhry/dhry.h
type Enumeration (line 391) | typedef int Enumeration;
type Enumeration (line 393) | typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5}
type One_Thirty (line 408) | typedef int One_Thirty;
type One_Fifty (line 409) | typedef int One_Fifty;
type Capital_Letter (line 410) | typedef char Capital_Letter;
type Boolean (line 411) | typedef int Boolean;
type Rec_Type (line 416) | typedef struct record
FILE: testbench/tests/dhry/dhry_1.c
type tms (line 53) | struct tms
function main (line 99) | int
function Proc_1 (line 343) | void
function Proc_2 (line 378) | void
function Proc_3 (line 402) | void
function Proc_4 (line 418) | void
function Proc_5 (line 431) | void
FILE: testbench/tests/dhry/dhry_2.c
function strcmp (line 30) | int
function Proc_6 (line 49) | void
function Proc_7 (line 84) | void
function Proc_8 (line 105) | void
function Enumeration (line 131) | Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val)
function Boolean (line 157) | Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref)
function Boolean (line 199) | Boolean Func_3 (Enum_Par_Val)
FILE: testbench/tests/ecc/ecc.c
function sleep (line 45) | void sleep(uint32_t count) {
function read_mcause (line 51) | int read_mcause(void) {
function read_mscause (line 62) | int read_mscause(void) {
function read_mfdc (line 73) | int read_mfdc(void) {
function read_mdccmect (line 84) | int read_mdccmect(void) {
function read_miccmect (line 95) | int read_miccmect(void) {
function clear_causes (line 106) | void clear_causes(void) {
function disable_ecc_check (line 117) | void disable_ecc_check(void) {
function enable_ecc_check (line 126) | void enable_ecc_check(void) {
function trap_handler (line 135) | void trap_handler(void) {
function run_iccm_err_test (line 163) | void run_iccm_err_test(int execute) {
function run_dccm_err_test (line 212) | void run_dccm_err_test(void) {
function execute_from_iccm (line 241) | void execute_from_iccm (void) {
function main (line 245) | void main(void)
FILE: testbench/tests/insns/insns.c
type trap_info_t (line 27) | struct trap_info_t {
type trap_info_t (line 32) | struct trap_info_t
function trap_handler (line 34) | void trap_handler () {
function clear_trap (line 46) | void clear_trap () {
function check (line 53) | void check (int cond) {
function main (line 64) | int main () {
function user_main (line 113) | __attribute__((noreturn)) void user_main () {
FILE: testbench/tests/irq/irq.c
function trigger_nmi_irq (line 50) | void trigger_nmi_irq (int state) {
function trigger_timer_irq (line 55) | void trigger_timer_irq (int state) {
function trigger_soft_irq (line 60) | void trigger_soft_irq (int state) {
function trigger_ext_irq (line 65) | void trigger_ext_irq (int state, int irq) {
function release_all_irqs (line 70) | void release_all_irqs () {
type trap_data_t (line 76) | struct trap_data_t {
type trap_data_t (line 81) | struct trap_data_t
function trap_handler (line 84) | void trap_handler () {
function nmi_handler (line 103) | void nmi_handler () {
function main (line 112) | int main () {
function user_main (line 226) | __attribute__((noreturn)) void user_main () {
FILE: testbench/tests/modesw/modesw.c
type trap_data_t (line 32) | struct trap_data_t {
type trap_data_t (line 37) | struct trap_data_t
function trap_handler (line 42) | int32_t trap_handler (uint32_t cmd, uint32_t arg) {
function main (line 89) | int main () {
function user_main (line 182) | __attribute__((noreturn)) void user_main () {
FILE: testbench/tests/perf_counters/perf_counters.c
function ecall_handler (line 82) | int32_t ecall_handler (uint32_t cmd, uint32_t arg) {
function trap_handler (line 99) | int32_t trap_handler (uint32_t a0, uint32_t a1) {
function main (line 118) | int main () {
function read_and_check (line 171) | uint32_t read_and_check (int32_t csr, int should_succeed) {
function read_and_check64 (line 218) | uint64_t read_and_check64(int32_t csr_base, int should_succeed) {
function check_counters (line 226) | void check_counters (const uint64_t* cur_counters) {
function user_main (line 262) | __attribute__((noreturn)) void user_main () {
FILE: testbench/tests/perf_counters/veer.c
function _exit (line 23) | __attribute__((__noreturn__)) void _exit (int status)
function veer_tb_putc (line 30) | int veer_tb_putc(char c, FILE *stream)
FILE: testbench/tests/pmp/fault.c
type rv_jmp_buf (line 23) | struct rv_jmp_buf
type fault (line 24) | struct fault
function fault_setjmp (line 26) | void fault_setjmp(struct rv_jmp_buf* env)
function fault_last_get (line 31) | struct fault fault_last_get(void)
function fault_return (line 36) | void fault_return(const struct fault *fault)
FILE: testbench/tests/pmp/fault.h
type rv_jmp_buf (line 27) | struct rv_jmp_buf
type fault (line 28) | struct fault
type fault (line 29) | struct fault
FILE: testbench/tests/pmp/main.c
function test_hello (line 90) | void __attribute__((noinline)) test_hello () {
function test_read (line 95) | int __attribute__((noinline)) test_read (const uint32_t* pattern) {
function test_write (line 115) | void __attribute__((noinline)) test_write (const uint32_t* pattern) {
function test_exec (line 124) | void __attribute__((noinline, section(".area.code"))) test_exec () {
function trap_handler (line 132) | int trap_handler (const struct fault* fault) {
function main (line 179) | int main () {
type pmp_entry_s (line 422) | struct pmp_entry_s
FILE: testbench/tests/pmp/pmp.c
function pmp_clear (line 4) | int pmp_clear ()
function pmp_read_pmpcfg (line 25) | int pmp_read_pmpcfg(unsigned int offset, uintptr_t * dest)
function pmp_read_pmpaddr (line 56) | int pmp_read_pmpaddr(unsigned int offset, uintptr_t * dest)
function pmp_write_pmpcfg (line 139) | int pmp_write_pmpcfg(unsigned int offset, uintptr_t * src)
function pmp_write_pmpaddr (line 171) | int pmp_write_pmpaddr(unsigned int offset, uintptr_t * src)
function pmp_entry_read (line 254) | int pmp_entry_read(unsigned int id, struct pmp_entry_s * entry)
function pmp_entry_write (line 281) | int pmp_entry_write(unsigned int id, struct pmp_entry_s * entry)
function pmp_is_cfg_legal (line 308) | int pmp_is_cfg_legal (unsigned int cfg) {
FILE: testbench/tests/pmp/pmp.h
type pmp_entry_s (line 36) | struct pmp_entry_s {
type pmp_entry_s (line 46) | struct pmp_entry_s
type pmp_entry_s (line 47) | struct pmp_entry_s
FILE: testbench/tests/pmp/trap.h
type fault (line 43) | struct fault {
FILE: testbench/tests/pmp/veer.c
function veer_syscall (line 27) | int64_t veer_syscall (int64_t a0, int64_t a1, int64_t a2, int64_t a3) {
function _exit (line 55) | __attribute__((__noreturn__)) void _exit (int status)
function veer_tb_putc (line 66) | int veer_tb_putc(char c, FILE *stream)
FILE: testbench/tests/pmp/veer.h
type rv_jmp_buf (line 25) | struct rv_jmp_buf {
type rv_jmp_buf (line 32) | struct rv_jmp_buf
type rv_jmp_buf (line 34) | struct rv_jmp_buf
FILE: testbench/tests/pmp_random/main.c
function test_hello (line 79) | void __attribute__((noinline)) test_hello () {
function test_read (line 84) | int __attribute__((noinline)) test_read (const uint32_t* pattern, uint32...
function test_write (line 99) | void __attribute__((noinline)) test_write (const uint32_t* pattern, uint...
function test_exec (line 106) | void __attribute__((noinline, naked, optimize("O0"), section(".area.code...
function trap_handler (line 114) | int trap_handler (const struct fault* fault) {
type RegionType (line 134) | enum RegionType {
function reconcile_address (line 141) | uint32_t reconcile_address(uint32_t address) {
function legalize_address (line 166) | uint32_t legalize_address(uintptr_t address, enum RegionType region_type) {
function legalize_config (line 191) | uint8_t legalize_config(uint32_t config) {
function generate_napot_mask (line 233) | uint32_t generate_napot_mask(uint32_t value) {
function get_effective_range (line 241) | int get_effective_range(uintptr_t * const address, enum RegionType regio...
function main (line 284) | int main () {
FILE: testbench/tests/write_unaligned/write_unaligned.c
function handler (line 5) | int handler() {
function main (line 9) | int main () {
FILE: tools/riscof/spike/riscof_spike.py
class spike (line 18) | class spike(pluginTemplate):
method __init__ (line 22) | def __init__(self, *args, **kwargs):
method initialise (line 60) | def initialise(self, suite, work_dir, archtest_env):
method build (line 81) | def build(self, isa_yaml, platform_yaml):
method runTests (line 108) | def runTests(self, testList):
FILE: tools/riscof/veer/riscof_veer.py
class veer (line 18) | class veer(pluginTemplate):
method __init__ (line 22) | def __init__(self, *args, **kwargs):
method initialise (line 57) | def initialise(self, suite, work_dir, archtest_env):
method build (line 83) | def build(self, isa_yaml, platform_yaml):
method runTests (line 108) | def runTests(self, testList):
FILE: tools/riscv-dv/code_fixup.py
class AssemblyLine (line 7) | class AssemblyLine:
method __init__ (line 14) | def __init__(self, text):
method __str__ (line 37) | def __str__(self):
function main (line 45) | def main():
FILE: tools/riscv-dv/riscv_core_setting.py
function check_sha256 (line 26) | def check_sha256(path: Path, exp_sha256: str):
function _parse_enum_with_one_hex (line 36) | def _parse_enum_with_one_hex(content: List[str], regexp: str, lower: int...
function _parse_enum_with_insn (line 54) | def _parse_enum_with_insn(content: List[str], lower: int, upper: int):
function parse_riscv_instr_pkg (line 85) | def parse_riscv_instr_pkg(riscv_instr_pkg_path: Path):
function _parse_veer_decode (line 99) | def _parse_veer_decode(content: List[str], lower: int, upper: int, repla...
function parse_veer_decode (line 116) | def parse_veer_decode(decode_path: Path):
function _parse_veer_csrdecode (line 122) | def _parse_veer_csrdecode(content: List[str], lower: int, upper: int, re...
function parse_veer_csrdecode (line 140) | def parse_veer_csrdecode(csrdecode_path: Path):
function _parse_veer_irqs_and_excp (line 146) | def _parse_veer_irqs_and_excp(content: List[str], lower: int, upper: int):
function parse_veer_dec_tlu_ctl (line 163) | def parse_veer_dec_tlu_ctl(dec_tlu_ctl_path: Path):
function inv_dict (line 175) | def inv_dict(data: Dict) -> Dict:
function remove_suffix_number (line 182) | def remove_suffix_number(string: str) -> str:
function count_nonempty (line 185) | def count_nonempty(d: Dict) -> int:
FILE: tools/riscv-dv/veer_log_to_trace_csv.py
function parse_log (line 25) | def parse_log(file_name):
function write_csv (line 177) | def write_csv(file_name, data):
function main (line 193) | def main():
FILE: verification/block/common/axi.py
class BusWriteItem (line 12) | class BusWriteItem(uvm_sequence_item):
method __init__ (line 17) | def __init__(self, addr, data, resp=None):
class BusReadItem (line 24) | class BusReadItem(uvm_sequence_item):
method __init__ (line 29) | def __init__(self, addr, data=None, resp=None):
class Axi4LiteMonitor (line 39) | class Axi4LiteMonitor(uvm_component):
class Transfer (line 44) | class Transfer:
method __init__ (line 45) | def __init__(self, tid, addr=None):
method __init__ (line 50) | def __init__(self, *args, **kwargs):
method build_phase (line 55) | def build_phase(self):
method _aw_active (line 58) | def _aw_active(self):
method _w_active (line 61) | def _w_active(self):
method _ar_active (line 64) | def _ar_active(self):
method _r_active (line 67) | def _r_active(self):
method _b_active (line 70) | def _b_active(self):
method _sample_w (line 73) | def _sample_w(self):
method _sample_r (line 79) | def _sample_r(self):
method watch_write (line 84) | async def watch_write(self):
method watch_read (line 138) | async def watch_read(self):
method run_phase (line 184) | async def run_phase(self):
FILE: verification/block/common/csrs.py
class CSR (line 4) | class CSR(int):
method __new__ (line 5) | def __new__(cls, addr: int, out: Callable[[int], int] = lambda x: x):
function get_bit (line 11) | def get_bit(value, i):
function _prevent_11_pairs (line 15) | def _prevent_11_pairs(value):
function _mhpme_zero_event (line 25) | def _mhpme_zero_event(value):
function _m_ect (line 35) | def _m_ect(value):
function _dicawics (line 42) | def _dicawics(value):
function _dcsr (line 55) | def _dcsr(value):
FILE: verification/block/common/utils.py
function collect_signals (line 11) | def collect_signals(signals, uut, obj, uut_prefix="", obj_prefix="", sig...
function collect_bytes (line 35) | def collect_bytes(data, strb=None):
function smallest_number_of_trials (line 54) | def smallest_number_of_trials(p: float, k: int, j: float):
FILE: verification/block/dccm/test_readwrite.py
class ReadWriteSequence (line 13) | class ReadWriteSequence(uvm_sequence):
method __init__ (line 20) | def __init__(self, name):
method body (line 23) | async def body(self):
class TestReadWrite (line 51) | class TestReadWrite(BaseTest):
method end_of_elaboration_phase (line 52) | def end_of_elaboration_phase(self):
method run (line 56) | async def run(self):
FILE: verification/block/dccm/testbench.py
class MemWriteItem (line 14) | class MemWriteItem(uvm_sequence_item):
method __init__ (line 19) | def __init__(self, addr, data):
class MemReadItem (line 25) | class MemReadItem(uvm_sequence_item):
method __init__ (line 30) | def __init__(self, addr, data=None):
class MemDriver (line 39) | class MemDriver(uvm_driver):
method __init__ (line 44) | def __init__(self, *args, **kwargs):
method run_phase (line 49) | async def run_phase(self):
class MemMonitor (line 88) | class MemMonitor(uvm_component):
method __init__ (line 93) | def __init__(self, *args, **kwargs):
method build_phase (line 98) | def build_phase(self):
method run_phase (line 101) | async def run_phase(self):
class Scoreboard (line 129) | class Scoreboard(uvm_component):
method __init__ (line 135) | def __init__(self, name, parent):
method build_phase (line 139) | def build_phase(self):
method connect_phase (line 143) | def connect_phase(self):
method check_phase (line 146) | def check_phase(self):
method final_phase (line 197) | def final_phase(self):
class BaseEnv (line 206) | class BaseEnv(uvm_env):
method build_phase (line 211) | def build_phase(self):
method connect_phase (line 232) | def connect_phase(self):
class BaseTest (line 240) | class BaseTest(uvm_test):
method __init__ (line 245) | def __init__(self, name, parent, env_class=BaseEnv):
method build_phase (line 254) | def build_phase(self):
method start_clock (line 257) | def start_clock(self, name):
method do_reset (line 263) | async def do_reset(self):
method run_phase (line 269) | async def run_phase(self):
method run (line 290) | async def run(self):
FILE: verification/block/dcls/test_lockstep.py
class TestReset (line 16) | class TestReset(BaseTest):
method assert_signals (line 22) | def assert_signals(self, signals):
method test_reset (line 34) | async def test_reset(self):
method run (line 53) | async def run(self):
class TestErrorInjection (line 58) | class TestErrorInjection(TestReset):
method run (line 63) | async def run(self):
FILE: verification/block/dcls/testbench.py
class BaseEnv (line 12) | class BaseEnv(uvm_env):
method build_phase (line 17) | def build_phase(self):
method connect_phase (line 22) | def connect_phase(self):
class BaseTest (line 29) | class BaseTest(uvm_test):
method __init__ (line 34) | def __init__(self, name, parent, env_class=BaseEnv):
method build_phase (line 45) | def build_phase(self):
method start_clock (line 48) | def start_clock(self, name):
method do_reset (line 54) | async def do_reset(self):
method run_phase (line 62) | async def run_phase(self):
method run (line 80) | async def run(self):
FILE: verification/block/dec/test_dec.py
class DecTluCtlTest (line 10) | class DecTluCtlTest(BaseTest):
method __init__ (line 11) | def __init__(self, test_name, name, parent, env_class=BaseEnv):
method end_of_elaboration_phase (line 15) | def end_of_elaboration_phase(self):
method run (line 20) | async def run(self):
class TestMeihap (line 25) | class TestMeihap(DecTluCtlTest):
method __init__ (line 26) | def __init__(self, name, parent, env_class=BaseEnv):
class TestMtdata (line 31) | class TestMtdata(DecTluCtlTest):
method __init__ (line 32) | def __init__(self, name, parent, env_class=BaseEnv):
class TestCsrAccess (line 37) | class TestCsrAccess(DecTluCtlTest):
method __init__ (line 38) | def __init__(self, name, parent, env_class=BaseEnv):
class TestDebugICCache (line 43) | class TestDebugICCache(DecTluCtlTest):
method __init__ (line 44) | def __init__(self, name, parent, env_class=BaseEnv):
class TestDebugCSRs (line 49) | class TestDebugCSRs(DecTluCtlTest):
method __init__ (line 50) | def __init__(self, name, parent, env_class=BaseEnv):
class TestMeicidpl (line 55) | class TestMeicidpl(DecTluCtlTest):
method __init__ (line 56) | def __init__(self, name, parent, env_class=BaseEnv):
FILE: verification/block/dec/testbench.py
class TriggerAnyPktT (line 33) | class TriggerAnyPktT:
method get_from_dut (line 43) | def get_from_dut(dut):
function log_mismatch_error (line 62) | def log_mismatch_error(logger, name, expected, got):
class Funct3 (line 70) | class Funct3(IntEnum):
function csr_access_inst (line 79) | def csr_access_inst(csr, rs1, funct3, rd, opcode):
class ReadCSRInst (line 95) | class ReadCSRInst:
method encode (line 99) | def encode(self):
class WriteCSRInst (line 104) | class WriteCSRInst:
method encode (line 108) | def encode(self):
function randint (line 112) | def randint(width=32):
class DecInputItem (line 116) | class DecInputItem(uvm_sequence_item):
method __init__ (line 121) | def __init__(
method randomize (line 146) | def randomize(self, test):
class DecOutputItem (line 214) | class DecOutputItem(uvm_sequence_item):
method __init__ (line 219) | def __init__(
class DecDriver (line 240) | class DecDriver(uvm_driver):
method __init__ (line 245) | def __init__(self, *args, **kwargs):
method read_csr (line 250) | async def read_csr(self, instr):
method write_csr (line 259) | async def write_csr(self, instr, data):
method run_phase (line 271) | async def run_phase(self):
class DecInputMonitor (line 323) | class DecInputMonitor(uvm_component):
method __init__ (line 328) | def __init__(self, *args, **kwargs):
method build_phase (line 333) | def build_phase(self):
method run_phase (line 336) | async def run_phase(self):
class DecOutputMonitor (line 404) | class DecOutputMonitor(uvm_component):
method __init__ (line 409) | def __init__(self, *args, **kwargs):
method build_phase (line 414) | def build_phase(self):
method run_phase (line 417) | async def run_phase(self):
class DecScoreboard (line 482) | class DecScoreboard(uvm_component):
method __init__ (line 487) | def __init__(self, name, parent):
method build_phase (line 492) | def build_phase(self):
method connect_phase (line 498) | def connect_phase(self):
method check_phase (line 502) | def check_phase(self): # noqa: C901
method final_phase (line 642) | def final_phase(self):
class DecSequence (line 651) | class DecSequence(uvm_sequence):
method __init__ (line 653) | def __init__(self, name, ops=None):
method body (line 656) | async def body(self):
class BaseEnv (line 671) | class BaseEnv(uvm_env):
method build_phase (line 676) | def build_phase(self):
method connect_phase (line 694) | def connect_phase(self):
class BaseTest (line 704) | class BaseTest(uvm_test):
method __init__ (line 709) | def __init__(self, name, parent, env_class=BaseEnv):
method build_phase (line 718) | def build_phase(self):
method start_clock (line 721) | def start_clock(self, name):
method enter_debug_mode (line 727) | async def enter_debug_mode(self):
method do_reset (line 734) | async def do_reset(self):
method run_phase (line 740) | async def run_phase(self):
method run (line 869) | async def run(self):
FILE: verification/block/dec_ib/test_dec_ib.py
class TestIbCtlLogic (line 14) | class TestIbCtlLogic(BaseTest):
method end_of_elaboration_phase (line 15) | def end_of_elaboration_phase(self):
method run_phase (line 19) | async def run_phase(self):
method run (line 27) | async def run(self):
FILE: verification/block/dec_ib/testbench.py
function get_opcode (line 31) | def get_opcode(asm_line, ext="rv32i_zicsr", size=32):
class DebugCmdType (line 47) | class DebugCmdType(IntEnum):
class DebugCmd (line 54) | class DebugCmd:
class IbCtlInputItem (line 60) | class IbCtlInputItem(uvm_sequence_item):
method __init__ (line 61) | def __init__(self, debug_cmd, ifu_instr):
method debug_instr (line 68) | def debug_instr(self):
class IbCtlOutputItem (line 82) | class IbCtlOutputItem(uvm_sequence_item):
method __init__ (line 83) | def __init__(self, instr):
class IbCtlDriver (line 91) | class IbCtlDriver(uvm_driver):
method __init__ (line 92) | def __init__(self, *args, **kwargs):
method run_phase (line 97) | async def run_phase(self):
class IbCtlInputMonitor (line 113) | class IbCtlInputMonitor(uvm_component):
method __init__ (line 114) | def __init__(self, *args, **kwargs):
method build_phase (line 119) | def build_phase(self):
method run_phase (line 122) | async def run_phase(self):
class IbCtlOutputMonitor (line 137) | class IbCtlOutputMonitor(uvm_component):
method __init__ (line 142) | def __init__(self, *args, **kwargs):
method build_phase (line 147) | def build_phase(self):
method run_phase (line 150) | async def run_phase(self):
class IbCtlScoreboard (line 165) | class IbCtlScoreboard(uvm_component):
method __init__ (line 166) | def __init__(self, name, parent):
method build_phase (line 170) | def build_phase(self):
method connect_phase (line 176) | def connect_phase(self):
method check_phase (line 180) | def check_phase(self):
method final_phase (line 206) | def final_phase(self):
class IbCtlSequence (line 215) | class IbCtlSequence(uvm_sequence):
method __init__ (line 216) | def __init__(self, name, ops=None):
method body (line 219) | async def body(self):
class BaseEnv (line 246) | class BaseEnv(uvm_env):
method build_phase (line 251) | def build_phase(self):
method connect_phase (line 269) | def connect_phase(self):
class BaseTest (line 279) | class BaseTest(uvm_test):
method __init__ (line 284) | def __init__(self, name, parent, env_class=BaseEnv):
method build_phase (line 293) | def build_phase(self):
method start_clock (line 296) | def start_clock(self, name):
method do_reset (line 302) | async def do_reset(self):
method run_phase (line 308) | async def run_phase(self):
method run (line 328) | async def run(self):
FILE: verification/block/dec_pmp_ctl/test_dec_pmp_ctl.py
class CsrSequence (line 21) | class CsrSequence(uvm_sequence):
method __init__ (line 26) | def __init__(self, name):
method legalize_pmpcfg (line 53) | def legalize_pmpcfg(self, item):
method legalize_pmpaddr (line 62) | def legalize_pmpaddr(self, item):
method body (line 68) | async def body(self):
class PmpCfgLockSequence (line 76) | class PmpCfgLockSequence(uvm_sequence):
method __init__ (line 81) | def __init__(self, name):
method legalize_pmpcfg (line 98) | def legalize_pmpcfg(self, item):
method body (line 106) | async def body(self):
class TestCsrAccess (line 118) | class TestCsrAccess(BaseTest):
method end_of_elaboration_phase (line 119) | def end_of_elaboration_phase(self):
method run (line 124) | async def run(self):
class TestPmpCfgLock (line 131) | class TestPmpCfgLock(BaseTest):
method end_of_elaboration_phase (line 132) | def end_of_elaboration_phase(self):
method run (line 137) | async def run(self):
FILE: verification/block/dec_pmp_ctl/testbench.py
class InputItem (line 36) | class InputItem(uvm_sequence_item):
method __init__ (line 43) | def __init__(self, addr=0, data=0):
method randomize (line 49) | def randomize(self):
class CsrWriteDriver (line 60) | class CsrWriteDriver(uvm_driver):
method __init__ (line 65) | def __init__(self, *args, **kwargs):
method run_phase (line 70) | async def run_phase(self):
class CsrReadDriver (line 91) | class CsrReadDriver(uvm_driver):
method __init__ (line 96) | def __init__(self, *args, **kwargs):
method run_phase (line 101) | async def run_phase(self):
class WriteMonitor (line 124) | class WriteMonitor(uvm_component):
method __init__ (line 129) | def __init__(self, *args, **kwargs):
method build_phase (line 134) | def build_phase(self):
method run_phase (line 137) | async def run_phase(self):
class ReadMonitor (line 151) | class ReadMonitor(uvm_component):
method __init__ (line 156) | def __init__(self, *args, **kwargs):
method build_phase (line 161) | def build_phase(self):
method run_phase (line 164) | async def run_phase(self):
class Scoreboard (line 182) | class Scoreboard(uvm_component):
method __init__ (line 187) | def __init__(self, name, parent):
method build_phase (line 192) | def build_phase(self):
method connect_phase (line 198) | def connect_phase(self):
method check_phase (line 202) | def check_phase(self):
method final_phase (line 233) | def final_phase(self):
class BaseEnv (line 242) | class BaseEnv(uvm_env):
method build_phase (line 247) | def build_phase(self):
method connect_phase (line 267) | def connect_phase(self):
class BaseTest (line 278) | class BaseTest(uvm_test):
method __init__ (line 283) | def __init__(self, name, parent, env_class=BaseEnv):
method build_phase (line 292) | def build_phase(self):
method start_clock (line 295) | def start_clock(self, name):
method do_reset (line 301) | async def do_reset(self):
method run_phase (line 376) | async def run_phase(self):
method run (line 399) | async def run(self):
FILE: verification/block/dec_tl/test_dec_tl.py
class TestTriggerLogic (line 14) | class TestTriggerLogic(BaseTest):
method end_of_elaboration_phase (line 15) | def end_of_elaboration_phase(self):
method run_phase (line 19) | async def run_phase(self):
method run (line 27) | async def run(self):
FILE: verification/block/dec_tl/testbench.py
class TlInputItem (line 28) | class TlInputItem(uvm_sequence_item):
method __init__ (line 33) | def __init__(self, data=0, tdata=None, match=0):
method randomize (line 43) | def randomize(self):
method random_trigger (line 58) | def random_trigger(self, data, matching):
class TlOutputItem (line 97) | class TlOutputItem(uvm_sequence_item):
method __init__ (line 102) | def __init__(self, matches):
class TlDriver (line 111) | class TlDriver(uvm_driver):
method __init__ (line 116) | def __init__(self, *args, **kwargs):
method run_phase (line 121) | async def run_phase(self):
class TlInputMonitor (line 149) | class TlInputMonitor(uvm_component):
method __init__ (line 154) | def __init__(self, *args, **kwargs):
method build_phase (line 159) | def build_phase(self):
method run_phase (line 162) | async def run_phase(self):
class TlOutputMonitor (line 180) | class TlOutputMonitor(uvm_component):
method __init__ (line 185) | def __init__(self, *args, **kwargs):
method build_phase (line 190) | def build_phase(self):
method run_phase (line 193) | async def run_phase(self):
class TlScoreboard (line 208) | class TlScoreboard(uvm_component):
method __init__ (line 213) | def __init__(self, name, parent):
method build_phase (line 218) | def build_phase(self):
method connect_phase (line 224) | def connect_phase(self):
method check_phase (line 228) | def check_phase(self):
method final_phase (line 266) | def final_phase(self):
class TlSequence (line 275) | class TlSequence(uvm_sequence):
method __init__ (line 281) | def __init__(self, name, ops=None):
method body (line 284) | async def body(self):
class BaseEnv (line 298) | class BaseEnv(uvm_env):
method build_phase (line 303) | def build_phase(self):
method connect_phase (line 321) | def connect_phase(self):
class BaseTest (line 331) | class BaseTest(uvm_test):
method __init__ (line 336) | def __init__(self, name, parent, env_class=BaseEnv):
method build_phase (line 345) | def build_phase(self):
method start_clock (line 348) | def start_clock(self, name):
method do_reset (line 354) | async def do_reset(self):
method run_phase (line 360) | async def run_phase(self):
method run (line 380) | async def run(self):
FILE: verification/block/dec_tlu_ctl/common.py
class BaseSequence (line 7) | class BaseSequence(uvm_sequence):
method __init__ (line 10) | def __init__(self, name):
method accessAtAddr (line 18) | async def accessAtAddr(self, addr):
method randomAccessInAddrRange (line 27) | async def randomAccessInAddrRange(self, start_addr, end_addr):
method checkRangeBoundary (line 32) | async def checkRangeBoundary(self, addr):
FILE: verification/block/dec_tlu_ctl/test_dec_tl.py
class TestMeihap (line 14) | class TestMeihap(BaseTest):
method end_of_elaboration_phase (line 15) | def end_of_elaboration_phase(self):
method run (line 20) | async def run(self):
class TestMtdata (line 25) | class TestMtdata(BaseTest):
method end_of_elaboration_phase (line 26) | def end_of_elaboration_phase(self):
method run (line 31) | async def run(self):
class TestMhpme (line 36) | class TestMhpme(BaseTest):
method end_of_elaboration_phase (line 37) | def end_of_elaboration_phase(self):
method run (line 42) | async def run(self):
class TestMdseac (line 47) | class TestMdseac(BaseTest):
method end_of_elaboration_phase (line 48) | def end_of_elaboration_phase(self):
method run (line 53) | async def run(self):
class TestCsrAccess (line 58) | class TestCsrAccess(BaseTest):
method end_of_elaboration_phase (line 59) | def end_of_elaboration_phase(self):
method run (line 64) | async def run(self):
class TestDebugCSRs (line 69) | class TestDebugCSRs(BaseTest):
method end_of_elaboration_phase (line 70) | def end_of_elaboration_phase(self):
method run (line 75) | async def run(self):
class TestDebugICCache (line 80) | class TestDebugICCache(BaseTest):
method end_of_elaboration_phase (line 81) | def end_of_elaboration_phase(self):
method run (line 86) | async def run(self):
FILE: verification/block/dec_tlu_ctl/testbench.py
class TriggerAnyPktT (line 33) | class TriggerAnyPktT:
method get_from_dut (line 43) | def get_from_dut(dut):
class TlInputItem (line 62) | class TlInputItem(uvm_sequence_item):
method __init__ (line 67) | def __init__(
method randomize (line 94) | def randomize(self, test):
class TlOutputItem (line 200) | class TlOutputItem(uvm_sequence_item):
method __init__ (line 205) | def __init__(
class TlDriver (line 228) | class TlDriver(uvm_driver):
method __init__ (line 233) | def __init__(self, *args, **kwargs):
method read_csr (line 238) | async def read_csr(self, address):
method write_csr (line 242) | async def write_csr(self, address, value):
method do_reset (line 251) | async def do_reset(self):
method run_phase (line 257) | async def run_phase(self):
class TlInputMonitor (line 327) | class TlInputMonitor(uvm_component):
method __init__ (line 332) | def __init__(self, *args, **kwargs):
method build_phase (line 337) | def build_phase(self):
method run_phase (line 340) | async def run_phase(self):
class TlOutputMonitor (line 402) | class TlOutputMonitor(uvm_component):
method __init__ (line 407) | def __init__(self, *args, **kwargs):
method build_phase (line 412) | def build_phase(self):
method run_phase (line 415) | async def run_phase(self):
class TlScoreboard (line 483) | class TlScoreboard(uvm_component):
method __init__ (line 488) | def __init__(self, name, parent):
method build_phase (line 493) | def build_phase(self):
method connect_phase (line 499) | def connect_phase(self):
method check_phase (line 503) | def check_phase(self): # noqa: C901
method final_phase (line 687) | def final_phase(self):
class TlSequence (line 696) | class TlSequence(uvm_sequence):
method __init__ (line 698) | def __init__(self, name, ops=None):
method body (line 701) | async def body(self):
class BaseEnv (line 716) | class BaseEnv(uvm_env):
method build_phase (line 721) | def build_phase(self):
method connect_phase (line 739) | def connect_phase(self):
class BaseTest (line 749) | class BaseTest(uvm_test):
method __init__ (line 754) | def __init__(self, name, parent, env_class=BaseEnv):
method build_phase (line 763) | def build_phase(self):
method start_clock (line 766) | def start_clock(self, name):
method do_reset (line 772) | async def do_reset(self):
method run_phase (line 778) | async def run_phase(self):
method run (line 880) | async def run(self):
FILE: verification/block/dma/scoreboards.py
class ReadScoreboard (line 20) | class ReadScoreboard(uvm_component):
method __init__ (line 26) | def __init__(self, name, parent):
method build_phase (line 37) | def build_phase(self):
method connect_phase (line 41) | def connect_phase(self):
method is_iccm (line 44) | def is_iccm(self, addr):
method is_dccm (line 47) | def is_dccm(self, addr):
method check_phase (line 50) | def check_phase(self):
method final_phase (line 140) | def final_phase(self):
class WriteScoreboard (line 149) | class WriteScoreboard(uvm_component):
method __init__ (line 155) | def __init__(self, name, parent):
method build_phase (line 166) | def build_phase(self):
method connect_phase (line 170) | def connect_phase(self):
method is_iccm (line 173) | def is_iccm(self, addr):
method is_dccm (line 176) | def is_dccm(self, addr):
method check_phase (line 179) | def check_phase(self):
method final_phase (line 275) | def final_phase(self):
class AccessScoreboard (line 284) | class AccessScoreboard(uvm_component):
method __init__ (line 290) | def __init__(self, name, parent):
method build_phase (line 295) | def build_phase(self):
method connect_phase (line 299) | def connect_phase(self):
method check_phase (line 302) | def check_phase(self):
method final_phase (line 338) | def final_phase(self):
FILE: verification/block/dma/sequences.py
class MemWriteSequence (line 15) | class MemWriteSequence(uvm_sequence):
method __init__ (line 20) | def __init__(self, name, mem, dwidth=32):
method body (line 25) | async def body(self):
class AnyMemWriteSequence (line 57) | class AnyMemWriteSequence(uvm_sequence):
method __init__ (line 62) | def __init__(self, name, dwidth=32):
method body (line 66) | async def body(self):
class MemReadSequence (line 111) | class MemReadSequence(uvm_sequence):
method __init__ (line 116) | def __init__(self, name, mem):
method body (line 120) | async def body(self):
class AnyMemReadSequence (line 142) | class AnyMemReadSequence(uvm_sequence):
method __init__ (line 147) | def __init__(self, name):
method body (line 150) | async def body(self):
class InvalidAddressSequence (line 185) | class InvalidAddressSequence(uvm_sequence):
method __init__ (line 191) | def __init__(self, name, dwidth=32):
method body (line 195) | async def body(self):
FILE: verification/block/dma/test_address.py
class TestEnv (line 12) | class TestEnv(BaseEnv):
method build_phase (line 13) | def build_phase(self):
method connect_phase (line 19) | def connect_phase(self):
class TestAddressOutOfRange (line 31) | class TestAddressOutOfRange(BaseTest):
method __init__ (line 36) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 39) | def end_of_elaboration_phase(self):
method run (line 43) | async def run(self):
FILE: verification/block/dma/test_debug_address.py
class TestEnv (line 12) | class TestEnv(BaseEnv):
method build_phase (line 13) | def build_phase(self):
method connect_phase (line 19) | def connect_phase(self):
class TestAddressOutOfRange (line 31) | class TestAddressOutOfRange(BaseTest):
method __init__ (line 36) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 39) | def end_of_elaboration_phase(self):
method run (line 43) | async def run(self):
FILE: verification/block/dma/test_debug_read.py
class TestEnv (line 13) | class TestEnv(BaseEnv):
method build_phase (line 14) | def build_phase(self):
method connect_phase (line 20) | def connect_phase(self):
class TestDCCMRead (line 32) | class TestDCCMRead(BaseTest):
method __init__ (line 37) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 40) | def end_of_elaboration_phase(self):
method run (line 44) | async def run(self):
class TestICCMRead (line 49) | class TestICCMRead(BaseTest):
method __init__ (line 54) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 57) | def end_of_elaboration_phase(self):
method run (line 61) | async def run(self):
class TestBothRead (line 66) | class TestBothRead(BaseTest):
method __init__ (line 71) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 74) | def end_of_elaboration_phase(self):
method run (line 78) | async def run(self):
FILE: verification/block/dma/test_debug_write.py
class TestEnv (line 12) | class TestEnv(BaseEnv):
method build_phase (line 13) | def build_phase(self):
method connect_phase (line 19) | def connect_phase(self):
class TestDCCMWrite (line 31) | class TestDCCMWrite(BaseTest):
method __init__ (line 36) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 39) | def end_of_elaboration_phase(self):
method run (line 43) | async def run(self):
class TestICCMWrite (line 48) | class TestICCMWrite(BaseTest):
method __init__ (line 53) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 56) | def end_of_elaboration_phase(self):
method run (line 60) | async def run(self):
class TestBothWrite (line 65) | class TestBothWrite(BaseTest):
method __init__ (line 70) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 73) | def end_of_elaboration_phase(self):
method run (line 77) | async def run(self):
FILE: verification/block/dma/test_ecc.py
class Scoreboard (line 14) | class Scoreboard(uvm_component):
method __init__ (line 17) | def __init__(self, name, parent):
method build_phase (line 28) | def build_phase(self):
method connect_phase (line 32) | def connect_phase(self):
method is_iccm (line 35) | def is_iccm(self, addr):
method is_dccm (line 38) | def is_dccm(self, addr):
method check_phase (line 41) | def check_phase(self):
method final_phase (line 116) | def final_phase(self):
class TestEnv (line 125) | class TestEnv(BaseEnv):
method build_phase (line 126) | def build_phase(self):
method connect_phase (line 135) | def connect_phase(self):
class TestEccError (line 147) | class TestEccError(BaseTest):
method __init__ (line 152) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 155) | def end_of_elaboration_phase(self):
method run (line 159) | async def run(self):
FILE: verification/block/dma/test_read.py
class TestEnv (line 12) | class TestEnv(BaseEnv):
method build_phase (line 13) | def build_phase(self):
method connect_phase (line 19) | def connect_phase(self):
class TestDCCMRead (line 31) | class TestDCCMRead(BaseTest):
method __init__ (line 36) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 39) | def end_of_elaboration_phase(self):
method run (line 43) | async def run(self):
class TestICCMRead (line 48) | class TestICCMRead(BaseTest):
method __init__ (line 53) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 56) | def end_of_elaboration_phase(self):
method run (line 60) | async def run(self):
class TestBothRead (line 65) | class TestBothRead(BaseTest):
method __init__ (line 70) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 73) | def end_of_elaboration_phase(self):
method run (line 77) | async def run(self):
FILE: verification/block/dma/test_reset.py
class TestReset (line 12) | class TestReset(BaseTest):
method run (line 17) | async def run(self):
FILE: verification/block/dma/test_write.py
class TestEnv (line 12) | class TestEnv(BaseEnv):
method build_phase (line 13) | def build_phase(self):
method connect_phase (line 19) | def connect_phase(self):
class TestDCCMWrite (line 31) | class TestDCCMWrite(BaseTest):
method __init__ (line 36) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 39) | def end_of_elaboration_phase(self):
method run (line 43) | async def run(self):
class TestICCMWrite (line 48) | class TestICCMWrite(BaseTest):
method __init__ (line 53) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 56) | def end_of_elaboration_phase(self):
method run (line 60) | async def run(self):
class TestBothWrite (line 65) | class TestBothWrite(BaseTest):
method __init__ (line 70) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 73) | def end_of_elaboration_phase(self):
method run (line 77) | async def run(self):
FILE: verification/block/dma/testbench.py
class MemWriteItem (line 30) | class MemWriteItem(uvm_sequence_item):
method __init__ (line 35) | def __init__(self, mem, addr, data, size=64, resp=None):
class MemReadItem (line 44) | class MemReadItem(uvm_sequence_item):
method __init__ (line 49) | def __init__(self, mem, addr, data, size=64, resp=None):
class DebugWriteItem (line 58) | class DebugWriteItem(uvm_sequence_item):
method __init__ (line 63) | def __init__(self, addr, data, size=32, fail=False):
class DebugReadItem (line 71) | class DebugReadItem(uvm_sequence_item):
method __init__ (line 76) | def __init__(self, addr, data=None, size=32, fail=False):
class CoreMemoryBFM (line 87) | class CoreMemoryBFM(uvm_component):
method __init__ (line 113) | def __init__(self, name, parent, uut):
method build_phase (line 123) | def build_phase(self):
method iccm_busy_task (line 142) | async def iccm_busy_task(self):
method dccm_busy_task (line 159) | async def dccm_busy_task(self):
method responder (line 176) | async def responder(self):
method run_phase (line 231) | async def run_phase(self):
class CoreMemoryMonitor (line 242) | class CoreMemoryMonitor(uvm_component):
method __init__ (line 247) | def __init__(self, *args, **kwargs):
method build_phase (line 256) | def build_phase(self):
method run_phase (line 259) | async def run_phase(self):
class Axi4LiteBFM (line 317) | class Axi4LiteBFM(uvm_component):
class Transfer (line 354) | class Transfer:
method __init__ (line 359) | def __init__(self, tid):
method __init__ (line 366) | def __init__(self, name, parent, uut, signal_map):
method build_phase (line 390) | def build_phase(self):
method _wait (line 393) | async def _wait(self, signal, max_cycles=200):
method write (line 405) | async def write(self, addr, data):
method write_handler (line 463) | async def write_handler(self):
method read (line 495) | async def read(self, addr, data):
method run_phase (line 532) | async def run_phase(self):
class Axi4LiteSubordinateDriver (line 540) | class Axi4LiteSubordinateDriver(uvm_driver):
method __init__ (line 545) | def __init__(self, *args, **kwargs):
method run_phase (line 550) | async def run_phase(self):
class DebugInterfaceBFM (line 570) | class DebugInterfaceBFM(uvm_component):
method __init__ (line 590) | def __init__(self, name, parent, uut):
method build_phase (line 596) | def build_phase(self):
method _wait (line 604) | async def _wait(self, signal, max_cycles=150):
method write (line 616) | async def write(self, addr, data):
method read (line 644) | async def read(self, addr):
method run_phase (line 671) | async def run_phase(self):
class DebugInterfaceDriver (line 700) | class DebugInterfaceDriver(uvm_driver):
method __init__ (line 705) | def __init__(self, *args, **kwargs):
method run_phase (line 710) | async def run_phase(self):
class DebugInterfaceMonitor (line 725) | class DebugInterfaceMonitor(uvm_component):
method __init__ (line 730) | def __init__(self, *args, **kwargs):
method build_phase (line 735) | def build_phase(self):
method run_phase (line 738) | async def run_phase(self):
class BaseEnv (line 810) | class BaseEnv(uvm_env):
method build_phase (line 815) | def build_phase(self):
method connect_phase (line 912) | def connect_phase(self):
class BaseTest (line 920) | class BaseTest(uvm_test):
method __init__ (line 925) | def __init__(self, name, parent, env_class=BaseEnv):
method build_phase (line 934) | def build_phase(self):
method start_clock (line 937) | def start_clock(self, name):
method do_reset (line 943) | async def do_reset(self):
method run_phase (line 985) | async def run_phase(self):
method run (line 1010) | async def run(self):
FILE: verification/block/dmi/common.py
class BaseSeq (line 11) | class BaseSeq(uvm_sequence):
method run_items (line 12) | async def run_items(self, items):
class Defaults (line 19) | class Defaults:
function collect_signals (line 33) | def collect_signals(signals, uut, obj):
function get_int (line 49) | def get_int(signal):
FILE: verification/block/dmi/dmi_agent.py
class DMIAgent (line 7) | class DMIAgent(uvm_agent):
method build_phase (line 13) | def build_phase(self):
method connect_phase (line 20) | def connect_phase(self):
class DMIDriver (line 24) | class DMIDriver(uvm_driver):
method build_phase (line 25) | def build_phase(self):
method start_of_simulation_phase (line 28) | def start_of_simulation_phase(self):
method run_phase (line 31) | async def run_phase(self):
class DMIMonitor (line 40) | class DMIMonitor(uvm_component):
method __init__ (line 41) | def __init__(self, name, parent, method_name):
method build_phase (line 45) | def build_phase(self):
method run_phase (line 50) | async def run_phase(self):
FILE: verification/block/dmi/dmi_bfm.py
class MemoryModel (line 13) | class MemoryModel:
method __init__ (line 14) | def __init__(self):
method write (line 18) | def write(self, addr, data):
method read (line 21) | def read(self, addr):
method reset (line 24) | def reset(self):
class DMITestBfm (line 32) | class DMITestBfm(metaclass=utility_classes.Singleton):
method __init__ (line 59) | def __init__(self):
method req_driver_q_put (line 73) | async def req_driver_q_put(self, item):
method rsp_monitor_q_get (line 76) | async def rsp_monitor_q_get(self):
method driver_bfm (line 80) | async def driver_bfm(self):
method rsp_monitor_q_bfm (line 101) | async def rsp_monitor_q_bfm(self):
method start_bfm (line 151) | def start_bfm(self):
FILE: verification/block/dmi/dmi_seq.py
class SetUncoreEnableSeqItem (line 11) | class SetUncoreEnableSeqItem(uvm_sequence_item):
method __init__ (line 12) | def __init__(self, name, uncore_enable):
method __str__ (line 16) | def __str__(self):
method randomize (line 19) | def randomize(self):
class SetUncoreEnableSequence (line 23) | class SetUncoreEnableSequence(BaseSeq):
method __init__ (line 24) | def __init__(self, name, value):
method body (line 29) | async def body(self):
class AccessDMIRegSequence (line 34) | class AccessDMIRegSequence(BaseSeq):
method __init__ (line 35) | def __init__(self, name, addr, data=0x0, is_write=False):
method body (line 44) | async def body(self):
FILE: verification/block/dmi/jtag_agent.py
class JTAGAgent (line 7) | class JTAGAgent(uvm_agent):
method build_phase (line 13) | def build_phase(self):
method connect_phase (line 20) | def connect_phase(self):
class JTAGDriver (line 24) | class JTAGDriver(uvm_driver):
method build_phase (line 25) | def build_phase(self):
method start_of_simulation_phase (line 28) | def start_of_simulation_phase(self):
method run_phase (line 31) | async def run_phase(self):
class JTAGMonitor (line 41) | class JTAGMonitor(uvm_component):
method __init__ (line 42) | def __init__(self, name, parent, method_name):
method build_phase (line 46) | def build_phase(self):
method run_phase (line 51) | async def run_phase(self):
FILE: verification/block/dmi/jtag_bfm.py
class MemoryModel (line 15) | class MemoryModel:
method __init__ (line 16) | def __init__(self):
method write (line 19) | def write(self, addr, data):
method read (line 22) | def read(self, addr):
method reset (line 26) | def reset(self):
class JTAGBfm (line 30) | class JTAGBfm(metaclass=utility_classes.Singleton):
method __init__ (line 46) | def __init__(self):
method req_driver_q_put (line 56) | async def req_driver_q_put(self, tms, tdi):
method rsp_monitor_q_get (line 60) | async def rsp_monitor_q_get(self):
method reset (line 64) | async def reset(self):
method driver_bfm (line 74) | async def driver_bfm(self):
method req_monitor_q_bfm (line 87) | async def req_monitor_q_bfm(self):
method rsp_monitor_q_bfm (line 96) | async def rsp_monitor_q_bfm(self):
method start_bfm (line 119) | def start_bfm(self):
FILE: verification/block/dmi/jtag_pkg.py
class JTAGDefaults (line 6) | class JTAGDefaults:
class JTAGInstructions (line 13) | class JTAGInstructions:
class JTAGStates (line 19) | class JTAGStates(IntEnum):
FILE: verification/block/dmi/jtag_predictor.py
class JTAGPredictor (line 12) | class JTAGPredictor:
method __init__ (line 18) | def __init__(self, dut):
method __str__ (line 53) | def __str__(self):
method update_state (line 76) | def update_state(self):
method update_nstate (line 86) | def update_nstate(self):
method predict_regs_posedge (line 199) | def predict_regs_posedge(self):
method predict_nsr_reg (line 227) | def predict_nsr_reg(self):
method predict_regs_negedge (line 278) | def predict_regs_negedge(self):
method predict_ports (line 287) | def predict_ports(self):
method predict_jtag_outputs (line 310) | def predict_jtag_outputs(self, edge):
FILE: verification/block/dmi/jtag_seq.py
class JTAGBaseSeqItem (line 10) | class JTAGBaseSeqItem(uvm_sequence_item):
method __init__ (line 11) | def __init__(self, name, tms=1, tdi=0):
method __str__ (line 17) | def __str__(self):
method randomize (line 20) | def randomize(self):
class SetIRSequence (line 24) | class SetIRSequence(BaseSeq):
method __init__ (line 25) | def __init__(self, name, instruction):
method body (line 29) | async def body(self):
class ReadIDCODESequence (line 48) | class ReadIDCODESequence(SetIRSequence):
method __init__ (line 49) | def __init__(self, name):
class CaptureDRSequence (line 53) | class CaptureDRSequence(BaseSeq):
method __init__ (line 54) | def __init__(self, name):
method body (line 57) | async def body(self):
FILE: verification/block/dmi/test_dmi_read_write.py
class TestDMIReadRegs (line 11) | class TestDMIReadRegs(BaseTest):
method end_of_elaboration_phase (line 12) | def end_of_elaboration_phase(self):
method run (line 19) | async def run(self):
class TestDMIWriteRegs (line 27) | class TestDMIWriteRegs(BaseTest):
method end_of_elaboration_phase (line 28) | def end_of_elaboration_phase(self):
method run (line 38) | async def run(self):
class TestDMIReadWriteRegs (line 45) | class TestDMIReadWriteRegs(BaseTest):
method end_of_elaboration_phase (line 46) | def end_of_elaboration_phase(self):
method run (line 58) | async def run(self):
class TestUncoreDMIReadWriteRegs (line 67) | class TestUncoreDMIReadWriteRegs(BaseTest):
method end_of_elaboration_phase (line 68) | def end_of_elaboration_phase(self):
method run (line 90) | async def run(self):
FILE: verification/block/dmi/test_dmi_tap_fsm.py
function test_full_tap_fsm (line 117) | async def test_full_tap_fsm(dut):
FILE: verification/block/dmi/test_jtag_ir.py
class TestJTAGSetIR (line 11) | class TestJTAGSetIR(BaseTest):
method end_of_elaboration_phase (line 12) | def end_of_elaboration_phase(self):
method run (line 16) | async def run(self):
class TestJTAGReadIDCODE (line 21) | class TestJTAGReadIDCODE(BaseTest):
method end_of_elaboration_phase (line 22) | def end_of_elaboration_phase(self):
method run (line 26) | async def run(self):
class TestJTAGSetIRReadDR (line 31) | class TestJTAGSetIRReadDR(BaseTest):
method end_of_elaboration_phase (line 32) | def end_of_elaboration_phase(self):
method run (line 37) | async def run(self):
FILE: verification/block/dmi/testbench.py
class Scoreboard (line 17) | class Scoreboard(uvm_scoreboard):
method build_phase (line 18) | def build_phase(self):
method connect_phase (line 27) | def connect_phase(self):
method check_phase (line 31) | def check_phase(self):
method check_dmi (line 36) | def check_dmi(self):
method check_jtag (line 59) | def check_jtag(self):
class BaseEnvironment (line 81) | class BaseEnvironment(uvm_env):
method __init__ (line 82) | def __init__(self, name, test_obj):
method build_phase (line 85) | def build_phase(self):
method connect_phase (line 99) | def connect_phase(self):
class BaseTest (line 107) | class BaseTest(uvm_test):
method __init__ (line 112) | def __init__(self, name, parent):
method build_phase (line 119) | def build_phase(self):
method start_clock (line 122) | def start_clock(self, name, period):
method do_reset (line 127) | async def do_reset(self, signals, timeLength="100e-9", isActiveHigh=Tr...
method run_phase (line 140) | async def run_phase(self):
method run (line 162) | async def run(self):
FILE: verification/block/exu_alu/test_arith.py
class TestAdd (line 14) | class TestAdd(BaseTest):
method end_of_elaboration_phase (line 15) | def end_of_elaboration_phase(self):
method run (line 19) | async def run(self):
class TestSub (line 24) | class TestSub(BaseTest):
method end_of_elaboration_phase (line 25) | def end_of_elaboration_phase(self):
method run (line 29) | async def run(self):
class TestAll (line 34) | class TestAll(BaseTest):
method end_of_elaboration_phase (line 35) | def end_of_elaboration_phase(self):
method run (line 39) | async def run(self):
FILE: verification/block/exu_alu/test_logic.py
class TestAnd (line 14) | class TestAnd(BaseTest):
method end_of_elaboration_phase (line 15) | def end_of_elaboration_phase(self):
method run (line 19) | async def run(self):
class TestOr (line 24) | class TestOr(BaseTest):
method end_of_elaboration_phase (line 25) | def end_of_elaboration_phase(self):
method run (line 29) | async def run(self):
class TestXor (line 34) | class TestXor(BaseTest):
method end_of_elaboration_phase (line 35) | def end_of_elaboration_phase(self):
method run (line 39) | async def run(self):
class TestAll (line 44) | class TestAll(BaseTest):
method end_of_elaboration_phase (line 45) | def end_of_elaboration_phase(self):
method run (line 49) | async def run(self):
FILE: verification/block/exu_alu/test_zba.py
class TestSh1add (line 14) | class TestSh1add(BaseTest):
method end_of_elaboration_phase (line 15) | def end_of_elaboration_phase(self):
method run (line 19) | async def run(self):
class TestSh2add (line 24) | class TestSh2add(BaseTest):
method end_of_elaboration_phase (line 25) | def end_of_elaboration_phase(self):
method run (line 29) | async def run(self):
class TestSh3add (line 34) | class TestSh3add(BaseTest):
method end_of_elaboration_phase (line 35) | def end_of_elaboration_phase(self):
method run (line 39) | async def run(self):
class TestAll (line 44) | class TestAll(BaseTest):
method end_of_elaboration_phase (line 45) | def end_of_elaboration_phase(self):
method run (line 49) | async def run(self):
FILE: verification/block/exu_alu/test_zbb.py
class TestClz (line 14) | class TestClz(BaseTest):
method end_of_elaboration_phase (line 15) | def end_of_elaboration_phase(self):
method run (line 19) | async def run(self):
class TestCtz (line 24) | class TestCtz(BaseTest):
method end_of_elaboration_phase (line 25) | def end_of_elaboration_phase(self):
method run (line 29) | async def run(self):
class TestCpop (line 34) | class TestCpop(BaseTest):
method end_of_elaboration_phase (line 35) | def end_of_elaboration_phase(self):
method run (line 39) | async def run(self):
class TestSextb (line 44) | class TestSextb(BaseTest):
method end_of_elaboration_phase (line 45) | def end_of_elaboration_phase(self):
method run (line 49) | async def run(self):
class TestSexth (line 54) | class TestSexth(BaseTest):
method end_of_elaboration_phase (line 55) | def end_of_elaboration_phase(self):
method run (line 59) | async def run(self):
class TestRol (line 64) | class TestRol(BaseTest):
method end_of_elaboration_phase (line 65) | def end_of_elaboration_phase(self):
method run (line 69) | async def run(self):
class TestRor (line 74) | class TestRor(BaseTest):
method end_of_elaboration_phase (line 75) | def end_of_elaboration_phase(self):
method run (line 79) | async def run(self):
class TestAll (line 84) | class TestAll(BaseTest):
method end_of_elaboration_phase (line 85) | def end_of_elaboration_phase(self):
method run (line 91) | async def run(self):
FILE: verification/block/exu_alu/test_zbp.py
class TestPack (line 14) | class TestPack(BaseTest):
method end_of_elaboration_phase (line 15) | def end_of_elaboration_phase(self):
method run (line 19) | async def run(self):
class TestPackh (line 24) | class TestPackh(BaseTest):
method end_of_elaboration_phase (line 25) | def end_of_elaboration_phase(self):
method run (line 29) | async def run(self):
class TestAll (line 34) | class TestAll(BaseTest):
method end_of_elaboration_phase (line 35) | def end_of_elaboration_phase(self):
method run (line 39) | async def run(self):
FILE: verification/block/exu_alu/test_zbs.py
class TestBset (line 14) | class TestBset(BaseTest):
method end_of_elaboration_phase (line 15) | def end_of_elaboration_phase(self):
method run (line 19) | async def run(self):
class TestBclr (line 24) | class TestBclr(BaseTest):
method end_of_elaboration_phase (line 25) | def end_of_elaboration_phase(self):
method run (line 29) | async def run(self):
class TestBinv (line 34) | class TestBinv(BaseTest):
method end_of_elaboration_phase (line 35) | def end_of_elaboration_phase(self):
method run (line 39) | async def run(self):
class TestBext (line 44) | class TestBext(BaseTest):
method end_of_elaboration_phase (line 45) | def end_of_elaboration_phase(self):
method run (line 49) | async def run(self):
class TestAll (line 54) | class TestAll(BaseTest):
method end_of_elaboration_phase (line 55) | def end_of_elaboration_phase(self):
method run (line 59) | async def run(self):
FILE: verification/block/exu_alu/testbench.py
class AluInputItem (line 25) | class AluInputItem(uvm_sequence_item):
method __init__ (line 30) | def __init__(self, op, a, b, csr=0, pc=0):
class AluOutputItem (line 39) | class AluOutputItem(uvm_sequence_item):
method __init__ (line 44) | def __init__(self, out):
class AluDriver (line 52) | class AluDriver(uvm_driver):
method __init__ (line 57) | def __init__(self, *args, **kwargs):
method run_phase (line 62) | async def run_phase(self):
class AluInputMonitor (line 120) | class AluInputMonitor(uvm_component):
method __init__ (line 125) | def __init__(self, *args, **kwargs):
method build_phase (line 130) | def build_phase(self):
method run_phase (line 133) | async def run_phase(self):
class AluOutputMonitor (line 199) | class AluOutputMonitor(uvm_component):
method __init__ (line 204) | def __init__(self, *args, **kwargs):
method build_phase (line 209) | def build_phase(self):
method run_phase (line 212) | async def run_phase(self):
class AluScoreboard (line 230) | class AluScoreboard(uvm_component):
method __init__ (line 235) | def __init__(self, name, parent):
method build_phase (line 240) | def build_phase(self):
method connect_phase (line 246) | def connect_phase(self):
method check_phase (line 250) | def check_phase(self):
method final_phase (line 344) | def final_phase(self):
class BaseSequence (line 353) | class BaseSequence(uvm_sequence):
method __init__ (line 359) | def __init__(self, name, ops=None):
method body (line 367) | async def body(self):
class BaseEnv (line 384) | class BaseEnv(uvm_env):
method build_phase (line 389) | def build_phase(self):
method connect_phase (line 407) | def connect_phase(self):
class BaseTest (line 417) | class BaseTest(uvm_test):
method __init__ (line 422) | def __init__(self, name, parent, env_class=BaseEnv):
method build_phase (line 431) | def build_phase(self):
method start_clock (line 434) | def start_clock(self, name):
method do_reset (line 440) | async def do_reset(self):
method run_phase (line 502) | async def run_phase(self):
method run (line 525) | async def run(self):
FILE: verification/block/exu_div/test_div.py
class TestDiv (line 14) | class TestDiv(BaseTest):
method end_of_elaboration_phase (line 15) | def end_of_elaboration_phase(self):
method run (line 19) | async def run(self):
class TestRem (line 24) | class TestRem(BaseTest):
method end_of_elaboration_phase (line 25) | def end_of_elaboration_phase(self):
method run (line 29) | async def run(self):
class TestAll (line 34) | class TestAll(BaseTest):
method end_of_elaboration_phase (line 35) | def end_of_elaboration_phase(self):
method run (line 39) | async def run(self):
FILE: verification/block/exu_div/testbench.py
class DivInputItem (line 25) | class DivInputItem(uvm_sequence_item):
method __init__ (line 30) | def __init__(self, op, num, den, unsign=1):
class DivOutputItem (line 38) | class DivOutputItem(uvm_sequence_item):
method __init__ (line 43) | def __init__(self, out):
class DivDriver (line 51) | class DivDriver(uvm_driver):
method __init__ (line 56) | def __init__(self, *args, **kwargs):
method run_phase (line 61) | async def run_phase(self):
class DivInputMonitor (line 90) | class DivInputMonitor(uvm_component):
method __init__ (line 95) | def __init__(self, *args, **kwargs):
method build_phase (line 100) | def build_phase(self):
method run_phase (line 103) | async def run_phase(self):
class DivOutputMonitor (line 122) | class DivOutputMonitor(uvm_component):
method __init__ (line 127) | def __init__(self, *args, **kwargs):
method build_phase (line 132) | def build_phase(self):
method run_phase (line 135) | async def run_phase(self):
class DivScoreboard (line 150) | class DivScoreboard(uvm_component):
method __init__ (line 155) | def __init__(self, name, parent):
method build_phase (line 160) | def build_phase(self):
method connect_phase (line 166) | def connect_phase(self):
method check_phase (line 170) | def check_phase(self):
method final_phase (line 219) | def final_phase(self):
class BaseSequence (line 228) | class BaseSequence(uvm_sequence):
method __init__ (line 234) | def __init__(self, name, ops=None):
method body (line 242) | async def body(self):
class BaseEnv (line 259) | class BaseEnv(uvm_env):
method build_phase (line 264) | def build_phase(self):
method connect_phase (line 282) | def connect_phase(self):
class BaseTest (line 292) | class BaseTest(uvm_test):
method __init__ (line 297) | def __init__(self, name, parent, env_class=BaseEnv):
method build_phase (line 306) | def build_phase(self):
method start_clock (line 309) | def start_clock(self, name):
method do_reset (line 315) | async def do_reset(self):
method run_phase (line 330) | async def run_phase(self):
method run (line 350) | async def run(self):
FILE: verification/block/exu_mul/test_mul.py
class TestMul (line 14) | class TestMul(BaseTest):
method end_of_elaboration_phase (line 15) | def end_of_elaboration_phase(self):
method run (line 19) | async def run(self):
FILE: verification/block/exu_mul/testbench.py
class MulInputItem (line 25) | class MulInputItem(uvm_sequence_item):
method __init__ (line 30) | def __init__(self, op, a, b, low=0):
class MulOutputItem (line 38) | class MulOutputItem(uvm_sequence_item):
method __init__ (line 43) | def __init__(self, out):
class MulDriver (line 51) | class MulDriver(uvm_driver):
method __init__ (line 56) | def __init__(self, *args, **kwargs):
method run_phase (line 61) | async def run_phase(self):
class MulInputMonitor (line 89) | class MulInputMonitor(uvm_component):
method __init__ (line 94) | def __init__(self, *args, **kwargs):
method build_phase (line 99) | def build_phase(self):
method run_phase (line 102) | async def run_phase(self):
class MulOutputMonitor (line 128) | class MulOutputMonitor(uvm_component):
method __init__ (line 133) | def __init__(self, *args, **kwargs):
method build_phase (line 138) | def build_phase(self):
method run_phase (line 141) | async def run_phase(self):
class MulScoreboard (line 159) | class MulScoreboard(uvm_component):
method __init__ (line 164) | def __init__(self, name, parent):
method build_phase (line 169) | def build_phase(self):
method connect_phase (line 175) | def connect_phase(self):
method check_phase (line 179) | def check_phase(self):
method final_phase (line 224) | def final_phase(self):
class BaseSequence (line 233) | class BaseSequence(uvm_sequence):
method __init__ (line 239) | def __init__(self, name, ops=None):
method body (line 247) | async def body(self):
class BaseEnv (line 267) | class BaseEnv(uvm_env):
method build_phase (line 272) | def build_phase(self):
method connect_phase (line 290) | def connect_phase(self):
class BaseTest (line 300) | class BaseTest(uvm_test):
method __init__ (line 305) | def __init__(self, name, parent, env_class=BaseEnv):
method build_phase (line 314) | def build_phase(self):
method start_clock (line 317) | def start_clock(self, name):
method do_reset (line 323) | async def do_reset(self):
method run_phase (line 357) | async def run_phase(self):
method run (line 377) | async def run(self):
FILE: verification/block/iccm/test_readwrite.py
class ReadWriteSequence (line 12) | class ReadWriteSequence(uvm_sequence):
method __init__ (line 19) | def __init__(self, name):
method body (line 22) | async def body(self):
class TestReadWrite (line 53) | class TestReadWrite(BaseTest):
method end_of_elaboration_phase (line 54) | def end_of_elaboration_phase(self):
method run (line 58) | async def run(self):
FILE: verification/block/iccm/testbench.py
class MemWriteItem (line 13) | class MemWriteItem(uvm_sequence_item):
method __init__ (line 18) | def __init__(self, addr, data):
class MemReadItem (line 24) | class MemReadItem(uvm_sequence_item):
method __init__ (line 29) | def __init__(self, addr, data=None):
class MemDriver (line 38) | class MemDriver(uvm_driver):
method __init__ (line 43) | def __init__(self, *args, **kwargs):
method run_phase (line 48) | async def run_phase(self):
class MemMonitor (line 84) | class MemMonitor(uvm_component):
method __init__ (line 89) | def __init__(self, *args, **kwargs):
method build_phase (line 94) | def build_phase(self):
method run_phase (line 97) | async def run_phase(self):
class Scoreboard (line 126) | class Scoreboard(uvm_component):
method __init__ (line 132) | def __init__(self, name, parent):
method build_phase (line 136) | def build_phase(self):
method connect_phase (line 140) | def connect_phase(self):
method check_phase (line 143) | def check_phase(self):
method final_phase (line 194) | def final_phase(self):
class BaseEnv (line 203) | class BaseEnv(uvm_env):
method build_phase (line 208) | def build_phase(self):
method connect_phase (line 228) | def connect_phase(self):
class BaseTest (line 236) | class BaseTest(uvm_test):
method __init__ (line 241) | def __init__(self, name, parent, env_class=BaseEnv):
method build_phase (line 250) | def build_phase(self):
method start_clock (line 253) | def start_clock(self, name):
method do_reset (line 259) | async def do_reset(self):
method run_phase (line 286) | async def run_phase(self):
method run (line 311) | async def run(self):
FILE: verification/block/ifu_compress/test_compress.py
class TestDecompressor (line 7) | class TestDecompressor(BaseTest):
method __init__ (line 12) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 15) | def end_of_elaboration_phase(self):
method run (line 19) | async def run(self):
FILE: verification/block/ifu_compress/testbench.py
function collect_signals (line 13) | def collect_signals(signals, uut, obj, uut_prefix="", obj_prefix=""):
function get_opcode (line 33) | def get_opcode(asm_line, ext="rv32i", size=32):
function generate_assembly_pair (line 52) | def generate_assembly_pair():
class CompressedGenerator (line 85) | class CompressedGenerator:
method get (line 94) | def get(self):
method check (line 109) | def check(self, com, dec):
class InstructionPairItem (line 119) | class InstructionPairItem(uvm_sequence_item):
method __init__ (line 124) | def __init__(self, din, dout):
class CompressedInstructionItem (line 134) | class CompressedInstructionItem(uvm_sequence_item):
method __init__ (line 139) | def __init__(self):
class CompressedSequence (line 149) | class CompressedSequence(uvm_sequence):
method __init__ (line 154) | def __init__(self, name):
method body (line 157) | async def body(self):
class DecompressorDriver (line 167) | class DecompressorDriver(uvm_driver):
method __init__ (line 174) | def __init__(self, *args, **kwargs):
method write (line 182) | async def write(self, instr):
method run_phase (line 190) | async def run_phase(self):
class DecompressorMonitor (line 200) | class DecompressorMonitor(uvm_component):
method __init__ (line 207) | def __init__(self, *args, **kwargs):
method build_phase (line 215) | def build_phase(self):
method run_phase (line 218) | async def run_phase(self):
class Scoreboard (line 225) | class Scoreboard(uvm_component):
method __init__ (line 230) | def __init__(self, name, parent):
method build_phase (line 235) | def build_phase(self):
method connect_phase (line 239) | def connect_phase(self):
method check_phase (line 242) | def check_phase(self):
method final_phase (line 263) | def final_phase(self):
class BaseEnv (line 269) | class BaseEnv(uvm_env):
method build_phase (line 274) | def build_phase(self):
method connect_phase (line 290) | def connect_phase(self):
class BaseTest (line 295) | class BaseTest(uvm_test):
method __init__ (line 300) | def __init__(self, name, parent, env_class=BaseEnv):
method build_phase (line 309) | def build_phase(self):
method run_phase (line 312) | async def run_phase(self):
method run (line 317) | async def run(self):
FILE: verification/block/ifu_mem_ctl/common.py
class Axi4LiteBFM (line 11) | class Axi4LiteBFM:
method __init__ (line 12) | def __init__(self, dut):
method _wait (line 15) | async def _wait(self, signal, max_cycles=200):
method read_handler (line 27) | async def read_handler(self):
function reset (line 47) | async def reset(dut):
function initialize (line 58) | async def initialize(dut):
function write (line 116) | async def write(dut, addr, wdata):
function read (line 129) | async def read(dut, addr):
function rand_iccm_addr (line 136) | def rand_iccm_addr():
function rand_iccm_data (line 140) | def rand_iccm_data():
function rand_ifu_addr (line 144) | def rand_ifu_addr():
function get_bitflip_mask (line 148) | def get_bitflip_mask(do_double_bit):
FILE: verification/block/ifu_mem_ctl/test_err.py
function fetch_miss (line 21) | async def fetch_miss(dut, addr, req_bf_raw=1, uncacheable_bf=1):
function verify_state (line 32) | def verify_state(dut, exp_state):
function dma_sb_error (line 45) | async def dma_sb_error(dut, force_halt=False):
function test_dma_sb_error (line 62) | async def test_dma_sb_error(dut):
function test_dma_sb_error_force_halt (line 73) | async def test_dma_sb_error_force_halt(dut):
function test_ecc_corr (line 83) | async def test_ecc_corr(dut):
function ic_wff (line 96) | async def ic_wff(dut):
function test_ic_wff (line 111) | async def test_ic_wff(dut):
function test_ic_wff_force_halt (line 121) | async def test_ic_wff_force_halt(dut):
function ecc_wff (line 131) | async def ecc_wff(dut):
function test_ecc_wff (line 147) | async def test_ecc_wff(dut):
function test_ecc_wff_force_halt (line 158) | async def test_ecc_wff_force_halt(dut):
FILE: verification/block/ifu_mem_ctl/test_err_stop.py
function fetch_miss (line 13) | async def fetch_miss(dut, addr, req_bf_raw=1, uncacheable_bf=1):
function verify_state (line 24) | def verify_state(dut, exp_state):
function test_err_fetch1 (line 37) | async def test_err_fetch1(dut):
function test_err_fetch2 (line 57) | async def test_err_fetch2(dut):
function test_err_stop_fetch (line 90) | async def test_err_stop_fetch(dut):
FILE: verification/block/ifu_mem_ctl/test_miss.py
function fetch_miss (line 24) | async def fetch_miss(dut, addr, req_bf_raw=1, uncacheable_bf=1, dma_acce...
function verify_state (line 38) | def verify_state(dut, exp_state):
function crit_byp_ok (line 54) | async def crit_byp_ok(dut):
function test_crit_byp_ok (line 65) | async def test_crit_byp_ok(dut):
function test_crit_byp_ok_force_halt (line 73) | async def test_crit_byp_ok_force_halt(dut):
function crit_wrd_rdy (line 82) | async def crit_wrd_rdy(dut):
function test_crit_wrd_rdy (line 98) | async def test_crit_wrd_rdy(dut):
function test_crit_wrd_rdy_force_halt (line 106) | async def test_crit_wrd_rdy_force_halt(dut):
function hit_u_miss (line 115) | async def hit_u_miss(dut):
function test_hit_u_miss (line 131) | async def test_hit_u_miss(dut):
function test_hit_u_miss_force_halt (line 139) | async def test_hit_u_miss_force_halt(dut):
function scnd_miss (line 148) | async def scnd_miss(dut):
function test_scnd_miss (line 159) | async def test_scnd_miss(dut):
function test_scnd_miss_force_halt (line 167) | async def test_scnd_miss_force_halt(dut):
function stall_scnd_miss (line 176) | async def stall_scnd_miss(dut):
function test_stall_scnd_miss (line 187) | async def test_stall_scnd_miss(dut):
function test_stall_scnd_miss_force_halt (line 195) | async def test_stall_scnd_miss_force_halt(dut):
FILE: verification/block/lib_ahb_to_axi4/test_read.py
class AHBReadSequence (line 20) | class AHBReadSequence(uvm_sequence):
method __init__ (line 21) | def __init__(self, name):
method body (line 24) | async def body(self):
class AXI4LiteReadResponseSequence (line 33) | class AXI4LiteReadResponseSequence(uvm_sequence):
method __init__ (line 34) | def __init__(self, name):
method body (line 37) | async def body(self):
class AXI4LiteNoReadDataResponseSequence (line 52) | class AXI4LiteNoReadDataResponseSequence(uvm_sequence):
method __init__ (line 53) | def __init__(self, name):
method body (line 56) | async def body(self):
class AXI4LiteReadReadySequence (line 66) | class AXI4LiteReadReadySequence(uvm_sequence):
method __init__ (line 67) | def __init__(self, name):
method body (line 70) | async def body(self):
function later (line 80) | async def later(cr, cycles):
class NoBackpressureReadSequence (line 88) | class NoBackpressureReadSequence(uvm_sequence):
method body (line 89) | async def body(self):
class BackpressureReadSequence (line 107) | class BackpressureReadSequence(uvm_sequence):
method body (line 108) | async def body(self):
class NoReadDataResponseSequence (line 123) | class NoReadDataResponseSequence(uvm_sequence):
method body (line 124) | async def body(self):
class TestReadNoBackpressure (line 146) | class TestReadNoBackpressure(BaseTest):
method end_of_elaboration_phase (line 151) | def end_of_elaboration_phase(self):
method run (line 155) | async def run(self):
class TestReadBackpressure (line 165) | class TestReadBackpressure(BaseTest):
method end_of_elaboration_phase (line 170) | def end_of_elaboration_phase(self):
method run (line 174) | async def run(self):
class TestReadNoDataResponse (line 184) | class TestReadNoDataResponse(BaseTest):
method end_of_elaboration_phase (line 190) | def end_of_elaboration_phase(self):
method run (line 194) | async def run(self):
FILE: verification/block/lib_ahb_to_axi4/test_write.py
class AHBWriteSequence (line 20) | class AHBWriteSequence(uvm_sequence):
method __init__ (line 21) | def __init__(self, name):
method body (line 24) | async def body(self):
class AXI4LiteWriteResponseSequence (line 36) | class AXI4LiteWriteResponseSequence(uvm_sequence):
method __init__ (line 37) | def __init__(self, name):
method body (line 40) | async def body(self):
class AXI4LiteNoWriteDataResponseSequence (line 55) | class AXI4LiteNoWriteDataResponseSequence(uvm_sequence):
method __init__ (line 56) | def __init__(self, name):
method body (line 59) | async def body(self):
class AXI4LiteNoWriteAddrResponseSequence (line 74) | class AXI4LiteNoWriteAddrResponseSequence(uvm_sequence):
method __init__ (line 75) | def __init__(self, name):
method body (line 78) | async def body(self):
class AXI4LiteNoWriteResponseSequence (line 93) | class AXI4LiteNoWriteResponseSequence(uvm_sequence):
method __init__ (line 94) | def __init__(self, name):
method body (line 97) | async def body(self):
class AXI4LiteWriteReadySequence (line 107) | class AXI4LiteWriteReadySequence(uvm_sequence):
method __init__ (line 108) | def __init__(self, name):
method body (line 111) | async def body(self):
class AXI4LiteNoWriteDataReadySequence (line 118) | class AXI4LiteNoWriteDataReadySequence(uvm_sequence):
method __init__ (line 119) | def __init__(self, name):
method body (line 122) | async def body(self):
class AXI4LiteNoWriteAddrReadySequence (line 129) | class AXI4LiteNoWriteAddrReadySequence(uvm_sequence):
method __init__ (line 130) | def __init__(self, name):
method body (line 133) | async def body(self):
class NoBackpressureWriteSequence (line 143) | class NoBackpressureWriteSequence(uvm_sequence):
method body (line 144) | async def body(self):
class BackpressureWriteSequence (line 158) | class BackpressureWriteSequence(uvm_sequence):
method body (line 159) | async def body(self):
class NoWriteResponseSequence (line 171) | class NoWriteResponseSequence(uvm_sequence):
method body (line 172) | async def body(self):
class NoWriteDataResponseSequence (line 185) | class NoWriteDataResponseSequence(uvm_sequence):
method body (line 186) | async def body(self):
class NoWriteAddrResponseSequence (line 199) | class NoWriteAddrResponseSequence(uvm_sequence):
method body (line 200) | async def body(self):
class TestWriteNoBackpressure (line 217) | class TestWriteNoBackpressure(BaseTest):
method end_of_elaboration_phase (line 222) | def end_of_elaboration_phase(self):
method run (line 226) | async def run(self):
class TestWriteBackpressure (line 236) | class TestWriteBackpressure(BaseTest):
method end_of_elaboration_phase (line 241) | def end_of_elaboration_phase(self):
method run (line 245) | async def run(self):
class TestWriteNoResponse (line 257) | class TestWriteNoResponse(BaseTest):
method end_of_elaboration_phase (line 262) | def end_of_elaboration_phase(self):
method run (line 266) | async def run(self):
class TestWriteNoAddrResponse (line 276) | class TestWriteNoAddrResponse(BaseTest):
method end_of_elaboration_phase (line 282) | def end_of_elaboration_phase(self):
method run (line 286) | async def run(self):
class TestWriteNoDataResponse (line 298) | class TestWriteNoDataResponse(BaseTest):
method end_of_elaboration_phase (line 304) | def end_of_elaboration_phase(self):
method run (line 308) | async def run(self):
FILE: verification/block/lib_ahb_to_axi4/testbench.py
class AXI4LiteReadyItem (line 19) | class AXI4LiteReadyItem(uvm_sequence_item):
method __init__ (line 25) | def __init__(self, channels, ready=True):
class AXI4LiteResponseItem (line 31) | class AXI4LiteResponseItem(uvm_sequence_item):
method __init__ (line 36) | def __init__(self, channels):
class AHBLiteManagerBFM (line 44) | class AHBLiteManagerBFM(uvm_component):
class HTRANS (line 66) | class HTRANS(Enum):
class HBURST (line 72) | class HBURST(Enum):
method __init__ (line 82) | def __init__(self, name, parent, uut, signal_prefix="", signal_map=None):
method _wait (line 111) | async def _wait(self, signal, max_cycles=200):
method write (line 124) | async def write(self, addr, data):
method read (line 161) | async def read(self, addr, length):
class AHBLiteManagerDriver (line 197) | class AHBLiteManagerDriver(uvm_driver):
method __init__ (line 202) | def __init__(self, *args, **kwargs):
method run_phase (line 207) | async def run_phase(self):
class AHBLiteMonitor (line 225) | class AHBLiteMonitor(uvm_component):
method __init__ (line 230) | def __init__(self, *args, **kwargs):
method build_phase (line 235) | def build_phase(self):
method watch (line 238) | async def watch(self):
method run_phase (line 299) | async def run_phase(self):
class AXI4LiteSubordinateBFM (line 306) | class AXI4LiteSubordinateBFM(uvm_component):
method __init__ (line 340) | def __init__(self, name, parent, uut, signal_prefix="", signal_map=None):
method _wait (line 370) | async def _wait(self, signal, max_cycles=200):
method set_ready (line 383) | async def set_ready(self, channel, ready):
method respond_aw (line 394) | async def respond_aw(self):
method respond_w (line 400) | async def respond_w(self):
method respond_b (line 407) | async def respond_b(self):
method respond_ar (line 417) | async def respond_ar(self):
method respond_r (line 423) | async def respond_r(self):
class AXI4LiteSubordinateDriver (line 433) | class AXI4LiteSubordinateDriver(uvm_driver):
method __init__ (line 438) | def __init__(self, *args, **kwargs):
method run_phase (line 443) | async def run_phase(self):
class Scoreboard (line 472) | class Scoreboard(uvm_component):
method __init__ (line 478) | def __init__(self, name, parent):
method build_phase (line 483) | def build_phase(self):
method connect_phase (line 489) | def connect_phase(self):
method check_phase (line 493) | def check_phase(self):
method final_phase (line 527) | def final_phase(self):
class BaseEnv (line 536) | class BaseEnv(uvm_env):
method build_phase (line 541) | def build_phase(self):
method connect_phase (line 589) | def connect_phase(self):
class BaseTest (line 600) | class BaseTest(uvm_test):
method __init__ (line 605) | def __init__(self, name, parent, env_class=BaseEnv):
method build_phase (line 614) | def build_phase(self):
method start_clock (line 617) | def start_clock(self, name):
method do_reset (line 623) | async def do_reset(self):
method run_phase (line 652) | async def run_phase(self):
method run (line 676) | async def run(self):
FILE: verification/block/lib_axi4_to_ahb/ahb_lite_agent.py
class AHBLiteAgent (line 13) | class AHBLiteAgent(uvm_agent):
method build_phase (line 19) | def build_phase(self):
method connect_phase (line 25) | def connect_phase(self):
class AHBLiteDriver (line 29) | class AHBLiteDriver(uvm_driver):
method build_phase (line 30) | def build_phase(self):
method start_of_simulation_phase (line 35) | def start_of_simulation_phase(self):
method run_phase (line 38) | async def run_phase(self):
method drive (line 58) | async def drive(self, item):
class AHBLiteMonitor (line 66) | class AHBLiteMonitor(BaseMonitor):
method __init__ (line 67) | def __init__(self, name, parent):
method build_phase (line 70) | def build_phase(self):
FILE: verification/block/lib_axi4_to_ahb/ahb_lite_bfm.py
class AHBLiteBFM (line 18) | class AHBLiteBFM(metaclass=utility_classes.Singleton):
method __init__ (line 19) | def __init__(self):
method req_driver_q_put (line 28) | async def req_driver_q_put(self, ahb_hrdata, ahb_hready, ahb_hresp):
method req_monitor_q_get (line 32) | async def req_monitor_q_get(self):
method rsp_monitor_q_get (line 36) | async def rsp_monitor_q_get(self):
method drive (line 40) | async def drive(self):
method req_monitor_q_bfm (line 78) | async def req_monitor_q_bfm(self):
method rsp_monitor_q_bfm (line 89) | async def rsp_monitor_q_bfm(self):
method start_bfm (line 97) | def start_bfm(self):
FILE: verification/block/lib_axi4_to_ahb/ahb_lite_pkg.py
class AHB_LITE_RESPONSE_CODES (line 25) | class AHB_LITE_RESPONSE_CODES(IntEnum):
class AHB_LITE_TRANSFER_TYPE_ENCODING (line 29) | class AHB_LITE_TRANSFER_TYPE_ENCODING(IntEnum):
class AHB_LITE_NOTIFICATION (line 36) | class AHB_LITE_NOTIFICATION(IntEnum):
FILE: verification/block/lib_axi4_to_ahb/ahb_lite_seq.py
class AHBLiteBaseSeqItem (line 12) | class AHBLiteBaseSeqItem(uvm_sequence_item):
method __init__ (line 13) | def __init__(self, name):
method randomize (line 19) | def randomize(self):
method __eq__ (line 22) | def __eq__(self, other):
method __str__ (line 25) | def __str__(self):
class AHBLiteInactiveSeqItem (line 29) | class AHBLiteInactiveSeqItem(AHBLiteBaseSeqItem):
method __init__ (line 30) | def __init__(self, name):
class AHBLiteReadyReadSeqItem (line 34) | class AHBLiteReadyReadSeqItem(AHBLiteBaseSeqItem):
method __init__ (line 35) | def __init__(self, name):
method randomize (line 40) | def randomize(self):
class AHBLiteReadyWriteSeqItem (line 44) | class AHBLiteReadyWriteSeqItem(AHBLiteBaseSeqItem):
method __init__ (line 45) | def __init__(self, name):
class AHBLiteReadyNoDataSeqItem (line 51) | class AHBLiteReadyNoDataSeqItem(AHBLiteBaseSeqItem):
method __init__ (line 52) | def __init__(self, name):
class AHBLiteAcceptWriteSeq (line 58) | class AHBLiteAcceptWriteSeq(BaseSeq):
method body (line 59) | async def body(self):
class AHBLiteAcceptReadSeq (line 67) | class AHBLiteAcceptReadSeq(BaseSeq):
method body (line 68) | async def body(self):
FILE: verification/block/lib_axi4_to_ahb/axi_pkg.py
class AXI_WRITE_RESPONSE_CODES (line 50) | class AXI_WRITE_RESPONSE_CODES(IntEnum):
class AXI_READ_RESPONSE_CODES (line 61) | class AXI_READ_RESPONSE_CODES(IntEnum):
class AXI_AXSIZE_ENCODING (line 72) | class AXI_AXSIZE_ENCODING(IntEnum):
class AXI_NOTIFICATION (line 83) | class AXI_NOTIFICATION(IntEnum):
FILE: verification/block/lib_axi4_to_ahb/axi_r_agent.py
class AXIReadChannelAgent (line 16) | class AXIReadChannelAgent(uvm_agent):
method build_phase (line 17) | def build_phase(self):
method connect_phase (line 23) | def connect_phase(self):
class AXIReadChannelDriver (line 27) | class AXIReadChannelDriver(uvm_driver):
method build_phase (line 28) | def build_phase(self):
method start_of_simulation_phase (line 33) | def start_of_simulation_phase(self):
method run_phase (line 36) | async def run_phase(self):
method drive (line 62) | async def drive(self, item):
class AXIReadChannelMonitor (line 73) | class AXIReadChannelMonitor(BaseMonitor):
method __init__ (line 74) | def __init__(self, name, parent):
method build_phase (line 77) | def build_phase(self):
FILE: verification/block/lib_axi4_to_ahb/axi_r_bfm.py
class AXIReadChannelBFM (line 13) | class AXIReadChannelBFM(metaclass=utility_classes.Singleton):
method __init__ (line 14) | def __init__(self):
method req_driver_q_put (line 24) | async def req_driver_q_put(
method req_monitor_q_get (line 43) | async def req_monitor_q_get(self):
method rsp_monitor_q_get (line 47) | async def rsp_monitor_q_get(self):
method drive (line 51) | async def drive(self):
method req_monitor_q_bfm (line 91) | async def req_monitor_q_bfm(self):
method rsp_monitor_q_bfm (line 109) | async def rsp_monitor_q_bfm(self):
method start_bfm (line 121) | def start_bfm(self):
FILE: verification/block/lib_axi4_to_ahb/axi_r_seq.py
class AXIReadBaseSeqItem (line 12) | class AXIReadBaseSeqItem(uvm_sequence_item):
method __init__ (line 13) | def __init__(self, name):
method randomize (line 25) | def randomize(self):
method __eq__ (line 28) | def __eq__(self, other):
method __str__ (line 31) | def __str__(self):
class AXIReadTransactionRequestSeqItem (line 35) | class AXIReadTransactionRequestSeqItem(AXIReadBaseSeqItem):
method __init__ (line 36) | def __init__(self, name):
method randomize (line 40) | def randomize(self):
class AXIReadResponseReadSeqItem (line 44) | class AXIReadResponseReadSeqItem(AXIReadBaseSeqItem):
method __init__ (line 45) | def __init__(
class AXIReadInactiveSeqItem (line 53) | class AXIReadInactiveSeqItem(AXIReadBaseSeqItem):
method __init__ (line 54) | def __init__(self, name):
class AXIReadTransactionRequestSeq (line 59) | class AXIReadTransactionRequestSeq(BaseSeq):
method body (line 60) | async def body(self):
class AXIReadTransactionResponseSeq (line 68) | class AXIReadTransactionResponseSeq(BaseSeq):
method body (line 69) | async def body(self):
FILE: verification/block/lib_axi4_to_ahb/axi_w_agent.py
class AXIWriteChannelAgent (line 19) | class AXIWriteChannelAgent(uvm_agent):
method build_phase (line 25) | def build_phase(self):
method connect_phase (line 31) | def connect_phase(self):
class AXIWriteChannelDriver (line 35) | class AXIWriteChannelDriver(uvm_driver):
method build_phase (line 36) | def build_phase(self):
method start_of_simulation_phase (line 39) | def start_of_simulation_phase(self):
method run_phase (line 42) | async def run_phase(self):
method wait_handshake (line 78) | async def wait_handshake(self, sig_name=None, TIMEOUT_THRESHOLD=30):
method drive (line 90) | async def drive(self, item):
class AXIWriteChannelMonitor (line 105) | class AXIWriteChannelMonitor(BaseMonitor):
method __init__ (line 106) | def __init__(self, name, parent):
method build_phase (line 109) | def build_phase(self):
FILE: verification/block/lib_axi4_to_ahb/axi_w_bfm.py
class AXIWriteChannelBFM (line 13) | class AXIWriteChannelBFM(metaclass=utility_classes.Singleton):
method __init__ (line 14) | def __init__(self):
method req_driver_q_put (line 22) | async def req_driver_q_put(
method req_monitor_q_get (line 49) | async def req_monitor_q_get(self):
method rsp_monitor_q_get (line 53) | async def rsp_monitor_q_get(self):
method drive (line 57) | async def drive(self):
method req_monitor_q_bfm (line 99) | async def req_monitor_q_bfm(self):
method rsp_monitor_q_bfm (line 129) | async def rsp_monitor_q_bfm(self):
method start_bfm (line 141) | def start_bfm(self):
FILE: verification/block/lib_axi4_to_ahb/axi_w_seq.py
class AXIWriteBaseSeqItem (line 13) | class AXIWriteBaseSeqItem(uvm_sequence_item):
method __init__ (line 14) | def __init__(self, name):
method randomize (line 30) | def randomize(self):
method __eq__ (line 33) | def __eq__(self, other):
method __str__ (line 36) | def __str__(self):
class AXIWriteTransactionRequestSeqItem (line 40) | class AXIWriteTransactionRequestSeqItem(AXIWriteBaseSeqItem):
method __init__ (line 41) | def __init__(self, name):
method randomize (line 45) | def randomize(self):
class AXIWriteDataSeqItem (line 50) | class AXIWriteDataSeqItem(AXIWriteBaseSeqItem):
method __init__ (line 51) | def __init__(self, name):
method randomize (line 56) | def randomize(self):
class AXIWriteLastDataSeqItem (line 60) | class AXIWriteLastDataSeqItem(AXIWriteDataSeqItem):
method __init__ (line 61) | def __init__(self, name):
class AXIWriteResponseWriteSeqItem (line 66) | class AXIWriteResponseWriteSeqItem(AXIWriteBaseSeqItem):
method __init__ (line 67) | def __init__(
class AXIWriteInactiveSeqItem (line 75) | class AXIWriteInactiveSeqItem(AXIWriteBaseSeqItem):
method __init__ (line 76) | def __init__(self, name):
class AXIWriteTransactionRequestSeq (line 82) | class AXIWriteTransactionRequestSeq(BaseSeq):
method body (line 83) | async def body(self):
class AXIWriteDataSeq (line 92) | class AXIWriteDataSeq(BaseSeq):
method body (line 93) | async def body(self):
class AXIWriteResponseSeq (line 102) | class AXIWriteResponseSeq(BaseSeq):
method body (line 103) | async def body(self):
FILE: verification/block/lib_axi4_to_ahb/common.py
function collect_signals (line 10) | def collect_signals(signals, uut, obj):
function get_int (line 26) | def get_int(signal):
function get_signals (line 34) | def get_signals(signals, obj):
class BaseSeq (line 48) | class BaseSeq(uvm_sequence):
method run_items (line 49) | async def run_items(self, items):
class BaseMonitor (line 56) | class BaseMonitor(uvm_component):
method __init__ (line 57) | def __init__(self, name, parent):
method build_phase (line 60) | def build_phase(self):
method monitor_req (line 65) | async def monitor_req(self):
method monitor_rsp (line 71) | async def monitor_rsp(self):
method run_phase (line 77) | async def run_phase(self):
FILE: verification/block/lib_axi4_to_ahb/coordinator_seq.py
class CoordinatorSeq (line 19) | class CoordinatorSeq(uvm_sequence):
method axi_write (line 20) | async def axi_write(self, axi_seqr, ahb_seqr):
method axi_read (line 38) | async def axi_read(self, axi_seqr, ahb_seqr):
method delay (line 53) | async def delay(self, i):
method ahb_response_handler (line 57) | async def ahb_response_handler(self, ahb_seqr, is_read=True):
class TestWriteChannelSeq (line 77) | class TestWriteChannelSeq(CoordinatorSeq):
method body (line 78) | async def body(self):
class TestReadChannelSeq (line 88) | class TestReadChannelSeq(CoordinatorSeq):
method body (line 89) | async def body(self):
class TestBothChannelsSeq (line 99) | class TestBothChannelsSeq(CoordinatorSeq):
method body (line 100) | async def body(self):
FILE: verification/block/lib_axi4_to_ahb/test_axi.py
class TestAXI (line 11) | class TestAXI(BaseTest):
method end_of_elaboration_phase (line 12) | def end_of_elaboration_phase(self):
method run (line 15) | async def run(self):
FILE: verification/block/lib_axi4_to_ahb/test_axi_read_channel.py
class TestAXIReadChannel (line 11) | class TestAXIReadChannel(BaseTest):
method end_of_elaboration_phase (line 12) | def end_of_elaboration_phase(self):
method run (line 15) | async def run(self):
FILE: verification/block/lib_axi4_to_ahb/test_axi_write_channel.py
class TestAXIWriteChannel (line 10) | class TestAXIWriteChannel(BaseTest):
method end_of_elaboration_phase (line 11) | def end_of_elaboration_phase(self):
method run (line 14) | async def run(self):
FILE: verification/block/lib_axi4_to_ahb/testbench.py
class Scoreboard (line 27) | class Scoreboard(uvm_component):
method build_phase (line 28) | def build_phase(self):
method connect_phase (line 50) | def connect_phase(self):
method check_phase (line 60) | def check_phase(self):
method check_axi_write (line 92) | def check_axi_write(self):
method check_axi_read (line 145) | def check_axi_read(self):
method check_ahb (line 192) | def check_ahb(self):
class BaseEnvironment (line 265) | class BaseEnvironment(uvm_env):
method build_phase (line 266) | def build_phase(self):
method connect_phase (line 282) | def connect_phase(self):
class BaseTest (line 293) | class BaseTest(uvm_test):
method __init__ (line 296) | def __init__(self, name, parent):
method build_phase (line 303) | def build_phase(self):
method start_clock (line 307) | def start_clock(self, name):
method do_reset (line 313) | async def do_reset(self, signalName, timeLength="100e-9", isActiveHigh...
method config (line 346) | def config(self):
method run_phase (line 352) | async def run_phase(self):
method run (line 370) | async def run(self):
FILE: verification/block/lsu_tl/test_lsu_tl.py
class TestTriggerLogic (line 14) | class TestTriggerLogic(BaseTest):
method end_of_elaboration_phase (line 15) | def end_of_elaboration_phase(self):
method run_phase (line 19) | async def run_phase(self):
method run (line 27) | async def run(self):
FILE: verification/block/lsu_tl/testbench.py
class TlInputItem (line 28) | class TlInputItem(uvm_sequence_item):
method __init__ (line 33) | def __init__(self, data=0, tdata=None, match=0):
method randomize (line 43) | def randomize(self):
method random_trigger (line 58) | def random_trigger(self, data, matching):
class TlOutputItem (line 97) | class TlOutputItem(uvm_sequence_item):
method __init__ (line 102) | def __init__(self, matches):
class TlDriver (line 111) | class TlDriver(uvm_driver):
method __init__ (line 116) | def __init__(self, *args, **kwargs):
method run_phase (line 121) | async def run_phase(self):
class TlInputMonitor (line 150) | class TlInputMonitor(uvm_component):
method __init__ (line 155) | def __init__(self, *args, **kwargs):
method build_phase (line 160) | def build_phase(self):
method run_phase (line 163) | async def run_phase(self):
class TlOutputMonitor (line 181) | class TlOutputMonitor(uvm_component):
method __init__ (line 186) | def __init__(self, *args, **kwargs):
method build_phase (line 191) | def build_phase(self):
method run_phase (line 194) | async def run_phase(self):
class TlScoreboard (line 209) | class TlScoreboard(uvm_component):
method __init__ (line 214) | def __init__(self, name, parent):
method build_phase (line 219) | def build_phase(self):
method connect_phase (line 225) | def connect_phase(self):
method check_phase (line 229) | def check_phase(self):
method final_phase (line 269) | def final_phase(self):
class TlSequence (line 278) | class TlSequence(uvm_sequence):
method __init__ (line 284) | def __init__(self, name, ops=None):
method body (line 287) | async def body(self):
class BaseEnv (line 301) | class BaseEnv(uvm_env):
method build_phase (line 306) | def build_phase(self):
method connect_phase (line 324) | def connect_phase(self):
class BaseTest (line 334) | class BaseTest(uvm_test):
method __init__ (line 339) | def __init__(self, name, parent, env_class=BaseEnv):
method build_phase (line 348) | def build_phase(self):
method start_clock (line 351) | def start_clock(self, name):
method do_reset (line 357) | async def do_reset(self):
method run_phase (line 363) | async def run_phase(self):
method run (line 383) | async def run(self):
FILE: verification/block/noxfile.py
function isSimFailure (line 32) | def isSimFailure(
function verify_block (line 95) | def verify_block(session, blockName, testName, coverage=""):
function pic_verify (line 146) | def pic_verify(session, blockName, testName, coverage):
function pic_gw_verify (line 154) | def pic_gw_verify(session, blockName, testName, coverage):
function dec_tl_verify (line 162) | def dec_tl_verify(session, blockName, testName, coverage):
function dec_ib_verify (line 170) | def dec_ib_verify(session, blockName, testName, coverage):
function dma_verify (line 190) | def dma_verify(session, blockName, testName, coverage):
function ifu_compress_verify (line 198) | def ifu_compress_verify(session, blockName, testName, coverage):
function ifu_mem_ctl_verify (line 206) | def ifu_mem_ctl_verify(session, blockName, testName, coverage):
function exu_alu_verify (line 224) | def exu_alu_verify(session, blockName, testName, coverage):
function exu_mul_verify (line 237) | def exu_mul_verify(session, blockName, testName, coverage):
function exu_div_verify (line 250) | def exu_div_verify(session, blockName, testName, coverage):
function iccm_verify (line 263) | def iccm_verify(session, blockName, testName, coverage):
function dccm_verify (line 276) | def dccm_verify(session, blockName, testName, coverage):
function dcls_verify (line 289) | def dcls_verify(session, blockName, testName, coverage):
function lib_axi4_to_ahb_verify (line 304) | def lib_axi4_to_ahb_verify(session, blockName, testName, coverage):
function lib_ahb_to_axi4_verify (line 318) | def lib_ahb_to_axi4_verify(session, blockName, testName, coverage):
function pmp_verify (line 333) | def pmp_verify(session, blockName, testName, coverage):
function pmp_random_verify (line 346) | def pmp_random_verify(session, blockName, testName, coverage):
function dec_verify (line 359) | def dec_verify(session, blockName, testName, coverage):
function dec_tlu_ctl_verify (line 372) | def dec_tlu_ctl_verify(session, blockName, testName, coverage):
function dmi_verify (line 387) | def dmi_verify(session, blockName, testName, coverage):
function lsu_tl_verify (line 395) | def lsu_tl_verify(session, blockName, testName, coverage):
function dec_pmp_ctl_verify (line 403) | def dec_pmp_ctl_verify(session, blockName, testName, coverage):
function lint (line 408) | def lint(session: nox.Session) -> None:
function test_lint (line 417) | def test_lint(session: nox.Session) -> None:
FILE: verification/block/pic/test_clken.py
class ClockEnableItem (line 16) | class ClockEnableItem(uvm_sequence_item):
method __init__ (line 17) | def __init__(self, clk_en, io_clk_en):
class ClockStateItem (line 23) | class ClockStateItem(uvm_sequence_item):
method __init__ (line 24) | def __init__(self, state):
class ClkenDriver (line 32) | class ClkenDriver(uvm_driver):
method __init__ (line 42) | def __init__(self, *args, **kwargs):
method run_phase (line 50) | async def run_phase(self):
class ClkenMonitor (line 63) | class ClkenMonitor(uvm_component):
method __init__ (line 74) | def __init__(self, *args, **kwargs):
method build_phase (line 85) | def build_phase(self):
method run_phase (line 88) | async def run_phase(self):
class ClockMonitor (line 108) | class ClockMonitor(uvm_component):
method __init__ (line 133) | def __init__(self, *args, **kwargs):
method build_phase (line 144) | def build_phase(self):
method run_phase (line 147) | async def run_phase(self):
method monitor_clock (line 163) | async def monitor_clock(self, name):
class Scoreboard (line 184) | class Scoreboard(uvm_component):
method __init__ (line 202) | def __init__(self, name, parent):
method build_phase (line 207) | def build_phase(self):
method connect_phase (line 211) | def connect_phase(self):
method check_phase (line 214) | def check_phase(self):
method final_phase (line 255) | def final_phase(self):
class TestSequence (line 264) | class TestSequence(uvm_sequence):
method body (line 269) | async def body(self):
class TestEnv (line 316) | class TestEnv(BaseEnv):
method build_phase (line 321) | def build_phase(self):
method connect_phase (line 337) | def connect_phase(self):
class TestClockEnable (line 345) | class TestClockEnable(BaseTest):
method __init__ (line 350) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 353) | def end_of_elaboration_phase(self):
method run (line 357) | async def run(self):
FILE: verification/block/pic/test_config.py
class TestSequence (line 12) | class TestSequence(uvm_sequence):
method __init__ (line 18) | def __init__(self, name):
method body (line 22) | async def body(self):
class Scoreboard (line 64) | class Scoreboard(uvm_component):
method __init__ (line 70) | def __init__(self, name, parent):
method build_phase (line 77) | def build_phase(self):
method connect_phase (line 81) | def connect_phase(self):
method check_phase (line 84) | def check_phase(self):
method final_phase (line 128) | def final_phase(self):
class TestEnv (line 137) | class TestEnv(BaseEnv):
method build_phase (line 138) | def build_phase(self):
method connect_phase (line 144) | def connect_phase(self):
class TestConfig (line 152) | class TestConfig(BaseTest):
method __init__ (line 157) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 160) | def end_of_elaboration_phase(self):
method run (line 164) | async def run(self):
FILE: verification/block/pic/test_pending.py
class TestSequence (line 14) | class TestSequence(uvm_sequence):
method __init__ (line 15) | def __init__(self, name):
method body (line 23) | async def body(self):
class Scoreboard (line 69) | class Scoreboard(uvm_component):
method __init__ (line 70) | def __init__(self, name, parent):
method build_phase (line 76) | def build_phase(self):
method connect_phase (line 80) | def connect_phase(self):
method check_phase (line 83) | def check_phase(self):
method final_phase (line 121) | def final_phase(self):
class TestEnv (line 130) | class TestEnv(BaseEnv):
method build_phase (line 131) | def build_phase(self):
method connect_phase (line 141) | def connect_phase(self):
class TestPending (line 150) | class TestPending(BaseTest):
method __init__ (line 155) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 158) | def end_of_elaboration_phase(self):
method run (line 162) | async def run(self):
FILE: verification/block/pic/test_prioritization.py
class TestSequence (line 25) | class TestSequence(uvm_sequence):
method __init__ (line 26) | def __init__(self, name):
method body (line 35) | async def body(self):
class Scoreboard (line 129) | class Scoreboard(uvm_component):
method __init__ (line 130) | def __init__(self, name, parent):
method build_phase (line 137) | def build_phase(self):
method connect_phase (line 141) | def connect_phase(self):
method check_phase (line 144) | def check_phase(self):
method final_phase (line 277) | def final_phase(self):
class TestEnv (line 286) | class TestEnv(BaseEnv):
method build_phase (line 287) | def build_phase(self):
method connect_phase (line 293) | def connect_phase(self):
class TestPrioritization (line 304) | class TestPrioritization(BaseTest):
method __init__ (line 307) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 310) | def end_of_elaboration_phase(self):
method run (line 314) | async def run(self):
FILE: verification/block/pic/test_reset.py
class TestReset (line 12) | class TestReset(BaseTest):
method run (line 17) | async def run(self):
FILE: verification/block/pic/test_servicing.py
class TestSequence (line 25) | class TestSequence(uvm_sequence):
method __init__ (line 26) | def __init__(self, name):
method body (line 35) | async def body(self):
class Scoreboard (line 149) | class Scoreboard(uvm_component):
method __init__ (line 150) | def __init__(self, name, parent):
method build_phase (line 157) | def build_phase(self):
method connect_phase (line 161) | def connect_phase(self):
method check_phase (line 164) | def check_phase(self):
method final_phase (line 259) | def final_phase(self):
class TestEnv (line 268) | class TestEnv(BaseEnv):
method build_phase (line 269) | def build_phase(self):
method connect_phase (line 275) | def connect_phase(self):
class TestServicing (line 286) | class TestServicing(BaseTest):
method __init__ (line 289) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 292) | def end_of_elaboration_phase(self):
method run (line 296) | async def run(self):
FILE: verification/block/pic/testbench.py
class RegisterMap (line 15) | class RegisterMap:
method __init__ (line 20) | def __init__(self, max_irqs=32, base_addr=0xF00C0000):
method add_reg (line 51) | def add_reg(self, name, addr):
class BusWriteItem (line 59) | class BusWriteItem(uvm_sequence_item):
method __init__ (line 64) | def __init__(self, addr, data):
method randomize (line 69) | def randomize(self):
class BusReadItem (line 73) | class BusReadItem(uvm_sequence_item):
method __init__ (line 78) | def __init__(self, addr, data=None):
method randomize (line 83) | def randomize(self):
class PrioLvlItem (line 87) | class PrioLvlItem(uvm_sequence_item):
method __init__ (line 88) | def __init__(self, prio):
class PrioThrItem (line 93) | class PrioThrItem(uvm_sequence_item):
method __init__ (line 94) | def __init__(self, prio):
class IrqItem (line 99) | class IrqItem(uvm_sequence_item):
method __init__ (line 100) | def __init__(self, irqs):
class ClaimItem (line 105) | class ClaimItem(uvm_sequence_item):
method __init__ (line 106) | def __init__(self, claimid, claimpl, mexintpend, mhwakeup):
class WaitItem (line 115) | class WaitItem(uvm_sequence_item):
method __init__ (line 120) | def __init__(self, cycles):
method randomize (line 124) | def randomize(self):
function collect_signals (line 131) | def collect_signals(signals, uut, obj):
class RegisterBfm (line 150) | class RegisterBfm:
method __init__ (line 165) | def __init__(self, uut, clk):
method read (line 173) | async def read(self, addr):
method write (line 194) | async def write(self, addr, data):
class RegisterDriver (line 211) | class RegisterDriver(uvm_driver):
method __init__ (line 216) | def __init__(self, *args, **kwargs):
method run_phase (line 221) | async def run_phase(self):
class RegisterMonitor (line 237) | class RegisterMonitor(uvm_component):
method __init__ (line 242) | def __init__(self, *args, **kwargs):
method build_phase (line 247) | def build_phase(self):
method run_phase (line 250) | async def run_phase(self):
class PrioDriver (line 275) | class PrioDriver(uvm_driver):
method __init__ (line 285) | def __init__(self, *args, **kwargs):
method run_phase (line 293) | async def run_phase(self):
class PrioMonitor (line 307) | class PrioMonitor(uvm_component):
method __init__ (line 318) | def __init__(self, *args, **kwargs):
method build_phase (line 329) | def build_phase(self):
method run_phase (line 332) | async def run_phase(self):
class IrqDriver (line 355) | class IrqDriver(uvm_driver):
method __init__ (line 364) | def __init__(self, *args, **kwargs):
method run_phase (line 372) | async def run_phase(self):
class IrqMonitor (line 384) | class IrqMonitor(uvm_component):
method __init__ (line 394) | def __init__(self, *args, **kwargs):
method build_phase (line 404) | def build_phase(self):
method run_phase (line 407) | async def run_phase(self):
class ClaimMonitor (line 423) | class ClaimMonitor(uvm_component):
method __init__ (line 434) | def __init__(self, *args, **kwargs):
method build_phase (line 445) | def build_phase(self):
method run_phase (line 448) | async def run_phase(self):
class PriorityPredictor (line 478) | class PriorityPredictor:
class Irq (line 479) | class Irq:
method __init__ (line 484) | def __init__(self, n):
method __str__ (line 490) | def __str__(self):
method __repr__ (line 498) | def __repr__(self):
method __init__ (line 501) | def __init__(self, logger=None):
method predict (line 509) | def predict(self):
class BaseEnv (line 557) | class BaseEnv(uvm_env):
method build_phase (line 562) | def build_phase(self):
method connect_phase (line 597) | def connect_phase(self):
class BaseTest (line 606) | class BaseTest(uvm_test):
method __init__ (line 611) | def __init__(self, name, parent, env_class=BaseEnv):
method build_phase (line 619) | def build_phase(self):
method start_clock (line 622) | def start_clock(self, name):
method do_reset (line 628) | async def do_reset(self):
method run_phase (line 649) | async def run_phase(self):
method run (line 670) | async def run(self):
FILE: verification/block/pic_gw/test_gateway.py
function start_clocks (line 14) | async def start_clocks(dut):
function do_reset (line 31) | async def do_reset(dut):
function clear_pending (line 46) | async def clear_pending(dut):
function test_level (line 61) | async def test_level(dut, pol):
function test_level_hi (line 118) | async def test_level_hi(dut):
function test_level_lo (line 124) | async def test_level_lo(dut):
function test_edge (line 129) | async def test_edge(dut, pol):
function test_edge_rising (line 177) | async def test_edge_rising(dut):
function test_edge_falling (line 183) | async def test_edge_falling(dut):
function test_edge_reset (line 188) | async def test_edge_reset(dut, pol):
function test_edge_rising_reset (line 236) | async def test_edge_rising_reset(dut):
function test_edge_falling_reset (line 242) | async def test_edge_falling_reset(dut):
FILE: verification/block/pmp/common.py
class BaseSequence (line 7) | class BaseSequence(uvm_sequence):
method __init__ (line 10) | def __init__(self, name):
method accessAtAddr (line 18) | async def accessAtAddr(self, addr):
method randomAccessInAddrRange (line 27) | async def randomAccessInAddrRange(self, start_addr, end_addr):
method checkRangeBoundary (line 32) | async def checkRangeBoundary(self, addr):
FILE: verification/block/pmp/test_address_matching.py
class TestSequence (line 88) | class TestSequence(BaseSequence):
method __init__ (line 89) | def __init__(self, name):
method body (line 92) | async def body(self):
class TestAddressMatching (line 133) | class TestAddressMatching(BaseTest):
method __init__ (line 145) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 148) | def end_of_elaboration_phase(self):
method run (line 152) | async def run(self):
FILE: verification/block/pmp/test_multiple_configs.py
class TestSequence (line 64) | class TestSequence(BaseSequence):
method __init__ (line 65) | def __init__(self, name):
method body (line 68) | async def body(self):
class TestMultipleConfigs (line 96) | class TestMultipleConfigs(BaseTest):
method __init__ (line 102) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 105) | def end_of_elaboration_phase(self):
method run (line 109) | async def run(self):
FILE: verification/block/pmp/test_xwr_access.py
class TestSequence (line 16) | class TestSequence(uvm_sequence):
method __init__ (line 17) | def __init__(self, name):
method body (line 22) | async def body(self):
class TestXWRAccess (line 67) | class TestXWRAccess(BaseTest):
method __init__ (line 73) | def __init__(self, name, parent):
method end_of_elaboration_phase (line 76) | def end_of_elaboration_phase(self):
method run (line 80) | async def run(self):
FILE: verification/block/pmp/testbench.py
class RegisterMap (line 22) | class RegisterMap:
method __init__ (line 23) | def __init__(self, pmp_entries):
function getDecodedEntryCfg (line 33) | def getDecodedEntryCfg(regs, index, range_only=False):
class PMPWriteCfgCSRItem (line 88) | class PMPWriteCfgCSRItem(uvm_sequence_item):
method __init__ (line 89) | def __init__(self, index, pmpcfg):
class PMPWriteAddrCSRItem (line 95) | class PMPWriteAddrCSRItem(uvm_sequence_item):
method __init__ (line 96) | def __init__(self, index, pmpaddr):
class PMPCheckItem (line 102) | class PMPCheckItem(uvm_sequence_item):
method __init__ (line 103) | def __init__(self, channel, addr, type, err=None):
function collect_signals (line 114) | def collect_signals(signals, uut, obj):
class PMPDriver (line 133) | class PMPDriver(uvm_driver):
method __init__ (line 144) | def __init__(self, *args, **kwargs):
method run_phase (line 153) | async def run_phase(self):
class PMPMonitor (line 173) | class PMPMonitor(uvm_component):
method __init__ (line 185) | def __init__(self, *args, **kwargs):
method build_phase (line 196) | def build_phase(self):
method run_phase (line 199) | async def run_phase(self):
class Scoreboard (line 215) | class Scoreboard(uvm_component):
method build_phase (line 216) | def build_phase(self):
method connect_phase (line 222) | def connect_phase(self):
method check_phase (line 225) | def check_phase(self):
method final_phase (line 276) | def final_phase(self):
class BaseEnv (line 285) | class BaseEnv(uvm_env):
method build_phase (line 290) | def build_phase(self):
method connect_phase (line 316) | def connect_phase(self):
class BaseTest (line 324) | class BaseTest(uvm_test):
method __init__ (line 329) | def __init__(self, name, parent, env_class=BaseEnv):
method build_phase (line 338) | def build_phase(self):
method start_clock (line 341) | def start_clock(self, name):
method run_phase (line 347) | async def run_phase(self):
method run (line 363) | async def run(self):
FILE: verification/block/pmp_random/test_pmp_random.py
class PMPRandomLegalSequence (line 13) | class PMPRandomLegalSequence(uvm_sequence):
method __init__ (line 16) | def __init__(self, name):
method legalize_pmpcfg (line 19) | def legalize_pmpcfg(self, item):
method legalize_pmpaddr (line 28) | def legalize_pmpaddr(self, item):
method body (line 34) | async def body(self):
class TestRandomPMP (line 50) | class TestRandomPMP(BaseTest):
method end_of_elaboration_phase (line 51) | def end_of_elaboration_phase(self):
method run (line 56) | async def run(self):
FILE: verification/block/pmp_random/testbench.py
class InputItem (line 35) | class InputItem(uvm_sequence_item):
method __init__ (line 42) | def __init__(self, cfg=0, entry=0, pmp_addr=0, chan_addr=0, chan_type=...
method randomize (line 53) | def randomize(self):
class PMPWriteDriver (line 68) | class PMPWriteDriver(uvm_driver):
method __init__ (line 73) | def __init__(self, *args, **kwargs):
method run_phase (line 78) | async def run_phase(self):
class WriteMonitor (line 99) | class WriteMonitor(uvm_component):
method __init__ (line 104) | def __init__(self, *args, **kwargs):
method build_phase (line 109) | def build_phase(self):
method run_phase (line 112) | async def run_phase(self):
class ReadMonitor (line 124) | class ReadMonitor(uvm_component):
method __init__ (line 129) | def __init__(self, *args, **kwargs):
method build_phase (line 134) | def build_phase(self):
method run_phase (line 137) | async def run_phase(self):
class Scoreboard (line 149) | class Scoreboard(uvm_component):
method __init__ (line 154) | def __init__(self, name, parent):
method build_phase (line 159) | def build_phase(self):
method connect_phase (line 165) | def connect_phase(self):
method check_phase (line 169) | def check_phase(self):
method final_phase (line 198) | def final_phase(self):
class BaseEnv (line 207) | class BaseEnv(uvm_env):
method build_phase (line 212) | def build_phase(self):
method connect_phase (line 230) | def connect_phase(self):
class BaseTest (line 240) | class BaseTest(uvm_test):
method __init__ (line 245) | def __init__(self, name, parent, env_class=BaseEnv):
method build_phase (line 254) | def build_phase(self):
method start_clock (line 257) | def start_clock(self, name):
method do_reset (line 263) | async def do_reset(self):
method run_phase (line 269) | async def run_phase(self):
method run (line 289) | async def run(self):
FILE: verification/test_debug/test_debug.py
class TestDebug (line 8) | class TestDebug():
method test_debug (line 9) | def test_debug(self):
FILE: verification/top/test_pyuvm/conftest.py
function type_checker_cov (line 3) | def type_checker_cov(value):
function type_checker_sim (line 9) | def type_checker_sim(value):
function pytest_addoption (line 15) | def pytest_addoption(parser):
function coverage_opt (line 27) | def coverage_opt(request):
function sim_opt (line 31) | def sim_opt(request):
function conf_params (line 35) | def conf_params(request):
FILE: verification/top/test_pyuvm/test_irq/irq_utils.py
function get_int (line 11) | def get_int(signal):
class IrqBfm (line 19) | class IrqBfm(metaclass=utility_classes.Singleton):
method __init__ (line 37) | def __init__(self):
method send_interrupt_source (line 47) | async def send_interrupt_source(self, ints):
method get_interrupt_source (line 50) | async def get_interrupt_source(self):
method get_trace_interrupt (line 54) | async def get_trace_interrupt(self):
method reset (line 58) | async def reset(self):
method interrupt_driver_bfm (line 66) | async def interrupt_driver_bfm(self):
method interrupt_source_bfm (line 82) | async def interrupt_source_bfm(self):
method interrupt_trace_bfm (line 93) | async def interrupt_trace_bfm(self):
method start_bfm (line 99) | def start_bfm(self):
FILE: verification/top/test_pyuvm/test_irq/irq_uvm.py
class IrqRandomSeq (line 10) | class IrqRandomSeq(uvm_sequence):
method body (line 11) | async def body(self):
class vIrqSeq (line 17) | class vIrqSeq(uvm_sequence):
method body (line 18) | async def body(self):
class IrqTriggerSeqItem (line 26) | class IrqTriggerSeqItem(uvm_sequence_item):
method __init__ (line 27) | def __init__(self, name, nmi, soft, timer, ext):
method __eq__ (line 34) | def __eq__(self, other):
method __str__ (line 38) | def __str__(self):
method randomize (line 41) | def randomize(self):
class IrqMonitor (line 48) | class IrqMonitor(uvm_monitor):
method __init__ (line 49) | def __init__(self, name, parent, method_name):
method build_phase (line 53) | def build_phase(self):
method run_phase (line 58) | async def run_phase(self):
class Scoreboard (line 65) | class Scoreboard(uvm_component):
method build_phase (line 66) | def build_phase(self):
method connect_phase (line 75) | def connect_phase(self):
method check_phase (line 79) | def check_phase(self):
class IrqDriver (line 88) | class IrqDriver(uvm_driver):
method build_phase (line 89) | def build_phase(self):
method start_of_simulation_phase (line 92) | def start_of_simulation_phase(self):
method initialize_tb (line 95) | async def initialize_tb(self):
method run_phase (line 99) | async def run_phase(self):
class IrqAgent (line 108) | class IrqAgent(uvm_agent):
method build_phase (line 109) | def build_phase(self):
method connect_phase (line 115) | def connect_phase(self):
class VeerEl2Env (line 119) | class VeerEl2Env(uvm_env):
method build_phase (line 120) | def build_phase(self):
method connect_phase (line 124) | def connect_phase(self):
FILE: verification/top/test_pyuvm/test_irq/test_irq.py
class BaseTest (line 11) | class BaseTest(uvm_test):
method build_phase (line 12) | def build_phase(self):
method end_of_elaboration_phase (line 16) | def end_of_elaboration_phase(self):
method run_phase (line 19) | async def run_phase(self):
FILE: verification/top/test_pyuvm/test_pyuvm.py
class TestPyUVM (line 6) | class TestPyUVM():
method test_pyuvm (line 9) | def test_pyuvm(self, UVM_TEST, coverage_opt, sim_opt, conf_params):
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"path": "design/el2_veer.sv",
"chars": 64185,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "design/el2_veer_lockstep.sv",
"chars": 66956,
"preview": "// Copyright 2024 Antmicro <www.antmicro.com>\n//\n// SPDX-License-Identifier: Apache-2.0\n\nmodule el2_veer_lockstep\n impo"
},
{
"path": "design/el2_veer_wrapper.sv",
"chars": 42085,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n// Copyright (c)"
},
{
"path": "design/exu/el2_exu.sv",
"chars": 23225,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "design/exu/el2_exu_alu_ctl.sv",
"chars": 21421,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "design/exu/el2_exu_div_ctl.sv",
"chars": 104541,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "design/exu/el2_exu_mul_ctl.sv",
"chars": 31111,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "design/flist",
"chars": 1742,
"preview": "$RV_ROOT/design/el2_veer_wrapper.sv\n$RV_ROOT/design/el2_veer_lockstep.sv\n$RV_ROOT/design/el2_mem.sv\n$RV_ROOT/design/el2_"
},
{
"path": "design/flist.formal",
"chars": 2353,
"preview": "#-*-dotf-*-\n\n$RV_ROOT/design/include/el2_def.sv\n\n+incdir+$RV_ROOT/design/lib\n+incdir+$RV_ROOT/design/include\n+incdir+$RV"
},
{
"path": "design/flist.lint",
"chars": 1842,
"preview": "+libext+.v+.sv\n+define+RV_OPENSOURCE\n+incdir+$RV_ROOT/design/include\n+incdir+$RV_ROOT/design/lib\n+incdir+$RV_ROOT/design"
},
{
"path": "design/flist.questa",
"chars": 2271,
"preview": "#-*-dotf-*-\n\n# $RV_ROOT/workspace/work/snapshots/default/common_defines.vh\n# $RV_ROOT/configs/snapshots/default/common_d"
},
{
"path": "design/ifu/el2_ifu.sv",
"chars": 20296,
"preview": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2."
},
{
"path": "design/ifu/el2_ifu_aln_ctl.sv",
"chars": 36317,
"preview": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2."
},
{
"path": "design/ifu/el2_ifu_bp_ctl.sv",
"chars": 45535,
"preview": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2."
},
{
"path": "design/ifu/el2_ifu_compress_ctl.sv",
"chars": 11667,
"preview": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2."
},
{
"path": "design/ifu/el2_ifu_ic_mem.sv",
"chars": 79031,
"preview": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2."
},
{
"path": "design/ifu/el2_ifu_iccm_mem.sv",
"chars": 13976,
"preview": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2."
},
{
"path": "design/ifu/el2_ifu_ifc_ctl.sv",
"chars": 9943,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "design/ifu/el2_ifu_mem_ctl.sv",
"chars": 100616,
"preview": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2."
},
{
"path": "design/ifu/el2_ifu_tb_memread.sv",
"chars": 2324,
"preview": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2."
},
{
"path": "design/include/el2_dec_csr_equ_m.svh",
"chars": 19862,
"preview": "logic csr_misa;\nlogic csr_mvendorid;\nlogic csr_marchid;\nlogic csr_mimpid;\nlogic csr_mhartid;\nlogic csr_mstatus;\nlogic cs"
},
{
"path": "design/include/el2_dec_csr_equ_mu.svh",
"chars": 24138,
"preview": "logic csr_misa;\nlogic csr_mvendorid;\nlogic csr_marchid;\nlogic csr_mimpid;\nlogic csr_mhartid;\nlogic csr_mstatus;\nlogic cs"
},
{
"path": "design/include/el2_def.sv",
"chars": 15029,
"preview": "// performance monitor stuff\n//`ifndef EL2_DEF_SV\n//`define EL2_DEF_SV\npackage el2_pkg;\n\n`include \"el2_pdef.vh\"\n\ntypedef"
},
{
"path": "design/lib/ahb_to_axi4.sv",
"chars": 18113,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "design/lib/axi4_to_ahb.sv",
"chars": 26851,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "design/lib/beh_lib.sv",
"chars": 26467,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "design/lib/el2_lib.sv",
"chars": 2706,
"preview": "module el2_btb_tag_hash\nimport el2_pkg::*;\n#(\n`include \"el2_param.vh\"\n ) (\n input logic [pt.BTB_AD"
},
{
"path": "design/lib/el2_mem_if.sv",
"chars": 6009,
"preview": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2."
},
{
"path": "design/lib/el2_regfile_if.sv",
"chars": 2325,
"preview": "//********************************************************************************\n// SPDX-License-Identifier: Apache-2."
},
{
"path": "design/lib/mem_lib.sv",
"chars": 7181,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or it's affiliates.\n//\n// Licensed "
},
{
"path": "design/lsu/el2_lsu.sv",
"chars": 24033,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "design/lsu/el2_lsu_addrcheck.sv",
"chars": 14607,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "design/lsu/el2_lsu_bus_buffer.sv",
"chars": 70124,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "design/lsu/el2_lsu_bus_intf.sv",
"chars": 21997,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "design/lsu/el2_lsu_clkdomain.sv",
"chars": 7247,
"preview": "// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed under the Apache License, Version 2.0 (t"
},
{
"path": "design/lsu/el2_lsu_dccm_ctl.sv",
"chars": 32054,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "design/lsu/el2_lsu_dccm_mem.sv",
"chars": 7629,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n// Copyright (c)"
},
{
"path": "design/lsu/el2_lsu_ecc.sv",
"chars": 14782,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "design/lsu/el2_lsu_lsc_ctl.sv",
"chars": 20545,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "design/lsu/el2_lsu_stbuf.sv",
"chars": 21391,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "design/lsu/el2_lsu_trigger.sv",
"chars": 2875,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2020 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "docs/Makefile",
"chars": 341,
"preview": "SPHINXOPTS ?=\nSPHINXBUILD ?= sphinx-build\nSOURCEDIR = source\nBUILDDIR = build\n\n# Catch-all target: route a"
},
{
"path": "docs/dashboard-styles/gcov.css",
"chars": 11874,
"preview": "/* All views: initial background and text color */\n@import url('https://fonts.googleapis.com/css2?family=Roboto:wght@400"
},
{
"path": "docs/dashboard-styles/main.css",
"chars": 352,
"preview": "[data-md-color-scheme=\"slate\"] {\n --md-hue: 218;\n --md-default-bg-color: hsla(var(--md-hue), 22%, 7%, 1);\n}\n\n[data-md-"
},
{
"path": "docs/requirements.txt",
"chars": 86,
"preview": "Sphinx>=8.0.2,<9\r\nhttps://github.com/antmicro/antmicro-sphinx-utils/archive/main.zip\r\n"
},
{
"path": "docs/source/adaptations.md",
"chars": 8296,
"preview": "# Standard RISC-V CSRs with Core-Specific Adaptations\n\nA summary of standard RISC-V control/status registers in CSR spac"
},
{
"path": "docs/source/build-args.md",
"chars": 3976,
"preview": "# Build Arguments\n\n## Memory Protection Build Arguments\n\n### Memory Protection Build Argument Rules\n\nThe rules for valid"
},
{
"path": "docs/source/cache.md",
"chars": 19358,
"preview": "# Cache Control\n\nThis chapter describes the features to control the VeeR EL2 core's instruction cache (I-cache).\n\n## Fea"
},
{
"path": "docs/source/clocks.md",
"chars": 8761,
"preview": "# Clock And Reset\n\nThis chapter describes clocking and reset signals used by the VeeR EL2 core complex.\n\n## Features\n\nTh"
},
{
"path": "docs/source/complex-ports.md",
"chars": 16346,
"preview": "# Complex Port List\n\n{numref}`tab-core-complex-signals` lists the core complex signals.\nNot all signals are present in a"
},
{
"path": "docs/source/conf.py",
"chars": 1504,
"preview": "from datetime import datetime\n\nfrom antmicro_sphinx_utils.defaults import (\n extensions as default_extensions,\n my"
},
{
"path": "docs/source/core-control.md",
"chars": 4937,
"preview": "# Low-Level Core Control\n\nThis chapter describes some low-level core control registers.\n\n## Control/Status Registers\n\nA "
},
{
"path": "docs/source/csrs.md",
"chars": 9186,
"preview": "# CSR Address Map\n\n## Standard RISC-V CSRs\n\n{numref}`tab-veer-el2-core-specific-std-rv-machine-information-csrs` lists t"
},
{
"path": "docs/source/debugging.md",
"chars": 48234,
"preview": "# Debug Support\n\nThe VeeR EL2 core conforms to the \"RISC-V Debug Specification 0.13.2, with JTAG DTM\" document [[3]](int"
},
{
"path": "docs/source/dual-core-lock-step.md",
"chars": 27530,
"preview": "# Dual-Core Lockstep (DCLS)\n\nThis chapter describes the proposed Dual-Core Lockstep functionality and its future impleme"
},
{
"path": "docs/source/errata.md",
"chars": 1389,
"preview": "# Errata\n\n## Back-To-Back Write Transactions Not Supported on AHB-Lite Bus\n\n* **Description**:\nThe AHB-Lite bus interfac"
},
{
"path": "docs/source/error-protection.md",
"chars": 20029,
"preview": "# Memory Error Protection\n## General Description\n### Parity\n\nParity is a simple and relatively cheap protection scheme g"
},
{
"path": "docs/source/index.md",
"chars": 342,
"preview": "# {{project}}\n\n```{toctree}\n:maxdepth: 2\n:numbered:\n\nintro\noverview\nmemory-map\nerror-protection\ndual-core-lock-step\ntime"
},
{
"path": "docs/source/interrupt-priority.md",
"chars": 1137,
"preview": "# Interrupt Priorities\n\n{numref}`tab-veer-el2-platform-specific-and-std-risc-v-interrupt-priorities` summarizes the VeeR"
},
{
"path": "docs/source/interrupts.md",
"chars": 53199,
"preview": "# External Interrupts\n\nSee *Chapter 7, Platform-Level Interrupt Controller (PLIC)* in [[2 (PLIC)]](intro.md#ref-2-plic) "
},
{
"path": "docs/source/intro.md",
"chars": 11880,
"preview": "# RISC-V VeeR EL2 Programmer's Reference Manual\n\n**Revision:** 2.0 January 14, 2025\n\n![CHIPS Alliance logo](img/logo.pn"
},
{
"path": "docs/source/memory-map.md",
"chars": 55540,
"preview": "# Memory Map\n\nThis chapter describes the memory map as well as the various memories and their properties of the VeeR EL2"
},
{
"path": "docs/source/overview.md",
"chars": 6121,
"preview": "# Core Overview\n\nThis chapter provides a high-level overview of the VeeR EL2 core and core complex. VeeR EL2 is a machin"
},
{
"path": "docs/source/performance.md",
"chars": 9438,
"preview": "# Performance Monitoring\n\nThis chapter describes the performance monitoring features of the VeeR EL2 core.\n\n## Features\n"
},
{
"path": "docs/source/physical-memory-protection.md",
"chars": 7363,
"preview": "# Physical Memory Protection\n\nThe Physical Memory Protection unit implemented in the VeeR EL2 Core is compliant with \"Se"
},
{
"path": "docs/source/power.md",
"chars": 34328,
"preview": "# Power Management and Multi-Core Debug Control\n\nThis chapter specifies the power management and multi-core debug contro"
},
{
"path": "docs/source/simulation-debugging.md",
"chars": 3015,
"preview": "# Interactive Debugging in Simulation\n\nIt is possible to perform a debugging session through a virtual JTAG interface wi"
},
{
"path": "docs/source/tests.md",
"chars": 3394,
"preview": "# Compliance Test Suite Failures\n\n## *I-MISALIGN_LDST-01*\n\n* **Test Location**: [https://github.com/riscv/riscv-complian"
},
{
"path": "docs/source/timers.md",
"chars": 8275,
"preview": "# Internal Timers\n\nThis chapter describes the internal timer feature of the VeeR EL2 core.\n\n## Features\n\nThe VeeR EL2's "
},
{
"path": "docs/source/tock.md",
"chars": 3174,
"preview": "# Running Tock OS\n\nThis chapter describes the steps necessary to build a [Tock OS](https://github.com/tock/tock) applica"
},
{
"path": "docs/source/user-mode.md",
"chars": 3613,
"preview": "# User Mode\n\nOriginally, VeeR EL2 only implemented machine mode, and user mode support was added for the Caliptra projec"
},
{
"path": "docs/source/verification.md",
"chars": 16462,
"preview": "# Verification\n\nThis chapter documents verification of the VeeR EL2 Core and coverage data collection, including RTL-lev"
},
{
"path": "docs/update_styles.sh",
"chars": 2024,
"preview": "#!/bin/bash\n\nSELF_DIR=\"$(dirname $(readlink -f ${BASH_SOURCE[0]}))\"\ncheck_args_count(){\n # Check argument count funct"
},
{
"path": "release-notes.md",
"chars": 3117,
"preview": "# Release notes\n\n## 2.0\n\n* Extended the core with support for RISC-V User privilege level\n* Extended the core with suppo"
},
{
"path": "requirements.txt",
"chars": 545,
"preview": "# Build and Workflow Tools\nnox\nmeson\n\n# Linters\nisort\nblack\nflake8\n\n# Documentation\nSphinx>=8.0.2,<9\n# Sphinx utilities\n"
},
{
"path": "testbench/ahb_lite_2to1_mux.sv",
"chars": 11764,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2024 Antmicro <www.antmicro.com>\n//\n// Licensed under the Apache Lic"
},
{
"path": "testbench/ahb_lsu_dma_bridge.sv",
"chars": 5103,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2024 Antmicro <www.antmicro.com>\n//\n// Licensed under the Apache Lic"
},
{
"path": "testbench/ahb_sif.sv",
"chars": 6860,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2019 Western Digital Corporation or its affiliates.\n// Copyright 202"
},
{
"path": "testbench/asm/bitmanip.s",
"chars": 4724,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2024 Antmicro <www.antmicro.com>\n//\n// Licensed under the Apache Lic"
},
{
"path": "testbench/asm/cmark.c",
"chars": 76838,
"preview": "#include \"defines.h\"\n\n#define ITERATIONS 1\n\n\n/*\nAuthor : Shay Gal-On, EEMBC\n\nThis file is part of EEMBC(R) and CoreMark"
},
{
"path": "testbench/asm/cmark.mki",
"chars": 127,
"preview": "TEST_CFLAGS = -finline-limit=400 -mbranch-cost=1 -Ofast -fno-code-hoisting -funroll-all-loops\nOFILES = crt0.o printf.o c"
},
{
"path": "testbench/asm/cmark_iccm.ld",
"chars": 470,
"preview": "OUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n . = 0x80000000 ;\n .text : { crt0.o (.text*) }\n _end = .;\n . = 0xe"
},
{
"path": "testbench/asm/cmark_iccm.mki",
"chars": 73,
"preview": "TEST_CFLAGS = -g -O3 -funroll-all-loops\nOFILES = crt0.o printf.o cmark.o\n"
},
{
"path": "testbench/asm/common.s",
"chars": 1515,
"preview": "#include \"defines.h\"\n#include \"tb.h\"\n\n.section .text\n.global _start\n_start:\n // Clear minstret\n csrw minstret, zer"
},
{
"path": "testbench/asm/crt0.s",
"chars": 1437,
"preview": "# SPDX-License-Identifier: Apache-2.0\n# Copyright 2020 Western Digital Corporation or its affiliates.\n#\n# Licensed under"
},
{
"path": "testbench/asm/dbus_nonblocking_load_error.s",
"chars": 343,
"preview": "#include \"common.s\"\n\ndbus_nonblocking_load_error:\n li x4, 0xF0000001\n li x5, 0x0\n // trigger bus fault at next "
},
{
"path": "testbench/asm/dbus_store_error.s",
"chars": 413,
"preview": "#include \"common.s\"\n\ndbus_store_error:\n li x4, 0xF0000000\n li x5, 0x0\n // address of some data that resides in "
},
{
"path": "testbench/asm/dside_access_across_region_boundary.s",
"chars": 472,
"preview": "#include \"common.s\"\n\ndside_load_across_region_boundary:\n li x4, 0x4\n li x5, 0x2\n // load from across region bou"
},
{
"path": "testbench/asm/dside_access_region_prediction_error.s",
"chars": 583,
"preview": "#include \"common.s\"\n\ndside_load_region_prediction_error:\n li x4, 0x5\n li x5, 0x5\n // We take a large address th"
},
{
"path": "testbench/asm/dside_core_local_access_unmapped_address_error.s",
"chars": 609,
"preview": "#include \"common.s\"\n\ndside_core_local_load_unmapped_address_error:\n li x4, 0x5\n li x5, 0x2\n // load from DCCM u"
},
{
"path": "testbench/asm/dside_pic_access_error.s",
"chars": 467,
"preview": "#include \"common.s\"\n\ndside_pic_load_access_error:\n li x4, 0x5\n li x5, 0x6\n // perform not word-sized load from "
},
{
"path": "testbench/asm/dside_size_misaligned_access_to_non_idempotent_address.s",
"chars": 732,
"preview": "#include \"common.s\"\n\ndside_size_misaligned_load_to_non_idempotent_address:\n li x4, 0x4\n li x5, 0x1\n // load fro"
},
{
"path": "testbench/asm/ebreak_ecall.s",
"chars": 291,
"preview": "#include \"common.s\"\n\nbreakpoint_ebreak:\n li x4, 0x3\n li x5, 0x2\n ebreak\n j fail_if_not_serviced\n\nenvironment"
},
{
"path": "testbench/asm/hello_world.ld",
"chars": 253,
"preview": "OUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n . = 0x80000000;\n .text : { *(.text*) }\n _end = .;\n .data : { "
},
{
"path": "testbench/asm/hello_world.s",
"chars": 1619,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2019 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "testbench/asm/hello_world_dccm.ld",
"chars": 335,
"preview": "OUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n . = 0x80000000;\n .text : { *(.text*) }\n _end = .;\n . = 0xd0580000"
},
{
"path": "testbench/asm/hello_world_iccm.ld",
"chars": 284,
"preview": "OUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n . = 0x80000000;\n .text : { *(.text*) }\n .data : { *(.*data) *(."
},
{
"path": "testbench/asm/hello_world_iccm.s",
"chars": 1968,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2019 Western Digital Corporation or its affiliates.\n//\n// Licensed u"
},
{
"path": "testbench/asm/icache.ld",
"chars": 129,
"preview": "OUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n .text : { *(.text*) }\n . = 0x10000;\n .data : { *(.*data) *(.rod"
},
{
"path": "testbench/asm/icache.s",
"chars": 1380,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2024 Antmicro <www.antmicro.com>\n//\n// Licensed under the Apache Lic"
},
{
"path": "testbench/asm/illegal_instruction.s",
"chars": 160,
"preview": "#include \"common.s\"\n\nillegal_instruction:\n li x4, 0x2\n li x5, 0x0\n .word 0\n j fail_if_not_serviced\n\nmain:\n "
},
{
"path": "testbench/asm/infinite_loop.ld",
"chars": 281,
"preview": "OUTPUT_ARCH( \"riscv\" )\nENTRY(_start)\n\nSECTIONS {\n .text : { *(.text*) }\n . = 0x10000;\n .data : { *(.*data) *(.rod"
},
{
"path": "testbench/asm/infinite_loop.s",
"chars": 1310,
"preview": "// SPDX-License-Identifier: Apache-2.0\n// Copyright 2019 Western Digital Corporation or its affiliates.\n// Copyright 202"
},
{
"path": "testbench/asm/internal_timer_ints.s",
"chars": 900,
"preview": "#include \"common.s\"\n\nmachine_internal_timer0_local_interrupt:\n li x4, 0x8000001d\n li x5, 0x0\n csrw 0x7D4, 0x0 /"
},
{
"path": "testbench/asm/iside_core_local_unmapped_address_error.s",
"chars": 286,
"preview": "#include \"common.s\"\n\niside_core_local_unmapped_address_error:\n li x4, 0x1\n li x5, 0x2\n // jump to address that'"
},
{
"path": "testbench/asm/iside_fetch_precise_bus_error.s",
"chars": 410,
"preview": "#include \"common.s\"\n\niside_fetch_precise_bus_error:\n li x4, 0x1\n li x5, 0x9\n li x2, TRIGGER_IBUS_FAULT\n li x"
},
{
"path": "testbench/asm/lsu_trigger_hit.s",
"chars": 362,
"preview": "#include \"common.s\"\n\nlsu_trigger_hit:\n la x4, 0x3\n la x5, 0x1\n // set up address to trigger on\n li x2, 0xdea"
},
{
"path": "testbench/asm/machine_external_ints.s",
"chars": 616,
"preview": "#include \"common.s\"\n\nmachine_software_interrupt:\n la x4, 0x80000003\n li x5, 0x0\n // enable software interrupt\n "
}
]
// ... and 403 more files (download for full content)
About this extraction
This page contains the full source code of the chipsalliance/Cores-SweRV-EL2 GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 603 files (5.2 MB), approximately 1.4M tokens, and a symbol index with 1940 extracted functions, classes, methods, constants, and types. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.
Extracted by GitExtract — free GitHub repo to text converter for AI. Built by Nikandr Surkov.