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Repository: pigirons/cpufp
Branch: master
Commit: 93e165ea3cd2
Files: 78
Total size: 332.3 KB
Directory structure:
gitextract_2p1llcmt/
├── .gitignore
├── LICENSE
├── README.md
├── arm64/
│ ├── asm/
│ │ ├── _ASIMD_.S
│ │ ├── _ASIMD_DP_.S
│ │ ├── _ASIMD_HP_.S
│ │ ├── _BF16_.S
│ │ └── _I8MM_.S
│ ├── cpufp.cpp
│ └── cpuid.c
├── benchmark_result/
│ ├── arm64/
│ │ ├── AWS_Graviton_3E.md
│ │ ├── Apple_Silicon_M2_Max.md
│ │ ├── Apple_Silicon_M4_Max.md
│ │ ├── Broadcom_BCM2711.md
│ │ ├── Broadcom_BCM2712.md
│ │ ├── CIX_P1_CD8180.md
│ │ ├── HUAWEI_Kunpeng_920_7260.md
│ │ ├── HUAWEI_Kunpeng_D920_2249K.md
│ │ ├── Phytium_D2000.md
│ │ ├── Qualcomm_Snapdragon_X_Elite_X1E80100.md
│ │ ├── RockChip_RK3399.md
│ │ └── RockChip_RK3588.md
│ ├── e2k/
│ │ ├── Elbrus_4C.md
│ │ ├── Elbrus_8C.md
│ │ └── Elbrus_8C2.md
│ ├── loongarch64/
│ │ ├── Loongson_3A5000M.md
│ │ ├── Loongson_3A6000.md
│ │ └── Loongson_3C5000.md
│ ├── riscv64/
│ │ ├── Kendryte_K230.md
│ │ └── SpacemiT_K1.md
│ └── x64/
│ ├── AMD_Ryzen7_8845HS.md
│ ├── AMD_Ryzen7_9700X.md
│ ├── AMD_Ryzen9_6900HX.md
│ ├── Intel_Core_i3_8121U.md
│ ├── Intel_Core_i5_1340P.md
│ ├── Intel_N150.md
│ ├── Intel_Ultra7_255H.md
│ ├── Intel_Xeon_Gold_6455B.md
│ ├── Intel_Xeon_W9_3495X.md
│ └── ZHAOXIN_KX_6640MA.md
├── build_arm64.sh
├── build_e2k.sh
├── build_loongarch64.sh
├── build_riscv64.sh
├── build_x64.sh
├── clean.sh
├── common/
│ ├── smtl.cpp
│ ├── smtl.hpp
│ ├── table.cpp
│ └── table.hpp
├── e2k/
│ ├── asm.S
│ └── cpufp.cpp
├── loongarch64/
│ ├── asm/
│ │ ├── _FP_DP_.S
│ │ ├── _FP_SP_.S
│ │ ├── _LASX_.S
│ │ └── _LSX_.S
│ ├── cpufp.cpp
│ └── cpuid.c
├── riscv64/
│ ├── asm/
│ │ ├── _IME_.S
│ │ └── _VECTOR_.S
│ ├── cpufp.cpp
│ └── cpuid.c
└── x64/
├── asm/
│ ├── _AMX_BF16_.S
│ ├── _AMX_FP16_.S
│ ├── _AMX_INT8_.S
│ ├── _AVX512F_.S
│ ├── _AVX512_BF16_.S
│ ├── _AVX512_FP16_.S
│ ├── _AVX512_VNNI_.S
│ ├── _AVX_.S
│ ├── _AVX_VNNI_.S
│ ├── _AVX_VNNI_INT16_.S
│ ├── _AVX_VNNI_INT8_.S
│ ├── _FMA_.S
│ ├── _SSE2_.S
│ └── _SSE_.S
├── cpufp.cpp
└── cpuid.c
================================================
FILE CONTENTS
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FILE: .gitignore
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build_dir/
cpufp
================================================
FILE: LICENSE
================================================
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================================================
FILE: README.md
================================================
# cpufp
This is a cpu tool for benchmarking the peak performance of floating-points and AI ISAs.
It can automatically sense the local SIMD|DSA ISAs while compiling.
## Support OS and ISA
| Arch |Linux| MacOS| Windows|
|:--------------|:---:|:----:|:------:|
| arm64 | yes | yes | no |
| e2k | yes | no | no |
| loongarch64 | yes | no | no |
| riscv64 | yes | no | no |
| x86-64 | yes | no | no |
## Support x86-64 SIMD|DSA ISA
|Arch|ISA|Feature|Data Type|Description|
| ------------ | ------------ | ------------ | ------------ | ------------ |
|SIMD|SSE|Vector|fp32|Before Sandy Bridge|
|SIMD|SSE2|Vector|fp64|Before Sandy Bridge|
|SIMD|AVX|Vector|fp32/fp64|From Sandy Bridge|
|SIMD|FMA|Vector|fp32/fp64|From Haswell/Zen|
|SIMD|AVX512f|Vector|fp32/fp64|From Skylake X/Zen4|
|SIMD|AVX512_VNNI|Vector|int8/int16|From IceLake|
|SIMD|AVX_VNNI|Vector|int8/int16|From Alder Lake|
|SIMD|AVX512_FP16|Vector|fp16|From Intel Sapphire Rapids|
|SIMD|AVX512_BF16|Vector|bf16|From AMD Zen4|
|SIMD|AVX_VNNI_INT8|Vector|int8|From Intel Lunar Lake|
|SIMD|AVX_VNNI_INT16|Vector|int16|From Intel Lunar Lake|
|DSA|AMX_INT8|Matrix|int8|From Intel Sapphire Rapids|
|DSA|AMX_BF16|Matrix|bf16|From Intel Sapphire Rapids|
|DSA|AMX_FP16|Matrix|fp16|From Intel Granite Rapids|
## Support arm64 SIMD ISA
|Arch|ISA|Feature|Data Type|Description|
| ------------ | ------------ | ------------ | ------------ | ------------ |
|SIMD|asimd|Vector|fp32/fp64|From Cortex-A57/A53|
|SIMD|asimd_hp|Vector|fp16|From Cortex-A75/A55|
|SIMD|asimd_dp|Vector|int8|From Cortex-A75/A55|
|SIMD|bf16|Matrix|bf16|From Cortex-X2/A710/A510|
|SIMD|i8mm|Matrix|int8|From Cortex-X2/A710/A510|
## Support riscv64 VECTOR ISA
|Arch|ISA|Feature|Data Type|Description|
| ------------ | ------------ | ------------ | ------------ | ------------ |
|SIMD|V|Vector|fp16/fp32/fp64|From RISC-V "V" vector extension. Version 1.0|
|DSA|ime|Matrix|int8|From SpacemiT-X60|
NOTE: ime is a SpacemiT custom vendor extension.
## Support loongarch64 ISA
|Arch|ISA|Feature|Data Type|Description|
| ------------ | ------------ | ------------ | ------------ | ------------ |
|SIMD|LASX|Vector|fp32/fp64|From Loongson 3A5000|
|SIMD|LSX|Vector|fp32/fp64|From Loongson 3A5000|
|Scalar|FP|Scalar|fp32/fp64|From Loongson 3A5000|
## Support e2k ISA
| Arch | ISA |Feature| Vector Width | Data Type |Description
|:-----|:------|:-----:|:------------:|----------:|:----------
| SIMD | v6 | Vector| 128 | fp32/fp64 | FMA
| SIMD | v5 | Vector| 128 | fp32/fp64 | Combined operations
|Scalar| v1-v4 | Scalar| | fp64 | Combined operations
| SIMD | v1-v4 | Vector| 64 | fp32 | Combined operations
### Combined operations
E2K has support for instructions that perform two independant operations.
It is like FMA, but with additional rounding as these operations is independant.
#### Example `fmul_addd`
```
fmul_addd src1, src2, src3, dst
```
##### Description
Multiply double-precision (64-bit) floating-point values from `src1` and `src2`,
and add the intermediate result to value from `src3`. Store the result in `dst`.
##### Operation
```
dst[63:0] := src3[63:0] + src1[63:0] * src2[63:0]
```
##### Latency and Throughput
| Architecture | Latency | Throughput (CPI) | ALC
|:--------------|:-------:|:----------------:|:---:
| elbrus-v4 | 8 | 0.16 | `012345`
| elbrus-v1 | 8 | 0.25 | `01-34-`
* ALC (Arithmetic Logic Complex/Channel) is an execution port for RISC-like instructions
## How to build
build x64 version:
`./build_x64.sh`
build arm64 version:
`./build_arm64.sh`
build riscv64 version:
`./build_riscv64.sh`
build loongarch64 version:
`./build_loongarch64.sh`
build e2k version:
`./build_e2k.sh`
clean:
`./clean.sh`
## How to benchmark
`./cpufp --thread_pool=[xxx] --idle_time=yyy`
--thread_pool: [xxx] is the list of cpu thread to benchmarking, from setting affinities. Please reference the result of lstopo command. For example, [0,3,5-8,13-15].
--idle_time: the interval time(sec) between any two adjacent benchmarks, default is 0.
## Benchmark results
<table>
<tr>
<td>Arch</td>
<td>Benchmark</td>
</tr>
<tr>
<td rowspan="10">x86-64</td>
<td><a href="benchmark_result/x64/AMD_Ryzen7_9700X.md">AMD Ryzen7 9700X</a></td>
</tr>
<tr>
<td><a href="benchmark_result/x64/AMD_Ryzen7_8845HS.md">AMD Ryzen7 8845HS</a></td>
</tr>
<tr>
<td><a href="benchmark_result/x64/AMD_Ryzen9_6900HX.md">AMD Ryzen9 6900HX</a></td>
</tr>
<tr>
<td><a href="benchmark_result/x64/Intel_Xeon_Gold_6455B.md">Intel Xeon Gold 6455B</a></td>
</tr>
<tr>
<td><a href="benchmark_result/x64/Intel_Xeon_W9_3495X.md">Intel Xeon W9-3495X</a></td>
</tr>
<tr>
<td><a href="benchmark_result/x64/Intel_Core_i5_1340P.md">Intel Core i5 1340P</a></td>
</tr>
<tr>
<td><a href="benchmark_result/x64/Intel_Ultra7_255H.md">Intel Ultra7 255H</a></td>
</tr>
<tr>
<td><a href="benchmark_result/x64/Intel_Core_i3_8121U.md">Intel Core i3_8121U</a></td>
</tr>
<tr>
<td><a href="benchmark_result/x64/Intel_N150.md">Intel N150</a></td>
</tr>
<tr>
<td><a href="benchmark_result/x64/ZHAOXIN_KX_6640MA.md">ZHAOXIN KX-6640MA</a></td>
</tr>
<tr>
<td rowspan="12">arm64</td>
<td><a href="benchmark_result/arm64/Apple_Silicon_M4_Max.md">Apple Silicon M4 Max</a></td>
</tr>
<tr>
<td><a href="benchmark_result/arm64/Apple_Silicon_M2_Max.md">Apple Silicon M2 Max</a></td>
</tr>
<tr>
<td><a href="benchmark_result/arm64/Qualcomm_Snapdragon_X_Elite_X1E80100.md">Qualcomm Snapdragon X Elite X1E80100</a></td>
</tr>
<tr>
<td><a href="benchmark_result/arm64/AWS_Graviton_3E.md">AWS Graviton 3E</a></td>
</tr>
<tr>
<td><a href="benchmark_result/arm64/Broadcom_BCM2712.md">Broadcom BCM2712</a></td>
</tr>
<tr>
<td><a href="benchmark_result/arm64/Broadcom_BCM2711.md">Broadcom BCM2711</a></td>
</tr>
<tr>
<td><a href="benchmark_result/arm64/CIX_P1_CD8180.md">CIX P1 CD8180</a></td>
</tr>
<tr>
<td><a href="benchmark_result/arm64/HUAWEI_Kunpeng_920_7260.md">HUAWEI Kunpeng 920 7260</a></td>
</tr>
<tr>
<td><a href="benchmark_result/arm64/HUAWEI_Kunpeng_D920_2249K.md">HUAWEI Kunpeng D920 2249K</a></td>
</tr>
<tr>
<td><a href="benchmark_result/arm64/Phytium_D2000.md">Phytium D2000/8</a></td>
</tr>
<tr>
<td><a href="benchmark_result/arm64/RockChip_RK3588.md">RockChip RK3588</a></td>
</tr>
<tr>
<td><a href="benchmark_result/arm64/RockChip_RK3399.md">RockChip RK3399</a></td>
</tr>
<tr>
<td rowspan="2">riscv64</td>
<td><a href="benchmark_result/riscv64/SpacemiT_K1.md">SpacemiT K1</a></td>
</tr>
<tr>
<td><a href="benchmark_result/riscv64/Kendryte_K230.md">Kendryte K230</a></td>
</tr>
<tr>
<td rowspan="3">loongarch64</td>
<td><a href="benchmark_result/loongarch64/Loongson_3A6000.md">Loongson 3A6000</a></td>
</tr>
<tr>
<td><a href="benchmark_result/loongarch64/Loongson_3C5000.md">Loongson 3C5000</a></td>
</tr>
<tr>
<td><a href="benchmark_result/loongarch64/Loongson_3A5000M.md">Loongson 3A5000M</a></td>
</tr>
<tr>
<td rowspan="3">e2k</td>
<td><a href="benchmark_result/e2k/Elbrus_8C2.md">Elbrus 8C2</a></td>
</tr>
<tr>
<td><a href="benchmark_result/e2k/Elbrus_8C.md">Elbrus 8C</a></td>
</tr>
<tr>
<td><a href="benchmark_result/e2k/Elbrus_4C.md">Elbrus 4C</a></td>
</tr>
</table>
## Todo list
Add armv9(SVE, SVE2 & SME) Supports.
================================================
FILE: arm64/asm/_ASIMD_.S
================================================
.align 4
.macro preserve_caller_vec
stp d8, d9, [sp, #-16]!
stp d10, d11, [sp, #-16]!
stp d12, d13, [sp, #-16]!
stp d14, d15, [sp, #-16]!
.endm
.macro restore_caller_vec
ldp d14, d15, [sp], #16
ldp d12, d13, [sp], #16
ldp d10, d11, [sp], #16
ldp d8, d9, [sp], #16
.endm
#ifdef __APPLE__
.globl _asimd_fmla_vs_f32f32f32
_asimd_fmla_vs_f32f32f32:
#else
.globl asimd_fmla_vs_f32f32f32
asimd_fmla_vs_f32f32f32:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.fmla.vs.f32f32f32.L1:
fmla v8.4s, v0.4s, v1.s[0]
fmla v9.4s, v0.4s, v1.s[0]
fmla v10.4s, v0.4s, v1.s[0]
fmla v11.4s, v0.4s, v1.s[0]
fmla v12.4s, v0.4s, v1.s[0]
fmla v13.4s, v0.4s, v1.s[0]
fmla v14.4s, v0.4s, v1.s[0]
fmla v15.4s, v0.4s, v1.s[0]
fmla v16.4s, v0.4s, v1.s[0]
fmla v17.4s, v0.4s, v1.s[0]
fmla v18.4s, v0.4s, v1.s[0]
fmla v19.4s, v0.4s, v1.s[0]
subs x0, x0, #1
fmla v20.4s, v0.4s, v1.s[0]
fmla v21.4s, v0.4s, v1.s[0]
fmla v22.4s, v0.4s, v1.s[0]
fmla v23.4s, v0.4s, v1.s[0]
fmla v24.4s, v0.4s, v1.s[0]
fmla v25.4s, v0.4s, v1.s[0]
fmla v26.4s, v0.4s, v1.s[0]
fmla v27.4s, v0.4s, v1.s[0]
fmla v28.4s, v0.4s, v1.s[0]
fmla v29.4s, v0.4s, v1.s[0]
fmla v30.4s, v0.4s, v1.s[0]
fmla v31.4s, v0.4s, v1.s[0]
bne .asimd.fmla.vs.f32f32f32.L1
restore_caller_vec
ret
#ifdef __APPLE__
.globl _asimd_fmla_vv_f32f32f32
_asimd_fmla_vv_f32f32f32:
#else
.globl asimd_fmla_vv_f32f32f32
asimd_fmla_vv_f32f32f32:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.fmla.vv.f32f32f32.L1:
fmla v8.4s, v0.4s, v1.4s
fmla v9.4s, v0.4s, v1.4s
fmla v10.4s, v0.4s, v1.4s
fmla v11.4s, v0.4s, v1.4s
fmla v12.4s, v0.4s, v1.4s
fmla v13.4s, v0.4s, v1.4s
fmla v14.4s, v0.4s, v1.4s
fmla v15.4s, v0.4s, v1.4s
fmla v16.4s, v0.4s, v1.4s
fmla v17.4s, v0.4s, v1.4s
fmla v18.4s, v0.4s, v1.4s
fmla v19.4s, v0.4s, v1.4s
subs x0, x0, #1
fmla v20.4s, v0.4s, v1.4s
fmla v21.4s, v0.4s, v1.4s
fmla v22.4s, v0.4s, v1.4s
fmla v23.4s, v0.4s, v1.4s
fmla v24.4s, v0.4s, v1.4s
fmla v25.4s, v0.4s, v1.4s
fmla v26.4s, v0.4s, v1.4s
fmla v27.4s, v0.4s, v1.4s
fmla v28.4s, v0.4s, v1.4s
fmla v29.4s, v0.4s, v1.4s
fmla v30.4s, v0.4s, v1.4s
fmla v31.4s, v0.4s, v1.4s
bne .asimd.fmla.vv.f32f32f32.L1
restore_caller_vec
ret
#ifdef __APPLE__
.globl _asimd_fmla_vs_f64f64f64
_asimd_fmla_vs_f64f64f64:
#else
.globl asimd_fmla_vs_f64f64f64
asimd_fmla_vs_f64f64f64:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.fmla.vs.f64f64f64.L1:
fmla v8.2d, v0.2d, v1.d[0]
fmla v9.2d, v0.2d, v1.d[0]
fmla v10.2d, v0.2d, v1.d[0]
fmla v11.2d, v0.2d, v1.d[0]
fmla v12.2d, v0.2d, v1.d[0]
fmla v13.2d, v0.2d, v1.d[0]
fmla v14.2d, v0.2d, v1.d[0]
fmla v15.2d, v0.2d, v1.d[0]
fmla v16.2d, v0.2d, v1.d[0]
fmla v17.2d, v0.2d, v1.d[0]
fmla v18.2d, v0.2d, v1.d[0]
fmla v19.2d, v0.2d, v1.d[0]
subs x0, x0, #1
fmla v20.2d, v0.2d, v1.d[0]
fmla v21.2d, v0.2d, v1.d[0]
fmla v22.2d, v0.2d, v1.d[0]
fmla v23.2d, v0.2d, v1.d[0]
fmla v24.2d, v0.2d, v1.d[0]
fmla v25.2d, v0.2d, v1.d[0]
fmla v26.2d, v0.2d, v1.d[0]
fmla v27.2d, v0.2d, v1.d[0]
fmla v28.2d, v0.2d, v1.d[0]
fmla v29.2d, v0.2d, v1.d[0]
fmla v30.2d, v0.2d, v1.d[0]
fmla v31.2d, v0.2d, v1.d[0]
bne .asimd.fmla.vs.f64f64f64.L1
restore_caller_vec
ret
#ifdef __APPLE__
.globl _asimd_fmla_vv_f64f64f64
_asimd_fmla_vv_f64f64f64:
#else
.globl asimd_fmla_vv_f64f64f64
asimd_fmla_vv_f64f64f64:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.fmla.vv.f64f64f64.L1:
fmla v8.2d, v0.2d, v1.2d
fmla v9.2d, v0.2d, v1.2d
fmla v10.2d, v0.2d, v1.2d
fmla v11.2d, v0.2d, v1.2d
fmla v12.2d, v0.2d, v1.2d
fmla v13.2d, v0.2d, v1.2d
fmla v14.2d, v0.2d, v1.2d
fmla v15.2d, v0.2d, v1.2d
fmla v16.2d, v0.2d, v1.2d
fmla v17.2d, v0.2d, v1.2d
fmla v18.2d, v0.2d, v1.2d
fmla v19.2d, v0.2d, v1.2d
subs x0, x0, #1
fmla v20.2d, v0.2d, v1.2d
fmla v21.2d, v0.2d, v1.2d
fmla v22.2d, v0.2d, v1.2d
fmla v23.2d, v0.2d, v1.2d
fmla v24.2d, v0.2d, v1.2d
fmla v25.2d, v0.2d, v1.2d
fmla v26.2d, v0.2d, v1.2d
fmla v27.2d, v0.2d, v1.2d
fmla v28.2d, v0.2d, v1.2d
fmla v29.2d, v0.2d, v1.2d
fmla v30.2d, v0.2d, v1.2d
fmla v31.2d, v0.2d, v1.2d
bne .asimd.fmla.vv.f64f64f64.L1
restore_caller_vec
ret
================================================
FILE: arm64/asm/_ASIMD_DP_.S
================================================
.align 4
.macro preserve_caller_vec
stp d8, d9, [sp, #-16]!
stp d10, d11, [sp, #-16]!
stp d12, d13, [sp, #-16]!
stp d14, d15, [sp, #-16]!
.endm
.macro restore_caller_vec
ldp d14, d15, [sp], #16
ldp d12, d13, [sp], #16
ldp d10, d11, [sp], #16
ldp d8, d9, [sp], #16
.endm
#ifdef __APPLE__
.globl _asimd_dp4a_vs_s32s8s8
_asimd_dp4a_vs_s32s8s8:
#else
.globl asimd_dp4a_vs_s32s8s8
asimd_dp4a_vs_s32s8s8:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.dp4a.vs.s32s8s8.L1:
sdot v8.4s, v0.16b, v1.4b[0]
sdot v9.4s, v0.16b, v1.4b[0]
sdot v10.4s, v0.16b, v1.4b[0]
sdot v11.4s, v0.16b, v1.4b[0]
sdot v12.4s, v0.16b, v1.4b[0]
sdot v13.4s, v0.16b, v1.4b[0]
sdot v14.4s, v0.16b, v1.4b[0]
sdot v15.4s, v0.16b, v1.4b[0]
sdot v16.4s, v0.16b, v1.4b[0]
sdot v17.4s, v0.16b, v1.4b[0]
sdot v18.4s, v0.16b, v1.4b[0]
sdot v19.4s, v0.16b, v1.4b[0]
subs x0, x0, #1
sdot v20.4s, v0.16b, v1.4b[0]
sdot v21.4s, v0.16b, v1.4b[0]
sdot v22.4s, v0.16b, v1.4b[0]
sdot v23.4s, v0.16b, v1.4b[0]
sdot v24.4s, v0.16b, v1.4b[0]
sdot v25.4s, v0.16b, v1.4b[0]
sdot v26.4s, v0.16b, v1.4b[0]
sdot v27.4s, v0.16b, v1.4b[0]
sdot v28.4s, v0.16b, v1.4b[0]
sdot v29.4s, v0.16b, v1.4b[0]
sdot v30.4s, v0.16b, v1.4b[0]
sdot v31.4s, v0.16b, v1.4b[0]
bne .asimd.dp4a.vs.s32s8s8.L1
restore_caller_vec
ret
#ifdef __APPLE__
.globl _asimd_dp4a_vv_s32s8s8
_asimd_dp4a_vv_s32s8s8:
#else
.globl asimd_dp4a_vv_s32s8s8
asimd_dp4a_vv_s32s8s8:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.dp4a.vv.s32s8s8.L1:
sdot v8.4s, v0.16b, v1.16b
sdot v9.4s, v0.16b, v1.16b
sdot v10.4s, v0.16b, v1.16b
sdot v11.4s, v0.16b, v1.16b
sdot v12.4s, v0.16b, v1.16b
sdot v13.4s, v0.16b, v1.16b
sdot v14.4s, v0.16b, v1.16b
sdot v15.4s, v0.16b, v1.16b
sdot v16.4s, v0.16b, v1.16b
sdot v17.4s, v0.16b, v1.16b
sdot v18.4s, v0.16b, v1.16b
sdot v19.4s, v0.16b, v1.16b
subs x0, x0, #1
sdot v20.4s, v0.16b, v1.16b
sdot v21.4s, v0.16b, v1.16b
sdot v22.4s, v0.16b, v1.16b
sdot v23.4s, v0.16b, v1.16b
sdot v24.4s, v0.16b, v1.16b
sdot v25.4s, v0.16b, v1.16b
sdot v26.4s, v0.16b, v1.16b
sdot v27.4s, v0.16b, v1.16b
sdot v28.4s, v0.16b, v1.16b
sdot v29.4s, v0.16b, v1.16b
sdot v30.4s, v0.16b, v1.16b
sdot v31.4s, v0.16b, v1.16b
bne .asimd.dp4a.vv.s32s8s8.L1
restore_caller_vec
ret
#ifdef __APPLE__
.globl _asimd_dp4a_vs_u32u8u8
_asimd_dp4a_vs_u32u8u8:
#else
.globl asimd_dp4a_vs_u32u8u8
asimd_dp4a_vs_u32u8u8:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.dp4a.vs.u32u8u8.L1:
udot v8.4s, v0.16b, v1.4b[0]
udot v9.4s, v0.16b, v1.4b[0]
udot v10.4s, v0.16b, v1.4b[0]
udot v11.4s, v0.16b, v1.4b[0]
udot v12.4s, v0.16b, v1.4b[0]
udot v13.4s, v0.16b, v1.4b[0]
udot v14.4s, v0.16b, v1.4b[0]
udot v15.4s, v0.16b, v1.4b[0]
udot v16.4s, v0.16b, v1.4b[0]
udot v17.4s, v0.16b, v1.4b[0]
udot v18.4s, v0.16b, v1.4b[0]
udot v19.4s, v0.16b, v1.4b[0]
subs x0, x0, #1
udot v20.4s, v0.16b, v1.4b[0]
udot v21.4s, v0.16b, v1.4b[0]
udot v22.4s, v0.16b, v1.4b[0]
udot v23.4s, v0.16b, v1.4b[0]
udot v24.4s, v0.16b, v1.4b[0]
udot v25.4s, v0.16b, v1.4b[0]
udot v26.4s, v0.16b, v1.4b[0]
udot v27.4s, v0.16b, v1.4b[0]
udot v28.4s, v0.16b, v1.4b[0]
udot v29.4s, v0.16b, v1.4b[0]
udot v30.4s, v0.16b, v1.4b[0]
udot v31.4s, v0.16b, v1.4b[0]
bne .asimd.dp4a.vs.u32u8u8.L1
restore_caller_vec
ret
#ifdef __APPLE__
.globl _asimd_dp4a_vv_u32u8u8
_asimd_dp4a_vv_u32u8u8:
#else
.globl asimd_dp4a_vv_u32u8u8
asimd_dp4a_vv_u32u8u8:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.dp4a.vv.u32u8u8.L1:
udot v8.4s, v0.16b, v1.16b
udot v9.4s, v0.16b, v1.16b
udot v10.4s, v0.16b, v1.16b
udot v11.4s, v0.16b, v1.16b
udot v12.4s, v0.16b, v1.16b
udot v13.4s, v0.16b, v1.16b
udot v14.4s, v0.16b, v1.16b
udot v15.4s, v0.16b, v1.16b
udot v16.4s, v0.16b, v1.16b
udot v17.4s, v0.16b, v1.16b
udot v18.4s, v0.16b, v1.16b
udot v19.4s, v0.16b, v1.16b
subs x0, x0, #1
udot v20.4s, v0.16b, v1.16b
udot v21.4s, v0.16b, v1.16b
udot v22.4s, v0.16b, v1.16b
udot v23.4s, v0.16b, v1.16b
udot v24.4s, v0.16b, v1.16b
udot v25.4s, v0.16b, v1.16b
udot v26.4s, v0.16b, v1.16b
udot v27.4s, v0.16b, v1.16b
udot v28.4s, v0.16b, v1.16b
udot v29.4s, v0.16b, v1.16b
udot v30.4s, v0.16b, v1.16b
udot v31.4s, v0.16b, v1.16b
bne .asimd.dp4a.vv.u32u8u8.L1
restore_caller_vec
ret
================================================
FILE: arm64/asm/_ASIMD_HP_.S
================================================
.align 4
.macro preserve_caller_vec
stp d8, d9, [sp, #-16]!
stp d10, d11, [sp, #-16]!
stp d12, d13, [sp, #-16]!
stp d14, d15, [sp, #-16]!
.endm
.macro restore_caller_vec
ldp d14, d15, [sp], #16
ldp d12, d13, [sp], #16
ldp d10, d11, [sp], #16
ldp d8, d9, [sp], #16
.endm
#ifdef __APPLE__
.globl _asimd_fmla_vs_fp16fp16fp16
_asimd_fmla_vs_fp16fp16fp16:
#else
.globl asimd_fmla_vs_fp16fp16fp16
asimd_fmla_vs_fp16fp16fp16:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.fmla.vs.fp16fp16fp16.L1:
fmla v8.8h, v0.8h, v1.h[0]
fmla v9.8h, v0.8h, v1.h[0]
fmla v10.8h, v0.8h, v1.h[0]
fmla v11.8h, v0.8h, v1.h[0]
fmla v12.8h, v0.8h, v1.h[0]
fmla v13.8h, v0.8h, v1.h[0]
fmla v14.8h, v0.8h, v1.h[0]
fmla v15.8h, v0.8h, v1.h[0]
fmla v16.8h, v0.8h, v1.h[0]
fmla v17.8h, v0.8h, v1.h[0]
fmla v18.8h, v0.8h, v1.h[0]
fmla v19.8h, v0.8h, v1.h[0]
subs x0, x0, #1
fmla v20.8h, v0.8h, v1.h[0]
fmla v21.8h, v0.8h, v1.h[0]
fmla v22.8h, v0.8h, v1.h[0]
fmla v23.8h, v0.8h, v1.h[0]
fmla v24.8h, v0.8h, v1.h[0]
fmla v25.8h, v0.8h, v1.h[0]
fmla v26.8h, v0.8h, v1.h[0]
fmla v27.8h, v0.8h, v1.h[0]
fmla v28.8h, v0.8h, v1.h[0]
fmla v29.8h, v0.8h, v1.h[0]
fmla v30.8h, v0.8h, v1.h[0]
fmla v31.8h, v0.8h, v1.h[0]
bne .asimd.fmla.vs.fp16fp16fp16.L1
restore_caller_vec
ret
#ifdef __APPLE__
.globl _asimd_fmla_vv_fp16fp16fp16
_asimd_fmla_vv_fp16fp16fp16:
#else
.globl asimd_fmla_vv_fp16fp16fp16
asimd_fmla_vv_fp16fp16fp16:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.fmla.vv.fp16fp16fp16.L1:
fmla v8.8h, v0.8h, v1.8h
fmla v9.8h, v0.8h, v1.8h
fmla v10.8h, v0.8h, v1.8h
fmla v11.8h, v0.8h, v1.8h
fmla v12.8h, v0.8h, v1.8h
fmla v13.8h, v0.8h, v1.8h
fmla v14.8h, v0.8h, v1.8h
fmla v15.8h, v0.8h, v1.8h
fmla v16.8h, v0.8h, v1.8h
fmla v17.8h, v0.8h, v1.8h
fmla v18.8h, v0.8h, v1.8h
fmla v19.8h, v0.8h, v1.8h
subs x0, x0, #1
fmla v20.8h, v0.8h, v1.8h
fmla v21.8h, v0.8h, v1.8h
fmla v22.8h, v0.8h, v1.8h
fmla v23.8h, v0.8h, v1.8h
fmla v24.8h, v0.8h, v1.8h
fmla v25.8h, v0.8h, v1.8h
fmla v26.8h, v0.8h, v1.8h
fmla v27.8h, v0.8h, v1.8h
fmla v28.8h, v0.8h, v1.8h
fmla v29.8h, v0.8h, v1.8h
fmla v30.8h, v0.8h, v1.8h
fmla v31.8h, v0.8h, v1.8h
bne .asimd.fmla.vv.fp16fp16fp16.L1
restore_caller_vec
ret
================================================
FILE: arm64/asm/_BF16_.S
================================================
.align 4
.macro preserve_caller_vec
stp d8, d9, [sp, #-16]!
stp d10, d11, [sp, #-16]!
stp d12, d13, [sp, #-16]!
stp d14, d15, [sp, #-16]!
.endm
.macro restore_caller_vec
ldp d14, d15, [sp], #16
ldp d12, d13, [sp], #16
ldp d10, d11, [sp], #16
ldp d8, d9, [sp], #16
.endm
#ifdef __APPLE__
.globl _asimd_mmla_fp32bf16bf16
_asimd_mmla_fp32bf16bf16:
#else
.globl asimd_mmla_fp32bf16bf16
asimd_mmla_fp32bf16bf16:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.mmla.fp32bf16bf16.L1:
bfmmla v8.4s, v0.8h, v1.8h
bfmmla v9.4s, v0.8h, v1.8h
bfmmla v10.4s, v0.8h, v1.8h
bfmmla v11.4s, v0.8h, v1.8h
bfmmla v12.4s, v0.8h, v1.8h
bfmmla v13.4s, v0.8h, v1.8h
bfmmla v14.4s, v0.8h, v1.8h
bfmmla v15.4s, v0.8h, v1.8h
bfmmla v16.4s, v0.8h, v1.8h
bfmmla v17.4s, v0.8h, v1.8h
bfmmla v18.4s, v0.8h, v1.8h
bfmmla v19.4s, v0.8h, v1.8h
subs x0, x0, #1
bfmmla v20.4s, v0.8h, v1.8h
bfmmla v21.4s, v0.8h, v1.8h
bfmmla v22.4s, v0.8h, v1.8h
bfmmla v23.4s, v0.8h, v1.8h
bfmmla v24.4s, v0.8h, v1.8h
bfmmla v25.4s, v0.8h, v1.8h
bfmmla v26.4s, v0.8h, v1.8h
bfmmla v27.4s, v0.8h, v1.8h
bfmmla v28.4s, v0.8h, v1.8h
bfmmla v29.4s, v0.8h, v1.8h
bfmmla v30.4s, v0.8h, v1.8h
bfmmla v31.4s, v0.8h, v1.8h
bne .asimd.mmla.fp32bf16bf16.L1
restore_caller_vec
ret
#ifdef __APPLE__
.globl _asimd_dp2a_vs_fp32bf16bf16
_asimd_dp2a_vs_fp32bf16bf16:
#else
.globl asimd_dp2a_vs_fp32bf16bf16
asimd_dp2a_vs_fp32bf16bf16:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.dp2a.vs.fp32bf16bf16.L1:
bfdot v8.4s, v0.8h, v1.2h[0]
bfdot v9.4s, v0.8h, v1.2h[0]
bfdot v10.4s, v0.8h, v1.2h[0]
bfdot v11.4s, v0.8h, v1.2h[0]
bfdot v12.4s, v0.8h, v1.2h[0]
bfdot v13.4s, v0.8h, v1.2h[0]
bfdot v14.4s, v0.8h, v1.2h[0]
bfdot v15.4s, v0.8h, v1.2h[0]
bfdot v16.4s, v0.8h, v1.2h[0]
bfdot v17.4s, v0.8h, v1.2h[0]
bfdot v18.4s, v0.8h, v1.2h[0]
bfdot v19.4s, v0.8h, v1.2h[0]
subs x0, x0, #1
bfdot v20.4s, v0.8h, v1.2h[0]
bfdot v21.4s, v0.8h, v1.2h[0]
bfdot v22.4s, v0.8h, v1.2h[0]
bfdot v23.4s, v0.8h, v1.2h[0]
bfdot v24.4s, v0.8h, v1.2h[0]
bfdot v25.4s, v0.8h, v1.2h[0]
bfdot v26.4s, v0.8h, v1.2h[0]
bfdot v27.4s, v0.8h, v1.2h[0]
bfdot v28.4s, v0.8h, v1.2h[0]
bfdot v29.4s, v0.8h, v1.2h[0]
bfdot v30.4s, v0.8h, v1.2h[0]
bfdot v31.4s, v0.8h, v1.2h[0]
bne .asimd.dp2a.vs.fp32bf16bf16.L1
restore_caller_vec
ret
#ifdef __APPLE__
.globl _asimd_dp2a_vv_fp32bf16bf16
_asimd_dp2a_vv_fp32bf16bf16:
#else
.globl asimd_dp2a_vv_fp32bf16bf16
asimd_dp2a_vv_fp32bf16bf16:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.dp2a.vv.fp32bf16bf16.L1:
bfdot v8.4s, v0.8h, v1.8h
bfdot v9.4s, v0.8h, v1.8h
bfdot v10.4s, v0.8h, v1.8h
bfdot v11.4s, v0.8h, v1.8h
bfdot v12.4s, v0.8h, v1.8h
bfdot v13.4s, v0.8h, v1.8h
bfdot v14.4s, v0.8h, v1.8h
bfdot v15.4s, v0.8h, v1.8h
bfdot v16.4s, v0.8h, v1.8h
bfdot v17.4s, v0.8h, v1.8h
bfdot v18.4s, v0.8h, v1.8h
bfdot v19.4s, v0.8h, v1.8h
subs x0, x0, #1
bfdot v20.4s, v0.8h, v1.8h
bfdot v21.4s, v0.8h, v1.8h
bfdot v22.4s, v0.8h, v1.8h
bfdot v23.4s, v0.8h, v1.8h
bfdot v24.4s, v0.8h, v1.8h
bfdot v25.4s, v0.8h, v1.8h
bfdot v26.4s, v0.8h, v1.8h
bfdot v27.4s, v0.8h, v1.8h
bfdot v28.4s, v0.8h, v1.8h
bfdot v29.4s, v0.8h, v1.8h
bfdot v30.4s, v0.8h, v1.8h
bfdot v31.4s, v0.8h, v1.8h
bne .asimd.dp2a.vv.fp32bf16bf16.L1
restore_caller_vec
ret
================================================
FILE: arm64/asm/_I8MM_.S
================================================
.align 4
.macro preserve_caller_vec
stp d8, d9, [sp, #-16]!
stp d10, d11, [sp, #-16]!
stp d12, d13, [sp, #-16]!
stp d14, d15, [sp, #-16]!
.endm
.macro restore_caller_vec
ldp d14, d15, [sp], #16
ldp d12, d13, [sp], #16
ldp d10, d11, [sp], #16
ldp d8, d9, [sp], #16
.endm
#ifdef __APPLE__
.globl _asimd_mmla_s32s8s8
_asimd_mmla_s32s8s8:
#else
.globl asimd_mmla_s32s8s8
asimd_mmla_s32s8s8:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.mmla.s32s8s8.L1:
smmla v8.4s, v0.16b, v1.16b
smmla v9.4s, v0.16b, v1.16b
smmla v10.4s, v0.16b, v1.16b
smmla v11.4s, v0.16b, v1.16b
smmla v12.4s, v0.16b, v1.16b
smmla v13.4s, v0.16b, v1.16b
smmla v14.4s, v0.16b, v1.16b
smmla v15.4s, v0.16b, v1.16b
smmla v16.4s, v0.16b, v1.16b
smmla v17.4s, v0.16b, v1.16b
smmla v18.4s, v0.16b, v1.16b
smmla v19.4s, v0.16b, v1.16b
subs x0, x0, #1
smmla v20.4s, v0.16b, v1.16b
smmla v21.4s, v0.16b, v1.16b
smmla v22.4s, v0.16b, v1.16b
smmla v23.4s, v0.16b, v1.16b
smmla v24.4s, v0.16b, v1.16b
smmla v25.4s, v0.16b, v1.16b
smmla v26.4s, v0.16b, v1.16b
smmla v27.4s, v0.16b, v1.16b
smmla v28.4s, v0.16b, v1.16b
smmla v29.4s, v0.16b, v1.16b
smmla v30.4s, v0.16b, v1.16b
smmla v31.4s, v0.16b, v1.16b
bne .asimd.mmla.s32s8s8.L1
restore_caller_vec
ret
#ifdef __APPLE__
.globl _asimd_mmla_u32u8u8
_asimd_mmla_u32u8u8:
#else
.globl asimd_mmla_u32u8u8
asimd_mmla_u32u8u8:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.mmla.u32u8u8.L1:
ummla v8.4s, v0.16b, v1.16b
ummla v9.4s, v0.16b, v1.16b
ummla v10.4s, v0.16b, v1.16b
ummla v11.4s, v0.16b, v1.16b
ummla v12.4s, v0.16b, v1.16b
ummla v13.4s, v0.16b, v1.16b
ummla v14.4s, v0.16b, v1.16b
ummla v15.4s, v0.16b, v1.16b
ummla v16.4s, v0.16b, v1.16b
ummla v17.4s, v0.16b, v1.16b
ummla v18.4s, v0.16b, v1.16b
ummla v19.4s, v0.16b, v1.16b
subs x0, x0, #1
ummla v20.4s, v0.16b, v1.16b
ummla v21.4s, v0.16b, v1.16b
ummla v22.4s, v0.16b, v1.16b
ummla v23.4s, v0.16b, v1.16b
ummla v24.4s, v0.16b, v1.16b
ummla v25.4s, v0.16b, v1.16b
ummla v26.4s, v0.16b, v1.16b
ummla v27.4s, v0.16b, v1.16b
ummla v28.4s, v0.16b, v1.16b
ummla v29.4s, v0.16b, v1.16b
ummla v30.4s, v0.16b, v1.16b
ummla v31.4s, v0.16b, v1.16b
bne .asimd.mmla.u32u8u8.L1
restore_caller_vec
ret
#ifdef __APPLE__
.globl _asimd_mmla_s32u8s8
_asimd_mmla_s32u8s8:
#else
.globl asimd_mmla_s32u8s8
asimd_mmla_s32u8s8:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.mmla.s32u8s8.L1:
usmmla v8.4s, v0.16b, v1.16b
usmmla v9.4s, v0.16b, v1.16b
usmmla v10.4s, v0.16b, v1.16b
usmmla v11.4s, v0.16b, v1.16b
usmmla v12.4s, v0.16b, v1.16b
usmmla v13.4s, v0.16b, v1.16b
usmmla v14.4s, v0.16b, v1.16b
usmmla v15.4s, v0.16b, v1.16b
usmmla v16.4s, v0.16b, v1.16b
usmmla v17.4s, v0.16b, v1.16b
usmmla v18.4s, v0.16b, v1.16b
usmmla v19.4s, v0.16b, v1.16b
subs x0, x0, #1
usmmla v20.4s, v0.16b, v1.16b
usmmla v21.4s, v0.16b, v1.16b
usmmla v22.4s, v0.16b, v1.16b
usmmla v23.4s, v0.16b, v1.16b
usmmla v24.4s, v0.16b, v1.16b
usmmla v25.4s, v0.16b, v1.16b
usmmla v26.4s, v0.16b, v1.16b
usmmla v27.4s, v0.16b, v1.16b
usmmla v28.4s, v0.16b, v1.16b
usmmla v29.4s, v0.16b, v1.16b
usmmla v30.4s, v0.16b, v1.16b
usmmla v31.4s, v0.16b, v1.16b
bne .asimd.mmla.s32u8s8.L1
restore_caller_vec
ret
#ifdef __APPLE__
.globl _asimd_dp4a_vs_s32s8u8
_asimd_dp4a_vs_s32s8u8:
#else
.globl asimd_dp4a_vs_s32s8u8
asimd_dp4a_vs_s32s8u8:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.dp4a.vs.s32s8u8.L1:
sudot v8.4s, v0.16b, v1.4b[0]
sudot v9.4s, v0.16b, v1.4b[0]
sudot v10.4s, v0.16b, v1.4b[0]
sudot v11.4s, v0.16b, v1.4b[0]
sudot v12.4s, v0.16b, v1.4b[0]
sudot v13.4s, v0.16b, v1.4b[0]
sudot v14.4s, v0.16b, v1.4b[0]
sudot v15.4s, v0.16b, v1.4b[0]
sudot v16.4s, v0.16b, v1.4b[0]
sudot v17.4s, v0.16b, v1.4b[0]
sudot v18.4s, v0.16b, v1.4b[0]
sudot v19.4s, v0.16b, v1.4b[0]
subs x0, x0, #1
sudot v20.4s, v0.16b, v1.4b[0]
sudot v21.4s, v0.16b, v1.4b[0]
sudot v22.4s, v0.16b, v1.4b[0]
sudot v23.4s, v0.16b, v1.4b[0]
sudot v24.4s, v0.16b, v1.4b[0]
sudot v25.4s, v0.16b, v1.4b[0]
sudot v26.4s, v0.16b, v1.4b[0]
sudot v27.4s, v0.16b, v1.4b[0]
sudot v28.4s, v0.16b, v1.4b[0]
sudot v29.4s, v0.16b, v1.4b[0]
sudot v30.4s, v0.16b, v1.4b[0]
sudot v31.4s, v0.16b, v1.4b[0]
bne .asimd.dp4a.vs.s32s8u8.L1
restore_caller_vec
ret
#ifdef __APPLE__
.globl _asimd_dp4a_vs_s32u8s8
_asimd_dp4a_vs_s32u8s8:
#else
.globl asimd_dp4a_vs_s32u8s8
asimd_dp4a_vs_s32u8s8:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.dp4a.vs.s32u8s8.L1:
usdot v8.4s, v0.16b, v1.4b[0]
usdot v9.4s, v0.16b, v1.4b[0]
usdot v10.4s, v0.16b, v1.4b[0]
usdot v11.4s, v0.16b, v1.4b[0]
usdot v12.4s, v0.16b, v1.4b[0]
usdot v13.4s, v0.16b, v1.4b[0]
usdot v14.4s, v0.16b, v1.4b[0]
usdot v15.4s, v0.16b, v1.4b[0]
usdot v16.4s, v0.16b, v1.4b[0]
usdot v17.4s, v0.16b, v1.4b[0]
usdot v18.4s, v0.16b, v1.4b[0]
usdot v19.4s, v0.16b, v1.4b[0]
subs x0, x0, #1
usdot v20.4s, v0.16b, v1.4b[0]
usdot v21.4s, v0.16b, v1.4b[0]
usdot v22.4s, v0.16b, v1.4b[0]
usdot v23.4s, v0.16b, v1.4b[0]
usdot v24.4s, v0.16b, v1.4b[0]
usdot v25.4s, v0.16b, v1.4b[0]
usdot v26.4s, v0.16b, v1.4b[0]
usdot v27.4s, v0.16b, v1.4b[0]
usdot v28.4s, v0.16b, v1.4b[0]
usdot v29.4s, v0.16b, v1.4b[0]
usdot v30.4s, v0.16b, v1.4b[0]
usdot v31.4s, v0.16b, v1.4b[0]
bne .asimd.dp4a.vs.s32u8s8.L1
restore_caller_vec
ret
#ifdef __APPLE__
.globl _asimd_dp4a_vv_s32u8s8
_asimd_dp4a_vv_s32u8s8:
#else
.globl asimd_dp4a_vv_s32u8s8
asimd_dp4a_vv_s32u8s8:
#endif
preserve_caller_vec
eor v0.16b, v0.16b, v0.16b
eor v1.16b, v1.16b, v1.16b
eor v8.16b, v8.16b, v8.16b
eor v9.16b, v9.16b, v9.16b
eor v10.16b, v10.16b, v10.16b
eor v11.16b, v11.16b, v11.16b
eor v12.16b, v12.16b, v12.16b
eor v13.16b, v13.16b, v13.16b
eor v14.16b, v14.16b, v14.16b
eor v15.16b, v15.16b, v15.16b
eor v16.16b, v16.16b, v16.16b
eor v17.16b, v17.16b, v17.16b
eor v18.16b, v18.16b, v18.16b
eor v19.16b, v19.16b, v19.16b
eor v20.16b, v20.16b, v20.16b
eor v21.16b, v21.16b, v21.16b
eor v22.16b, v22.16b, v22.16b
eor v23.16b, v23.16b, v23.16b
eor v24.16b, v24.16b, v24.16b
eor v25.16b, v25.16b, v25.16b
eor v26.16b, v26.16b, v26.16b
eor v27.16b, v27.16b, v27.16b
eor v28.16b, v28.16b, v28.16b
eor v29.16b, v29.16b, v29.16b
eor v30.16b, v30.16b, v30.16b
eor v31.16b, v31.16b, v31.16b
.asimd.dp4a.vv.s32u8s8.L1:
usdot v8.4s, v0.16b, v1.16b
usdot v9.4s, v0.16b, v1.16b
usdot v10.4s, v0.16b, v1.16b
usdot v11.4s, v0.16b, v1.16b
usdot v12.4s, v0.16b, v1.16b
usdot v13.4s, v0.16b, v1.16b
usdot v14.4s, v0.16b, v1.16b
usdot v15.4s, v0.16b, v1.16b
usdot v16.4s, v0.16b, v1.16b
usdot v17.4s, v0.16b, v1.16b
usdot v18.4s, v0.16b, v1.16b
usdot v19.4s, v0.16b, v1.16b
subs x0, x0, #1
usdot v20.4s, v0.16b, v1.16b
usdot v21.4s, v0.16b, v1.16b
usdot v22.4s, v0.16b, v1.16b
usdot v23.4s, v0.16b, v1.16b
usdot v24.4s, v0.16b, v1.16b
usdot v25.4s, v0.16b, v1.16b
usdot v26.4s, v0.16b, v1.16b
usdot v27.4s, v0.16b, v1.16b
usdot v28.4s, v0.16b, v1.16b
usdot v29.4s, v0.16b, v1.16b
usdot v30.4s, v0.16b, v1.16b
usdot v31.4s, v0.16b, v1.16b
bne .asimd.dp4a.vv.s32u8s8.L1
restore_caller_vec
ret
================================================
FILE: arm64/cpufp.cpp
================================================
#include "table.hpp"
#include "smtl.hpp"
#include <unistd.h>
#include <cstdint>
#include <ctime>
#include <cstring>
#include <cstdint>
#include <vector>
#include <sstream>
#include <iomanip>
using namespace std;
extern "C"
{
#ifdef _ASIMD_
void asimd_fmla_vs_f32f32f32(int64_t);
void asimd_fmla_vv_f32f32f32(int64_t);
void asimd_fmla_vs_f64f64f64(int64_t);
void asimd_fmla_vv_f64f64f64(int64_t);
#endif
#ifdef _ASIMD_HP_
void asimd_fmla_vs_fp16fp16fp16(int64_t);
void asimd_fmla_vv_fp16fp16fp16(int64_t);
#endif
#ifdef _ASIMD_DP_
void asimd_dp4a_vs_s32s8s8(int64_t);
void asimd_dp4a_vv_s32s8s8(int64_t);
void asimd_dp4a_vs_u32u8u8(int64_t);
void asimd_dp4a_vv_u32u8u8(int64_t);
#endif
#ifdef _BF16_
void asimd_mmla_fp32bf16bf16(int64_t);
void asimd_dp2a_vs_fp32bf16bf16(int64_t);
void asimd_dp2a_vv_fp32bf16bf16(int64_t);
#endif
#ifdef _I8MM_
void asimd_mmla_s32s8s8(int64_t);
void asimd_mmla_u32u8u8(int64_t);
void asimd_mmla_s32u8s8(int64_t);
void asimd_dp4a_vs_s32s8u8(int64_t);
void asimd_dp4a_vs_s32u8s8(int64_t);
void asimd_dp4a_vv_s32u8s8(int64_t);
#endif
}
typedef struct
{
std::string isa;
std::string type;
std::string dim;
int64_t loop_time;
int64_t comp_pl;
void (*bench)(int64_t);
} cpubm_t;
static vector<cpubm_t> bm_list;
static double get_time(struct timespec *start,
struct timespec *end)
{
return end->tv_sec - start->tv_sec +
(end->tv_nsec - start->tv_nsec) * 1e-9;
}
static void reg_new_isa(std::string isa,
std::string type,
std::string dim,
int64_t loop_time,
int64_t comp_pl,
void (*bench)(int64_t))
{
cpubm_t new_one;
new_one.isa = isa;
new_one.type = type;
new_one.dim = dim;
new_one.loop_time = loop_time;
new_one.comp_pl = comp_pl;
new_one.bench = bench;
bm_list.push_back(new_one);
}
static void thread_func(void *params)
{
cpubm_t *bm = (cpubm_t*)params;
bm->bench(bm->loop_time);
}
static void cpubm_arm64_one(smtl_handle sh,
cpubm_t &item,
Table &table)
{
struct timespec start, end;
double time_used, perf;
char perfUnit = 'G';
int i;
int num_threads = smtl_num_threads(sh);
// warm up
for (i = 0; i < num_threads; i++)
{
smtl_add_task(sh, thread_func, (void*)&item);
}
smtl_begin_tasks(sh);
smtl_wait_tasks_finished(sh);
clock_gettime(CLOCK_MONOTONIC_RAW, &start);
for (i = 0; i < num_threads; i++)
{
smtl_add_task(sh, thread_func, (void*)&item);
}
smtl_begin_tasks(sh);
smtl_wait_tasks_finished(sh);
clock_gettime(CLOCK_MONOTONIC_RAW, &end);
time_used = get_time(&start, &end);
perf = item.loop_time * item.comp_pl * num_threads /
time_used;
if (perf > 1e12)
{
perfUnit = 'T';
perf /= 1e12;
}
else
{
perf /= 1e9;
}
stringstream ss;
ss << std::setprecision(5) << perf << " " << perfUnit << item.dim;
vector<string> cont;
cont.resize(3);
cont[0] = item.isa;
cont[1] = item.type;
cont[2] = ss.str();
table.addOneItem(cont);
}
static void cpubm_do_bench(std::vector<int> &set_of_threads,
uint32_t idle_time)
{
int i;
if (bm_list.size() > 0)
{
int num_threads = set_of_threads.size();
printf("Number Threads: %d\n", num_threads);
printf("Thread Pool Binding:");
for (i = 0; i < num_threads; i++)
{
printf(" %d", set_of_threads[i]);
}
printf("\n");
// set table head
vector<string> ti;
ti.resize(3);
ti[0] = "Instruction Set";
ti[1] = "Core Computation";
ti[2] = "Peak Performance";
Table table;
table.setColumnNum(3);
table.addOneItem(ti);
// set thread pool
smtl_handle sh;
smtl_init(&sh, set_of_threads);
// traverse task list
cpubm_arm64_one(sh, bm_list[0], table);
for (i = 1; i < bm_list.size(); i++)
{
sleep(idle_time);
cpubm_arm64_one(sh, bm_list[i], table);
}
table.print();
smtl_fini(sh);
}
else
{
printf("Sorry, there's no any supported SIMD isa.\n");
}
}
static void parse_thread_pool(char *sets,
vector<int> &set_of_threads)
{
if (sets[0] != '[')
{
return;
}
int pos = 1;
int left = 0, right = 0;
int state = 0;
while (sets[pos] != ']' && sets[pos] != '\0')
{
if (state == 0)
{
if (sets[pos] >= '0' && sets[pos] <= '9')
{
left *= 10;
left += (int)(sets[pos] - '0');
}
else if (sets[pos] == ',')
{
set_of_threads.push_back(left);
left = 0;
}
else if (sets[pos] == '-')
{
right = 0;
state = 1;
}
}
else if (state == 1)
{
if (sets[pos] >= '0' && sets[pos] <= '9')
{
right *= 10;
right += (int)(sets[pos] - '0');
}
else if (sets[pos] == ',')
{
int i;
for (i = left; i <= right; i++)
{
set_of_threads.push_back(i);
}
left = 0;
state = 0;
}
}
pos++;
}
if (sets[pos] != ']')
{
return;
}
if (state == 0)
{
set_of_threads.push_back(left);
}
else if (state == 1)
{
int i;
for (i = left; i <= right; i++)
{
set_of_threads.push_back(i);
}
}
}
static void cpufp_register_isa()
{
#ifdef _I8MM_
reg_new_isa("i8mm", "mmla(s32,s8,s8)", "OPS",
0x10000000LL, 1536LL, asimd_mmla_s32s8s8);
reg_new_isa("i8mm", "mmla(u32,u8,u8)", "OPS",
0x10000000LL, 1536LL, asimd_mmla_u32u8u8);
reg_new_isa("i8mm", "mmla(s32,u8,s8)", "OPS",
0x10000000LL, 1536LL, asimd_mmla_s32u8s8);
reg_new_isa("i8mm", "dp4a.vs(s32,s8,u8)", "OPS",
0x10000000LL, 768LL, asimd_dp4a_vs_s32s8u8);
reg_new_isa("i8mm", "dp4a.vs(s32,u8,s8)", "OPS",
0x10000000LL, 768LL, asimd_dp4a_vs_s32u8s8);
reg_new_isa("i8mm", "dp4a.vv(s32,u8,s8)", "OPS",
0x10000000LL, 768LL, asimd_dp4a_vv_s32u8s8);
#endif
#ifdef _ASIMD_DP_
reg_new_isa("asimd_dp", "dp4a.vs(s32,s8,s8)", "OPS",
0x10000000LL, 768LL, asimd_dp4a_vs_s32s8s8);
reg_new_isa("asimd_dp", "dp4a.vv(s32,s8,s8)", "OPS",
0x10000000LL, 768LL, asimd_dp4a_vv_s32s8s8);
reg_new_isa("asimd_dp", "dp4a.vs(u32,u8,u8)", "OPS",
0x10000000LL, 768LL, asimd_dp4a_vs_u32u8u8);
reg_new_isa("asimd_dp", "dp4a.vv(u32,u8,u8)", "OPS",
0x10000000LL, 768LL, asimd_dp4a_vv_u32u8u8);
#endif
#ifdef _BF16_
reg_new_isa("bf16", "mmla(f32,bf16,bf16)", "FLOPS",
0x10000000LL, 768LL, asimd_mmla_fp32bf16bf16);
reg_new_isa("bf16", "dp2a.vs(f32,bf16,bf16)", "FLOPS",
0x10000000LL, 384LL, asimd_dp2a_vs_fp32bf16bf16);
reg_new_isa("bf16", "dp2a.vv(f32,bf16,bf16)", "FLOPS",
0x10000000LL, 384LL, asimd_dp2a_vv_fp32bf16bf16);
#endif
#ifdef _ASIMD_HP_
reg_new_isa("asimd_hp", "fmla.vs(fp16,fp16,fp16)", "FLOPS",
0x10000000LL, 384LL, asimd_fmla_vs_fp16fp16fp16);
reg_new_isa("asimd_hp", "fmla.vv(fp16,fp16,fp16)", "FLOPS",
0x10000000LL, 384LL, asimd_fmla_vv_fp16fp16fp16);
#endif
#ifdef _ASIMD_
reg_new_isa("asimd", "fmla.vs(f32,f32,f32)", "FLOPS",
0x10000000LL, 192LL, asimd_fmla_vs_f32f32f32);
reg_new_isa("asimd", "fmla.vv(f32,f32,f32)", "FLOPS",
0x10000000LL, 192LL, asimd_fmla_vv_f32f32f32);
reg_new_isa("asimd", "fmla.vs(f64,f64,f64)", "FLOPS",
0x10000000LL, 96LL, asimd_fmla_vs_f64f64f64);
reg_new_isa("asimd", "fmla.vv(f64,f64,f64)", "FLOPS",
0x10000000LL, 96LL, asimd_fmla_vv_f64f64f64);
#endif
}
int main(int argc, char *argv[])
{
vector<int> set_of_threads;
uint32_t idle_time = 0;
bool params_enough = false;
int i;
for (i = 1; i < argc; i++)
{
if (strncmp(argv[i], "--thread_pool=", 14) == 0)
{
parse_thread_pool(argv[i] + 14, set_of_threads);
params_enough = true;
}
else if (strncmp(argv[i], "--idle_time=", 12) == 0)
{
idle_time = (uint32_t)atoi(argv[i] + 12);
}
}
if (!params_enough)
{
fprintf(stderr, "Error: You must set --thread_pool parameter.\n");
fprintf(stderr, "You may also set --idle_time parameter.\n");
fprintf(stderr, "Usage: %s --thread_pool=[xxx] --idle_time=yyy\n", argv[0]);
fprintf(stderr, "[xxx] indicates all cores to benchmark.\n");
fprintf(stderr, "Example: [0,3,5-8,13-15].\n");
fprintf(stderr, "idle_time is the interval time(s) between every two benchmarks.\n");
fprintf(stderr, "idle_time parameter can be ignored, the default value is 0s.\n");
fprintf(stderr, "Notice: there must NOT be any spaces.\n");
exit(0);
}
cpufp_register_isa();
cpubm_do_bench(set_of_threads, idle_time);
return 0;
}
================================================
FILE: arm64/cpuid.c
================================================
#include <stdio.h>
#include <stdint.h>
#ifndef __APPLE__
#include <asm/hwcap.h>
#include <sys/auxv.h>
#else
#include <stdlib.h>
#include <sys/types.h>
#include <sys/sysctl.h>
#include <string.h>
#endif
int main()
{
#ifndef __APPLE__
uint64_t hwcaps = getauxval(AT_HWCAP);
#ifdef HWCAP2_I8MM
if (hwcaps & HWCAP2_I8MM)
{
printf("_I8MM_\n");
}
#endif
#ifdef HWCAP2_BF16
if (hwcaps & HWCAP2_BF16)
{
printf("_BF16_\n");
}
#endif
#ifdef HWCAP_ASIMDDP
if (hwcaps & HWCAP_ASIMDDP)
{
printf("_ASIMD_DP_\n");
}
#endif
#ifdef HWCAP_ASIMDHP
if (hwcaps & HWCAP_ASIMDHP)
{
printf("_ASIMD_HP_\n");
}
#endif
#ifdef HWCAP_ASIMD
if (hwcaps & HWCAP_ASIMD)
{
printf("_ASIMD_\n");
}
#endif
#else
size_t size = 4;
uint32_t res;
sysctlbyname("hw.optional.arm.FEAT_I8MM", &res, &size, NULL, 0);
if (res == 1) {
printf("_I8MM_\n");
}
sysctlbyname("hw.optional.arm.FEAT_BF16", &res, &size, NULL, 0);
if (res == 1) {
printf("_BF16_\n");
}
sysctlbyname("hw.optional.arm.FEAT_DotProd", &res, &size, NULL, 0);
if (res == 1) {
printf("_ASIMD_DP_\n");
}
sysctlbyname("hw.optional.AdvSIMD_HPFPCv", &res, &size, NULL, 0);
if (res == 1) {
printf("_ASIMD_HP_\n");
}
sysctlbyname("hw.optional.AdvSIMD", &res, &size, NULL, 0);
if (res == 1) {
printf("_ASIMD_\n");
}
#endif
return 0;
}
================================================
FILE: benchmark_result/arm64/AWS_Graviton_3E.md
================================================
# AWS Graviton 3E
Architecture: Neoverse V1
Setting: Virtual 1 Core
For single core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 332.34 GGOPS |
| i8mm | mmla(u32,u8,u8) | 332.46 GGOPS |
| i8mm | mmla(s32,u8,s8) | 332.46 GGOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 166.23 GGOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 166.17 GGOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 166.14 GGOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 166.18 GGOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 166.22 GGOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 166.22 GGOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 166.22 GGOPS |
| bf16 | mmla(f32,bf16,bf16) | 166.18 GGFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 83.085 GGFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 83.111 GGFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 83.105 GGFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 83.113 GGFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 41.549 GGFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 41.542 GGFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 35.96 GGFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 20.779 GGFLOPS |
----------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/arm64/Apple_Silicon_M2_Max.md
================================================
# Apple M2 Max (Macbook Pro 16)
Setting: 8 Avalanche P-Cores + 4 Blizzard E-Cores
OS: MacOS 15.1
For 1 P-core:
<pre>
> ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
Warning: cpu thread policy is not supported by OS
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 347.22 GOPS |
| i8mm | mmla(u32,u8,u8) | 353.72 GOPS |
| i8mm | mmla(s32,u8,s8) | 361.84 GOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 426.77 GOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 418.49 GOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 436.31 GOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 425.79 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 420.44 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 430.16 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 425.55 GOPS |
| bf16 | mmla(f32,bf16,bf16) | 51.959 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 53.449 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 53.995 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 215.06 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 210.01 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 105.54 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 107.27 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 54.109 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 51.883 GFLOPS |
----------------------------------------------------------------
</pre>
For 8 P-cores:
<pre>
> ./cpufp --thread_pool=[0-7]
Number Threads: 8
Thread Pool Binding: 0 1 2 3 4 5 6 7
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 2.5416 TOPS |
| i8mm | mmla(u32,u8,u8) | 2.2677 TOPS |
| i8mm | mmla(s32,u8,s8) | 2.6085 TOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 3.0364 TOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 3.0657 TOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 3.1035 TOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 2.9913 TOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 3.0582 TOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 2.9646 TOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 2.3463 TOPS |
| bf16 | mmla(f32,bf16,bf16) | 384.6 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 375.38 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 369.55 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 1.5043 TFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 1.5192 TFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 763 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 765.33 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 377.3 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 377.05 GFLOPS |
----------------------------------------------------------------
</pre>
For 1 E-core:
<pre>
> taskpolicy -c background ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
Warning: cpu thread policy is not supported by OS
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 101.41 GOPS |
| i8mm | mmla(u32,u8,u8) | 97.71 GOPS |
| i8mm | mmla(s32,u8,s8) | 100.49 GOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 101.54 GOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 96.847 GOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 98.375 GOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 102.21 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 95.13 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 98.558 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 102.73 GOPS |
| bf16 | mmla(f32,bf16,bf16) | 12.526 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 11.987 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 11.877 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 50.557 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 51.691 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 23.584 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 23.78 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 12.689 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 12.744 GFLOPS |
----------------------------------------------------------------
</pre>
For 4 E-cores (OS is running and therefore using some of them):
<pre>
> taskpolicy -c background ./cpufp --thread_pool=[0-3]
Number Threads: 4
Thread Pool Binding: 0 1 2 3
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 292.61 GOPS |
| i8mm | mmla(u32,u8,u8) | 278.35 GOPS |
| i8mm | mmla(s32,u8,s8) | 288.3 GOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 315.5 GOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 312.98 GOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 245.39 GOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 205.68 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 267.14 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 320.75 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 279.87 GOPS |
| bf16 | mmla(f32,bf16,bf16) | 37.858 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 36.48 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 35.658 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 145.14 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 140.57 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 74.868 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 78.191 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 40.488 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 36.496 GFLOPS |
----------------------------------------------------------------
</pre>
For 8 P-cores and 4 E-cores:
<pre>
> ./cpufp --thread_pool=[0-11]
Number Threads: 12
Thread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 2.3888 TOPS |
| i8mm | mmla(u32,u8,u8) | 2.4141 TOPS |
| i8mm | mmla(s32,u8,s8) | 2.2572 TOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 2.7256 TOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 2.4714 TOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 2.6389 TOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 2.7067 TOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 2.626 TOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 2.7011 TOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 2.6723 TOPS |
| bf16 | mmla(f32,bf16,bf16) | 345.83 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 341.14 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 340.41 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 1.3411 TFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 1.2838 TFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 645.88 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 668.01 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 339.89 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 337.88 GFLOPS |
----------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/arm64/Apple_Silicon_M4_Max.md
================================================
# Apple M4 Max (Macbook Pro 16)
Setting: 12 P-Cores + 4 E-Cores
OS: MacOS 15.1
For 1 P-core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
Warning: cpu thread policy is not supported by OS
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 477.42 GOPS |
| i8mm | mmla(u32,u8,u8) | 477.76 GOPS |
| i8mm | mmla(s32,u8,s8) | 478.18 GOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 472.27 GOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 472.34 GOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 472.57 GOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 472.39 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 472.39 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 472.66 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 472.7 GOPS |
| bf16 | mmla(f32,bf16,bf16) | 71.964 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 71.942 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 71.915 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 233.67 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 236.39 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 116.7 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 118.4 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 58.344 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 59.124 GFLOPS |
----------------------------------------------------------------
</pre>
For 12 P-cores:
<pre>
$ ./cpufp --thread_pool=[0-11]
Number Threads: 12
Thread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 4.9542 TOPS |
| i8mm | mmla(u32,u8,u8) | 4.9557 TOPS |
| i8mm | mmla(s32,u8,s8) | 4.9335 TOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 4.8965 TOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 4.8873 TOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 4.896 TOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 4.891 TOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 4.8954 TOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 4.8983 TOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 4.8943 TOPS |
| bf16 | mmla(f32,bf16,bf16) | 745.35 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 745.37 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 745.28 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 2.4183 TFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 2.4491 TFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 1.208 TFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 1.2245 TFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 604.22 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 612.65 GFLOPS |
----------------------------------------------------------------
</pre>
For 1 E-core:
<pre>
$ taskpolicy -c background ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
Warning: cpu thread policy is not supported by OS
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 66.327 GOPS |
| i8mm | mmla(u32,u8,u8) | 68.298 GOPS |
| i8mm | mmla(s32,u8,s8) | 75.25 GOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 65.959 GOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 66.819 GOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 69.26 GOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 67.005 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 66.623 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 64.867 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 65.323 GOPS |
| bf16 | mmla(f32,bf16,bf16) | 11.234 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 11.222 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 11.242 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 32.67 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 33.329 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 16.367 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 16.262 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 8.1371 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 8.5853 GFLOPS |
----------------------------------------------------------------
</pre>
For 4 E-cores (OS is running and therefore using some of them):
<pre>
$ taskpolicy -c background ./cpufp --thread_pool=[0-3]
Number Threads: 4
Thread Pool Binding: 0 1 2 3
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 245.5 GOPS |
| i8mm | mmla(u32,u8,u8) | 254.44 GOPS |
| i8mm | mmla(s32,u8,s8) | 254.65 GOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 250.63 GOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 254.65 GOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 254.88 GOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 247.45 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 255.69 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 254.06 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 253.43 GOPS |
| bf16 | mmla(f32,bf16,bf16) | 42.842 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 43.632 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 43.273 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 126.73 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 132.21 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 65.895 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 63.022 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 31.509 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 31.543 GFLOPS |
----------------------------------------------------------------
</pre>
For 12 P-cores + 4 E-cores:
<pre>
$ ./cpufp --thread_pool=[0-15]
Number Threads: 16
Thread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
Warning: cpu thread policy is not supported by OS
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 5.4673 TOPS |
| i8mm | mmla(u32,u8,u8) | 5.5309 TOPS |
| i8mm | mmla(s32,u8,s8) | 5.5254 TOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 5.4348 TOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 5.4187 TOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 5.4255 TOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 5.4434 TOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 5.4171 TOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 5.4069 TOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 5.3969 TOPS |
| bf16 | mmla(f32,bf16,bf16) | 844.34 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 843.35 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 841.86 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 2.6914 TFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 2.735 TFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 1.3444 TFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 1.3631 TFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 673.16 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 678.52 GFLOPS |
----------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/arm64/Broadcom_BCM2711.md
================================================
# Broadcom BCM2711(RaspBerry Pi 4)
Setting: 4 Cortex-A72 Cores
For single core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
-------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd | fmla.vs(f32,f32,f32) | 11.958 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 11.958 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 5.9792 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 5.9792 GFLOPS |
-------------------------------------------------------------
</pre>
For 4 cores:
<pre>
$ ./cpufp --thread_pool=[0-3]
Number Threads: 4
Thread Pool Binding: 0 1 2 3
-------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd | fmla.vs(f32,f32,f32) | 47.883 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 47.88 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 23.933 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 23.943 GFLOPS |
-------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/arm64/Broadcom_BCM2712.md
================================================
# Broadcom BCM2712(RaspBerry Pi 5)
Setting: 4 Cortex-A76 Cores
For single core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd_dp | dp4a.vs(s32,s8,s8) | 153.48 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 153.48 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 153.47 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 153.48 GOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 76.738 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 76.738 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 38.369 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 38.369 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 19.185 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 19.185 GFLOPS |
----------------------------------------------------------------
</pre>
For 4 cores:
<pre>
$ ./cpufp --thread_pool=[0-3]
Number Threads: 4
Thread Pool Binding: 0 1 2 3
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd_dp | dp4a.vs(s32,s8,s8) | 613.79 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 614.02 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 613.98 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 613.99 GOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 306.88 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 306.98 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 153.48 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 153.5 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 74.513 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 76.751 GFLOPS |
----------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/arm64/CIX_P1_CD8180.md
================================================
# CIX P1 CD8180(Radxa Orion O6)
Settings:
Cortex-A720 @ 2.5GHz: 0,11
Cortex-A720 @ 2.4GHz: 9,10
Cortex-A720 @ 2.3GHz: 5,6
Cortex-A720 @ 2.2GHz: 7,8
Cortex-A520 @ 1.8GHz: 1-4
Power policy: Balance
For single P-Core @ 2.5GHz:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 319.69 GOPS |
| i8mm | mmla(u32,u8,u8) | 319.71 GOPS |
| i8mm | mmla(s32,u8,s8) | 319.71 GOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 159.86 GOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 159.88 GOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 159.85 GOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 159.87 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 159.89 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 159.87 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 159.89 GOPS |
| bf16 | mmla(f32,bf16,bf16) | 159.9 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 79.947 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 79.949 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 79.948 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 79.944 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 39.971 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 39.972 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 19.985 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 19.984 GFLOPS |
----------------------------------------------------------------
</pre>
For 2 P-Cores @ 2.5GHz:
<pre>
$ ./cpufp --thread_pool=[0,11]
Number Threads: 2
Thread Pool Binding: 0 11
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 638.37 GOPS |
| i8mm | mmla(u32,u8,u8) | 639.22 GOPS |
| i8mm | mmla(s32,u8,s8) | 639.3 GOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 319.61 GOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 319.58 GOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 319.69 GOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 319.67 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 319.61 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 319.6 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 319.65 GOPS |
| bf16 | mmla(f32,bf16,bf16) | 319.64 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 159.87 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 159.86 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 159.85 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 159.85 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 79.899 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 79.935 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 39.956 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 39.963 GFLOPS |
----------------------------------------------------------------
</pre>
For single P-Core @ 2.4GHz:
<pre>
$ ./cpufp --thread_pool=[9]
Number Threads: 1
Thread Pool Binding: 9
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 306.95 GOPS |
| i8mm | mmla(u32,u8,u8) | 306.94 GOPS |
| i8mm | mmla(s32,u8,s8) | 306.98 GOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 153.47 GOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 153.46 GOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 153.48 GOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 153.46 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 153.46 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 153.48 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 153.47 GOPS |
| bf16 | mmla(f32,bf16,bf16) | 153.49 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 76.745 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 76.732 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 76.734 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 76.75 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 38.369 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 38.367 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 19.186 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 19.185 GFLOPS |
----------------------------------------------------------------
</pre>
For 2 P-Cores @ 2.4GHz:
<pre>
$ ./cpufp --thread_pool=[9,10]
Number Threads: 2
Thread Pool Binding: 9 10
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 613.78 GOPS |
| i8mm | mmla(u32,u8,u8) | 613.84 GOPS |
| i8mm | mmla(s32,u8,s8) | 613.84 GOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 306.92 GOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 306.9 GOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 306.95 GOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 306.92 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 306.89 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 306.94 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 306.93 GOPS |
| bf16 | mmla(f32,bf16,bf16) | 306.9 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 153.47 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 153.46 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 153.45 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 153.46 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 76.725 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 76.726 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 38.368 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 38.364 GFLOPS |
----------------------------------------------------------------
</pre>
For single P-Core @ 2.3GHz:
<pre>
$ ./cpufp --thread_pool=[5]
Number Threads: 1
Thread Pool Binding: 5
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 294.17 GOPS |
| i8mm | mmla(u32,u8,u8) | 294.15 GOPS |
| i8mm | mmla(s32,u8,s8) | 294.14 GOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 147.07 GOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 147.08 GOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 147.07 GOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 147.07 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 147.07 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 147.07 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 147.08 GOPS |
| bf16 | mmla(f32,bf16,bf16) | 147.07 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 73.532 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 73.539 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 73.541 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 73.537 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 36.768 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 36.772 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 18.383 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 18.384 GFLOPS |
----------------------------------------------------------------
</pre>
For 2 P-Cores @ 2.3GHz:
<pre>
$ ./cpufp --thread_pool=[5,6]
Number Threads: 2
Thread Pool Binding: 5 6
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 586.66 GOPS |
| i8mm | mmla(u32,u8,u8) | 587.38 GOPS |
| i8mm | mmla(s32,u8,s8) | 587.83 GOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 293.61 GOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 293.87 GOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 293.46 GOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 293.87 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 293.94 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 293.91 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 293.86 GOPS |
| bf16 | mmla(f32,bf16,bf16) | 293.81 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 146.88 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 146.91 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 146.94 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 146.84 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 73.442 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 73.456 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 36.735 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 36.728 GFLOPS |
----------------------------------------------------------------
</pre>
For single P-Core @ 2.2GHz:
<pre>
$ ./cpufp --thread_pool=[7]
Number Threads: 1
Thread Pool Binding: 7
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 281.34 GOPS |
| i8mm | mmla(u32,u8,u8) | 281.37 GOPS |
| i8mm | mmla(s32,u8,s8) | 281.35 GOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 140.67 GOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 140.68 GOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 140.68 GOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 140.68 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 140.7 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 140.69 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 140.69 GOPS |
| bf16 | mmla(f32,bf16,bf16) | 140.67 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 70.338 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 70.335 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 70.346 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 70.345 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 35.169 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 35.172 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 17.587 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 17.585 GFLOPS |
----------------------------------------------------------------
</pre>
For 2 P-Cores @ 2.2GHz:
<pre>
$ ./cpufp --thread_pool=[7,8]
Number Threads: 2
Thread Pool Binding: 7 8
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 562.68 GOPS |
| i8mm | mmla(u32,u8,u8) | 562.69 GOPS |
| i8mm | mmla(s32,u8,s8) | 562.75 GOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 281.34 GOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 281.32 GOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 281.32 GOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 281.32 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 281.36 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 281.38 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 281.36 GOPS |
| bf16 | mmla(f32,bf16,bf16) | 281.34 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 140.68 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 140.67 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 140.67 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 140.69 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 70.344 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 70.342 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 35.171 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 35.17 GFLOPS |
----------------------------------------------------------------
</pre>
For single E-core @ 1.8GHz:
<pre>
$ ./cpufp --thread_pool=[1]
Number Threads: 1
Thread Pool Binding: 1
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 114.83 GOPS |
| i8mm | mmla(u32,u8,u8) | 114.82 GOPS |
| i8mm | mmla(s32,u8,s8) | 114.81 GOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 57.415 GOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 57.414 GOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 57.417 GOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 57.411 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 57.417 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 57.418 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 57.415 GOPS |
| bf16 | mmla(f32,bf16,bf16) | 22.967 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 28.706 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 28.708 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 28.703 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 28.708 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 14.354 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 14.353 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 7.1768 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 7.1766 GFLOPS |
----------------------------------------------------------------
</pre>
For 4 E-Cores @ 1.8GHz:
<pre>
$ ./cpufp --thread_pool=[1-4]
Number Threads: 4
Thread Pool Binding: 1 2 3 4
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 402.75 GOPS |
| i8mm | mmla(u32,u8,u8) | 402.79 GOPS |
| i8mm | mmla(s32,u8,s8) | 402.79 GOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 201.37 GOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 201.35 GOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 201.35 GOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 201.37 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 201.29 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 201.35 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 201.36 GOPS |
| bf16 | mmla(f32,bf16,bf16) | 80.555 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 100.68 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 100.66 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 100.68 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 100.7 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 50.355 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 50.348 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 25.172 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 25.172 GFLOPS |
----------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/arm64/HUAWEI_Kunpeng_920_7260.md
================================================
# HUAWEI Kunpeng 920 7260
Architecture: Taishan V110
Setting: 2 * 64 cores
For single core:
<pre>
$ ./cpufp --thread_pool=[1]
Number Threads: 1
Thread Pool Binding: 1
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd_dp | dp4a.vs(s32,s8,s8) | 166.3 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 166.32 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 166.31 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 166.29 GOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 83.161 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 83.151 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 41.576 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 41.579 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 10.395 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 10.394 GFLOPS |
----------------------------------------------------------------
</pre>
For 32 cores:
<pre>
$ ./cpufp --thread_pool=[0-31]
Number Threads: 32
Thread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd_dp | dp4a.vs(s32,s8,s8) | 5.304 TOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 5.3108 TOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 5.307 TOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 5.3123 TOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 2.6555 TFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 2.6564 TFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 1.3252 TFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 1.328 TFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 331.95 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 331.98 GFLOPS |
----------------------------------------------------------------
</pre>
For 64 cores:
<pre>
$ ./cpufp --thread_pool=[0-63]
Number Threads: 64
Thread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd_dp | dp4a.vs(s32,s8,s8) | 10.601 TOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 10.586 TOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 10.587 TOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 10.593 TOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 5.2966 TFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 5.2975 TFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 2.6551 TFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 2.6557 TFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 663.98 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 663.73 GFLOPS |
----------------------------------------------------------------
</pre>
For 128 cores:
<pre>
$ ./cpufp --thread_pool=[0-127]
Number Threads: 128
Thread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd_dp | dp4a.vs(s32,s8,s8) | 20.951 TOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 20.27 TOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 19.736 TOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 16.495 TOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 10.481 TFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 10.514 TFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 5.1993 TFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 4.117 TFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 1.2754 TFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 1.049 TFLOPS |
----------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/arm64/HUAWEI_Kunpeng_D920_2249K.md
================================================
# HUAWEI Kunpeng D920 2249K
Architecture: Taishan V110
Setting: 8 cores
For single core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd_dp | dp4a.vs(s32,s8,s8) | 166.21 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 166.21 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 166.21 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 166.2 GOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 83.104 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 83.104 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 41.553 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 41.553 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 10.388 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 10.388 GFLOPS |
----------------------------------------------------------------
</pre>
For 8 cores:
<pre>
$ ./cpufp --thread_pool=[0-7]
Number Threads: 8
Thread Pool Binding: 0 1 2 3 4 5 6 7
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd_dp | dp4a.vs(s32,s8,s8) | 1.3132 TOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 1.3014 TOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 1.3034 TOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 1.3016 TOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 651.87 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 652.34 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 326.4 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 326.12 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 81.791 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 81.503 GFLOPS |
----------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/arm64/Phytium_D2000.md
================================================
# Phytium D2000/8
Setting: 8 FTC663 Cores
For single core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
-------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd | fmla.vs(f32,f32,f32) | 18.376 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 18.375 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 9.1877 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 9.1891 GFLOPS |
-------------------------------------------------------------
</pre>
For 4 cores:
<pre>
$ ./cpufp --thread_pool=[0-3]
Number Threads: 4
Thread Pool Binding: 0 1 2 3
-------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd | fmla.vs(f32,f32,f32) | 73.51 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 73.51 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 36.755 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 36.747 GFLOPS |
-------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/arm64/Qualcomm_Snapdragon_X_Elite_X1E80100.md
================================================
# Qualcomm Snapdragon X Elite - X1E80100
Architecture: Oryon-1
Setting: 4 E-cores @ 3.4Ghz + 8 P-cores @ 4.0Ghz
For single core:
<pre>
> .\cpufp.exe --thread_pool=[4]
Number Threads: 1
Thread Pool Binding: 4
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 442.36 GOPS |
| i8mm | mmla(u32,u8,u8) | 434.67 GOPS |
| i8mm | mmla(s32,u8,s8) | 437.35 GOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 520.02 GOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 525.78 GOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 515.6 GOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 510.91 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 516.89 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 518 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 514.3 GOPS |
| bf16 | mmla(f32,bf16,bf16) | 223.53 GFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 256.44 GFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 252.13 GFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 260.4 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 259.04 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 127.29 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 125.67 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 65.2 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 65.195 GFLOPS |
----------------------------------------------------------------
</pre>
For 12 cores:
<pre>
> .\cpufp.exe --thread_pool=[0-11]
Number Threads: 12
Thread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| i8mm | mmla(s32,s8,s8) | 4.3971 TOPS |
| i8mm | mmla(u32,u8,u8) | 4.3813 TOPS |
| i8mm | mmla(s32,u8,s8) | 4.3889 TOPS |
| i8mm | dp4a.vs(s32,s8,u8) | 5.1953 TOPS |
| i8mm | dp4a.vs(s32,u8,s8) | 5.221 TOPS |
| i8mm | dp4a.vv(s32,u8,s8) | 5.209 TOPS |
| asimd_dp | dp4a.vs(s32,s8,s8) | 5.2081 TOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 5.2275 TOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 5.222 TOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 5.2146 TOPS |
| bf16 | mmla(f32,bf16,bf16) | 2.2578 TFLOPS |
| bf16 | dp2a.vs(f32,bf16,bf16) | 2.6124 TFLOPS |
| bf16 | dp2a.vv(f32,bf16,bf16) | 2.6172 TFLOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 2.6051 TFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 2.6035 TFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 1.3028 TFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 1.3032 TFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 654.67 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 654.44 GFLOPS |
----------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/arm64/RockChip_RK3399.md
================================================
# Rockchip RK3399
Setting: 2 Cortex-A72(big) Cores + 4 Cortex-A53(Little) Cores
For single Little core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
-------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd | fmla.vs(f32,f32,f32) | 11.255 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 11.255 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 5.6275 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 5.6277 GFLOPS |
-------------------------------------------------------------
</pre>
For 4 Little cores:
<pre>
$ ./cpufp --thread_pool=[0-3]
Number Threads: 4
Thread Pool Binding: 0 1 2 3
-------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd | fmla.vs(f32,f32,f32) | 45.029 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 45.027 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 22.509 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 22.513 GFLOPS |
-------------------------------------------------------------
</pre>
For single big core:
<pre>
$ ./cpufp --thread_pool=[4]
Number Threads: 1
Thread Pool Binding: 4
-------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd | fmla.vs(f32,f32,f32) | 14.348 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 14.348 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 7.1744 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 7.1743 GFLOPS |
-------------------------------------------------------------
</pre>
For 2 big cores:
<pre>
$ ./cpufp --thread_pool=[4,5]
Number Threads: 2
Thread Pool Binding: 4 5
-------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd | fmla.vs(f32,f32,f32) | 28.698 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 28.698 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 14.349 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 14.347 GFLOPS |
-------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/arm64/RockChip_RK3588.md
================================================
# RockChip RK3588
Setting: 4 Cortex-A76(big) Cores + 4 Cortex-A55(Little) Cores
For single Little core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd_dp | dp4a.vs(s32,s8,s8) | 58.379 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 58.371 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 58.369 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 58.382 GOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 29.193 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 29.192 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 14.593 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 14.596 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 7.2971 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 7.2972 GFLOPS |
----------------------------------------------------------------
</pre>
For 4 Little cores:
<pre>
$ ./cpufp --thread_pool=[0-3]
Number Threads: 4
Thread Pool Binding: 0 1 2 3
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd_dp | dp4a.vs(s32,s8,s8) | 233.08 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 233.05 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 233.06 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 233.05 GOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 116.54 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 116.51 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 58.261 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 58.258 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 29.13 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 29.126 GFLOPS |
----------------------------------------------------------------
</pre>
For single big core:
<pre>
$ ./cpufp --thread_pool=[4]
Number Threads: 1
Thread Pool Binding: 4
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd_dp | dp4a.vs(s32,s8,s8) | 152.1 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 152.1 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 152.06 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 152.08 GOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 76.022 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 76.027 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 38.012 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 38.008 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 19.004 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 19.004 GFLOPS |
----------------------------------------------------------------
</pre>
For 4 big cores:
<pre>
$ ./cpufp --thread_pool=[4-7]
Number Threads: 4
Thread Pool Binding: 4 5 6 7
----------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| asimd_dp | dp4a.vs(s32,s8,s8) | 601.71 GOPS |
| asimd_dp | dp4a.vv(s32,s8,s8) | 602.2 GOPS |
| asimd_dp | dp4a.vs(u32,u8,u8) | 602.22 GOPS |
| asimd_dp | dp4a.vv(u32,u8,u8) | 602.2 GOPS |
| asimd_hp | fmla.vs(fp16,fp16,fp16) | 300.97 GFLOPS |
| asimd_hp | fmla.vv(fp16,fp16,fp16) | 300.93 GFLOPS |
| asimd | fmla.vs(f32,f32,f32) | 149.79 GFLOPS |
| asimd | fmla.vv(f32,f32,f32) | 150.15 GFLOPS |
| asimd | fmla.vs(f64,f64,f64) | 75.222 GFLOPS |
| asimd | fmla.vv(f64,f64,f64) | 75.215 GFLOPS |
----------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/e2k/Elbrus_4C.md
================================================
# Elbrus-4C
Setting: 4 Sockets x 4 Elbrus-v3
Freqency: 750 MHz
For single core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| v1 | ADD(MUL(f32,f32),f32) | 11.939 GFLOPS |
| v1 | ADD(MUL(f64,f64),f64) | 5.9801 GFLOPS |
--------------------------------------------------------------
</pre>
For 4 cores:
<pre>
$ ./cpufp --thread_pool=[0-3]
Number Threads: 4
Thread Pool Binding: 0 1 2 3
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| v1 | ADD(MUL(f32,f32),f32) | 47.704 GFLOPS |
| v1 | ADD(MUL(f64,f64),f64) | 23.913 GFLOPS |
--------------------------------------------------------------
</pre>
For 16 cores:
<pre>
$ ./cpufp --thread_pool=[0-15]
Number Threads: 16
Thread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| v1 | ADD(MUL(f32,f32),f32) | 189.81 GFLOPS |
| v1 | ADD(MUL(f64,f64),f64) | 95.294 GFLOPS |
--------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/e2k/Elbrus_8C.md
================================================
# Elbrus-8C
Setting: 4 Sockets x 8 Elbrus-v4
Frequency: 1.2 GHz
For single core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| v4 | ADD(MUL(f32,f32),f32) | 28.704 GFLOPS |
| v4 | ADD(MUL(f64,f64),f64) | 14.353 GFLOPS |
--------------------------------------------------------------
</pre>
For 8 cores:
<pre>
$ ./cpufp --thread_pool=[0-7]
Number Threads: 8
Thread Pool Binding: 0 1 2 3 4 5 6 7
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| v4 | ADD(MUL(f32,f32),f32) | 229.42 GFLOPS |
| v4 | ADD(MUL(f64,f64),f64) | 114.56 GFLOPS |
--------------------------------------------------------------
</pre>
For 32 cores:
<pre>
$ ./cpufp --thread_pool=[0-31]
Number Threads: 32
Thread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| v4 | ADD(MUL(f32,f32),f32) | 896.58 GFLOPS |
| v4 | ADD(MUL(f64,f64),f64) | 448.7 GFLOPS |
--------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/e2k/Elbrus_8C2.md
================================================
# Elbrus-8C2
Setting: 4 Sockets x 8 Elbrus-v5
Frequency: 1.2 GHz
For single core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| v5 | ADD(MUL(f32,f32),f32) | 57.413 GFLOPS |
| v5 | ADD(MUL(f64,f64),f64) | 28.707 GFLOPS |
| v4 | ADD(MUL(f32,f32),f32) | 28.727 GFLOPS |
| v4 | ADD(MUL(f64,f64),f64) | 14.353 GFLOPS |
--------------------------------------------------------------
</pre>
For 8 cores:
<pre>
$ ./cpufp --thread_pool=[0-7]
Number Threads: 8
Thread Pool Binding: 0 1 2 3 4 5 6 7
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| v5 | ADD(MUL(f32,f32),f32) | 459.61 GFLOPS |
| v5 | ADD(MUL(f64,f64),f64) | 229.72 GFLOPS |
| v4 | ADD(MUL(f32,f32),f32) | 229.76 GFLOPS |
| v4 | ADD(MUL(f64,f64),f64) | 114.89 GFLOPS |
--------------------------------------------------------------
</pre>
For 32 cores:
<pre>
$ ./cpufp --thread_pool=[0-31]
Number Threads: 32
Thread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| v5 | ADD(MUL(f32,f32),f32) | 1.835 TFLOPS |
| v5 | ADD(MUL(f64,f64),f64) | 917.64 GFLOPS |
| v4 | ADD(MUL(f32,f32),f32) | 917.56 GFLOPS |
| v4 | ADD(MUL(f64,f64),f64) | 458.77 GFLOPS |
--------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/loongarch64/Loongson_3A5000M.md
================================================
# Loongson 3A5000M
Setting: 4 LA464 Cores
For single core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
-------------------------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| LASX | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 47.831 GFLOPS |
| LASX | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 23.888 GFLOPS |
| LSX | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 23.918 GFLOPS |
| LSX | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 11.957 GFLOPS |
| FP_SP | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 5.9803 GFLOPS |
| FP_DP | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 5.9803 GFLOPS |
-------------------------------------------------------------------------------
</pre>
For 4 cores:
<pre>
$ ./cpufp --thread_pool=[0-3]
Number Threads: 4
Thread Pool Binding: 0 1 2 3
-------------------------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| LASX | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 190.92 GFLOPS |
| LASX | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 95.47 GFLOPS |
| LSX | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 95.184 GFLOPS |
| LSX | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 47.652 GFLOPS |
| FP_SP | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 23.847 GFLOPS |
| FP_DP | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 23.876 GFLOPS |
-------------------------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/loongarch64/Loongson_3A6000.md
================================================
# Loongson 3A6000
Setting: 4 LA664 Cores
For single core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
------------------------------------------------------------------------------
| Instruction Set | Vector Length | Core Computation | Peak Performance |
|-----------------|---------------|-----------------------|------------------|
| LASX | 256b | fmadd(f32,f32,f32) | 79.781 GFLOPS |
| LASX | 256b | fmadd(f64,f64,f64) | 39.939 GFLOPS |
| LASX | 256b | add(mul(f32,f32),f32) | 79.853 GFLOPS |
| LASX | 256b | add(mul(f64,f64),f64) | 39.937 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| LSX | 128b | fmadd(f32,f32,f32) | 39.916 GFLOPS |
| LSX | 128b | fmadd(f64,f64,f64) | 19.97 GFLOPS |
| LSX | 128b | add(mul(f32,f32),f32) | 39.935 GFLOPS |
| LSX | 128b | add(mul(f64,f64),f64) | 19.968 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| FP_SP | scalar | fmadd(f32,f32,f32) | 9.9848 GFLOPS |
| FP_DP | scalar | fmadd(f64,f64,f64) | 9.979 GFLOPS |
------------------------------------------------------------------------------
</pre>
For 4 cores:
<pre>
$ ./cpufp --thread_pool=[0,2,4,6]
Number Threads: 4
Thread Pool Binding: 0 2 4 6
------------------------------------------------------------------------------
| Instruction Set | Vector Length | Core Computation | Peak Performance |
|-----------------|---------------|-----------------------|------------------|
| LASX | 256b | fmadd(f32,f32,f32) | 319.54 GFLOPS |
| LASX | 256b | fmadd(f64,f64,f64) | 159.71 GFLOPS |
| LASX | 256b | add(mul(f32,f32),f32) | 319.15 GFLOPS |
| LASX | 256b | add(mul(f64,f64),f64) | 159.61 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| LSX | 128b | fmadd(f32,f32,f32) | 159.75 GFLOPS |
| LSX | 128b | fmadd(f64,f64,f64) | 79.876 GFLOPS |
| LSX | 128b | add(mul(f32,f32),f32) | 159.56 GFLOPS |
| LSX | 128b | add(mul(f64,f64),f64) | 79.751 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| FP_SP | scalar | fmadd(f32,f32,f32) | 39.937 GFLOPS |
| FP_DP | scalar | fmadd(f64,f64,f64) | 39.937 GFLOPS |
------------------------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/loongarch64/Loongson_3C5000.md
================================================
# Loongson 3C5000
Setting: 16 LA464 Cores
For single core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
-------------------------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| LASX | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 52.603 GFLOPS |
| LASX | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 26.331 GFLOPS |
| LSX | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 26.323 GFLOPS |
| LSX | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 13.166 GFLOPS |
| FP_SP | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 6.583 GFLOPS |
| FP_DP | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 6.5723 GFLOPS |
-------------------------------------------------------------------------------
</pre>
For 16 cores:
<pre>
$ ./cpufp --thread_pool=[0-15]
Number Threads: 16
Thread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
-------------------------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| LASX | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 841.77 GFLOPS |
| LASX | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 406.52 GFLOPS |
| LSX | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 420.84 GFLOPS |
| LSX | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 210.01 GFLOPS |
| FP_SP | fmadd(f32,f32,f32) + fadd(f32,f32,f32) | 105.21 GFLOPS |
| FP_DP | fmadd(f64,f64,f64) + fadd(f64,f64,f64) | 104.59 GFLOPS |
-------------------------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/riscv64/Kendryte_K230.md
================================================
# Kendryte K230
Setting: 2 C908 Cores
For single core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
---------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| vector | vfmacc.vf(f16,f16,f16) | 25.014 GFLOPS |
| vector | vfmacc.vv(f16,f16,f16) | 25.01 GFLOPS |
| vector | vfmacc.vf(f32,f32,f32) | 12.507 GFLOPS |
| vector | vfmacc.vv(f32,f32,f32) | 12.508 GFLOPS |
| vector | vfmacc.vf(f64,f64,f64) | 6.254 GFLOPS |
| vector | vfmacc.vv(f64,f64,f64) | 6.2541 GFLOPS |
---------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/riscv64/SpacemiT_K1.md
================================================
# SpacemiT K1
Setting: 8 SpacemiT-X60 Cores
For single core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
---------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| ime | vmadot(s32,s8,s8) | 511.53 GOPS |
| ime | vmadotu(u32,u8,u8) | 511.5 GOPS |
| ime | vmadotus(s32,u8,s8) | 511.53 GOPS |
| ime | vmadotsu(s32,s8,u8) | 511.51 GOPS |
| ime | vmadotslide(s32,s8,s8) | 511.51 GOPS |
| vector | vfmacc.vf(f16,f16,f16) | 66.722 GFLOPS |
| vector | vfmacc.vv(f16,f16,f16) | 63.936 GFLOPS |
| vector | vfmacc.vf(f32,f32,f32) | 33.36 GFLOPS |
| vector | vfmacc.vv(f32,f32,f32) | 31.968 GFLOPS |
| vector | vfmacc.vf(f64,f64,f64) | 16.679 GFLOPS |
| vector | vfmacc.vv(f64,f64,f64) | 15.985 GFLOPS |
---------------------------------------------------------------
</pre>
For cluster 0(with ime extension), 4 cores:
<pre>
$ ./cpufp --thread_pool=[0-3]
Number Threads: 4
Thread Pool Binding: 0 1 2 3
---------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| ime | vmadot(s32,s8,s8) | 2.046 TOPS |
| ime | vmadotu(u32,u8,u8) | 2.0462 TOPS |
| ime | vmadotus(s32,u8,s8) | 2.0461 TOPS |
| ime | vmadotsu(s32,s8,u8) | 2.0462 TOPS |
| ime | vmadotslide(s32,s8,s8) | 2.0461 TOPS |
| vector | vfmacc.vf(f16,f16,f16) | 266.88 GFLOPS |
| vector | vfmacc.vv(f16,f16,f16) | 255.75 GFLOPS |
| vector | vfmacc.vf(f32,f32,f32) | 133.43 GFLOPS |
| vector | vfmacc.vv(f32,f32,f32) | 127.85 GFLOPS |
| vector | vfmacc.vf(f64,f64,f64) | 66.709 GFLOPS |
| vector | vfmacc.vv(f64,f64,f64) | 63.935 GFLOPS |
---------------------------------------------------------------
</pre>
For 2 clusters, 8 cores:
<pre>
$ ./cpufp --thread_pool=[0-7]
Number Threads: 8
Thread Pool Binding: 0 1 2 3 4 5 6 7
---------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| vector | vfmacc.vf(f16,f16,f16) | 533.65 GFLOPS |
| vector | vfmacc.vv(f16,f16,f16) | 511.45 GFLOPS |
| vector | vfmacc.vf(f32,f32,f32) | 266.89 GFLOPS |
| vector | vfmacc.vv(f32,f32,f32) | 255.75 GFLOPS |
| vector | vfmacc.vf(f64,f64,f64) | 133.42 GFLOPS |
| vector | vfmacc.vv(f64,f64,f64) | 127.86 GFLOPS |
---------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/x64/AMD_Ryzen7_8845HS.md
================================================
# AMD Ryzen7 8845HS
Architecture: Zen4
Setting: 8 Zen4 Cores
For single core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| AVX512_VNNI | DP4A(s32,u8,s8) | 647.97 GOPS |
| AVX512_VNNI | DP2A(s32,s16,s16) | 324.27 GOPS |
| AVX512_BF16 | DP2A(f32,bf16,bf16) | 324.92 GFLOPS |
| AVX512F | FMA(f32,f32,f32) | 163.58 GFLOPS |
| AVX512F | FMA(f64,f64,f64) | 81.786 GFLOPS |
| FMA | FMA(f32,f32,f32) | 163.57 GFLOPS |
| FMA | FMA(f64,f64,f64) | 81.785 GFLOPS |
| AVX | ADD(MUL(f32,f32),f32) | 157.36 GFLOPS |
| AVX | ADD(MUL(f64,f64),f64) | 79.045 GFLOPS |
| SSE | ADD(MUL(f32,f32),f32) | 80.34 GFLOPS |
| SSE2 | ADD(MUL(f64,f64),f64) | 40.371 GFLOPS |
--------------------------------------------------------------
</pre>
For 8 cores:
<pre>
$ ./cpufp --thread_pool=[0-7]
Number Threads: 8
Thread Pool Binding: 0 1 2 3 4 5 6 7
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| AVX512_VNNI | DP4A(s32,u8,s8) | 5113.8 GOPS |
| AVX512_VNNI | DP2A(s32,s16,s16) | 2559.1 GOPS |
| AVX512_BF16 | DP2A(f32,bf16,bf16) | 2551.6 GFLOPS |
| AVX512F | FMA(f32,f32,f32) | 1283.6 GFLOPS |
| AVX512F | FMA(f64,f64,f64) | 641.21 GFLOPS |
| FMA | FMA(f32,f32,f32) | 1271.7 GFLOPS |
| FMA | FMA(f64,f64,f64) | 632.3 GFLOPS |
| AVX | ADD(MUL(f32,f32),f32) | 1193.6 GFLOPS |
| AVX | ADD(MUL(f64,f64),f64) | 590.85 GFLOPS |
| SSE | ADD(MUL(f32,f32),f32) | 613.54 GFLOPS |
| SSE2 | ADD(MUL(f64,f64),f64) | 307.67 GFLOPS |
--------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/x64/AMD_Ryzen7_9700X.md
================================================
# AMD Ryzen7 9700X
Microarchitecture: Zen5
Setting: 8 Zen5 Cores
For single core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
------------------------------------------------------------------------------
| Instruction Set | Vector Length | Core Computation | Peak Performance |
|-----------------|---------------|-----------------------|------------------|
| AVX512_VNNI | 512b | DP4A(s32,u8,s8) | 1.4172 TOPS |
| AVX512_VNNI | 512b | DP2A(s32,s16,s16) | 708.61 GOPS |
| AVX512_BF16 | 512b | DP2A(f32,bf16,bf16) | 708.19 GFLOPS |
| AVX512F | 512b | FMA(f32,f32,f32) | 354.29 GFLOPS |
| AVX512F | 512b | FMA(f64,f64,f64) | 177.09 GFLOPS |
| AVX512F | 512b | ADD(MUL(f32,f32),f32) | 353.63 GFLOPS |
| AVX512F | 512b | ADD(MUL(f64,f64),f64) | 176.47 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| AVX512_VNNI | 256b | DP4A(s32,u8,s8) | 708.55 GOPS |
| AVX_VNNI | 256b | DP4A(s32,u8,s8) | 708.64 GOPS |
| AVX512_VNNI | 256b | DP2A(s32,s16,s16) | 354.38 GOPS |
| AVX_VNNI | 256b | DP2A(s32,s16,s16) | 354.22 GOPS |
| AVX512_BF16 | 256b | DP2A(f32,bf16,bf16) | 354.39 GFLOPS |
| FMA | 256b | FMA(f32,f32,f32) | 177.14 GFLOPS |
| FMA | 256b | FMA(f64,f64,f64) | 88.565 GFLOPS |
| AVX | 256b | ADD(MUL(f32,f32),f32) | 176.96 GFLOPS |
| AVX | 256b | ADD(MUL(f64,f64),f64) | 88.467 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| AVX512_VNNI | 128b | DP4A(s32,u8,s8) | 354.53 GOPS |
| AVX_VNNI | 128b | DP4A(s32,u8,s8) | 354.53 GOPS |
| AVX512_VNNI | 128b | DP2A(s32,s16,s16) | 177.27 GOPS |
| AVX_VNNI | 128b | DP2A(s32,s16,s16) | 177.24 GOPS |
| AVX512_BF16 | 128b | DP2A(f32,bf16,bf16) | 177.26 GFLOPS |
| FMA | 128b | FMA(f32,f32,f32) | 88.641 GFLOPS |
| FMA | 128b | FMA(f64,f64,f64) | 44.308 GFLOPS |
| SSE | 128b | ADD(MUL(f32,f32),f32) | 88.465 GFLOPS |
| SSE2 | 128b | ADD(MUL(f64,f64),f64) | 44.259 GFLOPS |
------------------------------------------------------------------------------
</pre>
For 8 cores:
<pre>
$ ./cpufp --thread_pool=[0-7]
Number Threads: 8
Thread Pool Binding: 0 1 2 3 4 5 6 7
------------------------------------------------------------------------------
| Instruction Set | Vector Length | Core Computation | Peak Performance |
|-----------------|---------------|-----------------------|------------------|
| AVX512_VNNI | 512b | DP4A(s32,u8,s8) | 11.064 TOPS |
| AVX512_VNNI | 512b | DP2A(s32,s16,s16) | 5.5293 TOPS |
| AVX512_BF16 | 512b | DP2A(f32,bf16,bf16) | 5.5324 TFLOPS |
| AVX512F | 512b | FMA(f32,f32,f32) | 2.7598 TFLOPS |
| AVX512F | 512b | FMA(f64,f64,f64) | 1.3768 TFLOPS |
| AVX512F | 512b | ADD(MUL(f32,f32),f32) | 2.7312 TFLOPS |
| AVX512F | 512b | ADD(MUL(f64,f64),f64) | 1.3605 TFLOPS |
|-----------------|---------------|-----------------------|------------------|
| AVX512_VNNI | 256b | DP4A(s32,u8,s8) | 5.5604 TOPS |
| AVX_VNNI | 256b | DP4A(s32,u8,s8) | 5.5592 TOPS |
| AVX512_VNNI | 256b | DP2A(s32,s16,s16) | 2.7816 TOPS |
| AVX_VNNI | 256b | DP2A(s32,s16,s16) | 2.7783 TOPS |
| AVX512_BF16 | 256b | DP2A(f32,bf16,bf16) | 2.7814 TFLOPS |
| FMA | 256b | FMA(f32,f32,f32) | 1.3884 TFLOPS |
| FMA | 256b | FMA(f64,f64,f64) | 694.02 GFLOPS |
| AVX | 256b | ADD(MUL(f32,f32),f32) | 1.3781 TFLOPS |
| AVX | 256b | ADD(MUL(f64,f64),f64) | 688.82 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| AVX512_VNNI | 128b | DP4A(s32,u8,s8) | 2.7881 TOPS |
| AVX_VNNI | 128b | DP4A(s32,u8,s8) | 2.7881 TOPS |
| AVX512_VNNI | 128b | DP2A(s32,s16,s16) | 1.3938 TOPS |
| AVX_VNNI | 128b | DP2A(s32,s16,s16) | 1.3938 TOPS |
| AVX512_BF16 | 128b | DP2A(f32,bf16,bf16) | 1.3958 TFLOPS |
| FMA | 128b | FMA(f32,f32,f32) | 696.63 GFLOPS |
| FMA | 128b | FMA(f64,f64,f64) | 348.12 GFLOPS |
| SSE | 128b | ADD(MUL(f32,f32),f32) | 686.34 GFLOPS |
| SSE2 | 128b | ADD(MUL(f64,f64),f64) | 344.64 GFLOPS |
------------------------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/x64/AMD_Ryzen9_6900HX.md
================================================
# AMD Ryzen9 6900HX
Architecture: Zen3+
Setting: 8 Zen3+ Cores
For single core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| FMA | FMA(f32,f32,f32) | 151.84 GFLOPS |
| FMA | FMA(f64,f64,f64) | 75.702 GFLOPS |
| AVX | ADD(MUL(f32,f32),f32) | 150.86 GFLOPS |
| AVX | ADD(MUL(f64,f64),f64) | 75.476 GFLOPS |
| SSE | ADD(MUL(f32,f32),f32) | 75.452 GFLOPS |
| SSE2 | ADD(MUL(f64,f64),f64) | 37.737 GFLOPS |
--------------------------------------------------------------
</pre>
For 8 cores:
<pre>
$ ./cpufp --thread_pool=[0,2,4,6,8,10,12,14]
Number Threads: 8
Thread Pool Binding: 0 2 4 6 8 10 12 14
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| FMA | FMA(f32,f32,f32) | 1057.8 GFLOPS |
| FMA | FMA(f64,f64,f64) | 534.37 GFLOPS |
| AVX | ADD(MUL(f32,f32),f32) | 1037.6 GFLOPS |
| AVX | ADD(MUL(f64,f64),f64) | 516.21 GFLOPS |
| SSE | ADD(MUL(f32,f32),f32) | 518.32 GFLOPS |
| SSE2 | ADD(MUL(f64,f64),f64) | 258.92 GFLOPS |
--------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/x64/Intel_Core_i3_8121U.md
================================================
# Intel Core i3-8121U
Product Code Name: Cannon-Lake
Setting: 2 Cannon-Lake Cores
For single Core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
------------------------------------------------------------------------------
| Instruction Set | Vector Length | Core Computation | Peak Performance |
|-----------------|---------------|-----------------------|------------------|
| AVX512F | 512b | FMA(f32,f32,f32) | 101.56 GFLOPS |
| AVX512F | 512b | FMA(f64,f64,f64) | 50.784 GFLOPS |
| AVX512F | 512b | ADD(MUL(f32,f32),f32) | 50.783 GFLOPS |
| AVX512F | 512b | ADD(MUL(f64,f64),f64) | 25.391 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| FMA | 256b | FMA(f32,f32,f32) | 101.55 GFLOPS |
| FMA | 256b | FMA(f64,f64,f64) | 50.803 GFLOPS |
| AVX | 256b | ADD(MUL(f32,f32),f32) | 50.744 GFLOPS |
| AVX | 256b | ADD(MUL(f64,f64),f64) | 25.39 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| FMA | 128b | FMA(f32,f32,f32) | 50.772 GFLOPS |
| FMA | 128b | FMA(f64,f64,f64) | 25.376 GFLOPS |
| SSE | 128b | ADD(MUL(f32,f32),f32) | 12.69 GFLOPS |
| SSE2 | 128b | ADD(MUL(f64,f64),f64) | 6.3453 GFLOPS |
------------------------------------------------------------------------------
</pre>
For 2 Cores:
<pre>
$ ./cpufp --thread_pool=[0,1]
Number Threads: 2
Thread Pool Binding: 0 1
------------------------------------------------------------------------------
| Instruction Set | Vector Length | Core Computation | Peak Performance |
|-----------------|---------------|-----------------------|------------------|
| AVX512F | 512b | FMA(f32,f32,f32) | 197.25 GFLOPS |
| AVX512F | 512b | FMA(f64,f64,f64) | 98.624 GFLOPS |
| AVX512F | 512b | ADD(MUL(f32,f32),f32) | 98.62 GFLOPS |
| AVX512F | 512b | ADD(MUL(f64,f64),f64) | 49.315 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| FMA | 256b | FMA(f32,f32,f32) | 197.18 GFLOPS |
| FMA | 256b | FMA(f64,f64,f64) | 98.594 GFLOPS |
| AVX | 256b | ADD(MUL(f32,f32),f32) | 98.64 GFLOPS |
| AVX | 256b | ADD(MUL(f64,f64),f64) | 49.304 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| FMA | 128b | FMA(f32,f32,f32) | 98.629 GFLOPS |
| FMA | 128b | FMA(f64,f64,f64) | 49.319 GFLOPS |
| SSE | 128b | ADD(MUL(f32,f32),f32) | 24.658 GFLOPS |
| SSE2 | 128b | ADD(MUL(f64,f64),f64) | 12.326 GFLOPS |
------------------------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/x64/Intel_Core_i5_1340P.md
================================================
# Intel Core i5-1340P
Product Code Name: Raptor Lake
Setting: 4 Raptor Cove(P-Core) Cores + 8 Gracemont(E-Core) Cores
For single P-Core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| AVX_VNNI | DP4A(s32,u8,s8) | 586.84 Gops |
| AVX_VNNI | DP2A(s32,s16,s16) | 293.5 Gops |
| FMA | FMA(f32,f32,f32) | 146.76 Gflops |
| FMA | FMA(f64,f64,f64) | 73.373 Gflops |
| AVX | ADD(MUL(f32,f32),f32) | 107.7 Gflops |
| AVX | ADD(MUL(f64,f64),f64) | 53.512 Gflops |
| SSE | ADD(MUL(f32,f32),f32) | 54.49 Gflops |
| SSE2 | ADD(MUL(f64,f64),f64) | 27.243 Gflops |
--------------------------------------------------------------
</pre>
For 4 P-Cores:
<pre>
$ ./cpufp --thread_pool=[0,2,4,6]
Number Threads: 4
Thread Pool Binding: 0 2 4 6
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| AVX_VNNI | DP4A(s32,u8,s8) | 2.2454 Tops |
| AVX_VNNI | DP2A(s32,s16,s16) | 1.1215 Tops |
| FMA | FMA(f32,f32,f32) | 546.31 Gflops |
| FMA | FMA(f64,f64,f64) | 267.62 Gflops |
| AVX | ADD(MUL(f32,f32),f32) | 356.72 Gflops |
| AVX | ADD(MUL(f64,f64),f64) | 176.89 Gflops |
| SSE | ADD(MUL(f32,f32),f32) | 183.39 Gflops |
| SSE2 | ADD(MUL(f64,f64),f64) | 91.293 Gflops |
--------------------------------------------------------------
</pre>
For single E-Core:
<pre>
$ ./cpufp --thread_pool=[8]
Number Threads: 1
Thread Pool Binding: 8
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| AVX_VNNI | DP4A(s32,u8,s8) | 108.5 Gops |
| AVX_VNNI | DP2A(s32,s16,s16) | 54.251 Gops |
| FMA | FMA(f32,f32,f32) | 54.248 Gflops |
| FMA | FMA(f64,f64,f64) | 27.125 Gflops |
| AVX | ADD(MUL(f32,f32),f32) | 27.126 Gflops |
| AVX | ADD(MUL(f64,f64),f64) | 13.563 Gflops |
| SSE | ADD(MUL(f32,f32),f32) | 27.122 Gflops |
| SSE2 | ADD(MUL(f64,f64),f64) | 13.561 Gflops |
--------------------------------------------------------------
</pre>
For 8 E-Cores:
<pre>
$ ./cpufp --thread_pool=[8-15]
Number Threads: 8
Thread Pool Binding: 8 9 10 11 12 13 14 15
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| AVX_VNNI | DP4A(s32,u8,s8) | 791.36 Gops |
| AVX_VNNI | DP2A(s32,s16,s16) | 395.68 Gops |
| FMA | FMA(f32,f32,f32) | 395.67 Gflops |
| FMA | FMA(f64,f64,f64) | 197.83 Gflops |
| AVX | ADD(MUL(f32,f32),f32) | 197.84 Gflops |
| AVX | ADD(MUL(f64,f64),f64) | 98.921 Gflops |
| SSE | ADD(MUL(f32,f32),f32) | 197.83 Gflops |
| SSE2 | ADD(MUL(f64,f64),f64) | 98.916 Gflops |
--------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/x64/Intel_N150.md
================================================
# Intel N150
Product Code Name: Twin-Lake
Setting: 4 Gracemont Cores
For single core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
------------------------------------------------------------------------------
| Instruction Set | Vector Length | Core Computation | Peak Performance |
|-----------------|---------------|-----------------------|------------------|
| AVX_VNNI | 256b | DP4A(s32,u8,s8) | 114.75 GOPS |
| AVX_VNNI | 256b | DP2A(s32,s16,s16) | 57.372 GOPS |
| FMA | 256b | FMA(f32,f32,f32) | 57.374 GFLOPS |
| FMA | 256b | FMA(f64,f64,f64) | 28.608 GFLOPS |
| AVX | 256b | ADD(MUL(f32,f32),f32) | 28.688 GFLOPS |
| AVX | 256b | ADD(MUL(f64,f64),f64) | 14.344 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| AVX_VNNI | 128b | DP4A(s32,u8,s8) | 114.75 GOPS |
| AVX_VNNI | 128b | DP2A(s32,s16,s16) | 57.352 GOPS |
| FMA | 128b | FMA(f32,f32,f32) | 56.509 GFLOPS |
| FMA | 128b | FMA(f64,f64,f64) | 28.259 GFLOPS |
| SSE | 128b | ADD(MUL(f32,f32),f32) | 28.685 GFLOPS |
| SSE2 | 128b | ADD(MUL(f64,f64),f64) | 14.34 GFLOPS |
------------------------------------------------------------------------------
</pre>
For 4 cores:
<pre>
$ ./cpufp --thread_pool=[0-3]
Number Threads: 4
Thread Pool Binding: 0 1 2 3
------------------------------------------------------------------------------
| Instruction Set | Vector Length | Core Computation | Peak Performance |
|-----------------|---------------|-----------------------|------------------|
| AVX_VNNI | 256b | DP4A(s32,u8,s8) | 369.64 GOPS |
| AVX_VNNI | 256b | DP2A(s32,s16,s16) | 184.83 GOPS |
| FMA | 256b | FMA(f32,f32,f32) | 179.63 GFLOPS |
| FMA | 256b | FMA(f64,f64,f64) | 89.945 GFLOPS |
| AVX | 256b | ADD(MUL(f32,f32),f32) | 91.402 GFLOPS |
| AVX | 256b | ADD(MUL(f64,f64),f64) | 45.469 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| AVX_VNNI | 128b | DP4A(s32,u8,s8) | 369.7 GOPS |
| AVX_VNNI | 128b | DP2A(s32,s16,s16) | 184.84 GOPS |
| FMA | 128b | FMA(f32,f32,f32) | 171.99 GFLOPS |
| FMA | 128b | FMA(f64,f64,f64) | 86.56 GFLOPS |
| SSE | 128b | ADD(MUL(f32,f32),f32) | 88.764 GFLOPS |
| SSE2 | 128b | ADD(MUL(f64,f64),f64) | 44.468 GFLOPS |
------------------------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/x64/Intel_Ultra7_255H.md
================================================
# Intel Ultra7 255H
Product Code Name: Arrow Lake-H
Setting: 6 Lion Cove P-Cores + 8 Skymont E-Cores + 2 (Unknown Arch) LPE-Cores
For single P-Core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
------------------------------------------------------------------------------
| Instruction Set | Vector Length | Core Computation | Peak Performance |
|-----------------|---------------|-----------------------|------------------|
| AVX_VNNI | 256b | DP4A(s32,u8,s8) | 647.06 GOPS |
| AVX_VNNI_INT8 | 256b | DP4A(s32,s8,s8) | 646.81 GOPS |
| AVX_VNNI_INT8 | 256b | DP4A(s32,s8,u8) | 647.17 GOPS |
| AVX_VNNI_INT8 | 256b | DP4A(s32,u8,u8) | 646.86 GOPS |
| AVX_VNNI | 256b | DP2A(s32,s16,s16) | 323.05 GOPS |
| FMA | 256b | FMA(f32,f32,f32) | 161.55 GFLOPS |
| FMA | 256b | FMA(f64,f64,f64) | 80.961 GFLOPS |
| AVX | 256b | ADD(MUL(f32,f32),f32) | 132.12 GFLOPS |
| AVX | 256b | ADD(MUL(f64,f64),f64) | 66.11 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| AVX_VNNI | 128b | DP4A(s32,u8,s8) | 323.03 GOPS |
| AVX_VNNI_INT8 | 128b | DP4A(s32,s8,s8) | 323.55 GOPS |
| AVX_VNNI_INT8 | 128b | DP4A(s32,s8,u8) | 323.24 GOPS |
| AVX_VNNI_INT8 | 128b | DP4A(s32,u8,u8) | 323.2 GOPS |
| AVX_VNNI | 128b | DP2A(s32,s16,s16) | 161.58 GOPS |
| FMA | 128b | FMA(f32,f32,f32) | 80.786 GFLOPS |
| FMA | 128b | FMA(f64,f64,f64) | 40.381 GFLOPS |
| SSE | 128b | ADD(MUL(f32,f32),f32) | 67.709 GFLOPS |
| SSE2 | 128b | ADD(MUL(f64,f64),f64) | 33.791 GFLOPS |
------------------------------------------------------------------------------
</pre>
For 6 P-Cores:
<pre>
$ ./cpufp --thread_pool=[0-5]
Number Threads: 6
Thread Pool Binding: 0 1 2 3 4 5
------------------------------------------------------------------------------
| Instruction Set | Vector Length | Core Computation | Peak Performance |
|-----------------|---------------|-----------------------|------------------|
| AVX_VNNI | 256b | DP4A(s32,u8,s8) | 3.4864 TOPS |
| AVX_VNNI_INT8 | 256b | DP4A(s32,s8,s8) | 3.4477 TOPS |
| AVX_VNNI_INT8 | 256b | DP4A(s32,s8,u8) | 3.416 TOPS |
| AVX_VNNI_INT8 | 256b | DP4A(s32,u8,u8) | 3.4142 TOPS |
| AVX_VNNI | 256b | DP2A(s32,s16,s16) | 1.7058 TOPS |
| FMA | 256b | FMA(f32,f32,f32) | 854.05 GFLOPS |
| FMA | 256b | FMA(f64,f64,f64) | 426.89 GFLOPS |
| AVX | 256b | ADD(MUL(f32,f32),f32) | 710.61 GFLOPS |
| AVX | 256b | ADD(MUL(f64,f64),f64) | 355.38 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| AVX_VNNI | 128b | DP4A(s32,u8,s8) | 1.7078 TOPS |
| AVX_VNNI_INT8 | 128b | DP4A(s32,s8,s8) | 1.7078 TOPS |
| AVX_VNNI_INT8 | 128b | DP4A(s32,s8,u8) | 1.7081 TOPS |
| AVX_VNNI_INT8 | 128b | DP4A(s32,u8,u8) | 1.7087 TOPS |
| AVX_VNNI | 128b | DP2A(s32,s16,s16) | 853.72 GOPS |
| FMA | 128b | FMA(f32,f32,f32) | 426.93 GFLOPS |
| FMA | 128b | FMA(f64,f64,f64) | 213.29 GFLOPS |
| SSE | 128b | ADD(MUL(f32,f32),f32) | 354.37 GFLOPS |
| SSE2 | 128b | ADD(MUL(f64,f64),f64) | 178.34 GFLOPS |
------------------------------------------------------------------------------
</pre>
For single E-Core:
<pre>
$ ./cpufp --thread_pool=[6]
Number Threads: 1
Thread Pool Binding: 6
------------------------------------------------------------------------------
| Instruction Set | Vector Length | Core Computation | Peak Performance |
|-----------------|---------------|-----------------------|------------------|
| AVX_VNNI | 256b | DP4A(s32,u8,s8) | 561.38 GOPS |
| AVX_VNNI_INT8 | 256b | DP4A(s32,s8,s8) | 561.39 GOPS |
| AVX_VNNI_INT8 | 256b | DP4A(s32,s8,u8) | 561.43 GOPS |
| AVX_VNNI_INT8 | 256b | DP4A(s32,u8,u8) | 561.43 GOPS |
| AVX_VNNI | 256b | DP2A(s32,s16,s16) | 280.72 GOPS |
| FMA | 256b | FMA(f32,f32,f32) | 140.35 GFLOPS |
| FMA | 256b | FMA(f64,f64,f64) | 70.175 GFLOPS |
| AVX | 256b | ADD(MUL(f32,f32),f32) | 70.177 GFLOPS |
| AVX | 256b | ADD(MUL(f64,f64),f64) | 35.089 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| AVX_VNNI | 128b | DP4A(s32,u8,s8) | 449.23 GOPS |
| AVX_VNNI_INT8 | 128b | DP4A(s32,s8,s8) | 449.91 GOPS |
| AVX_VNNI_INT8 | 128b | DP4A(s32,s8,u8) | 449.35 GOPS |
| AVX_VNNI_INT8 | 128b | DP4A(s32,u8,u8) | 449.5 GOPS |
| AVX_VNNI | 128b | DP2A(s32,s16,s16) | 224.62 GOPS |
| FMA | 128b | FMA(f32,f32,f32) | 113.49 GFLOPS |
| FMA | 128b | FMA(f64,f64,f64) | 56.793 GFLOPS |
| SSE | 128b | ADD(MUL(f32,f32),f32) | 70.099 GFLOPS |
| SSE2 | 128b | ADD(MUL(f64,f64),f64) | 35.043 GFLOPS |
------------------------------------------------------------------------------
</pre>
For 8 E-Cores:
<pre>
$ ./cpufp --thread_pool=[6-13]
Number Threads: 8
Thread Pool Binding: 6 7 8 9 10 11 12 13
------------------------------------------------------------------------------
| Instruction Set | Vector Length | Core Computation | Peak Performance |
|-----------------|---------------|-----------------------|------------------|
| AVX_VNNI | 256b | DP4A(s32,u8,s8) | 4.1754 TOPS |
| AVX_VNNI_INT8 | 256b | DP4A(s32,s8,s8) | 4.1767 TOPS |
| AVX_VNNI_INT8 | 256b | DP4A(s32,s8,u8) | 4.1732 TOPS |
| AVX_VNNI_INT8 | 256b | DP4A(s32,u8,u8) | 4.1708 TOPS |
| AVX_VNNI | 256b | DP2A(s32,s16,s16) | 2.0668 TOPS |
| FMA | 256b | FMA(f32,f32,f32) | 1.029 TFLOPS |
| FMA | 256b | FMA(f64,f64,f64) | 513.76 GFLOPS |
| AVX | 256b | ADD(MUL(f32,f32),f32) | 511.26 GFLOPS |
| AVX | 256b | ADD(MUL(f64,f64),f64) | 254.99 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| AVX_VNNI | 128b | DP4A(s32,u8,s8) | 3.26 TOPS |
| AVX_VNNI_INT8 | 128b | DP4A(s32,s8,s8) | 3.2669 TOPS |
| AVX_VNNI_INT8 | 128b | DP4A(s32,s8,u8) | 3.2702 TOPS |
| AVX_VNNI_INT8 | 128b | DP4A(s32,u8,u8) | 3.2616 TOPS |
| AVX_VNNI | 128b | DP2A(s32,s16,s16) | 1.6311 TOPS |
| FMA | 128b | FMA(f32,f32,f32) | 824.83 GFLOPS |
| FMA | 128b | FMA(f64,f64,f64) | 412.47 GFLOPS |
| SSE | 128b | ADD(MUL(f32,f32),f32) | 509.08 GFLOPS |
| SSE2 | 128b | ADD(MUL(f64,f64),f64) | 254.62 GFLOPS |
------------------------------------------------------------------------------
</pre>
For single LPE-Core:
<pre>
$ ./cpufp --thread_pool=[14]
Number Threads: 1
Thread Pool Binding: 14
------------------------------------------------------------------------------
| Instruction Set | Vector Length | Core Computation | Peak Performance |
|-----------------|---------------|-----------------------|------------------|
| AVX_VNNI | 256b | DP4A(s32,u8,s8) | 157.12 GOPS |
| AVX_VNNI_INT8 | 256b | DP4A(s32,s8,s8) | 157 GOPS |
| AVX_VNNI_INT8 | 256b | DP4A(s32,s8,u8) | 157.02 GOPS |
| AVX_VNNI_INT8 | 256b | DP4A(s32,u8,u8) | 156.96 GOPS |
| AVX_VNNI | 256b | DP2A(s32,s16,s16) | 78.469 GOPS |
| FMA | 256b | FMA(f32,f32,f32) | 39.237 GFLOPS |
| FMA | 256b | FMA(f64,f64,f64) | 19.624 GFLOPS |
| AVX | 256b | ADD(MUL(f32,f32),f32) | 19.63 GFLOPS |
| AVX | 256b | ADD(MUL(f64,f64),f64) | 9.8176 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| AVX_VNNI | 128b | DP4A(s32,u8,s8) | 156.93 GOPS |
| AVX_VNNI_INT8 | 128b | DP4A(s32,s8,s8) | 157.11 GOPS |
| AVX_VNNI_INT8 | 128b | DP4A(s32,s8,u8) | 156.99 GOPS |
| AVX_VNNI_INT8 | 128b | DP4A(s32,u8,u8) | 156.87 GOPS |
| AVX_VNNI | 128b | DP2A(s32,s16,s16) | 78.453 GOPS |
| FMA | 128b | FMA(f32,f32,f32) | 39.312 GFLOPS |
| FMA | 128b | FMA(f64,f64,f64) | 19.628 GFLOPS |
| SSE | 128b | ADD(MUL(f32,f32),f32) | 19.615 GFLOPS |
| SSE2 | 128b | ADD(MUL(f64,f64),f64) | 9.8155 GFLOPS |
------------------------------------------------------------------------------
</pre>
For 2 LPE-Cores:
<pre>
$ ./cpufp --thread_pool=[14,15]
Number Threads: 2
Thread Pool Binding: 14 15
------------------------------------------------------------------------------
| Instruction Set | Vector Length | Core Computation | Peak Performance |
|-----------------|---------------|-----------------------|------------------|
| AVX_VNNI | 256b | DP4A(s32,u8,s8) | 316.22 GOPS |
| AVX_VNNI_INT8 | 256b | DP4A(s32,s8,s8) | 316.14 GOPS |
| AVX_VNNI_INT8 | 256b | DP4A(s32,s8,u8) | 315.76 GOPS |
| AVX_VNNI_INT8 | 256b | DP4A(s32,u8,u8) | 316.06 GOPS |
| AVX_VNNI | 256b | DP2A(s32,s16,s16) | 158.13 GOPS |
| FMA | 256b | FMA(f32,f32,f32) | 79.052 GFLOPS |
| FMA | 256b | FMA(f64,f64,f64) | 39.483 GFLOPS |
| AVX | 256b | ADD(MUL(f32,f32),f32) | 39.472 GFLOPS |
| AVX | 256b | ADD(MUL(f64,f64),f64) | 19.759 GFLOPS |
|-----------------|---------------|-----------------------|------------------|
| AVX_VNNI | 128b | DP4A(s32,u8,s8) | 315.74 GOPS |
| AVX_VNNI_INT8 | 128b | DP4A(s32,s8,s8) | 316.01 GOPS |
| AVX_VNNI_INT8 | 128b | DP4A(s32,s8,u8) | 315.23 GOPS |
| AVX_VNNI_INT8 | 128b | DP4A(s32,u8,u8) | 316.03 GOPS |
| AVX_VNNI | 128b | DP2A(s32,s16,s16) | 157.66 GOPS |
| FMA | 128b | FMA(f32,f32,f32) | 79.005 GFLOPS |
| FMA | 128b | FMA(f64,f64,f64) | 39.435 GFLOPS |
| SSE | 128b | ADD(MUL(f32,f32),f32) | 39.406 GFLOPS |
| SSE2 | 128b | ADD(MUL(f64,f64),f64) | 19.723 GFLOPS |
------------------------------------------------------------------------------
</pre>
================================================
FILE: benchmark_result/x64/Intel_Xeon_Gold_6455B.md
================================================
# Intel Xeon Gold 6455B
Microarchitecture: Sapphire Rapids
Setting: 2 Sockets x 32 Golden Cove Cores
For single core:
<pre>
$ ./cpufp --thread_pool=[0]
Number Threads: 1
Thread Pool Binding: 0
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| AMX_INT8 | MM(s32,s8,s8) | 6.3726 Tops |
| AMX_INT8 | MM(s32,s8,u8) | 7.5746 Tops |
| AMX_INT8 | MM(s32,u8,s8) | 7.5733 Tops |
| AMX_INT8 | MM(s32,u8,u8) | 7.5718 Tops |
| AMX_BF16 | MM(f32,bf16,bf16) | 3.7868 Tflops |
| AVX512_VNNI | DP4A(s32,u8,s8) | 998.07 Gops |
| AVX512_VNNI | DP2A(s32,s16,s16) | 499.07 Gops |
| AVX_VNNI | DP4A(s32,u8,s8) | 498.96 Gops |
| AVX_VNNI | DP2A(s32,s16,s16) | 249.47 Gops |
| AVX512_BF16 | DP2A(f32,bf16,bf16) | 115.16 Gflops |
| AVX512_FP16 | FMA(f16,f16,f16) | 499.08 Gflops |
| AVX512F | FMA(f32,f32,f32) | 230.28 Gflops |
| AVX512F | FMA(f64,f64,f64) | 115.17 Gflops |
| FMA | FMA(f32,f32,f32) | 118.35 Gflops |
| FMA | FMA(f64,f64,f64) | 62.385 Gflops |
| AVX | ADD(MUL(f32,f32),f32) | 91.59 Gflops |
| AVX | ADD(MUL(f64,f64),f64) | 45.85 Gflops |
| SSE | ADD(MUL(f32,f32),f32) | 46.493 Gflops |
| SSE2 | ADD(MUL(f64,f64),f64) | 23.235 Gflops |
--------------------------------------------------------------
</pre>
For 64 cores:
<pre>
$ ./cpufp --thread_pool=[0-63]
Number Threads: 64
Thread Pool Binding: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
--------------------------------------------------------------
| Instruction Set | Core Computation | Peak Performance |
| AMX_INT8 | MM(s32,s8,s8) | 390.67 Tops |
| AMX_INT8 | MM(s32,s8,u8) | 380.93 Tops |
| AMX_INT8 | MM(s32,u8,s8) | 391.32 Tops |
| AMX_INT8 | MM(s32,u8,u8) | 380.28 Tops |
| AMX_BF16 | MM(f32,bf16,bf16) | 192.47 Tflops |
| AVX512_VNNI | DP4A(s32,u8,s8) | 48.114 Tops |
| AVX512_VNNI | DP2A(s32,s16,s16) | 24.169 Tops |
| AVX_VNNI | DP4A(s32,u8,s8) | 30.818 Tops |
| AVX_VNNI | DP2A(s32,s16,s16) | 15.74 Tops |
| AVX512_BF16 | DP2A(f32,bf16,bf16) | 7.09 Tflops |
| AVX512_FP16 | FMA(f16,f16,f16) | 31.473 Tflops |
| AVX512F | FMA(f32,f32,f32) | 14.329 Tflops |
| AVX512F | FMA(f64,f64,f64) | 6.5406 Tflops |
| FMA | FMA(f32,f32,f32) | 7.4039 Tflops |
| FMA | FMA(f64,f64,f64) | 3.9067 Tflops |
| AVX | ADD(MUL(f32,f32),f32) | 5.4087 Tflops |
| AVX | ADD(MUL(f64,f64),f64) | 2.7339 Tflops |
| SSE | ADD(MUL(f32,f32),f32) | 2.9077 Tflops |
| SSE2 | ADD(MUL(f
gitextract_2p1llcmt/
├── .gitignore
├── LICENSE
├── README.md
├── arm64/
│ ├── asm/
│ │ ├── _ASIMD_.S
│ │ ├── _ASIMD_DP_.S
│ │ ├── _ASIMD_HP_.S
│ │ ├── _BF16_.S
│ │ └── _I8MM_.S
│ ├── cpufp.cpp
│ └── cpuid.c
├── benchmark_result/
│ ├── arm64/
│ │ ├── AWS_Graviton_3E.md
│ │ ├── Apple_Silicon_M2_Max.md
│ │ ├── Apple_Silicon_M4_Max.md
│ │ ├── Broadcom_BCM2711.md
│ │ ├── Broadcom_BCM2712.md
│ │ ├── CIX_P1_CD8180.md
│ │ ├── HUAWEI_Kunpeng_920_7260.md
│ │ ├── HUAWEI_Kunpeng_D920_2249K.md
│ │ ├── Phytium_D2000.md
│ │ ├── Qualcomm_Snapdragon_X_Elite_X1E80100.md
│ │ ├── RockChip_RK3399.md
│ │ └── RockChip_RK3588.md
│ ├── e2k/
│ │ ├── Elbrus_4C.md
│ │ ├── Elbrus_8C.md
│ │ └── Elbrus_8C2.md
│ ├── loongarch64/
│ │ ├── Loongson_3A5000M.md
│ │ ├── Loongson_3A6000.md
│ │ └── Loongson_3C5000.md
│ ├── riscv64/
│ │ ├── Kendryte_K230.md
│ │ └── SpacemiT_K1.md
│ └── x64/
│ ├── AMD_Ryzen7_8845HS.md
│ ├── AMD_Ryzen7_9700X.md
│ ├── AMD_Ryzen9_6900HX.md
│ ├── Intel_Core_i3_8121U.md
│ ├── Intel_Core_i5_1340P.md
│ ├── Intel_N150.md
│ ├── Intel_Ultra7_255H.md
│ ├── Intel_Xeon_Gold_6455B.md
│ ├── Intel_Xeon_W9_3495X.md
│ └── ZHAOXIN_KX_6640MA.md
├── build_arm64.sh
├── build_e2k.sh
├── build_loongarch64.sh
├── build_riscv64.sh
├── build_x64.sh
├── clean.sh
├── common/
│ ├── smtl.cpp
│ ├── smtl.hpp
│ ├── table.cpp
│ └── table.hpp
├── e2k/
│ ├── asm.S
│ └── cpufp.cpp
├── loongarch64/
│ ├── asm/
│ │ ├── _FP_DP_.S
│ │ ├── _FP_SP_.S
│ │ ├── _LASX_.S
│ │ └── _LSX_.S
│ ├── cpufp.cpp
│ └── cpuid.c
├── riscv64/
│ ├── asm/
│ │ ├── _IME_.S
│ │ └── _VECTOR_.S
│ ├── cpufp.cpp
│ └── cpuid.c
└── x64/
├── asm/
│ ├── _AMX_BF16_.S
│ ├── _AMX_FP16_.S
│ ├── _AMX_INT8_.S
│ ├── _AVX512F_.S
│ ├── _AVX512_BF16_.S
│ ├── _AVX512_FP16_.S
│ ├── _AVX512_VNNI_.S
│ ├── _AVX_.S
│ ├── _AVX_VNNI_.S
│ ├── _AVX_VNNI_INT16_.S
│ ├── _AVX_VNNI_INT8_.S
│ ├── _FMA_.S
│ ├── _SSE2_.S
│ └── _SSE_.S
├── cpufp.cpp
└── cpuid.c
SYMBOL INDEX (72 symbols across 12 files)
FILE: arm64/cpufp.cpp
function get_time (line 64) | static double get_time(struct timespec *start,
function reg_new_isa (line 71) | static void reg_new_isa(std::string isa,
function thread_func (line 89) | static void thread_func(void *params)
function cpubm_arm64_one (line 95) | static void cpubm_arm64_one(smtl_handle sh,
function cpubm_do_bench (line 147) | static void cpubm_do_bench(std::vector<int> &set_of_threads,
function parse_thread_pool (line 197) | static void parse_thread_pool(char *sets,
function cpufp_register_isa (line 265) | static void cpufp_register_isa()
function main (line 322) | int main(int argc, char *argv[])
FILE: arm64/cpuid.c
function main (line 13) | int main()
FILE: common/smtl.cpp
type smtl_status (line 16) | enum smtl_status
type queue_node_t (line 23) | struct queue_node_t
type queue_node_t (line 27) | struct queue_node_t
type smtl_t (line 30) | struct smtl_t
type queue_node_t (line 34) | struct queue_node_t
type smtl_status (line 45) | enum smtl_status
type smtl_tp_t (line 48) | struct smtl_tp_t
type smtl_t (line 52) | struct smtl_t
function thread_bind (line 55) | static void thread_bind(int cpu)
type smtl_tp_t (line 86) | struct smtl_tp_t
type smtl_t (line 52) | struct smtl_t
type smtl_tp_t (line 86) | struct smtl_tp_t
type smtl_t (line 52) | struct smtl_t
type smtl_t (line 89) | struct smtl_t
type queue_node_t (line 34) | struct queue_node_t
type smtl_status (line 45) | enum smtl_status
type queue_node_t (line 134) | struct queue_node_t
type queue_node_t (line 27) | struct queue_node_t
type queue_node_t (line 135) | struct queue_node_t
type queue_node_t (line 27) | struct queue_node_t
function smtl_init (line 173) | void smtl_init(smtl_handle *psh,
function smtl_fini (line 250) | void smtl_fini(smtl_handle sh)
function smtl_num_threads (line 325) | int smtl_num_threads(smtl_handle sh)
function smtl_add_task (line 330) | void smtl_add_task(smtl_handle sh,
function smtl_begin_tasks (line 353) | void smtl_begin_tasks(smtl_handle sh)
function smtl_wait_tasks_finished (line 381) | void smtl_wait_tasks_finished(smtl_handle sh)
FILE: common/smtl.hpp
type smtl_t (line 6) | struct smtl_t
FILE: common/table.hpp
class Table (line 7) | class Table
method Table (line 13) | Table(const Table &) = delete;
method Table (line 14) | Table &operator=(const Table &) = delete;
FILE: e2k/cpufp.cpp
function get_time (line 44) | static double get_time(struct timespec *start,
function reg_new_isa (line 51) | static void reg_new_isa(std::string isa,
function thread_func (line 71) | static void thread_func(void *params)
function cpubm_e2k_one (line 84) | static void cpubm_e2k_one(smtl_handle sh,
function cpubm_do_bench (line 136) | static void cpubm_do_bench(std::vector<int> &set_of_threads,
function parse_thread_pool (line 182) | static void parse_thread_pool(char *sets,
function cpufp_register_isa (line 250) | static void cpufp_register_isa()
function main (line 282) | int main(int argc, char *argv[])
FILE: loongarch64/cpufp.cpp
function get_time (line 57) | static double get_time(struct timespec *start,
function reg_new_isa (line 64) | static void reg_new_isa(std::string isa,
function thread_func (line 84) | static void thread_func(void *params)
function cpubm_x64_one (line 90) | static void cpubm_x64_one(smtl_handle sh,
function cpubm_do_bench (line 143) | static void cpubm_do_bench(std::vector<int> &set_of_threads,
function parse_thread_pool (line 215) | static void parse_thread_pool(char *sets,
function cpufp_register_isa (line 283) | static void cpufp_register_isa()
function main (line 322) | int main(int argc, char *argv[])
FILE: loongarch64/cpuid.c
function read_cpucfg (line 6) | uint32_t read_cpucfg(uint32_t reg)
function main (line 16) | int main()
FILE: riscv64/cpufp.cpp
function get_time (line 46) | static double get_time(struct timespec *start,
function reg_new_isa (line 53) | static void reg_new_isa(std::string isa,
function thread_func (line 71) | static void thread_func(void *params)
function cpubm_riscv64_one (line 77) | static void cpubm_riscv64_one(smtl_handle sh,
function cpubm_do_bench (line 129) | static void cpubm_do_bench(std::vector<int> &set_of_threads,
function parse_thread_pool (line 179) | static void parse_thread_pool(char *sets,
function cpufp_register_isa (line 247) | static void cpufp_register_isa()
function main (line 293) | int main(int argc, char *argv[])
FILE: riscv64/cpuid.c
function main (line 11) | int main()
FILE: x64/cpufp.cpp
function init_tile_cfg (line 119) | void init_tile_cfg()
function get_time (line 158) | static double get_time(struct timespec *start,
function reg_new_isa (line 165) | static void reg_new_isa(std::string isa,
function thread_func (line 187) | static void thread_func(void *params)
function cpubm_x64_one (line 200) | static void cpubm_x64_one(smtl_handle sh,
function cpubm_do_bench (line 253) | static void cpubm_do_bench(std::vector<int> &set_of_threads,
function parse_thread_pool (line 338) | static void parse_thread_pool(char *sets,
function cpufp_register_isa (line 406) | static void cpufp_register_isa()
function main (line 623) | int main(int argc, char *argv[])
FILE: x64/cpuid.c
type cpuid_t (line 3) | struct cpuid_t
function cpuid_x86_exec (line 13) | static void cpuid_x86_exec(unsigned int ieax,
function main (line 22) | int main()
Condensed preview — 78 files, each showing path, character count, and a content snippet. Download the .json file or copy for the full structured content (356K chars).
[
{
"path": ".gitignore",
"chars": 18,
"preview": "build_dir/\n\ncpufp\n"
},
{
"path": "LICENSE",
"chars": 35141,
"preview": " GNU GENERAL PUBLIC LICENSE\n Version 3, 29 June 2007\n\n Copyright (C) 2007 Free "
},
{
"path": "README.md",
"chars": 7307,
"preview": "# cpufp\n\nThis is a cpu tool for benchmarking the peak performance of floating-points and AI ISAs.\n\nIt can automatically "
},
{
"path": "arm64/asm/_ASIMD_.S",
"chars": 7877,
"preview": ".align 4\n\n.macro preserve_caller_vec\n\tstp d8, d9, [sp, #-16]!\n\tstp d10, d11, [sp, #-16]!\n\tstp d12, d13, [sp, #-16]!\n\tstp"
},
{
"path": "arm64/asm/_ASIMD_DP_.S",
"chars": 8021,
"preview": ".align 4\n\n.macro preserve_caller_vec\n\tstp d8, d9, [sp, #-16]!\n\tstp d10, d11, [sp, #-16]!\n\tstp d12, d13, [sp, #-16]!\n\tstp"
},
{
"path": "arm64/asm/_ASIMD_HP_.S",
"chars": 4115,
"preview": ".align 4\n\n.macro preserve_caller_vec\n\tstp d8, d9, [sp, #-16]!\n\tstp d10, d11, [sp, #-16]!\n\tstp d12, d13, [sp, #-16]!\n\tstp"
},
{
"path": "arm64/asm/_BF16_.S",
"chars": 6110,
"preview": ".align 4\n\n.macro preserve_caller_vec\n\tstp d8, d9, [sp, #-16]!\n\tstp d10, d11, [sp, #-16]!\n\tstp d12, d13, [sp, #-16]!\n\tstp"
},
{
"path": "arm64/asm/_I8MM_.S",
"chars": 11957,
"preview": ".align 4\n\n.macro preserve_caller_vec\n\tstp d8, d9, [sp, #-16]!\n\tstp d10, d11, [sp, #-16]!\n\tstp d12, d13, [sp, #-16]!\n\tstp"
},
{
"path": "arm64/cpufp.cpp",
"chars": 9283,
"preview": "#include \"table.hpp\"\n#include \"smtl.hpp\"\n\n#include <unistd.h>\n#include <cstdint>\n#include <ctime>\n#include <cstring>\n#in"
},
{
"path": "arm64/cpuid.c",
"chars": 1475,
"preview": "#include <stdio.h>\n#include <stdint.h>\n#ifndef __APPLE__\n#include <asm/hwcap.h>\n#include <sys/auxv.h>\n#else\n#include <st"
},
{
"path": "benchmark_result/arm64/AWS_Graviton_3E.md",
"chars": 1601,
"preview": "# AWS Graviton 3E\n\nArchitecture: Neoverse V1\n\nSetting: Virtual 1 Core\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread_pool=["
},
{
"path": "benchmark_result/arm64/Apple_Silicon_M2_Max.md",
"chars": 9207,
"preview": "# Apple M2 Max (Macbook Pro 16)\n\nSetting: 8 Avalanche P-Cores + 4 Blizzard E-Cores\n\nOS: MacOS 15.1\n\nFor 1 P-core:\n\n<pre>"
},
{
"path": "benchmark_result/arm64/Apple_Silicon_M4_Max.md",
"chars": 9613,
"preview": "# Apple M4 Max (Macbook Pro 16)\n\nSetting: 12 P-Cores + 4 E-Cores\n\nOS: MacOS 15.1\n\nFor 1 P-core:\n\n<pre>\n$ ./cpufp --threa"
},
{
"path": "benchmark_result/arm64/Broadcom_BCM2711.md",
"chars": 1138,
"preview": "# Broadcom BCM2711(RaspBerry Pi 4)\n\nSetting: 4 Cortex-A72 Cores\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread_pool=[0]\nNum"
},
{
"path": "benchmark_result/arm64/Broadcom_BCM2712.md",
"chars": 1960,
"preview": "# Broadcom BCM2712(RaspBerry Pi 5)\n\nSetting: 4 Cortex-A76 Cores\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread_pool=[0]\nNum"
},
{
"path": "benchmark_result/arm64/CIX_P1_CD8180.md",
"chars": 15636,
"preview": "# CIX P1 CD8180(Radxa Orion O6)\n\nSettings: \nCortex-A720 @ 2.5GHz: 0,11 \nCortex-A720 @ 2.4GHz: 9,10 \nCortex-A720 @ 2.3"
},
{
"path": "benchmark_result/arm64/HUAWEI_Kunpeng_920_7260.md",
"chars": 4531,
"preview": "# HUAWEI Kunpeng 920 7260\n\nArchitecture: Taishan V110\n\nSetting: 2 * 64 cores\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread"
},
{
"path": "benchmark_result/arm64/HUAWEI_Kunpeng_D920_2249K.md",
"chars": 1978,
"preview": "# HUAWEI Kunpeng D920 2249K\n\nArchitecture: Taishan V110\n\nSetting: 8 cores\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread_po"
},
{
"path": "benchmark_result/arm64/Phytium_D2000.md",
"chars": 1117,
"preview": "# Phytium D2000/8\n\nSetting: 8 FTC663 Cores\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread"
},
{
"path": "benchmark_result/arm64/Qualcomm_Snapdragon_X_Elite_X1E80100.md",
"chars": 3209,
"preview": "# Qualcomm Snapdragon X Elite - X1E80100\n\nArchitecture: Oryon-1\n\nSetting: 4 E-cores @ 3.4Ghz + 8 P-cores @ 4.0Ghz\n\nFor s"
},
{
"path": "benchmark_result/arm64/RockChip_RK3399.md",
"chars": 2247,
"preview": "# Rockchip RK3399\n\nSetting: 2 Cortex-A72(big) Cores + 4 Cortex-A53(Little) Cores\n\nFor single Little core:\n\n<pre>\n$ ./cpu"
},
{
"path": "benchmark_result/arm64/RockChip_RK3588.md",
"chars": 3895,
"preview": "# RockChip RK3588\n\nSetting: 4 Cortex-A76(big) Cores + 4 Cortex-A55(Little) Cores\n\nFor single Little core:\n\n<pre>\n$ ./cpu"
},
{
"path": "benchmark_result/e2k/Elbrus_4C.md",
"chars": 1354,
"preview": "# Elbrus-4C\n\nSetting: 4 Sockets x 4 Elbrus-v3\n\nFreqency: 750 MHz\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread_pool=[0]\nNu"
},
{
"path": "benchmark_result/e2k/Elbrus_8C.md",
"chars": 1411,
"preview": "# Elbrus-8C\n\nSetting: 4 Sockets x 8 Elbrus-v4\n\nFrequency: 1.2 GHz\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread_pool=[0]\nN"
},
{
"path": "benchmark_result/e2k/Elbrus_8C2.md",
"chars": 1790,
"preview": "# Elbrus-8C2\n\nSetting: 4 Sockets x 8 Elbrus-v5\n\nFrequency: 1.2 GHz\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread_pool=[0]\n"
},
{
"path": "benchmark_result/loongarch64/Loongson_3A5000M.md",
"chars": 1689,
"preview": "# Loongson 3A5000M\n\nSetting: 4 LA464 Cores\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread"
},
{
"path": "benchmark_result/loongarch64/Loongson_3A6000.md",
"chars": 2781,
"preview": "# Loongson 3A6000\n\nSetting: 4 LA664 Cores\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread "
},
{
"path": "benchmark_result/loongarch64/Loongson_3C5000.md",
"chars": 1722,
"preview": "# Loongson 3C5000\n\nSetting: 16 LA464 Cores\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread"
},
{
"path": "benchmark_result/riscv64/Kendryte_K230.md",
"chars": 716,
"preview": "# Kendryte K230\n\nSetting: 2 C908 Cores\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThread Poo"
},
{
"path": "benchmark_result/riscv64/SpacemiT_K1.md",
"chars": 2775,
"preview": "# SpacemiT K1\n\nSetting: 8 SpacemiT-X60 Cores\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread_pool=[0]\nNumber Threads: 1\nThre"
},
{
"path": "benchmark_result/x64/AMD_Ryzen7_8845HS.md",
"chars": 2041,
"preview": "# AMD Ryzen7 8845HS\n\nArchitecture: Zen4\n\nSetting: 8 Zen4 Cores\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread_pool=[0]\nNumb"
},
{
"path": "benchmark_result/x64/AMD_Ryzen7_9700X.md",
"chars": 5180,
"preview": "# AMD Ryzen7 9700X\n\nMicroarchitecture: Zen5\n\nSetting: 8 Zen5 Cores\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread_pool=[0]\n"
},
{
"path": "benchmark_result/x64/AMD_Ryzen9_6900HX.md",
"chars": 1431,
"preview": "# AMD Ryzen9 6900HX\n\nArchitecture: Zen3+\n\nSetting: 8 Zen3+ Cores\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread_pool=[0]\nNu"
},
{
"path": "benchmark_result/x64/Intel_Core_i3_8121U.md",
"chars": 3131,
"preview": "# Intel Core i3-8121U\n\nProduct Code Name: Cannon-Lake\n\nSetting: 2 Cannon-Lake Cores\n\nFor single Core:\n\n<pre>\n$ ./cpufp -"
},
{
"path": "benchmark_result/x64/Intel_Core_i5_1340P.md",
"chars": 3331,
"preview": "# Intel Core i5-1340P\n\nProduct Code Name: Raptor Lake\n\nSetting: 4 Raptor Cove(P-Core) Cores + 8 Gracemont(E-Core) Cores\n"
},
{
"path": "benchmark_result/x64/Intel_N150.md",
"chars": 2964,
"preview": "# Intel N150\n\nProduct Code Name: Twin-Lake\n\nSetting: 4 Gracemont Cores\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread_pool="
},
{
"path": "benchmark_result/x64/Intel_Ultra7_255H.md",
"chars": 11688,
"preview": "# Intel Ultra7 255H\n\nProduct Code Name: Arrow Lake-H\n\nSetting: 6 Lion Cove P-Cores + 8 Skymont E-Cores + 2 (Unknown Arch"
},
{
"path": "benchmark_result/x64/Intel_Xeon_Gold_6455B.md",
"chars": 3258,
"preview": "# Intel Xeon Gold 6455B\n\nMicroarchitecture: Sapphire Rapids\n\nSetting: 2 Sockets x 32 Golden Cove Cores\n\nFor single core:"
},
{
"path": "benchmark_result/x64/Intel_Xeon_W9_3495X.md",
"chars": 3232,
"preview": "# Intel Xeon W9-3495X\n\nMicroarchitecture: Sapphire Rapids\n\nSetting: 1 Sockets x 56 Golden Cove Cores\n\nFor single core:\n\n"
},
{
"path": "benchmark_result/x64/ZHAOXIN_KX_6640MA.md",
"chars": 1151,
"preview": "# ZHAOXIN KX-6640MA\n\nArchitecture: LuJiaZui\n\nSetting: 4 Cores\n\nFor single core:\n\n<pre>\n$ ./cpufp --thread_pool=[0]\nNumbe"
},
{
"path": "build_arm64.sh",
"chars": 1286,
"preview": "SRC=arm64\nASM=$SRC/asm\nCOMM=common\nBUILD_DIR=build_dir\nOS=$(uname -o)\n\n# make directory\nif [ -d \"$BUILD_DIR\" ]; then\n "
},
{
"path": "build_e2k.sh",
"chars": 560,
"preview": "SRC=e2k\nCOMM=common\nBUILD_DIR=build_dir\n\n# make directory\nif [ -d \"$BUILD_DIR\" ]; then\n rm -rf $BUILD_DIR/*\nelse\n "
},
{
"path": "build_loongarch64.sh",
"chars": 762,
"preview": "SRC=loongarch64\nASM=$SRC/asm\nCOMM=common\nBUILD_DIR=build_dir\n\n# make directory\nif [ -d \"$BUILD_DIR\" ]; then\n rm -rf $"
},
{
"path": "build_riscv64.sh",
"chars": 795,
"preview": "SRC=riscv64\nASM=$SRC/asm\nCOMM=common\nBUILD_DIR=build_dir\n\n# make directory\nif [ -d \"$BUILD_DIR\" ]; then\n rm -rf $BUIL"
},
{
"path": "build_x64.sh",
"chars": 754,
"preview": "SRC=x64\nASM=$SRC/asm\nCOMM=common\nBUILD_DIR=build_dir\n\n# make directory\nif [ -d \"$BUILD_DIR\" ]; then\n rm -rf $BUILD_DI"
},
{
"path": "clean.sh",
"chars": 44,
"preview": "BUILD_DIR=build_dir\nrm -rf $BUILD_DIR cpufp\n"
},
{
"path": "common/smtl.cpp",
"chars": 9552,
"preview": "#include \"smtl.hpp\"\n\n#include <cstdlib>\n#include <cstdio>\n#include <cstring>\n#ifdef __APPLE__\n#include <mach/thread_poli"
},
{
"path": "common/smtl.hpp",
"chars": 448,
"preview": "#ifndef _SMTL_H\n#define _SMTL_H\n\n#include <vector>\n\ntypedef struct smtl_t* smtl_handle;\ntypedef void (*task_func_t)(void"
},
{
"path": "common/table.cpp",
"chars": 1573,
"preview": "#include \"table.hpp\"\n\n#include <iostream>\nusing namespace std;\n\nTable::Table()\n{\n col = 0;\n}\n\nTable::~Table()\n{\n}\n\nvo"
},
{
"path": "common/table.hpp",
"chars": 483,
"preview": "#ifndef _TABLE_HPP\n#define _TABLE_HPP\n\n#include <string>\n#include <vector>\n\nclass Table\n{\npublic:\n Table();\n ~Tabl"
},
{
"path": "e2k/asm.S",
"chars": 2276,
"preview": "#if __iset__ < 5\n# define CLEAR addd\n#else\n# define CLEAR qppackdl\n#endif\n\n.macro impl_bench name, op\n .global \\name\n"
},
{
"path": "e2k/cpufp.cpp",
"chars": 7596,
"preview": "#include \"table.hpp\"\n#include \"smtl.hpp\"\n\n#include <unistd.h>\n#include <cstdint>\n#include <ctime>\n#include <cstring>\n#in"
},
{
"path": "loongarch64/asm/_FP_DP_.S",
"chars": 1050,
"preview": ".globl fp64_fmadd_f64f64f64\nfp64_fmadd_f64f64f64:\n\tmovgr2fr.d $f0, $r0\n\tmovgr2fr.d $f1, $r0\n\tmovgr2fr.d $f2, $r0\n\tmovgr2"
},
{
"path": "loongarch64/asm/_FP_SP_.S",
"chars": 1050,
"preview": ".globl fp32_fmadd_f32f32f32\nfp32_fmadd_f32f32f32:\n\tmovgr2fr.w $f0, $r0\n\tmovgr2fr.w $f1, $r0\n\tmovgr2fr.w $f2, $r0\n\tmovgr2"
},
{
"path": "loongarch64/asm/_LASX_.S",
"chars": 6093,
"preview": ".globl lasx_fp32_fmadd_f32f32f32\n.globl lasx_fp64_fmadd_f64f64f64\n.globl lasx_fp32_add_mul_f32f32_f32\n.globl lasx_fp64_a"
},
{
"path": "loongarch64/asm/_LSX_.S",
"chars": 5913,
"preview": ".globl lsx_fp32_fmadd_f32f32f32\n.globl lsx_fp64_fmadd_f64f64f64\n.globl lsx_fp32_add_mul_f32f32_f32\n.globl lsx_fp64_add_m"
},
{
"path": "loongarch64/cpufp.cpp",
"chars": 8861,
"preview": "#include \"table.hpp\"\n#include \"smtl.hpp\"\n\n#include <unistd.h>\n#include <cstdint>\n#include <ctime>\n#include <cstring>\n#in"
},
{
"path": "loongarch64/cpuid.c",
"chars": 690,
"preview": "#include <stdio.h>\n#include <stdint.h>\n\n#define BIT_TEST(bit_map, pos) (((bit_map) & (0x1 << (pos))) ? 1 : 0)\n\nuint32_t "
},
{
"path": "riscv64/asm/_IME_.S",
"chars": 4251,
"preview": ".align 4\n\n.macro preserve_caller_vec\n csrr x5, vtype\n csrr x6, vl\n vsetvli x7, x0, e8, m8\n sub sp, sp, x7\n "
},
{
"path": "riscv64/asm/_VECTOR_.S",
"chars": 6926,
"preview": ".align 4\n\n.macro preserve_caller_vec\n csrr x5, vtype\n csrr x6, vl\n vsetvli x7, x0, e8, m8\n sub sp, sp, x7\n "
},
{
"path": "riscv64/cpufp.cpp",
"chars": 8442,
"preview": "#include \"table.hpp\"\n#include \"smtl.hpp\"\n\n#include <unistd.h>\n#include <cstdint>\n#include <ctime>\n#include <cstring>\n#in"
},
{
"path": "riscv64/cpuid.c",
"chars": 1129,
"preview": "\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include <stdint.h>\n#include <asm/hwcap.h>\n#include <sys/aux"
},
{
"path": "x64/asm/_AMX_BF16_.S",
"chars": 415,
"preview": ".globl amx_bf16_mm_f32bf16bf16\n\namx_bf16_mm_f32bf16bf16:\n ldtilecfg (%rsi)\n tilezero %tmm0\n tilezero %tmm1\n "
},
{
"path": "x64/asm/_AMX_FP16_.S",
"chars": 406,
"preview": ".globl amx_fp16_mm_f32f16f16\n\namx_fp16_mm_f32f16f16:\n ldtilecfg (%rsi)\n tilezero %tmm0\n tilezero %tmm1\n tile"
},
{
"path": "x64/asm/_AMX_INT8_.S",
"chars": 1561,
"preview": ".globl amx_int8_mm_s32s8s8\n.globl amx_int8_mm_s32s8u8\n.globl amx_int8_mm_s32u8s8\n.globl amx_int8_mm_s32u8u8\n\namx_int8_mm"
},
{
"path": "x64/asm/_AVX512F_.S",
"chars": 4957,
"preview": ".globl avx512f_512b_fma_f32f32f32\n.globl avx512f_512b_fma_f64f64f64\n.globl avx512f_512b_add_mul_f32f32_f32\n.globl avx512"
},
{
"path": "x64/asm/_AVX512_BF16_.S",
"chars": 3798,
"preview": ".globl avx512_bf16_512b_dp2a_f32bf16bf16\n.globl avx512_bf16_256b_dp2a_f32bf16bf16\n.globl avx512_bf16_128b_dp2a_f32bf16bf"
},
{
"path": "x64/asm/_AVX512_FP16_.S",
"chars": 3690,
"preview": ".globl avx512_fp16_512b_fma_f16f16f16\n.globl avx512_fp16_256b_fma_f16f16f16\n.globl avx512_fp16_128b_fma_f16f16f16\n\navx51"
},
{
"path": "x64/asm/_AVX512_VNNI_.S",
"chars": 7091,
"preview": ".globl avx512_vnni_512b_dp4a_s32u8s8\n.globl avx512_vnni_512b_dp2a_s32s16s16\n.globl avx512_vnni_256b_dp4a_s32u8s8\n.globl "
},
{
"path": "x64/asm/_AVX_.S",
"chars": 2387,
"preview": ".globl avx_256b_add_mul_f32f32_f32\n.globl avx_256b_add_mul_f64f64_f64\n\navx_256b_add_mul_f32f32_f32:\n vxorps %ymm0, %y"
},
{
"path": "x64/asm/_AVX_VNNI_.S",
"chars": 4953,
"preview": ".globl avx_vnni_256b_dp4a_s32u8s8\n.globl avx_vnni_256b_dp2a_s32s16s16\n.globl avx_vnni_128b_dp4a_s32u8s8\n.globl avx_vnni_"
},
{
"path": "x64/asm/_AVX_VNNI_INT16_.S",
"chars": 7021,
"preview": ".globl avx_vnni_int16_256b_dp2a_s32s16u16\n.globl avx_vnni_int16_256b_dp2a_s32u16s16\n.globl avx_vnni_int16_256b_dp2a_s32u"
},
{
"path": "x64/asm/_AVX_VNNI_INT8_.S",
"chars": 6949,
"preview": ".globl avx_vnni_int8_256b_dp4a_s32s8s8\n.globl avx_vnni_int8_256b_dp4a_s32s8u8\n.globl avx_vnni_int8_256b_dp4a_s32u8u8\n.gl"
},
{
"path": "x64/asm/_FMA_.S",
"chars": 4745,
"preview": ".globl fma_256b_fma_f32f32f32\n.globl fma_256b_fma_f64f64f64\n.globl fma_128b_fma_f32f32f32\n.globl fma_128b_fma_f64f64f64\n"
},
{
"path": "x64/asm/_SSE2_.S",
"chars": 930,
"preview": ".globl sse2_128b_add_mul_f64f64_f64\n\nsse2_128b_add_mul_f64f64_f64:\n xorpd %xmm0, %xmm0\n xorpd %xmm1, %xmm1\n xor"
},
{
"path": "x64/asm/_SSE_.S",
"chars": 926,
"preview": ".globl sse_128b_add_mul_f32f32_f32\n\nsse_128b_add_mul_f32f32_f32:\n xorps %xmm0, %xmm0\n xorps %xmm1, %xmm1\n xorps"
},
{
"path": "x64/cpufp.cpp",
"chars": 18895,
"preview": "#include \"table.hpp\"\n#include \"smtl.hpp\"\n\n#include <unistd.h>\n#include <cstdint>\n#include <ctime>\n#include <cstring>\n#in"
},
{
"path": "x64/cpuid.c",
"chars": 1985,
"preview": "#include <stdio.h>\n\nstruct cpuid_t\n{\n unsigned int eax;\n unsigned int ebx;\n unsigned int ecx;\n unsigned int "
}
]
About this extraction
This page contains the full source code of the pigirons/cpufp GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 78 files (332.3 KB), approximately 140.0k tokens, and a symbol index with 72 extracted functions, classes, methods, constants, and types. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.
Extracted by GitExtract — free GitHub repo to text converter for AI. Built by Nikandr Surkov.