Copy disabled (too large)
Download .txt
Showing preview only (11,420K chars total). Download the full file to get everything.
Repository: Xilinx/device-tree-xlnx
Branch: master
Commit: ac65e0142e52
Files: 1805
Total size: 10.5 MB
Directory structure:
gitextract__dnvpkf3/
├── .github/
│ └── pull_request_template.md
├── .gitignore
├── RM/
│ └── data/
│ ├── RM.mdd
│ └── RM.tcl
├── ai_engine/
│ └── data/
│ ├── ai_engine.mdd
│ └── ai_engine.tcl
├── ams/
│ └── data/
│ ├── ams.mdd
│ └── ams.tcl
├── apmps/
│ └── data/
│ ├── apmps.mdd
│ └── apmps.tcl
├── audio_embed/
│ └── data/
│ ├── audio_embed.mdd
│ └── audio_embed.tcl
├── audio_formatter/
│ └── data/
│ ├── audio_formatter.mdd
│ └── audio_formatter.tcl
├── audio_spdif/
│ └── data/
│ ├── audio_spdif.mdd
│ └── audio_spdif.tcl
├── axi_can/
│ └── data/
│ ├── axi_can.mdd
│ └── axi_can.tcl
├── axi_cdma/
│ └── data/
│ ├── axi_cdma.mdd
│ └── axi_cdma.tcl
├── axi_clk_wiz/
│ └── data/
│ ├── axi_clk_wiz.mdd
│ └── axi_clk_wiz.tcl
├── axi_dma/
│ └── data/
│ ├── axi_dma.mdd
│ └── axi_dma.tcl
├── axi_emc/
│ └── data/
│ ├── axi_emc.mdd
│ └── axi_emc.tcl
├── axi_ethernet/
│ └── data/
│ ├── axi_ethernet.mdd
│ └── axi_ethernet.tcl
├── axi_gpio/
│ └── data/
│ ├── gpio.mdd
│ └── gpio.tcl
├── axi_iic/
│ └── data/
│ ├── axi_iic.mdd
│ └── axi_iic.tcl
├── axi_mcdma/
│ └── data/
│ ├── axi_mcdma.mdd
│ └── axi_mcdma.tcl
├── axi_pcie/
│ └── data/
│ ├── axi_pcie.mdd
│ └── axi_pcie.tcl
├── axi_perf_mon/
│ └── data/
│ ├── axi_perf_mon.mdd
│ └── axi_perf_mon.tcl
├── axi_qspi/
│ └── data/
│ ├── axi_qspi.mdd
│ └── axi_qspi.tcl
├── axi_sysace/
│ └── data/
│ ├── axi_sysace.mdd
│ └── axi_sysace.tcl
├── axi_tft/
│ └── data/
│ ├── axi_tft.mdd
│ └── axi_tft.tcl
├── axi_timebase_wdt/
│ └── data/
│ ├── axi_timebase_wdt.mdd
│ └── axi_timebase_wdt.tcl
├── axi_traffic_gen/
│ └── data/
│ ├── axi_traffic_gen.mdd
│ └── axi_traffic_gen.tcl
├── axi_usb2_device/
│ └── data/
│ ├── axi_usb2_device.mdd
│ └── axi_usb2_device.tcl
├── axi_vcu/
│ └── data/
│ ├── axi_vcu.mdd
│ └── axi_vcu.tcl
├── axi_vdma/
│ └── data/
│ ├── axi_vdma.mdd
│ └── axi_vdma.tcl
├── axi_vdu/
│ └── data/
│ ├── axi_vdu.mdd
│ └── axi_vdu.tcl
├── axi_xadc/
│ └── data/
│ ├── axi_xadc.mdd
│ └── axi_xadc.tcl
├── axis_switch/
│ └── data/
│ ├── axis_switch.mdd
│ └── axis_switch.tcl
├── canfdps/
│ └── data/
│ ├── canfdps.mdd
│ └── canfdps.tcl
├── canps/
│ └── data/
│ ├── canps.mdd
│ └── canps.tcl
├── cpu/
│ └── data/
│ ├── cpu.mdd
│ └── cpu.tcl
├── cpu_cortexa53/
│ └── data/
│ ├── cpu_cortexa53.mdd
│ └── cpu_cortexa53.tcl
├── cpu_cortexa72/
│ └── data/
│ ├── cpu_cortexa72.mdd
│ └── cpu_cortexa72.tcl
├── cpu_cortexa78/
│ └── data/
│ ├── cpu_cortexa78.mdd
│ └── cpu_cortexa78.tcl
├── cpu_cortexa9/
│ └── data/
│ ├── cpu_cortexa9.mdd
│ └── cpu_cortexa9.tcl
├── dccps/
│ └── data/
│ ├── dccps.mdd
│ └── dccps.tcl
├── ddrcps/
│ └── data/
│ ├── ddrcps.mdd
│ └── ddrcps.tcl
├── ddrps/
│ └── data/
│ ├── ddrps.mdd
│ └── ddrps.tcl
├── ddrpsv/
│ └── data/
│ ├── ddrpsv.mdd
│ └── ddrpsv.tcl
├── debug_bridge/
│ └── data/
│ ├── debug_bridge.mdd
│ └── debug_bridge.tcl
├── demosaic/
│ └── data/
│ ├── demosaic.mdd
│ └── demosaic.tcl
├── devcfg/
│ └── data/
│ ├── devcfg.mdd
│ └── devcfg.tcl
├── device_tree/
│ └── data/
│ ├── common_proc.tcl
│ ├── device_tree.mld
│ ├── device_tree.mss
│ ├── device_tree.tcl
│ └── kernel_dtsi/
│ ├── 2014.4/
│ │ └── zynq/
│ │ ├── skeleton.dtsi
│ │ └── zynq-7000.dtsi
│ ├── 2015.1/
│ │ └── zynq/
│ │ ├── skeleton.dtsi
│ │ └── zynq-7000.dtsi
│ ├── 2015.2/
│ │ └── zynq/
│ │ ├── skeleton.dtsi
│ │ └── zynq-7000.dtsi
│ ├── 2015.3/
│ │ └── zynq/
│ │ ├── skeleton.dtsi
│ │ └── zynq-7000.dtsi
│ ├── 2015.4/
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2016.1/
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2016.2/
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2016.3/
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2016.4/
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2017.1/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu102.dtsi
│ │ │ ├── zcu106.dtsi
│ │ │ └── zedboard.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2017.2/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu102.dtsi
│ │ │ ├── zcu106.dtsi
│ │ │ └── zedboard.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2017.3/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zedboard.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2017.4/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zedboard.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2018.1/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1275-revb.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ └── zedboard.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2018.2/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1275-revb.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ └── zedboard.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2018.3/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1275-revb.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ └── zedboard.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2019.1/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1275-revb.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-g-reva.dtsi
│ │ │ ├── zynqmp-a2197-m-reva.dtsi
│ │ │ ├── zynqmp-a2197-p-reva.dtsi
│ │ │ └── zynqmp-a2197-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ └── pinctrl/
│ │ │ └── pinctrl-zynqmp.h
│ │ ├── versal/
│ │ │ └── versal.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2019.2/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ └── zynqmp-e-a2197-00-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ └── pinctrl/
│ │ │ └── pinctrl-zynqmp.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ └── versal.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2020.1/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ └── zynqmp-p-a2197-00-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2020.2/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vck5000-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ └── zynqmp-p-a2197-00-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2021.1/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vck5000-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── versal-vp-x-a2785-00-reva.dtsi
│ │ │ ├── versal-vpk120-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zcu670-reva.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-sm-k26-reva-mlcc.dtsi
│ │ │ ├── zynqmp-sm-k26-reva.dtsi
│ │ │ ├── zynqmp-sm-k26-reva01-mlcc.dtsi
│ │ │ ├── zynqmp-sm-k26-reva01.dtsi
│ │ │ ├── zynqmp-sm-k26-revb-mlcc.dtsi
│ │ │ ├── zynqmp-sm-k26-revb.dtsi
│ │ │ ├── zynqmp-sm-k26-revb01-mlcc.dtsi
│ │ │ ├── zynqmp-sm-k26-revb01.dtsi
│ │ │ ├── zynqmp-smk-k26-reva.dtsi
│ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi
│ │ │ └── zynqmp-vpk120-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── dma/
│ │ │ │ └── xlnx-zynqmp-dpdma.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2021.2/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105-tmr.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vck5000-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── versal-vp-x-a2785-00-reva.dtsi
│ │ │ ├── versal-vpk120-reva.dtsi
│ │ │ ├── versal-vpk120-revb.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zcu670-reva.dtsi
│ │ │ ├── zcu670-revb.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-sc-revb.dtsi
│ │ │ ├── zynqmp-sm-k26-reva.dtsi
│ │ │ ├── zynqmp-smk-k26-reva.dtsi
│ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi
│ │ │ └── zynqmp-vpk120-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── dma/
│ │ │ │ └── xlnx-zynqmp-dpdma.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2022.1/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105-tmr.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vck5000-reva.dtsi
│ │ │ ├── versal-vhk158-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── versal-vp-x-a2785-00-reva.dtsi
│ │ │ ├── versal-vpk120-reva.dtsi
│ │ │ ├── versal-vpk120-revb.dtsi
│ │ │ ├── versal-vpk180-reva.dtsi
│ │ │ ├── versal-x-ebm-01-reva.dtsi
│ │ │ ├── versal-x-ebm-02-reva.dtsi
│ │ │ ├── versal-x-ebm-03-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zcu670-reva.dtsi
│ │ │ ├── zcu670-revb.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-sc-revb.dtsi
│ │ │ ├── zynqmp-sm-k26-reva.dtsi
│ │ │ ├── zynqmp-smk-k26-reva.dtsi
│ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi
│ │ │ └── zynqmp-vpk120-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── dma/
│ │ │ │ └── xlnx-zynqmp-dpdma.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── net/
│ │ │ │ └── ti-dp83867.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2022.2/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105-tmr.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-net-emu-rev1.9.dtsi
│ │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi
│ │ │ ├── versal-net-ipp-rev1.9.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vck5000-reva.dtsi
│ │ │ ├── versal-vek280-reva.dtsi
│ │ │ ├── versal-vhk158-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── versal-vp-x-a2785-00-reva.dtsi
│ │ │ ├── versal-vpk120-reva.dtsi
│ │ │ ├── versal-vpk120-revb.dtsi
│ │ │ ├── versal-vpk180-reva.dtsi
│ │ │ ├── versal-x-ebm-01-reva.dtsi
│ │ │ ├── versal-x-ebm-02-reva.dtsi
│ │ │ ├── versal-x-ebm-03-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zcu670-reva.dtsi
│ │ │ ├── zcu670-revb.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-revb.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-sc-revb.dtsi
│ │ │ ├── zynqmp-sm-k26-reva.dtsi
│ │ │ ├── zynqmp-smk-k26-reva.dtsi
│ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi
│ │ │ └── zynqmp-vpk120-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── dma/
│ │ │ │ └── xlnx-zynqmp-dpdma.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── net/
│ │ │ │ └── ti-dp83867.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-net-power.h
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ ├── xlnx-versal-regnode.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ ├── xlnx-versal-net-resets.h
│ │ │ ├── xlnx-versal-resets.h
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── versal-net/
│ │ │ └── versal-net-ipp-rev1.9.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2023.1/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105-tmr.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-net-emu-rev1.9.dtsi
│ │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi
│ │ │ ├── versal-net-ipp-rev1.9.dtsi
│ │ │ ├── versal-net-vn-p-b2197-00-reva-pl.dtsi
│ │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vck5000-reva.dtsi
│ │ │ ├── versal-vek280-reva.dtsi
│ │ │ ├── versal-vek280-revb.dtsi
│ │ │ ├── versal-vhk158-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── versal-vp-x-a2785-00-reva.dtsi
│ │ │ ├── versal-vpk120-reva.dtsi
│ │ │ ├── versal-vpk120-revb.dtsi
│ │ │ ├── versal-vpk180-reva.dtsi
│ │ │ ├── versal-x-ebm-01-reva.dtsi
│ │ │ ├── versal-x-ebm-02-reva.dtsi
│ │ │ ├── versal-x-ebm-03-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zcu670-reva.dtsi
│ │ │ ├── zcu670-revb.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-revb.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-sc-revb.dtsi
│ │ │ ├── zynqmp-sc-revc.dtsi
│ │ │ ├── zynqmp-sc-vek280-reva.dtsi
│ │ │ ├── zynqmp-sc-vek280-revb.dtsi
│ │ │ ├── zynqmp-sm-k24-reva.dtsi
│ │ │ ├── zynqmp-sm-k26-reva.dtsi
│ │ │ ├── zynqmp-smk-k24-reva.dtsi
│ │ │ ├── zynqmp-smk-k26-reva.dtsi
│ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi
│ │ │ └── zynqmp-vpk120-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ ├── xlnx-versal-net-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── dma/
│ │ │ │ └── xlnx-zynqmp-dpdma.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── net/
│ │ │ │ ├── mscc-phy-vsc8531.h
│ │ │ │ └── ti-dp83867.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-net-power.h
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ ├── xlnx-versal-regnode.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ ├── xlnx-versal-net-resets.h
│ │ │ ├── xlnx-versal-resets.h
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── versal-net/
│ │ │ ├── versal-net-clk-ccf.dtsi
│ │ │ ├── versal-net-clk.dtsi
│ │ │ ├── versal-net-ipp-rev1.9.dtsi
│ │ │ └── versal-net.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2023.2/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105-tmr.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-net-emu-rev1.9.dtsi
│ │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi
│ │ │ ├── versal-net-ipp-rev1.9.dtsi
│ │ │ ├── versal-net-vn-p-b2197-00-reva-pl.dtsi
│ │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi
│ │ │ ├── versal-net-vn-x-b2197-00-reva.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vck5000-reva.dtsi
│ │ │ ├── versal-vek280-reva.dtsi
│ │ │ ├── versal-vek280-revb.dtsi
│ │ │ ├── versal-vhk158-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── versal-vp-x-a2785-00-reva.dtsi
│ │ │ ├── versal-vpk120-reva.dtsi
│ │ │ ├── versal-vpk120-revb.dtsi
│ │ │ ├── versal-vpk180-reva.dtsi
│ │ │ ├── versal-x-ebm-01-reva.dtsi
│ │ │ ├── versal-x-ebm-02-reva.dtsi
│ │ │ ├── versal-x-ebm-03-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zcu670-reva.dtsi
│ │ │ ├── zcu670-revb.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-revb.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-sc-revb.dtsi
│ │ │ ├── zynqmp-sc-revc.dtsi
│ │ │ ├── zynqmp-sc-vek280-reva.dtsi
│ │ │ ├── zynqmp-sc-vek280-revb.dtsi
│ │ │ ├── zynqmp-sm-k24-reva.dtsi
│ │ │ ├── zynqmp-sm-k26-reva.dtsi
│ │ │ ├── zynqmp-smk-k24-reva.dtsi
│ │ │ ├── zynqmp-smk-k26-reva.dtsi
│ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi
│ │ │ └── zynqmp-vpk120-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ ├── xlnx-versal-net-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── dma/
│ │ │ │ └── xlnx-zynqmp-dpdma.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── net/
│ │ │ │ ├── mscc-phy-vsc8531.h
│ │ │ │ └── ti-dp83867.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-net-power.h
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ ├── xlnx-versal-regnode.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ ├── xlnx-versal-net-resets.h
│ │ │ ├── xlnx-versal-resets.h
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── versal-net/
│ │ │ ├── versal-net-clk-ccf.dtsi
│ │ │ ├── versal-net-clk.dtsi
│ │ │ ├── versal-net-ipp-rev1.9.dtsi
│ │ │ └── versal-net.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2024.1/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105-tmr.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emb-plus-ve2302-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-net-emu-rev1.9.dtsi
│ │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi
│ │ │ ├── versal-net-ipp-rev1.9.dtsi
│ │ │ ├── versal-net-vn-p-b2197-00-reva-pl.dtsi
│ │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi
│ │ │ ├── versal-net-vn-x-b2197-00-reva.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vck5000-reva.dtsi
│ │ │ ├── versal-vek280-reva.dtsi
│ │ │ ├── versal-vek280-revb.dtsi
│ │ │ ├── versal-vhk158-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── versal-vp-x-a2785-00-reva.dtsi
│ │ │ ├── versal-vpk120-reva.dtsi
│ │ │ ├── versal-vpk120-revb.dtsi
│ │ │ ├── versal-vpk180-reva.dtsi
│ │ │ ├── versal-x-ebm-01-reva.dtsi
│ │ │ ├── versal-x-ebm-02-reva.dtsi
│ │ │ ├── versal-x-ebm-03-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zcu670-reva.dtsi
│ │ │ ├── zcu670-revb.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-revb.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-sc-revb.dtsi
│ │ │ ├── zynqmp-sc-revc.dtsi
│ │ │ ├── zynqmp-sc-vek280-reva.dtsi
│ │ │ ├── zynqmp-sc-vek280-revb.dtsi
│ │ │ ├── zynqmp-sm-k24-reva.dtsi
│ │ │ ├── zynqmp-sm-k26-reva.dtsi
│ │ │ ├── zynqmp-smk-k24-reva.dtsi
│ │ │ ├── zynqmp-smk-k26-reva.dtsi
│ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi
│ │ │ └── zynqmp-vpk120-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ ├── xlnx-versal-net-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── dma/
│ │ │ │ └── xlnx-zynqmp-dpdma.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── net/
│ │ │ │ ├── mscc-phy-vsc8531.h
│ │ │ │ └── ti-dp83867.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-net-power.h
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ ├── xlnx-versal-regnode.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ ├── xlnx-versal-net-resets.h
│ │ │ ├── xlnx-versal-resets.h
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── versal-net/
│ │ │ ├── versal-net-clk-ccf.dtsi
│ │ │ ├── versal-net-clk.dtsi
│ │ │ ├── versal-net-ipp-rev1.9.dtsi
│ │ │ └── versal-net.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2024.2/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105-tmr.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emb-plus-ve2302-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-net-emu-rev1.9.dtsi
│ │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi
│ │ │ ├── versal-net-ipp-rev1.9.dtsi
│ │ │ ├── versal-net-vn-p-b2197-00-reva-pl.dtsi
│ │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi
│ │ │ ├── versal-net-vn-x-b2197-00-reva.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vck5000-reva.dtsi
│ │ │ ├── versal-vek280-reva.dtsi
│ │ │ ├── versal-vek280-revb.dtsi
│ │ │ ├── versal-vhk158-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── versal-vp-x-a2785-00-reva.dtsi
│ │ │ ├── versal-vpk120-reva.dtsi
│ │ │ ├── versal-vpk120-revb.dtsi
│ │ │ ├── versal-vpk180-reva.dtsi
│ │ │ ├── versal-x-ebm-01-reva.dtsi
│ │ │ ├── versal-x-ebm-02-reva.dtsi
│ │ │ ├── versal-x-ebm-03-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zcu670-reva.dtsi
│ │ │ ├── zcu670-revb.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-revb.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-sc-revb.dtsi
│ │ │ ├── zynqmp-sc-revc.dtsi
│ │ │ ├── zynqmp-sc-vek280-reva.dtsi
│ │ │ ├── zynqmp-sc-vek280-revb.dtsi
│ │ │ ├── zynqmp-sm-k24-reva.dtsi
│ │ │ ├── zynqmp-sm-k26-reva.dtsi
│ │ │ ├── zynqmp-smk-k24-reva.dtsi
│ │ │ ├── zynqmp-smk-k26-reva.dtsi
│ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi
│ │ │ └── zynqmp-vpk120-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ ├── xlnx-versal-net-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── dma/
│ │ │ │ └── xlnx-zynqmp-dpdma.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── net/
│ │ │ │ ├── mscc-phy-vsc8531.h
│ │ │ │ └── ti-dp83867.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-net-power.h
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ ├── xlnx-versal-regnode.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ ├── xlnx-versal-net-resets.h
│ │ │ ├── xlnx-versal-resets.h
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── versal-net/
│ │ │ ├── versal-net-clk-ccf.dtsi
│ │ │ ├── versal-net-clk.dtsi
│ │ │ ├── versal-net-ipp-rev1.9.dtsi
│ │ │ └── versal-net.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── v4.17/
│ │ ├── board/
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc1751-dc3.dtsi
│ │ │ ├── zc1751-dc4.dtsi
│ │ │ ├── zc1751-dc5.dtsi
│ │ │ ├── zcep108.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zcu111-reva.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── v4.18/
│ │ ├── board/
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc1751-dc3.dtsi
│ │ │ ├── zc1751-dc4.dtsi
│ │ │ ├── zc1751-dc5.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zcu111-reva.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── v4.19/
│ │ ├── board/
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc1751-dc3.dtsi
│ │ │ ├── zc1751-dc4.dtsi
│ │ │ ├── zc1751-dc5.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zcu111-reva.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── v4.20/
│ │ ├── board/
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc1751-dc3.dtsi
│ │ │ ├── zc1751-dc4.dtsi
│ │ │ ├── zc1751-dc5.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zcu111-reva.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── v5.0/
│ │ ├── board/
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc1751-dc3.dtsi
│ │ │ ├── zc1751-dc4.dtsi
│ │ │ ├── zc1751-dc5.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zcu111-reva.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── v5.1/
│ │ ├── board/
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc1751-dc3.dtsi
│ │ │ ├── zc1751-dc4.dtsi
│ │ │ ├── zc1751-dc5.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zcu111-reva.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── v5.2/
│ │ ├── board/
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc1751-dc3.dtsi
│ │ │ ├── zc1751-dc4.dtsi
│ │ │ ├── zc1751-dc5.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zcu111-reva.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── v5.3/
│ │ ├── board/
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc1751-dc3.dtsi
│ │ │ ├── zc1751-dc4.dtsi
│ │ │ ├── zc1751-dc5.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zcu111-reva.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ └── v5.4/
│ ├── board/
│ │ ├── avnet-ultra96-rev1.dtsi
│ │ ├── zc1232-reva.dtsi
│ │ ├── zc1254-reva.dtsi
│ │ ├── zc1275-reva.dtsi
│ │ ├── zc1751-dc1.dtsi
│ │ ├── zc1751-dc2.dtsi
│ │ ├── zc1751-dc3.dtsi
│ │ ├── zc1751-dc4.dtsi
│ │ ├── zc1751-dc5.dtsi
│ │ ├── zcu100-revc.dtsi
│ │ ├── zcu102-rev1.0.dtsi
│ │ ├── zcu102-reva.dtsi
│ │ ├── zcu102-revb.dtsi
│ │ ├── zcu104-reva.dtsi
│ │ ├── zcu106-reva.dtsi
│ │ └── zcu111-reva.dtsi
│ └── zynqmp/
│ ├── zynqmp-clk.dtsi
│ └── zynqmp.dtsi
├── dfx_axi_shutdown_manager/
│ └── data/
│ ├── dfx_axi_shutdown_manager.mdd
│ └── dfx_axi_shutdown_manager.tcl
├── dmaps/
│ └── data/
│ ├── dmaps.mdd
│ └── dmaps.tcl
├── dp/
│ └── data/
│ ├── dp.mdd
│ └── dp.tcl
├── dp_rx/
│ └── data/
│ ├── dp_rx.mdd
│ └── dp_rx.tcl
├── dp_tx/
│ └── data/
│ ├── dp_tx.mdd
│ └── dp_tx.tcl
├── dpu_eu/
│ └── data/
│ ├── dpu_eu.mdd
│ └── dpu_eu.tcl
├── emaclite/
│ └── data/
│ ├── emaclite.mdd
│ └── emaclite.tcl
├── emacps/
│ └── data/
│ ├── emacps.mdd
│ └── emacps.tcl
├── ernic/
│ └── data/
│ ├── ernic.mdd
│ └── ernic.tcl
├── framebuf_rd/
│ └── data/
│ ├── framebuf_rd.mdd
│ └── framebuf_rd.tcl
├── framebuf_wr/
│ └── data/
│ ├── framebuf_wr.mdd
│ └── framebuf_wr.tcl
├── gamma_lut/
│ └── data/
│ ├── gamma_lut.mdd
│ └── gamma_lut.tcl
├── generic/
│ └── data/
│ ├── generic.mdd
│ └── generic.tcl
├── globaltimerps/
│ └── data/
│ ├── globaltimerps.mdd
│ └── globaltimerps.tcl
├── gpiops/
│ └── data/
│ ├── gpiops.mdd
│ └── gpiops.tcl
├── hdmi_ctrl/
│ └── data/
│ ├── hdmi_ctrl.mdd
│ └── hdmi_ctrl.tcl
├── hdmi_gt_ctrl/
│ └── data/
│ ├── hdmi_gt_ctrl.mdd
│ └── hdmi_gt_ctrl.tcl
├── hdmi_rx_ss/
│ └── data/
│ ├── hdmi_rx_ss.mdd
│ └── hdmi_rx_ss.tcl
├── hdmi_tx_ss/
│ └── data/
│ ├── hdmi_tx_ss.mdd
│ └── hdmi_tx_ss.tcl
├── i2s_receiver/
│ └── data/
│ ├── i2s_receiver.mdd
│ └── i2s_receiver.tcl
├── i2s_transmitter/
│ └── data/
│ ├── i2s_transmitter.mdd
│ └── i2s_transmitter.tcl
├── i3cpsx/
│ └── data/
│ ├── i3cpsx.mdd
│ └── i3cpsx.tcl
├── iicps/
│ └── data/
│ ├── iicps.mdd
│ └── iicps.tcl
├── intc/
│ └── data/
│ ├── intc.mdd
│ └── intc.tcl
├── isppipeline/
│ └── data/
│ ├── ispipeline.mdd
│ └── ispipeline.tcl
├── mig_7series/
│ └── data/
│ ├── mig_7series.mdd
│ └── mig_7series.tcl
├── mipi_csi2_rx/
│ └── data/
│ ├── mipi_csi2_rx.mdd
│ └── mipi_csi2_rx.tcl
├── mipi_dsi_tx/
│ └── data/
│ ├── mipi_dsi_tx.mdd
│ └── mipi_dsi_tx.tcl
├── mixer/
│ └── data/
│ ├── mixer.mdd
│ └── mixer.tcl
├── mrmac/
│ └── data/
│ ├── mrmac.mdd
│ └── mrmac.tcl
├── multi_scaler/
│ └── data/
│ ├── multi_scaler.mdd
│ └── multi_scaler.tcl
├── nandps/
│ └── data/
│ ├── nandps.mdd
│ └── nandps.tcl
├── norps/
│ └── data/
│ ├── norps.mdd
│ └── norps.tcl
├── nvme_aggr/
│ └── data/
│ ├── nvme_aggr.mdd
│ └── nvme_aggr.tcl
├── ocmcps/
│ └── data/
│ ├── ocmcps.mdd
│ └── ocmcps.tcl
├── ospips/
│ └── data/
│ ├── ospips.mdd
│ └── ospips.tcl
├── pl310ps/
│ └── data/
│ ├── pl310ps.mdd
│ └── pl310ps.tcl
├── pmups/
│ └── data/
│ ├── pmups.mdd
│ └── pmups.tcl
├── pr_decoupler/
│ └── data/
│ ├── pr_decoupler.mdd
│ └── pr_decoupler.tcl
├── ptp_1588_timer_syncer/
│ └── data/
│ ├── ptp_1588_timer_syncer.mdd
│ └── ptp_1588_timer_syncer.tcl
├── qspips/
│ └── data/
│ ├── qspips.mdd
│ └── qspips.tcl
├── ramps/
│ └── data/
│ ├── ramps.mdd
│ └── ramps.tcl
├── rfdc/
│ └── data/
│ ├── rfdc.mdd
│ └── rfdc.tcl
├── scene_change_detector/
│ └── data/
│ ├── scene_change_detector.mdd
│ └── scene_change_detector.tcl
├── scugic/
│ └── data/
│ ├── scugic.mdd
│ └── scugic.tcl
├── scutimer/
│ └── data/
│ ├── scutimer.mdd
│ └── scutimer.tcl
├── scuwdt/
│ └── data/
│ ├── scuwdt.mdd
│ └── scuwdt.tcl
├── sdfec/
│ └── data/
│ ├── sdfec.mdd
│ └── sdfec.tcl
├── sdi_rx/
│ └── data/
│ ├── sdi_rx.mdd
│ └── sdi_rx.tcl
├── sdi_tx/
│ └── data/
│ ├── sdi_tx.mdd
│ └── sdi_tx.tcl
├── sdps/
│ └── data/
│ ├── sdps.mdd
│ └── sdps.tcl
├── slcrps/
│ └── data/
│ ├── slcrps.mdd
│ └── slcrps.tcl
├── smccps/
│ └── data/
│ ├── smccps.mdd
│ └── smccps.tcl
├── spips/
│ └── data/
│ ├── spips.mdd
│ └── spips.tcl
├── sync_ip/
│ └── data/
│ ├── sync_ip.mdd
│ └── sync_ip.tcl
├── sysmonpsv/
│ └── data/
│ ├── sysmonpsv.mdd
│ └── sysmonpsv.tcl
├── tmrctr/
│ └── data/
│ ├── tmrctr.mdd
│ └── tmrctr.tcl
├── tpg/
│ └── data/
│ ├── tpg.mdd
│ └── tpg.tcl
├── tsn/
│ └── data/
│ ├── tsn.mdd
│ └── tsn.tcl
├── ttcps/
│ └── data/
│ ├── ttcps.mdd
│ └── ttcps.tcl
├── uartlite/
│ └── data/
│ ├── uartlite.mdd
│ └── uartlite.tcl
├── uartns/
│ └── data/
│ ├── uartns.mdd
│ └── uartns.tcl
├── uartps/
│ └── data/
│ ├── uartps.mdd
│ └── uartps.tcl
├── usbps/
│ └── data/
│ ├── usbps.mdd
│ └── usbps.tcl
├── vid_phy_ctrl/
│ └── data/
│ ├── vid_phy_ctrl.mdd
│ └── vid_phy_ctrl.tcl
├── vproc_ss/
│ └── data/
│ ├── vproc_ss.mdd
│ └── vproc_ss.tcl
├── vtc/
│ └── data/
│ ├── vtc.mdd
│ └── vtc.tcl
├── wdtps/
│ └── data/
│ ├── wdtps.mdd
│ └── wdtps.tcl
└── xadcps/
└── data/
├── xadcps.mdd
└── xadcps.tcl
================================================
FILE CONTENTS
================================================
================================================
FILE: .github/pull_request_template.md
================================================
Please do not submit a Pull Request via github. Our project makes use
of mailing lists for patch submission and review. For more details
please see
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842172/Create+and+Submit+a+Patch
================================================
FILE: .gitignore
================================================
*~
================================================
FILE: RM/data/RM.mdd
================================================
#
# (C) Copyright 2017-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver RM
OPTION supported_peripherals = (RM);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = RM;
PARAMETER name = dev_type, default = fpga_region, type = string;
DTGPARAM name = compatible, default = "fpga-region", type = stringlist;
DTGPARAM name = "#address-cells", default = 1, type = int;
DTGPARAM name = "#size-cells", default = 1, type = int;
DTGPARAM name = ranges, type = boolean;
END driver
================================================
FILE: RM/data/RM.tcl
================================================
#
# (C) Copyright 2017-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
set val [get_property FAMILY [get_hw_designs]]
switch -glob $val {
"zynq" {
hsi::utils::add_new_property $drv_handle "fpga-mgr" string "<&devcfg>"
}
}
}
================================================
FILE: ai_engine/data/ai_engine.mdd
================================================
#
# (C) Copyright 2018-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver ai_engine
OPTION supported_peripherals = (ai_engine);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = ai_engine;
END driver
================================================
FILE: ai_engine/data/ai_engine.tcl
================================================
#
# (C) Copyright 2018-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
variable aie_array_cols_start
variable aie_array_cols_num
proc generate_aie_array_device_info {node drv_handle bus_node} {
set aie_array_id 0
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,ai-engine-v2.0"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
#set default values for S80 device
set hw_gen "AIE"
set aie_rows_start 1
set aie_rows_num 8
set mem_rows_start 0
set mem_rows_num 0
set shim_rows_start 0
set shim_rows_num 1
set ::aie_array_cols_start 0
set ::aie_array_cols_num 50
# override the above default values if AIE primitives are available in
# xsa
set CommandExists [ namespace which hsi::get_hw_primitives]
if {$CommandExists != ""} {
set aie_prop [hsi::get_hw_primitives aie]
if {$aie_prop != ""} {
puts "INFO: Reading AIE hardware properties from XSA."
set hw_gen [get_property HWGEN [hsi::get_hw_primitives aie]]
set aie_rows [get_property AIETILEROWS [hsi::get_hw_primitives aie]]
set mem_rows [get_property MEMTILEROW [hsi::get_hw_primitives aie]]
set shim_rows [get_property SHIMROW [hsi::get_hw_primitives aie]]
set ::aie_array_cols_num [get_property AIEARRAYCOLUMNS [hsi::get_hw_primitives aie]]
set aie_rows_start [lindex [split $aie_rows ":"] 0]
set aie_rows_num [lindex [split $aie_rows ":"] 1]
set mem_rows_start [lindex [split $mem_rows ":"] 0]
if {$mem_rows_start==-1} {
set mem_rows_start 0
}
set mem_rows_num [lindex [split $mem_rows ":"] 1]
set shim_rows_start [lindex [split $shim_rows ":"] 0]
set shim_rows_num [lindex [split $shim_rows ":"] 1]
} else {
dtg_warning "$drv_handle: AIE hardware properties are not available in XSA, using defaults."
}
} else {
dtg_warning "$drv_handle: AIE hardware properties are not available in XSA, using defaults."
}
if {$hw_gen=="AIE"} {
append aiegen "/bits/ 8 <0x1>"
} elseif {$hw_gen=="AIEML"} {
append aiegen "/bits/ 8 <0x2>"
}
hsi::utils::add_new_dts_param "${node}" "xlnx,aie-gen" $aiegen noformating
append shimrows "/bits/ 8 <${shim_rows_start} ${shim_rows_num}>"
hsi::utils::add_new_dts_param "${node}" "xlnx,shim-rows" $shimrows noformating
append corerows "/bits/ 8 <${aie_rows_start} ${aie_rows_num}>"
hsi::utils::add_new_dts_param "${node}" "xlnx,core-rows" $corerows noformating
append memrows "/bits/ 8 <$mem_rows_start $mem_rows_num>"
hsi::utils::add_new_dts_param "${node}" "xlnx,mem-rows" $memrows noformating
set name [get_property NAME [get_current_part $drv_handle]]
set part_num [string range $name 0 7]
if {$part_num == "xcvp2502"} {
#s100
set power_domain "&versal_firmware 0x18225072"
} elseif {$part_num == "xcvp2802"} {
#s200
set power_domain "&versal_firmware 0x18227072"
} else {
set power_domain "&versal_firmware 0x18224072"
}
hsi::utils::add_new_dts_param "${node}" "power-domains" $power_domain intlist
hsi::utils::add_new_dts_param "${node}" "#address-cells" "2" intlist
hsi::utils::add_new_dts_param "${node}" "#size-cells" "2" intlist
hsi::utils::add_new_dts_param "${node}" "ranges" "" boolean
set ai_clk_node [add_or_get_dt_node -n "aie_core_ref_clk_0" -l "aie_core_ref_clk_0" -p ${bus_node}]
set clk_freq [get_property CONFIG.AIE_CORE_REF_CTRL_FREQMHZ [get_cells -hier $drv_handle]]
set clk_freq [expr ${clk_freq} * 1000000]
hsi::utils::add_new_dts_param "${ai_clk_node}" "compatible" "fixed-clock" stringlist
hsi::utils::add_new_dts_param "${ai_clk_node}" "#clock-cells" 0 int
hsi::utils::add_new_dts_param "${ai_clk_node}" "clock-frequency" $clk_freq int
set clocks "aie_core_ref_clk_0"
set_drv_prop $drv_handle clocks "$clocks" reference
hsi::utils::add_new_dts_param "${node}" "clock-names" "aclk0" stringlist
return ${node}
}
proc generate {drv_handle} {
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set node [gen_peripheral_nodes $drv_handle]
if {$node == 0} {
return
}
set dt_overlay [get_property CONFIG.dt_overlay [get_os]]
if {$dt_overlay} {
set RpRm [hsi::utils::get_rp_rm_for_drv $drv_handle]
regsub -all { } $RpRm "" RpRm
set bus_node "amba"
} else {
set bus_node "amba_pl"
}
generate_aie_array_device_info ${node} ${drv_handle} ${bus_node}
set ip [get_cells -hier $drv_handle]
set unit_addr [get_baseaddr ${ip} no_prefix]
set aperture_id 0
set aperture_node [add_or_get_dt_node -n "aie_aperture" -u "${unit_addr}" -l "aie_aperture_${aperture_id}" -p ${node}]
set reg [get_property CONFIG.reg ${drv_handle}]
hsi::utils::add_new_dts_param "${aperture_node}" "reg" $reg noformat
set name [get_property NAME [get_current_part $drv_handle]]
set part_num [string range $name 0 7]
set part_num_v70 [string range $name 0 4]
if {$part_num == "xcvp2502"} {
#s100
set power_domain "&versal_firmware 0x18225072"
hsi::utils::add_new_dts_param "${aperture_node}" "xlnx,device-name" "100" int
set aperture_nodeid 0x18801000
} elseif {$part_num == "xcvp2802"} {
#s200
set power_domain "&versal_firmware 0x18227072"
hsi::utils::add_new_dts_param "${aperture_node}" "xlnx,device-name" "200" int
set aperture_nodeid 0x18803000
} elseif {$part_num_v70 == "xcv70"} {
#v70
set power_domain "&versal_firmware 0x18224072"
hsi::utils::add_new_dts_param "${aperture_node}" "xlnx,device-name" "0" int
set aperture_nodeid 0x18800000
} else {
#NON SSIT devices
set intr_names "interrupt1"
lappend intr_names "interrupt2"
lappend intr_names "interrupt3"
set intr_num "0x0 0x94 0x4>, <0x0 0x95 0x4>, <0x0 0x96 0x4"
set power_domain "&versal_firmware 0x18224072"
hsi::utils::add_new_dts_param "${aperture_node}" "interrupt-names" $intr_names stringlist
hsi::utils::add_new_dts_param "${aperture_node}" "interrupts" $intr_num intlist
hsi::utils::add_new_dts_param "${aperture_node}" "interrupt-parent" gic reference
hsi::utils::add_new_dts_param "${aperture_node}" "xlnx,device-name" "0" int
set aperture_nodeid 0x18800000
}
hsi::utils::add_new_dts_param "${aperture_node}" "power-domains" $power_domain intlist
hsi::utils::add_new_dts_param "${aperture_node}" "#address-cells" "2" intlist
hsi::utils::add_new_dts_param "${aperture_node}" "#size-cells" "2" intlist
hsi::utils::add_new_dts_param "${aperture_node}" "xlnx,columns" "$::aie_array_cols_start $::aie_array_cols_num" intlist
hsi::utils::add_new_dts_param "${aperture_node}" "xlnx,node-id" "${aperture_nodeid}" intlist
}
================================================
FILE: ams/data/ams.mdd
================================================
#
# (C) Copyright 2017-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver ams
OPTION supported_peripherals = (psu_ams);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = ams;
END driver
================================================
FILE: ams/data/ams.tcl
================================================
#
# (C) Copyright 2017-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set mainline_ker [get_property CONFIG.mainline_kernel [get_os]]
if {[string match -nocase $mainline_ker "none"]} {
set ams_list "ams_ps ams_pl"
set dts_file [get_property CONFIG.pcw_dts [get_os]]
foreach ams_name ${ams_list} {
set ams_node [add_or_get_dt_node -n "&${ams_name}" -d $dts_file]
hsi::utils::add_new_dts_param "${ams_node}" "status" "okay" string
}
}
}
================================================
FILE: apmps/data/apmps.mdd
================================================
#
# (C) Copyright 2019-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver apmps
OPTION supported_peripherals = (psu_apm psv_apm psx_apm);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = apmps;
END driver
================================================
FILE: apmps/data/apmps.tcl
================================================
#
# (C) Copyright 2019-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
}
================================================
FILE: audio_embed/data/audio_embed.mdd
================================================
#
# (C) Copyright 2018-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver audio_embed
OPTION supported_peripherals = (v_uhdsdi_audio);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = audio_embed;
DTGPARAM name = dtg.ip_params, type = boolean;
END driver
================================================
FILE: audio_embed/data/audio_embed.tcl
================================================
#
# (C) Copyright 2018-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set node [gen_peripheral_nodes $drv_handle]
if {$node == 0} {
return
}
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,v-uhdsdi-audio-2.0"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
set connected_embed_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "SDI_EMBED_ANC_DS_IN"]
if {[llength $connected_embed_ip] != 0} {
set connected_embed_ip_type [get_property IP_NAME $connected_embed_ip]
if {[string match -nocase $connected_embed_ip_type "v_smpte_uhdsdi_tx_ss"]} {
set sdi_av_port [add_or_get_dt_node -n "port" -l sdi_av_port -u 0 -p $node]
hsi::utils::add_new_dts_param "$sdi_av_port" "reg" 0 int
set sdi_embed_node [add_or_get_dt_node -n "endpoint" -l sditx_audio_embed_src -p $sdi_av_port]
hsi::utils::add_new_dts_param "$sdi_embed_node" "remote-endpoint" sdi_audio_sink_port reference
}
} else {
dtg_warning "$drv_handle connected_ip is NULL for the pin SDI_EMBED_ANC_DS_IN"
}
set connected_extract_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "SDI_EXTRACT_ANC_DS_IN"]
if {[llength $connected_extract_ip] != 0} {
hsi::utils::add_new_dts_param "$node" "xlnx,sdi-rx-video" $connected_extract_ip reference
} else {
dtg_warning "$drv_handle connected_extract_ip is NULL for the pin SDI_EXTRACT_ANC_DS_IN"
}
set connected_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "S_AXIS_DATA"]
if {[llength $connected_ip] != 0} {
set index [lsearch [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $connected_ip]
if {$index != -1 } {
hsi::utils::add_new_dts_param "$node" "xlnx,snd-pcm" $connected_ip reference
}
} else {
dtg_warning "$drv_handle connected ip is NULL for the pin S_AXIS_DATA"
}
set connect_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "M_AXIS_DATA"]
if {[llength $connect_ip] != 0} {
set index [lsearch [get_mem_ranges -of_objects [get_cells -hier [get_sw_processor]]] $connect_ip]
if {$index != -1 } {
hsi::utils::add_new_dts_param "$node" "xlnx,snd-pcm" $connect_ip reference
}
} else {
dtg_warning "$drv_handle connected ip is NULL for the pin M_AXIS_DATA"
}
}
================================================
FILE: audio_formatter/data/audio_formatter.mdd
================================================
#
# (C) Copyright 2018-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver audio_formatter
OPTION supported_peripherals = (audio_formatter);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = audio_formatter;
DTGPARAM name = dtg.ip_params, type = boolean;
END driver
================================================
FILE: audio_formatter/data/audio_formatter.tcl
================================================
#
# (C) Copyright 2018-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set node [gen_peripheral_nodes $drv_handle]
if {$node == 0} {
return
}
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,audio-formatter-1.0"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
set tx_connect_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "m_axis_mm2s"]
if {[llength $tx_connect_ip] != 0} {
hsi::utils::add_new_dts_param "$node" "xlnx,tx" $tx_connect_ip reference
} else {
dtg_warning "$drv_handle pin m_axis_mm2s is not connected... check your design"
}
set rx_connect_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] "s_axis_s2mm"]
if {[llength $rx_connect_ip] != 0} {
hsi::utils::add_new_dts_param "$node" "xlnx,rx" $rx_connect_ip reference
} else {
dtg_warning "$drv_handle pin s_axis_s2mm is not connected... check your design"
}
}
================================================
FILE: audio_spdif/data/audio_spdif.mdd
================================================
#
# (C) Copyright 2018-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver audio_spdif
OPTION supported_peripherals = (spdif);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = audio_spdif;
END driver
================================================
FILE: audio_spdif/data/audio_spdif.tcl
================================================
#
# (C) Copyright 2018-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set node [gen_peripheral_nodes $drv_handle]
if {$node == 0} {
return
}
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,spdif-2.0"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
set spdif_mode [get_property CONFIG.SPDIF_Mode [get_cells -hier $drv_handle]]
hsi::utils::add_new_dts_param "${node}" "xlnx,spdif-mode" $spdif_mode int
set cstatus_reg [get_property CONFIG.CSTATUS_REG [get_cells -hier $drv_handle]]
hsi::utils::add_new_dts_param "${node}" "xlnx,chstatus-reg" $cstatus_reg int
set userdata_reg [get_property CONFIG.USERDATA_REG [get_cells -hier $drv_handle]]
hsi::utils::add_new_dts_param "${node}" "xlnx,userdata-reg" $userdata_reg int
set axi_buffer_size [get_property CONFIG.AXI_BUFFER_Size [get_cells -hier $drv_handle]]
hsi::utils::add_new_dts_param "${node}" "xlnx,fifo-depth" $axi_buffer_size int
set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "aud_clk_i"]
if {[llength $clk_freq] != 0} {
hsi::utils::add_new_dts_param "${node}" "clock-frequency" $clk_freq int
}
}
================================================
FILE: axi_can/data/axi_can.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_can
OPTION supported_peripherals = (can canfd);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_can;
DTGPARAM name = compatible, type = stringlist, default = "xlnx,axi-can-1.00.a";
END driver
================================================
FILE: axi_can/data/axi_can.tcl
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
# try to source the common tcl procs
# assuming the order of return is based on repo priority
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set node [gen_peripheral_nodes $drv_handle]
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,axi-can-1.00.a"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
set ip_name [get_property IP_NAME [get_cells -hier $drv_handle]]
set ecc [get_property CONFIG.ENABLE_ECC [get_cells -hier $drv_handle]]
if { [llength $ecc] } {
hsi::utils::add_new_dts_param $node "xlnx,has-ecc" "" boolean
}
set version [string tolower [common::get_property VLNV $drv_handle]]
if {[string match -nocase $ip_name "canfd"]} {
if {[string compare -nocase "xilinx.com:ip:canfd:1.0" $version] == 0} {
hsi::utils::add_new_property $drv_handle "compatible" stringlist "xlnx,canfd-1.0"
} else {
hsi::utils::add_new_property $drv_handle "compatible" stringlist "xlnx,canfd-2.0"
}
set_drv_conf_prop $drv_handle NUM_OF_TX_BUF tx-mailbox-count hexint
set_drv_conf_prop $drv_handle NUM_OF_TX_BUF rx-fifo-depth hexint
} else {
set_drv_conf_prop $drv_handle c_can_tx_dpth tx-fifo-depth hexint
set_drv_conf_prop $drv_handle c_can_rx_dpth rx-fifo-depth hexint
}
set proc_type [get_sw_proc_prop IP_NAME]
switch $proc_type {
"microblaze" {
gen_dev_ccf_binding $drv_handle "s_axi_aclk"
}
}
}
================================================
FILE: axi_cdma/data/axi_cdma.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_cdma
OPTION supported_peripherals = (axi_cdma);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_cdma;
DTGPARAM name = dev_type, default = dma , type = string;
DTGPARAM name = compatible, type = stringlist, default = "xlnx,axi-cdma-1.00.a";
DTGPARAM name = "#dma-cells", type = int, default = 1;
END driver
================================================
FILE: axi_cdma/data/axi_cdma.tcl
================================================
#
# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
# Based on original code:
# (C) Copyright 2007-2014 Michal Simek
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Michal SIMEK <monstr@monstr.eu>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
# try to source the common tcl procs
# assuming the order of return is based on repo priority
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set_drv_conf_prop $drv_handle C_INCLUDE_SG xlnx,include-sg boolean
set_drv_conf_prop $drv_handle C_NUM_FSTORES xlnx,num-fstores
set_drv_conf_prop $drv_handle C_USE_FSYNC xlnx,flush-fsync
set_drv_conf_prop $drv_handle C_ADDR_WIDTH xlnx,addrwidth
set node [gen_peripheral_nodes $drv_handle]
if {$node == 0} {
return
}
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,axi-cdma-1.00.a"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
set dma_ip [get_cells -hier $drv_handle]
set cdma_count [hsi::utils::get_os_parameter_value "cdma_count"]
if { [llength $cdma_count] == 0 } {
set cdma_count 0
}
set baseaddr [get_baseaddr $dma_ip no_prefix]
set tx_chan [add_dma_channel $drv_handle $node "axi-cdma" $baseaddr "MM2S" $cdma_count ]
incr cdma_count
hsi::utils::set_os_parameter_value "cdma_count" $cdma_count
set mainline_ker [get_property CONFIG.mainline_kernel [get_os]]
if {[string match -nocase $mainline_ker "none"]} {
set proc_type [get_sw_proc_prop IP_NAME]
switch $proc_type {
"microblaze" {
gen_dev_ccf_binding $drv_handle "s_axi_lite_aclk m_axi_aclk"
set_drv_prop_if_empty $drv_handle "clock-names" "s_axi_lite_aclk m_axi_aclk" stringlist
}
}
} else {
generate_clk_nodes $drv_handle
}
}
proc add_dma_channel {drv_handle parent_node xdma addr mode devid} {
#set ip [get_cells -hier $drv_handle]
set modellow [string tolower $mode]
set modeIndex [string index $mode 0]
#set node_name [format "dma-channel@%x" $addr]
set dma_channel [add_or_get_dt_node -n "dma-channel" -u $addr -p $parent_node]
hsi::utils::add_new_dts_param $dma_channel "compatible" [format "xlnx,%s-channel" $xdma] stringlist
hsi::utils::add_new_dts_param $dma_channel "xlnx,device-id" $devid hexint
add_cross_property_to_dtnode $drv_handle "CONFIG.C_INCLUDE_DRE" $dma_channel "xlnx,include-dre" boolean
add_cross_property_to_dtnode $drv_handle "CONFIG.C_M_AXI_DATA_WIDTH" $dma_channel "xlnx,datawidth"
add_cross_property_to_dtnode $drv_handle "CONFIG.C_USE_DATAMOVER_LITE" $dma_channel "xlnx,lite-mode" boolean
add_cross_property_to_dtnode $drv_handle "CONFIG.C_M_AXI_MAX_BURST_LEN" $dma_channel "xlnx,max-burst-len"
set intr_info [get_intr_id $drv_handle "cdma_introut" ]
if { [llength $intr_info] && ![string match -nocase $intr_info "-1"] } {
hsi::utils::add_new_dts_param $dma_channel "interrupts" $intr_info intlist
} else {
dtg_warning "ERROR: ${drv_handle}: cdma_introut port is not connected"
}
return $dma_channel
}
proc generate_clk_nodes {drv_handle} {
set proc_type [get_sw_proc_prop IP_NAME]
switch $proc_type {
"ps7_cortexa9" {
set_drv_prop_if_empty $drv_handle "clocks" "clkc 15>, <&clkc 15" reference
set_drv_prop_if_empty $drv_handle "clock-names" "s_axi_lite_aclk m_axi_aclk" stringlist
} "psu_cortexa53" {
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "s_axi_lite_aclk"]
if {![string equal $clk_freq ""]} {
if {[lsearch $bus_clk_list $clk_freq] < 0} {
set bus_clk_list [lappend bus_clk_list $clk_freq]
}
}
set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]
set dts_file [current_dt_tree]
set bus_node [add_or_get_bus_node $drv_handle $dts_file]
set misc_clk_node [add_or_get_dt_node -n "misc_clk_${bus_clk_cnt}" -l "misc_clk_${bus_clk_cnt}" \
-d ${dts_file} -p ${bus_node}]
hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-clock" stringlist
hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int
hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int
set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]
set_drv_prop_if_empty $drv_handle "clocks" "$clk_refs>, <&$clk_refs" reference
set_drv_prop_if_empty $drv_handle "clock-names" "s_axi_lite_aclk m_axi_aclk" stringlist
} "microblaze" {
gen_dev_ccf_binding $drv_handle "s_axi_lite_aclk m_axi_aclk"
set_drv_prop_if_empty $drv_handle "clock-names" "s_axi_lite_aclk m_axi_aclk" stringlist
}
default {
error "Unknown arch"
}
}
}
================================================
FILE: axi_clk_wiz/data/axi_clk_wiz.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_clk_wiz
OPTION supported_peripherals = (clk_wiz clk_wizard);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_clk_wiz;
#DTGPARAM name = dtg.ip_params, type = boolean;
DTGPARAM name = compatible, type = stringlist, default = "xlnx,clocking-wizard";
DTGPARAM name = clock-output-names, type = stringlist, default = "";
DTGPARAM name = "#clock-cells", type = int, default = 1;
END driver
================================================
FILE: axi_clk_wiz/data/axi_clk_wiz.tcl
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
# try to source the common tcl procs
# assuming the order of return is based on repo priority
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,clocking-wizard"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
set ip [get_cells -hier $drv_handle]
gen_speedgrade $drv_handle
set j 0
set output_names ""
for {set i 1} {$i < 8} {incr i} {
if {[get_property CONFIG.C_CLKOUT${i}_USED $ip] != 0} {
set freq [get_property CONFIG.C_CLKOUT${i}_OUT_FREQ $ip]
set pin_name [get_property CONFIG.C_CLK_OUT${i}_PORT $ip]
set basefrq [string tolower [get_property CONFIG.C_BASEADDR $ip]]
set pin_name "$basefrq-$pin_name"
lappend output_names $pin_name
incr j
}
}
if {![string_is_empty $output_names]} {
set_property CONFIG.clock-output-names $output_names $drv_handle
hsi::utils::add_new_property $drv_handle "xlnx,nr-outputs" int $j
}
gen_dev_ccf_binding $drv_handle "clk_in1 s_axi_aclk" "clocks clock-names"
set sw_proc [get_sw_processor]
set proc_ip [get_cells -hier $sw_proc]
set proctype [get_property IP_NAME $proc_ip]
if {[string match -nocase $proctype "microblaze"] } {
gen_dev_ccf_binding $drv_handle "clk_in1 s_axi_aclk" "clocks clock-names"
}
}
proc gen_speedgrade {drv_handle} {
set speedgrade [get_property SPEEDGRADE [get_hw_designs]]
set num [regexp -all -inline -- {[0-9]} $speedgrade]
if {![string equal $num ""]} {
hsi::utils::add_new_property $drv_handle "xlnx,speed-grade" int $num
}
}
================================================
FILE: axi_dma/data/axi_dma.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_dma
OPTION supported_peripherals = (axi_dma);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_dma;
DTGPARAM name = dev_type, default = dma , type = string;
DTGPARAM name = compatible, type = stringlist, default = "xlnx,axi-dma-1.00.a";
DTGPARAM name = "#dma-cells", type = int, default = 1;
END driver
================================================
FILE: axi_dma/data/axi_dma.tcl
================================================
#
# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
# Based on original code:
# (C) Copyright 2007-2014 Michal Simek
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Michal SIMEK <monstr@monstr.eu>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
set connected_ip 0
proc generate {drv_handle} {
global connected_ip
# try to source the common tcl procs
# assuming the order of return is based on repo priority
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set node [gen_peripheral_nodes $drv_handle]
if {$node == 0} {
return
}
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,axi-dma-1.00.a"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
set dma_ip [get_cells -hier $drv_handle]
set dma_count [hsi::utils::get_os_parameter_value "dma_count"]
if { [llength $dma_count] == 0 } {
set dma_count 0
}
set axiethernetfound 0
set connected_ip [hsi::utils::get_connected_stream_ip $dma_ip "M_AXIS_MM2S"]
if { [llength $connected_ip] } {
set connected_ip_type [get_property IP_NAME $connected_ip]
if { [string match -nocase $connected_ip_type axi_ethernet ]
|| [string match -nocase $connected_ip_type axi_ethernet_buffer ] } {
set axiethernetfound 1
}
} else {
dtg_warning "$drv_handle connected ip is NULL for the pin M_AXIS_MM2S"
}
set is_xxv [get_connected_ip $drv_handle "M_AXIS_MM2S"]
if { $axiethernetfound || $is_xxv == 1} {
set compatstring "xlnx,eth-dma"
set_property compatible "$compatstring" $drv_handle
}
set tx_chan 0
set rx_chan 0
if { $axiethernetfound != 1 && $is_xxv != 1} {
set_drv_conf_prop $drv_handle C_INCLUDE_SG xlnx,include-sg boolean
set_drv_conf_prop $drv_handle C_SG_INCLUDE_STSCNTRL_STRM xlnx,sg-include-stscntrl-strm boolean
set_drv_conf_prop $drv_handle c_enable_multi_channel xlnx,multichannel-dma boolean
set_drv_conf_prop $drv_handle c_addr_width xlnx,addrwidth
set_drv_conf_prop $drv_handle c_sg_length_width xlnx,sg-length-width
set baseaddr [get_baseaddr $dma_ip no_prefix]
set tx_chan [hsi::utils::get_ip_param_value $dma_ip C_INCLUDE_MM2S]
if { $tx_chan == 1 } {
set connected_ip [hsi::utils::get_connected_stream_ip $dma_ip "M_AXIS_MM2S"]
set tx_chan_node [add_dma_channel $drv_handle $node "axi-dma" $baseaddr "MM2S" $dma_count ]
set intr_info [get_intr_id $drv_handle "mm2s_introut"]
#set intc [hsi::utils::get_interrupt_parent $dma_ip "mm2s_introut"]
if { [llength $intr_info] && ![string match -nocase $intr_info "-1"] } {
hsi::utils::add_new_dts_param $tx_chan_node "interrupts" $intr_info intlist
} else {
dtg_warning "ERROR: ${drv_handle}: mm2s_introut port is not connected"
}
add_dma_coherent_prop $drv_handle "M_AXI_MM2S"
}
set rx_chan [hsi::utils::get_ip_param_value $dma_ip C_INCLUDE_S2MM]
if { $rx_chan ==1 } {
set connected_ip [hsi::utils::get_connected_stream_ip $dma_ip "S_AXIS_S2MM"]
set rx_bassaddr [format %08x [expr 0x$baseaddr + 0x30]]
set rx_chan_node [add_dma_channel $drv_handle $node "axi-dma" $rx_bassaddr "S2MM" $dma_count]
set intr_info [get_intr_id $drv_handle "s2mm_introut"]
#set intc [hsi::utils::get_interrupt_parent $dma_ip "s2mm_introut"]
if { [llength $intr_info] && ![string match -nocase $intr_info "-1"] } {
hsi::utils::add_new_dts_param $rx_chan_node "interrupts" $intr_info intlist
} else {
dtg_warning "ERROR: ${drv_handle}: s2mm_introut port is not connected"
}
add_dma_coherent_prop $drv_handle "M_AXI_S2MM"
}
} else {
set proc_type [get_sw_proc_prop IP_NAME]
if {[string match -nocase $proc_type "ps7_cortexa9"] || [string match -nocase $proc_type "microblaze"] } {
set_drv_property $drv_handle axistream-connected "$connected_ip" reference
set_drv_property $drv_handle axistream-control-connected "$connected_ip" reference
}
set ip_prop CONFIG.c_include_mm2s_dre
add_cross_property $drv_handle $ip_prop $drv_handle "xlnx,include-dre" boolean
set addr_width [get_property CONFIG.c_addr_width $dma_ip]
set inhex [format %x $addr_width]
append addrwidth "/bits/ 8 <0x$inhex>"
hsi::utils::add_new_dts_param "$node" "xlnx,addrwidth" $addrwidth noformating
set num_queues [get_property CONFIG.c_num_mm2s_channels $dma_ip]
set inhex [format %x $num_queues]
append numqueues "/bits/ 16 <0x$inhex>"
hsi::utils::add_new_dts_param $node "xlnx,num-queues" $numqueues noformating
}
incr dma_count
hsi::utils::set_os_parameter_value "dma_count" $dma_count
set mainline_ker [get_property CONFIG.mainline_kernel [get_os]]
if {[string match -nocase $mainline_ker "none"]} {
set proc_type [get_sw_proc_prop IP_NAME]
if {[string match -nocase $proc_type "microblaze"]} {
generate_clk_nodes $drv_handle $axiethernetfound $tx_chan $rx_chan
}
} else {
generate_clk_nodes $drv_handle $axiethernetfound $tx_chan $rx_chan
}
}
proc add_dma_channel {drv_handle parent_node xdma addr mode devid} {
set modellow [string tolower $mode]
set modeIndex [string index $mode 0]
set dma_channel [add_or_get_dt_node -n "dma-channel" -u $addr -p $parent_node]
hsi::utils::add_new_dts_param $dma_channel "compatible" [format "xlnx,%s-%s-channel" $xdma $modellow] stringlist
hsi::utils::add_new_dts_param $dma_channel "xlnx,device-id" $devid hexint
add_cross_property_to_dtnode $drv_handle [format "CONFIG.C_INCLUDE_%s_DRE" $mode] $dma_channel "xlnx,include-dre" boolean
if {[string match -nocase $mode "MM2S"]} {
set datawidth [get_property CONFIG.C_M_AXI_MM2S_DATA_WIDTH [get_cells -hier $drv_handle]]
}
if {[string match -nocase $mode "S2MM"]} {
set datawidth [get_property CONFIG.C_S_AXIS_S2MM_TDATA_WIDTH [get_cells -hier $drv_handle]]
}
hsi::utils::add_new_dts_param $dma_channel "xlnx,datawidth" $datawidth hexint
set num_channles [get_property CONFIG.c_num_mm2s_channels [get_cells -hier $drv_handle]]
hsi::utils::add_new_dts_param $dma_channel "dma-channels" $num_channles hexint
return $dma_channel
}
proc add_dma_coherent_prop {drv_handle intf} {
set ip_name [::hsi::get_cells -hier -filter "NAME==$drv_handle"]
set connectedip [hsi::utils::get_connected_stream_ip $drv_handle $intf]
if {[llength $connectedip] == 0} {
return
}
set intrconnect [get_property IP_NAME [get_cells -hier $connectedip]]
set num_master [get_property CONFIG.NUM_MI $connectedip]
set done 0
# check whether dma connected to interconnect ip, loop until you get the
# port name ACP or HP
while {[string match -nocase $intrconnect "axi_interconnect"]} {
# loop over number of master interfaces
set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectedip] -filter {TYPE==MASTER}]
if {[llength $master_intf] == 0} {
break
}
foreach interface ${master_intf} {
set intf_port [hsi::utils::get_connected_intf $connectedip $interface]
set intrconnect [hsi::utils::get_connected_stream_ip $connectedip $interface]
if {![string_is_empty $intf_port] && [string match -nocase $intf_port "S_AXI_ACP"]} {
hsi::utils::add_new_property $drv_handle "dma-coherent" boolean ""
# here dma connected to ACP port
set done 1
break;
}
if {$done} {
break
}
}
}
}
proc generate_clk_nodes {drv_handle axiethernetfound tx_chan rx_chan} {
set proc_type [get_sw_proc_prop IP_NAME]
set clocknames "s_axi_lite_aclk"
switch $proc_type {
"ps7_cortexa9" {
set clocks "clkc 15"
if { $axiethernetfound != 1 } {
append clocknames " " "m_axi_sg_aclk"
append clocks "" ">, <&clkc 15"
}
if { $tx_chan ==1 } {
append clocknames " " "m_axi_mm2s_aclk"
append clocks "" ">, <&clkc 15"
}
if { $rx_chan ==1 } {
append clocknames " " "m_axi_s2mm_aclk"
append clocks "" ">, <&clkc 15"
}
set_drv_prop_if_empty $drv_handle "clocks" $clocks reference
set_drv_prop_if_empty $drv_handle "clock-names" $clocknames stringlist
} "psu_cortexa53" {
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "s_axi_lite_aclk"]
if {![string equal $clk_freq ""]} {
if {[lsearch $bus_clk_list $clk_freq] < 0} {
set bus_clk_list [lappend bus_clk_list $clk_freq]
}
}
set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]
set dts_file [current_dt_tree]
set bus_node [add_or_get_bus_node $drv_handle $dts_file]
set misc_clk_node [add_or_get_dt_node -n "misc_clk_${bus_clk_cnt}" -l "misc_clk_${bus_clk_cnt}" \
-d ${dts_file} -p ${bus_node}]
hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-clock" stringlist
hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int
hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int
set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]
set clocks "$clk_refs"
if { $axiethernetfound != 1 } {
append clocknames " " "m_axi_sg_aclk"
append clocks "" ">, <&$clk_refs"
}
if { $tx_chan ==1 } {
append clocknames " " "m_axi_mm2s_aclk"
append clocks "" ">, <&$clk_refs"
}
if { $rx_chan ==1 } {
append clocknames " " "m_axi_s2mm_aclk"
append clocks "" ">, <&$clk_refs"
}
set_drv_prop_if_empty $drv_handle "clocks" "$clocks" reference
set_drv_prop_if_empty $drv_handle "clock-names" "$clocknames" stringlist
} "microblaze" {
if { $axiethernetfound != 1 } {
append clocknames " " "m_axi_sg_aclk"
}
if { $tx_chan ==1 } {
append clocknames " " "m_axi_mm2s_aclk"
}
if { $rx_chan ==1 } {
append clocknames " " "m_axi_s2mm_aclk"
}
gen_dev_ccf_binding $drv_handle "$clocknames"
set_drv_prop_if_empty $drv_handle "clock-names" "$clocknames" stringlist
}
default {
error "Unknown arch"
}
}
}
proc get_connected_ip {drv_handle dma_pin} {
global connected_ip
# Check whether dma is connected to 10G/25G MAC
# currently we are handling only data fifo
set intf [::hsi::get_intf_pins -of_objects [get_cells -hier $drv_handle] $dma_pin]
set valid_eth_list "xxv_ethernet axi_ethernet axi_10g_ethernet usxgmii ethernet_1_10_25g"
if {[string_is_empty ${intf}]} {
return 0
}
set connected_ip [::hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] $intf]
if {[string_is_empty ${connected_ip}]} {
dtg_warning "$drv_handle connected ip is NULL for the pin $intf"
return 0
}
set iptype [get_property IP_NAME [get_cells -hier $connected_ip]]
if {[string match -nocase $iptype "axis_data_fifo"] } {
# here dma connected to data fifo
set dma_pin "M_AXIS"
get_connected_ip $connected_ip $dma_pin
} elseif {[lsearch -nocase $valid_eth_list $iptype] >= 0 } {
# dma connected to 10G/25G MAC, 1G or 10G
return 1
} elseif {[string match -nocase $iptype "axis_add_tuser"]|| [string match -nocase $iptype "axis_duplicate_master_out"]} {
set dma_pin "mas_0"
get_connected_ip $connected_ip $dma_pin
} elseif {[string match -nocase $iptype "axis_switch"]} {
set dma_pin "M00_AXIS"
get_connected_ip $connected_ip $dma_pin
} else {
# dma connected via interconnects
set dma_pin "M_AXIS"
get_connected_ip $connected_ip $dma_pin
}
}
================================================
FILE: axi_emc/data/axi_emc.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_emc
OPTION supported_peripherals = (axi_emc);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_emc;
OPTION supported_os_types = (DTS);
DTGPARAM name = dtg.ip_params, type = boolean;
DTGPARAM name = dev_type, default = flash , type = string;
DTGPARAM name = compatible, type =stringlist, default = "cfi-flash";
DTGPARAM name = bank-width, type = int;
END driver
================================================
FILE: axi_emc/data/axi_emc.tcl
================================================
#
# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
# Based on original code:
# (C) Copyright 2007-2014 Michal Simek
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Michal SIMEK <monstr@monstr.eu>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set ip [get_cells -hier $drv_handle]
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "cfi-flash"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
set count [hsi::utils::get_ip_param_value $ip "C_NUM_BANKS_MEM"]
if { [llength $count] == 0 } {
set count 1
}
for {set x 0} { $x < $count} {incr x} {
set datawidth [hsi::utils::get_ip_param_value $ip [format "C_MEM%d_WIDTH" $x]]
set_property bank-width "[expr ($datawidth/8)]" $drv_handle
}
}
================================================
FILE: axi_ethernet/data/axi_ethernet.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_ethernet
OPTION supported_peripherals = (axi_ethernet axi_ethernet_buffer axi_10g_ethernet xxv_ethernet usxgmii ethernet_1_10_25g);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_ethernet;
OPTION supported_os_types = (DTS);
PARAMETER name = dev_type, default = ethernet, type = string;
DTGPARAM name = dtg.ip_params, type = boolean;
DTGPARAM name = dtg.alias , type = reference, default = ethernet;
DTGPARAM name = axistream-connected , type = reference;
DTGPARAM name = axistream-control-connected, type = reference;
DTGPARAM name = clock-frequency, type = int, default = 100000000;
DTGPARAM name = compatible, type =stringlist, default = "xlnx,axi-ethernet-1.00.a";
DTGPARAM name = device_type, type = string, default = network;
DTGPARAM name = xlnx,txcsum, type = hex, default = 0x0;
DTGPARAM name = xlnx,rxcsum, type = hex, default = 0x0;
DTGPARAM name = xlnx,rxmem, type = hex, default = 0x8000;
DTGPARAM name = xlnx,phyaddr, type = hex, default = 0x0;
DTGPARAM name = phy-mode, default = gmii
END driver
================================================
FILE: axi_ethernet/data/axi_ethernet.tcl
================================================
#
# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
# Based on original code:
# (C) Copyright 2007-2014 Michal Simek
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Michal SIMEK <monstr@monstr.eu>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
set rxethmem 0
proc generate {drv_handle} {
global rxethmem
set rxethmem 0
global ddrv_handle
set ddrv_handle $drv_handle
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set remove_pl [get_property CONFIG.remove_pl [get_os]]
if {[is_pl_ip $drv_handle] && $remove_pl} {
return 0
}
set node [gen_peripheral_nodes $drv_handle]
set hw_design [hsi::current_hw_design]
set board_name ""
if {[llength $hw_design]} {
set board [split [get_property BOARD $hw_design] ":"]
set board_name [lindex $board 1]
}
update_eth_mac_addr $drv_handle
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,axi-ethernet-1.00.a"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
set dt_overlay [get_property CONFIG.dt_overlay [get_os]]
set default_dts [set_drv_def_dts $drv_handle]
#adding stream connectivity
set eth_ip [get_cells -hier $drv_handle]
# search for a valid bus interface name
# This is required to work with Vivado 2015.1 due to IP PIN naming change
set hasbuf [get_property CONFIG.processor_mode $eth_ip]
set ip_name [get_property IP_NAME $eth_ip]
set num_cores 1
if {($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")} {
set ip_mem_handles [hsi::utils::get_ip_mem_ranges [get_cells -hier $drv_handle]]
set num 0
set base [string tolower [get_property BASE_VALUE [lindex $ip_mem_handles $num]]]
set high [string tolower [get_property HIGH_VALUE [lindex $ip_mem_handles $num]]]
set reg [generate_reg_property $base $high]
hsi::utils::add_new_dts_param "${node}" "reg" $reg inthexlist
set num_cores [get_property CONFIG.NUM_OF_CORES [get_cells -hier $drv_handle]]
}
set new_label ""
set clk_label ""
set connected_ip ""
set eth_node ""
for {set core 0} {$core < $num_cores} {incr core} {
if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core != 0)} {
if {$dt_overlay} {
set bus_node "amba"
} else {
set bus_node "amba_pl"
}
set dts_file [current_dt_tree]
set ipmem_len [llength $ip_mem_handles]
if {$ipmem_len > 1} {
set base_addr [string tolower [get_property BASE_VALUE [lindex $ip_mem_handles $core]]]
regsub -all {^0x} $base_addr {} base_addr
append new_label $drv_handle "_" $core
append clk_label $drv_handle "_" $core
set eth_node [add_or_get_dt_node -n "ethernet" -l "$new_label" -u $base_addr -d $dts_file -p $bus_node]
set base [string tolower [get_property BASE_VALUE [lindex $ip_mem_handles $core]]]
set high [string tolower [get_property HIGH_VALUE [lindex $ip_mem_handles $core]]]
set reg [generate_reg_property $base $high]
hsi::utils::add_new_dts_param "${eth_node}" "reg" $reg inthexlist
}
}
if {(($hasbuf == "true") || ($hasbuf == "")) && ($ip_name != "axi_10g_ethernet") && ($ip_name != "ten_gig_eth_mac") && ($ip_name != "xxv_ethernet") && ($ip_name != "usxgmii") && ($ip_name != "ethernet_1_10_25g")} {
foreach n "AXI_STR_RXD m_axis_rxd" {
set intf [get_intf_pins -of_objects $eth_ip ${n}]
if {[string_is_empty ${intf}] != 1} {
break
}
}
if { [llength $intf] } {
set intf_net [get_intf_nets -of_objects $intf ]
if { [llength $intf_net] } {
set target_intf [::hsi::utils::get_other_intf_pin $intf_net $intf]
if { [llength $target_intf] } {
set connected_ip [get_connectedip $intf]
if {[llength $connected_ip]} {
set_property axistream-connected "$connected_ip" $drv_handle
set_property axistream-control-connected "$connected_ip" $drv_handle
set ip_prop CONFIG.c_include_mm2s_dre
add_cross_property $connected_ip $ip_prop $drv_handle "xlnx,include-dre" boolean
} else {
dtg_warning "$drv_handle connected ip is NULL for the interface $intf"
}
set ip_prop CONFIG.Enable_1588
add_cross_property $eth_ip $ip_prop $drv_handle "xlnx,eth-hasptp" boolean
}
}
}
foreach n "AXI_STR_RXD m_axis_tx_ts" {
set intf [get_intf_pins -of_objects $eth_ip ${n}]
if {[string_is_empty ${intf}] != 1} {
break
}
}
if {[string_is_empty ${intf}] != 1} {
set tx_tsip [get_connectedip $intf]
set_drv_prop $drv_handle axififo-connected "$tx_tsip" reference
}
} else {
foreach n "AXI_STR_RXD m_axis_rx" {
set intf [get_intf_pins -of_objects $eth_ip ${n}]
if {[string_is_empty ${intf}] != 1} {
break
}
}
if {($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g") || ($ip_name == "usxgmii")} {
foreach n "AXI_STR_RXD axis_rx_0" {
set intf [get_intf_pins -of_objects $eth_ip ${n}]
if {[string_is_empty ${intf}] != 1} {
break
}
}
}
if { [llength $intf] } {
set connected_ip [get_connectedip $intf]
}
foreach n "AXI_STR_RXD m_axis_tx_ts" {
set intf [get_intf_pins -of_objects $eth_ip ${n}]
if {[string_is_empty ${intf}] != 1} {
break
}
}
if {[string_is_empty ${intf}] != 1} {
set tx_tsip [get_connectedip $intf]
if {[llength $tx_tsip]} {
set_drv_prop $drv_handle axififo-connected "$tx_tsip" reference
}
} else {
set port_pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $eth_ip] "tx_ptp_tag_field_in_0"]]
if {[llength $port_pins]} {
set periph [::hsi::get_cells -of_objects $port_pins]
if {[llength $periph]} {
if {[string match -nocase [get_property IP_NAME $periph] "xlslice"]} {
set intf "Din"
set in1_pin [::hsi::get_pins -of_objects $periph -filter "NAME==$intf"]
set sink_pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $periph] $in1_pin]]
if {[llength $sink_pins]} {
set per [::hsi::get_cells -of_objects $sink_pins]
if {[llength $per] && [string match -nocase [get_property IP_NAME $per] "axis_clock_converter"]} {
set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $per] "s_axis_tdata"]]
if {[llength $pins]} {
set txfifo [get_cells -of_objects $pins]
if {[llength $txfifo]} {
set_drv_prop $drv_handle axififo-connected "$txfifo" reference
}
}
}
}
}
}
}
}
set rxfifo_port_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $eth_ip] "rx_ptp_tstamp_out_0"]]
if {[llength $rxfifo_port_pins]} {
set periph [::hsi::get_cells -of_objects $rxfifo_port_pins]
if {[llength $periph]} {
if {[string match -nocase [get_property IP_NAME $periph] "xlconcat"]} {
set intf "dout"
set in1_pin [::hsi::get_pins -of_objects $periph -filter "NAME==$intf"]
set sink_pins [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $periph] $in1_pin]]
if {[llength $sink_pins]} {
set per [::hsi::get_cells -of_objects $sink_pins]
if {[llength $per] && [string match -nocase [get_property IP_NAME $per] "axis_dwidth_converter"]} {
set con_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $per] "M_AXIS"]
if {[llength $con_ip]} {
if {[string match -nocase [get_property IP_NAME $con_ip] "axis_clock_converter"]} {
set rxtsfifo_ip [hsi::utils::get_connected_stream_ip [get_cells -hier $con_ip] "M_AXIS"]
if {[llength $rxtsfifo_ip]} {
set_drv_prop $drv_handle xlnx,rxtsfifo "$rxtsfifo_ip" reference
}
}
}
}
}
}
}
}
if {![string_is_empty $connected_ip]} {
set_property axistream-connected "$connected_ip" $drv_handle
set_property axistream-control-connected "$connected_ip" $drv_handle
set ip_prop CONFIG.c_include_mm2s_dre
add_cross_property $connected_ip $ip_prop $drv_handle "xlnx,include-dre" boolean
}
set_property xlnx,rxmem "$rxethmem" $drv_handle
if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core != 0)} {
set intf [get_intf_pins -of_objects $eth_ip "axis_rx_${core}"]
if {[llength $intf] && [llength $eth_node]} {
set connected_ip [get_connectedip $intf]
if {![string_is_empty $connected_ip]} {
hsi::utils::add_new_dts_param $eth_node "axistream-connected" "$connected_ip" reference
hsi::utils::add_new_dts_param $eth_node "axistream-control-connected" "$connected_ip" reference
}
hsi::utils::add_new_dts_param $eth_node "xlnx,include-dre" "" boolean
hsi::utils::add_new_dts_param $eth_node "xlnx,rxmem" "$rxethmem" hex
}
}
}
if {$ip_name == "axi_ethernet"} {
set txcsum [get_property CONFIG.TXCSUM $eth_ip]
set txcsum [get_checksum $txcsum]
set rxcsum [get_property CONFIG.RXCSUM $eth_ip]
set rxcsum [get_checksum $rxcsum]
set phytype [get_property CONFIG.PHY_TYPE $eth_ip]
set phytype [get_phytype $phytype]
set phyaddr [get_property CONFIG.PHYADDR $eth_ip]
set phyaddr [::hsi::utils::convert_binary_to_decimal $phyaddr]
set rxmem [get_property CONFIG.RXMEM $eth_ip]
set rxmem [get_memrange $rxmem]
set_property xlnx,txcsum "$txcsum" $drv_handle
set_property xlnx,rxcsum "$rxcsum" $drv_handle
set_property xlnx,phyaddr "$phyaddr" $drv_handle
set_property xlnx,rxmem "$rxmem" $drv_handle
}
set is_nobuf 0
if {$ip_name == "axi_ethernet"} {
set avail_param [list_property [get_cells -hier $drv_handle]]
if {[lsearch -nocase $avail_param "CONFIG.speed_1_2p5"] >= 0} {
if {[get_property CONFIG.speed_1_2p5 [get_cells -hier $drv_handle]] == "2p5G"} {
set is_nobuf 1
set_property compatible "xlnx,axi-2_5-gig-ethernet-1.0" $drv_handle
}
}
}
if { $hasbuf == "false" && $is_nobuf == 0} {
set ip_prop CONFIG.processor_mode
add_cross_property $eth_ip $ip_prop $drv_handle "xlnx,eth-hasnobuf" boolean
}
#adding clock frequency
set clk [get_pins -of_objects $eth_ip "S_AXI_ACLK"]
if {[llength $clk] } {
set freq [get_property CLK_FREQ $clk]
set_property clock-frequency "$freq" $drv_handle
if {$ip_name == "xxv_ethernet" && [llength $eth_node]} {
hsi::utils::add_new_dts_param $eth_node "clock-frequency" "$freq" int
}
}
# node must be created before child node
set node [gen_peripheral_nodes $drv_handle]
if {$ip_name == "axi_ethernet"} {
set hier_params [gen_hierip_params $drv_handle]
}
set mdio_node [gen_mdio_node $drv_handle $node]
set phytype [string tolower [get_property CONFIG.PHY_TYPE $eth_ip]]
if {$phytype == "rgmii" && $board_name == "kc705"} {
set phytype "rgmii-rxid"
} elseif {$phytype == "1000basex"} {
set phytype "1000base-x"
}
set_property phy-mode "$phytype" $drv_handle
if {$phytype == "sgmii" || $phytype == "1000base-x"} {
set_property phy-mode "$phytype" $drv_handle
set phynode [pcspma_phy_node $eth_ip]
set phya [lindex $phynode 0]
if { $phya != "-1"} {
set phy_name "[lindex $phynode 1]"
set_drv_prop $drv_handle pcs-handle "$drv_handle$phy_name" reference
gen_phy_node $mdio_node $phy_name $phya $drv_handle
if {[llength $node]} {
hsi::utils::add_new_dts_param $node "managed" "in-band-status" string
hsi::utils::add_new_dts_param $node "xlnx,switch-x-sgmii" "" boolean
}
}
}
if {$ip_name == "xxv_ethernet" && $core != 0 && [llength $eth_node]} {
append new_label "_" mdio
set mdionode [add_or_get_dt_node -l "$new_label" -n mdio -p $eth_node]
hsi::utils::add_new_dts_param "${mdionode}" "#address-cells" 1 int ""
hsi::utils::add_new_dts_param "${mdionode}" "#size-cells" 0 int ""
set new_label ""
}
if {$ip_name == "axi_10g_ethernet"} {
set phytype [string tolower [get_property CONFIG.base_kr $eth_ip]]
set_property phy-mode "$phytype" $drv_handle
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,ten-gig-eth-mac"]
set_property compatible "$compatible" $drv_handle
}
if {$ip_name == "xxv_ethernet"} {
set phytype [string tolower [get_property CONFIG.BASE_R_KR $eth_ip]]
set linerate [get_property CONFIG.LINE_RATE $eth_ip]
set_property phy-mode "${linerate}g${phytype}" $drv_handle
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,xxv-ethernet-1.0"]
set_property compatible "$compatible" $drv_handle
set_property "managed" "in-band-status" $drv_handle
if { $core!= 0 && [llength $eth_node]} {
hsi::utils::add_new_dts_param $eth_node "compatible" $compatible stringlist
hsi::utils::add_new_dts_param $eth_node "phy-mode" "${linerate}g${phytype}" string
hsi::utils::add_new_dts_param $eth_node "managed" "in-band-status" string
}
}
if {$ip_name == "usxgmii"} {
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,xxv-usxgmii-ethernet-1.0"]
set_property compatible $compatible $drv_handle
# phy-mode is usxgmii in this case ip_name also same
set_property phy-mode "$ip_name" $drv_handle
hsi::utils::add_new_dts_param $node "xlnx,usxgmii-rate" 1000 int
}
set ips [get_cells -hier $drv_handle]
foreach ip [get_drivers] {
if {[string compare -nocase $ip $connected_ip] == 0} {
set target_handle $ip
}
}
set hsi_version [get_hsi_version]
set ver [split $hsi_version "."]
set version [lindex $ver 0]
if {![string_is_empty $connected_ip]} {
set connected_ipname [get_property IP_NAME $connected_ip]
if {$connected_ipname == "axi_mcdma" || $connected_ipname == "axi_dma"} {
set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]
set num_queues [get_property CONFIG.c_num_mm2s_channels $connected_ip]
set inhex [format %x $num_queues]
set numqueues "/bits/ 16 <0x$inhex>"
hsi::utils::add_new_dts_param $node "xlnx,num-queues" $numqueues noformating
if {$version < 2018} {
dtg_warning "quotes to be removed or use 2018.1 version for $node param xlnx,num-queues"
}
set id 1
for {set i 2} {$i <= $num_queues} {incr i} {
set i [format "%x" $i]
append id "\""
append id ",\"" $i
set i [expr 0x$i]
}
set_drv_prop $drv_handle "xlnx,channel-ids" $id stringlist
if {$ip_name == "xxv_ethernet" && $core!= 0 && [llength $eth_node]} {
hsi::utils::add_new_dts_param $eth_node "xlnx,num-queues" $numqueues noformating
hsi::utils::add_new_dts_param $eth_node "xlnx,channel-ids" $id stringlist
}
set intr_val [get_property CONFIG.interrupts $target_handle]
set intr_parent [get_property CONFIG.interrupt-parent $target_handle]
set int_names [get_property CONFIG.interrupt-names $target_handle]
if { $hasbuf == "true" && $ip_name == "axi_ethernet"} {
set intr_val1 [get_property CONFIG.interrupts $drv_handle]
lappend intr_val1 $intr_val
set intr_name [get_property CONFIG.interrupt-names $drv_handle]
append intr_names " " $intr_name " " $int_names
if {![string match -nocase $proctype "microblaze"]} {
set null ""
set_property "interrupt-names" $null $drv_handle
set_property "interrupts" $null $drv_handle
}
} else {
set intr_names $int_names
}
if {![string_is_empty $intr_parent]} {
if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core!= 0) && [llength $eth_node]} {
hsi::utils::add_new_dts_param "${eth_node}" "interrupts" $intr_val int
hsi::utils::add_new_dts_param "${eth_node}" "interrupt-parent" $intr_parent reference
hsi::utils::add_new_dts_param "${eth_node}" "interrupt-names" $intr_names stringlist
} else {
if { $hasbuf == "true" && $ip_name == "axi_ethernet"} {
regsub -all "\{||\t" $intr_val1 {} intr_val1
regsub -all "\}||\t" $intr_val1 {} intr_val1
if {![string match -nocase $proctype "microblaze"]} {
set_property "interrupts" $intr_val1 $drv_handle
set_property "interrupt-names" $intr_names $drv_handle
}
hsi::utils::add_new_dts_param "${node}" "interrupts" $intr_val1 int
} else {
hsi::utils::add_new_dts_param "${node}" "interrupts" $intr_val int
}
hsi::utils::add_new_dts_param "${node}" "interrupt-parent" $intr_parent reference
hsi::utils::add_new_dts_param "${node}" "interrupt-names" $intr_names stringlist
}
}
}
if {$connected_ipname == "axi_dma" || $connected_ipname == "axi_mcdma"} {
set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]
if {![string match -nocase $proctype "microblaze"]} {
set eth_clk_names [get_property CONFIG.clock-names $drv_handle]
set eth_clks [get_property CONFIG.clocks $drv_handle]
if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core == 0)} {
set_property "zclocks" $eth_clks $drv_handle
set_drv_prop $drv_handle "zclock-names" $eth_clk_names stringlist
}
if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core != 0)} {
set eth_clks [get_property CONFIG.zclocks $drv_handle]
set eth_clk_names [get_property CONFIG.zclock-names $drv_handle]
}
set eth_clkname_len [llength $eth_clk_names]
set i 0
set dclk ""
while {$i < $eth_clkname_len} {
set clkname [lindex $eth_clk_names $i]
for {set corenum 0} {$corenum < $num_cores} {incr corenum} {
if {[string match -nocase $clkname "rx_core_clk_$corenum"]} {
set core_clk_$corenum "rx_core_clk"
set index_$corenum $i
}
if {[string match -nocase $clkname "s_axi_aclk_$corenum"]} {
set axi_aclk_$corenum "s_axi_aclk"
set axi_index_$corenum $i
}
if {[string match -nocase $clkname "dclk"]} {
set dclk "dclk"
set dclk_index $i
}
}
incr i
}
set eth_clk_len [expr {[llength [split $eth_clks ","]]}]
set clk_list [split $eth_clks ","]
set clk_names [get_property CONFIG.clock-names $target_handle]
set clks [get_property CONFIG.clocks $target_handle]
append names "$eth_clk_names" "$clk_names"
set names ""
append clk "$eth_clks>," "<&$clks"
set null ""
set_property "clock-names" $null $drv_handle
set_property "clocks" $null $drv_handle
if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core== 0)} {
if {[llength $dclk]} {
lappend clknames "$core_clk_0" "$dclk" "$axi_aclk_0"
} else {
lappend clknames "$core_clk_0" "$axi_aclk_0"
}
append clknames1 "$clknames" "$clk_names"
set index0 [lindex $clk_list $axi_index_0]
regsub -all "\>||\t" $index0 {} index0
set ini0 [lindex $clk_list $index_0]
regsub -all " " $ini0 "" ini0
regsub -all "\<&||\t" $ini0 {} ini0
if {[llength $dclk]} {
set dclk_ini [lindex $clk_list $dclk_index]
set dclk_ini [string trim $dclk_ini]
if {![string match -nocase "<&*" "$dclk_ini"]} {
set dclk_ini "<&$dclk_ini"
}
append clkvals "$ini0, $dclk_ini, $index0>, <&$clks"
} else {
append clkvals "$ini0, $index0>, <&$clks"
}
set_property "clocks" $clkvals $drv_handle
set_property "clock-names" $clknames1 $drv_handle
set clknames1 ""
}
if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core == 1) && [llength $eth_node]} {
if {[llength $dclk]} {
lappend clknames1 "$core_clk_1" "$dclk" "$axi_aclk_1"
} else {
lappend clknames1 "$core_clk_1" "$axi_aclk_1"
}
append clk_names1 "$clknames1" "$clk_names"
set index1 [lindex $clk_list $axi_index_1]
regsub -all "\>||\t" $index1 {} index1
set ini1 [lindex $clk_list $index_1]
regsub -all " " $ini1 "" ini1
regsub -all "\<&||\t" $ini1 {} ini1
if {[llength $dclk]} {
set dclk_ini1 [lindex $clk_list $dclk_index]
set dclk_ini1 [string trim $dclk_ini1]
if {![string match -nocase "<&*" "$dclk_ini1"]} {
set dclk_ini1 "<&$dclk_ini1"
}
append clkvals1 "$ini1, $dclk_ini1, $index1>, <&$clks"
} else {
append clkvals1 "$ini1, $index1>, <&$clks"
}
hsi::utils::add_new_dts_param "${eth_node}" "clocks" $clkvals1 reference
hsi::utils::add_new_dts_param "${eth_node}" "clock-names" $clk_names1 stringlist
set clk_names1 ""
set clkvals1 ""
}
if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core == 2) && [llength $eth_node]} {
if {[llength $dclk]} {
lappend clknames2 "$core_clk_2" "$dclk" "$axi_aclk_2"
} else {
lappend clknames2 "$core_clk_2" "$axi_aclk_2"
}
append clk_names2 "$clknames2" "$clk_names"
set index2 [lindex $clk_list $axi_index_2]
regsub -all "\>||\t" $index2 {} index2
set ini2 [lindex $clk_list $index_2]
regsub -all " " $ini2 "" ini2
regsub -all "\<&||\t" $ini2 {} ini2
if {[llength $dclk]} {
set dclk_ini2 [lindex $clk_list $dclk_index]
set dclk_ini2 [string trim $dclk_ini2]
if {![string match -nocase "<&*" "$dclk_ini2"]} {
set dclk_ini2 "<&$dclk_ini2"
}
append clkvals2 "$ini2, $dclk_ini2, $index2>, <&$clks"
} else {
append clkvals2 "$ini2, $index2>, <&$clks"
}
append clk_label2 $drv_handle "_" $core
hsi::utils::add_new_dts_param "${eth_node}" "clocks" $clkvals2 reference
hsi::utils::add_new_dts_param "${eth_node}" "clock-names" $clk_names2 stringlist
set clk_names2 ""
set clkvals2 ""
}
if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core == 3) && [llength $eth_node]} {
if {[llength $dclk]} {
lappend clknames3 "$core_clk_3" "$dclk" "$axi_aclk_3"
} else {
lappend clknames3 "$core_clk_3" "$axi_aclk_3"
}
append clk_names3 "$clknames3" "$clk_names"
set index3 [lindex $clk_list $axi_index_3]
regsub -all "\>||\t" $index3 {} index3
set ini [lindex $clk_list $index_3]
regsub -all " " $ini "" ini
regsub -all "\<&||\t" $ini {} ini
if {[llength $dclk]} {
set dclk_ini3 [lindex $clk_list $dclk_index]
set dclk_ini3 [string trim $dclk_ini3]
if {![string match -nocase "<&*" "$dclk_ini3"]} {
set dclk_ini3 "<&$dclk_ini3"
}
append clkvals3 "$ini, $dclk_ini3, $index3>, <&$clks"
} else {
append clkvals3 "$ini, $index3>, <&$clks"
}
append clk_label3 $drv_handle "_" $core
hsi::utils::add_new_dts_param "${eth_node}" "clocks" $clkvals3 reference
hsi::utils::add_new_dts_param "${eth_node}" "clock-names" $clk_names3 stringlist
set clk_names3 ""
set clkvals3 ""
}
}
}
}
if {(($ip_name == "xxv_ethernet") || ($ip_name == "ethernet_1_10_25g")) && ($core!= 0) && [llength $eth_node]} {
gen_drv_prop_eth_ip $drv_handle $eth_node
}
gen_dev_ccf_binding $drv_handle "s_axi_aclk"
}
set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]
if {![string match -nocase $proctype "microblaze"]} {
set null "NULL"
set_property "zclock-names" $null $drv_handle
set_property "zclocks" "$null" $drv_handle
}
}
proc pcspma_phy_node {slave} {
set phyaddr [get_property CONFIG.PHYADDR $slave]
set phyaddr [::hsi::utils::convert_binary_to_decimal $phyaddr]
set phymode "phy$phyaddr"
return "$phyaddr $phymode"
}
proc get_checksum {value} {
if {[string compare -nocase $value "None"] == 0} {
set value 0
} elseif {[string compare -nocase $value "Partial"] == 0} {
set value 1
} else {
set value 2
}
return $value
}
proc get_memrange {value} {
set values [split $value "k"]
lassign $values value1 value2
return [expr $value1 * 1024]
}
proc get_phytype {value} {
if {[string compare -nocase $value "MII"] == 0} {
set value 0
} elseif {[string compare -nocase $value "GMII"] == 0} {
set value 1
} elseif {[string compare -nocase $value "RGMII"] == 0} {
set value 3
} elseif {[string compare -nocase $value "SGMII"] == 0} {
set value 4
} else {
set value 5
}
return $value
}
proc gen_hierip_params {drv_handle} {
set prop_name_list [deault_parameters $drv_handle]
foreach prop_name ${prop_name_list} {
ip2drv_prop $drv_handle $prop_name
}
}
proc deault_parameters {ip_handle {dont_generate ""}} {
set par_handles [get_ip_conf_prop_list $ip_handle "CONFIG.*"]
set valid_prop_names {}
foreach par $par_handles {
regsub -all {CONFIG.} $par {} tmp_par
# Ignore some parameters that are always handled specially
switch -glob $tmp_par {
$dont_generate - \
"Component_Name" - \
"DIFFCLK_BOARD_INTERFACE" - \
"EDK_IPTYPE" - \
"ETHERNET_BOARD_INTERFACE" - \
"Include_IO" - \
"PHY_TYPE" - \
"RXCSUM" - \
"TXCSUM" - \
"TXMEM" - \
"RXMEM" - \
"PHYADDR" - \
"C_BASEADDR" - \
"C_HIGHADDR" - \
"processor_mode" - \
"ENABLE_AVB" - \
"ENABLE_LVDS" - \
"Enable_1588_1step" - \
"Enable_1588" - \
"speed_1_2p5" - \
"lvdsclkrate" - \
"gtrefclkrate" - \
"drpclkrate" - \
"Enable_Pfc" - \
"Frame_Filter" - \
"MCAST_EXTEND" - \
"MDIO_BOARD_INTERFACE" - \
"Number_of_Table_Entries" - \
"PHYRST_BOARD_INTERFACE" - \
"RXVLAN_STRP" - \
"RXVLAN_TAG" - \
"RXVLAN_TRAN" - \
"TXVLAN_STRP" - \
"TXVLAN_TAG" - \
"TXVLAN_TRAN" - \
"SIMULATION_MODE" - \
"Statistics_Counters" - \
"Statistics_Reset" - \
"Statistics_Width" - \
"SupportLevel" - \
"TIMER_CLK_PERIOD" - \
"Timer_Format" - \
"SupportLevel" - \
"TransceiverControl" - \
"USE_BOARD_FLOW" - \
"HW_VER" { } \
default {
lappend valid_prop_names $par
}
}
}
return $valid_prop_names
}
proc gen_phy_node args {
set mdio_node [lindex $args 0]
set phy_name [lindex $args 1]
set phya [lindex $args 2]
set drv [lindex $args 3]
set phy_node [add_or_get_dt_node -l $drv$phy_name -n phy -u $phya -p $mdio_node]
hsi::utils::add_new_dts_param "${phy_node}" "reg" $phya int
hsi::utils::add_new_dts_param "${phy_node}" "device_type" "ethernet-phy" string
return $phy_node
}
proc is_ethsupported_target {connected_ip} {
set connected_ipname [get_property IP_NAME $connected_ip]
if {$connected_ipname == "axi_dma" || $connected_ipname == "axi_fifo_mm_s" || $connected_ipname == "axi_mcdma"} {
return "true"
} else {
return "false"
}
}
proc get_targetip {ip} {
global ddrv_handle
if {[string_is_empty $ip] != 0} {
return
}
set p2p_busifs_i [get_intf_pins -of_objects $ip -filter "TYPE==INITIATOR || TYPE==MASTER"]
set target_periph ""
foreach p2p_busif $p2p_busifs_i {
set busif_name [string toupper [get_property NAME $p2p_busif]]
set conn_busif_handle [::hsi::utils::get_connected_intf $ip $busif_name]
if {[string_is_empty $conn_busif_handle] != 0} {
continue
}
set target_periph [get_cells -of_objects $conn_busif_handle]
set cell_name [get_cells -hier $target_periph]
set target_name [get_property IP_NAME [get_cells -hier $target_periph]]
if {$target_name == "axis_data_fifo" || $target_name == "Ethernet_filter"} {
#set target_periph [get_cells -of_objects $conn_busif_handle]
set master_slaves [get_intf_pins -of [get_cells -hier $cell_name]]
if {[llength $master_slaves] == 0} {
return
}
set master_intf ""
foreach periph_intf $master_slaves {
set prop [get_property TYPE $periph_intf]
if {$prop == "INITIATOR"} {
set master_intf $periph_intf
}
}
if {[llength $master_intf] == 0} {
return
}
set intf [get_intf_pins -of_objects $cell_name $master_intf]
set intf_net [get_intf_nets -of_objects $intf]
set intf_pins [::hsi::utils::get_other_intf_pin $intf_net $intf]
foreach intf $intf_pins {
set target_intf [get_intf_pins -of_objects $intf_net -filter "TYPE==TARGET" $intf]
if {[llength $target_intf]} {
set connected_ip [get_cells -of_objects $target_intf]
if {[llength $connected_ip]} {
set cell [get_cells -hier $connected_ip]
set target_name [get_property IP_NAME [get_cells -hier $cell]]
if {$target_name == "axis_data_fifo"} {
return [get_targetip $connected_ip]
}
if {![string_is_empty $connected_ip] && [is_ethsupported_target $connected_ip] == "true"} {
return $connected_ip
}
} else {
dtg_warning "$ddrv_handle connected ip is NULL for the target intf $target_intf"
}
} else {
dtg_warning "$ddrv_handle target interface is NULL for the intf pin $intf"
}
}
}
}
return $target_periph
}
proc get_connectedip {intf} {
global rxethmem
if { [llength $intf]} {
set connected_ip ""
set intf_net [get_intf_nets -of_objects $intf ]
if { [llength $intf_net] } {
set target_intf [::hsi::utils::get_other_intf_pin $intf_net $intf]
if { [llength $target_intf] } {
set connected_ip [get_cells -of_objects $target_intf]
if {[llength $connected_ip]} {
set target_ipname [get_property IP_NAME $connected_ip]
if {$target_ipname == "ila"} {
return
}
if {$target_ipname == "axis_data_fifo"} {
set fifo_width_bytes [get_property CONFIG.TDATA_NUM_BYTES $connected_ip]
if {[string_is_empty $fifo_width_bytes]} {
set fifo_width_bytes 1
}
set rxethmem [get_property CONFIG.FIFO_DEPTH $connected_ip]
# FIFO can be other than 8 bits, and we need the rxmem in bytes
set rxethmem [expr $rxethmem * $fifo_width_bytes]
} else {
# In 10G MAC case if the rx_stream interface is not connected to
# a Stream-fifo set the rxethmem value to a default jumbo MTU size
set rxethmem 9600
}
} else {
dtg_warning "$drv_handle connected_ip is NULL for the target_intf $target_intf"
}
}
if {[string_is_empty $connected_ip]} {
return ""
}
set target_ip [is_ethsupported_target $connected_ip]
if { $target_ip == "true"} {
return $connected_ip
} else {
set i 0
set retries 5
# When AXI Ethernet Configured in Non-Buf mode or In case of 10G MAC
# The Ethernet MAC won't directly got connected to fifo or dma
# We need to traverse through stream data fifo's and axi interconnects
# Inorder to find the target IP(AXI DMA or AXI FIFO)
while {$i < $retries} {
set target_ip "false"
set target_periph [get_targetip $connected_ip]
if {[string_is_empty $target_periph] == 0} {
set target_ip [is_ethsupported_target $target_periph]
}
if { $target_ip == "true"} {
return $target_periph
}
set connected_ip $target_periph
incr i
}
dtg_warning "Couldn't find a valid target_ip Please cross check hw design"
}
}
}
}
proc gen_drv_prop_eth_ip {drv_handle ipname} {
set prop_name_list [default_parameters $drv_handle]
foreach prop_name ${prop_name_list} {
ip2_prop $ipname $prop_name $drv_handle
}
}
proc ip2_prop {ip_name ip_prop_name drv_handle} {
set drv_prop_name $ip_prop_name
regsub -all {CONFIG.C_} $drv_prop_name {xlnx,} drv_prop_name
regsub -all {_} $drv_prop_name {-} drv_prop_name
set drv_prop_name [string tolower $drv_prop_name]
set value [get_property ${ip_prop_name} [get_cells -hier $drv_handle]]
if {[llength $value]} {
if {$value != "-1" && [llength $value] !=0} {
set type "hex"
if {[string equal -nocase $type "boolean"]} {
if {[expr $value < 1]} {
return 0
}
set value ""
}
if {[regexp "(int|hex).*" $type match]} {
regsub -all {"} $value "" value
}
hsi::utils::add_new_dts_param "$ip_name" "$drv_prop_name" $value $type
return 0
}
}
}
================================================
FILE: axi_gpio/data/gpio.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver gpio
OPTION supported_peripherals = (axi_gpio);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = gpio;
PARAMETER name = dev_type, default = gpio, type = string;
DTGPARAM name = dtg.ip_params, type = boolean;
DTGPARAM name = gpio-controller, type = boolean;
DTGPARAM name = compatible, default = "xlnx,xps-gpio-1.00.a", type = stringlist;
DTGPARAM name = "#gpio-cells", default = 2, type = int;
DTGPARAM name = dtg.device_type, default = gpio, type = string;
END driver
================================================
FILE: axi_gpio/data/gpio.tcl
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
# try to source the common tcl procs
# assuming the order of return is based on repo priority
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set node [gen_peripheral_nodes $drv_handle]
if {$node == 0} {
return
}
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,xps-gpio-1.00.a"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
set intr_present [get_property CONFIG.C_INTERRUPT_PRESENT [get_cells -hier $drv_handle]]
if {[string match $intr_present "1"]} {
set node [gen_peripheral_nodes $drv_handle]
if {$node != 0} {
hsi::utils::add_new_dts_param "${node}" "#interrupt-cells" 2 int ""
}
hsi::utils::add_new_property $drv_handle "interrupt-controller" boolean ""
}
set proc_type [get_sw_proc_prop IP_NAME]
switch $proc_type {
"microblaze" {
gen_dev_ccf_binding $drv_handle "s_axi_aclk"
set_drv_prop_if_empty $drv_handle "clock-names" "s_axi_aclk" stringlist
}
}
#Workaround: There is no unique way to differentiate the gt_ctrl, so hardcoding the size
#for the address 0xa4010000 to 0x40000
set ips [get_cells -hier -filter {IP_NAME == "mrmac"}]
if {[llength $ips]} {
set mem_ranges [hsi::utils::get_ip_mem_ranges [get_cells -hier $drv_handle]]
foreach mem_range $mem_ranges {
set base_addr [string tolower [get_property BASE_VALUE $mem_range]]
set high_addr [string tolower [get_property HIGH_VALUE $mem_range]]
if {[string match -nocase $base_addr "0xa4010000"]} {
set reg "0x0 0xa4010000 0x0 0x40000"
hsi::utils::add_new_dts_param "${node}" "reg" $reg inthexlist
}
}
}
}
================================================
FILE: axi_iic/data/axi_iic.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_iic
OPTION supported_peripherals = (axi_iic);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_iic;
PARAMETER name = dev_type, default = i2c, type = string;
DTGPARAM name = dtg.alias , type = reference, default = i2c;
DTGPARAM name = compatible, type = stringlist, default = "xlnx,xps-iic-2.00.a";
DTGPARAM name = "#address-cells", default = 1, type = int;
DTGPARAM name = "#size-cells", default = 0, type = int;
END driver
================================================
FILE: axi_iic/data/axi_iic.tcl
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,xps-iic-2.00.a"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]
if {[string match -nocase $proctype "microblaze"] } {
gen_dev_ccf_binding $drv_handle "s_axi_aclk"
}
}
================================================
FILE: axi_mcdma/data/axi_mcdma.mdd
================================================
#
# (C) Copyright 2019-2022 Xilinx, Inc.
# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_mcdma
OPTION supported_peripherals = (axi_mcdma);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_mcdma;
DTGPARAM name = dtg.ip_params, type = boolean;
DTGPARAM name = compatible, type = stringlist, default = "xlnx,axi-mcdma-1.00.a";
DTGPARAM name = "#dma-cells", type = int, default = 1;
END driver
================================================
FILE: axi_mcdma/data/axi_mcdma.tcl
================================================
#
# (C) Copyright 2019-2022 Xilinx, Inc.
# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
# try to source the common tcl procs
# assuming the order of return is based on repo priority
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set node [gen_peripheral_nodes $drv_handle]
if {$node == 0} {
return
}
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,axi-mcdma-1.00.a xlnx,eth-dma"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
set mcdma_ip [get_cells -hier $drv_handle]
set dma_count [hsi::utils::get_os_parameter_value "dma_count"]
if { [llength $dma_count] == 0 } {
set dma_count 0
}
set axiethernetfound 0
set connected_ip [hsi::utils::get_connected_stream_ip $mcdma_ip "M_AXIS_MM2S"]
if { [llength $connected_ip] } {
set connected_ip_type [get_property IP_NAME $connected_ip]
if { [string match -nocase $connected_ip_type axi_ethernet ] || [string match -nocase $connected_ip_type axi_ethernet_buffer ] } {
set axiethernetfound 1
}
} else {
dtg_warning "$drv_handle connected ip is NULL for the pin M_AXIS_MM2S"
}
set is_xxv [get_connected_ip $drv_handle "M_AXIS_MM2S"]
set is_mrmac [is_mrmac_connected $drv_handle "M_AXIS_MM2S"]
# if tsn ip exists in the design then it is through mcdma so changing the compatible string
set tsn_inst_name [get_cells -filter {IP_NAME =~ "*tsn*"}]
if { $axiethernetfound || $is_xxv == 1 || $is_mrmac == 1 || [llength $tsn_inst_name] } {
set compatstring "xlnx,eth-dma"
set_property compatible "$compatstring" $drv_handle
}
if { $axiethernetfound != 1 && $is_xxv != 1 && $is_mrmac != 1} {
set ip_prop CONFIG.c_include_mm2s_dre
add_cross_property $drv_handle $ip_prop $drv_handle "xlnx,include-dre" boolean
set_drv_conf_prop $drv_handle c_addr_width xlnx,addrwidth
set baseaddr [get_baseaddr $mcdma_ip no_prefix]
set tx_chan [hsi::utils::get_ip_param_value $mcdma_ip C_INCLUDE_MM2S]
if { $tx_chan == 1 } {
set tx_chan_node [add_dma_channel $drv_handle $node "axi-dma" $baseaddr "MM2S" $dma_count ]
set num_mm2s_channles [get_property CONFIG.c_num_mm2s_channels [get_cells -hier $drv_handle]]
set intr_info [get_interrupt_info $drv_handle "MM2S"]
if { [llength $intr_info] && ![string match -nocase $intr_info "-1"] } {
hsi::utils::add_new_dts_param $tx_chan_node "interrupts" $intr_info intlist
} else {
dtg_warning "ERROR: ${drv_handle}: mm2s_introut port is not connected"
}
set intr_parent [get_property CONFIG.interrupt-parent $drv_handle]
if {[llength $intr_parent]} {
hsi::utils::add_new_dts_param "${tx_chan_node}" "interrupt-parent" $intr_parent reference
}
add_dma_coherent_prop $drv_handle "M_AXI_MM2S"
}
set rx_chan [hsi::utils::get_ip_param_value $mcdma_ip C_INCLUDE_S2MM]
if { $rx_chan ==1 } {
set rx_bassaddr [format %08x [expr 0x$baseaddr + 0x30]]
set rx_chan_node [add_dma_channel $drv_handle $node "axi-dma" $rx_bassaddr "S2MM" $dma_count]
set intr_info [get_interrupt_info $drv_handle "S2MM"]
if { [llength $intr_info] && ![string match -nocase $intr_info "-1"] } {
hsi::utils::add_new_dts_param $rx_chan_node "interrupts" $intr_info intlist
} else {
dtg_warning "ERROR: ${drv_handle}: s2mm_introut port is not connected"
}
set intr_parent [get_property CONFIG.interrupt-parent $drv_handle]
if {[llength $intr_parent]} {
hsi::utils::add_new_dts_param "${rx_chan_node}" "interrupt-parent" $intr_parent reference
}
add_dma_coherent_prop $drv_handle "M_AXI_S2MM"
}
} else {
set ip_prop CONFIG.c_include_mm2s_dre
add_cross_property $drv_handle $ip_prop $drv_handle "xlnx,include-dre" boolean
set addr_width [get_property CONFIG.c_addr_width $mcdma_ip]
set inhex [format %x $addr_width]
append addrwidth "/bits/ 8 <0x$inhex>"
hsi::utils::add_new_dts_param "$node" "xlnx,addrwidth" $addrwidth noformating
}
incr dma_count
hsi::utils::set_os_parameter_value "dma_count" $dma_count
}
proc get_interrupt_info {drv_handle chan_name} {
if {[string match -nocase $chan_name "MM2S"]} {
set num_channles [get_property CONFIG.c_num_mm2s_channels [get_cells -hier $drv_handle]]
} else {
set num_channles [get_property CONFIG.c_num_s2mm_channels [get_cells -hier $drv_handle]]
}
set intr_info ""
for {set i 1} {$i <= $num_channles} {incr i} {
set intr_pin_name [format "%s_%s_introut" [string tolower $chan_name] ch$i]
set intr1_info [get_intr_id $drv_handle $intr_pin_name]
if {[string match -nocase $intr1_info "-1"]} {
continue
}
lappend intr_info $intr1_info
}
if {[llength $intr_info]} {
regsub -all "\{||\t" $intr_info {} intr_info
regsub -all "\}||\t" $intr_info {} intr_info
return $intr_info
}
}
proc get_connected_ip {drv_handle dma_pin} {
global connected_ip
# Check whether dma is connected to 10G/25G MAC
# currently we are handling only data fifo
set intf [::hsi::get_intf_pins -of_objects [get_cells -hier $drv_handle] $dma_pin]
set valid_eth_list "xxv_ethernet axi_ethernet axi_10g_ethernet usxgmii ethernet_1_10_25g"
if {[string_is_empty ${intf}]} {
return 0
}
set connected_ip [::hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] $intf]
if {[string_is_empty ${connected_ip}]} {
dtg_warning "$drv_handle connected ip is NULL for the pin $intf"
return 0
}
set iptype [get_property IP_NAME [get_cells -hier $connected_ip]]
if {[string match -nocase $iptype "axis_data_fifo"] } {
# here dma connected to data fifo
set dma_pin "M_AXIS"
get_connected_ip $connected_ip $dma_pin
} elseif {[lsearch -nocase $valid_eth_list $iptype] >= 0 } {
# dma connected to 10G/25G MAC, 1G or 10G
return 1
} else {
# dma connected via interconnects
set dma_pin "M_AXIS"
get_connected_ip $connected_ip $dma_pin
}
}
proc is_mrmac_connected {drv_handle dma_pin} {
set intf [::hsi::get_intf_pins -of_objects [get_cells -hier $drv_handle] $dma_pin]
if {[llength $intf]} {
set connected_ip [::hsi::utils::get_connected_stream_ip [get_cells -hier $drv_handle] $intf]
if {[llength $connected_ip]} {
if {[string match -nocase [get_property IP_NAME $connected_ip] "axis_data_fifo"]} {
set mux_ip [::hsi::utils::get_connected_stream_ip [get_cells -hier $connected_ip] "M_AXIS"]
if {[llength $mux_ip]} {
if {[string match -nocase [get_property IP_NAME $mux_ip] "mrmac_10g_mux"]} {
set data_fifo_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $mux_ip] "tx_m_axis_tdata"]]
set data_fifo_per [::hsi::get_cells -of_objects $data_fifo_pin]
if {[string match -nocase [get_property IP_NAME $data_fifo_per] "axis_data_fifo"]} {
set fifo_pin [::hsi::utils::get_sink_pins [get_pins -of_objects [get_cells -hier $data_fifo_per] "m_axis_tdata"]]
set mrmac_per [::hsi::get_cells -of_objects $fifo_pin]
if {[string match -nocase [get_property IP_NAME $mrmac_per] "mrmac"]} {
return 1
}
}
}
}
}
}
}
}
proc add_dma_channel {drv_handle parent_node xdma addr mode devid} {
set modellow [string tolower $mode]
set modeIndex [string index $mode 0]
set dma_channel [add_or_get_dt_node -n "dma-channel" -u $addr -p $parent_node]
hsi::utils::add_new_dts_param $dma_channel "compatible" [format "xlnx,%s-%s-channel" $xdma $modellow] stringlist
hsi::utils::add_new_dts_param $dma_channel "xlnx,device-id" $devid hexint
add_cross_property_to_dtnode $drv_handle [format "CONFIG.C_INCLUDE_%s_DRE" $mode] $dma_channel "xlnx,include-dre" boolean
# detection based on two property
set datawidth_list "[format "CONFIG.C_%s_AXIS_%s_DATA_WIDTH" $modeIndex $mode] [format "CONFIG.C_%s_AXIS_%s_TDATA_WIDTH" $modeIndex $mode]"
add_cross_property_to_dtnode $drv_handle $datawidth_list $dma_channel "xlnx,datawidth"
if {[string match -nocase $mode "MM2S"]} {
set num_channles [get_property CONFIG.c_num_mm2s_channels [get_cells -hier $drv_handle]]
} else {
set num_channles [get_property CONFIG.c_num_s2mm_channels [get_cells -hier $drv_handle]]
}
hsi::utils::add_new_dts_param $dma_channel "dma-channels" $num_channles hexint
return $dma_channel
}
proc add_dma_coherent_prop {drv_handle intf} {
set ip_name [::hsi::get_cells -hier -filter "NAME==$drv_handle"]
set connectedip [hsi::utils::get_connected_stream_ip $drv_handle $intf]
if {[llength $connectedip] == 0} {
return
}
set intrconnect [get_property IP_NAME [get_cells -hier $connectedip]]
set num_master [get_property CONFIG.NUM_MI $connectedip]
set done 0
# check whether dma connected to interconnect ip, loop until you get the
# port name ACP or HP
while {[string match -nocase $intrconnect "axi_interconnect"]} {
# loop over number of master interfaces
set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $connectedip] -filter {TYPE==MASTER}]
if {[llength $master_intf] == 0} {
break
}
foreach interface ${master_intf} {
set intf_port [hsi::utils::get_connected_intf $connectedip $interface]
set intrconnect [hsi::utils::get_connected_stream_ip $connectedip $interface]
if {![string_is_empty $intf_port] && [string match -nocase $intf_port "S_AXI_ACP"]} {
hsi::utils::add_new_property $drv_handle "dma-coherent" boolean ""
# here dma connected to ACP port
set done 1
break;
}
if {$done} {
break
}
}
}
}
================================================
FILE: axi_pcie/data/axi_pcie.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_pcie
OPTION supported_peripherals = (axi_pcie axi_pcie3 qdma xdma pcie_dma_versal);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_pcie;
PARAMETER name = dev_type, default = axi-pcie, type = string;
DTGPARAM name = compatible, type = stringlist, default = "xlnx,axi-pcie-host-1.00.a";
DTGPARAM name = "#address-cells", default = 3, type = int;
DTGPARAM name = "#size-cells", default = 2 , type = int;
DTGPARAM name = "#interrupt-cells", default = 1 , type = int;
DTGPARAM name = device_type, type = string, default = pci;
END driver
================================================
FILE: axi_pcie/data/axi_pcie.tcl
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc set_pcie_ranges {drv_handle proctype} {
if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "qdma"] \
|| [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "xdma"]} {
set axibar_num [get_ip_property $drv_handle "CONFIG.axibar_num"]
} else {
set axibar_num [get_ip_property $drv_handle "CONFIG.AXIBAR_NUM"]
}
if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "pcie_dma_versal"]} {
set axibar_num [get_ip_property $drv_handle "CONFIG.C_AXIBAR_NUM"]
}
set range_type 0x02000000
# 64-bit high address.
set high_64bit 0x00000000
set ranges ""
for {set x 0} {$x < $axibar_num} {incr x} {
if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "qdma"] \
|| [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "xdma"] \
|| [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "axi_pcie3"] \
|| [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "pcie_dma_versal"] \
} {
set axi_baseaddr [get_ip_property $drv_handle [format "CONFIG.axibar_%d" $x]]
set pcie_baseaddr [get_ip_property $drv_handle [format "CONFIG.axibar2pciebar_%d" $x]]
set axi_highaddr [get_ip_property $drv_handle [format "CONFIG.axibar_highaddr_%d" $x]]
} else {
set axi_baseaddr [get_ip_property $drv_handle [format "CONFIG.C_AXIBAR_%d" $x]]
set pcie_baseaddr [get_ip_property $drv_handle [format "CONFIG.C_AXIBAR2PCIEBAR_%d" $x]]
set axi_highaddr [get_ip_property $drv_handle [format "CONFIG.C_AXIBAR_HIGHADDR_%d" $x]]
}
set size [expr $axi_highaddr -$axi_baseaddr + 1]
# Check the size of pci memory region is 4GB or not,if
# yes then split the size to MSB and LSB.
if {[regexp -nocase {([0-9a-f]{9})} "$size" match]} {
set size [format 0x%016x [expr $axi_highaddr -$axi_baseaddr + 1]]
set low_size [string range $size 0 9]
set high_size "0x[string range $size 10 17]"
set size "$low_size $high_size"
} else {
set size [format 0x%08x [expr $axi_highaddr - $axi_baseaddr + 1]]
set size "$high_64bit $size"
}
if {[regexp -nocase {([0-9a-f]{9})} "$axi_baseaddr" match] || [regexp -nocase {([0-9a-f]{9})} "$axi_highaddr" match]} {
set range_type 0x43000000
}
if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "qdma"] \
|| [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "xdma"] \
|| [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "pcie_dma_versal"]} {
if {[regexp -nocase {([0-9a-f]{9})} "$pcie_baseaddr" match]} {
set temp $pcie_baseaddr
set temp [string trimleft [string trimleft $temp 0] x]
set len [string length $temp]
set rem [expr {${len} - 8}]
set high_base "0x[string range $temp $rem $len]"
set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]"
set low_base [format 0x%08x $low_base]
set pcie_baseaddr "$low_base $high_base"
} else {
set pcie_baseaddr "$high_64bit $pcie_baseaddr"
}
if {[regexp -nocase {([0-9a-f]{9})} "$axi_baseaddr" match]} {
set temp $axi_baseaddr
set temp [string trimleft [string trimleft $temp 0] x]
set len [string length $temp]
set rem [expr {${len} - 8}]
set high_base "0x[string range $temp $rem $len]"
set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]"
set low_base [format 0x%08x $low_base]
set axi_baseaddr "$low_base $high_base"
} else {
if {[string match -nocase $proctype "microblaze"] } {
set axi_baseaddr "$axi_baseaddr"
} else {
set axi_baseaddr "0x0 $axi_baseaddr"
}
}
set value "<$range_type $pcie_baseaddr $axi_baseaddr $size>"
} else {
set value "<$range_type $high_64bit $pcie_baseaddr $axi_baseaddr $size>"
}
if {[string match "" $ranges]} {
set ranges $value
} else {
append ranges ", " $value
}
}
set_property CONFIG.ranges $ranges $drv_handle
}
proc get_reg_prop {highaddr baseaddr proctype} {
set reg ""
set size [format 0x%X [expr $highaddr -$baseaddr + 1]]
if {[regexp -nocase {0x([0-9a-f]{9})} "$baseaddr" match]} {
set temp $baseaddr
set temp [string trimleft [string trimleft $temp 0] x]
set len [string length $temp]
set rem [expr {${len} - 8}]
set high_base "0x[string range $temp $rem $len]"
set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]"
set low_base [format 0x%08x $low_base]
set reg "$low_base $high_base 0x0 $size"
} else {
if {[string match -nocase $proctype "microblaze"] } {
set reg "$baseaddr $size"
} else {
set reg "0x0 $baseaddr 0x0 $size"
}
}
return $reg
}
proc set_pcie_reg {drv_handle proctype} {
if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "xdma"] \
|| [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "axi_pcie3"] \
|| [string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "pcie_dma_versal"]} {
set baseaddr [get_ip_property $drv_handle CONFIG.baseaddr]
set highaddr [get_ip_property $drv_handle CONFIG.highaddr]
set reg [get_reg_prop $highaddr $baseaddr $proctype]
if {[llength $reg]} {
set_property CONFIG.reg $reg $drv_handle
}
} elseif {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "qdma"]} {
set mem_ranges [hsi::utils::get_ip_mem_ranges $drv_handle]
set reg ""
set reg_names ""
foreach mem_range $mem_ranges {
set baseaddr [string tolower [get_property BASE_VALUE $mem_range]]
set highaddr [string tolower [get_property HIGH_VALUE $mem_range]]
set slave_intf [string tolower [get_property SLAVE_INTERFACE $mem_range]]
dtg_verbose "slave_intf:$slave_intf"
set reg_prop ""
if {[string match -nocase $slave_intf "s_axi_lite"]} {
set reg_prop [get_reg_prop $highaddr $baseaddr $proctype]
append reg_names " " "cfg"
} elseif {[string match -nocase $slave_intf "s_axi_lite_csr"]} {
set reg_prop [get_reg_prop $highaddr $baseaddr $proctype]
append reg_names " " "breg"
}
if {[llength $reg_prop]} {
if {![llength $reg]} {
set reg "$reg_prop"
} else {
append reg ">, <" "$reg_prop"
}
}
}
if {[llength $reg]} {
set_property CONFIG.reg $reg $drv_handle
}
if {[llength $reg_names]} {
hsi::utils::add_new_property $drv_handle "reg-names" stringlist "$reg_names"
}
} else {
set baseaddr [get_ip_property $drv_handle CONFIG.BASEADDR]
set highaddr [get_ip_property $drv_handle CONFIG.HIGHADDR]
set size [format 0x%X [expr $highaddr -$baseaddr + 1]]
set_property CONFIG.reg "$baseaddr $size" $drv_handle
}
}
proc axibar_num_workaround {drv_handle} {
# this required to workaround 2014.2_web tag kernel
# must have both xlnx,pciebar2axibar-0 and xlnx,pciebar2axibar-1 generated
set axibar_num [get_ip_property $drv_handle "CONFIG.AXIBAR_NUM"]
if {[expr $axibar_num <= 1]} {
set axibar_num 2
}
return $axibar_num
}
proc generate {drv_handle} {
# try to source the common tcl procs
# assuming the order of return is based on repo priority
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set node [gen_peripheral_nodes $drv_handle]
if {$node == 0} {
return
}
set proctype [get_property IP_NAME [get_cells -hier [get_sw_processor]]]
set compatible [get_comp_str $drv_handle]
if {![string match -nocase $proctype "psv_cortexa72"]} {
set compatible [append compatible " " "xlnx,axi-pcie-host-1.00.a"]
}
set_drv_prop $drv_handle compatible "$compatible" stringlist
if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "xdma"]} {
hsi::utils::add_new_property $drv_handle "compatible" stringlist "xlnx,xdma-host-3.00"
set msi_rx_pin_en [get_property CONFIG.msi_rx_pin_en [get_cells -hier $drv_handle]]
if {[string match -nocase $msi_rx_pin_en "true"]} {
set intr_names "misc msi0 msi1"
set_drv_prop $drv_handle "interrupt-names" $intr_names stringlist
}
}
if {[string match -nocase [get_property IP_NAME [get_cells -hier $drv_handle]] "qdma"]} {
hsi::utils::add_new_property $drv_handle "compatible" stringlist "xlnx,qdma-host-3.00"
}
set_pcie_reg $drv_handle $proctype
set_pcie_ranges $drv_handle $proctype
set_drv_prop $drv_handle interrupt-map-mask "0 0 0 7" intlist
if {[string match -nocase $proctype "microblaze"] } {
set_drv_prop $drv_handle bus-range "0x0 0xff" hexint
}
# Add Interrupt controller child node
if {[string match -nocase $proctype "psv_cortexa72"]} {
set psv_pcieintc_cnt [get_os_dev_count "psv_pci_intc_cnt"]
set pcie_child_intc_node [add_or_get_dt_node -l "psv_pcie_intc_${psv_pcieintc_cnt}" -n interrupt-controller -p $node]
set int_map "0 0 0 1 &psv_pcie_intc_${psv_pcieintc_cnt} 1>, <0 0 0 2 &psv_pcie_intc_${psv_pcieintc_cnt} 2>, <0 0 0 3 &psv_pcie_intc_${psv_pcieintc_cnt} 3>,\
<0 0 0 4 &psv_pcie_intc_${psv_pcieintc_cnt} 4"
incr psv_pcieintc_cnt
hsi::utils::set_os_parameter_value "psv_pci_intc_cnt" $psv_pcieintc_cnt
set intr_names "misc msi0 msi1"
set_drv_prop $drv_handle "interrupt-names" $intr_names stringlist
} else {
set pcieintc_cnt [get_os_dev_count "pci_intc_cnt"]
set pcie_child_intc_node [add_or_get_dt_node -l "pcie_intc_${pcieintc_cnt}" -n interrupt-controller -p $node]
set int_map "0 0 0 1 &pcie_intc_${pcieintc_cnt} 1>, <0 0 0 2 &pcie_intc_${pcieintc_cnt} 2>, <0 0 0 3 &pcie_intc_${pcieintc_cnt} 3>,\
<0 0 0 4 &pcie_intc_${pcieintc_cnt} 4"
incr pcieintc_cnt
hsi::utils::set_os_parameter_value "pci_intc_cnt" $pcieintc_cnt
}
set_drv_prop $drv_handle interrupt-map $int_map int
hsi::utils::add_new_dts_param "${pcie_child_intc_node}" "interrupt-controller" "" boolean
hsi::utils::add_new_dts_param "${pcie_child_intc_node}" "#address-cells" 0 int
hsi::utils::add_new_dts_param "${pcie_child_intc_node}" "#interrupt-cells" 1 int
}
================================================
FILE: axi_perf_mon/data/axi_perf_mon.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_perf_mon
OPTION supported_peripherals = (axi_perf_mon);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_perf_mon;
DTGPARAM name = compatible, type = stringlist, default = "xlnx,axi-perf-monitor";
END driver
================================================
FILE: axi_perf_mon/data/axi_perf_mon.tcl
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
# try to source the common tcl procs
# assuming the order of return is based on repo priority
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,axi-perf-monitor"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
set check_list "enable-profile enable-trace num-monitor-slots enable-event-count enable-event-log have-sampled-metric-cnt num-of-counters metric-count-width metrics-sample-count-width global-count-width metric-count-scale"
foreach p ${check_list} {
set ip_conf [string toupper "c_${p}"]
regsub -all {\-} $ip_conf {_} ip_conf
set_drv_conf_prop $drv_handle ${ip_conf} xlnx,${p} hexint
}
}
================================================
FILE: axi_qspi/data/axi_qspi.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_qspi
OPTION supported_peripherals = (axi_quad_spi);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_qspi;
DTGPARAM name = compatible, type = stringlist, default = "xlnx,xps-spi-2.00.a";
DTGPARAM name = dtg.alias , default = spi;
END driver
================================================
FILE: axi_qspi/data/axi_qspi.tcl
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
# try to source the common tcl procs
# assuming the order of return is based on repo priority
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,xps-spi-2.00.a"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
set_drv_conf_prop $drv_handle "C_NUM_SS_BITS" "xlnx,num-ss-bits"
set_drv_conf_prop $drv_handle "C_NUM_SS_BITS" "num-cs"
set_drv_conf_prop $drv_handle "C_NUM_TRANSFER_BITS" "bits-per-word" int
set_drv_conf_prop $drv_handle "C_FIFO_DEPTH" "fifo-size" int
set_drv_conf_prop $drv_handle "C_SPI_MODE" "xlnx,spi-mode" int
set_drv_conf_prop $drv_handle "C_USE_STARTUP" "xlnx,startup-block" boolean
}
================================================
FILE: axi_sysace/data/axi_sysace.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_sysace
OPTION supported_peripherals = (axi_sysace);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_sysace;
DTGPARAM name = compatible, type = stringlist, default = "xlnx,xps-sysace-1.00.a";
DTGPARAM name = port-number, type = int, default = 0;
END driver
================================================
FILE: axi_sysace/data/axi_sysace.tcl
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
}
================================================
FILE: axi_tft/data/axi_tft.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_tft
OPTION supported_peripherals = (axi_tft);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_tft;
DTGPARAM name = compatible, type = stringlist, default = "xlnx,xps-tft-1.00.a";
END driver
================================================
FILE: axi_tft/data/axi_tft.tcl
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
}
================================================
FILE: axi_timebase_wdt/data/axi_timebase_wdt.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_timebase_wdt
OPTION supported_peripherals = (axi_timebase_wdt);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_timebase_wdt;
DTGPARAM name = dev_type, default = watchdog , type = string;
DTGPARAM name = compatible, type = stringlist, default = "xlnx,xps-timebase-wdt-1.00.a";
END driver
================================================
FILE: axi_timebase_wdt/data/axi_timebase_wdt.tcl
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
# try to source the common tcl procs
# assuming the order of return is based on repo priority
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,xps-timebase-wdt-1.00.a"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
# get bus clock frequency
set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "S_AXI_ACLK"]
if {![string equal $clk_freq ""]} {
set_property CONFIG.clock-frequency $clk_freq $drv_handle
}
set_drv_conf_prop $drv_handle "C_WDT_ENABLE_ONCE" "xlnx,wdt-enable-once"
set_drv_conf_prop $drv_handle "C_WDT_INTERVAL" "xlnx,wdt-interval"
}
================================================
FILE: axi_traffic_gen/data/axi_traffic_gen.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_traffic_gen
OPTION supported_peripherals = (axi_traffic_gen);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_traffic_gen;
DTGPARAM name = compatible, type = stringlist, default = "xlnx,axi-traffic-gen";
DTGPARAM name = "xlnx,device-id", type = int, default = 0;
END driver
================================================
FILE: axi_traffic_gen/data/axi_traffic_gen.tcl
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
# try to source the common tcl procs
# assuming the order of return is based on repo priority
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,axi-traffic-gen"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
# the interrupt related setting is only required for AXI4 protocol only
set atg_mode [get_property "CONFIG.C_ATG_MODE" [get_cells -hier $drv_handle]]
if { ![string match -nocase $atg_mode "AXI4"] } {
return 0
}
set proc_type [get_sw_proc_prop IP_NAME]
# set up interrupt-names
set intr_list "irq_out err_out"
set interrupts ""
set interrupt_names ""
foreach irq ${intr_list} {
set intr_info [get_intr_id $drv_handle $irq]
if { [string match -nocase $intr_info "-1"] } {
if {[string match -nocase $proc_type "psv_cortexa72"] || [string match -nocase $proc_type "psx_cortexa78"]} {
continue
} else {
error "ERROR: ${drv_handle}: $irq port is not connected"
}
}
if { [string match -nocase $interrupt_names ""] } {
if {[string match -nocase $irq "irq_out"]} {
set irq "irq-out"
}
if {[string match -nocase $irq "err_out"]} {
set irq "err-out"
}
set interrupt_names "$irq"
set interrupts "$intr_info"
} else {
if {[string match -nocase $irq "irq_out"]} {
set irq "irq-out"
}
if {[string match -nocase $irq "err_out"]} {
set irq "err-out"
}
append interrupt_names " " "$irq"
append interrupts " " "$intr_info"
}
}
hsi::utils::add_new_property $drv_handle "interrupts" int $interrupts
hsi::utils::add_new_property $drv_handle "interrupt-names" stringlist $interrupt_names
}
================================================
FILE: axi_usb2_device/data/axi_usb2_device.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_usb2_device
OPTION supported_peripherals = (axi_usb2_device);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_usb2_device;
DTGPARAM name = compatible, type = stringlist, default = "xlnx,usb2-device-4.00.a";
END driver
================================================
FILE: axi_usb2_device/data/axi_usb2_device.tcl
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,usb2-device-4.00.a"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
set ip [get_cells -hier $drv_handle]
set include_dma [get_property CONFIG.C_INCLUDE_DMA $ip]
if { $include_dma eq "1"} {
set_drv_conf_prop $drv_handle C_INCLUDE_DMA xlnx,has-builtin-dma boolean
}
}
================================================
FILE: axi_vcu/data/axi_vcu.mdd
================================================
#
# (C) Copyright 2017-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_vcu
OPTION supported_peripherals = (vcu);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_vcu;
END driver
================================================
FILE: axi_vcu/data/axi_vcu.tcl
================================================
#
# (C) Copyright 2017-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
# try to source the common tcl procs
# assuming the order of return is based on repo priority
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
# Generate properties required for vcu node
set node [gen_peripheral_nodes $drv_handle]
if {$node == 0} {
return
}
hsi::utils::add_new_dts_param "${node}" "#address-cells" 2 int
hsi::utils::add_new_dts_param "${node}" "#size-cells" 2 int
hsi::utils::add_new_dts_param "${node}" "#clock-cells" 1 int
set vcu_ip [get_cells -hier $drv_handle]
set baseaddr [get_baseaddr $vcu_ip no_prefix]
set slcr_offset 0x40000
set logicore_offset 0x41000
set vcu_slcr_reg [format %08x [expr 0x$baseaddr + $slcr_offset]]
set logicore_reg [format %08x [expr 0x$baseaddr + $logicore_offset]]
set reg "0x0 0x$vcu_slcr_reg 0x0 0x1000>, <0x0 0x$logicore_reg 0x0 0x1000"
set_drv_prop $drv_handle reg $reg int
set intr_val [get_property CONFIG.interrupts $drv_handle]
set intr_parent [get_property CONFIG.interrupt-parent $drv_handle]
set clock-names "pll_ref"
set clock-names [append clock-names " aclk"]
hsi::utils::add_new_dts_param "${node}" "clock-names" ${clock-names} stringlist
zynq_gen_pl_clk_binding $drv_handle
set first_reg_name "vcu_slcr"
set second_reg_name " logicore"
set reg_name [append first_reg_name $second_reg_name]
hsi::utils::add_new_dts_param "${node}" "reg-names" ${reg_name} stringlist
hsi::utils::add_new_dts_param "${node}" "ranges" "" boolean
set compatible [get_ipdetails $drv_handle "compatible"]
set vcu_comp " xlnx,vcu"
set compatible [append compatible $vcu_comp]
set_drv_prop $drv_handle compatible "$compatible" stringlist
hsi::utils::add_new_dts_param "${node}" "compatible" ${compatible} stringlist
# Generate child encoder
set ver [get_ipdetails $drv_handle "ver"]
set encoder_enable [get_property CONFIG.ENABLE_ENCODER [get_cells -hier $drv_handle]]
if {[string match -nocase $encoder_enable "TRUE"]} {
set encoder_node [add_or_get_dt_node -l "encoder" -n "al5e@$baseaddr" -p $node]
set encoder_comp "al,al5e-${ver}"
set encoder_comp [append encoder_comp " al,al5e"]
hsi::utils::add_new_dts_param "${encoder_node}" "compatible" $encoder_comp stringlist
set encoder_reg "0x0 0x$baseaddr 0x0 0x10000"
hsi::utils::add_new_dts_param "${encoder_node}" "reg" $encoder_reg int
hsi::utils::add_new_dts_param "${encoder_node}" "interrupts" $intr_val int
hsi::utils::add_new_dts_param "${encoder_node}" "interrupt-parent" $intr_parent reference
}
# Fenerate child decoder
set decoder_enable [get_property CONFIG.ENABLE_DECODER [get_cells -hier $drv_handle]]
if {[string match -nocase $decoder_enable "TRUE"]} {
set decoder_offset 0x20000
set decoder_reg [format %08x [expr 0x$baseaddr + $decoder_offset]]
set decoder_node [add_or_get_dt_node -l "decoder" -n "al5d@$decoder_reg" -p $node]
set decoder_comp "al,al5d-${ver}"
set decoder_comp [append decoder_comp " al,al5d"]
hsi::utils::add_new_dts_param "${decoder_node}" "compatible" $decoder_comp stringlist
set decoder_reg "0x0 0x$decoder_reg 0x0 0x10000"
hsi::utils::add_new_dts_param "${decoder_node}" "reg" $decoder_reg int
hsi::utils::add_new_dts_param "${decoder_node}" "interrupts" $intr_val int
hsi::utils::add_new_dts_param "${decoder_node}" "interrupt-parent" $intr_parent reference
}
set clknames "pll_ref aclk vcu_core_enc vcu_mcu_enc vcu_core_dec vcu_mcu_dec"
overwrite_clknames $clknames $drv_handle
set ip [get_cells -hier $drv_handle]
set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $ip] "vcu_resetn"]]
foreach pin $pins {
set sink_periph [::hsi::get_cells -of_objects $pin]
if {[llength $sink_periph]} {
set sink_ip [get_property IP_NAME $sink_periph]
if {[string match -nocase $sink_ip "xlslice"]} {
set gpio [get_property CONFIG.DIN_FROM $sink_periph]
set pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph "Din"]]]
foreach pin $pins {
set periph [::hsi::get_cells -of_objects $pin]
if {[llength $periph]} {
set ip [get_property IP_NAME $periph]
set proc_type [get_sw_proc_prop IP_NAME]
if {[string match -nocase $proc_type "psv_cortexa72"] } {
if { $ip in { "versal_cips" "ps_wizard" }} {
# As in versal there is only bank0 for MIOs
set gpio [expr $gpio + 26]
hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio0 $gpio 0" reference
break
}
}
if {[string match -nocase $proc_type "psu_cortexa53"] } {
if {[string match -nocase $ip "zynq_ultra_ps_e"]} {
set gpio [expr $gpio + 78]
hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio $gpio 0" reference
break
}
}
if {[string match -nocase $ip "axi_gpio"]} {
hsi::utils::add_new_dts_param "$node" "reset-gpios" "$periph $gpio 0 1" reference
}
} else {
dtg_warning "periph for the pin:$pin is NULL $periph...check the design"
}
}
}
} else {
dtg_warning "peripheral for the pin:$pin is NULL $sink_periph...check the design"
}
}
}
proc get_ipdetails {drv_handle arg} {
set slave [get_cells -hier ${drv_handle}]
set vlnv [split [get_property VLNV $slave] ":"]
set ver [lindex $vlnv 3]
set name [lindex $vlnv 2]
set ver [lindex $vlnv 3]
set comp_prop "xlnx,${name}-${ver}"
regsub -all {_} $comp_prop {-} comp_prop
if {[string match -nocase $arg "ver"]} {
return $ver
} else {
return $comp_prop
}
}
================================================
FILE: axi_vdma/data/axi_vdma.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_vdma
OPTION supported_peripherals = (axi_vdma);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_vdma;
PARAMETER name = dev_type, default = dma, type = string;
DTGPARAM name = compatible, type = stringlist, default = "xlnx,axi-vdma-1.00.a";
DTGPARAM name = "#dma-cells", type = int, default = 1;
END driver
================================================
FILE: axi_vdma/data/axi_vdma.tcl
================================================
#
# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
# Based on original code:
# (C) Copyright 2007-2014 Michal Simek
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Michal SIMEK <monstr@monstr.eu>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
# try to source the common tcl procs
# assuming the order of return is based on repo priority
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set node [gen_peripheral_nodes $drv_handle]
if {$node == 0} {
return
}
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,axi-vdma-1.00.a"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
set dma_ip [get_cells -hier $drv_handle]
set vdma_count [hsi::utils::get_os_parameter_value "vdma_count"]
if { [llength $vdma_count] == 0 } {
set vdma_count 0
}
# check for C_ENABLE_DEBUG parameters
# C_ENABLE_DEBUG_INFO_15 - Enable S2MM Frame Count Interrupt bit
# C_ENABLE_DEBUG_INFO_14 - Enable S2MM Delay Counter Interrupt bit
# C_ENABLE_DEBUG_INFO_7 - Enable MM2S Frame Count Interrupt bit
# C_ENABLE_DEBUG_INFO_6 - Enable MM2S Delay Counter Interrupt bit
set dbg15 [hsi::utils::get_ip_param_value $dma_ip C_ENABLE_DEBUG_INFO_15]
set dbg14 [hsi::utils::get_ip_param_value $dma_ip C_ENABLE_DEBUG_INFO_14]
set dbg07 [hsi::utils::get_ip_param_value $dma_ip C_ENABLE_DEBUG_INFO_7]
set dbg06 [hsi::utils::get_ip_param_value $dma_ip C_ENABLE_DEBUG_INFO_6]
if { $dbg15 != 1 || $dbg14 != 1 || $dbg07 != 1 || $dbg06 != 1 } {
puts "ERROR: Failed to generate AXI VDMA node,"
puts "ERROR: Essential VDMA Debug parameters for driver are not enabled in IP"
return;
}
set_drv_conf_prop $drv_handle C_INCLUDE_SG xlnx,include-sg boolean
set_drv_conf_prop $drv_handle c_num_fstores xlnx,num-fstores
set_drv_conf_prop $drv_handle C_USE_FSYNC xlnx,flush-fsync
set_drv_conf_prop $drv_handle c_addr_width xlnx,addrwidth
set baseaddr [get_baseaddr $dma_ip no_prefix]
set tx_chan [hsi::utils::get_ip_param_value $dma_ip C_INCLUDE_MM2S]
if { $tx_chan == 1 } {
set connected_ip [hsi::utils::get_connected_stream_ip $dma_ip "M_AXIS_MM2S"]
set tx_chan_node [add_dma_channel $drv_handle $node "axi-vdma" $baseaddr "MM2S" $vdma_count ]
set intr_info [get_intr_id $drv_handle "mm2s_introut"]
#set intc [hsi::utils::get_interrupt_parent $dma_ip "mm2s_introut"]
if { [llength $intr_info] && ![string match -nocase $intr_info "-1"] } {
hsi::utils::add_new_dts_param $tx_chan_node "interrupts" $intr_info intlist
} else {
dtg_warning "ERROR: ${drv_handle}: mm2s_introut port is not connected"
}
}
set rx_chan [hsi::utils::get_ip_param_value $dma_ip C_INCLUDE_S2MM]
if { $rx_chan ==1 } {
set connected_ip [hsi::utils::get_connected_stream_ip $dma_ip "S_AXIS_S2MM"]
set rx_bassaddr [format %08x [expr 0x$baseaddr + 0x30]]
set rx_chan_node [add_dma_channel $drv_handle $node "axi-vdma" $rx_bassaddr "S2MM" $vdma_count]
set intr_info [get_intr_id $drv_handle "s2mm_introut"]
#set intc [hsi::utils::get_interrupt_parent $dma_ip "s2mm_introut"]
if { [llength $intr_info] && ![string match -nocase $intr_info "-1"] } {
hsi::utils::add_new_dts_param $rx_chan_node "interrupts" $intr_info intlist
} else {
dtg_warning "ERROR: ${drv_handle}: s2mm_introut port is not connected"
}
}
incr vdma_count
hsi::utils::set_os_parameter_value "vdma_count" $vdma_count
set mainline_ker [get_property CONFIG.mainline_kernel [get_os]]
if {[string match -nocase $mainline_ker "none"]} {
set proc_type [get_sw_proc_prop IP_NAME]
set clocknames "s_axi_lite_aclk"
if { $tx_chan ==1 } {
append clocknames " " "m_axi_mm2s_aclk"
append clocknames " " "m_axi_mm2s_aclk"
}
if { $rx_chan ==1 } {
append clocknames " " "m_axi_s2mm_aclk"
append clocknames " " "m_axi_s2mm_aclk"
}
switch $proc_type {
"microblaze" {
gen_dev_ccf_binding $drv_handle "$clocknames"
set_drv_prop_if_empty $drv_handle "clock-names" "$clocknames" stringlist
}
}
} else {
generate_clk_nodes $drv_handle $tx_chan $rx_chan
}
}
proc add_dma_channel {drv_handle parent_node xdma addr mode devid} {
set ip [get_cells -hier $drv_handle]
set modellow [string tolower $mode]
set modeIndex [string index $mode 0]
set dma_channel [add_or_get_dt_node -n "dma-channel" -u $addr -p $parent_node]
hsi::utils::add_new_dts_param $dma_channel "compatible" [format "xlnx,%s-%s-channel" $xdma $modellow] stringlist
hsi::utils::add_new_dts_param $dma_channel "xlnx,device-id" $devid hexint
if {[string match -nocase $mode "S2MM"]} {
set vert_flip [hsi::utils::get_ip_param_value $ip C_ENABLE_VERT_FLIP]
if {$vert_flip == 1} {
hsi::utils::add_new_dts_param $dma_channel "xlnx,enable-vert-flip" "" boolean
}
}
add_cross_property_to_dtnode $drv_handle [format "CONFIG.C_INCLUDE_%s_DRE" $mode] $dma_channel "xlnx,include-dre" boolean
# detection based on two property
set datawidth_list "[format "CONFIG.C_%s_AXIS_%s_DATA_WIDTH" $modeIndex $mode] [format "CONFIG.C_%s_AXIS_%s_TDATA_WIDTH" $modeIndex $mode]"
add_cross_property_to_dtnode $drv_handle $datawidth_list $dma_channel "xlnx,datawidth"
add_cross_property_to_dtnode $drv_handle [format "CONFIG.C_%s_GENLOCK_MODE" $mode] $dma_channel "xlnx,genlock-mode" boolean
return $dma_channel
}
proc generate_clk_nodes {drv_handle tx_chan rx_chan} {
set proc_type [get_sw_proc_prop IP_NAME]
set clocknames "s_axi_lite_aclk"
switch $proc_type {
"ps7_cortexa9" {
set clocks "clkc 15"
if { $tx_chan ==1 } {
append clocknames " " "m_axi_mm2s_aclk"
append clocknames " " "m_axi_mm2s_aclk"
append clocks "" ">, <&clkc 15"
append clocks "" ">, <&clkc 15"
}
if { $rx_chan ==1 } {
append clocknames " " "m_axi_s2mm_aclk"
append clocknames " " "m_axi_s2mm_aclk"
append clocks "" ">, <&clkc 15"
append clocks "" ">, <&clkc 15"
}
set_drv_prop_if_empty $drv_handle "clocks" $clocks reference
set_drv_prop_if_empty $drv_handle "clock-names" $clocknames stringlist
} "psu_cortexa53" {
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set clk_freq [get_clock_frequency [get_cells -hier $drv_handle] "s_axi_lite_aclk"]
if {![string equal $clk_freq ""]} {
if {[lsearch $bus_clk_list $clk_freq] < 0} {
set bus_clk_list [lappend bus_clk_list $clk_freq]
}
}
set bus_clk_cnt [lsearch -exact $bus_clk_list $clk_freq]
set dts_file [current_dt_tree]
set bus_node [add_or_get_bus_node $drv_handle $dts_file]
set misc_clk_node [add_or_get_dt_node -n "misc_clk_${bus_clk_cnt}" -l "misc_clk_${bus_clk_cnt}" \
-d ${dts_file} -p ${bus_node}]
hsi::utils::add_new_dts_param "${misc_clk_node}" "compatible" "fixed-clock" stringlist
hsi::utils::add_new_dts_param "${misc_clk_node}" "#clock-cells" 0 int
hsi::utils::add_new_dts_param "${misc_clk_node}" "clock-frequency" $clk_freq int
# create the node and assuming reg 0 is taken by cpu
set clk_refs [lappend clk_refs misc_clk_${bus_clk_cnt}]
set clocks "$clk_refs"
if { $tx_chan ==1 } {
append clocknames " " "m_axi_mm2s_aclk"
append clocknames " " "m_axi_mm2s_aclk"
append clocks "" ">, <&$clk_refs"
append clocks "" ">, <&$clk_refs"
}
if { $rx_chan ==1 } {
append clocknames " " "m_axi_s2mm_aclk"
append clocknames " " "m_axi_s2mm_aclk"
append clocks "" ">, <&$clk_refs"
append clocks "" ">, <&$clk_refs"
}
set_drv_prop_if_empty $drv_handle "clocks" $clocks reference
set_drv_prop_if_empty $drv_handle "clock-names" $clocknames stringlist
} "microblaze" {
if { $tx_chan ==1 } {
append clocknames " " "m_axi_mm2s_aclk"
append clocknames " " "m_axi_mm2s_aclk"
}
if { $rx_chan ==1 } {
append clocknames " " "m_axi_s2mm_aclk"
append clocknames " " "m_axi_s2mm_aclk"
}
gen_dev_ccf_binding $drv_handle "$clocknames"
set_drv_prop_if_empty $drv_handle "clock-names" "$clocknames" stringlist
}
default {
error "Unknown arch"
}
}
}
================================================
FILE: axi_vdu/data/axi_vdu.mdd
================================================
#
# (C) Copyright 2017-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_vdu
OPTION supported_peripherals = (vdu);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_vdu;
END driver
================================================
FILE: axi_vdu/data/axi_vdu.tcl
================================================
#
# (C) Copyright 2017-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc gen_reset_gpio {drv_handle node} {
set ip [get_cells -hier $drv_handle]
set pins [::hsi::utils::get_source_pins [get_pins -of_objects [get_cells -hier $ip] "vdu_resetn"]]
foreach pin $pins {
set sink_periph [::hsi::get_cells -of_objects $pin]
if {[llength $sink_periph]} {
set sink_ip [get_property IP_NAME $sink_periph]
if {[string match -nocase $sink_ip "axi_gpio"]} {
hsi::utils::add_new_dts_param "$node" "reset-gpios" "$sink_periph 0 1" reference
}
if {[string match -nocase $sink_ip "xlslice"]} {
set gpio [get_property CONFIG.DIN_FROM $sink_periph]
set pins [get_pins -of_objects [get_nets -of_objects [get_pins -of_objects $sink_periph "Din"]]]
foreach pin $pins {
set periph [::hsi::get_cells -of_objects $pin]
if {[llength $periph]} {
set ip [get_property IP_NAME $periph]
set proc_type [get_sw_proc_prop IP_NAME]
if {[string match -nocase $proc_type "psv_cortexa72"] } {
if { $ip in { "versal_cips" "ps_wizard" }} {
# As in versal there is only bank0 for MIOs
set gpio [expr $gpio + 26]
hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio0 $gpio 0" reference
break
}
}
if {[string match -nocase $proc_type "psu_cortexa53"] } {
if {[string match -nocase $ip "zynq_ultra_ps_e"]} {
set gpio [expr $gpio + 78]
hsi::utils::add_new_dts_param "$node" "reset-gpios" "gpio $gpio 0" reference
break
}
}
if {[string match -nocase $ip "axi_gpio"]} {
hsi::utils::add_new_dts_param "$node" "reset-gpios" "$periph $gpio 0 1" reference
}
} else {
dtg_warning "periph for the pin:$pin is NULL $periph...check the design"
}
}
}
} else {
dtg_warning "peripheral for the pin:$pin is NULL $sink_periph...check the design"
}
}
}
proc get_intr_width {intr_parent} {
set intr_width ""
if { [string match -nocase $intr_parent "gic"] } {
set intr_width "3"
} else {
set intr_width "2"
}
return $intr_width
}
proc generate {drv_handle} {
# try to source the common tcl procs
# assuming the order of return is based on repo priority
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
# Generate properties required for vdu node
set node [gen_peripheral_nodes $drv_handle]
if {$node == 0} {
return
}
set drv_label [ps_node_mapping $drv_handle label]
set default_dts [set_drv_def_dts $drv_handle]
set dt_overlay [get_property CONFIG.dt_overlay [get_os]]
if {$dt_overlay} {
set bus_node "amba"
} else {
set bus_node "amba_pl"
}
set vdu_ip [get_cells -hier $drv_handle]
set core_clk [get_property CONFIG.Actual_CORE_CLK [get_cells -hier $drv_handle]]
if {[llength $core_clk]} {
hsi::utils::add_new_dts_param "${node}" "xlnx,core_clk" ${core_clk} int
}
set mcu_clk [get_property CONFIG.Actual_MCU_CLK [get_cells -hier $drv_handle]]
if {[llength $mcu_clk]} {
hsi::utils::add_new_dts_param "${node}" "xlnx,mcu_clk" ${mcu_clk} int
}
set ref_clk [get_property CONFIG.REF_CLK [get_cells -hier $drv_handle]]
if {[llength $ref_clk]} {
hsi::utils::add_new_dts_param "${node}" "xlnx,ref_clk" ${ref_clk} int
}
gen_reset_gpio "$drv_handle" "$node"
set intr_val ""
set intr_parent ""
set intr_names ""
global drv_handlers_mapping
if {[info exists drv_handlers_mapping] && [dict exists $drv_handlers_mapping $drv_handle]} {
if {[dict exists $drv_handlers_mapping $drv_handle "interrupts"]} {
set intr_val [dict get $drv_handlers_mapping $drv_handle "interrupts"]
}
if {[dict exists $drv_handlers_mapping $drv_handle "interrupt-parent"]} {
set intr_parent [dict get $drv_handlers_mapping $drv_handle "interrupt-parent"]
}
if {[dict exists $drv_handlers_mapping $drv_handle "interrupt-names"]} {
set intr_names [dict get $drv_handlers_mapping $drv_handle "interrupt-names"]
}
}
set intrnames_List ""
if {[llength $intr_names]} {
set intrnames_List [regexp -inline -all -- {\S+} $intr_names]
}
set baseaddr [get_baseaddr $vdu_ip no_prefix]
set num_decoders [get_property CONFIG.NUM_DECODER_INSTANCES [get_cells -hier $drv_handle]]
set al5d_baseoffset "0x20000"
set al5d_baseaddr [format %08x [expr 0x$baseaddr + $al5d_baseoffset]]
set al5d_offset "0x100000"
set intr_width ""
for {set inst 0} {$inst < $num_decoders} {incr inst} {
set al5d_node [add_or_get_dt_node -n al5d@$al5d_baseaddr -d $default_dts -p $bus_node]
hsi::utils::add_new_dts_param $al5d_node "compatible" "al,al5d" string
hsi::utils::add_new_dts_param $al5d_node "al,devicename" "allegroDecodeIP$inst" string
hsi::utils::add_new_dts_param $al5d_node "xlnx,vdu" "$drv_label" reference
hsi::utils::add_new_dts_param $al5d_node \
"/*To be filled by user depending on design else CMA region will be used */" "" comment
hsi::utils::add_new_dts_param $al5d_node "/*memory-region = <&mem_reg_0> */" "" comment
# check if base address is 64bit and split it as MSB and LSB
if {[regexp -nocase {0x([0-9a-f]{9})} "0x$al5d_baseaddr" match]} {
set temp $al5d_baseaddr
set temp [string trimleft [string trimleft $temp 0] x]
set len [string length $temp]
set rem [expr {${len} - 8}]
set high_base "0x[string range $temp $rem $len]"
set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]"
set low_base [format 0x%08x $low_base]
if {[regexp -nocase {0x([0-9a-f]{9})} "$al5d_offset" match]} {
set temp $al5d_offset
set temp [string trimleft [string trimleft $temp 0] x]
set len [string length $temp]
set rem [expr {${len} - 8}]
set high_size "0x[string range $temp $rem $len]"
set low_size "0x[string range $temp 0 [expr {${rem} - 1}]]"
set low_size [format 0x%08x $low_size]
set reg "$low_base $high_base $low_size $high_size"
} else {
set reg "$low_base $high_base 0x0 $al5d_offset"
}
} else {
set reg "0x0 0x$al5d_baseaddr 0x0 $al5d_offset"
}
hsi::utils::add_new_dts_param $al5d_node "reg" "$reg" int
if {[llength $intr_parent]} {
set intr_width [get_intr_width $intr_parent]
hsi::utils::add_new_dts_param $al5d_node "interrupt-parent" "$intr_parent" reference
}
if {[llength $intr_width] && [llength $intr_val]} {
set intrs_List [regexp -inline -all -- {\S+} $intr_val]
set intrs_cnt [llength $intrs_List]
set start "[expr {${inst} * $intr_width}]"
set end "[expr {$start + $intr_width - 1}]"
if { $intrs_cnt > $intr_width } {
hsi::utils::add_new_dts_param $al5d_node "interrupts" "[lrange $intrs_List $start $end]" intlist
} else {
hsi::utils::add_new_dts_param $al5d_node "interrupts" "$intrs_List" intlist
}
}
if {[llength $intrnames_List]} {
set intrnames_cnt [llength $intrnames_List]
if { $intrnames_cnt > 1 } {
hsi::utils::add_new_dts_param $al5d_node "interrupt-names" "[lindex $intrnames_List $inst]" string
} else {
hsi::utils::add_new_dts_param $al5d_node "interrupt-names" "[lindex $intrnames_List 0]" string
}
}
set al5d_baseaddr [format %08x [expr 0x$al5d_baseaddr + $al5d_offset]]
}
}
================================================
FILE: axi_xadc/data/axi_xadc.mdd
================================================
#
# (C) Copyright 2015-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axi_xadc
OPTION supported_peripherals = (xadc_wiz);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axi_xadc;
DTGPARAM name = dtg.ip_params, type = boolean;
END driver
================================================
FILE: axi_xadc/data/axi_xadc.tcl
================================================
#
# (C) Copyright 2015-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
# try to source the common tcl procs
# assuming the order of return is based on repo priority
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
gen_xadc_driver_prop $drv_handle
}
proc gen_xadc_driver_prop {drv_handle} {
gen_drv_prop_from_ip $drv_handle
gen_dev_ccf_binding $drv_handle "s_axi_aclk"
set compatible [get_comp_str $drv_handle]
set compatible [append compatible " " "xlnx,axi-xadc-1.00.a"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
set adc_ip [get_cells -hier $drv_handle]
set has_dma [get_property CONFIG.C_HAS_EXTERNAL_MUX $adc_ip]
if {$has_dma == 0} {
set has_dma_str "none"
} elseif {$has_dma == 1} {
set has_dma_str "single"
}
hsi::utils::add_new_property $drv_handle "xlnx,external-mux" string $has_dma_str
if {$has_dma != 0} {
set ext_mux_chan [get_property CONFIG.EXTERNAL_MUX_CHANNEL $adc_ip]
if {[string match -nocase $ext_mux_chan "VP_VN"] } {
set chan_nr 0
} else {
for {set i 0} { $i < 16 } { incr i} {
if {[string match -nocase $ext_mux_chan "VAUXP${i}_VAUXN${i}"]} {
set chan_nr [expr $i + 1]
}
}
}
hsi::utils::add_new_property $drv_handle "xlnx,external-mux-channel" int $chan_nr
}
}
================================================
FILE: axis_switch/data/axis_switch.mdd
================================================
#
# (C) Copyright 2020-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver axis_switch
OPTION supported_peripherals = (axis_switch);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = axis_switch;
END driver
================================================
FILE: axis_switch/data/axis_switch.tcl
================================================
#
# (C) Copyright 2020-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
# try to source the common tcl procs
# assuming the order of return is based on repo priority
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set node [gen_peripheral_nodes $drv_handle]
if {$node == 0} {
return
}
set compatible [get_comp_str $drv_handle]
#set compatible [append compatible " " "xlnx,axis-switch"]
set_drv_prop $drv_handle compatible "$compatible" stringlist
set routing_mode [get_property CONFIG.ROUTING_MODE [get_cells -hier $drv_handle]]
hsi::utils::add_new_dts_param "$node" "xlnx,routing-mode" $routing_mode int
set num_si [get_property CONFIG.NUM_SI [get_cells -hier $drv_handle]]
hsi::utils::add_new_dts_param "$node" "xlnx,num-si-slots" $num_si int
set num_mi [get_property CONFIG.NUM_MI [get_cells -hier $drv_handle]]
hsi::utils::add_new_dts_param "$node" "xlnx,num-mi-slots" $num_mi int
set ports_node [add_or_get_dt_node -n "ports" -l axis_switch_ports$drv_handle -p $node]
hsi::utils::add_new_dts_param "$ports_node" "#address-cells" 1 int
hsi::utils::add_new_dts_param "$ports_node" "#size-cells" 0 int
set port1_node [add_or_get_dt_node -n "port" -l axis_switch_port1$drv_handle -u 1 -p $ports_node]
hsi::utils::add_new_dts_param "$port1_node" "reg" 1 int
set count 0
set master_intf [::hsi::get_intf_pins -of_objects [get_cells -hier $drv_handle] -filter {TYPE==MASTER || TYPE ==INITIATOR}]
set ip [get_cells -hier $drv_handle]
foreach intf $master_intf {
set connectip [get_connected_stream_ip [get_cells -hier $ip] $intf]
if {[llength $connectip]} {
set outipname [get_property IP_NAME $connectip]
set valid_mmip_list "mipi_csi2_rx_subsystem v_tpg v_smpte_uhdsdi_rx_ss v_smpte_uhdsdi_tx_ss v_demosaic v_gamma_lut v_proc_ss v_frmbuf_rd v_frmbuf_wr v_uhdsdi_audio i2s_receiver mipi_dsi_tx_subsystem v_mix v_multi_scaler v_scenechange"
if {[lsearch -nocase $valid_mmip_list $outipname] >= 0} {
set ip_mem_handles [hsi::utils::get_ip_mem_ranges $connectip]
incr count
}
if {$count ==1} {
if {[llength $connectip]} {
set port_node [add_or_get_dt_node -n "port" -l axis_switch_port1$ip -u 1 -p $ports_node]
hsi::utils::add_new_dts_param "$port_node" "reg" 1 int
set axis_node [add_or_get_dt_node -n "endpoint" -l axis_switch_out1$ip -p $port_node]
gen_axis_switch_port1_endpoint $ip "axis_switch_out1$ip"
hsi::utils::add_new_dts_param "$axis_node" "remote-endpoint" $connectip$ip reference
gen_axis_switch_port1_remote_endpoint $ip $connectip$ip
}
}
if {$count == 2} {
if {[llength $connectip]} {
set port_node [add_or_get_dt_node -n "port" -l axis_switch_port2$ip -u 2 -p $ports_node]
hsi::utils::add_new_dts_param "$port_node" "reg" 2 int
set axis_node [add_or_get_dt_node -n "endpoint" -l axis_switch_out2$ip -p $port_node]
gen_axis_switch_port2_endpoint $ip "axis_switch_out2$ip"
hsi::utils::add_new_dts_param "$axis_node" "remote-endpoint" $connectip$ip reference
gen_axis_switch_port2_remote_endpoint $ip $connectip$ip
}
}
}
}
}
================================================
FILE: canfdps/data/canfdps.mdd
================================================
#
# (C) Copyright 2019-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver canfdps
OPTION supported_peripherals = (psu_canfd psv_canfd psx_canfd);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = canfdps;
END driver
================================================
FILE: canfdps/data/canfdps.tcl
================================================
#
# (C) Copyright 2019-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
}
================================================
FILE: canps/data/canps.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver canps
OPTION supported_peripherals = (ps7_can psu_can psv_can);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = canps;
END driver
================================================
FILE: canps/data/canps.tcl
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
}
================================================
FILE: cpu/data/cpu.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver cpu
OPTION driver_state = ACTIVE;
OPTION supported_peripherals = (microblaze);
OPTION supported_os_types = (DTS);
OPTION NAME = cpu;
DTGPARAM name = dev_type, default = cpu , type = string;
DTGPARAM name = device_type, default = cpu , type = string;
DTGPARAM name = clock-frequency, type = int , default = 1000000 ;
DTGPARAM name = clocks, type = int, default = &clk_cpu;
DTGPARAM name = timebase-frequency, type = int , default = 1000000 ;
DTGPARAM name = d-cache-baseaddr, type = hexint ;
DTGPARAM name = d-cache-highaddr, type = hexint ;
DTGPARAM name = d-cache-line-size, type = hexint ;
DTGPARAM name = d-cache-size, type = hexint ;
DTGPARAM name = i-cache-baseaddr, type = hexint ;
DTGPARAM name = i-cache-highaddr, type = hexint ;
DTGPARAM name = i-cache-line-size, type = hexint ;
DTGPARAM name = i-cache-size, type = hexint ;
DTGPARAM name = model, type = string;
DTGPARAM name = dtg.ip_params, type = boolean;
END driver
================================================
FILE: cpu/data/cpu.tcl
================================================
#
# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd
# Based on original code:
# (C) Copyright 2007-2014 Michal Simek
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Michal SIMEK <monstr@monstr.eu>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set ip [get_cells -hier $drv_handle]
set clk ""
set clkhandle [get_pins -of_objects $ip "CLK"]
if { [string compare -nocase $clkhandle ""] != 0 } {
set clk [get_property CLK_FREQ $clkhandle]
}
if { [llength $ip] } {
set_property CONFIG.clock-frequency "$clk" $drv_handle
set_property CONFIG.timebase-frequency "$clk" $drv_handle
}
set icache_size [hsi::utils::get_ip_param_value $ip "C_CACHE_BYTE_SIZE"]
set isize [check_64bit $icache_size]
set icache_base [hsi::utils::get_ip_param_value $ip "C_ICACHE_BASEADDR"]
set ibase [check_64bit $icache_base]
set icache_high [hsi::utils::get_ip_param_value $ip "C_ICACHE_HIGHADDR"]
set ihigh_base [check_64bit $icache_high]
set dcache_size [hsi::utils::get_ip_param_value $ip "C_DCACHE_BYTE_SIZE"]
set dsize [check_64bit $dcache_size]
set dcache_base [hsi::utils::get_ip_param_value $ip "C_DCACHE_BASEADDR"]
set dbase [check_64bit $dcache_base]
set dcache_high [hsi::utils::get_ip_param_value $ip "C_DCACHE_HIGHADDR"]
set dhigh_base [check_64bit $dcache_high]
set icache_line_size [expr 4*[hsi::utils::get_ip_param_value $ip "C_ICACHE_LINE_LEN"]]
set dcache_line_size [expr 4*[hsi::utils::get_ip_param_value $ip "C_DCACHE_LINE_LEN"]]
if { [llength $icache_size] != 0 } {
set_property CONFIG.i-cache-baseaddr "$ibase" $drv_handle
set_property CONFIG.i-cache-highaddr "$ihigh_base" $drv_handle
set_property CONFIG.i-cache-size "$isize" $drv_handle
set_property CONFIG.i-cache-line-size "$icache_line_size" $drv_handle
}
if { [llength $dcache_size] != 0 } {
set_property CONFIG.d-cache-baseaddr "$dbase" $drv_handle
set_property CONFIG.d-cache-highaddr "$dhigh_base" $drv_handle
set_property CONFIG.d-cache-size "$dsize" $drv_handle
set_property CONFIG.d-cache-line-size "$dcache_line_size" $drv_handle
}
set model "[get_property IP_NAME $ip],[hsi::utils::get_ip_version $ip]"
set_property CONFIG.model $model $drv_handle
# create root node
set master_root_node [gen_root_node $drv_handle]
set nodes [gen_cpu_nodes $drv_handle]
}
proc check_64bit {base} {
if {[regexp -nocase {0x([0-9a-f]{9})} "$base" match]} {
set temp $base
set temp [string trimleft [string trimleft $temp 0] x]
set len [string length $temp]
set rem [expr {${len} - 8}]
set high_base "0x[string range $temp $rem $len]"
set low_base "0x[string range $temp 0 [expr {${rem} - 1}]]"
set low_base [format 0x%08x $low_base]
if {$low_base == 0x0} {
set reg "$high_base"
} else {
set reg "$low_base $high_base"
}
} else {
set reg "$base"
}
return $reg
}
================================================
FILE: cpu_cortexa53/data/cpu_cortexa53.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver cpu_cortexa53
OPTION driver_state = ACTIVE;
OPTION supported_peripherals = (psu_cortexa53);
OPTION supported_os_types = (DTS);
OPTION NAME = cpu_cortexa53;
END driver
================================================
FILE: cpu_cortexa53/data/cpu_cortexa53.tcl
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
global dtsi_fname
set mainline_ker [get_property CONFIG.mainline_kernel [get_os]]
set valid_mainline_kernel_list "v4.17 v4.18 v4.19 v5.0 v5.1 v5.2 v5.3 v5.4"
if {[lsearch $valid_mainline_kernel_list $mainline_ker] >= 0 } {
set dtsi_fname "zynqmp/zynqmp.dtsi"
} else {
set dtsi_fname "zynqmp/zynqmp.dtsi"
}
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
# create root node
set master_root_node [gen_root_node $drv_handle]
set nodes [gen_cpu_nodes $drv_handle]
}
================================================
FILE: cpu_cortexa72/data/cpu_cortexa72.mdd
================================================
#
# (C) Copyright 2018-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver cpu_cortexa72
OPTION driver_state = ACTIVE;
OPTION supported_peripherals = (psv_cortexa72);
OPTION supported_os_types = (DTS);
OPTION NAME = cpu_cortexa72;
END driver
================================================
FILE: cpu_cortexa72/data/cpu_cortexa72.tcl
================================================
#
# (C) Copyright 2018-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
global dtsi_fname
set dtsi_fname "versal/versal.dtsi"
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
# create root node
set master_root_node [gen_root_node $drv_handle]
set nodes [gen_cpu_nodes $drv_handle]
}
================================================
FILE: cpu_cortexa78/data/cpu_cortexa78.mdd
================================================
#
# (C) Copyright 2018-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver cpu_cortexa78
OPTION driver_state = ACTIVE;
OPTION supported_peripherals = (psx_cortexa78);
OPTION supported_os_types = (DTS);
OPTION NAME = cpu_cortexa78;
END driver
================================================
FILE: cpu_cortexa78/data/cpu_cortexa78.tcl
================================================
#
# (C) Copyright 2018-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
global dtsi_fname
set board_dtsi_file ""
set overrides [get_property CONFIG.periph_type_overrides [get_os]]
foreach override $overrides {
if {[lindex $override 0] == "BOARD"} {
set board_dtsi_file [lindex $override 1]
}
}
#TMP fix to support ipp fixed clocks
if {[string match -nocase $board_dtsi_file "versal-net-ipp-rev1.9"]} {
set dtsi_fname "versal-net/versal-net-ipp-rev1.9.dtsi"
} else {
set dtsi_fname "versal-net/versal-net.dtsi"
}
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
# create root node
set master_root_node [gen_root_node $drv_handle]
set nodes [gen_cpu_nodes $drv_handle]
}
================================================
FILE: cpu_cortexa9/data/cpu_cortexa9.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver cpu_cortexa9
OPTION driver_state = ACTIVE;
OPTION supported_peripherals = (ps7_cortexa9);
OPTION supported_os_types = (DTS);
OPTION NAME = cpu_cortexa9;
END driver
================================================
FILE: cpu_cortexa9/data/cpu_cortexa9.tcl
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
global dtsi_fname
set dtsi_fname "zynq/zynq-7000.dtsi"
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
# create root node
set master_root_node [gen_root_node $drv_handle]
set nodes [gen_cpu_nodes $drv_handle]
}
================================================
FILE: dccps/data/dccps.mdd
================================================
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
OPTION psf_version = 3.0;
BEGIN driver dccps
OPTION supported_peripherals = (psu_coresight_0 psv_coresight psx_coresight);
OPTION supported_os_types = (DTS);
OPTION driver_state = ACTIVE;
OPTION NAME = dccps;
DTGPARAM name = device_type , type = string, default = serial;
DTGPARAM name = dtg.alias, type = string, default = serial;
DTGPARAM name = port-number, type = int, default = 0;
END driver
================================================
FILE: dccps/data/dccps.tcl
================================================
#
# (C) Copyright 2020-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
proc generate {drv_handle} {
# try to source the common tcl procs
# assuming the order of return is based on repo priority
foreach i [get_sw_cores device_tree] {
set common_tcl_file "[get_property "REPOSITORY" $i]/data/common_proc.tcl"
if {[file exists $common_tcl_file]} {
source $common_tcl_file
break
}
}
set ip [get_cells -hier $drv_handle]
set def_dts [get_property CONFIG.pcw_dts [get_os]]
set dcc_node [add_or_get_dt_node -n "&dcc" -d $def_dts]
hsi::utils::add_new_dts_param "${dcc_node}" "status" "okay" string
}
================================================
FILE: ddrcps/data/ddrcps.mdd
================================================
#
# (C) Copyright 2014-2022 Xilinx, Inc.
# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.
#
gitextract__dnvpkf3/
├── .github/
│ └── pull_request_template.md
├── .gitignore
├── RM/
│ └── data/
│ ├── RM.mdd
│ └── RM.tcl
├── ai_engine/
│ └── data/
│ ├── ai_engine.mdd
│ └── ai_engine.tcl
├── ams/
│ └── data/
│ ├── ams.mdd
│ └── ams.tcl
├── apmps/
│ └── data/
│ ├── apmps.mdd
│ └── apmps.tcl
├── audio_embed/
│ └── data/
│ ├── audio_embed.mdd
│ └── audio_embed.tcl
├── audio_formatter/
│ └── data/
│ ├── audio_formatter.mdd
│ └── audio_formatter.tcl
├── audio_spdif/
│ └── data/
│ ├── audio_spdif.mdd
│ └── audio_spdif.tcl
├── axi_can/
│ └── data/
│ ├── axi_can.mdd
│ └── axi_can.tcl
├── axi_cdma/
│ └── data/
│ ├── axi_cdma.mdd
│ └── axi_cdma.tcl
├── axi_clk_wiz/
│ └── data/
│ ├── axi_clk_wiz.mdd
│ └── axi_clk_wiz.tcl
├── axi_dma/
│ └── data/
│ ├── axi_dma.mdd
│ └── axi_dma.tcl
├── axi_emc/
│ └── data/
│ ├── axi_emc.mdd
│ └── axi_emc.tcl
├── axi_ethernet/
│ └── data/
│ ├── axi_ethernet.mdd
│ └── axi_ethernet.tcl
├── axi_gpio/
│ └── data/
│ ├── gpio.mdd
│ └── gpio.tcl
├── axi_iic/
│ └── data/
│ ├── axi_iic.mdd
│ └── axi_iic.tcl
├── axi_mcdma/
│ └── data/
│ ├── axi_mcdma.mdd
│ └── axi_mcdma.tcl
├── axi_pcie/
│ └── data/
│ ├── axi_pcie.mdd
│ └── axi_pcie.tcl
├── axi_perf_mon/
│ └── data/
│ ├── axi_perf_mon.mdd
│ └── axi_perf_mon.tcl
├── axi_qspi/
│ └── data/
│ ├── axi_qspi.mdd
│ └── axi_qspi.tcl
├── axi_sysace/
│ └── data/
│ ├── axi_sysace.mdd
│ └── axi_sysace.tcl
├── axi_tft/
│ └── data/
│ ├── axi_tft.mdd
│ └── axi_tft.tcl
├── axi_timebase_wdt/
│ └── data/
│ ├── axi_timebase_wdt.mdd
│ └── axi_timebase_wdt.tcl
├── axi_traffic_gen/
│ └── data/
│ ├── axi_traffic_gen.mdd
│ └── axi_traffic_gen.tcl
├── axi_usb2_device/
│ └── data/
│ ├── axi_usb2_device.mdd
│ └── axi_usb2_device.tcl
├── axi_vcu/
│ └── data/
│ ├── axi_vcu.mdd
│ └── axi_vcu.tcl
├── axi_vdma/
│ └── data/
│ ├── axi_vdma.mdd
│ └── axi_vdma.tcl
├── axi_vdu/
│ └── data/
│ ├── axi_vdu.mdd
│ └── axi_vdu.tcl
├── axi_xadc/
│ └── data/
│ ├── axi_xadc.mdd
│ └── axi_xadc.tcl
├── axis_switch/
│ └── data/
│ ├── axis_switch.mdd
│ └── axis_switch.tcl
├── canfdps/
│ └── data/
│ ├── canfdps.mdd
│ └── canfdps.tcl
├── canps/
│ └── data/
│ ├── canps.mdd
│ └── canps.tcl
├── cpu/
│ └── data/
│ ├── cpu.mdd
│ └── cpu.tcl
├── cpu_cortexa53/
│ └── data/
│ ├── cpu_cortexa53.mdd
│ └── cpu_cortexa53.tcl
├── cpu_cortexa72/
│ └── data/
│ ├── cpu_cortexa72.mdd
│ └── cpu_cortexa72.tcl
├── cpu_cortexa78/
│ └── data/
│ ├── cpu_cortexa78.mdd
│ └── cpu_cortexa78.tcl
├── cpu_cortexa9/
│ └── data/
│ ├── cpu_cortexa9.mdd
│ └── cpu_cortexa9.tcl
├── dccps/
│ └── data/
│ ├── dccps.mdd
│ └── dccps.tcl
├── ddrcps/
│ └── data/
│ ├── ddrcps.mdd
│ └── ddrcps.tcl
├── ddrps/
│ └── data/
│ ├── ddrps.mdd
│ └── ddrps.tcl
├── ddrpsv/
│ └── data/
│ ├── ddrpsv.mdd
│ └── ddrpsv.tcl
├── debug_bridge/
│ └── data/
│ ├── debug_bridge.mdd
│ └── debug_bridge.tcl
├── demosaic/
│ └── data/
│ ├── demosaic.mdd
│ └── demosaic.tcl
├── devcfg/
│ └── data/
│ ├── devcfg.mdd
│ └── devcfg.tcl
├── device_tree/
│ └── data/
│ ├── common_proc.tcl
│ ├── device_tree.mld
│ ├── device_tree.mss
│ ├── device_tree.tcl
│ └── kernel_dtsi/
│ ├── 2014.4/
│ │ └── zynq/
│ │ ├── skeleton.dtsi
│ │ └── zynq-7000.dtsi
│ ├── 2015.1/
│ │ └── zynq/
│ │ ├── skeleton.dtsi
│ │ └── zynq-7000.dtsi
│ ├── 2015.2/
│ │ └── zynq/
│ │ ├── skeleton.dtsi
│ │ └── zynq-7000.dtsi
│ ├── 2015.3/
│ │ └── zynq/
│ │ ├── skeleton.dtsi
│ │ └── zynq-7000.dtsi
│ ├── 2015.4/
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2016.1/
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2016.2/
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2016.3/
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2016.4/
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2017.1/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu102.dtsi
│ │ │ ├── zcu106.dtsi
│ │ │ └── zedboard.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2017.2/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu102.dtsi
│ │ │ ├── zcu106.dtsi
│ │ │ └── zedboard.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2017.3/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zedboard.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2017.4/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zedboard.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2018.1/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1275-revb.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ └── zedboard.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2018.2/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1275-revb.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ └── zedboard.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2018.3/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1275-revb.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ └── zedboard.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2019.1/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1275-revb.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-g-reva.dtsi
│ │ │ ├── zynqmp-a2197-m-reva.dtsi
│ │ │ ├── zynqmp-a2197-p-reva.dtsi
│ │ │ └── zynqmp-a2197-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ └── pinctrl/
│ │ │ └── pinctrl-zynqmp.h
│ │ ├── versal/
│ │ │ └── versal.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2019.2/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ └── zynqmp-e-a2197-00-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ └── pinctrl/
│ │ │ └── pinctrl-zynqmp.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ └── versal.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2020.1/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ └── zynqmp-p-a2197-00-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2020.2/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vck5000-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ └── zynqmp-p-a2197-00-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2021.1/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vck5000-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── versal-vp-x-a2785-00-reva.dtsi
│ │ │ ├── versal-vpk120-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zcu670-reva.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-sm-k26-reva-mlcc.dtsi
│ │ │ ├── zynqmp-sm-k26-reva.dtsi
│ │ │ ├── zynqmp-sm-k26-reva01-mlcc.dtsi
│ │ │ ├── zynqmp-sm-k26-reva01.dtsi
│ │ │ ├── zynqmp-sm-k26-revb-mlcc.dtsi
│ │ │ ├── zynqmp-sm-k26-revb.dtsi
│ │ │ ├── zynqmp-sm-k26-revb01-mlcc.dtsi
│ │ │ ├── zynqmp-sm-k26-revb01.dtsi
│ │ │ ├── zynqmp-smk-k26-reva.dtsi
│ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi
│ │ │ └── zynqmp-vpk120-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── dma/
│ │ │ │ └── xlnx-zynqmp-dpdma.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2021.2/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105-tmr.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vck5000-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── versal-vp-x-a2785-00-reva.dtsi
│ │ │ ├── versal-vpk120-reva.dtsi
│ │ │ ├── versal-vpk120-revb.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zcu670-reva.dtsi
│ │ │ ├── zcu670-revb.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-sc-revb.dtsi
│ │ │ ├── zynqmp-sm-k26-reva.dtsi
│ │ │ ├── zynqmp-smk-k26-reva.dtsi
│ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi
│ │ │ └── zynqmp-vpk120-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── dma/
│ │ │ │ └── xlnx-zynqmp-dpdma.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2022.1/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105-tmr.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vck5000-reva.dtsi
│ │ │ ├── versal-vhk158-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── versal-vp-x-a2785-00-reva.dtsi
│ │ │ ├── versal-vpk120-reva.dtsi
│ │ │ ├── versal-vpk120-revb.dtsi
│ │ │ ├── versal-vpk180-reva.dtsi
│ │ │ ├── versal-x-ebm-01-reva.dtsi
│ │ │ ├── versal-x-ebm-02-reva.dtsi
│ │ │ ├── versal-x-ebm-03-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zcu670-reva.dtsi
│ │ │ ├── zcu670-revb.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-sc-revb.dtsi
│ │ │ ├── zynqmp-sm-k26-reva.dtsi
│ │ │ ├── zynqmp-smk-k26-reva.dtsi
│ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi
│ │ │ └── zynqmp-vpk120-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── dma/
│ │ │ │ └── xlnx-zynqmp-dpdma.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── net/
│ │ │ │ └── ti-dp83867.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2022.2/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105-tmr.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-net-emu-rev1.9.dtsi
│ │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi
│ │ │ ├── versal-net-ipp-rev1.9.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vck5000-reva.dtsi
│ │ │ ├── versal-vek280-reva.dtsi
│ │ │ ├── versal-vhk158-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── versal-vp-x-a2785-00-reva.dtsi
│ │ │ ├── versal-vpk120-reva.dtsi
│ │ │ ├── versal-vpk120-revb.dtsi
│ │ │ ├── versal-vpk180-reva.dtsi
│ │ │ ├── versal-x-ebm-01-reva.dtsi
│ │ │ ├── versal-x-ebm-02-reva.dtsi
│ │ │ ├── versal-x-ebm-03-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zcu670-reva.dtsi
│ │ │ ├── zcu670-revb.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-revb.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-sc-revb.dtsi
│ │ │ ├── zynqmp-sm-k26-reva.dtsi
│ │ │ ├── zynqmp-smk-k26-reva.dtsi
│ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi
│ │ │ └── zynqmp-vpk120-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── dma/
│ │ │ │ └── xlnx-zynqmp-dpdma.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── net/
│ │ │ │ └── ti-dp83867.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-net-power.h
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ ├── xlnx-versal-regnode.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ ├── xlnx-versal-net-resets.h
│ │ │ ├── xlnx-versal-resets.h
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── versal-net/
│ │ │ └── versal-net-ipp-rev1.9.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2023.1/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105-tmr.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-net-emu-rev1.9.dtsi
│ │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi
│ │ │ ├── versal-net-ipp-rev1.9.dtsi
│ │ │ ├── versal-net-vn-p-b2197-00-reva-pl.dtsi
│ │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vck5000-reva.dtsi
│ │ │ ├── versal-vek280-reva.dtsi
│ │ │ ├── versal-vek280-revb.dtsi
│ │ │ ├── versal-vhk158-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── versal-vp-x-a2785-00-reva.dtsi
│ │ │ ├── versal-vpk120-reva.dtsi
│ │ │ ├── versal-vpk120-revb.dtsi
│ │ │ ├── versal-vpk180-reva.dtsi
│ │ │ ├── versal-x-ebm-01-reva.dtsi
│ │ │ ├── versal-x-ebm-02-reva.dtsi
│ │ │ ├── versal-x-ebm-03-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zcu670-reva.dtsi
│ │ │ ├── zcu670-revb.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-revb.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-sc-revb.dtsi
│ │ │ ├── zynqmp-sc-revc.dtsi
│ │ │ ├── zynqmp-sc-vek280-reva.dtsi
│ │ │ ├── zynqmp-sc-vek280-revb.dtsi
│ │ │ ├── zynqmp-sm-k24-reva.dtsi
│ │ │ ├── zynqmp-sm-k26-reva.dtsi
│ │ │ ├── zynqmp-smk-k24-reva.dtsi
│ │ │ ├── zynqmp-smk-k26-reva.dtsi
│ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi
│ │ │ └── zynqmp-vpk120-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ ├── xlnx-versal-net-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── dma/
│ │ │ │ └── xlnx-zynqmp-dpdma.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── net/
│ │ │ │ ├── mscc-phy-vsc8531.h
│ │ │ │ └── ti-dp83867.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-net-power.h
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ ├── xlnx-versal-regnode.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ ├── xlnx-versal-net-resets.h
│ │ │ ├── xlnx-versal-resets.h
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── versal-net/
│ │ │ ├── versal-net-clk-ccf.dtsi
│ │ │ ├── versal-net-clk.dtsi
│ │ │ ├── versal-net-ipp-rev1.9.dtsi
│ │ │ └── versal-net.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2023.2/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105-tmr.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-net-emu-rev1.9.dtsi
│ │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi
│ │ │ ├── versal-net-ipp-rev1.9.dtsi
│ │ │ ├── versal-net-vn-p-b2197-00-reva-pl.dtsi
│ │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi
│ │ │ ├── versal-net-vn-x-b2197-00-reva.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vck5000-reva.dtsi
│ │ │ ├── versal-vek280-reva.dtsi
│ │ │ ├── versal-vek280-revb.dtsi
│ │ │ ├── versal-vhk158-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── versal-vp-x-a2785-00-reva.dtsi
│ │ │ ├── versal-vpk120-reva.dtsi
│ │ │ ├── versal-vpk120-revb.dtsi
│ │ │ ├── versal-vpk180-reva.dtsi
│ │ │ ├── versal-x-ebm-01-reva.dtsi
│ │ │ ├── versal-x-ebm-02-reva.dtsi
│ │ │ ├── versal-x-ebm-03-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zcu670-reva.dtsi
│ │ │ ├── zcu670-revb.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-revb.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-sc-revb.dtsi
│ │ │ ├── zynqmp-sc-revc.dtsi
│ │ │ ├── zynqmp-sc-vek280-reva.dtsi
│ │ │ ├── zynqmp-sc-vek280-revb.dtsi
│ │ │ ├── zynqmp-sm-k24-reva.dtsi
│ │ │ ├── zynqmp-sm-k26-reva.dtsi
│ │ │ ├── zynqmp-smk-k24-reva.dtsi
│ │ │ ├── zynqmp-smk-k26-reva.dtsi
│ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi
│ │ │ └── zynqmp-vpk120-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ ├── xlnx-versal-net-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── dma/
│ │ │ │ └── xlnx-zynqmp-dpdma.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── net/
│ │ │ │ ├── mscc-phy-vsc8531.h
│ │ │ │ └── ti-dp83867.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-net-power.h
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ ├── xlnx-versal-regnode.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ ├── xlnx-versal-net-resets.h
│ │ │ ├── xlnx-versal-resets.h
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── versal-net/
│ │ │ ├── versal-net-clk-ccf.dtsi
│ │ │ ├── versal-net-clk.dtsi
│ │ │ ├── versal-net-ipp-rev1.9.dtsi
│ │ │ └── versal-net.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2024.1/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105-tmr.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emb-plus-ve2302-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-net-emu-rev1.9.dtsi
│ │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi
│ │ │ ├── versal-net-ipp-rev1.9.dtsi
│ │ │ ├── versal-net-vn-p-b2197-00-reva-pl.dtsi
│ │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi
│ │ │ ├── versal-net-vn-x-b2197-00-reva.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vck5000-reva.dtsi
│ │ │ ├── versal-vek280-reva.dtsi
│ │ │ ├── versal-vek280-revb.dtsi
│ │ │ ├── versal-vhk158-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── versal-vp-x-a2785-00-reva.dtsi
│ │ │ ├── versal-vpk120-reva.dtsi
│ │ │ ├── versal-vpk120-revb.dtsi
│ │ │ ├── versal-vpk180-reva.dtsi
│ │ │ ├── versal-x-ebm-01-reva.dtsi
│ │ │ ├── versal-x-ebm-02-reva.dtsi
│ │ │ ├── versal-x-ebm-03-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zcu670-reva.dtsi
│ │ │ ├── zcu670-revb.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-revb.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-sc-revb.dtsi
│ │ │ ├── zynqmp-sc-revc.dtsi
│ │ │ ├── zynqmp-sc-vek280-reva.dtsi
│ │ │ ├── zynqmp-sc-vek280-revb.dtsi
│ │ │ ├── zynqmp-sm-k24-reva.dtsi
│ │ │ ├── zynqmp-sm-k26-reva.dtsi
│ │ │ ├── zynqmp-smk-k24-reva.dtsi
│ │ │ ├── zynqmp-smk-k26-reva.dtsi
│ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi
│ │ │ └── zynqmp-vpk120-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ ├── xlnx-versal-net-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── dma/
│ │ │ │ └── xlnx-zynqmp-dpdma.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── net/
│ │ │ │ ├── mscc-phy-vsc8531.h
│ │ │ │ └── ti-dp83867.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-net-power.h
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ ├── xlnx-versal-regnode.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ ├── xlnx-versal-net-resets.h
│ │ │ ├── xlnx-versal-resets.h
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── versal-net/
│ │ │ ├── versal-net-clk-ccf.dtsi
│ │ │ ├── versal-net-clk.dtsi
│ │ │ ├── versal-net-ipp-rev1.9.dtsi
│ │ │ └── versal-net.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── 2024.2/
│ │ ├── BOARD/
│ │ │ ├── ac701-full.dtsi
│ │ │ ├── ac701-lite.dtsi
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── kc705-full.dtsi
│ │ │ ├── kc705-lite.dtsi
│ │ │ ├── kcu105-tmr.dtsi
│ │ │ ├── kcu105.dtsi
│ │ │ ├── sp701-rev1.0.dtsi
│ │ │ ├── vcu118-rev2.0.dtsi
│ │ │ ├── versal-a2197-sc-reva.dtsi
│ │ │ ├── versal-emb-plus-ve2302-reva.dtsi
│ │ │ ├── versal-emu-itr8-cn13940875.dtsi
│ │ │ ├── versal-net-emu-rev1.9.dtsi
│ │ │ ├── versal-net-ipp-rev1.9-ospi.dtsi
│ │ │ ├── versal-net-ipp-rev1.9.dtsi
│ │ │ ├── versal-net-vn-p-b2197-00-reva-pl.dtsi
│ │ │ ├── versal-net-vn-p-b2197-00-reva.dtsi
│ │ │ ├── versal-net-vn-x-b2197-00-reva.dtsi
│ │ │ ├── versal-spp-itr8-cn13940875.dtsi
│ │ │ ├── versal-v350-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva-pm.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva-ospi.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── versal-vc-p-a2197-00-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-rev1.1.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vck190-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vck190-reva.dtsi
│ │ │ ├── versal-vck5000-reva.dtsi
│ │ │ ├── versal-vek280-reva.dtsi
│ │ │ ├── versal-vek280-revb.dtsi
│ │ │ ├── versal-vhk158-reva.dtsi
│ │ │ ├── versal-virt.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-rev1.1.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-01-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-02-reva.dtsi
│ │ │ ├── versal-vmk180-reva-x-ebm-03-reva.dtsi
│ │ │ ├── versal-vmk180-reva.dtsi
│ │ │ ├── versal-vp-x-a2785-00-reva.dtsi
│ │ │ ├── versal-vpk120-reva.dtsi
│ │ │ ├── versal-vpk120-revb.dtsi
│ │ │ ├── versal-vpk180-reva.dtsi
│ │ │ ├── versal-x-ebm-01-reva.dtsi
│ │ │ ├── versal-x-ebm-02-reva.dtsi
│ │ │ ├── versal-x-ebm-03-reva.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc702.dtsi
│ │ │ ├── zc706.dtsi
│ │ │ ├── zcu100-reva.dtsi
│ │ │ ├── zcu100-revb.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu104-revc.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ ├── zcu111-reva.dtsi
│ │ │ ├── zcu1275-reva.dtsi
│ │ │ ├── zcu1275-revb.dtsi
│ │ │ ├── zcu1285-reva.dtsi
│ │ │ ├── zcu208-reva.dtsi
│ │ │ ├── zcu216-reva.dtsi
│ │ │ ├── zcu670-reva.dtsi
│ │ │ ├── zcu670-revb.dtsi
│ │ │ ├── zedboard.dtsi
│ │ │ ├── zynqmp-a2197-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-e-a2197-00-revb.dtsi
│ │ │ ├── zynqmp-g-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-01-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-02-reva.dtsi
│ │ │ ├── zynqmp-m-a2197-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-01-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-02-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-03-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-04-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva-x-prc-05-reva.dtsi
│ │ │ ├── zynqmp-p-a2197-00-reva.dtsi
│ │ │ ├── zynqmp-sc-revb.dtsi
│ │ │ ├── zynqmp-sc-revc.dtsi
│ │ │ ├── zynqmp-sc-vek280-reva.dtsi
│ │ │ ├── zynqmp-sc-vek280-revb.dtsi
│ │ │ ├── zynqmp-sm-k24-reva.dtsi
│ │ │ ├── zynqmp-sm-k26-reva.dtsi
│ │ │ ├── zynqmp-smk-k24-reva.dtsi
│ │ │ ├── zynqmp-smk-k26-reva.dtsi
│ │ │ ├── zynqmp-vp-x-a2785-00-reva.dtsi
│ │ │ └── zynqmp-vpk120-reva.dtsi
│ │ ├── include/
│ │ │ └── dt-bindings/
│ │ │ ├── clock/
│ │ │ │ ├── xlnx-versal-clk.h
│ │ │ │ ├── xlnx-versal-net-clk.h
│ │ │ │ └── xlnx-zynqmp-clk.h
│ │ │ ├── dma/
│ │ │ │ └── xlnx-zynqmp-dpdma.h
│ │ │ ├── gpio/
│ │ │ │ └── gpio.h
│ │ │ ├── input/
│ │ │ │ └── input.h
│ │ │ ├── interrupt-controller/
│ │ │ │ └── irq.h
│ │ │ ├── net/
│ │ │ │ ├── mscc-phy-vsc8531.h
│ │ │ │ └── ti-dp83867.h
│ │ │ ├── phy/
│ │ │ │ └── phy.h
│ │ │ ├── pinctrl/
│ │ │ │ └── pinctrl-zynqmp.h
│ │ │ ├── power/
│ │ │ │ ├── xlnx-versal-net-power.h
│ │ │ │ ├── xlnx-versal-power.h
│ │ │ │ ├── xlnx-versal-regnode.h
│ │ │ │ └── xlnx-zynqmp-power.h
│ │ │ └── reset/
│ │ │ ├── xlnx-versal-net-resets.h
│ │ │ ├── xlnx-versal-resets.h
│ │ │ └── xlnx-zynqmp-resets.h
│ │ ├── versal/
│ │ │ ├── versal-clk.dtsi
│ │ │ ├── versal-spp-pm.dtsi
│ │ │ └── versal.dtsi
│ │ ├── versal-net/
│ │ │ ├── versal-net-clk-ccf.dtsi
│ │ │ ├── versal-net-clk.dtsi
│ │ │ ├── versal-net-ipp-rev1.9.dtsi
│ │ │ └── versal-net.dtsi
│ │ ├── zynq/
│ │ │ ├── skeleton.dtsi
│ │ │ └── zynq-7000.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk-ccf.dtsi
│ │ └── zynqmp.dtsi
│ ├── v4.17/
│ │ ├── board/
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc1751-dc3.dtsi
│ │ │ ├── zc1751-dc4.dtsi
│ │ │ ├── zc1751-dc5.dtsi
│ │ │ ├── zcep108.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zcu111-reva.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── v4.18/
│ │ ├── board/
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc1751-dc3.dtsi
│ │ │ ├── zc1751-dc4.dtsi
│ │ │ ├── zc1751-dc5.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zcu111-reva.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── v4.19/
│ │ ├── board/
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc1751-dc3.dtsi
│ │ │ ├── zc1751-dc4.dtsi
│ │ │ ├── zc1751-dc5.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zcu111-reva.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── v4.20/
│ │ ├── board/
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc1751-dc3.dtsi
│ │ │ ├── zc1751-dc4.dtsi
│ │ │ ├── zc1751-dc5.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zcu111-reva.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── v5.0/
│ │ ├── board/
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc1751-dc3.dtsi
│ │ │ ├── zc1751-dc4.dtsi
│ │ │ ├── zc1751-dc5.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zcu111-reva.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── v5.1/
│ │ ├── board/
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc1751-dc3.dtsi
│ │ │ ├── zc1751-dc4.dtsi
│ │ │ ├── zc1751-dc5.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zcu111-reva.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── v5.2/
│ │ ├── board/
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc1751-dc3.dtsi
│ │ │ ├── zc1751-dc4.dtsi
│ │ │ ├── zc1751-dc5.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zcu111-reva.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ ├── v5.3/
│ │ ├── board/
│ │ │ ├── avnet-ultra96-rev1.dtsi
│ │ │ ├── zc1232-reva.dtsi
│ │ │ ├── zc1254-reva.dtsi
│ │ │ ├── zc1275-reva.dtsi
│ │ │ ├── zc1751-dc1.dtsi
│ │ │ ├── zc1751-dc2.dtsi
│ │ │ ├── zc1751-dc3.dtsi
│ │ │ ├── zc1751-dc4.dtsi
│ │ │ ├── zc1751-dc5.dtsi
│ │ │ ├── zcu100-revc.dtsi
│ │ │ ├── zcu102-rev1.0.dtsi
│ │ │ ├── zcu102-reva.dtsi
│ │ │ ├── zcu102-revb.dtsi
│ │ │ ├── zcu104-reva.dtsi
│ │ │ ├── zcu106-reva.dtsi
│ │ │ └── zcu111-reva.dtsi
│ │ └── zynqmp/
│ │ ├── zynqmp-clk.dtsi
│ │ └── zynqmp.dtsi
│ └── v5.4/
│ ├── board/
│ │ ├── avnet-ultra96-rev1.dtsi
│ │ ├── zc1232-reva.dtsi
│ │ ├── zc1254-reva.dtsi
│ │ ├── zc1275-reva.dtsi
│ │ ├── zc1751-dc1.dtsi
│ │ ├── zc1751-dc2.dtsi
│ │ ├── zc1751-dc3.dtsi
│ │ ├── zc1751-dc4.dtsi
│ │ ├── zc1751-dc5.dtsi
│ │ ├── zcu100-revc.dtsi
│ │ ├── zcu102-rev1.0.dtsi
│ │ ├── zcu102-reva.dtsi
│ │ ├── zcu102-revb.dtsi
│ │ ├── zcu104-reva.dtsi
│ │ ├── zcu106-reva.dtsi
│ │ └── zcu111-reva.dtsi
│ └── zynqmp/
│ ├── zynqmp-clk.dtsi
│ └── zynqmp.dtsi
├── dfx_axi_shutdown_manager/
│ └── data/
│ ├── dfx_axi_shutdown_manager.mdd
│ └── dfx_axi_shutdown_manager.tcl
├── dmaps/
│ └── data/
│ ├── dmaps.mdd
│ └── dmaps.tcl
├── dp/
│ └── data/
│ ├── dp.mdd
│ └── dp.tcl
├── dp_rx/
│ └── data/
│ ├── dp_rx.mdd
│ └── dp_rx.tcl
├── dp_tx/
│ └── data/
│ ├── dp_tx.mdd
│ └── dp_tx.tcl
├── dpu_eu/
│ └── data/
│ ├── dpu_eu.mdd
│ └── dpu_eu.tcl
├── emaclite/
│ └── data/
│ ├── emaclite.mdd
│ └── emaclite.tcl
├── emacps/
│ └── data/
│ ├── emacps.mdd
│ └── emacps.tcl
├── ernic/
│ └── data/
│ ├── ernic.mdd
│ └── ernic.tcl
├── framebuf_rd/
│ └── data/
│ ├── framebuf_rd.mdd
│ └── framebuf_rd.tcl
├── framebuf_wr/
│ └── data/
│ ├── framebuf_wr.mdd
│ └── framebuf_wr.tcl
├── gamma_lut/
│ └── data/
│ ├── gamma_lut.mdd
│ └── gamma_lut.tcl
├── generic/
│ └── data/
│ ├── generic.mdd
│ └── generic.tcl
├── globaltimerps/
│ └── data/
│ ├── globaltimerps.mdd
│ └── globaltimerps.tcl
├── gpiops/
│ └── data/
│ ├── gpiops.mdd
│ └── gpiops.tcl
├── hdmi_ctrl/
│ └── data/
│ ├── hdmi_ctrl.mdd
│ └── hdmi_ctrl.tcl
├── hdmi_gt_ctrl/
│ └── data/
│ ├── hdmi_gt_ctrl.mdd
│ └── hdmi_gt_ctrl.tcl
├── hdmi_rx_ss/
│ └── data/
│ ├── hdmi_rx_ss.mdd
│ └── hdmi_rx_ss.tcl
├── hdmi_tx_ss/
│ └── data/
│ ├── hdmi_tx_ss.mdd
│ └── hdmi_tx_ss.tcl
├── i2s_receiver/
│ └── data/
│ ├── i2s_receiver.mdd
│ └── i2s_receiver.tcl
├── i2s_transmitter/
│ └── data/
│ ├── i2s_transmitter.mdd
│ └── i2s_transmitter.tcl
├── i3cpsx/
│ └── data/
│ ├── i3cpsx.mdd
│ └── i3cpsx.tcl
├── iicps/
│ └── data/
│ ├── iicps.mdd
│ └── iicps.tcl
├── intc/
│ └── data/
│ ├── intc.mdd
│ └── intc.tcl
├── isppipeline/
│ └── data/
│ ├── ispipeline.mdd
│ └── ispipeline.tcl
├── mig_7series/
│ └── data/
│ ├── mig_7series.mdd
│ └── mig_7series.tcl
├── mipi_csi2_rx/
│ └── data/
│ ├── mipi_csi2_rx.mdd
│ └── mipi_csi2_rx.tcl
├── mipi_dsi_tx/
│ └── data/
│ ├── mipi_dsi_tx.mdd
│ └── mipi_dsi_tx.tcl
├── mixer/
│ └── data/
│ ├── mixer.mdd
│ └── mixer.tcl
├── mrmac/
│ └── data/
│ ├── mrmac.mdd
│ └── mrmac.tcl
├── multi_scaler/
│ └── data/
│ ├── multi_scaler.mdd
│ └── multi_scaler.tcl
├── nandps/
│ └── data/
│ ├── nandps.mdd
│ └── nandps.tcl
├── norps/
│ └── data/
│ ├── norps.mdd
│ └── norps.tcl
├── nvme_aggr/
│ └── data/
│ ├── nvme_aggr.mdd
│ └── nvme_aggr.tcl
├── ocmcps/
│ └── data/
│ ├── ocmcps.mdd
│ └── ocmcps.tcl
├── ospips/
│ └── data/
│ ├── ospips.mdd
│ └── ospips.tcl
├── pl310ps/
│ └── data/
│ ├── pl310ps.mdd
│ └── pl310ps.tcl
├── pmups/
│ └── data/
│ ├── pmups.mdd
│ └── pmups.tcl
├── pr_decoupler/
│ └── data/
│ ├── pr_decoupler.mdd
│ └── pr_decoupler.tcl
├── ptp_1588_timer_syncer/
│ └── data/
│ ├── ptp_1588_timer_syncer.mdd
│ └── ptp_1588_timer_syncer.tcl
├── qspips/
│ └── data/
│ ├── qspips.mdd
│ └── qspips.tcl
├── ramps/
│ └── data/
│ ├── ramps.mdd
│ └── ramps.tcl
├── rfdc/
│ └── data/
│ ├── rfdc.mdd
│ └── rfdc.tcl
├── scene_change_detector/
│ └── data/
│ ├── scene_change_detector.mdd
│ └── scene_change_detector.tcl
├── scugic/
│ └── data/
│ ├── scugic.mdd
│ └── scugic.tcl
├── scutimer/
│ └── data/
│ ├── scutimer.mdd
│ └── scutimer.tcl
├── scuwdt/
│ └── data/
│ ├── scuwdt.mdd
│ └── scuwdt.tcl
├── sdfec/
│ └── data/
│ ├── sdfec.mdd
│ └── sdfec.tcl
├── sdi_rx/
│ └── data/
│ ├── sdi_rx.mdd
│ └── sdi_rx.tcl
├── sdi_tx/
│ └── data/
│ ├── sdi_tx.mdd
│ └── sdi_tx.tcl
├── sdps/
│ └── data/
│ ├── sdps.mdd
│ └── sdps.tcl
├── slcrps/
│ └── data/
│ ├── slcrps.mdd
│ └── slcrps.tcl
├── smccps/
│ └── data/
│ ├── smccps.mdd
│ └── smccps.tcl
├── spips/
│ └── data/
│ ├── spips.mdd
│ └── spips.tcl
├── sync_ip/
│ └── data/
│ ├── sync_ip.mdd
│ └── sync_ip.tcl
├── sysmonpsv/
│ └── data/
│ ├── sysmonpsv.mdd
│ └── sysmonpsv.tcl
├── tmrctr/
│ └── data/
│ ├── tmrctr.mdd
│ └── tmrctr.tcl
├── tpg/
│ └── data/
│ ├── tpg.mdd
│ └── tpg.tcl
├── tsn/
│ └── data/
│ ├── tsn.mdd
│ └── tsn.tcl
├── ttcps/
│ └── data/
│ ├── ttcps.mdd
│ └── ttcps.tcl
├── uartlite/
│ └── data/
│ ├── uartlite.mdd
│ └── uartlite.tcl
├── uartns/
│ └── data/
│ ├── uartns.mdd
│ └── uartns.tcl
├── uartps/
│ └── data/
│ ├── uartps.mdd
│ └── uartps.tcl
├── usbps/
│ └── data/
│ ├── usbps.mdd
│ └── usbps.tcl
├── vid_phy_ctrl/
│ └── data/
│ ├── vid_phy_ctrl.mdd
│ └── vid_phy_ctrl.tcl
├── vproc_ss/
│ └── data/
│ ├── vproc_ss.mdd
│ └── vproc_ss.tcl
├── vtc/
│ └── data/
│ ├── vtc.mdd
│ └── vtc.tcl
├── wdtps/
│ └── data/
│ ├── wdtps.mdd
│ └── wdtps.tcl
└── xadcps/
└── data/
├── xadcps.mdd
└── xadcps.tcl
Copy disabled (too large)
Download .json
Condensed preview — 1805 files, each showing path, character count, and a content snippet. Download the .json file for the full structured content (12,820K chars).
[
{
"path": ".github/pull_request_template.md",
"chars": 237,
"preview": "Please do not submit a Pull Request via github. Our project makes use\nof mailing lists for patch submission and review. "
},
{
"path": ".gitignore",
"chars": 3,
"preview": "*~\n"
},
{
"path": "RM/data/RM.mdd",
"chars": 1092,
"preview": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "RM/data/RM.tcl",
"chars": 800,
"preview": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "ai_engine/data/ai_engine.mdd",
"chars": 813,
"preview": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "ai_engine/data/ai_engine.tcl",
"chars": 7114,
"preview": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "ams/data/ams.mdd",
"chars": 799,
"preview": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "ams/data/ams.tcl",
"chars": 1323,
"preview": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "apmps/data/apmps.mdd",
"chars": 817,
"preview": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "apmps/data/apmps.tcl",
"chars": 639,
"preview": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "audio_embed/data/audio_embed.mdd",
"chars": 876,
"preview": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "audio_embed/data/audio_embed.tcl",
"chars": 3044,
"preview": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "audio_formatter/data/audio_formatter.mdd",
"chars": 885,
"preview": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "audio_formatter/data/audio_formatter.tcl",
"chars": 1733,
"preview": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "audio_spdif/data/audio_spdif.mdd",
"chars": 817,
"preview": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "audio_spdif/data/audio_spdif.tcl",
"chars": 1908,
"preview": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_can/data/axi_can.mdd",
"chars": 891,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_can/data/axi_can.tcl",
"chars": 2337,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_cdma/data/axi_cdma.mdd",
"chars": 1009,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_cdma/data/axi_cdma.tcl",
"chars": 5707,
"preview": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C)"
},
{
"path": "axi_clk_wiz/data/axi_clk_wiz.mdd",
"chars": 1088,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_clk_wiz/data/axi_clk_wiz.tcl",
"chars": 2334,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_dma/data/axi_dma.mdd",
"chars": 1010,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n#"
},
{
"path": "axi_dma/data/axi_dma.tcl",
"chars": 12698,
"preview": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C)"
},
{
"path": "axi_emc/data/axi_emc.mdd",
"chars": 1022,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_emc/data/axi_emc.tcl",
"chars": 1485,
"preview": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C)"
},
{
"path": "axi_ethernet/data/axi_ethernet.mdd",
"chars": 1706,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n#"
},
{
"path": "axi_ethernet/data/axi_ethernet.tcl",
"chars": 37231,
"preview": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C)"
},
{
"path": "axi_gpio/data/gpio.mdd",
"chars": 1168,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_gpio/data/gpio.tcl",
"chars": 2382,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_iic/data/axi_iic.mdd",
"chars": 1130,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_iic/data/axi_iic.tcl",
"chars": 1250,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_mcdma/data/axi_mcdma.mdd",
"chars": 1008,
"preview": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n#"
},
{
"path": "axi_mcdma/data/axi_mcdma.tcl",
"chars": 9984,
"preview": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n#"
},
{
"path": "axi_pcie/data/axi_pcie.mdd",
"chars": 1244,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_pcie/data/axi_pcie.tcl",
"chars": 10683,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_perf_mon/data/axi_perf_mon.mdd",
"chars": 906,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_perf_mon/data/axi_perf_mon.tcl",
"chars": 1497,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_qspi/data/axi_qspi.mdd",
"chars": 941,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_qspi/data/axi_qspi.tcl",
"chars": 1498,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_sysace/data/axi_sysace.mdd",
"chars": 958,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_sysace/data/axi_sysace.tcl",
"chars": 640,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_tft/data/axi_tft.mdd",
"chars": 890,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_tft/data/axi_tft.tcl",
"chars": 640,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_timebase_wdt/data/axi_timebase_wdt.mdd",
"chars": 990,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_timebase_wdt/data/axi_timebase_wdt.tcl",
"chars": 1460,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_traffic_gen/data/axi_traffic_gen.mdd",
"chars": 976,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_traffic_gen/data/axi_traffic_gen.tcl",
"chars": 2468,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n#"
},
{
"path": "axi_usb2_device/data/axi_usb2_device.mdd",
"chars": 918,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_usb2_device/data/axi_usb2_device.tcl",
"chars": 1212,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_vcu/data/axi_vcu.mdd",
"chars": 803,
"preview": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_vcu/data/axi_vcu.tcl",
"chars": 6563,
"preview": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_vdma/data/axi_vdma.mdd",
"chars": 1009,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_vdma/data/axi_vdma.tcl",
"chars": 9459,
"preview": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C)"
},
{
"path": "axi_vdu/data/axi_vdu.mdd",
"chars": 803,
"preview": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_vdu/data/axi_vdu.tcl",
"chars": 8307,
"preview": "#\n# (C) Copyright 2017-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_xadc/data/axi_xadc.mdd",
"chars": 859,
"preview": "#\n# (C) Copyright 2015-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axi_xadc/data/axi_xadc.tcl",
"chars": 1972,
"preview": "#\n# (C) Copyright 2015-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axis_switch/data/axis_switch.mdd",
"chars": 819,
"preview": "#\n# (C) Copyright 2020-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "axis_switch/data/axis_switch.tcl",
"chars": 4146,
"preview": "#\n# (C) Copyright 2020-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n#\n# Th"
},
{
"path": "canfdps/data/canfdps.mdd",
"chars": 829,
"preview": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "canfdps/data/canfdps.tcl",
"chars": 639,
"preview": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "canps/data/canps.mdd",
"chars": 819,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "canps/data/canps.tcl",
"chars": 639,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "cpu/data/cpu.mdd",
"chars": 1620,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "cpu/data/cpu.tcl",
"chars": 3773,
"preview": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C)"
},
{
"path": "cpu_cortexa53/data/cpu_cortexa53.mdd",
"chars": 825,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "cpu_cortexa53/data/cpu_cortexa53.tcl",
"chars": 1271,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "cpu_cortexa72/data/cpu_cortexa72.mdd",
"chars": 825,
"preview": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "cpu_cortexa72/data/cpu_cortexa72.tcl",
"chars": 1005,
"preview": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "cpu_cortexa78/data/cpu_cortexa78.mdd",
"chars": 825,
"preview": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "cpu_cortexa78/data/cpu_cortexa78.tcl",
"chars": 1445,
"preview": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "cpu_cortexa9/data/cpu_cortexa9.mdd",
"chars": 822,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "cpu_cortexa9/data/cpu_cortexa9.tcl",
"chars": 1006,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "dccps/data/dccps.mdd",
"chars": 1020,
"preview": "# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This p"
},
{
"path": "dccps/data/dccps.tcl",
"chars": 1149,
"preview": "#\n# (C) Copyright 2020-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "ddrcps/data/ddrcps.mdd",
"chars": 824,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "ddrcps/data/ddrcps.tcl",
"chars": 639,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "ddrps/data/ddrps.mdd",
"chars": 819,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "ddrps/data/ddrps.tcl",
"chars": 7813,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "ddrpsv/data/ddrpsv.mdd",
"chars": 838,
"preview": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "ddrpsv/data/ddrpsv.tcl",
"chars": 4291,
"preview": "#\n# (C) Copyright 2019-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "debug_bridge/data/debug_bridge.mdd",
"chars": 871,
"preview": "#\n# (C) Copyright 2020-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "debug_bridge/data/debug_bridge.tcl",
"chars": 1169,
"preview": "#\n# (C) Copyright 2020-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "demosaic/data/demosaic.mdd",
"chars": 866,
"preview": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "demosaic/data/demosaic.tcl",
"chars": 7280,
"preview": "#\n# (C) Copyright 2018-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "devcfg/data/devcfg.mdd",
"chars": 808,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "devcfg/data/devcfg.tcl",
"chars": 639,
"preview": "#\n# (C) Copyright 2014-2022 Xilinx, Inc.\n# (C) Copyright 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n#\n# This"
},
{
"path": "device_tree/data/common_proc.tcl",
"chars": 290571,
"preview": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C)"
},
{
"path": "device_tree/data/device_tree.mld",
"chars": 4167,
"preview": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C)"
},
{
"path": "device_tree/data/device_tree.mss",
"chars": 889,
"preview": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C)"
},
{
"path": "device_tree/data/device_tree.tcl",
"chars": 58751,
"preview": "#\n# (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd\n# Based on original code:\n# (C) Copyright 2007-2014 Michal Simek\n# (C)"
},
{
"path": "device_tree/data/kernel_dtsi/2014.4/zynq/skeleton.dtsi",
"chars": 876,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n"
},
{
"path": "device_tree/data/kernel_dtsi/2014.4/zynq/zynq-7000.dtsi",
"chars": 10254,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n *"
},
{
"path": "device_tree/data/kernel_dtsi/2015.1/zynq/skeleton.dtsi",
"chars": 875,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n"
},
{
"path": "device_tree/data/kernel_dtsi/2015.1/zynq/zynq-7000.dtsi",
"chars": 10204,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n *"
},
{
"path": "device_tree/data/kernel_dtsi/2015.2/zynq/skeleton.dtsi",
"chars": 875,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n"
},
{
"path": "device_tree/data/kernel_dtsi/2015.2/zynq/zynq-7000.dtsi",
"chars": 10035,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n *"
},
{
"path": "device_tree/data/kernel_dtsi/2015.3/zynq/skeleton.dtsi",
"chars": 876,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n"
},
{
"path": "device_tree/data/kernel_dtsi/2015.3/zynq/zynq-7000.dtsi",
"chars": 10214,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n *"
},
{
"path": "device_tree/data/kernel_dtsi/2015.4/zynq/skeleton.dtsi",
"chars": 876,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n"
},
{
"path": "device_tree/data/kernel_dtsi/2015.4/zynq/zynq-7000.dtsi",
"chars": 10266,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n *"
},
{
"path": "device_tree/data/kernel_dtsi/2015.4/zynqmp/zynqmp-clk.dtsi",
"chars": 2538,
"preview": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Mi"
},
{
"path": "device_tree/data/kernel_dtsi/2015.4/zynqmp/zynqmp.dtsi",
"chars": 16351,
"preview": "/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices"
},
{
"path": "device_tree/data/kernel_dtsi/2016.1/zynq/skeleton.dtsi",
"chars": 875,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n"
},
{
"path": "device_tree/data/kernel_dtsi/2016.1/zynq/zynq-7000.dtsi",
"chars": 10389,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n *"
},
{
"path": "device_tree/data/kernel_dtsi/2016.1/zynqmp/zynqmp-clk.dtsi",
"chars": 3120,
"preview": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Mi"
},
{
"path": "device_tree/data/kernel_dtsi/2016.1/zynqmp/zynqmp.dtsi",
"chars": 22275,
"preview": "/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices"
},
{
"path": "device_tree/data/kernel_dtsi/2016.2/zynq/skeleton.dtsi",
"chars": 875,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n"
},
{
"path": "device_tree/data/kernel_dtsi/2016.2/zynq/zynq-7000.dtsi",
"chars": 10389,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n *"
},
{
"path": "device_tree/data/kernel_dtsi/2016.2/zynqmp/zynqmp-clk.dtsi",
"chars": 3120,
"preview": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Mi"
},
{
"path": "device_tree/data/kernel_dtsi/2016.2/zynqmp/zynqmp.dtsi",
"chars": 24564,
"preview": "/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices"
},
{
"path": "device_tree/data/kernel_dtsi/2016.3/zynq/skeleton.dtsi",
"chars": 875,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n"
},
{
"path": "device_tree/data/kernel_dtsi/2016.3/zynq/zynq-7000.dtsi",
"chars": 10530,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n *"
},
{
"path": "device_tree/data/kernel_dtsi/2016.3/zynqmp/zynqmp-clk.dtsi",
"chars": 3120,
"preview": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Mi"
},
{
"path": "device_tree/data/kernel_dtsi/2016.3/zynqmp/zynqmp.dtsi",
"chars": 24726,
"preview": "/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices"
},
{
"path": "device_tree/data/kernel_dtsi/2016.4/zynq/skeleton.dtsi",
"chars": 875,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n"
},
{
"path": "device_tree/data/kernel_dtsi/2016.4/zynq/zynq-7000.dtsi",
"chars": 10574,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n *"
},
{
"path": "device_tree/data/kernel_dtsi/2016.4/zynqmp/zynqmp-clk.dtsi",
"chars": 3583,
"preview": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Mi"
},
{
"path": "device_tree/data/kernel_dtsi/2016.4/zynqmp/zynqmp.dtsi",
"chars": 25710,
"preview": "/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices"
},
{
"path": "device_tree/data/kernel_dtsi/2017.1/BOARD/ac701-full.dtsi",
"chars": 1066,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xili"
},
{
"path": "device_tree/data/kernel_dtsi/2017.1/BOARD/ac701-lite.dtsi",
"chars": 1051,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xili"
},
{
"path": "device_tree/data/kernel_dtsi/2017.1/BOARD/kc705-full.dtsi",
"chars": 1098,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xili"
},
{
"path": "device_tree/data/kernel_dtsi/2017.1/BOARD/kc705-lite.dtsi",
"chars": 1059,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xili"
},
{
"path": "device_tree/data/kernel_dtsi/2017.1/BOARD/kcu105.dtsi",
"chars": 619,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\ni * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx,"
},
{
"path": "device_tree/data/kernel_dtsi/2017.1/BOARD/zc1751-dc1.dtsi",
"chars": 6435,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xil"
},
{
"path": "device_tree/data/kernel_dtsi/2017.1/BOARD/zc1751-dc2.dtsi",
"chars": 8355,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xil"
},
{
"path": "device_tree/data/kernel_dtsi/2017.1/BOARD/zc702.dtsi",
"chars": 7373,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micr"
},
{
"path": "device_tree/data/kernel_dtsi/2017.1/BOARD/zc706.dtsi",
"chars": 5776,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Dev"
},
{
"path": "device_tree/data/kernel_dtsi/2017.1/BOARD/zcu102-revb.dtsi",
"chars": 16452,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, "
},
{
"path": "device_tree/data/kernel_dtsi/2017.1/BOARD/zcu102.dtsi",
"chars": 16490,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n"
},
{
"path": "device_tree/data/kernel_dtsi/2017.1/BOARD/zcu106.dtsi",
"chars": 15908,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n"
},
{
"path": "device_tree/data/kernel_dtsi/2017.1/BOARD/zedboard.dtsi",
"chars": 1452,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micr"
},
{
"path": "device_tree/data/kernel_dtsi/2017.1/zynq/skeleton.dtsi",
"chars": 875,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n"
},
{
"path": "device_tree/data/kernel_dtsi/2017.1/zynq/zynq-7000.dtsi",
"chars": 10759,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n *"
},
{
"path": "device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp-clk-ccf.dtsi",
"chars": 5367,
"preview": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Mi"
},
{
"path": "device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp-clk.dtsi",
"chars": 3606,
"preview": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Mi"
},
{
"path": "device_tree/data/kernel_dtsi/2017.1/zynqmp/zynqmp.dtsi",
"chars": 27661,
"preview": "/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices"
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/BOARD/ac701-full.dtsi",
"chars": 1051,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xili"
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/BOARD/ac701-lite.dtsi",
"chars": 1051,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xili"
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/BOARD/kc705-full.dtsi",
"chars": 1098,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xili"
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/BOARD/kc705-lite.dtsi",
"chars": 1059,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xili"
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/BOARD/kcu105.dtsi",
"chars": 618,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, "
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zc1751-dc1.dtsi",
"chars": 6435,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xil"
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zc1751-dc2.dtsi",
"chars": 8355,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xil"
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zc702.dtsi",
"chars": 7373,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micr"
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zc706.dtsi",
"chars": 5780,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micr"
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zcu100-reva.dtsi",
"chars": 8502,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, "
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zcu100-revb.dtsi",
"chars": 12436,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevB\n *\n * (C) Copyright 2015-2022 Xilinx, "
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zcu102-revb.dtsi",
"chars": 16452,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, "
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zcu102.dtsi",
"chars": 16490,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n"
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zcu106.dtsi",
"chars": 15908,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n"
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/BOARD/zedboard.dtsi",
"chars": 1452,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micr"
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/zynq/skeleton.dtsi",
"chars": 875,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n"
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/zynq/zynq-7000.dtsi",
"chars": 10759,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n *"
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp-clk-ccf.dtsi",
"chars": 5367,
"preview": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Mi"
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp-clk.dtsi",
"chars": 3606,
"preview": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Mi"
},
{
"path": "device_tree/data/kernel_dtsi/2017.2/zynqmp/zynqmp.dtsi",
"chars": 27661,
"preview": "/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices"
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/ac701-full.dtsi",
"chars": 1051,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xili"
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/ac701-lite.dtsi",
"chars": 1051,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xili"
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/kc705-full.dtsi",
"chars": 1098,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xili"
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/kc705-lite.dtsi",
"chars": 1059,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xili"
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/kcu105.dtsi",
"chars": 618,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, "
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zc1232-reva.dtsi",
"chars": 1853,
"preview": "/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro "
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zc1254-reva.dtsi",
"chars": 1153,
"preview": "/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro "
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zc1275-reva.dtsi",
"chars": 1153,
"preview": "/*\n * dts file for Xilinx ZynqMP ZC1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro "
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zc1751-dc1.dtsi",
"chars": 6396,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xil"
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zc1751-dc2.dtsi",
"chars": 8341,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm016-dc2\n *\n * (C) Copyright 2015-2022 Xil"
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zc702.dtsi",
"chars": 7373,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micr"
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zc706.dtsi",
"chars": 5780,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micr"
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zcu100-reva.dtsi",
"chars": 8502,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, "
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zcu100-revb.dtsi",
"chars": 10170,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevB\n *\n * (C) Copyright 2015-2022 Xilinx, "
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zcu100-revc.dtsi",
"chars": 10366,
"preview": "/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced M"
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zcu102-rev1.0.dtsi",
"chars": 16291,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, I"
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zcu102-reva.dtsi",
"chars": 16092,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, "
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zcu102-revb.dtsi",
"chars": 16009,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 RevB\n *\n * (C) Copyright 2016-2022 Xilinx, "
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zcu104-reva.dtsi",
"chars": 8030,
"preview": "/*\n * dts file for Xilinx ZynqMP ZCU104\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro "
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zcu106-reva.dtsi",
"chars": 15946,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU106\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n"
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/BOARD/zedboard.dtsi",
"chars": 1452,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2017-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micr"
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/zynq/skeleton.dtsi",
"chars": 876,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.\n"
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/zynq/zynq-7000.dtsi",
"chars": 10759,
"preview": "/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022 Advanced Micro Devices, Inc. All Rights Reserved.\n *\n *"
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp-clk-ccf.dtsi",
"chars": 5368,
"preview": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Mi"
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp-clk.dtsi",
"chars": 3606,
"preview": "/*\n * Clock specification for Xilinx ZynqMP\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Mi"
},
{
"path": "device_tree/data/kernel_dtsi/2017.3/zynqmp/zynqmp.dtsi",
"chars": 28325,
"preview": "/*\n * dts file for Xilinx ZynqMP\n *\n * (C) Copyright 2014-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro Devices"
},
{
"path": "device_tree/data/kernel_dtsi/2017.4/BOARD/ac701-full.dtsi",
"chars": 1051,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-full.\n *\n * (C) Copyright 2017-2022 Xili"
},
{
"path": "device_tree/data/kernel_dtsi/2017.4/BOARD/ac701-lite.dtsi",
"chars": 1051,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze ac701-lite.\n *\n * (C) Copyright 2017-2022 Xili"
},
{
"path": "device_tree/data/kernel_dtsi/2017.4/BOARD/kc705-full.dtsi",
"chars": 1098,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-full.\n *\n * (C) Copyright 2017-2022 Xili"
},
{
"path": "device_tree/data/kernel_dtsi/2017.4/BOARD/kc705-lite.dtsi",
"chars": 1059,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kc705-lite.\n *\n * (C) Copyright 2017-2022 Xili"
},
{
"path": "device_tree/data/kernel_dtsi/2017.4/BOARD/kcu105.dtsi",
"chars": 618,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx Microblaze kcu105.\n *\n * (C) Copyright 2017-2022 Xilinx, "
},
{
"path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zc1232-reva.dtsi",
"chars": 1853,
"preview": "/*\n * dts file for Xilinx ZynqMP ZC1232\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro "
},
{
"path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zc1254-reva.dtsi",
"chars": 1153,
"preview": "/*\n * dts file for Xilinx ZynqMP ZC1254\n *\n * (C) Copyright 2015-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro "
},
{
"path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zc1275-reva.dtsi",
"chars": 1153,
"preview": "/*\n * dts file for Xilinx ZynqMP ZC1275\n *\n * (C) Copyright 2017-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced Micro "
},
{
"path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zc1751-dc1.dtsi",
"chars": 5860,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP zc1751-xm015-dc1\n *\n * (C) Copyright 2015-2022 Xil"
},
{
"path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zc1751-dc2.dtsi",
"chars": 7548,
"preview": "/ {\n\tmodel = \"ZynqMP zc1751-xm016-dc2 RevA\";\n\tcompatible = \"xlnx,zynqmp-zc1751\", \"xlnx,zynqmp\";\n};\n\n&can0 {\n\tpinctrl-nam"
},
{
"path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zc702.dtsi",
"chars": 7373,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micr"
},
{
"path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zc706.dtsi",
"chars": 5780,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * Copyright (C) 2011-2022 Xilinx, Inc.\n * Copyright (C) 2022-2023 Advanced Micr"
},
{
"path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zcu100-reva.dtsi",
"chars": 8502,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevA\n *\n * (C) Copyright 2015-2022 Xilinx, "
},
{
"path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zcu100-revb.dtsi",
"chars": 10170,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU100 RevB\n *\n * (C) Copyright 2015-2022 Xilinx, "
},
{
"path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zcu100-revc.dtsi",
"chars": 10366,
"preview": "/*\n * dts file for Xilinx ZynqMP ZCU100 revC\n *\n * (C) Copyright 2016-2022 Xilinx, Inc.\n * (C) Copyright 2022 Advanced M"
},
{
"path": "device_tree/data/kernel_dtsi/2017.4/BOARD/zcu102-rev1.0.dtsi",
"chars": 15750,
"preview": "// SPDX-License-Identifier: GPL-2.0+\n/*\n * dts file for Xilinx ZynqMP ZCU102 Rev1.0\n * (C) Copyright 2016-2022 Xilinx, I"
}
]
// ... and 1605 more files (download for full content)
About this extraction
This page contains the full source code of the Xilinx/device-tree-xlnx GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 1805 files (10.5 MB), approximately 2.9M tokens. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.
Extracted by GitExtract — free GitHub repo to text converter for AI. Built by Nikandr Surkov.