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Repository: daveshah1/CSI2Rx
Branch: master
Commit: 582f870d3140
Files: 350
Total size: 52.1 MB
Directory structure:
gitextract_o_fqoapy/
├── LICENSE
├── README.md
├── misc/
│ └── caminit/
│ ├── .gitignore
│ └── picam_init.cc
├── verilog_cores/
│ ├── .gitignore
│ ├── Makefile
│ ├── README.md
│ ├── csi/
│ │ ├── header_ecc.v
│ │ └── rx_packet_handler.v
│ ├── csi2.core
│ ├── link/
│ │ └── csi_rx_ice40.v
│ ├── misc/
│ │ └── downsample.v
│ ├── phy/
│ │ ├── byte_aligner.v
│ │ ├── dphy_iserdes.v
│ │ ├── dphy_oserdes.v
│ │ └── word_combiner.v
│ └── test/
│ └── icebreaker/
│ ├── .gitignore
│ ├── Makefile
│ ├── constraints.py
│ ├── icecam.pcf
│ ├── top.v
│ └── uart.v
└── vhdl_rx/
├── .gitignore
├── LICENSE.notes
├── README.md
├── demo-top/
│ ├── framebuffer_top.vhd
│ ├── mig_a.prj
│ └── ov13850_demo.vhd
├── dvi-tx/
│ ├── dvi_tx_clk_drv.vhd
│ ├── dvi_tx_tmds_enc.vhd
│ ├── dvi_tx_tmds_phy.vhd
│ └── dvi_tx_top.vhd
├── examples/
│ ├── .gitignore
│ └── ov13850_demo/
│ ├── ov13850_demo.cache/
│ │ └── ip/
│ │ ├── 54144841a4506c29/
│ │ │ ├── 54144841a4506c29.xci
│ │ │ ├── dvi_pll_sim_netlist.v
│ │ │ └── dvi_pll_stub.v
│ │ ├── 548aa35948ad692b/
│ │ │ ├── 548aa35948ad692b.xci
│ │ │ ├── camera_pll_sim_netlist.v
│ │ │ └── camera_pll_stub.v
│ │ └── 75280199e9655e6a/
│ │ ├── 75280199e9655e6a.xci
│ │ ├── dvi_pll_sim_netlist.v
│ │ └── dvi_pll_stub.v
│ ├── ov13850_demo.ip_user_files/
│ │ ├── ip/
│ │ │ ├── camera_pll/
│ │ │ │ └── camera_pll_stub.v
│ │ │ ├── ddr3_if/
│ │ │ │ └── ddr3_if_stub.v
│ │ │ ├── dvi_pll/
│ │ │ │ └── dvi_pll_stub.v
│ │ │ ├── ila_0/
│ │ │ │ └── ila_0_stub.v
│ │ │ ├── input_line_buffer/
│ │ │ │ └── input_line_buffer_stub.v
│ │ │ └── output_line_buffer/
│ │ │ └── output_line_buffer_stub.v
│ │ ├── ipstatic/
│ │ │ ├── hdl/
│ │ │ │ ├── fifo_generator_v13_1_rfs.v
│ │ │ │ └── fifo_generator_v13_1_rfs.vhd
│ │ │ └── simulation/
│ │ │ ├── blk_mem_gen_v8_3.v
│ │ │ └── fifo_generator_vlog_beh.v
│ │ ├── mem_init_files/
│ │ │ ├── mig_a.prj
│ │ │ └── mig_b.prj
│ │ └── sim_scripts/
│ │ ├── camera_pll_1/
│ │ │ ├── activehdl/
│ │ │ │ └── glbl.v
│ │ │ ├── ies/
│ │ │ │ └── glbl.v
│ │ │ ├── modelsim/
│ │ │ │ └── glbl.v
│ │ │ ├── questa/
│ │ │ │ └── glbl.v
│ │ │ ├── riviera/
│ │ │ │ └── glbl.v
│ │ │ ├── vcs/
│ │ │ │ └── glbl.v
│ │ │ └── xsim/
│ │ │ ├── cmd.tcl
│ │ │ ├── glbl.v
│ │ │ └── vlog.prj
│ │ ├── ddr3_if/
│ │ │ ├── activehdl/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_b.prj
│ │ │ ├── ies/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_b.prj
│ │ │ ├── modelsim/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_b.prj
│ │ │ ├── questa/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_b.prj
│ │ │ ├── riviera/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_b.prj
│ │ │ ├── vcs/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_b.prj
│ │ │ └── xsim/
│ │ │ ├── cmd.tcl
│ │ │ ├── glbl.v
│ │ │ ├── mig_b.prj
│ │ │ └── vlog.prj
│ │ ├── ddr3_if_1/
│ │ │ ├── activehdl/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_a.prj
│ │ │ ├── ies/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_a.prj
│ │ │ ├── modelsim/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_a.prj
│ │ │ ├── questa/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_a.prj
│ │ │ ├── riviera/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_a.prj
│ │ │ ├── vcs/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_a.prj
│ │ │ └── xsim/
│ │ │ ├── cmd.tcl
│ │ │ ├── glbl.v
│ │ │ ├── mig_a.prj
│ │ │ └── vlog.prj
│ │ ├── dvi_pll_1/
│ │ │ ├── activehdl/
│ │ │ │ └── glbl.v
│ │ │ ├── ies/
│ │ │ │ └── glbl.v
│ │ │ ├── modelsim/
│ │ │ │ └── glbl.v
│ │ │ ├── questa/
│ │ │ │ └── glbl.v
│ │ │ ├── riviera/
│ │ │ │ └── glbl.v
│ │ │ ├── vcs/
│ │ │ │ └── glbl.v
│ │ │ └── xsim/
│ │ │ ├── cmd.tcl
│ │ │ ├── glbl.v
│ │ │ └── vlog.prj
│ │ ├── framebuffer-ctrl/
│ │ │ ├── activehdl/
│ │ │ │ └── glbl.v
│ │ │ ├── ies/
│ │ │ │ └── glbl.v
│ │ │ ├── modelsim/
│ │ │ │ └── glbl.v
│ │ │ ├── questa/
│ │ │ │ └── glbl.v
│ │ │ ├── riviera/
│ │ │ │ └── glbl.v
│ │ │ └── vcs/
│ │ │ └── glbl.v
│ │ ├── ila_0/
│ │ │ ├── activehdl/
│ │ │ │ └── glbl.v
│ │ │ ├── ies/
│ │ │ │ └── glbl.v
│ │ │ ├── modelsim/
│ │ │ │ └── glbl.v
│ │ │ ├── questa/
│ │ │ │ └── glbl.v
│ │ │ ├── riviera/
│ │ │ │ └── glbl.v
│ │ │ ├── vcs/
│ │ │ │ └── glbl.v
│ │ │ └── xsim/
│ │ │ ├── cmd.tcl
│ │ │ ├── glbl.v
│ │ │ └── vlog.prj
│ │ ├── input_line_buffer/
│ │ │ ├── activehdl/
│ │ │ │ └── glbl.v
│ │ │ ├── ies/
│ │ │ │ └── glbl.v
│ │ │ ├── modelsim/
│ │ │ │ └── glbl.v
│ │ │ ├── questa/
│ │ │ │ └── glbl.v
│ │ │ ├── riviera/
│ │ │ │ └── glbl.v
│ │ │ ├── vcs/
│ │ │ │ └── glbl.v
│ │ │ └── xsim/
│ │ │ ├── cmd.tcl
│ │ │ ├── glbl.v
│ │ │ └── vlog.prj
│ │ ├── input_line_buffer_1/
│ │ │ ├── activehdl/
│ │ │ │ └── glbl.v
│ │ │ ├── ies/
│ │ │ │ └── glbl.v
│ │ │ ├── modelsim/
│ │ │ │ └── glbl.v
│ │ │ ├── questa/
│ │ │ │ └── glbl.v
│ │ │ ├── riviera/
│ │ │ │ └── glbl.v
│ │ │ ├── vcs/
│ │ │ │ └── glbl.v
│ │ │ └── xsim/
│ │ │ ├── cmd.tcl
│ │ │ ├── glbl.v
│ │ │ └── vlog.prj
│ │ ├── output_line_buffer/
│ │ │ ├── activehdl/
│ │ │ │ └── glbl.v
│ │ │ ├── ies/
│ │ │ │ └── glbl.v
│ │ │ ├── modelsim/
│ │ │ │ └── glbl.v
│ │ │ ├── questa/
│ │ │ │ └── glbl.v
│ │ │ ├── riviera/
│ │ │ │ └── glbl.v
│ │ │ ├── vcs/
│ │ │ │ └── glbl.v
│ │ │ └── xsim/
│ │ │ ├── cmd.tcl
│ │ │ ├── glbl.v
│ │ │ └── vlog.prj
│ │ └── output_line_buffer_1/
│ │ ├── activehdl/
│ │ │ └── glbl.v
│ │ ├── ies/
│ │ │ └── glbl.v
│ │ ├── modelsim/
│ │ │ └── glbl.v
│ │ ├── questa/
│ │ │ └── glbl.v
│ │ ├── riviera/
│ │ │ └── glbl.v
│ │ ├── vcs/
│ │ │ └── glbl.v
│ │ └── xsim/
│ │ ├── cmd.tcl
│ │ ├── glbl.v
│ │ └── vlog.prj
│ ├── ov13850_demo.runs/
│ │ ├── camera_pll_synth_1/
│ │ │ ├── camera_pll.tcl
│ │ │ └── dont_touch.xdc
│ │ ├── ddr3_if_synth_1/
│ │ │ └── ddr3_if.tcl
│ │ ├── dvi_pll_synth_1/
│ │ │ ├── dont_touch.xdc
│ │ │ └── dvi_pll.tcl
│ │ ├── impl_1/
│ │ │ └── ov13850_demo.tcl
│ │ ├── input_line_buffer_synth_1/
│ │ │ ├── dont_touch.xdc
│ │ │ ├── input_line_buffer.tcl
│ │ │ ├── input_line_buffer_sim_netlist.v
│ │ │ └── input_line_buffer_stub.v
│ │ ├── output_line_buffer_synth_1/
│ │ │ ├── dont_touch.xdc
│ │ │ ├── output_line_buffer.tcl
│ │ │ ├── output_line_buffer_sim_netlist.v
│ │ │ └── output_line_buffer_stub.v
│ │ └── synth_1/
│ │ ├── .Xil/
│ │ │ └── ov13850_demo_propImpl.xdc
│ │ └── ov13850_demo.tcl
│ ├── ov13850_demo.sim/
│ │ └── sim_1/
│ │ └── synth/
│ │ └── func/
│ │ ├── genesys2_fbtest.tcl
│ │ ├── genesys2_fbtest_func_synth.v
│ │ └── genesys2_fbtest_vlog.prj
│ ├── ov13850_demo.srcs/
│ │ ├── constrs_1/
│ │ │ └── imports/
│ │ │ ├── constraints/
│ │ │ │ └── ddr3_if.xdc
│ │ │ └── new/
│ │ │ └── genesys2.xdc
│ │ └── sources_1/
│ │ └── ip/
│ │ ├── camera_pll_1/
│ │ │ ├── camera_pll.v
│ │ │ ├── camera_pll.xci
│ │ │ ├── camera_pll.xdc
│ │ │ ├── camera_pll_board.xdc
│ │ │ ├── camera_pll_clk_wiz.v
│ │ │ ├── camera_pll_ooc.xdc
│ │ │ ├── camera_pll_sim_netlist.v
│ │ │ └── camera_pll_stub.v
│ │ ├── ddr3_if/
│ │ │ ├── mig_a.prj
│ │ │ └── mig_b.prj
│ │ ├── ddr3_if_1/
│ │ │ ├── ddr3_if/
│ │ │ │ └── user_design/
│ │ │ │ ├── constraints/
│ │ │ │ │ ├── ddr3_if.xdc
│ │ │ │ │ └── ddr3_if_ooc.xdc
│ │ │ │ └── rtl/
│ │ │ │ ├── axi/
│ │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_addr_decode.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_read.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_reg.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_reg_bank.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_top.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_write.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_ar_channel.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_aw_channel.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_b_channel.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_cmd_arbiter.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_cmd_fsm.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_cmd_translator.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_fifo.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_incr_cmd.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_r_channel.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_simple_fifo.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_w_channel.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_wr_cmd_fsm.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_wrap_cmd.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_a_upsizer.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_axi_register_slice.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_axi_upsizer.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_axic_register_slice.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_carry_and.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_carry_latch_and.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_carry_latch_or.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_carry_or.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_command_fifo.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_comparator.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_comparator_sel.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_comparator_sel_static.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_r_upsizer.v
│ │ │ │ │ └── mig_7series_v4_0_ddr_w_upsizer.v
│ │ │ │ ├── clocking/
│ │ │ │ │ ├── mig_7series_v4_0_clk_ibuf.v
│ │ │ │ │ ├── mig_7series_v4_0_infrastructure.v
│ │ │ │ │ ├── mig_7series_v4_0_iodelay_ctrl.v
│ │ │ │ │ └── mig_7series_v4_0_tempmon.v
│ │ │ │ ├── controller/
│ │ │ │ │ ├── mig_7series_v4_0_arb_mux.v
│ │ │ │ │ ├── mig_7series_v4_0_arb_row_col.v
│ │ │ │ │ ├── mig_7series_v4_0_arb_select.v
│ │ │ │ │ ├── mig_7series_v4_0_bank_cntrl.v
│ │ │ │ │ ├── mig_7series_v4_0_bank_common.v
│ │ │ │ │ ├── mig_7series_v4_0_bank_compare.v
│ │ │ │ │ ├── mig_7series_v4_0_bank_mach.v
│ │ │ │ │ ├── mig_7series_v4_0_bank_queue.v
│ │ │ │ │ ├── mig_7series_v4_0_bank_state.v
│ │ │ │ │ ├── mig_7series_v4_0_col_mach.v
│ │ │ │ │ ├── mig_7series_v4_0_mc.v
│ │ │ │ │ ├── mig_7series_v4_0_rank_cntrl.v
│ │ │ │ │ ├── mig_7series_v4_0_rank_common.v
│ │ │ │ │ ├── mig_7series_v4_0_rank_mach.v
│ │ │ │ │ └── mig_7series_v4_0_round_robin_arb.v
│ │ │ │ ├── ddr3_if.v
│ │ │ │ ├── ddr3_if_mig.v
│ │ │ │ ├── ddr3_if_mig_sim.v
│ │ │ │ ├── ecc/
│ │ │ │ │ ├── mig_7series_v4_0_ecc_buf.v
│ │ │ │ │ ├── mig_7series_v4_0_ecc_dec_fix.v
│ │ │ │ │ ├── mig_7series_v4_0_ecc_gen.v
│ │ │ │ │ ├── mig_7series_v4_0_ecc_merge_enc.v
│ │ │ │ │ └── mig_7series_v4_0_fi_xor.v
│ │ │ │ ├── ip_top/
│ │ │ │ │ ├── mig_7series_v4_0_mem_intfc.v
│ │ │ │ │ └── mig_7series_v4_0_memc_ui_top_axi.v
│ │ │ │ ├── phy/
│ │ │ │ │ ├── mig_7series_v4_0_ddr_byte_group_io.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_byte_lane.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_calib_top.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_if_post_fifo.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_mc_phy.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_mc_phy_wrapper.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_of_pre_fifo.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_4lanes.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_dqs_found_cal.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_dqs_found_cal_hr.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_init.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_cntlr.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_data.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_edge.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_lim.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_mux.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_samp.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_oclkdelay_cal.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_prbs_rdlvl.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_rdlvl.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_tempmon.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_top.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_wrcal.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_wrlvl.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_wrlvl_off_delay.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_prbs_gen.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_skip_calib_tap.v
│ │ │ │ │ ├── mig_7series_v4_0_poc_cc.v
│ │ │ │ │ ├── mig_7series_v4_0_poc_edge_store.v
│ │ │ │ │ ├── mig_7series_v4_0_poc_meta.v
│ │ │ │ │ ├── mig_7series_v4_0_poc_pd.v
│ │ │ │ │ ├── mig_7series_v4_0_poc_tap_base.v
│ │ │ │ │ └── mig_7series_v4_0_poc_top.v
│ │ │ │ └── ui/
│ │ │ │ ├── mig_7series_v4_0_ui_cmd.v
│ │ │ │ ├── mig_7series_v4_0_ui_rd_data.v
│ │ │ │ ├── mig_7series_v4_0_ui_top.v
│ │ │ │ └── mig_7series_v4_0_ui_wr_data.v
│ │ │ ├── ddr3_if.xci
│ │ │ ├── ddr3_if_sim_netlist.v
│ │ │ ├── ddr3_if_stub.v
│ │ │ └── mig_a.prj
│ │ ├── dvi_pll_1/
│ │ │ ├── dvi_pll.v
│ │ │ ├── dvi_pll.xci
│ │ │ ├── dvi_pll.xdc
│ │ │ ├── dvi_pll_board.xdc
│ │ │ ├── dvi_pll_clk_wiz.v
│ │ │ ├── dvi_pll_ooc.xdc
│ │ │ ├── dvi_pll_sim_netlist.v
│ │ │ └── dvi_pll_stub.v
│ │ ├── input_line_buffer_1/
│ │ │ ├── hdl/
│ │ │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd
│ │ │ ├── input_line_buffer.xci
│ │ │ ├── input_line_buffer_ooc.xdc
│ │ │ ├── input_line_buffer_sim_netlist.v
│ │ │ ├── input_line_buffer_stub.v
│ │ │ ├── misc/
│ │ │ │ └── blk_mem_gen_v8_3.vhd
│ │ │ ├── sim/
│ │ │ │ └── input_line_buffer.v
│ │ │ ├── simulation/
│ │ │ │ └── blk_mem_gen_v8_3.v
│ │ │ └── synth/
│ │ │ └── input_line_buffer.vhd
│ │ └── output_line_buffer_1/
│ │ ├── hdl/
│ │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd
│ │ ├── misc/
│ │ │ └── blk_mem_gen_v8_3.vhd
│ │ ├── output_line_buffer.xci
│ │ ├── output_line_buffer_ooc.xdc
│ │ ├── output_line_buffer_sim_netlist.v
│ │ ├── output_line_buffer_stub.v
│ │ ├── sim/
│ │ │ └── output_line_buffer.v
│ │ ├── simulation/
│ │ │ └── blk_mem_gen_v8_3.v
│ │ └── synth/
│ │ └── output_line_buffer.vhd
│ └── ov13850_demo.xpr
├── framebuffer-ctrl/
│ ├── framebuffer_ctrl.vhd
│ ├── input_line_buffer.xci
│ └── output_line_buffer.xci
├── mipi-csi-rx/
│ ├── csi_rx_10bit_unpack.vhd
│ ├── csi_rx_4_lane_link.vhd
│ ├── csi_rx_byte_align.vhd
│ ├── csi_rx_clock_det.vhd
│ ├── csi_rx_hdr_ecc.vhd
│ ├── csi_rx_hs_clk_phy.vhd
│ ├── csi_rx_hs_lane_phy.vhd
│ ├── csi_rx_idelayctrl_gen.vhd
│ ├── csi_rx_line_buffer.vhd
│ ├── csi_rx_packet_handler.vhd
│ ├── csi_rx_top.vhd
│ ├── csi_rx_video_output.vhd
│ ├── csi_rx_word_align.vhd
│ └── synth.ys
├── ov-cam-control/
│ ├── manual_focus.vhd
│ ├── ov13850_4k_regs.vhd
│ ├── ov13850_control_top.vhd
│ ├── ov16825_1080p120_regs.vhd
│ ├── ov_i2c_control.vhd
│ └── vcm_i2c_control.vhd
└── video-misc/
├── image_gain_wb.vhd
├── simple_debayer.vhd
├── test_pattern_gen.vhd
├── video_fb_output.vhd
├── video_register.vhd
└── video_timing_ctrl.vhd
================================================
FILE CONTENTS
================================================
================================================
FILE: LICENSE
================================================
MIT License
Copyright (c) 2016-2018 David Shah <dave@ds0.me>
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
================================================
FILE: README.md
================================================
# MIPI CSI-2 IP Cores
The _vhdl\_rx_ folder contains a tried-and-tested high performance CSI-2 receiver core in VHDL. This can handle 4k video at over 30fps (most likely 60fps with a suitable camera module). This has been tested with the OV13850 camera module with a Xilinx Kintex-7 FPGA. It is currently limited to a 4-lane and 10bpp without modification, other parameters such as timing can be modified at compile time. Also in this folder are an example project and some miscellaneous VHDL support IP such as an AXI-4 framebuffer controller.
The _verilog\_cores_ contains work-in-progress CSI-2 transmit and receive cores in Verilog. These are designed to be more flexible and run on a variety of platforms. The first target will be 640x480 video using a Raspberry Pi camera with an iCE40 FPGA.
All cores are licensed under the MIT License, see LICENSE for details.
================================================
FILE: misc/caminit/.gitignore
================================================
/caminit
================================================
FILE: misc/caminit/picam_init.cc
================================================
// Simple I2C using MPSSE bitbang implementation (passed thru FPGA) to initialise a PiCam2
// Some code taken from iceprog
#include <ftdi.h>
#include <stdint.h>
#include <stdio.h>
static struct ftdi_context ftdic;
static bool ftdic_open = false;
static bool verbose = false;
static bool ftdic_latency_set = false;
static unsigned char ftdi_latency;
/* MPSSE engine command definitions */
enum mpsse_cmd
{
/* Mode commands */
MC_SETB_LOW = 0x80, /* Set Data bits LowByte */
MC_READB_LOW = 0x81, /* Read Data bits LowByte */
MC_SETB_HIGH = 0x82, /* Set Data bits HighByte */
MC_READB_HIGH = 0x83, /* Read data bits HighByte */
MC_LOOPBACK_EN = 0x84, /* Enable loopback */
MC_LOOPBACK_DIS = 0x85, /* Disable loopback */
MC_SET_CLK_DIV = 0x86, /* Set clock divisor */
MC_FLUSH = 0x87, /* Flush buffer fifos to the PC. */
MC_WAIT_H = 0x88, /* Wait on GPIOL1 to go high. */
MC_WAIT_L = 0x89, /* Wait on GPIOL1 to go low. */
MC_TCK_X5 = 0x8A, /* Disable /5 div, enables 60MHz master clock */
MC_TCK_D5 = 0x8B, /* Enable /5 div, backward compat to FT2232D */
MC_EN_3PH_CLK = 0x8C, /* Enable 3 phase clk, DDR I2C */
MC_DIS_3PH_CLK = 0x8D, /* Disable 3 phase clk */
MC_CLK_N = 0x8E, /* Clock every bit, used for JTAG */
MC_CLK_N8 = 0x8F, /* Clock every byte, used for JTAG */
MC_CLK_TO_H = 0x94, /* Clock until GPIOL1 goes high */
MC_CLK_TO_L = 0x95, /* Clock until GPIOL1 goes low */
MC_EN_ADPT_CLK = 0x96, /* Enable adaptive clocking */
MC_DIS_ADPT_CLK = 0x97, /* Disable adaptive clocking */
MC_CLK8_TO_H = 0x9C, /* Clock until GPIOL1 goes high, count bytes */
MC_CLK8_TO_L = 0x9D, /* Clock until GPIOL1 goes low, count bytes */
MC_TRI = 0x9E, /* Set IO to only drive on 0 and tristate on 1 */
/* CPU mode commands */
MC_CPU_RS = 0x90, /* CPUMode read short address */
MC_CPU_RE = 0x91, /* CPUMode read extended address */
MC_CPU_WS = 0x92, /* CPUMode write short address */
MC_CPU_WE = 0x93, /* CPUMode write extended address */
};
static void check_rx()
{
while (1) {
uint8_t data;
int rc = ftdi_read_data(&ftdic, &data, 1);
if (rc <= 0)
break;
fprintf(stderr, "unexpected rx byte: %02X\n", data);
}
}
static void error(int status)
{
check_rx();
fprintf(stderr, "ABORT.\n");
if (ftdic_open) {
if (ftdic_latency_set)
ftdi_set_latency_timer(&ftdic, ftdi_latency);
ftdi_usb_close(&ftdic);
}
ftdi_deinit(&ftdic);
exit(status);
}
static uint8_t recv_byte()
{
uint8_t data;
while (1) {
int rc = ftdi_read_data(&ftdic, &data, 1);
if (rc < 0) {
fprintf(stderr, "Read error.\n");
error(2);
}
if (rc == 1)
break;
usleep(100);
}
return data;
}
static void send_byte(uint8_t data)
{
int rc = ftdi_write_data(&ftdic, &data, 1);
if (rc != 1) {
fprintf(stderr, "Write error (single byte, rc=%d, expected %d).\n", rc, 1);
error(2);
}
}
static void set_gpio(bool sda, bool scl)
{
uint8_t gpio = 0;
if (sda) gpio |= 0x01; //BDBUS0
if (scl) gpio |= 0x02; //BDBUS1
send_byte(MC_SETB_LOW);
send_byte(gpio);
send_byte(0x03); //both outputs
}
static void i2c_start() {
set_gpio(1, 1);
set_gpio(0, 1);
set_gpio(0, 0);
}
static void i2c_send(uint8_t data) {
for (int i = 7; i >= 0; i--) {
bool bit = (data >> i) & 0x1;
set_gpio(bit, 0);
set_gpio(bit, 1);
set_gpio(bit, 0);
}
set_gpio(1, 0);
set_gpio(1, 1);
set_gpio(1, 0);
}
static void i2c_stop() {
set_gpio(0, 0);
set_gpio(0, 1);
set_gpio(1, 1);
}
static void write_cmos_sensor(uint16_t addr, uint8_t value) {
fprintf(stderr, "cam[0x%04X] <= 0x%02X\n", addr, value);
i2c_start();
i2c_send(0x10 << 1);
i2c_send((addr >> 8) & 0xFF);
i2c_send(addr & 0xFF);
i2c_send(value);
i2c_stop();
}
const int framelength = 666;
const int linelength = 3448;
static void cam_init() {
// Based on "Preview Setting" from a Linux driver
write_cmos_sensor(0x0100, 0x00); //standby mode
write_cmos_sensor(0x30EB, 0x05); //mfg specific access begin
write_cmos_sensor(0x30EB, 0x0C); //
write_cmos_sensor(0x300A, 0xFF); //
write_cmos_sensor(0x300B, 0xFF); //
write_cmos_sensor(0x30EB, 0x05); //
write_cmos_sensor(0x30EB, 0x09); //mfg specific access end
write_cmos_sensor(0x0114, 0x01); //CSI_LANE_MODE: 2-lane
write_cmos_sensor(0x0128, 0x00); //DPHY_CTRL: auto mode (?)
write_cmos_sensor(0x012A, 0x18); //EXCK_FREQ[15:8] = 24MHz
write_cmos_sensor(0x012B, 0x00); //EXCK_FREQ[7:0]
write_cmos_sensor(0x0160, ((framelength >> 8) & 0xFF)); //framelength
write_cmos_sensor(0x0161, (framelength & 0xFF));
write_cmos_sensor(0x0162, ((linelength >> 8) & 0xFF));
write_cmos_sensor(0x0163, (linelength & 0xFF));
write_cmos_sensor(0x0164, 0x00); //X_ADD_STA_A[11:8]
write_cmos_sensor(0x0165, 0x00); //X_ADD_STA_A[7:0]
write_cmos_sensor(0x0166, 0x0A); //X_ADD_END_A[11:8]
write_cmos_sensor(0x0167, 0x00); //X_ADD_END_A[7:0]
write_cmos_sensor(0x0168, 0x00); //Y_ADD_STA_A[11:8]
write_cmos_sensor(0x0169, 0x00); //Y_ADD_STA_A[7:0]
write_cmos_sensor(0x016A, 0x07); //Y_ADD_END_A[11:8]
write_cmos_sensor(0x016B, 0x80); //Y_ADD_END_A[7:0]
write_cmos_sensor(0x016C, 0x02); //x_output_size[11:8] = 640
write_cmos_sensor(0x016D, 0x80); //x_output_size[7:0]
write_cmos_sensor(0x016E, 0x01); //y_output_size[11:8] = 480
write_cmos_sensor(0x016F, 0xE0); //y_output_size[7:0]
write_cmos_sensor(0x0170, 0x01); //X_ODD_INC_A
write_cmos_sensor(0x0171, 0x01); //Y_ODD_INC_A
write_cmos_sensor(0x0174, 0x02); //BINNING_MODE_H_A = x4-binning
write_cmos_sensor(0x0175, 0x02); //BINNING_MODE_V_A = x4-binning
write_cmos_sensor(0x018C, 0x08); //CSI_DATA_FORMAT_A[15:8]
write_cmos_sensor(0x018D, 0x08); //CSI_DATA_FORMAT_A[7:0]
write_cmos_sensor(0x0301, 0x08); //VTPXCK_DIV
write_cmos_sensor(0x0303, 0x01); //VTSYCK_DIV
write_cmos_sensor(0x0304, 0x03); //PREPLLCK_VT_DIV
write_cmos_sensor(0x0305, 0x03); //PREPLLCK_OP_DIV
write_cmos_sensor(0x0306, 0x00); //PLL_VT_MPY[10:8]
write_cmos_sensor(0x0307, 0x14); //PLL_VT_MPY[7:0]
write_cmos_sensor(0x0309, 0x08); //OPPXCK_DIV
write_cmos_sensor(0x030B, 0x02); //OPSYCK_DIV
write_cmos_sensor(0x030C, 0x00); //PLL_OP_MPY[10:8]
write_cmos_sensor(0x030D, 0x0A); //PLL_OP_MPY[7:0]
write_cmos_sensor(0x455E, 0x00); //??
write_cmos_sensor(0x471E, 0x4B); //??
write_cmos_sensor(0x4767, 0x0F); //??
write_cmos_sensor(0x4750, 0x14); //??
write_cmos_sensor(0x4540, 0x00); //??
write_cmos_sensor(0x47B4, 0x14); //??
write_cmos_sensor(0x4713, 0x30); //??
write_cmos_sensor(0x478B, 0x10); //??
write_cmos_sensor(0x478F, 0x10); //??
write_cmos_sensor(0x4793, 0x10); //??
write_cmos_sensor(0x4797, 0x0E); //??
write_cmos_sensor(0x479B, 0x0E); //??
//write_cmos_sensor(0x0157, 232); // ANA_GAIN_GLOBAL_A
//write_cmos_sensor(0x0257, 232); // ANA_GAIN_GLOBAL_B
//write_cmos_sensor(0x0600, 0x00); // Test pattern: disable
//write_cmos_sensor(0x0601, 0x00); // Test pattern: disable
#if 0
write_cmos_sensor(0x0600, 0x00); // Test pattern: solid colour
write_cmos_sensor(0x0601, 0x01); //
write_cmos_sensor(0x0602, 0x02); // Test pattern: red
write_cmos_sensor(0x0603, 0xAA); //
write_cmos_sensor(0x0604, 0x02); // Test pattern: greenR
write_cmos_sensor(0x0605, 0xAA); //
write_cmos_sensor(0x0606, 0x02); // Test pattern: blue
write_cmos_sensor(0x0607, 0xAA); //
write_cmos_sensor(0x0608, 0x02); // Test pattern: greenB
write_cmos_sensor(0x0609, 0xAA); //
write_cmos_sensor(0x0624, 0x0A); // Test pattern width
write_cmos_sensor(0x0625, 0x00); //
write_cmos_sensor(0x0626, 0x07); // Test pattern height
write_cmos_sensor(0x0627, 0x80); //
#endif
write_cmos_sensor(0x0100, 0x01);
}
int main() {
enum ftdi_interface ifnum = INTERFACE_B;
fprintf(stderr, "init..\n");
ftdi_init(&ftdic);
ftdi_set_interface(&ftdic, ifnum);
if (ftdi_usb_open(&ftdic, 0x0403, 0x6010) && ftdi_usb_open(&ftdic, 0x0403, 0x6014)) {
fprintf(stderr, "Can't find FTDI USB device (vendor_id 0x0403, device_id 0x6010 or 0x6014).\n");
error(2);
}
if (ftdi_usb_reset(&ftdic)) {
fprintf(stderr, "Failed to reset FTDI USB device.\n");
error(2);
}
if (ftdi_usb_purge_buffers(&ftdic)) {
fprintf(stderr, "Failed to purge buffers on FTDI USB device.\n");
error(2);
}
if (ftdi_get_latency_timer(&ftdic, &ftdi_latency) < 0) {
fprintf(stderr, "Failed to get latency timer (%s).\n", ftdi_get_error_string(&ftdic));
error(2);
}
/* 1 is the fastest polling, it means 1 kHz polling */
if (ftdi_set_latency_timer(&ftdic, 1) < 0) {
fprintf(stderr, "Failed to set latency timer (%s).\n", ftdi_get_error_string(&ftdic));
error(2);
}
if (ftdi_set_bitmode(&ftdic, 0xff, BITMODE_MPSSE) < 0) {
fprintf(stderr, "Failed to set BITMODE_MPSSE on iCE FTDI USB device.\n");
error(2);
}
// enable clock divide by 5
send_byte(MC_TCK_D5);
// set 6 MHz clock
send_byte(MC_SET_CLK_DIV);
send_byte(0x00);
send_byte(0x00);
cam_init();
}
================================================
FILE: verilog_cores/.gitignore
================================================
*.o
work/
*.cf
*.blif
*.json
================================================
FILE: verilog_cores/Makefile
================================================
SOURCES=$(wildcard phy/*.v csi/*.v link/*.v)
LINT_TOP=csi_rx_ice40 # temp
SYN_TOP=csi_rx_ice40
lint: $(SOURCES)
verilator --top-module $(LINT_TOP) --lint-only $^ /usr/local/share/yosys/ice40/cells_sim.v
syn: $(SOURCES)
yosys -p "synth_ice40 -top ${SYN_TOP} -blif top.blif" $^
.PHONY: lint syn
================================================
FILE: verilog_cores/README.md
================================================
# Verilog MIPI CSI-2 Cores - WIP
================================================
FILE: verilog_cores/csi/header_ecc.v
================================================
/**
* The MIT License
* Copyright (c) 2016-2018 David Shah
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
*/
/**
* MIPI CSI-2 header ECC computation
*/
module csi_header_ecc (
input [23:0] data,
output [7:0] ecc
);
assign ecc[7:6] = 2'b00;
assign ecc[5] = data[10] ^ data[11] ^ data[12] ^ data[13] ^ data[14] ^ data[15] ^ data[16] ^ data[17] ^ data[18] ^ data[19] ^ data[21] ^ data[22] ^ data[23];
assign ecc[4] = data[4] ^ data[5] ^ data[6] ^ data[7] ^ data[8] ^ data[9] ^ data[16] ^ data[17] ^ data[18] ^ data[19] ^ data[20] ^ data[22] ^ data[23];
assign ecc[3] = data[1] ^ data[2] ^ data[3] ^ data[7] ^ data[8] ^ data[9] ^ data[13] ^ data[14] ^ data[15] ^ data[19] ^ data[20] ^ data[21] ^ data[23];
assign ecc[2] = data[0] ^ data[2] ^ data[3] ^ data[5] ^ data[6] ^ data[9] ^ data[11] ^ data[12] ^ data[15] ^ data[18] ^ data[20] ^ data[21] ^ data[22];
assign ecc[1] = data[0] ^ data[1] ^ data[3] ^ data[4] ^ data[6] ^ data[8] ^ data[10] ^ data[12] ^ data[14] ^ data[17] ^ data[20] ^ data[21] ^ data[22] ^ data[23];
assign ecc[0] = data[0] ^ data[1] ^ data[2] ^ data[4] ^ data[5] ^ data[7] ^ data[10] ^ data[11] ^ data[13] ^ data[16] ^ data[20] ^ data[21] ^ data[22] ^ data[23];
endmodule
================================================
FILE: verilog_cores/csi/rx_packet_handler.v
================================================
/**
* The MIT License
* Copyright (c) 2016-2018 David Shah
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
*/
/**
* MIPI CSI-2 receive packet handler
*
* This controls wait_for_sync and packet_done handshaking with
* byte/word aligners; keeps track of whether in frame
* by detecting FS/FE; and extracts video payload from long packets
*/
module csi_rx_packet_handler #(
parameter [1:0] VC = 2'b00, // MIPI CSI-2 "virtual channel"
parameter [5:0] FS_DT = 6'h00, // Frame start data type
parameter [5:0] FE_DT = 6'h01, // Frame end data type
parameter [5:0] VIDEO_DT = 6'h2A, // Video payload data type (6'h2A = 8-bit raw, 6'h2B = 10-bit raw, 6'h2C = 12-bit raw)
parameter [15:0] MAX_LEN = 8192 // Max expected packet len, used as timeout
) (
input clock, // byte/word clock
input reset, // active high sync reset
input enable, // active high clock enable
input [31:0] data, // data from word aligner
input data_enable, // data enable for less than 4-lane links
input data_frame, // data framing from word combiner
input lp_detect, // D-PHY LP mode detection, forces EoP
output sync_wait, // sync wait output to byte/word handlers
output packet_done, // packet done output to word combiner
output reg [31:0] payload, // payload output
output reg payload_enable, // payload data enable
output reg payload_frame, // payload framing
output reg vsync, // quasi-vsync for FS signal
output reg in_frame,
output reg in_line
);
wire [1:0] hdr_vc;
wire [5:0] hdr_dt;
wire [15:0] hdr_packet_len;
wire [7:0] hdr_ecc, expected_ecc;
wire long_packet, valid_packet;
wire is_hdr;
reg [15:0] packet_len;
reg [2:0] state;
reg [15:0] bytes_read;
always @(posedge clock)
begin
if (reset) begin
state <= 3'b000;
packet_len <= 0;
bytes_read <= 0;
payload <= 0;
payload_enable <= 0;
payload_frame <= 0;
vsync <= 0;
in_frame <= 0;
in_line <= 0;
end else if (enable) begin
if (lp_detect) begin
state <= 3'b000;
end else begin
case (state)
3'b000: state <= 3'b001; // init
3'b001: begin // wait for start
bytes_read <= 0;
if (data_enable) begin
packet_len <= hdr_packet_len;
if (long_packet && valid_packet)
state <= 3'b010;
else
state <= 3'b011;
end
end
3'b010: begin // rx long packet
if (data_enable) begin
if ((bytes_read < (packet_len - 4)) && (bytes_read < MAX_LEN))
bytes_read <= bytes_read + 4;
else
state <= 3'b011;
end
end
3'b011: state <= 3'b100; // end of packet, assert packet_done
3'b100: state <= 3'b001; // wait one cycle and reset
default: state <= 3'b000;
endcase
end
if (is_hdr && hdr_dt == FS_DT && valid_packet)
in_frame <= 1'b1;
else if (is_hdr && hdr_dt == FE_DT && valid_packet)
in_frame <= 1'b0;
if (is_hdr && hdr_dt == VIDEO_DT && valid_packet)
in_line <= 1'b1;
else if (state != 3'b010 && state != 3'b001)
in_line <= 1'b0;
vsync <= (is_hdr && hdr_dt == FS_DT && valid_packet);
payload <= data;
payload_frame <= (state == 3'b010);
payload_enable <= (state == 3'b010) && data_enable;
end
end
assign hdr_vc = data[7:6];
assign hdr_dt = data[5:0];
assign hdr_packet_len = data[23:8];
assign hdr_ecc = data[31:24];
csi_header_ecc ecc_i (
.data(data[23:0]),
.ecc(expected_ecc)
);
assign long_packet = hdr_dt > 6'h0F;
assign valid_packet = (hdr_vc == VC)
&& (hdr_dt == FS_DT || hdr_dt == FE_DT || hdr_dt == VIDEO_DT)
&& (hdr_ecc == expected_ecc);
assign is_hdr = data_enable && (state == 3'b001);
assign sync_wait = (state == 3'b001);
assign packet_done = (state == 3'b011) || lp_detect;
endmodule
================================================
FILE: verilog_cores/csi2.core
================================================
CAPI=2:
name : ::csi2:0
filesets:
icebreaker:
files:
- misc/downsample.v : {file_type : verilogSource}
- test/icebreaker/uart.v : {file_type : verilogSource}
- test/icebreaker/top.v : {file_type : verilogSource}
- test/icebreaker/icecam.pcf : {file_type : PCF}
core:
files:
- phy/dphy_iserdes.v
- phy/dphy_oserdes.v
- phy/word_combiner.v
- phy/byte_aligner.v
- csi/header_ecc.v
- csi/rx_packet_handler.v
file_type : verilogSource
link_ice40:
files:
- link/csi_rx_ice40.v : {file_type : verilogSource}
depend : ["!tool_icestorm? (yosys:techlibs:ice40)"]
targets:
default:
filesets : [core, link_ice40]
icebreaker:
default_tool : icestorm
filesets: [core, link_ice40, icebreaker]
tools:
icestorm:
pnr : next
nextpnr_options : [--up5k]
toplevel : top
lint:
default_tool : verilator
filesets: [core, link_ice40]
tools:
verilator:
mode : lint-only
toplevel : csi_rx_ice40
================================================
FILE: verilog_cores/link/csi_rx_ice40.v
================================================
/**
* The MIT License
* Copyright (c) 2016-2018 David Shah
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
*/
/*
* Example CSI-2 receiver for iCE40
*/
module csi_rx_ice40 #(
parameter LANES = 2, // lane count
parameter PAIRSWAP = 2'b10, // lane pair swap (inverts data for given lane)
parameter [1:0] VC = 2'b00, // MIPI CSI-2 "virtual channel"
parameter [5:0] FS_DT = 6'h00, // Frame start data type
parameter [5:0] FE_DT = 6'h01, // Frame end data type
parameter [5:0] VIDEO_DT = 6'h2A, // Video payload data type (6'h2A = 8-bit raw, 6'h2B = 10-bit raw, 6'h2C = 12-bit raw)
parameter [15:0] MAX_LEN = 8192 // Max expected packet len, used as timeout
)(
input dphy_clk_lane,
input [LANES-1:0] dphy_data_lane,
input dphy_lp_sense,
input areset,
output word_clk,
output [31:0] payload_data,
output payload_enable,
output payload_frame,
output [2*LANES-1:0] dbg_raw_ddr,
output [8*LANES-1:0] dbg_raw_deser,
output [8*LANES-1:0] dbg_aligned,
output [LANES-1:0] dbg_aligned_valid,
output dbg_wait_sync,
output vsync,
output in_line,
output in_frame
);
wire dphy_clk, dphy_clk_pre;
SB_IO #(
.PIN_TYPE(6'b000001),
.IO_STANDARD("SB_LVDS_INPUT")
) clk_iobuf (
.PACKAGE_PIN(dphy_clk_lane),
.D_IN_0(dphy_clk_pre)
);
SB_GB clk_gbuf (
.USER_SIGNAL_TO_GLOBAL_BUFFER(dphy_clk_pre),
.GLOBAL_BUFFER_OUTPUT(dphy_clk)
);
wire dphy_lp;
SB_IO #(
.PIN_TYPE(6'b000001),
.IO_STANDARD("SB_LVDS_INPUT")
) lp_compare (
.PACKAGE_PIN(dphy_lp_sense),
.D_IN_0(dphy_lp)
);
reg [1:0] div;
always @(posedge dphy_clk or posedge areset)
if (areset)
div <= 0;
else
div <= div + 1'b1;
assign word_clk = div[1];
wire sreset;
reg [7:0] sreset_ctr;
always @(posedge word_clk or posedge areset)
if (areset)
sreset_ctr <= 0;
else if (!(&sreset_ctr))
sreset_ctr <= sreset_ctr + 1'b1;
assign sreset = !(&sreset_ctr);
wire byte_packet_done, wait_for_sync;
wire [LANES*8-1:0] aligned_bytes;
wire [LANES-1:0] aligned_bytes_valid;
generate
genvar ii;
for (ii = 0; ii < LANES; ii++) begin
wire [1:0] din_raw;
SB_IO #(
.PIN_TYPE(6'b000000),
.IO_STANDARD("SB_LVDS_INPUT")
) data_iobuf (
.PACKAGE_PIN(dphy_data_lane[ii]),
.INPUT_CLK(dphy_clk),
.D_IN_0(din_raw[0]),
.D_IN_1(din_raw[1])
);
assign dbg_raw_ddr[2*ii+1:2*ii] = din_raw;
wire [7:0] din_deser;
dphy_iserdes #(
.REG_INPUT(1'b1)
) iserdes_i (
.dphy_clk(dphy_clk),
.din(din_raw),
.sys_clk(word_clk),
.areset(areset),
.dout(din_deser)
);
wire [7:0] din_deser_swap = PAIRSWAP[ii] ? ~din_deser : din_deser;
assign dbg_raw_deser[8*ii+7:8*ii] = din_deser_swap;
dphy_rx_byte_align baligner_i (
.clock(word_clk),
.reset(sreset),
.enable(1'b1),
.deser_byte(din_deser_swap),
.wait_for_sync(wait_for_sync),
.packet_done(byte_packet_done),
.valid_data(aligned_bytes_valid[ii]),
.data_out(aligned_bytes[8*ii+7:8*ii])
);
end
endgenerate
assign dbg_aligned = aligned_bytes;
assign dbg_aligned_valid = aligned_bytes_valid;
wire [31:0] comb_word;
wire comb_word_en, comb_word_frame;
wire word_packet_done;
dphy_rx_word_combiner #(
.LANES(LANES)
) combiner_i (
.clock(word_clk),
.reset(sreset),
.enable(1'b1),
.bytes_in(aligned_bytes),
.bytes_valid(aligned_bytes_valid),
.wait_for_sync(wait_for_sync),
.packet_done(word_packet_done),
.byte_packet_done(byte_packet_done),
.word_out(comb_word),
.word_enable(comb_word_en),
.word_frame(comb_word_frame)
);
assign dbg_wait_sync = wait_for_sync;
csi_rx_packet_handler #(
.VC(VC),
.FS_DT(FS_DT),
.FE_DT(FE_DT),
.VIDEO_DT(VIDEO_DT),
.MAX_LEN(MAX_LEN)
) handler_i (
.clock(word_clk),
.reset(sreset),
.enable(1'b1),
.data(comb_word),
.data_enable(comb_word_en),
.data_frame(comb_word_frame),
.lp_detect(!dphy_lp),
.sync_wait(wait_for_sync),
.packet_done(word_packet_done),
.payload(payload_data),
.payload_enable(payload_enable),
.payload_frame(payload_frame),
.vsync(vsync),
.in_frame(in_frame),
.in_line(in_line)
);
endmodule
================================================
FILE: verilog_cores/misc/downsample.v
================================================
/**
* The MIT License
* Copyright (c) 2016-2018 David Shah
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
*/
/*
* Simple downsampler and buffer 640x480 => 40x30
*/
module downsample (
input pixel_clock,
input in_line,
input in_frame,
input [31:0] pixel_data,
input data_enable,
input read_clock,
input [5:0] read_x,
input [4:0] read_y,
output reg [7:0] read_q
);
reg [7:0] buffer[0:2047];
reg [11:0] pixel_acc;
reg [7:0] pixel_x;
reg [8:0] pixel_y;
reg last_in_line;
wire [11:0] next_acc = pixel_acc + pixel_data[7:0] + pixel_data[15:8] + pixel_data[23:16] + pixel_data[31:24];
always @(posedge pixel_clock)
begin
if (!in_frame) begin
pixel_acc <= 0;
pixel_x <= 0;
pixel_y <= 0;
last_in_line <= in_line;
end else begin
if (in_line && data_enable) begin
if (pixel_y[3:0] == 0) begin
if (&(pixel_x[1:0])) begin
pixel_acc <= 0;
buffer[{pixel_y[8:4], pixel_x[7:2]}] <= next_acc[11:4];
end else begin
pixel_acc <= next_acc;
end
if (pixel_x < 160)
pixel_x <= pixel_x + 1;
end
end else if (!in_line) begin
pixel_x <= 0;
pixel_acc <= 0;
if (last_in_line)
pixel_y <= pixel_y + 1'b1;
end
last_in_line <= in_line;
end
end
always @(posedge read_clock)
read_q <= buffer[{read_y, read_x}];
endmodule
================================================
FILE: verilog_cores/phy/byte_aligner.v
================================================
/**
* The MIT License
* Copyright (c) 2016-2018 David Shah
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
*/
/**
* MIPI D-PHY byte aligner
* This receives raw, unaligned bytes (which could contain part of two actual bytes)
* from the SERDES and aligns them by looking for the D-PHY sync pattern
*
* When wait_for_sync is high the entity will wait until it sees the valid header at some alignment,
* at which point the found alignment is locked until packet_done is asserted
*
* valid_data is asserted as soon as the sync pattern is found, so the next byte
* contains the CSI packet header
*
* In reality to avoid false triggers we must look for a valid sync pattern on all k lanes,
* if this does not occur the word aligner (a seperate entity) will assert packet_done immediately
*
*/
`default_nettype none
module dphy_rx_byte_align(
input clock, // byte clock
input reset, // active high sync reset
input enable, // byte clock enable
input [7:0] deser_byte, // raw bytes from iserdes
input wait_for_sync, // when high will look for a sync pattern if sync not already found
input packet_done, // assert to reset synchronisation status
output reg valid_data, // goes high as soon as sync pattern is found (so data out on next cycle contains header)
output reg [7:0] data_out //aligned data out, typically delayed by 2 cycles
);
reg [7:0] curr_byte;
reg [7:0] last_byte;
reg [7:0] shifted_byte;
reg found_sync;
reg [2:0] sync_offs; // found offset of sync pattern
reg [2:0] data_offs; // current data offset
always @(posedge clock)
begin
if (reset) begin
valid_data <= 1'b0;
last_byte <= 0;
curr_byte <= 0;
data_out <= 0;
data_offs <= 0;
end else if (enable) begin
last_byte <= curr_byte;
curr_byte <= deser_byte;
data_out <= shifted_byte;
if (packet_done) begin
valid_data <= found_sync;
end else if (wait_for_sync && found_sync && !valid_data) begin
// Waiting for sync, just found it now so use sync position as offset
valid_data <= 1'b1;
data_offs <= sync_offs;
end
end
end
localparam [7:0] sync_word = 8'b10111000;
reg was_found;
reg [2:0] offset;
integer i;
wire [15:0] concat_word = {curr_byte, last_byte};
always @(*)
begin
offset = 0;
was_found = 1'b0;
found_sync = 1'b0;
sync_offs = 0;
for (i = 0; i < 8; i = i + 1) begin
if ((concat_word[(1+i) +: 8] == sync_word) && (last_byte[i:0] == 0)) begin
was_found = 1'b1;
offset = i;
end
end
if (was_found) begin
found_sync = 1'b1;
sync_offs = offset;
end
end
assign shifted_byte = concat_word[(1 + data_offs) +: 8];
endmodule
================================================
FILE: verilog_cores/phy/dphy_iserdes.v
================================================
/**
* The MIT License
* Copyright (c) 2018 David Shah
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
*/
/**
* MIPI D-PHY input SERDES
* This is designed to take 2 inputs per clock from an architecture specific
* DDR primitive
*/
module dphy_iserdes(
input dphy_clk, // Fast D-PHY DDR clock (4x sys_clk)
input [1:0] din, // Input from arch DDR primitive, D1 should be the bit after D0
input sys_clk, // System byte clock
input areset, // Active high async reset
output [7:0] dout // Output data
);
parameter REG_INPUT = 1'b0;
parameter NUM_OUT_SYNCFFS = 2;
wire [1:0] iserdes_din;
generate
if (REG_INPUT) begin
reg [1:0] din_reg;
always @(posedge dphy_clk, posedge areset)
if (areset)
din_reg <= 2'b00;
else
din_reg <= din;
assign iserdes_din = din_reg;
end else begin
assign iserdes_din = din;
end
endgenerate
reg [7:0] reg_word;
always @(posedge dphy_clk, posedge areset)
if (areset)
reg_word <= 0;
else
reg_word <= {iserdes_din, reg_word[7:2]}; // MIPI interface uses LSB first
reg [7:0] out_sync_regs[0:NUM_OUT_SYNCFFS-1];
integer i;
always @(posedge sys_clk, posedge areset)
if (areset)
for (i = 0; i < NUM_OUT_SYNCFFS; i = i + 1)
out_sync_regs[i] <= 0;
else begin
for (i = 1; i < NUM_OUT_SYNCFFS; i = i + 1)
out_sync_regs[i] <= out_sync_regs[i-1];
out_sync_regs[0] <= reg_word;
end
assign dout = out_sync_regs[NUM_OUT_SYNCFFS-1];
endmodule
================================================
FILE: verilog_cores/phy/dphy_oserdes.v
================================================
/**
* The MIT License
* Copyright (c) 2018 David Shah
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
*/
/**
* MIPI D-PHY output SERDES
* This is designed to generate 2 outputs per clock for an architecture specific
* DDR primitive
*/
module dphy_oserdes(
input sys_clk, // System byte clock
input areset, // Active high async reset
input [7:0] din, // Input from CSI-2 packetiser
input dphy_clk, // Fast D-PHY DDR clock (4x sys_clk)
output reg [1:0] dout // Output data, bit 1 should be the second bit transmitted
);
parameter NUM_SYNCFFS = 2;
reg [8:0] dclk_sclk_din[0:NUM_SYNCFFS-1];
// Input
integer i;
always @(posedge dphy_clk, posedge areset)
if (areset) begin
for (i = 0; i < NUM_SYNCFFS; i = i + 1)
dclk_sclk_din[i] <= 0;
end else begin
for (i = 1; i < NUM_SYNCFFS; i = i + 1)
dclk_sclk_din[i] <= dclk_sclk_din[i-1];
dclk_sclk_din[0] <= {sys_clk, din};
end
wire dclk_sclk = dclk_sclk_din[NUM_SYNCFFS-1][8];
wire [7:0] dclk_din = dclk_sclk_din[NUM_SYNCFFS-1][7:0];
reg last_sclk;
reg [7:0] reg_word;
always @(posedge dphy_clk, posedge areset)
if (areset) begin
last_sclk <= 1'b0;
dout <= 2'b00;
reg_word <= 0;
end else begin
last_sclk <= dclk_sclk;
dout <= reg_word[1:0]; // LSB first
if (dclk_sclk && !last_sclk) begin
reg_word <= dclk_din;
end else begin
reg_word <= {reg_word[1:0], reg_word[7:2]};
end
end
endmodule
================================================
FILE: verilog_cores/phy/word_combiner.v
================================================
/**
* The MIT License
* Copyright (c) 2016-2018 David Shah
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
*/
/**
* MIPI D-PHY word combiner
* This receives aligned bytes from the byte aligner(s), controls the byte aligner(s)
* and assembles the data stream back into 32-bit words for consistency across different
* widths
*
*/
module dphy_rx_word_combiner #(
parameter LANES = 2
) (
input clock, // byte clock
input reset, // active high sync reset
input enable, // active high clock enable
input [8*LANES-1:0] bytes_in, // input bytes from lane byte aligners
input [LANES-1:0] bytes_valid, // valid signals from lane byte aligners
input wait_for_sync, // input from packet handler
input packet_done, // packet done input from packet handler
output byte_packet_done, // packet done output to byte aligners
output reg [31:0] word_out, //fixed width 32-bit data out
output reg word_enable, // word enable used when in less than 4-lane mode
output reg word_frame // valid output high during valid packet even if word enable low
);
wire triggered = |bytes_valid;
wire all_valid = &bytes_valid;
wire invalid_start = triggered && !all_valid;
reg valid;
reg [31:0] word_int;
reg [1:0] byte_cnt;
always @(posedge clock)
begin
if (reset) begin
valid <= 0;
word_int <= 0;
byte_cnt <= 0;
word_out <= 0;
word_enable <= 0;
word_frame <= 0;
end else if (enable) begin
if (all_valid && !valid && wait_for_sync) begin
byte_cnt <= 0;
word_frame <= 1'b1;
valid <= 1'b1;
end else if (packet_done) begin
word_frame <= 1'b0;
valid <= 1'b0;
end
if (valid) begin
if (LANES == 4) begin
word_out <= bytes_in;
word_enable <= 1'b1;
end else begin
byte_cnt <= byte_cnt + LANES;
word_int <= {bytes_in, word_int[31:8*LANES]};
if ((byte_cnt + LANES) % 4 == 0) begin
word_out <= {bytes_in, word_int[31:8*LANES]};
word_enable <= 1'b1;
end else begin
word_enable <= 1'b0;
end
end
end else begin
word_enable <= 1'b0;
end
end
end
assign byte_packet_done = packet_done | invalid_start;
endmodule
================================================
FILE: verilog_cores/test/icebreaker/.gitignore
================================================
*.blif
*.json
*.asc
*.bin
*.rpt
*.log
================================================
FILE: verilog_cores/test/icebreaker/Makefile
================================================
SOURCES = $(wildcard ../../csi/*.v ../../phy/*.v ../../link/*.v ../../misc/*.v uart.v top.v)
PROJ=camera
PIN_DEF=icecam.pcf
DEVICE=up5k
all: $(PROJ).rpt $(PROJ).bin
%.json: $(SOURCES)
yosys -ql yosys.log -p 'synth_ice40 -top top -json $@' $(SOURCES)
%.asc: %.json $(PIN_DEF)
nextpnr-ice40 --pre-pack constraints.py --up5k --pcf $(PIN_DEF) --json $< --asc $@ --freq 40
gui: %.json $(PIN_DEF)
nextpnr-ice40 --up5k --pcf $(PIN_DEF) --json $< --asc $@ --freq 40 --gui
%.bin: %.asc
icepack $< $@
%.rpt: %.asc
icetime -d $(DEVICE) -mtr $@ $<
prog: $(PROJ).bin
iceprog $<
sudo-prog: $(PROJ).bin
@echo 'Executing prog as root!!!'
sudo iceprog $<
clean:
rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin
.SECONDARY:
.PHONY: all prog clean gui
================================================
FILE: verilog_cores/test/icebreaker/constraints.py
================================================
ctx.addClock("csi_rx_i.dphy_clk", 96)
ctx.addClock("video_clk", 24)
ctx.addClock("uart_i.sys_clk_i", 12)
================================================
FILE: verilog_cores/test/icebreaker/icecam.pcf
================================================
set_io mpsse_sda 6 #FTDI D0
set_io mpsse_scl 9 #FTDI D1
set_io cam_enable 3 #P1A7
set_io cam_sda 34 #P1B3
set_io cam_scl 28 #P1B10
set_io dphy_clk 32 #P1B9
set_io dphy_data[0] 42 #P1B7
set_io dphy_data[1] 43 #P1B1
set_io dphy_lp 48 #P1A8
set_io BTN_N 10
set_io LEDR_N 11
set_io LEDG_N 37
set_io LED2 27
set_io LED3 25
set_io LED5 21
set_io BTN2 19
set_io LED1 26
set_io LED4 23
set_io BTN1 20
set_io BTN3 18
set_io clk12 35
set_io dbg_tx 13
================================================
FILE: verilog_cores/test/icebreaker/top.v
================================================
/**
* The MIT License
* Copyright (c) 2018 David Shah
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
*/
module top(input clk12,
input mpsse_sda, mpsse_scl, inout cam_sda, cam_scl, output cam_enable,
input dphy_clk, input [1:0] dphy_data, input dphy_lp,
output LEDR_N, LEDG_N, LED1, LED2, LED3, LED4, LED5,
input BTN_N, BTN1, BTN2, BTN3,
output dbg_tx);
wire areset = !BTN_N;
assign cam_scl = mpsse_scl ? 1'bz : 1'b0;
assign cam_sda = mpsse_sda ? 1'bz : 1'b0;
assign cam_enable = 1'b1;
wire video_clk;
wire in_line, in_frame, vsync;
wire [31:0] payload_data;
wire payload_valid;
wire [15:0] raw_deser;
wire [15:0] aligned_deser;
wire [3:0] raw_ddr;
wire [1:0] aligned_valid;
wire wait_sync;
wire payload_frame;
csi_rx_ice40 #(
.LANES(2), // lane count
.PAIRSWAP(2'b10), // lane pair swap (inverts data for given lane)
.VC(2'b00), // MIPI CSI-2 "virtual channel"
.FS_DT(6'h12), // Frame start data type
.FE_DT(6'h01), // Frame end data type
.VIDEO_DT(6'h2A), // Video payload data type (6'h2A = 8-bit raw, 6'h2B = 10-bit raw, 6'h2C = 12-bit raw)
.MAX_LEN(8192) // Max expected packet len, used as timeout
) csi_rx_i (
.dphy_clk_lane(dphy_clk),
.dphy_data_lane(dphy_data),
.dphy_lp_sense(dphy_lp),
.areset(areset),
.word_clk(video_clk),
.payload_data(payload_data),
.payload_enable(payload_valid),
.payload_frame(payload_frame),
.vsync(vsync),
.in_line(in_line),
.in_frame(in_frame),
.dbg_aligned_valid(aligned_valid),
.dbg_raw_deser(raw_deser),
.dbg_raw_ddr(raw_ddr),
.dbg_wait_sync(wait_sync)
);
reg [22:0] sclk_div;
always @(posedge video_clk)
sclk_div <= sclk_div + 1'b1;
reg [15:0] vsync_monostable = 0;
always @(posedge video_clk)
if (vsync || vsync_monostable != 0)
vsync_monostable <= vsync_monostable + 1'b1;
assign LEDR_N = !sclk_div[22];
assign LEDG_N = !(|vsync_monostable);
assign LED1 = video_clk;
assign {LED5, LED4, LED3, LED2} = (payload_frame&&payload_valid) ? payload_data[5:2] : 0;
reg [5:0] read_x;
reg [4:0] read_y;
wire [7:0] read_data;
downsample ds_i(
.pixel_clock(video_clk),
.in_line(in_line),
.in_frame(!vsync),
.pixel_data(payload_data),
.data_enable(payload_frame&&payload_valid),
.read_clock(clk12),
.read_x(read_x),
.read_y(read_y),
.read_q(read_data)
);
reg do_send = 1'b0;
wire uart_busy;
reg uart_write;
reg [13:0] btn_debounce;
reg btn_reg;
reg [12:0] uart_holdoff;
always @(posedge clk12)
begin
btn_reg <= BTN1;
if (btn_reg)
btn_debounce <= 0;
else if (!&(btn_debounce))
btn_debounce <= btn_debounce + 1;
uart_write <= 1'b0;
if (btn_reg && &btn_debounce && !do_send) begin
do_send <= 1'b1;
read_x <= 0;
read_y <= 0;
end
if (uart_busy)
uart_holdoff <= 0;
else if (!&(uart_holdoff))
uart_holdoff <= uart_holdoff + 1'b1;
if (do_send) begin
if (read_x == 0 && read_y == 30) begin
do_send <= 1'b0;
end else begin
if (&uart_holdoff && !uart_busy && !uart_write) begin
uart_write <= 1'b1;
if (read_x == 39) begin
read_y <= read_y + 1'b1;
read_x <= 0;
end else begin
read_x <= read_x + 1'b1;
end
end
end
end
end
uart uart_i (
// Outputs
.uart_busy(uart_busy), // High means UART is transmitting
.uart_tx(dbg_tx), // UART transmit wire
// Inputs
.uart_wr_i(uart_write), // Raise to transmit byte
.uart_dat_i(read_data), // 8-bit data
.sys_clk_i(clk12), // System clock, 12 MHz
.sys_rst_i(areset) // System reset
);
endmodule
================================================
FILE: verilog_cores/test/icebreaker/uart.v
================================================
// From http://www.excamera.com/sphinx/fpga-uart.html
module uart(
// Outputs
uart_busy, // High means UART is transmitting
uart_tx, // UART transmit wire
// Inputs
uart_wr_i, // Raise to transmit byte
uart_dat_i, // 8-bit data
sys_clk_i, // System clock, 12 MHz
sys_rst_i // System reset
);
input uart_wr_i;
input [7:0] uart_dat_i;
input sys_clk_i;
input sys_rst_i;
output uart_busy;
output uart_tx;
reg [3:0] bitcount;
reg [8:0] shifter;
reg uart_tx;
wire uart_busy = |bitcount[3:1];
wire sending = |bitcount;
// sys_clk_i is 12MHz. We want a 3MHz clock
reg [28:0] d;
wire [28:0] dInc = d[28] ? (3000000) : (3000000 - 12000000);
wire [28:0] dNxt = d + dInc;
always @(posedge sys_clk_i)
begin
d = dNxt;
end
wire ser_clk = ~d[28]; // this is the 115200 Hz clock
always @(posedge sys_clk_i)
begin
if (sys_rst_i) begin
uart_tx <= 1;
bitcount <= 0;
shifter <= 0;
end else begin
// just got a new byte
if (uart_wr_i & ~uart_busy) begin
shifter <= { uart_dat_i[7:0], 1'h0 };
bitcount <= (1 + 8 + 2);
end
if (sending & ser_clk) begin
{ shifter, uart_tx } <= { 1'h1, shifter };
bitcount <= bitcount - 1;
end
end
end
endmodule
================================================
FILE: vhdl_rx/.gitignore
================================================
*.o
work/
*.cf
================================================
FILE: vhdl_rx/LICENSE.notes
================================================
All of the source code written by me (in particular */*.vhd except the examples
folder) is licensed under the MIT license,see the LICENSE file for more
information.
For obvious reasons this does not extend to any files in the example project
generated or included by Xilinx's tools (including but not limited to Xilinx's
IP cores such as the DDR3 interface). The copyright on these belongs to Xilinx
and Xilinx's restrictions will apply.
The register values in the `ov13850_4k_regs.vhd` file were based on open source
Linux drivers, but it is my understanding that these are not copyrightable in
themselves.
All mentioned trademarks are property of their respective owners.
================================================
FILE: vhdl_rx/README.md
================================================
# 4k MIPI CSI-2 FPGA Camera Interface
## Overview
This project is an open source (MIT license) MIPI CSI-2 receive core for Xilinx FPGAs, supporting 4k resolution at greater than 30fps.
It includes a complete demo project, designed for the Genesys 2 board with a custom FMC to camera card, that writes the 4k video into a DDR3 framebuffer and
outputs at 1080p (with a choice of scaled or cropped) to the HDMI and VGA ports. The demo camera module is the Omnivision OV13850 (using the Firefly camera module),
which supports 4k at up to 30fps, although the demo runs at 24fps where it seems performance is better - this may partly be down to the choice of register values though. Although the OV13850
sensor/ADC does not seem to work much above 30fps; the camera also has a "test pattern" mode which bypasses this and which I have used to test my driver up to 45fps.
## Structure
- The `mipi-csi-rx` folder contains all the components (except the `video_timing_ctrl` timing generator, in the `video-misc` folder) needed for the CSI-2 Rx itself.
- `csi_rx_top` is the top level for the CSI-2 interface, this is what you should use in your design
- `csi_rx_4_lane_link` encapsulates the link layer. In particular
- `csi_rx_hs_lane_phy` is the low-level data PHY, one for each lane, containing the input buffer and input SERDES
- `csi_rx_byte_align` ensures bytes are correctly aligned by looking for the sync byte that precedes packets
- `csi_rx_word_align` corrects any slight alignment differences between lanes, concatenating the 4 lane byte inputs to a single 32-bit word output
- `csi_rx_hs_clk_phy` handles the clock input and contains the necessary clock buffers
- `csi_rx_packet_handler` processes packets, looking for video packets and seperating off the payload
- `csi_rx_10bit_unpack` converts 32-bit packet payload input and outputs 4 10-bit pixels (with a `valid` output, as it does not produce pixels every clock cycle)
- `csi_rx_video_output` synchronises the CSI-2 clock domain to the pixel clock domain using a line buffer and outputs standard video format
- `ov-cam-control` contains a I2C interface for camera configuration, the 4k24 configuration for the OV13850, and `ov13850_control_top` which handles camera reseting
and writes the register values from the configuration ROM to the I2C interface.
- `framebuffer-ctrl` contains the framebuffer controller, which interfaces with external framebuffer memory (providing an AXI4 master to interface with the Xilinx DDR3 controller) to scale or crop the 4k frames from the camera to 1080p for the video output.
- `video-misc` contains the video timing controller, a test pattern generator for debugging, a video register for timing purposes and the basic ISP (a simple debayering core and colour channel gain adjustment for white balance).
- `dvi-tx` contains a simple DVI transmitter, for the Genesys 2 HDMI output port
- `demo-top` contains the top level files for the demo project; and `examples` contains the Vivado project itself for the demo
## Test Hardware
The current test platform is the Digilent Genesys 2 (Kintex-7 XC7K325T-2) with an OV13850 camera. The CSI-2 lanes connect to 2.5V LVDS inputs on the FPGA, using
a custom FMC interface board. Earlier testing was done on a Virtex-6 FPGA, unfortunately I no longer have access to this platform so support cannot be guaranteed.
The exact camera used was the Firefly RK3288 camera module, which is a convenient way of obtaining the OV13850 camera - search for "OV13850 Firefly RK3288" and various sites selling it can be
found starting from $40 or so. In the future I'm looking into using smartphone replacement camera modules. I have ordered some IUNI U2 replacement back cameras which are P16V01A modules based
on the 4k60-capable OV16825 and have a publicly available pinout.
The FMC board also has a connector for the 4k 5.5" Z5 premium LCD; which I am also working on code to drive. The KiCad board designs and gerbers are in the [DSITx](https://github.com/daveshah1/DSITx/tree/master/hardware/fmc-v1.2) repo.
A quick picture of my test setup is below.
## Customisation
See `csi_rx_top.vhd` for more information on the parameters that need to be adjusted depending on your camera and application.
## Future Work
In the future the debayering block needs to be improved to reduce colour fringing at sharp edges. A driver for the focus voice coil driver inside the camera module
needs to be added; along with autofocus and AEC/AGC (at the moment gain and exposure are buried deep within the camera config ROM).
================================================
FILE: vhdl_rx/demo-top/framebuffer_top.vhd
================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--Top Level Framebuffer and Video Output Design
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
entity framebuffer_top is
port(
--Video input port
input_pixck : in std_logic;
input_vsync : in std_logic;
input_line_start : in std_logic;
input_den : in std_logic;
input_data_even : in std_logic_vector(23 downto 0);
input_data_odd : in std_logic_vector(23 downto 0);
--System/control inputs
system_clock : in std_logic;
system_reset : in std_logic;
zoom_mode : in std_logic;
freeze : in std_logic;
--Video output port
output_pixck : in std_logic;
output_vsync : out std_logic;
output_hsync : out std_logic;
output_den : out std_logic;
output_line_start : out std_logic;
output_data : out std_logic_vector(23 downto 0);
--DDR3 interface
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_cas_n : out std_logic;
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_ras_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_dq : inout std_logic_vector(31 downto 0);
ddr3_dqs_n : inout std_logic_vector(3 downto 0);
ddr3_dqs_p : inout std_logic_vector(3 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(3 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0)
);
end framebuffer_top;
architecture Behavioral of framebuffer_top is
signal ui_clock : std_logic;
signal axi_resetn : std_logic;
signal axi_awid : std_logic_vector(0 downto 0);
signal axi_awaddr : std_logic_vector(29 downto 0);
signal axi_awlen : std_logic_vector(7 downto 0);
signal axi_awsize : std_logic_vector(2 downto 0);
signal axi_awburst : std_logic_vector(1 downto 0);
signal axi_awlock : std_logic_vector(0 downto 0);
signal axi_awcache : std_logic_vector(3 downto 0);
signal axi_awprot : std_logic_vector(2 downto 0);
signal axi_awqos : std_logic_vector(3 downto 0);
signal axi_awvalid : std_logic;
signal axi_awready : std_logic;
signal axi_wdata : std_logic_vector(255 downto 0);
signal axi_wstrb : std_logic_vector(31 downto 0);
signal axi_wlast : std_logic;
signal axi_wvalid : std_logic;
signal axi_wready : std_logic;
signal axi_bid : std_logic_vector(0 downto 0);
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_bready : std_logic;
signal axi_arid : std_logic_vector(0 downto 0);
signal axi_araddr : std_logic_vector(29 downto 0);
signal axi_arlen : std_logic_vector(7 downto 0);
signal axi_arsize : std_logic_vector(2 downto 0);
signal axi_arburst : std_logic_vector(1 downto 0);
signal axi_arlock : std_logic_vector(0 downto 0);
signal axi_arcache : std_logic_vector(3 downto 0);
signal axi_arprot : std_logic_vector(2 downto 0);
signal axi_arqos : std_logic_vector(3 downto 0);
signal axi_arvalid : std_logic;
signal axi_arready : std_logic;
signal axi_rid : std_logic_vector(0 downto 0);
signal axi_rdata : std_logic_vector(255 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rlast : std_logic;
signal axi_rvalid : std_logic;
signal axi_rready : std_logic;
signal fbc_ovsync : std_logic;
signal fbc_data : std_logic_vector(23 downto 0);
signal output_line_start_int : std_logic;
signal output_den_int : std_logic;
component ddr3_if is
port(
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_cas_n : out std_logic;
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_ras_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_dq : inout std_logic_vector(31 downto 0);
ddr3_dqs_n : inout std_logic_vector(3 downto 0);
ddr3_dqs_p : inout std_logic_vector(3 downto 0);
init_calib_complete : out std_logic;
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(3 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
mmcm_locked : out std_logic;
aresetn : in std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
s_axi_awid : in std_logic_vector(0 downto 0);
s_axi_awaddr : in std_logic_vector(29 downto 0);
s_axi_awlen : in std_logic_vector(7 downto 0);
s_axi_awsize : in std_logic_vector(2 downto 0);
s_axi_awburst : in std_logic_vector(1 downto 0);
s_axi_awlock : in std_logic_vector(0 downto 0);
s_axi_awcache : in std_logic_vector(3 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awqos : in std_logic_vector(3 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(255 downto 0);
s_axi_wstrb : in std_logic_vector(31 downto 0);
s_axi_wlast : in std_logic;
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(0 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_arid : in std_logic_vector(0 downto 0);
s_axi_araddr : in std_logic_vector(29 downto 0);
s_axi_arlen : in std_logic_vector(7 downto 0);
s_axi_arsize : in std_logic_vector(2 downto 0);
s_axi_arburst : in std_logic_vector(1 downto 0);
s_axi_arlock : in std_logic_vector(0 downto 0);
s_axi_arcache : in std_logic_vector(3 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arqos : in std_logic_vector(3 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(0 downto 0);
s_axi_rdata : out std_logic_vector(255 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
sys_clk_i : in std_logic;
sys_rst : in std_logic
);
end component;
begin
axi_resetn <= not system_reset;
fbctl : entity work.framebuffer_ctrl_crop_scale
generic map(
burst_len => 16,
input_width => 3840,
input_height => 2160,
output_width => 1920,
output_height => 1080,
crop_xoffset => 1024,
crop_yoffset => 540,
scale_xoffset => 0,
scale_yoffset => 0)
port map(
input_clock => input_pixck,
input_vsync => input_vsync,
input_line_start => input_line_start,
input_den => input_den,
input_data_even => input_data_even,
input_data_odd => input_data_odd,
output_clock => output_pixck,
output_vsync => fbc_ovsync,
output_line_start => output_line_start_int,
output_den => output_den_int,
output_data => fbc_data,
axi_clock => ui_clock,
axi_resetn => axi_resetn,
axi_awid => axi_awid,
axi_awaddr => axi_awaddr,
axi_awlen => axi_awlen,
axi_awsize => axi_awsize,
axi_awburst => axi_awburst,
axi_awlock => axi_awlock,
axi_awcache => axi_awcache,
axi_awprot => axi_awprot,
axi_awqos => axi_awqos,
axi_awvalid => axi_awvalid,
axi_awready => axi_awready,
axi_wdata => axi_wdata,
axi_wstrb => axi_wstrb,
axi_wlast => axi_wlast,
axi_wvalid => axi_wvalid,
axi_wready => axi_wready,
axi_bid => axi_bid,
axi_bresp => axi_bresp,
axi_bvalid => axi_bvalid,
axi_bready => axi_bready,
axi_arid => axi_arid,
axi_araddr => axi_araddr,
axi_arlen => axi_arlen,
axi_arsize => axi_arsize,
axi_arburst => axi_arburst,
axi_arlock => axi_arlock,
axi_arcache => axi_arcache,
axi_arprot => axi_arprot,
axi_arqos => axi_arqos,
axi_arvalid => axi_arvalid,
axi_arready => axi_arready,
axi_rid => axi_rid,
axi_rdata => axi_rdata,
axi_rresp => axi_rresp,
axi_rlast => axi_rlast,
axi_rvalid => axi_rvalid,
axi_rready => axi_rready,
zoom_mode => zoom_mode,
freeze => freeze
);
output : entity work.video_fb_output
generic map(
video_hlength => 2200,
video_vlength => 1125,
video_hsync_pol => true,
video_hsync_len => 44,
video_hbp_len => 148,
video_h_visible => 1920,
video_vsync_pol => true,
video_vsync_len => 5,
video_vbp_len => 36,
video_v_visible => 1080)
port map(
pixel_clock => output_pixck,
reset => system_reset,
fbc_vsync => fbc_ovsync,
fbc_data => fbc_data,
video_vsync => output_vsync,
video_hsync => output_hsync,
video_den => output_den_int,
video_line_start => output_line_start_int,
video_data => output_data);
output_den <= output_den_int;
output_line_start <= output_line_start_int;
memctl : ddr3_if
port map(
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_cas_n => ddr3_cas_n,
ddr3_ck_n => ddr3_ck_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_cke => ddr3_cke,
ddr3_ras_n => ddr3_ras_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_we_n => ddr3_we_n,
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
init_calib_complete => open,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
ui_clk => ui_clock,
ui_clk_sync_rst => open,
mmcm_locked => open,
aresetn => axi_resetn,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => open,
app_ref_ack => open,
app_zq_ack => open,
s_axi_awid => axi_awid,
s_axi_awaddr => axi_awaddr,
s_axi_awlen => axi_awlen,
s_axi_awsize => axi_awsize,
s_axi_awburst => axi_awburst,
s_axi_awlock => axi_awlock,
s_axi_awcache => axi_awcache,
s_axi_awprot => axi_awprot,
s_axi_awqos => axi_awqos,
s_axi_awvalid => axi_awvalid,
s_axi_awready => axi_awready,
s_axi_wdata => axi_wdata,
s_axi_wstrb => axi_wstrb,
s_axi_wlast => axi_wlast,
s_axi_wvalid => axi_wvalid,
s_axi_wready => axi_wready,
s_axi_bid => axi_bid,
s_axi_bresp => axi_bresp,
s_axi_bvalid => axi_bvalid,
s_axi_bready => axi_bready,
s_axi_arid => axi_arid,
s_axi_araddr => axi_araddr,
s_axi_arlen => axi_arlen,
s_axi_arsize => axi_arsize,
s_axi_arburst => axi_arburst,
s_axi_arlock => axi_arlock,
s_axi_arcache => axi_arcache,
s_axi_arprot => axi_arprot,
s_axi_arqos => axi_arqos,
s_axi_arvalid => axi_arvalid,
s_axi_arready => axi_arready,
s_axi_rid => axi_rid,
s_axi_rdata => axi_rdata,
s_axi_rresp => axi_rresp,
s_axi_rlast => axi_rlast,
s_axi_rvalid => axi_rvalid,
s_axi_rready => axi_rready,
sys_clk_i => system_clock,
sys_rst => '1');
end Behavioral;
================================================
FILE: vhdl_rx/demo-top/mig_a.prj
================================================
<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>ddr3_if</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>ON</LowPower_En>
<XADC_En>Enabled</XADC_En>
<TargetFPGA>xc7k325t-ffg900/-2</TargetFPGA>
<Version>4.0</Version>
<SystemClock>No Buffer</SystemClock>
<ReferenceClock>Use System Clock</ReferenceClock>
<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>0</InternalVref>
<dci_hr_inouts_inputs>OFF</dci_hr_inouts_inputs>
<dci_cascade>0</dci_cascade>
<Controller number="0" >
<MemoryDevice>DDR3_SDRAM/Components/MT41J256m16XX-107</MemoryDevice>
<TimePeriod>1250</TimePeriod>
<VccAuxIO>2.0V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>200</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks>
<MMCM_VCO>800</MMCM_VCO>
<MMCMClkOut0> 1.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>32</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Normal</Ordering>
<BankMachineCnt>2</BankMachineCnt>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>15</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<MemoryVoltage>1.5V</MemoryVoltage>
<UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC12" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB8" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA8" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB12" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA12" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH9" SLEW="" name="ddr3_addr[14]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE8" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD8" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC10" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD9" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA13" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA10" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA11" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="Y10" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="Y11" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE9" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB10" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC11" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF11" SLEW="" name="ddr3_cas_n" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AC9" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AB9" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ9" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH12" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD4" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF3" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH4" SLEW="" name="ddr3_dm[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF8" SLEW="" name="ddr3_dm[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD3" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF1" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE4" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE3" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE5" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF5" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF6" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ4" SLEW="" name="ddr3_dq[16]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH6" SLEW="" name="ddr3_dq[17]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH5" SLEW="" name="ddr3_dq[18]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH2" SLEW="" name="ddr3_dq[19]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC2" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ2" SLEW="" name="ddr3_dq[20]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ1" SLEW="" name="ddr3_dq[21]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK1" SLEW="" name="ddr3_dq[22]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ3" SLEW="" name="ddr3_dq[23]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF7" SLEW="" name="ddr3_dq[24]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG7" SLEW="" name="ddr3_dq[25]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ6" SLEW="" name="ddr3_dq[26]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK6" SLEW="" name="ddr3_dq[27]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ8" SLEW="" name="ddr3_dq[28]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK8" SLEW="" name="ddr3_dq[29]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC1" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK5" SLEW="" name="ddr3_dq[30]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK4" SLEW="" name="ddr3_dq[31]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC5" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC4" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD6" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE6" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC7" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF2" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE1" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG3" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH1" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ7" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD2" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG4" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG2" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH7" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK9" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE11" SLEW="" name="ddr3_ras_n" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="AG5" SLEW="" name="ddr3_reset_n" IN_TERM="" />
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG13" SLEW="" name="ddr3_we_n" IN_TERM="" />
</PinSelection>
<System_Control>
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
</System_Control>
<TimingParameters>
<Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="35" trtp="7.5" tcke="5" trfc="260" trp="13.91" tras="34" trcd="13.91" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
<mrCasLatency name="CAS Latency" >11</mrCasLatency>
<mrMode name="Mode" >Normal</mrMode>
<mrDllReset name="DLL Reset" >No</mrDllReset>
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Enabled</emrDQS>
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >8</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface>
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG_STARVE_LIMIT</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>1</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>
</Controller>
</Project>
================================================
FILE: vhdl_rx/demo-top/ov13850_demo.vhd
================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--OV13850 Demo Top Level Design
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
entity ov13850_demo is
Port (
clock_p : in std_logic;
clock_n : in std_logic;
reset_n : in std_logic;
hdmi_clk : out std_logic_vector(1 downto 0);
hdmi_d0 : out std_logic_vector(1 downto 0);
hdmi_d1 : out std_logic_vector(1 downto 0);
hdmi_d2 : out std_logic_vector(1 downto 0);
vga_hsync : out std_logic;
vga_vsync : out std_logic;
vga_r : out std_logic_vector(4 downto 0);
vga_g : out std_logic_vector(5 downto 0);
vga_b : out std_logic_vector(4 downto 0);
zoom_mode : in std_logic;
freeze : in std_logic;
--Camera CSI port
csi0_clk : in std_logic_vector(1 downto 0);
csi0_d0 : in std_logic_vector(1 downto 0);
csi0_d1 : in std_logic_vector(1 downto 0);
csi0_d2 : in std_logic_vector(1 downto 0);
csi0_d3 : in std_logic_vector(1 downto 0);
--Camera control port
cam_mclk : out std_logic;
cam_rstn : out std_logic;
cam_i2c_sda : inout std_logic;
cam_i2c_sck : inout std_logic;
--DDR3 interface
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_cas_n : out std_logic;
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_ras_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_dq : inout std_logic_vector(31 downto 0);
ddr3_dqs_n : inout std_logic_vector(3 downto 0);
ddr3_dqs_p : inout std_logic_vector(3 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(3 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0)
);
end ov13850_demo;
architecture Behavioral of ov13850_demo is
signal sys_clock : std_logic;
signal reset : std_logic;
signal dvi_pixel_clock, dvi_bit_clock : std_logic;
signal dvi_data : std_logic_vector(23 downto 0);
signal dvi_den, dvi_hsync, dvi_vsync : std_logic;
signal i2c_clk_in, i2c_clk_div_1, i2c_clk_div : std_logic;
signal cam_loading, csi_en, csi_rst : std_logic;
signal camera_rstn_int : std_logic;
signal input_pixel_clock : std_logic;
signal camera_line_start, camera_den, camera_hsync, camera_vsync, camera_odd_line : std_logic;
signal camera_data, camera_prev_line_data : std_logic_vector(19 downto 0);
signal debayer_line_start, debayer_den, debayer_hsync, debayer_vsync : std_logic;
signal debayer_data_even, debayer_data_odd : std_logic_vector(29 downto 0);
signal fbin_line_start, fbin_den, fbin_hsync, fbin_vsync : std_logic;
signal fbin_data_even, fbin_data_odd : std_logic_vector(23 downto 0);
component dvi_pll is
port(
sysclk : in std_logic;
pixel_clock : out std_logic;
dvi_bit_clock : out std_logic);
end component;
component camera_pll is
port(
sysclk : in std_logic;
camera_pixel_clock : out std_logic;
camera_mclk : out std_logic;
i2c_clkin : out std_logic);
end component;
begin
reset <= not reset_n;
clkbuf : IBUFGDS
generic map(
DIFF_TERM => TRUE,
IBUF_LOW_PWR => FALSE,
IOSTANDARD => "DEFAULT")
port map(
O => sys_clock,
I => clock_p,
IB => clock_n);
pll1 : dvi_pll
port map(
sysclk => sys_clock,
pixel_clock => dvi_pixel_clock,
dvi_bit_clock => dvi_bit_clock
);
pll2 : camera_pll
port map(
sysclk => sys_clock,
camera_pixel_clock => input_pixel_clock,
camera_mclk => cam_mclk,
i2c_clkin => i2c_clk_in
);
--Divide 5MHz from PLL to slower I2C/reset controller input clock
i2c_clkdiv : BUFR
generic map(
BUFR_DIVIDE => "8",
SIM_DEVICE => "7SERIES")
port map(
O => i2c_clk_div_1,
CE => '1',
CLR => reset,
I => i2c_clk_in);
i2c_clkdiv2 : BUFR
generic map(
BUFR_DIVIDE => "4",
SIM_DEVICE => "7SERIES")
port map(
O => i2c_clk_div,
CE => '1',
CLR => reset,
I => i2c_clk_div_1);
cam_ctl : entity work.ov13850_control_top
port map (
reset => reset,
clock => i2c_clk_div,
i2c_sda => cam_i2c_sda,
i2c_sck => cam_i2c_sck,
rst_out => camera_rstn_int,
loading_out => cam_loading);
cam_rstn <= camera_rstn_int;
csi_rst <= not camera_rstn_int;
csi_en <= not cam_loading;
csi_rx : entity work.csi_rx_4lane
generic map(
fpga_series => "7SERIES",
dphy_term_en => true,
d0_invert => false,
d1_invert => false,
d2_invert => false,
d3_invert => false,
d0_skew => 10,
d1_skew => 10,
d2_skew => 10,
d3_skew => 10,
video_hlength => 4041,
video_vlength => 2992,
video_hsync_pol => true,
video_hsync_len => 48,
video_hbp_len => 122,
video_h_visible => 3840,
video_vsync_pol => true,
video_vsync_len => 3,
video_vbp_len => 23 ,
video_v_visible => 2160,
pixels_per_clock => 2,
generate_idelayctrl => true)
port map(
ref_clock_in => sys_clock,
pixel_clock_in => input_pixel_clock,
byte_clock_out => open,
enable => csi_en,
reset => csi_rst,
video_valid => open,
dphy_clk => csi0_clk,
dphy_d0 => csi0_d0,
dphy_d1 => csi0_d1,
dphy_d2 => csi0_d2,
dphy_d3 => csi0_d3,
video_hsync => camera_hsync,
video_vsync => camera_vsync,
video_den => camera_den,
video_line_start => camera_line_start,
video_odd_line => camera_odd_line,
video_data => camera_data,
video_prev_line_data => camera_prev_line_data);
db : entity work.simple_debayer
port map(
clock => input_pixel_clock,
input_vsync => camera_vsync,
input_hsync => camera_hsync,
input_den => camera_den,
input_odd_line => camera_odd_line,
input_line_start => camera_line_start,
input_data => camera_data,
input_prev_line_data => camera_prev_line_data,
output_vsync => debayer_vsync,
output_hsync => debayer_hsync,
output_den => debayer_den,
output_line_start => debayer_line_start,
output_data_even => debayer_data_even,
output_data_odd => debayer_data_odd);
wb : entity work.image_gain_wb
generic map(
red_gain => 10,
green_gain => 7,
blue_gain => 9)
port map(
clock => input_pixel_clock,
input_vsync => debayer_vsync,
input_hsync => debayer_hsync,
input_den => debayer_den,
input_line_start => debayer_line_start,
input_data_even => debayer_data_even,
input_data_odd => debayer_data_odd,
output_vsync => fbin_vsync,
output_hsync => fbin_hsync,
output_den => fbin_den,
output_line_start => fbin_line_start,
output_data_even => fbin_data_even,
output_data_odd => fbin_data_odd);
fbtest : entity work.framebuffer_top
port map(
input_pixck => input_pixel_clock,
input_vsync => fbin_vsync,
input_line_start => fbin_line_start,
input_den => fbin_den,
input_data_even => fbin_data_even,
input_data_odd => fbin_data_odd,
system_clock => sys_clock,
system_reset => reset,
zoom_mode => zoom_mode,
freeze => freeze,
output_pixck => dvi_pixel_clock,
output_vsync => dvi_vsync,
output_hsync => dvi_hsync,
output_den => dvi_den,
output_line_start => open,
output_data => dvi_data,
--DDR3 interface
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_cas_n => ddr3_cas_n,
ddr3_ck_n => ddr3_ck_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_cke => ddr3_cke,
ddr3_ras_n => ddr3_ras_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_we_n => ddr3_we_n,
ddr3_dq => ddr3_dq,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt
);
dvi_tx : entity work.dvi_tx
port map(
pixel_clock => dvi_pixel_clock,
ddr_bit_clock => dvi_bit_clock,
reset => reset,
den => dvi_den,
hsync => dvi_hsync,
vsync => dvi_vsync,
pixel_data => dvi_data,
tmds_clk => hdmi_clk,
tmds_d0 => hdmi_d0,
tmds_d1 => hdmi_d1,
tmds_d2 => hdmi_d2
);
vga_hsync <= dvi_hsync;
vga_vsync <= dvi_vsync;
vga_r <= dvi_data(23 downto 19);
vga_g <= dvi_data(15 downto 10);
vga_b <= dvi_data(7 downto 3);
end Behavioral;
================================================
FILE: vhdl_rx/dvi-tx/dvi_tx_clk_drv.vhd
================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--DVI Transmitter clock lane driver
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This drives the TMDS clock lane, taking the pixel clock as input
entity dvi_tx_clk_drv is
port(
pixel_clock : in std_logic;
tmds_clk : out std_logic_vector(1 downto 0));
end dvi_tx_clk_drv;
architecture Behavioral of dvi_tx_clk_drv is
signal tmds_clk_pre : std_logic;
begin
--Using an ODDR simplifies clock routing and avoids the need for a clock capable output
clk_oddr : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map(
Q => tmds_clk_pre,
C => pixel_clock,
CE => '1',
D1 => '1',
D2 => '0',
R => '0',
S => '0');
clk_obuf : OBUFDS
generic map (
IOSTANDARD => "DEFAULT",
SLEW => "FAST")
port map (
O => tmds_clk(1),
OB => tmds_clk(0),
I => tmds_clk_pre);
end Behavioral;
================================================
FILE: vhdl_rx/dvi-tx/dvi_tx_tmds_enc.vhd
================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--DVI Transmitter TMDS encoder
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This encodes TMDS 'characters' according to the algorithm in the DVI specification
entity dvi_tx_tmds_enc is
port(
clock : in std_logic; --TMDS character clock
reset : in std_logic; --synchronous reset input
den : in std_logic; --display data enable
data : in std_logic_vector(7 downto 0); --8bit display data
ctrl : in std_logic_vector(1 downto 0); --2bit control (vsync+hsync for ch0)
tmds : out std_logic_vector(9 downto 0) --10bit encoded TMDS to transmit
);
end dvi_tx_tmds_enc;
architecture Behavioral of dvi_tx_tmds_enc is
signal data_lat : std_logic_vector(7 downto 0);
signal den_lat : std_logic;
signal ctrl_lat : std_logic_vector(1 downto 0);
signal tmds_int : std_logic_vector(9 downto 0);
signal cnt_q : integer range -256 to 255;
signal cnt_d : integer range -256 to 255;
signal q_m : std_logic_vector(8 downto 0);
function count_ones(x : std_logic_vector) return integer is
variable count : natural := 0;
begin
for i in x'range loop
if x(i) = '1' then
count := count + 1;
end if;
end loop;
return count;
end function;
function count_zeros(x : std_logic_vector) return integer is
variable count : natural := 0;
begin
for i in x'range loop
if x(i) = '0' then
count := count + 1;
end if;
end loop;
return count;
end function;
begin
process(clock)
begin
if rising_edge(clock) then
if reset = '1' then
data_lat <= (others => '0');
ctrl_lat <= (others => '0');
den_lat <= '0';
tmds <= (others => '0');
cnt_q <= 0;
else
data_lat <= data;
den_lat <= den;
ctrl_lat <= ctrl;
tmds <= tmds_int;
cnt_q <= cnt_d;
end if;
end if;
end process;
process(data_lat)
variable q_m_temp : std_logic_vector(8 downto 0);
begin
q_m_temp(0) := data_lat(0);
if count_ones(data_lat) > 4 or ((count_ones(data_lat) = 4) and data_lat(0) = '0') then
for i in 1 to 7 loop
q_m_temp(i) := not(q_m_temp(i-1) xor data_lat(i));
end loop;
q_m_temp(8) := '0';
else
for i in 1 to 7 loop
q_m_temp(i) := q_m_temp(i-1) xor data_lat(i);
end loop;
q_m_temp(8) := '1';
end if;
q_m <= q_m_temp;
end process;
process(cnt_q, q_m, den_lat, ctrl_lat)
variable q_out : std_logic_vector(9 downto 0);
begin
if den_lat = '0' then
cnt_d <= 0;
case ctrl_lat is
when "00" =>
q_out := "1101010100";
when "01" =>
q_out := "0010101011";
when "10" =>
q_out := "0101010100";
when "11" =>
q_out := "1010101011";
when others => --never occurs in synthesised system but keeps sims happy
q_out := "0000000000";
end case;
else
if cnt_q = 0 or count_ones(q_m(7 downto 0)) = 4 then
q_out(9) := not q_m(8);
q_out(8) := q_m(8);
if q_m(8) = '1' then
q_out(7 downto 0) := q_m(7 downto 0);
cnt_d <= cnt_q + 2 * (count_ones(q_m(7 downto 0)) - 4);
else
q_out(7 downto 0) := not q_m(7 downto 0);
cnt_d <= cnt_q + 2 * (4 - count_ones(q_m(7 downto 0)));
end if;
else
if ((cnt_q > 0) and (count_ones(q_m(7 downto 0)) > 4))
or ((cnt_q < 0) and (count_ones(q_m(7 downto 0)) < 4)) then
q_out(9) := '1';
q_out(8) := q_m(8);
q_out(7 downto 0) := not q_m(7 downto 0);
if q_m(8) = '1' then
cnt_d <= cnt_q + 2 + 2 * (4 - count_ones(q_m(7 downto 0)));
else
cnt_d <= cnt_q + 2 * (4 - count_ones(q_m(7 downto 0)));
end if;
else
q_out(9) := '0';
q_out(8) := q_m(8);
q_out(7 downto 0) := q_m(7 downto 0);
if q_m(8) = '0' then
cnt_d <= (cnt_q - 2) + 2 * (count_ones(q_m(7 downto 0)) - 4);
else
cnt_d <= cnt_q + 2 * (count_ones(q_m(7 downto 0)) - 4);
end if;
end if;
end if;
end if;
tmds_int <= q_out;
end process;
end Behavioral;
================================================
FILE: vhdl_rx/dvi-tx/dvi_tx_tmds_phy.vhd
================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--DVI Transmitter TMDS PHY for Xilinx 7-series devices
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This handles the actual serialisation and transmission of 10bit encoded
--TMDS data
entity dvi_tx_tmds_phy is
port(
pixel_clock : in std_logic; --DVI pixel clock in
ddr_bit_clock : in std_logic; --DDR bit clock i.e. pixel_clock*5 - must be from same MMCM/PLL as pixel_clock
reset : in std_logic; --SERDES reset input
data : in std_logic_vector(9 downto 0);
tmds_lane : out std_logic_vector(1 downto 0) --1 is P, 0 is N
);
end dvi_tx_tmds_phy;
architecture Behavioral of dvi_tx_tmds_phy is
signal reset_lat : std_logic; --reset latched to pixel clock
signal shift_1, shift_2 : std_logic; --used to link master and slave OSERDES
signal data_se : std_logic; --serialised data before output buffer
begin
process(pixel_clock)
begin
if rising_edge(pixel_clock) then
reset_lat <= reset;
end if;
end process;
master_oserdes : OSERDESE2
generic map(
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "SDR",
DATA_WIDTH => 10,
INIT_OQ => '0',
INIT_TQ => '0',
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TBYTE_CTL => "FALSE",
TBYTE_SRC => "FALSE",
TRISTATE_WIDTH => 1)
port map(
CLK => ddr_bit_clock,
CLKDIV => pixel_clock,
D1 => data(0),
D2 => data(1),
D3 => data(2),
D4 => data(3),
D5 => data(4),
D6 => data(5),
D7 => data(6),
D8 => data(7),
OCE => '1',
OFB => open,
OQ => data_se,
RST => reset_lat,
SHIFTIN1 => shift_1,
SHIFTIN2 => shift_2,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
TBYTEIN => '0',
TCE => '1',
TFB => open,
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0');
slave_oserdes : OSERDESE2
generic map(
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "SDR",
DATA_WIDTH => 10,
INIT_OQ => '0',
INIT_TQ => '0',
SERDES_MODE => "SLAVE",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TBYTE_CTL => "FALSE",
TBYTE_SRC => "FALSE",
TRISTATE_WIDTH => 1)
port map(
CLK => ddr_bit_clock,
CLKDIV => pixel_clock,
D1 => '0',
D2 => '0',
D3 => data(8),
D4 => data(9),
D5 => '0',
D6 => '0',
D7 => '0',
D8 => '0',
OCE => '1',
OFB => open,
OQ => open,
RST => reset_lat,
SHIFTIN1 => '0',
SHIFTIN2 => '0',
SHIFTOUT1 => shift_1,
SHIFTOUT2 => shift_2,
TBYTEIN => '0',
TCE => '1',
TFB => open,
TQ => open,
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0');
outbuf : OBUFDS
generic map (
IOSTANDARD => "DEFAULT",
SLEW => "FAST")
port map (
O => tmds_lane(1),
OB => tmds_lane(0),
I => data_se);
end Behavioral;
================================================
FILE: vhdl_rx/dvi-tx/dvi_tx_top.vhd
================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Simple DVI Transmitter for Xilinx 7-series devices
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This is a minimal DVI transmitter core designed for Xilinx 7-series devices
--and tested using the HDMI output the Digilent Genesys 2 board (Kintex-7 XC7K325T)
entity dvi_tx is
port(
pixel_clock : in std_logic; --pixel clock input
ddr_bit_clock : in std_logic; --DDR bit clock i.e. pixel_clock*5 - must be from same MMCM/PLL as pixel_clock
reset : in std_logic; --synchronous active high reset input
den : in std_logic; --video data valid input (active high)
hsync : in std_logic; --video hsync input (polarity is timing dependent)
vsync : in std_logic; --video vsync input (polarity is timing dependent)
pixel_data : in std_logic_vector(23 downto 0); --24-bit video data
tmds_clk : out std_logic_vector(1 downto 0); --TMDS clock lane; 1 is P, 0 is N
tmds_d0 : out std_logic_vector(1 downto 0); --TMDS data lanes; 1 is P, 0 is N
tmds_d1 : out std_logic_vector(1 downto 0);
tmds_d2 : out std_logic_vector(1 downto 0));
end dvi_tx;
architecture Behavioral of dvi_tx is
signal ctrl : std_logic_vector(5 downto 0); --TMDS control signal states
signal tmds_enc : std_logic_vector(29 downto 0); --TMDS encoded data
type tmds_lanes_t is array (0 to 2) of std_logic_vector(1 downto 0);
signal tmds_lanes : tmds_lanes_t;
begin
ctrl(0) <= hsync;
ctrl(1) <= vsync;
ctrl(5 downto 2) <= "0000";
gen_lane : for i in 0 to 2 generate
lane_enc : entity work.dvi_tx_tmds_enc
port map(
clock => pixel_clock,
reset => reset,
den => den,
data => pixel_data(((8*i) + 7) downto (8*i)),
ctrl => ctrl(((2*i) + 1) downto (2*i)),
tmds => tmds_enc( ((10*i) + 9) downto (10*i)));
lane_phy : entity work.dvi_tx_tmds_phy
port map(
pixel_clock => pixel_clock,
ddr_bit_clock => ddr_bit_clock,
reset => reset,
data => tmds_enc( ((10*i) + 9) downto (10*i)),
tmds_lane => tmds_lanes(i));
end generate;
clock_phy : entity work.dvi_tx_clk_drv
port map(
pixel_clock => pixel_clock,
tmds_clk => tmds_clk);
tmds_d0 <= tmds_lanes(0);
tmds_d1 <= tmds_lanes(1);
tmds_d2 <= tmds_lanes(2);
end Behavioral;
================================================
FILE: vhdl_rx/examples/.gitignore
================================================
#########################################################################################################
## This is an example .gitignore file for Vivado, please treat it as an example as
## it might not be complete. In addition, XAPP 1165 should be followed.
#########################################################################################################
#########
#Exclude all
#########
*
!*/
!.gitignore
###########################################################################
## VIVADO
###########################################################################
#########
#Source files:
#########
#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
!*.vhd
!*.v
!*.bd
!*.edif
#########
#IP files
#########
#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
#.xci + .dcp: implementation possible but not re-synthesis
#*.xci(www.spiritconsortium.org)
!*.xci
*.dcp(checkpoint files)
#!*.dcp
*.vds
*.pb
#All bd comments and layout coordinates are stored within .ui
!*.ui
!*.ooc
#########
#System Generator
#########
!*.mdl
!*.slx
!*.bxml
#########
#Simulation logic analyzer
#########
!*.wcfg
!*.coe
#########
#MIG
#########
!*.prj
!*.mem
#########
#Project files
#########
#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
#Do NOT ignore *.xpr files
!*.xpr
#Include *.xml files for 2013.4 or earlier version
*.xml
#########
#Constraint files
#########
#Do NOT ignore *.xdc files
!*.xdc
#########
#TCL - files
#########
!*.tcl
#########
#Journal - files
#########
*.jou
#########
#Reports
#########
*.rpt
*.txt
*.vdi
#########
#C-files
#########
!*.c
!*.h
!*.elf
!*.bmm
!*.xmp
================================================
FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/54144841a4506c29/54144841a4506c29.xci
================================================
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>ipcache</spirit:library>
<spirit:name>54144841a4506c29</spirit:name>
<spirit:version>0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>dvi_pll</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="5.3"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">50.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">136.844</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">157.836</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">124</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">105.471</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">157.836</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">620</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">pixel_clock</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">dvi_bit_clock</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">dvi_pll</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">31</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">5.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">sysclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">PLL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">200</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Global_buffer</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHECRC">e2451eba</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">54144841a4506c29</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESPECIALDATA">dvi_pll</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2016.3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
================================================
FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/54144841a4506c29/dvi_pll_sim_netlist.v
================================================
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016
// Date : Tue Nov 15 16:22:12 2016
// Host : david-desktop-arch running 64-bit unknown
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dvi_pll_sim_netlist.v
// Design : dvi_pll
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k325tffg900-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(pixel_clock,
dvi_bit_clock,
sysclk);
output pixel_clock;
output dvi_bit_clock;
input sysclk;
wire dvi_bit_clock;
wire pixel_clock;
wire sysclk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dvi_pll_clk_wiz inst
(.dvi_bit_clock(dvi_bit_clock),
.pixel_clock(pixel_clock),
.sysclk(sysclk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dvi_pll_clk_wiz
(pixel_clock,
dvi_bit_clock,
sysclk);
output pixel_clock;
output dvi_bit_clock;
input sysclk;
wire clkfbout_buf_dvi_pll;
wire clkfbout_dvi_pll;
wire dvi_bit_clock;
wire dvi_bit_clock_dvi_pll;
wire pixel_clock;
wire pixel_clock_dvi_pll;
wire sysclk;
wire sysclk_dvi_pll;
wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
wire NLW_plle2_adv_inst_LOCKED_UNCONNECTED;
wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_dvi_pll),
.O(clkfbout_buf_dvi_pll));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkin1_bufg
(.I(sysclk),
.O(sysclk_dvi_pll));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(pixel_clock_dvi_pll),
.O(pixel_clock));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(dvi_bit_clock_dvi_pll),
.O(dvi_bit_clock));
(* BOX_TYPE = "PRIMITIVE" *)
PLLE2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(31),
.CLKFBOUT_PHASE(0.000000),
.CLKIN1_PERIOD(5.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE(10),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT1_DIVIDE(2),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.COMPENSATION("BUF_IN"),
.DIVCLK_DIVIDE(5),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.STARTUP_WAIT("FALSE"))
plle2_adv_inst
(.CLKFBIN(clkfbout_buf_dvi_pll),
.CLKFBOUT(clkfbout_dvi_pll),
.CLKIN1(sysclk_dvi_pll),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKOUT0(pixel_clock_dvi_pll),
.CLKOUT1(dvi_bit_clock_dvi_pll),
.CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(NLW_plle2_adv_inst_LOCKED_UNCONNECTED),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
================================================
FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/54144841a4506c29/dvi_pll_stub.v
================================================
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016
// Date : Tue Nov 15 16:22:12 2016
// Host : david-desktop-arch running 64-bit unknown
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dvi_pll_stub.v
// Design : dvi_pll
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(pixel_clock, dvi_bit_clock, sysclk)
/* synthesis syn_black_box black_box_pad_pin="pixel_clock,dvi_bit_clock,sysclk" */;
output pixel_clock;
output dvi_bit_clock;
input sysclk;
endmodule
================================================
FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/548aa35948ad692b/548aa35948ad692b.xci
================================================
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">5.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">4.375</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">26</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">127</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">sysclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">200</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Global_buffer</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHECRC">e2451eba</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">548aa35948ad692b</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESPECIALDATA">camera_pll</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2016.3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
</spirit:configurableElementValues>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
================================================
FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/548aa35948ad692b/camera_pll_sim_netlist.v
================================================
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016
// Date : Tue Nov 15 14:32:35 2016
// Host : david-desktop-arch running 64-bit unknown
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ camera_pll_sim_netlist.v
// Design : camera_pll
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k325tffg900-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(camera_pixel_clock,
camera_mclk,
i2c_clkin,
sysclk);
output camera_pixel_clock;
output camera_mclk;
output i2c_clkin;
input sysclk;
wire camera_mclk;
wire camera_pixel_clock;
wire i2c_clkin;
wire sysclk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_camera_pll_clk_wiz inst
(.camera_mclk(camera_mclk),
.camera_pixel_clock(camera_pixel_clock),
.i2c_clkin(i2c_clkin),
.sysclk(sysclk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_camera_pll_clk_wiz
(camera_pixel_clock,
camera_mclk,
i2c_clkin,
sysclk);
output camera_pixel_clock;
output camera_mclk;
output i2c_clkin;
input sysclk;
wire camera_mclk;
wire camera_mclk_camera_pll;
wire camera_pixel_clock;
wire camera_pixel_clock_camera_pll;
wire clkfbout_buf_camera_pll;
wire clkfbout_camera_pll;
wire i2c_clkin;
wire i2c_clkin_camera_pll;
wire sysclk;
wire sysclk_camera_pll;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_camera_pll),
.O(clkfbout_buf_camera_pll));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkin1_bufg
(.I(sysclk),
.O(sysclk_camera_pll));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(camera_pixel_clock_camera_pll),
.O(camera_pixel_clock));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(camera_mclk_camera_pll),
.O(camera_mclk));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout3_buf
(.I(i2c_clkin_camera_pll),
.O(i2c_clkin));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(25.375000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(5.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(4.375000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(26),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(127),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("BUF_IN"),
.DIVCLK_DIVIDE(8),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_camera_pll),
.CLKFBOUT(clkfbout_camera_pll),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(sysclk_camera_pll),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(camera_pixel_clock_camera_pll),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(camera_mclk_camera_pll),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(i2c_clkin_camera_pll),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
================================================
FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/548aa35948ad692b/camera_pll_stub.v
================================================
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (lin64) Build 1682563 Mon Oct 10 19:07:26 MDT 2016
// Date : Tue Nov 15 14:32:35 2016
// Host : david-desktop-arch running 64-bit unknown
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ camera_pll_stub.v
// Design : camera_pll
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(camera_pixel_clock, camera_mclk, i2c_clkin,
sysclk)
/* synthesis syn_black_box black_box_pad_pin="camera_pixel_clock,camera_mclk,i2c_clkin,sysclk" */;
output camera_pixel_clock;
output camera_mclk;
output i2c_clkin;
input sysclk;
endmodule
================================================
FILE: vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/75280199e9655e6a/75280199e9655e6a.xci
================================================
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>ipcache</spirit:library>
<spirit:name>75280199e9655e6a</spirit:name>
<spirit:version>0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>dvi_pll</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="5.3"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">50.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">111.449</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">139.507</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">148</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">87.091</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">139.507</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">740</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementVal
gitextract_o_fqoapy/
├── LICENSE
├── README.md
├── misc/
│ └── caminit/
│ ├── .gitignore
│ └── picam_init.cc
├── verilog_cores/
│ ├── .gitignore
│ ├── Makefile
│ ├── README.md
│ ├── csi/
│ │ ├── header_ecc.v
│ │ └── rx_packet_handler.v
│ ├── csi2.core
│ ├── link/
│ │ └── csi_rx_ice40.v
│ ├── misc/
│ │ └── downsample.v
│ ├── phy/
│ │ ├── byte_aligner.v
│ │ ├── dphy_iserdes.v
│ │ ├── dphy_oserdes.v
│ │ └── word_combiner.v
│ └── test/
│ └── icebreaker/
│ ├── .gitignore
│ ├── Makefile
│ ├── constraints.py
│ ├── icecam.pcf
│ ├── top.v
│ └── uart.v
└── vhdl_rx/
├── .gitignore
├── LICENSE.notes
├── README.md
├── demo-top/
│ ├── framebuffer_top.vhd
│ ├── mig_a.prj
│ └── ov13850_demo.vhd
├── dvi-tx/
│ ├── dvi_tx_clk_drv.vhd
│ ├── dvi_tx_tmds_enc.vhd
│ ├── dvi_tx_tmds_phy.vhd
│ └── dvi_tx_top.vhd
├── examples/
│ ├── .gitignore
│ └── ov13850_demo/
│ ├── ov13850_demo.cache/
│ │ └── ip/
│ │ ├── 54144841a4506c29/
│ │ │ ├── 54144841a4506c29.xci
│ │ │ ├── dvi_pll_sim_netlist.v
│ │ │ └── dvi_pll_stub.v
│ │ ├── 548aa35948ad692b/
│ │ │ ├── 548aa35948ad692b.xci
│ │ │ ├── camera_pll_sim_netlist.v
│ │ │ └── camera_pll_stub.v
│ │ └── 75280199e9655e6a/
│ │ ├── 75280199e9655e6a.xci
│ │ ├── dvi_pll_sim_netlist.v
│ │ └── dvi_pll_stub.v
│ ├── ov13850_demo.ip_user_files/
│ │ ├── ip/
│ │ │ ├── camera_pll/
│ │ │ │ └── camera_pll_stub.v
│ │ │ ├── ddr3_if/
│ │ │ │ └── ddr3_if_stub.v
│ │ │ ├── dvi_pll/
│ │ │ │ └── dvi_pll_stub.v
│ │ │ ├── ila_0/
│ │ │ │ └── ila_0_stub.v
│ │ │ ├── input_line_buffer/
│ │ │ │ └── input_line_buffer_stub.v
│ │ │ └── output_line_buffer/
│ │ │ └── output_line_buffer_stub.v
│ │ ├── ipstatic/
│ │ │ ├── hdl/
│ │ │ │ ├── fifo_generator_v13_1_rfs.v
│ │ │ │ └── fifo_generator_v13_1_rfs.vhd
│ │ │ └── simulation/
│ │ │ ├── blk_mem_gen_v8_3.v
│ │ │ └── fifo_generator_vlog_beh.v
│ │ ├── mem_init_files/
│ │ │ ├── mig_a.prj
│ │ │ └── mig_b.prj
│ │ └── sim_scripts/
│ │ ├── camera_pll_1/
│ │ │ ├── activehdl/
│ │ │ │ └── glbl.v
│ │ │ ├── ies/
│ │ │ │ └── glbl.v
│ │ │ ├── modelsim/
│ │ │ │ └── glbl.v
│ │ │ ├── questa/
│ │ │ │ └── glbl.v
│ │ │ ├── riviera/
│ │ │ │ └── glbl.v
│ │ │ ├── vcs/
│ │ │ │ └── glbl.v
│ │ │ └── xsim/
│ │ │ ├── cmd.tcl
│ │ │ ├── glbl.v
│ │ │ └── vlog.prj
│ │ ├── ddr3_if/
│ │ │ ├── activehdl/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_b.prj
│ │ │ ├── ies/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_b.prj
│ │ │ ├── modelsim/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_b.prj
│ │ │ ├── questa/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_b.prj
│ │ │ ├── riviera/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_b.prj
│ │ │ ├── vcs/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_b.prj
│ │ │ └── xsim/
│ │ │ ├── cmd.tcl
│ │ │ ├── glbl.v
│ │ │ ├── mig_b.prj
│ │ │ └── vlog.prj
│ │ ├── ddr3_if_1/
│ │ │ ├── activehdl/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_a.prj
│ │ │ ├── ies/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_a.prj
│ │ │ ├── modelsim/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_a.prj
│ │ │ ├── questa/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_a.prj
│ │ │ ├── riviera/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_a.prj
│ │ │ ├── vcs/
│ │ │ │ ├── glbl.v
│ │ │ │ └── mig_a.prj
│ │ │ └── xsim/
│ │ │ ├── cmd.tcl
│ │ │ ├── glbl.v
│ │ │ ├── mig_a.prj
│ │ │ └── vlog.prj
│ │ ├── dvi_pll_1/
│ │ │ ├── activehdl/
│ │ │ │ └── glbl.v
│ │ │ ├── ies/
│ │ │ │ └── glbl.v
│ │ │ ├── modelsim/
│ │ │ │ └── glbl.v
│ │ │ ├── questa/
│ │ │ │ └── glbl.v
│ │ │ ├── riviera/
│ │ │ │ └── glbl.v
│ │ │ ├── vcs/
│ │ │ │ └── glbl.v
│ │ │ └── xsim/
│ │ │ ├── cmd.tcl
│ │ │ ├── glbl.v
│ │ │ └── vlog.prj
│ │ ├── framebuffer-ctrl/
│ │ │ ├── activehdl/
│ │ │ │ └── glbl.v
│ │ │ ├── ies/
│ │ │ │ └── glbl.v
│ │ │ ├── modelsim/
│ │ │ │ └── glbl.v
│ │ │ ├── questa/
│ │ │ │ └── glbl.v
│ │ │ ├── riviera/
│ │ │ │ └── glbl.v
│ │ │ └── vcs/
│ │ │ └── glbl.v
│ │ ├── ila_0/
│ │ │ ├── activehdl/
│ │ │ │ └── glbl.v
│ │ │ ├── ies/
│ │ │ │ └── glbl.v
│ │ │ ├── modelsim/
│ │ │ │ └── glbl.v
│ │ │ ├── questa/
│ │ │ │ └── glbl.v
│ │ │ ├── riviera/
│ │ │ │ └── glbl.v
│ │ │ ├── vcs/
│ │ │ │ └── glbl.v
│ │ │ └── xsim/
│ │ │ ├── cmd.tcl
│ │ │ ├── glbl.v
│ │ │ └── vlog.prj
│ │ ├── input_line_buffer/
│ │ │ ├── activehdl/
│ │ │ │ └── glbl.v
│ │ │ ├── ies/
│ │ │ │ └── glbl.v
│ │ │ ├── modelsim/
│ │ │ │ └── glbl.v
│ │ │ ├── questa/
│ │ │ │ └── glbl.v
│ │ │ ├── riviera/
│ │ │ │ └── glbl.v
│ │ │ ├── vcs/
│ │ │ │ └── glbl.v
│ │ │ └── xsim/
│ │ │ ├── cmd.tcl
│ │ │ ├── glbl.v
│ │ │ └── vlog.prj
│ │ ├── input_line_buffer_1/
│ │ │ ├── activehdl/
│ │ │ │ └── glbl.v
│ │ │ ├── ies/
│ │ │ │ └── glbl.v
│ │ │ ├── modelsim/
│ │ │ │ └── glbl.v
│ │ │ ├── questa/
│ │ │ │ └── glbl.v
│ │ │ ├── riviera/
│ │ │ │ └── glbl.v
│ │ │ ├── vcs/
│ │ │ │ └── glbl.v
│ │ │ └── xsim/
│ │ │ ├── cmd.tcl
│ │ │ ├── glbl.v
│ │ │ └── vlog.prj
│ │ ├── output_line_buffer/
│ │ │ ├── activehdl/
│ │ │ │ └── glbl.v
│ │ │ ├── ies/
│ │ │ │ └── glbl.v
│ │ │ ├── modelsim/
│ │ │ │ └── glbl.v
│ │ │ ├── questa/
│ │ │ │ └── glbl.v
│ │ │ ├── riviera/
│ │ │ │ └── glbl.v
│ │ │ ├── vcs/
│ │ │ │ └── glbl.v
│ │ │ └── xsim/
│ │ │ ├── cmd.tcl
│ │ │ ├── glbl.v
│ │ │ └── vlog.prj
│ │ └── output_line_buffer_1/
│ │ ├── activehdl/
│ │ │ └── glbl.v
│ │ ├── ies/
│ │ │ └── glbl.v
│ │ ├── modelsim/
│ │ │ └── glbl.v
│ │ ├── questa/
│ │ │ └── glbl.v
│ │ ├── riviera/
│ │ │ └── glbl.v
│ │ ├── vcs/
│ │ │ └── glbl.v
│ │ └── xsim/
│ │ ├── cmd.tcl
│ │ ├── glbl.v
│ │ └── vlog.prj
│ ├── ov13850_demo.runs/
│ │ ├── camera_pll_synth_1/
│ │ │ ├── camera_pll.tcl
│ │ │ └── dont_touch.xdc
│ │ ├── ddr3_if_synth_1/
│ │ │ └── ddr3_if.tcl
│ │ ├── dvi_pll_synth_1/
│ │ │ ├── dont_touch.xdc
│ │ │ └── dvi_pll.tcl
│ │ ├── impl_1/
│ │ │ └── ov13850_demo.tcl
│ │ ├── input_line_buffer_synth_1/
│ │ │ ├── dont_touch.xdc
│ │ │ ├── input_line_buffer.tcl
│ │ │ ├── input_line_buffer_sim_netlist.v
│ │ │ └── input_line_buffer_stub.v
│ │ ├── output_line_buffer_synth_1/
│ │ │ ├── dont_touch.xdc
│ │ │ ├── output_line_buffer.tcl
│ │ │ ├── output_line_buffer_sim_netlist.v
│ │ │ └── output_line_buffer_stub.v
│ │ └── synth_1/
│ │ ├── .Xil/
│ │ │ └── ov13850_demo_propImpl.xdc
│ │ └── ov13850_demo.tcl
│ ├── ov13850_demo.sim/
│ │ └── sim_1/
│ │ └── synth/
│ │ └── func/
│ │ ├── genesys2_fbtest.tcl
│ │ ├── genesys2_fbtest_func_synth.v
│ │ └── genesys2_fbtest_vlog.prj
│ ├── ov13850_demo.srcs/
│ │ ├── constrs_1/
│ │ │ └── imports/
│ │ │ ├── constraints/
│ │ │ │ └── ddr3_if.xdc
│ │ │ └── new/
│ │ │ └── genesys2.xdc
│ │ └── sources_1/
│ │ └── ip/
│ │ ├── camera_pll_1/
│ │ │ ├── camera_pll.v
│ │ │ ├── camera_pll.xci
│ │ │ ├── camera_pll.xdc
│ │ │ ├── camera_pll_board.xdc
│ │ │ ├── camera_pll_clk_wiz.v
│ │ │ ├── camera_pll_ooc.xdc
│ │ │ ├── camera_pll_sim_netlist.v
│ │ │ └── camera_pll_stub.v
│ │ ├── ddr3_if/
│ │ │ ├── mig_a.prj
│ │ │ └── mig_b.prj
│ │ ├── ddr3_if_1/
│ │ │ ├── ddr3_if/
│ │ │ │ └── user_design/
│ │ │ │ ├── constraints/
│ │ │ │ │ ├── ddr3_if.xdc
│ │ │ │ │ └── ddr3_if_ooc.xdc
│ │ │ │ └── rtl/
│ │ │ │ ├── axi/
│ │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_addr_decode.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_read.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_reg.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_reg_bank.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_top.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_ctrl_write.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_ar_channel.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_aw_channel.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_b_channel.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_cmd_arbiter.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_cmd_fsm.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_cmd_translator.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_fifo.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_incr_cmd.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_r_channel.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_simple_fifo.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_w_channel.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_wr_cmd_fsm.v
│ │ │ │ │ ├── mig_7series_v4_0_axi_mc_wrap_cmd.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_a_upsizer.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_axi_register_slice.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_axi_upsizer.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_axic_register_slice.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_carry_and.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_carry_latch_and.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_carry_latch_or.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_carry_or.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_command_fifo.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_comparator.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_comparator_sel.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_comparator_sel_static.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_r_upsizer.v
│ │ │ │ │ └── mig_7series_v4_0_ddr_w_upsizer.v
│ │ │ │ ├── clocking/
│ │ │ │ │ ├── mig_7series_v4_0_clk_ibuf.v
│ │ │ │ │ ├── mig_7series_v4_0_infrastructure.v
│ │ │ │ │ ├── mig_7series_v4_0_iodelay_ctrl.v
│ │ │ │ │ └── mig_7series_v4_0_tempmon.v
│ │ │ │ ├── controller/
│ │ │ │ │ ├── mig_7series_v4_0_arb_mux.v
│ │ │ │ │ ├── mig_7series_v4_0_arb_row_col.v
│ │ │ │ │ ├── mig_7series_v4_0_arb_select.v
│ │ │ │ │ ├── mig_7series_v4_0_bank_cntrl.v
│ │ │ │ │ ├── mig_7series_v4_0_bank_common.v
│ │ │ │ │ ├── mig_7series_v4_0_bank_compare.v
│ │ │ │ │ ├── mig_7series_v4_0_bank_mach.v
│ │ │ │ │ ├── mig_7series_v4_0_bank_queue.v
│ │ │ │ │ ├── mig_7series_v4_0_bank_state.v
│ │ │ │ │ ├── mig_7series_v4_0_col_mach.v
│ │ │ │ │ ├── mig_7series_v4_0_mc.v
│ │ │ │ │ ├── mig_7series_v4_0_rank_cntrl.v
│ │ │ │ │ ├── mig_7series_v4_0_rank_common.v
│ │ │ │ │ ├── mig_7series_v4_0_rank_mach.v
│ │ │ │ │ └── mig_7series_v4_0_round_robin_arb.v
│ │ │ │ ├── ddr3_if.v
│ │ │ │ ├── ddr3_if_mig.v
│ │ │ │ ├── ddr3_if_mig_sim.v
│ │ │ │ ├── ecc/
│ │ │ │ │ ├── mig_7series_v4_0_ecc_buf.v
│ │ │ │ │ ├── mig_7series_v4_0_ecc_dec_fix.v
│ │ │ │ │ ├── mig_7series_v4_0_ecc_gen.v
│ │ │ │ │ ├── mig_7series_v4_0_ecc_merge_enc.v
│ │ │ │ │ └── mig_7series_v4_0_fi_xor.v
│ │ │ │ ├── ip_top/
│ │ │ │ │ ├── mig_7series_v4_0_mem_intfc.v
│ │ │ │ │ └── mig_7series_v4_0_memc_ui_top_axi.v
│ │ │ │ ├── phy/
│ │ │ │ │ ├── mig_7series_v4_0_ddr_byte_group_io.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_byte_lane.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_calib_top.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_if_post_fifo.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_mc_phy.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_mc_phy_wrapper.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_of_pre_fifo.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_4lanes.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_dqs_found_cal.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_dqs_found_cal_hr.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_init.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_cntlr.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_data.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_edge.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_lim.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_mux.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_po_cntlr.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_ocd_samp.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_oclkdelay_cal.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_prbs_rdlvl.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_rdlvl.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_tempmon.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_top.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_wrcal.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_wrlvl.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_phy_wrlvl_off_delay.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_prbs_gen.v
│ │ │ │ │ ├── mig_7series_v4_0_ddr_skip_calib_tap.v
│ │ │ │ │ ├── mig_7series_v4_0_poc_cc.v
│ │ │ │ │ ├── mig_7series_v4_0_poc_edge_store.v
│ │ │ │ │ ├── mig_7series_v4_0_poc_meta.v
│ │ │ │ │ ├── mig_7series_v4_0_poc_pd.v
│ │ │ │ │ ├── mig_7series_v4_0_poc_tap_base.v
│ │ │ │ │ └── mig_7series_v4_0_poc_top.v
│ │ │ │ └── ui/
│ │ │ │ ├── mig_7series_v4_0_ui_cmd.v
│ │ │ │ ├── mig_7series_v4_0_ui_rd_data.v
│ │ │ │ ├── mig_7series_v4_0_ui_top.v
│ │ │ │ └── mig_7series_v4_0_ui_wr_data.v
│ │ │ ├── ddr3_if.xci
│ │ │ ├── ddr3_if_sim_netlist.v
│ │ │ ├── ddr3_if_stub.v
│ │ │ └── mig_a.prj
│ │ ├── dvi_pll_1/
│ │ │ ├── dvi_pll.v
│ │ │ ├── dvi_pll.xci
│ │ │ ├── dvi_pll.xdc
│ │ │ ├── dvi_pll_board.xdc
│ │ │ ├── dvi_pll_clk_wiz.v
│ │ │ ├── dvi_pll_ooc.xdc
│ │ │ ├── dvi_pll_sim_netlist.v
│ │ │ └── dvi_pll_stub.v
│ │ ├── input_line_buffer_1/
│ │ │ ├── hdl/
│ │ │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd
│ │ │ ├── input_line_buffer.xci
│ │ │ ├── input_line_buffer_ooc.xdc
│ │ │ ├── input_line_buffer_sim_netlist.v
│ │ │ ├── input_line_buffer_stub.v
│ │ │ ├── misc/
│ │ │ │ └── blk_mem_gen_v8_3.vhd
│ │ │ ├── sim/
│ │ │ │ └── input_line_buffer.v
│ │ │ ├── simulation/
│ │ │ │ └── blk_mem_gen_v8_3.v
│ │ │ └── synth/
│ │ │ └── input_line_buffer.vhd
│ │ └── output_line_buffer_1/
│ │ ├── hdl/
│ │ │ └── blk_mem_gen_v8_3_vhsyn_rfs.vhd
│ │ ├── misc/
│ │ │ └── blk_mem_gen_v8_3.vhd
│ │ ├── output_line_buffer.xci
│ │ ├── output_line_buffer_ooc.xdc
│ │ ├── output_line_buffer_sim_netlist.v
│ │ ├── output_line_buffer_stub.v
│ │ ├── sim/
│ │ │ └── output_line_buffer.v
│ │ ├── simulation/
│ │ │ └── blk_mem_gen_v8_3.v
│ │ └── synth/
│ │ └── output_line_buffer.vhd
│ └── ov13850_demo.xpr
├── framebuffer-ctrl/
│ ├── framebuffer_ctrl.vhd
│ ├── input_line_buffer.xci
│ └── output_line_buffer.xci
├── mipi-csi-rx/
│ ├── csi_rx_10bit_unpack.vhd
│ ├── csi_rx_4_lane_link.vhd
│ ├── csi_rx_byte_align.vhd
│ ├── csi_rx_clock_det.vhd
│ ├── csi_rx_hdr_ecc.vhd
│ ├── csi_rx_hs_clk_phy.vhd
│ ├── csi_rx_hs_lane_phy.vhd
│ ├── csi_rx_idelayctrl_gen.vhd
│ ├── csi_rx_line_buffer.vhd
│ ├── csi_rx_packet_handler.vhd
│ ├── csi_rx_top.vhd
│ ├── csi_rx_video_output.vhd
│ ├── csi_rx_word_align.vhd
│ └── synth.ys
├── ov-cam-control/
│ ├── manual_focus.vhd
│ ├── ov13850_4k_regs.vhd
│ ├── ov13850_control_top.vhd
│ ├── ov16825_1080p120_regs.vhd
│ ├── ov_i2c_control.vhd
│ └── vcm_i2c_control.vhd
└── video-misc/
├── image_gain_wb.vhd
├── simple_debayer.vhd
├── test_pattern_gen.vhd
├── video_fb_output.vhd
├── video_register.vhd
└── video_timing_ctrl.vhd
SYMBOL INDEX (13 symbols across 1 files)
FILE: misc/caminit/picam_init.cc
type ftdi_context (line 7) | struct ftdi_context
type mpsse_cmd (line 15) | enum mpsse_cmd
function check_rx (line 49) | static void check_rx()
function error (line 60) | static void error(int status)
function recv_byte (line 73) | static uint8_t recv_byte()
function send_byte (line 89) | static void send_byte(uint8_t data)
function set_gpio (line 98) | static void set_gpio(bool sda, bool scl)
function i2c_start (line 108) | static void i2c_start() {
function i2c_send (line 114) | static void i2c_send(uint8_t data) {
function i2c_stop (line 126) | static void i2c_stop() {
function write_cmos_sensor (line 132) | static void write_cmos_sensor(uint16_t addr, uint8_t value) {
function cam_init (line 145) | static void cam_init() {
function main (line 239) | int main() {
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Condensed preview — 350 files, each showing path, character count, and a content snippet. Download the .json file for the full structured content (25,820K chars).
[
{
"path": "LICENSE",
"chars": 1086,
"preview": "MIT License\n\nCopyright (c) 2016-2018 David Shah <dave@ds0.me>\n\nPermission is hereby granted, free of charge, to any pers"
},
{
"path": "README.md",
"chars": 872,
"preview": "# MIPI CSI-2 IP Cores\n\nThe _vhdl\\_rx_ folder contains a tried-and-tested high performance CSI-2 receiver core in VHDL. T"
},
{
"path": "misc/caminit/.gitignore",
"chars": 9,
"preview": "/caminit\n"
},
{
"path": "misc/caminit/picam_init.cc",
"chars": 8809,
"preview": "// Simple I2C using MPSSE bitbang implementation (passed thru FPGA) to initialise a PiCam2\n// Some code taken from icepr"
},
{
"path": "verilog_cores/.gitignore",
"chars": 29,
"preview": "*.o\nwork/\n*.cf\n*.blif\n*.json\n"
},
{
"path": "verilog_cores/Makefile",
"chars": 298,
"preview": "SOURCES=$(wildcard phy/*.v csi/*.v link/*.v)\nLINT_TOP=csi_rx_ice40 # temp\nSYN_TOP=csi_rx_ice40\n\nlint: $(SOURCES)\n\tverila"
},
{
"path": "verilog_cores/README.md",
"chars": 33,
"preview": "# Verilog MIPI CSI-2 Cores - WIP\n"
},
{
"path": "verilog_cores/csi/header_ecc.v",
"chars": 2240,
"preview": "/**\n * The MIT License\n * Copyright (c) 2016-2018 David Shah\n *\n * Permission is hereby granted, free of charge, to any "
},
{
"path": "verilog_cores/csi/rx_packet_handler.v",
"chars": 4750,
"preview": "/**\n * The MIT License\n * Copyright (c) 2016-2018 David Shah\n *\n * Permission is hereby granted, free of charge, to any "
},
{
"path": "verilog_cores/csi2.core",
"chars": 1042,
"preview": "CAPI=2:\n\nname : ::csi2:0\n\nfilesets:\n icebreaker:\n files:\n - misc/downsample.v : {file_type : verilogSource}\n "
},
{
"path": "verilog_cores/link/csi_rx_ice40.v",
"chars": 5097,
"preview": "/**\n * The MIT License\n * Copyright (c) 2016-2018 David Shah\n *\n * Permission is hereby granted, free of charge, to any "
},
{
"path": "verilog_cores/misc/downsample.v",
"chars": 2350,
"preview": "/**\n * The MIT License\n * Copyright (c) 2016-2018 David Shah\n *\n * Permission is hereby granted, free of charge, to any "
},
{
"path": "verilog_cores/phy/byte_aligner.v",
"chars": 3655,
"preview": "/**\n * The MIT License\n * Copyright (c) 2016-2018 David Shah\n *\n * Permission is hereby granted, free of charge, to any "
},
{
"path": "verilog_cores/phy/dphy_iserdes.v",
"chars": 2468,
"preview": "/**\n * The MIT License\n * Copyright (c) 2018 David Shah\n *\n * Permission is hereby granted, free of charge, to any perso"
},
{
"path": "verilog_cores/phy/dphy_oserdes.v",
"chars": 2449,
"preview": "/**\n * The MIT License\n * Copyright (c) 2018 David Shah\n *\n * Permission is hereby granted, free of charge, to any perso"
},
{
"path": "verilog_cores/phy/word_combiner.v",
"chars": 3161,
"preview": "/**\n * The MIT License\n * Copyright (c) 2016-2018 David Shah\n *\n * Permission is hereby granted, free of charge, to any "
},
{
"path": "verilog_cores/test/icebreaker/.gitignore",
"chars": 38,
"preview": "*.blif\n*.json\n*.asc\n*.bin\n*.rpt\n*.log\n"
},
{
"path": "verilog_cores/test/icebreaker/Makefile",
"chars": 758,
"preview": "SOURCES = $(wildcard ../../csi/*.v ../../phy/*.v ../../link/*.v ../../misc/*.v uart.v top.v)\nPROJ=camera\nPIN_DEF=icecam."
},
{
"path": "verilog_cores/test/icebreaker/constraints.py",
"chars": 105,
"preview": "ctx.addClock(\"csi_rx_i.dphy_clk\", 96)\nctx.addClock(\"video_clk\", 24)\nctx.addClock(\"uart_i.sys_clk_i\", 12)\n"
},
{
"path": "verilog_cores/test/icebreaker/icecam.pcf",
"chars": 507,
"preview": "set_io mpsse_sda 6 #FTDI D0\nset_io mpsse_scl 9 #FTDI D1\n\nset_io cam_enable 3 #P1A7\nset_io cam_sda 34 #P1B3\nset_io cam_sc"
},
{
"path": "verilog_cores/test/icebreaker/top.v",
"chars": 4596,
"preview": "/**\n * The MIT License\n * Copyright (c) 2018 David Shah\n *\n * Permission is hereby granted, free of charge, to any perso"
},
{
"path": "verilog_cores/test/icebreaker/uart.v",
"chars": 1308,
"preview": "// From http://www.excamera.com/sphinx/fpga-uart.html\n\nmodule uart(\n // Outputs\n uart_busy, // High means UART is "
},
{
"path": "vhdl_rx/.gitignore",
"chars": 15,
"preview": "*.o\nwork/\n*.cf\n"
},
{
"path": "vhdl_rx/LICENSE.notes",
"chars": 677,
"preview": "All of the source code written by me (in particular */*.vhd except the examples\nfolder) is licensed under the MIT licens"
},
{
"path": "vhdl_rx/README.md",
"chars": 4661,
"preview": "# 4k MIPI CSI-2 FPGA Camera Interface\n\n## Overview\nThis project is an open source (MIT license) MIPI CSI-2 receive core "
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"path": "vhdl_rx/demo-top/framebuffer_top.vhd",
"chars": 12058,
"preview": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--Top Level Framebuffer and Video Output Design\n--"
},
{
"path": "vhdl_rx/demo-top/mig_a.prj",
"chars": 12670,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/demo-top/ov13850_demo.vhd",
"chars": 9056,
"preview": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\nlibrary UNISIM;\nuse UNISIM.VComponents.all;\n\n--OV1"
},
{
"path": "vhdl_rx/dvi-tx/dvi_tx_clk_drv.vhd",
"chars": 1032,
"preview": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\nlibrary UNISIM;\nuse UNISIM.VComponents.all;\n\n--DVI Transmitter clock lane dr"
},
{
"path": "vhdl_rx/dvi-tx/dvi_tx_tmds_enc.vhd",
"chars": 4298,
"preview": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\nuse IEEE.NUMERIC_STD.ALL;\n\n--DVI Transmitter TMDS encoder\n--Copyright (C) 201"
},
{
"path": "vhdl_rx/dvi-tx/dvi_tx_tmds_phy.vhd",
"chars": 3035,
"preview": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\nlibrary UNISIM;\nuse UNISIM.VComponents.all;\n\n--DVI Transmitter TMDS PHY for "
},
{
"path": "vhdl_rx/dvi-tx/dvi_tx_top.vhd",
"chars": 2331,
"preview": "library IEEE;\nuse IEEE.STD_LOGIC_1164.ALL;\n\n--Simple DVI Transmitter for Xilinx 7-series devices\n--Copyright (C) 2016 Da"
},
{
"path": "vhdl_rx/examples/.gitignore",
"chars": 1703,
"preview": "#########################################################################################################\n##\tThis is an "
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"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/54144841a4506c29/54144841a4506c29.xci",
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"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/54144841a4506c29/dvi_pll_sim_netlist.v",
"chars": 5677,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
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"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/54144841a4506c29/dvi_pll_stub.v",
"chars": 1261,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
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"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/548aa35948ad692b/548aa35948ad692b.xci",
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"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/548aa35948ad692b/camera_pll_sim_netlist.v",
"chars": 7592,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
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"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/548aa35948ad692b/camera_pll_stub.v",
"chars": 1326,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
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"chars": 5677,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
},
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"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.cache/ip/75280199e9655e6a/dvi_pll_stub.v",
"chars": 1261,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
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"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/camera_pll/camera_pll_stub.v",
"chars": 1233,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
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"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/ddr3_if/ddr3_if_stub.v",
"chars": 4479,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
},
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"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/dvi_pll/dvi_pll_stub.v",
"chars": 1199,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/ila_0/ila_0_stub.v",
"chars": 1169,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
},
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"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/input_line_buffer/input_line_buffer_stub.v",
"chars": 1433,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
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"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ip/output_line_buffer/output_line_buffer_stub.v",
"chars": 1437,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ipstatic/hdl/fifo_generator_v13_1_rfs.v",
"chars": 595529,
"preview": "`pragma protect begin_protected\n`pragma protect version = 1\n`pragma protect encrypt_agent = \"XILINX\"\n`pragma protect enc"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ipstatic/hdl/fifo_generator_v13_1_rfs.vhd",
"chars": 1422259,
"preview": "`protect begin_protected\n`protect version = 1\n`protect encrypt_agent = \"XILINX\"\n`protect encrypt_agent_info = \"Xilinx En"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ipstatic/simulation/blk_mem_gen_v8_3.v",
"chars": 170692,
"preview": "/******************************************************************************\n-- (c) Copyright 2006 - 2013 Xilinx, Inc"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/ipstatic/simulation/fifo_generator_vlog_beh.v",
"chars": 452753,
"preview": "/*\n *******************************************************************************\n *\n * FIFO Generator - Verilog Behav"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/mem_init_files/mig_a.prj",
"chars": 12673,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/mem_init_files/mig_b.prj",
"chars": 12812,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/activehdl/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/ies/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/modelsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/questa/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/riviera/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/vcs/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/xsim/cmd.tcl",
"chars": 452,
"preview": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n a"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/xsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/camera_pll_1/xsim/vlog.prj",
"chars": 297,
"preview": "verilog xil_defaultlib \"../../../../ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_clk_wiz.v\" --include \"../../."
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/activehdl/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/activehdl/mig_b.prj",
"chars": 12673,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/ies/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/ies/mig_b.prj",
"chars": 12673,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/modelsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/modelsim/mig_b.prj",
"chars": 12673,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/questa/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/questa/mig_b.prj",
"chars": 12673,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/riviera/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/riviera/mig_b.prj",
"chars": 12673,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/vcs/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/vcs/mig_b.prj",
"chars": 12673,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/xsim/cmd.tcl",
"chars": 452,
"preview": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n a"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/xsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/xsim/mig_b.prj",
"chars": 12673,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if/xsim/vlog.prj",
"chars": 14525,
"preview": "verilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if/ddr3_if/user_design/rtl/axi/mig_7series_v"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/activehdl/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/activehdl/mig_a.prj",
"chars": 12673,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/ies/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/ies/mig_a.prj",
"chars": 12673,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/modelsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/modelsim/mig_a.prj",
"chars": 12673,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/questa/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/questa/mig_a.prj",
"chars": 12673,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/riviera/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/riviera/mig_a.prj",
"chars": 12673,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/vcs/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/vcs/mig_a.prj",
"chars": 12673,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/xsim/cmd.tcl",
"chars": 452,
"preview": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n a"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/xsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/xsim/mig_a.prj",
"chars": 12673,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ddr3_if_1/xsim/vlog.prj",
"chars": 14727,
"preview": "verilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/rtl/axi/mig_7series"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/activehdl/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/ies/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/modelsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/questa/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/riviera/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/vcs/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/xsim/cmd.tcl",
"chars": 452,
"preview": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n a"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/xsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/dvi_pll_1/xsim/vlog.prj",
"chars": 285,
"preview": "verilog xil_defaultlib \"../../../../ov13850_demo.srcs/sources_1/ip/dvi_pll_1/dvi_pll_clk_wiz.v\" --include \"../../../ipst"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/framebuffer-ctrl/activehdl/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/framebuffer-ctrl/ies/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/framebuffer-ctrl/modelsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/framebuffer-ctrl/questa/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/framebuffer-ctrl/riviera/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/framebuffer-ctrl/vcs/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/activehdl/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/ies/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/modelsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/questa/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/riviera/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/vcs/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/xsim/cmd.tcl",
"chars": 452,
"preview": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n a"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/xsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/ila_0/xsim/vlog.prj",
"chars": 208,
"preview": "verilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/ila_0/sim/ila_0.v\" --include \"../../../../framebu"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/activehdl/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/ies/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/modelsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/questa/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/riviera/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/vcs/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/xsim/cmd.tcl",
"chars": 452,
"preview": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n a"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/xsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer/xsim/vlog.prj",
"chars": 156,
"preview": "verilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/input_line_buffer/sim/input_line_buffer.v\" \n\nveri"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/activehdl/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/ies/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/modelsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/questa/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/riviera/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/vcs/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/xsim/cmd.tcl",
"chars": 452,
"preview": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n a"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/xsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/input_line_buffer_1/xsim/vlog.prj",
"chars": 158,
"preview": "verilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/input_line_buffer_1/sim/input_line_buffer.v\" \n\nve"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/activehdl/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/ies/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/modelsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/questa/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/riviera/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/vcs/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/xsim/cmd.tcl",
"chars": 452,
"preview": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n a"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/xsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer/xsim/vlog.prj",
"chars": 158,
"preview": "verilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/output_line_buffer/sim/output_line_buffer.v\" \n\nve"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/activehdl/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/ies/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/modelsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/questa/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/riviera/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/vcs/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/xsim/cmd.tcl",
"chars": 452,
"preview": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n a"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/xsim/glbl.v",
"chars": 1470,
"preview": "// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.ip_user_files/sim_scripts/output_line_buffer_1/xsim/vlog.prj",
"chars": 160,
"preview": "verilog xil_defaultlib \"../../../../framebuffer_test.srcs/sources_1/ip/output_line_buffer_1/sim/output_line_buffer.v\" \n\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1/camera_pll.tcl",
"chars": 8093,
"preview": "# \n# Synthesis run script generated by Vivado\n# \n\nset_msg_config -id {HDL 9-1061} -limit 100000\nset_msg_config -id {HDL "
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/camera_pll_synth_1/dont_touch.xdc",
"chars": 2233,
"preview": "# This file is automatically generated.\n# It contains project source information necessary for synthesis and implementat"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/ddr3_if_synth_1/ddr3_if.tcl",
"chars": 7940,
"preview": "# \n# Synthesis run script generated by Vivado\n# \n\nset_msg_config -msgmgr_mode ooc_run\ncreate_project -in_memory -part xc"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1/dont_touch.xdc",
"chars": 2161,
"preview": "# This file is automatically generated.\n# It contains project source information necessary for synthesis and implementat"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/dvi_pll_synth_1/dvi_pll.tcl",
"chars": 7933,
"preview": "# \n# Synthesis run script generated by Vivado\n# \n\nset_param xicom.use_bs_reader 1\nset_msg_config -id {HDL 9-1061} -limit"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/impl_1/ov13850_demo.tcl",
"chars": 1992,
"preview": "proc start_step { step } {\n set stopFile \".stop.rst\"\n if {[file isfile .stop.rst]} {\n puts \"\"\n puts \"*** Halting"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/input_line_buffer_synth_1/dont_touch.xdc",
"chars": 1201,
"preview": "# This file is automatically generated.\n# It contains project source information necessary for synthesis and implementat"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/input_line_buffer_synth_1/input_line_buffer.tcl",
"chars": 8673,
"preview": "# \n# Synthesis run script generated by Vivado\n# \n\nset_msg_config -msgmgr_mode ooc_run\ncreate_project -in_memory -part xc"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/input_line_buffer_synth_1/input_line_buffer_sim_netlist.v",
"chars": 165886,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/input_line_buffer_synth_1/input_line_buffer_stub.v",
"chars": 1467,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/output_line_buffer_synth_1/dont_touch.xdc",
"chars": 1213,
"preview": "# This file is automatically generated.\n# It contains project source information necessary for synthesis and implementat"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/output_line_buffer_synth_1/output_line_buffer.tcl",
"chars": 8737,
"preview": "# \n# Synthesis run script generated by Vivado\n# \n\nset_msg_config -msgmgr_mode ooc_run\ncreate_project -in_memory -part xc"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/output_line_buffer_synth_1/output_line_buffer_sim_netlist.v",
"chars": 165232,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/output_line_buffer_synth_1/output_line_buffer_stub.v",
"chars": 1469,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/synth_1/.Xil/ov13850_demo_propImpl.xdc",
"chars": 28276,
"preview": "set_property SRC_FILE_INFO {cfile:/home/dave/ip/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/new/genesys2.x"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.runs/synth_1/ov13850_demo.tcl",
"chars": 4430,
"preview": "# \n# Synthesis run script generated by Vivado\n# \n\nset_param xicom.use_bs_reader 1\nset_msg_config -id {HDL 9-1061} -limit"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.sim/sim_1/synth/func/genesys2_fbtest.tcl",
"chars": 449,
"preview": "set curr_wave [current_wave_config]\nif { [string length $curr_wave] == 0 } {\n if { [llength [get_objects]] > 0} {\n a"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.sim/sim_1/synth/func/genesys2_fbtest_func_synth.v",
"chars": 8670539,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.sim/sim_1/synth/func/genesys2_fbtest_vlog.prj",
"chars": 281,
"preview": "# compile verilog/system verilog design source files\nverilog xil_defaultlib \"genesys2_fbtest_func_synth.v\" --include \"."
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/constraints/ddr3_if.xdc",
"chars": 22314,
"preview": "##################################################################################################\n##\n## Xilinx, Inc. 2"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/constrs_1/imports/new/genesys2.xdc",
"chars": 5569,
"preview": "set_property PACKAGE_PIN AA20 [get_ports {hdmi_clk[1]}]\nset_property IOSTANDARD TMDS_33 [get_ports {hdmi_clk[1]}]\nset_pr"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.v",
"chars": 4097,
"preview": "\n// file: camera_pll.v\n// \n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n// \n// This file contains conf"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.xci",
"chars": 83037,
"preview": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<spirit:design xmlns:xilinx=\"http://www.xilinx.com\" xmlns:spirit=\"http://www.spir"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll.xdc",
"chars": 2645,
"preview": "\n# file: camera_pll.xdc\n# \n# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n# \n# This file contains confide"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_board.xdc",
"chars": 60,
"preview": "#--------------------Physical Constraints-----------------\n\n"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_clk_wiz.v",
"chars": 7375,
"preview": "\n// file: camera_pll.v\n// \n// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n// \n// This file contains conf"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_ooc.xdc",
"chars": 2482,
"preview": "\n# file: camera_pll_ooc.xdc\n# \n# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.\n# \n# This file contains con"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_sim_netlist.v",
"chars": 7437,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/camera_pll_1/camera_pll_stub.v",
"chars": 1233,
"preview": "// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.\n// ------------------------------------------------------------"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if/mig_a.prj",
"chars": 12670,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if/mig_b.prj",
"chars": 12812,
"preview": "<?xml version='1.0' encoding='UTF-8'?>\n<!-- IMPORTANT: This is an internal file that has been generated by the MIG softw"
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/constraints/ddr3_if.xdc",
"chars": 26402,
"preview": "##################################################################################################\n## \n## Xilinx, Inc. "
},
{
"path": "vhdl_rx/examples/ov13850_demo/ov13850_demo.srcs/sources_1/ip/ddr3_if_1/ddr3_if/user_design/constraints/ddr3_if_ooc.xdc",
"chars": 1694,
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]
// ... and 150 more files (download for full content)
About this extraction
This page contains the full source code of the daveshah1/CSI2Rx GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 350 files (52.1 MB), approximately 6.2M tokens, and a symbol index with 13 extracted functions, classes, methods, constants, and types. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.
Extracted by GitExtract — free GitHub repo to text converter for AI. Built by Nikandr Surkov.