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Repository: gdevic/A-Z80
Branch: master
Commit: d70a4f9ab3b0
Files: 407
Total size: 7.1 MB
Directory structure:
gitextract_gd2ymr2z/
├── .gitignore
├── cpu/
│ ├── alu/
│ │ ├── alu.bdf
│ │ ├── alu.bsf
│ │ ├── alu.v
│ │ ├── alu_bit_select.bdf
│ │ ├── alu_bit_select.bsf
│ │ ├── alu_bit_select.v
│ │ ├── alu_control.bdf
│ │ ├── alu_control.bsf
│ │ ├── alu_control.v
│ │ ├── alu_core.bdf
│ │ ├── alu_core.bsf
│ │ ├── alu_core.v
│ │ ├── alu_flags.bdf
│ │ ├── alu_flags.bsf
│ │ ├── alu_flags.v
│ │ ├── alu_mux_2.bdf
│ │ ├── alu_mux_2.bsf
│ │ ├── alu_mux_2.v
│ │ ├── alu_mux_2z.bdf
│ │ ├── alu_mux_2z.bsf
│ │ ├── alu_mux_2z.v
│ │ ├── alu_mux_3z.bdf
│ │ ├── alu_mux_3z.bsf
│ │ ├── alu_mux_3z.v
│ │ ├── alu_mux_4.bdf
│ │ ├── alu_mux_4.bsf
│ │ ├── alu_mux_4.v
│ │ ├── alu_mux_8.bdf
│ │ ├── alu_mux_8.bsf
│ │ ├── alu_mux_8.v
│ │ ├── alu_prep_daa.bdf
│ │ ├── alu_prep_daa.bsf
│ │ ├── alu_prep_daa.v
│ │ ├── alu_select.bdf
│ │ ├── alu_select.bsf
│ │ ├── alu_select.v
│ │ ├── alu_shifter_core.bdf
│ │ ├── alu_shifter_core.bsf
│ │ ├── alu_shifter_core.v
│ │ ├── alu_slice.bdf
│ │ ├── alu_slice.bsf
│ │ ├── alu_slice.v
│ │ ├── simulation/
│ │ │ └── modelsim/
│ │ │ ├── r
│ │ │ ├── test_alu.mpf
│ │ │ ├── wave_alu.do
│ │ │ ├── wave_core.do
│ │ │ ├── wave_mux_3z.do
│ │ │ ├── wave_prep_daa.do
│ │ │ ├── wave_shifter_core.do
│ │ │ └── wave_slice.do
│ │ ├── test_alu.qpf
│ │ ├── test_alu.qsf
│ │ ├── test_alu.sv
│ │ ├── test_core.sv
│ │ ├── test_mux_3z.sv
│ │ ├── test_prep_daa.sv
│ │ ├── test_shifter_core.sv
│ │ └── test_slice.sv
│ ├── bus/
│ │ ├── address_latch.bdf
│ │ ├── address_latch.bsf
│ │ ├── address_latch.v
│ │ ├── address_mux.bdf
│ │ ├── address_mux.bsf
│ │ ├── address_mux.v
│ │ ├── address_pins.bdf
│ │ ├── address_pins.bsf
│ │ ├── address_pins.v
│ │ ├── bus_control.bdf
│ │ ├── bus_control.bsf
│ │ ├── bus_control.v
│ │ ├── bus_switch.bsf
│ │ ├── bus_switch.v
│ │ ├── control_pins_n.bdf
│ │ ├── control_pins_n.bsf
│ │ ├── control_pins_n.v
│ │ ├── data_pins.bdf
│ │ ├── data_pins.bsf
│ │ ├── data_pins.v
│ │ ├── data_pins_lattice.v
│ │ ├── data_switch.bdf
│ │ ├── data_switch.bsf
│ │ ├── data_switch.v
│ │ ├── data_switch_mask.bdf
│ │ ├── data_switch_mask.bsf
│ │ ├── data_switch_mask.v
│ │ ├── inc_dec.bdf
│ │ ├── inc_dec.bsf
│ │ ├── inc_dec.v
│ │ ├── inc_dec_2bit.bdf
│ │ ├── inc_dec_2bit.bsf
│ │ ├── inc_dec_2bit.v
│ │ ├── simulation/
│ │ │ └── modelsim/
│ │ │ ├── r
│ │ │ ├── test_bus.mpf
│ │ │ ├── wave_bus.do
│ │ │ └── wave_pins.do
│ │ ├── test_bus.qpf
│ │ ├── test_bus.qsf
│ │ ├── test_bus.sv
│ │ └── test_pins.sv
│ ├── control/
│ │ ├── Timings.csv
│ │ ├── Timings.xlsm
│ │ ├── clk_delay.bdf
│ │ ├── clk_delay.bsf
│ │ ├── clk_delay.v
│ │ ├── decode_state.bdf
│ │ ├── decode_state.bsf
│ │ ├── decode_state.v
│ │ ├── exec_matrix.vh
│ │ ├── exec_matrix_compiled.vh
│ │ ├── exec_module.vh
│ │ ├── exec_zero.vh
│ │ ├── execute.bsf
│ │ ├── execute.v
│ │ ├── gencompile.py
│ │ ├── genmatrix.py
│ │ ├── genref.py
│ │ ├── interrupts.bdf
│ │ ├── interrupts.bsf
│ │ ├── interrupts.v
│ │ ├── ir.bdf
│ │ ├── ir.bsf
│ │ ├── ir.v
│ │ ├── memory_ifc.bdf
│ │ ├── memory_ifc.bsf
│ │ ├── memory_ifc.v
│ │ ├── pin_control.bdf
│ │ ├── pin_control.bsf
│ │ ├── pin_control.v
│ │ ├── pla_decode.bsf
│ │ ├── pla_decode.v
│ │ ├── resets.bdf
│ │ ├── resets.bsf
│ │ ├── resets.v
│ │ ├── sequencer.bdf
│ │ ├── sequencer.bsf
│ │ ├── sequencer.v
│ │ ├── simulation/
│ │ │ └── modelsim/
│ │ │ ├── r
│ │ │ ├── test_control.mpf
│ │ │ ├── wave_interrupts.do
│ │ │ ├── wave_pin_control.do
│ │ │ ├── wave_reset.do
│ │ │ └── wave_sequencer.do
│ │ ├── temp_wires.vh
│ │ ├── test_control.qpf
│ │ ├── test_control.qsf
│ │ ├── test_decode.sv
│ │ ├── test_interrupts.sv
│ │ ├── test_pin_control.sv
│ │ ├── test_reset.sv
│ │ ├── test_sequencer.sv
│ │ └── timing_macros.i
│ ├── copyleft.txt
│ ├── export.py
│ ├── readme.txt
│ ├── registers/
│ │ ├── reg_control.bdf
│ │ ├── reg_control.bsf
│ │ ├── reg_control.v
│ │ ├── reg_file.bdf
│ │ ├── reg_file.bsf
│ │ ├── reg_file.v
│ │ ├── reg_latch.bdf
│ │ ├── reg_latch.bsf
│ │ ├── reg_latch.v
│ │ ├── simulation/
│ │ │ └── modelsim/
│ │ │ ├── r
│ │ │ ├── test_registers.mpf
│ │ │ ├── wave_latch.do
│ │ │ ├── wave_regfile.do
│ │ │ └── wave_registers.do
│ │ ├── test_latch.sv
│ │ ├── test_regfile.sv
│ │ ├── test_registers.qpf
│ │ ├── test_registers.qsf
│ │ └── test_registers.sv
│ ├── top-level-files.txt
│ └── toplevel/
│ ├── core.vh
│ ├── coremodules.vh
│ ├── fuse/
│ │ ├── README
│ │ ├── regress.expected
│ │ ├── regress.in
│ │ ├── tests.expected
│ │ └── tests.in
│ ├── gencoremodules.py
│ ├── genfuse.py
│ ├── genglobals.py
│ ├── globals.vh
│ ├── simulation/
│ │ └── modelsim/
│ │ ├── io.hex
│ │ ├── r
│ │ ├── ram.hexdump
│ │ ├── test_top.mpf
│ │ ├── wave_fuse.do
│ │ └── wave_top.do
│ ├── tb_io.sv
│ ├── tb_iorq.sv
│ ├── tb_ram.sv
│ ├── test_fuse.sv
│ ├── test_fuse.vh
│ ├── test_top.sv
│ ├── toplevel.bdf
│ ├── toplevel.qpf
│ ├── toplevel.qsf
│ ├── z80.svh
│ ├── z80_top_direct_n.v
│ └── z80_top_ifc_n.sv
├── docs/
│ ├── A-Z80_UsersGuide.docx
│ ├── QuickStart.docx
│ └── Spectrum-VGA-timings.xlsx
├── host/
│ ├── basic_de1/
│ │ ├── basic_de1.qpf
│ │ ├── basic_de1.qsf
│ │ ├── basic_de1.sdc
│ │ ├── basic_de1_ModelSim.sv
│ │ ├── basic_de1_fpga.sv
│ │ ├── fpga.hex
│ │ ├── pll.ppf
│ │ ├── pll.qip
│ │ ├── pll.v
│ │ ├── ram.qip
│ │ ├── ram.v
│ │ ├── readme.txt
│ │ ├── simulation/
│ │ │ └── modelsim/
│ │ │ ├── fpga.hex
│ │ │ ├── r
│ │ │ ├── test_host.mpf
│ │ │ └── wave_host.do
│ │ └── test_host.sv
│ ├── basic_nexys3/
│ │ ├── Nexys3_master.ucf
│ │ ├── basic_nexys3.xise
│ │ ├── basic_nexys3_fpga.v
│ │ ├── cscope.cdc
│ │ ├── ipcore_dir/
│ │ │ ├── clock/
│ │ │ │ ├── example_design/
│ │ │ │ │ ├── clock_exdes.ucf
│ │ │ │ │ ├── clock_exdes.v
│ │ │ │ │ └── clock_exdes.xdc
│ │ │ │ ├── implement/
│ │ │ │ │ ├── implement.bat
│ │ │ │ │ ├── implement.sh
│ │ │ │ │ ├── planAhead_ise.bat
│ │ │ │ │ ├── planAhead_ise.sh
│ │ │ │ │ ├── planAhead_ise.tcl
│ │ │ │ │ ├── planAhead_rdn.bat
│ │ │ │ │ ├── planAhead_rdn.sh
│ │ │ │ │ ├── planAhead_rdn.tcl
│ │ │ │ │ ├── xst.prj
│ │ │ │ │ └── xst.scr
│ │ │ │ └── simulation/
│ │ │ │ ├── clock_tb.v
│ │ │ │ ├── functional/
│ │ │ │ │ ├── simcmds.tcl
│ │ │ │ │ ├── simulate_isim.bat
│ │ │ │ │ ├── simulate_isim.sh
│ │ │ │ │ ├── simulate_mti.bat
│ │ │ │ │ ├── simulate_mti.do
│ │ │ │ │ ├── simulate_mti.sh
│ │ │ │ │ ├── simulate_ncsim.sh
│ │ │ │ │ ├── simulate_vcs.sh
│ │ │ │ │ ├── ucli_commands.key
│ │ │ │ │ ├── vcs_session.tcl
│ │ │ │ │ ├── wave.do
│ │ │ │ │ └── wave.sv
│ │ │ │ └── timing/
│ │ │ │ ├── clock_tb.v
│ │ │ │ ├── sdf_cmd_file
│ │ │ │ ├── simcmds.tcl
│ │ │ │ ├── simulate_isim.sh
│ │ │ │ ├── simulate_mti.bat
│ │ │ │ ├── simulate_mti.do
│ │ │ │ ├── simulate_mti.sh
│ │ │ │ ├── simulate_ncsim.sh
│ │ │ │ ├── simulate_vcs.sh
│ │ │ │ ├── ucli_commands.key
│ │ │ │ ├── vcs_session.tcl
│ │ │ │ └── wave.do
│ │ │ ├── clock.asy
│ │ │ ├── clock.gise
│ │ │ ├── clock.ucf
│ │ │ ├── clock.v
│ │ │ ├── clock.veo
│ │ │ ├── clock.xco
│ │ │ ├── clock.xise
│ │ │ ├── coregen.cgp
│ │ │ ├── ila.asy
│ │ │ ├── ila.cdc
│ │ │ ├── ila.constraints/
│ │ │ │ ├── ila.ucf
│ │ │ │ └── ila.xdc
│ │ │ ├── ila.gise
│ │ │ ├── ila.ncf
│ │ │ ├── ila.ngc
│ │ │ ├── ila.sym
│ │ │ ├── ila.ucf
│ │ │ ├── ila.v
│ │ │ ├── ila.veo
│ │ │ ├── ila.xco
│ │ │ ├── ila.xdc
│ │ │ ├── ila.xise
│ │ │ └── ila_xmdf.tcl
│ │ ├── ram.v
│ │ ├── readme.txt
│ │ ├── test_host.v
│ │ └── work/
│ │ └── ram.mif
│ ├── common/
│ │ ├── uart.v
│ │ ├── wait_state.bdf
│ │ ├── wait_state.bsf
│ │ └── wait_state.v
│ └── zxspectrum_de1/
│ ├── pll.ppf
│ ├── pll.qip
│ ├── pll.v
│ ├── ram16.qip
│ ├── ram16.v
│ ├── readme.txt
│ ├── rom/
│ │ ├── assemble.bat
│ │ ├── combined.rom
│ │ ├── gw03.rom
│ │ ├── readme.txt
│ │ ├── tasm80.tab
│ │ └── zxspectrum_rom.asm
│ ├── ula/
│ │ ├── clocks.sv
│ │ ├── i2c_loader.vhd
│ │ ├── i2s_intf.vhd
│ │ ├── pll.ppf
│ │ ├── pll.qip
│ │ ├── pll.v
│ │ ├── ps2_kbd.sv
│ │ ├── ram8.qip
│ │ ├── ram8.v
│ │ ├── test_scr.hex
│ │ ├── test_ula.qpf
│ │ ├── test_ula.qsf
│ │ ├── test_ula.sv
│ │ ├── ula.sv
│ │ ├── video.sv
│ │ └── zx_kbd.sv
│ ├── zxspectrum_de1.qpf
│ ├── zxspectrum_de1.qsf
│ ├── zxspectrum_de1.sdc
│ └── zxspectrum_de1.sv
├── license.txt
├── modelsim_pre_commit.py
├── modelsim_setup.py
├── readme.txt
├── resources/
│ ├── connotate-fuse.bat
│ ├── connotate-fuse.py
│ ├── opcodes-cb-xx.txt
│ ├── opcodes-dd-cb.txt
│ ├── opcodes-dd-xx.txt
│ ├── opcodes-ed-xx.txt
│ ├── opcodes-fd-cb.txt
│ ├── opcodes-fd-xx.txt
│ ├── opcodes-xx.txt
│ ├── process-pla.py
│ ├── title-custom-medium.bsf
│ ├── title-custom-small.bsf
│ ├── z80-pla-original.txt
│ └── z80-pla.txt
└── tools/
├── Arduino/
│ └── Z80_dongle/
│ └── Z80_dongle.ino
├── dongle/
│ ├── cb.html
│ ├── daa/
│ │ ├── daa-concise.txt
│ │ ├── daa_a-00.out
│ │ ├── daa_a-0c.out
│ │ ├── daa_a-h0.out
│ │ ├── daa_a-hc.out
│ │ ├── daa_s-00.out
│ │ ├── daa_s-0c.out
│ │ ├── daa_s-h0.out
│ │ ├── daa_s-hc.out
│ │ ├── simulate-daa.py
│ │ └── z80-instruction-test-daa.py
│ ├── dd.html
│ ├── ddcb.html
│ ├── ed.html
│ ├── neg/
│ │ ├── neg-concise.txt
│ │ ├── neg.out
│ │ ├── simulate-neg.py
│ │ └── z80-instruction-test-neg.py
│ ├── sbc/
│ │ ├── simulate-sbc.py
│ │ └── simulate-sub.py
│ ├── xx.html
│ ├── z80-instruction-run-cb.py
│ ├── z80-instruction-run-dd-cb.py
│ ├── z80-instruction-run-dd.py
│ ├── z80-instruction-run-ed.py
│ ├── z80-instruction-run-xx.py
│ └── z80-instruction-run.bat
├── readme.txt
├── z80_pla_checker/
│ ├── readme.txt
│ └── source/
│ ├── ClassLog.cs
│ ├── ClassOpcodeTable.cs
│ ├── ClassPLA.cs
│ ├── ClassPLAEntry.cs
│ ├── FormMain.Designer.cs
│ ├── FormMain.cs
│ ├── FormMain.resx
│ ├── Program.cs
│ ├── Properties/
│ │ ├── AssemblyInfo.cs
│ │ ├── Resources.Designer.cs
│ │ ├── Resources.resx
│ │ ├── Settings.Designer.cs
│ │ └── Settings.settings
│ ├── app.config
│ ├── z80_pla_checker.csproj
│ └── z80_pla_checker.sln
└── zmac/
├── bin2coe.py
├── bin2hex.txt
├── bin2mif.py
├── bindump.py
├── hello_world.asm
├── make_fpga.bat
├── make_modelsim.bat
├── readme.txt
├── test.daa.asm
├── test.neg.asm
├── zexall.asm
├── zexdoc.asm
└── zmac.html
================================================
FILE CONTENTS
================================================
================================================
FILE: .gitignore
================================================
# Quartus generated files and folders
*.rpt
*.done
*.rpt
*.smsg
*.summary
*.ddb
db/
incremental_db/
out/
output_files/
greybox_tmp/
# Quartus workspace file: stores window position, dock state etc.
*.qws
# ModelSim files and folders
transcript
*.mti
*.wlf
_*
_temp/
_primary.*
*.prw
*.psm
*.vstf
mgc_location_map
# Generic backup files
*~
*.bak
# Visual Studio temporary files
*.suo
*.tss
*.user
obj/
Debug/
Release/
*.DotSettings
# ZMAC assembler output directory
zout/
================================================
FILE: cpu/alu/alu.bdf
================================================
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(section (rect 130 0 320 20)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu" (rect 43 2 70 21)(font "Arial" (font_size 12)(bold)))(border))
(section (rect 0 21 320 40)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 151 19)(font "Arial" (font_size 11)))(border))
(section (rect 0 41 240 60)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 18, 2014" (rect 56 3 149 19)(font "Arial" (font_size 10)))(border))
(section (rect 241 41 320 60)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.4" (rect 43 3 64 19)(font "Arial" (font_size 10)))(border))
(drawing
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)
================================================
FILE: cpu/alu/alu.bsf
================================================
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 272 464)
(text "alu" (rect 5 0 21 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 432 25 444)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "alu_oe" (rect 0 0 37 14)(font "Arial" (font_size 8)))
(text "alu_oe" (rect 21 27 58 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "alu_shift_in" (rect 0 0 64 14)(font "Arial" (font_size 8)))
(text "alu_shift_in" (rect 21 43 85 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "alu_shift_left" (rect 0 0 73 14)(font "Arial" (font_size 8)))
(text "alu_shift_left" (rect 21 59 94 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 0 80)
(input)
(text "alu_shift_right" (rect 0 0 80 14)(font "Arial" (font_size 8)))
(text "alu_shift_right" (rect 21 75 101 89)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80))
)
(port
(pt 0 96)
(input)
(text "alu_core_R" (rect 0 0 64 14)(font "Arial" (font_size 8)))
(text "alu_core_R" (rect 21 91 85 105)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96))
)
(port
(pt 0 112)
(input)
(text "alu_core_V" (rect 0 0 66 14)(font "Arial" (font_size 8)))
(text "alu_core_V" (rect 21 107 87 121)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 16 112))
)
(port
(pt 0 128)
(input)
(text "alu_core_S" (rect 0 0 64 14)(font "Arial" (font_size 8)))
(text "alu_core_S" (rect 21 123 85 137)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 16 128))
)
(port
(pt 0 144)
(input)
(text "alu_bs_oe" (rect 0 0 59 14)(font "Arial" (font_size 8)))
(text "alu_bs_oe" (rect 21 139 80 153)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 16 144))
)
(port
(pt 0 160)
(input)
(text "alu_parity_in" (rect 0 0 71 14)(font "Arial" (font_size 8)))
(text "alu_parity_in" (rect 21 155 92 169)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 16 160))
)
(port
(pt 0 176)
(input)
(text "alu_shift_oe" (rect 0 0 69 14)(font "Arial" (font_size 8)))
(text "alu_shift_oe" (rect 21 171 90 185)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 16 176))
)
(port
(pt 0 192)
(input)
(text "alu_core_cf_in" (rect 0 0 84 14)(font "Arial" (font_size 8)))
(text "alu_core_cf_in" (rect 21 187 105 201)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 16 192))
)
(port
(pt 0 208)
(input)
(text "alu_op2_oe" (rect 0 0 66 14)(font "Arial" (font_size 8)))
(text "alu_op2_oe" (rect 21 203 87 217)(font "Arial" (font_size 8)))
(line (pt 0 208)(pt 16 208))
)
(port
(pt 0 224)
(input)
(text "alu_op1_oe" (rect 0 0 66 14)(font "Arial" (font_size 8)))
(text "alu_op1_oe" (rect 21 219 87 233)(font "Arial" (font_size 8)))
(line (pt 0 224)(pt 16 224))
)
(port
(pt 0 240)
(input)
(text "alu_res_oe" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "alu_res_oe" (rect 21 235 84 249)(font "Arial" (font_size 8)))
(line (pt 0 240)(pt 16 240))
)
(port
(pt 0 256)
(input)
(text "alu_op1_sel_low" (rect 0 0 96 14)(font "Arial" (font_size 8)))
(text "alu_op1_sel_low" (rect 21 251 117 265)(font "Arial" (font_size 8)))
(line (pt 0 256)(pt 16 256))
)
(port
(pt 0 272)
(input)
(text "alu_op1_sel_zero" (rect 0 0 101 14)(font "Arial" (font_size 8)))
(text "alu_op1_sel_zero" (rect 21 267 122 281)(font "Arial" (font_size 8)))
(line (pt 0 272)(pt 16 272))
)
(port
(pt 0 288)
(input)
(text "alu_op1_sel_bus" (rect 0 0 96 14)(font "Arial" (font_size 8)))
(text "alu_op1_sel_bus" (rect 21 283 117 297)(font "Arial" (font_size 8)))
(line (pt 0 288)(pt 16 288))
)
(port
(pt 0 304)
(input)
(text "alu_op2_sel_zero" (rect 0 0 101 14)(font "Arial" (font_size 8)))
(text "alu_op2_sel_zero" (rect 21 299 122 313)(font "Arial" (font_size 8)))
(line (pt 0 304)(pt 16 304))
)
(port
(pt 0 320)
(input)
(text "alu_op2_sel_bus" (rect 0 0 96 14)(font "Arial" (font_size 8)))
(text "alu_op2_sel_bus" (rect 21 315 117 329)(font "Arial" (font_size 8)))
(line (pt 0 320)(pt 16 320))
)
(port
(pt 0 336)
(input)
(text "alu_op2_sel_lq" (rect 0 0 84 14)(font "Arial" (font_size 8)))
(text "alu_op2_sel_lq" (rect 21 331 105 345)(font "Arial" (font_size 8)))
(line (pt 0 336)(pt 16 336))
)
(port
(pt 0 352)
(input)
(text "alu_op_low" (rect 0 0 66 14)(font "Arial" (font_size 8)))
(text "alu_op_low" (rect 21 347 87 361)(font "Arial" (font_size 8)))
(line (pt 0 352)(pt 16 352))
)
(port
(pt 0 368)
(input)
(text "alu_sel_op2_neg" (rect 0 0 96 14)(font "Arial" (font_size 8)))
(text "alu_sel_op2_neg" (rect 21 363 117 377)(font "Arial" (font_size 8)))
(line (pt 0 368)(pt 16 368))
)
(port
(pt 0 384)
(input)
(text "alu_sel_op2_high" (rect 0 0 99 14)(font "Arial" (font_size 8)))
(text "alu_sel_op2_high" (rect 21 379 120 393)(font "Arial" (font_size 8)))
(line (pt 0 384)(pt 16 384))
)
(port
(pt 0 400)
(input)
(text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "clk" (rect 21 395 36 409)(font "Arial" (font_size 8)))
(line (pt 0 400)(pt 16 400))
)
(port
(pt 0 416)
(input)
(text "bsel[2..0]" (rect 0 0 51 14)(font "Arial" (font_size 8)))
(text "bsel[2..0]" (rect 21 411 72 425)(font "Arial" (font_size 8)))
(line (pt 0 416)(pt 16 416)(line_width 3))
)
(port
(pt 256 32)
(output)
(text "alu_zero" (rect 0 0 49 14)(font "Arial" (font_size 8)))
(text "alu_zero" (rect 186 27 235 41)(font "Arial" (font_size 8)))
(line (pt 256 32)(pt 240 32))
)
(port
(pt 256 48)
(output)
(text "alu_parity_out" (rect 0 0 80 14)(font "Arial" (font_size 8)))
(text "alu_parity_out" (rect 155 43 235 57)(font "Arial" (font_size 8)))
(line (pt 256 48)(pt 240 48))
)
(port
(pt 256 64)
(output)
(text "alu_high_eq_9" (rect 0 0 82 14)(font "Arial" (font_size 8)))
(text "alu_high_eq_9" (rect 153 59 235 73)(font "Arial" (font_size 8)))
(line (pt 256 64)(pt 240 64))
)
(port
(pt 256 80)
(output)
(text "alu_high_gt_9" (rect 0 0 79 14)(font "Arial" (font_size 8)))
(text "alu_high_gt_9" (rect 156 75 235 89)(font "Arial" (font_size 8)))
(line (pt 256 80)(pt 240 80))
)
(port
(pt 256 96)
(output)
(text "alu_low_gt_9" (rect 0 0 76 14)(font "Arial" (font_size 8)))
(text "alu_low_gt_9" (rect 159 91 235 105)(font "Arial" (font_size 8)))
(line (pt 256 96)(pt 240 96))
)
(port
(pt 256 112)
(output)
(text "alu_shift_db0" (rect 0 0 76 14)(font "Arial" (font_size 8)))
(text "alu_shift_db0" (rect 159 107 235 121)(font "Arial" (font_size 8)))
(line (pt 256 112)(pt 240 112))
)
(port
(pt 256 128)
(output)
(text "alu_shift_db7" (rect 0 0 76 14)(font "Arial" (font_size 8)))
(text "alu_shift_db7" (rect 159 123 235 137)(font "Arial" (font_size 8)))
(line (pt 256 128)(pt 240 128))
)
(port
(pt 256 144)
(output)
(text "alu_core_cf_out" (rect 0 0 93 14)(font "Arial" (font_size 8)))
(text "alu_core_cf_out" (rect 142 139 235 153)(font "Arial" (font_size 8)))
(line (pt 256 144)(pt 240 144))
)
(port
(pt 256 160)
(output)
(text "alu_sf_out" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "alu_sf_out" (rect 175 155 235 169)(font "Arial" (font_size 8)))
(line (pt 256 160)(pt 240 160))
)
(port
(pt 256 176)
(output)
(text "alu_yf_out" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "alu_yf_out" (rect 175 171 235 185)(font "Arial" (font_size 8)))
(line (pt 256 176)(pt 240 176))
)
(port
(pt 256 192)
(output)
(text "alu_xf_out" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "alu_xf_out" (rect 175 187 235 201)(font "Arial" (font_size 8)))
(line (pt 256 192)(pt 240 192))
)
(port
(pt 256 208)
(output)
(text "alu_vf_out" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "alu_vf_out" (rect 175 203 235 217)(font "Arial" (font_size 8)))
(line (pt 256 208)(pt 240 208))
)
(port
(pt 256 224)
(output)
(text "test_db_low[3..0]" (rect 0 0 99 14)(font "Arial" (font_size 8)))
(text "test_db_low[3..0]" (rect 136 219 235 233)(font "Arial" (font_size 8)))
(line (pt 256 224)(pt 240 224)(line_width 3))
)
(port
(pt 256 256)
(output)
(text "test_db_high[3..0]" (rect 0 0 101 14)(font "Arial" (font_size 8)))
(text "test_db_high[3..0]" (rect 134 251 235 265)(font "Arial" (font_size 8)))
(line (pt 256 256)(pt 240 256)(line_width 3))
)
(port
(pt 256 240)
(bidir)
(text "db[7..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "db[7..0]" (rect 193 235 235 249)(font "Arial" (font_size 8)))
(line (pt 256 240)(pt 240 240)(line_width 3))
)
(drawing
(rectangle (rect 16 16 240 432))
)
)
================================================
FILE: cpu/alu/alu.v
================================================
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Fri Nov 07 19:44:45 2014"
module alu(
alu_core_R,
alu_core_V,
alu_core_S,
alu_bs_oe,
alu_parity_in,
alu_oe,
alu_shift_oe,
alu_core_cf_in,
alu_op2_oe,
alu_op1_oe,
alu_res_oe,
alu_op1_sel_low,
alu_op1_sel_zero,
alu_op1_sel_bus,
alu_op2_sel_zero,
alu_op2_sel_bus,
alu_op2_sel_lq,
alu_op_low,
alu_shift_in,
alu_sel_op2_neg,
alu_sel_op2_high,
alu_shift_left,
alu_shift_right,
clk,
bsel,
alu_zero,
alu_parity_out,
alu_high_eq_9,
alu_high_gt_9,
alu_low_gt_9,
alu_shift_db0,
alu_shift_db7,
alu_core_cf_out,
alu_sf_out,
alu_yf_out,
alu_xf_out,
alu_vf_out,
db,
test_db_high,
test_db_low
);
input wire alu_core_R;
input wire alu_core_V;
input wire alu_core_S;
input wire alu_bs_oe;
input wire alu_parity_in;
input wire alu_oe;
input wire alu_shift_oe;
input wire alu_core_cf_in;
input wire alu_op2_oe;
input wire alu_op1_oe;
input wire alu_res_oe;
input wire alu_op1_sel_low;
input wire alu_op1_sel_zero;
input wire alu_op1_sel_bus;
input wire alu_op2_sel_zero;
input wire alu_op2_sel_bus;
input wire alu_op2_sel_lq;
input wire alu_op_low;
input wire alu_shift_in;
input wire alu_sel_op2_neg;
input wire alu_sel_op2_high;
input wire alu_shift_left;
input wire alu_shift_right;
input wire clk;
input wire [2:0] bsel;
output wire alu_zero;
output wire alu_parity_out;
output wire alu_high_eq_9;
output wire alu_high_gt_9;
output wire alu_low_gt_9;
output wire alu_shift_db0;
output wire alu_shift_db7;
output wire alu_core_cf_out;
output wire alu_sf_out;
output wire alu_yf_out;
output wire alu_xf_out;
output wire alu_vf_out;
inout wire [7:0] db;
output wire [3:0] test_db_high;
output wire [3:0] test_db_low;
wire [3:0] alu_op1;
wire [3:0] alu_op2;
wire [3:0] db_high;
wire [3:0] db_low;
reg [3:0] op1_high;
reg [3:0] op1_low;
reg [3:0] op2_high;
reg [3:0] op2_low;
wire [3:0] result_hi;
reg [3:0] result_lo;
wire [3:0] SYNTHESIZED_WIRE_0;
wire [3:0] SYNTHESIZED_WIRE_1;
wire [3:0] SYNTHESIZED_WIRE_2;
wire [3:0] SYNTHESIZED_WIRE_3;
wire SYNTHESIZED_WIRE_35;
wire [3:0] SYNTHESIZED_WIRE_5;
wire [3:0] SYNTHESIZED_WIRE_7;
wire [3:0] SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
wire [3:0] SYNTHESIZED_WIRE_10;
wire [3:0] SYNTHESIZED_WIRE_11;
wire [3:0] SYNTHESIZED_WIRE_12;
wire [3:0] SYNTHESIZED_WIRE_13;
wire [3:0] SYNTHESIZED_WIRE_14;
wire [3:0] SYNTHESIZED_WIRE_15;
wire [3:0] SYNTHESIZED_WIRE_16;
wire SYNTHESIZED_WIRE_17;
wire [3:0] SYNTHESIZED_WIRE_18;
wire SYNTHESIZED_WIRE_36;
wire SYNTHESIZED_WIRE_20;
wire [3:0] SYNTHESIZED_WIRE_21;
wire SYNTHESIZED_WIRE_23;
wire [3:0] SYNTHESIZED_WIRE_24;
wire SYNTHESIZED_WIRE_37;
wire SYNTHESIZED_WIRE_26;
wire [3:0] SYNTHESIZED_WIRE_27;
wire SYNTHESIZED_WIRE_29;
wire SYNTHESIZED_WIRE_30;
wire SYNTHESIZED_WIRE_31;
wire SYNTHESIZED_WIRE_32;
wire [3:0] SYNTHESIZED_WIRE_33;
wire [3:0] SYNTHESIZED_WIRE_34;
assign db_low[3] = alu_bs_oe ? SYNTHESIZED_WIRE_0[3] : 1'bz;
assign db_low[2] = alu_bs_oe ? SYNTHESIZED_WIRE_0[2] : 1'bz;
assign db_low[1] = alu_bs_oe ? SYNTHESIZED_WIRE_0[1] : 1'bz;
assign db_low[0] = alu_bs_oe ? SYNTHESIZED_WIRE_0[0] : 1'bz;
assign db_high[3] = alu_bs_oe ? SYNTHESIZED_WIRE_1[3] : 1'bz;
assign db_high[2] = alu_bs_oe ? SYNTHESIZED_WIRE_1[2] : 1'bz;
assign db_high[1] = alu_bs_oe ? SYNTHESIZED_WIRE_1[1] : 1'bz;
assign db_high[0] = alu_bs_oe ? SYNTHESIZED_WIRE_1[0] : 1'bz;
alu_core b2v_core(
.cy_in(alu_core_cf_in),
.S(alu_core_S),
.V(alu_core_V),
.R(alu_core_R),
.op1(alu_op1),
.op2(alu_op2),
.cy_out(alu_core_cf_out),
.vf_out(alu_vf_out),
.result(result_hi));
assign db[3] = alu_oe ? db_low[3] : 1'bz;
assign db[2] = alu_oe ? db_low[2] : 1'bz;
assign db[1] = alu_oe ? db_low[1] : 1'bz;
assign db[0] = alu_oe ? db_low[0] : 1'bz;
assign db[7] = alu_oe ? db_high[3] : 1'bz;
assign db[6] = alu_oe ? db_high[2] : 1'bz;
assign db[5] = alu_oe ? db_high[1] : 1'bz;
assign db[4] = alu_oe ? db_high[0] : 1'bz;
alu_bit_select b2v_input_bit_select(
.bsel(bsel),
.bs_out_high(SYNTHESIZED_WIRE_1),
.bs_out_low(SYNTHESIZED_WIRE_0));
alu_shifter_core b2v_input_shift(
.shift_in(alu_shift_in),
.shift_left(alu_shift_left),
.shift_right(alu_shift_right),
.db(db),
.shift_db0(alu_shift_db0),
.shift_db7(alu_shift_db7),
.out_high(SYNTHESIZED_WIRE_34),
.out_low(SYNTHESIZED_WIRE_33));
always@(posedge clk)
begin
if (alu_op_low)
begin
result_lo[3:0] <= result_hi[3:0];
end
end
assign alu_op1 = SYNTHESIZED_WIRE_2 | SYNTHESIZED_WIRE_3;
assign SYNTHESIZED_WIRE_17 = ~alu_op_low;
assign db_low[3] = alu_op2_oe ? op2_low[3] : 1'bz;
assign db_low[2] = alu_op2_oe ? op2_low[2] : 1'bz;
assign db_low[1] = alu_op2_oe ? op2_low[1] : 1'bz;
assign db_low[0] = alu_op2_oe ? op2_low[0] : 1'bz;
assign db_high[3] = alu_op2_oe ? op2_high[3] : 1'bz;
assign db_high[2] = alu_op2_oe ? op2_high[2] : 1'bz;
assign db_high[1] = alu_op2_oe ? op2_high[1] : 1'bz;
assign db_high[0] = alu_op2_oe ? op2_high[0] : 1'bz;
assign SYNTHESIZED_WIRE_5 = ~op2_low;
assign SYNTHESIZED_WIRE_7 = ~op2_high;
assign SYNTHESIZED_WIRE_12 = op2_low & {SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35};
assign SYNTHESIZED_WIRE_11 = {alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg} & SYNTHESIZED_WIRE_5;
assign SYNTHESIZED_WIRE_14 = op2_high & {SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35,SYNTHESIZED_WIRE_35};
assign SYNTHESIZED_WIRE_13 = {alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg,alu_sel_op2_neg} & SYNTHESIZED_WIRE_7;
assign SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_8 & {SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9,SYNTHESIZED_WIRE_9};
assign SYNTHESIZED_WIRE_15 = {alu_sel_op2_high,alu_sel_op2_high,alu_sel_op2_high,alu_sel_op2_high} & SYNTHESIZED_WIRE_10;
assign SYNTHESIZED_WIRE_8 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12;
assign SYNTHESIZED_WIRE_10 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14;
assign alu_op2 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
assign SYNTHESIZED_WIRE_35 = ~alu_sel_op2_neg;
assign SYNTHESIZED_WIRE_9 = ~alu_sel_op2_high;
assign db_low[3] = alu_res_oe ? result_lo[3] : 1'bz;
assign db_low[2] = alu_res_oe ? result_lo[2] : 1'bz;
assign db_low[1] = alu_res_oe ? result_lo[1] : 1'bz;
assign db_low[0] = alu_res_oe ? result_lo[0] : 1'bz;
assign db_high[3] = alu_res_oe ? result_hi[3] : 1'bz;
assign db_high[2] = alu_res_oe ? result_hi[2] : 1'bz;
assign db_high[1] = alu_res_oe ? result_hi[1] : 1'bz;
assign db_high[0] = alu_res_oe ? result_hi[0] : 1'bz;
assign SYNTHESIZED_WIRE_3 = op1_low & {alu_op_low,alu_op_low,alu_op_low,alu_op_low};
assign SYNTHESIZED_WIRE_2 = {SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17,SYNTHESIZED_WIRE_17} & op1_high;
always@(posedge SYNTHESIZED_WIRE_36)
begin
if (SYNTHESIZED_WIRE_20)
begin
op1_high[3:0] <= SYNTHESIZED_WIRE_18[3:0];
end
end
always@(posedge SYNTHESIZED_WIRE_36)
begin
if (SYNTHESIZED_WIRE_23)
begin
op1_low[3:0] <= SYNTHESIZED_WIRE_21[3:0];
end
end
always@(posedge SYNTHESIZED_WIRE_37)
begin
if (SYNTHESIZED_WIRE_26)
begin
op2_high[3:0] <= SYNTHESIZED_WIRE_24[3:0];
end
end
always@(posedge SYNTHESIZED_WIRE_37)
begin
if (SYNTHESIZED_WIRE_29)
begin
op2_low[3:0] <= SYNTHESIZED_WIRE_27[3:0];
end
end
assign db_low[3] = alu_op1_oe ? op1_low[3] : 1'bz;
assign db_low[2] = alu_op1_oe ? op1_low[2] : 1'bz;
assign db_low[1] = alu_op1_oe ? op1_low[1] : 1'bz;
assign db_low[0] = alu_op1_oe ? op1_low[0] : 1'bz;
assign db_high[3] = alu_op1_oe ? op1_high[3] : 1'bz;
assign db_high[2] = alu_op1_oe ? op1_high[2] : 1'bz;
assign db_high[1] = alu_op1_oe ? op1_high[1] : 1'bz;
assign db_high[0] = alu_op1_oe ? op1_high[0] : 1'bz;
assign SYNTHESIZED_WIRE_36 = ~clk;
assign SYNTHESIZED_WIRE_37 = ~clk;
alu_mux_2z b2v_op1_latch_mux_high(
.sel_a(alu_op1_sel_bus),
.sel_zero(alu_op1_sel_zero),
.a(db_high),
.ena(SYNTHESIZED_WIRE_20),
.Q(SYNTHESIZED_WIRE_18));
alu_mux_3z b2v_op1_latch_mux_low(
.sel_a(alu_op1_sel_bus),
.sel_b(alu_op1_sel_low),
.sel_zero(alu_op1_sel_zero),
.a(db_low),
.b(db_high),
.ena(SYNTHESIZED_WIRE_23),
.Q(SYNTHESIZED_WIRE_21));
alu_mux_3z b2v_op2_latch_mux_high(
.sel_a(alu_op2_sel_bus),
.sel_b(alu_op2_sel_lq),
.sel_zero(alu_op2_sel_zero),
.a(db_high),
.b(db_low),
.ena(SYNTHESIZED_WIRE_26),
.Q(SYNTHESIZED_WIRE_24));
alu_mux_3z b2v_op2_latch_mux_low(
.sel_a(alu_op2_sel_bus),
.sel_b(alu_op2_sel_lq),
.sel_zero(alu_op2_sel_zero),
.a(db_low),
.b(alu_op1),
.ena(SYNTHESIZED_WIRE_29),
.Q(SYNTHESIZED_WIRE_27));
assign alu_parity_out = SYNTHESIZED_WIRE_30 ^ result_hi[0];
assign SYNTHESIZED_WIRE_30 = SYNTHESIZED_WIRE_31 ^ result_hi[1];
assign SYNTHESIZED_WIRE_31 = SYNTHESIZED_WIRE_32 ^ result_hi[2];
assign SYNTHESIZED_WIRE_32 = alu_parity_in ^ result_hi[3];
alu_prep_daa b2v_prep_daa(
.high(op1_high),
.low(op1_low),
.low_gt_9(alu_low_gt_9),
.high_gt_9(alu_high_gt_9),
.high_eq_9(alu_high_eq_9));
assign db_low[3] = alu_shift_oe ? SYNTHESIZED_WIRE_33[3] : 1'bz;
assign db_low[2] = alu_shift_oe ? SYNTHESIZED_WIRE_33[2] : 1'bz;
assign db_low[1] = alu_shift_oe ? SYNTHESIZED_WIRE_33[1] : 1'bz;
assign db_low[0] = alu_shift_oe ? SYNTHESIZED_WIRE_33[0] : 1'bz;
assign db_high[3] = alu_shift_oe ? SYNTHESIZED_WIRE_34[3] : 1'bz;
assign db_high[2] = alu_shift_oe ? SYNTHESIZED_WIRE_34[2] : 1'bz;
assign db_high[1] = alu_shift_oe ? SYNTHESIZED_WIRE_34[1] : 1'bz;
assign db_high[0] = alu_shift_oe ? SYNTHESIZED_WIRE_34[0] : 1'bz;
assign alu_zero = ~(db_low[2] | db_low[1] | db_low[3] | db_high[1] | db_high[0] | db_high[2] | db_low[0] | db_high[3]);
assign alu_sf_out = db_high[3];
assign alu_yf_out = db_high[1];
assign alu_xf_out = db_low[3];
assign test_db_high = db_high;
assign test_db_low = db_low;
endmodule
================================================
FILE: cpu/alu/alu_bit_select.bdf
================================================
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(junction (pt 632 240))
(junction (pt 632 336))
(junction (pt 632 384))
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(title_block
(rect 24 536 281 588)
(name "title-custom-small")
(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu_bit_select" (rect 43 2 137 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
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================================================
FILE: cpu/alu/alu_bit_select.bsf
================================================
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 216 112)
(text "alu_bit_select" (rect 5 0 82 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 80 25 92)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "bsel[2..0]" (rect 0 0 51 14)(font "Arial" (font_size 8)))
(text "bsel[2..0]" (rect 21 27 72 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 200 32)
(output)
(text "bs_out_low[3..0]" (rect 0 0 95 14)(font "Arial" (font_size 8)))
(text "bs_out_low[3..0]" (rect 84 27 179 41)(font "Arial" (font_size 8)))
(line (pt 200 32)(pt 184 32)(line_width 3))
)
(port
(pt 200 48)
(output)
(text "bs_out_high[3..0]" (rect 0 0 97 14)(font "Arial" (font_size 8)))
(text "bs_out_high[3..0]" (rect 82 43 179 57)(font "Arial" (font_size 8)))
(line (pt 200 48)(pt 184 48)(line_width 3))
)
(drawing
(rectangle (rect 16 16 184 80))
)
(fill (color 217 255 255))
)
================================================
FILE: cpu/alu/alu_bit_select.v
================================================
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Mon Oct 13 12:21:31 2014"
module alu_bit_select(
bsel,
bs_out_high,
bs_out_low
);
input wire [2:0] bsel;
output wire [3:0] bs_out_high;
output wire [3:0] bs_out_low;
wire [3:0] bs_out_high_ALTERA_SYNTHESIZED;
wire [3:0] bs_out_low_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
wire SYNTHESIZED_WIRE_14;
assign bs_out_low_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;
assign bs_out_low_ALTERA_SYNTHESIZED[1] = bsel[0] & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;
assign bs_out_low_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_12 & bsel[1] & SYNTHESIZED_WIRE_14;
assign bs_out_low_ALTERA_SYNTHESIZED[3] = bsel[0] & bsel[1] & SYNTHESIZED_WIRE_14;
assign bs_out_high_ALTERA_SYNTHESIZED[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & bsel[2];
assign bs_out_high_ALTERA_SYNTHESIZED[1] = bsel[0] & SYNTHESIZED_WIRE_13 & bsel[2];
assign bs_out_high_ALTERA_SYNTHESIZED[2] = SYNTHESIZED_WIRE_12 & bsel[1] & bsel[2];
assign bs_out_high_ALTERA_SYNTHESIZED[3] = bsel[0] & bsel[1] & bsel[2];
assign SYNTHESIZED_WIRE_12 = ~bsel[0];
assign SYNTHESIZED_WIRE_13 = ~bsel[1];
assign SYNTHESIZED_WIRE_14 = ~bsel[2];
assign bs_out_high = bs_out_high_ALTERA_SYNTHESIZED;
assign bs_out_low = bs_out_low_ALTERA_SYNTHESIZED;
endmodule
================================================
FILE: cpu/alu/alu_control.bdf
================================================
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(text "Bit that is shifted in depends on the opcode:" (rect 576 288 824 302)(font "Arial" (font_size 8)))
(text "000 RLC -> old D[7]" (rect 576 304 685 318)(font "Arial" (font_size 8)))
(text "001 RRC -> old D[0]" (rect 576 320 686 334)(font "Arial" (font_size 8)))
(text "010 RL -> CF" (rect 576 336 650 350)(font "Arial" (font_size 8)))
(text "011 RR -> CF" (rect 576 352 651 366)(font "Arial" (font_size 8)))
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(text "High nibble 0x6" (rect 432 912 518 926)(font "Arial" (font_size 8)))
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(text "Half-parity control" (rect 352 1104 471 1120)(font "Arial" (font_size 10)))
(text "Flag condition mux" (rect 440 536 569 552)(font "Arial" (font_size 10)))
(text "Parity / Overflow input selector" (rect 336 1328 543 1344)(font "Arial" (font_size 10)))
(text "Mux: when op is low, \"1\"; else pf_tmp" (rect 432 1192 647 1206)(font "Arial" (font_size 8)))
(text "Carry flag into ALU core" (rect 352 1520 514 1536)(font "Arial" (font_size 10)))
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(section (rect 0 0 256 17)(text "PROJECT" (rect 2 0 52 12)(font "Arial" ))(text "A-Z80" (rect 56 2 94 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 104 0 256 17)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "alu_control" (rect 43 2 118 17)(font "Arial" (font_size 9)(bold)))(border))
(section (rect 0 18 256 34)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 135 17)(font "Arial" (font_size 9)))(border))
(section (rect 0 35 256 51)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "June 28, 2014" (rect 56 3 136 17)(font "Arial" (font_size 8)))(border))
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)
)
================================================
FILE: cpu/alu/alu_control.bsf
================================================
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 248 496)
(text "alu_control" (rect 5 0 67 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 464 25 476)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "alu_shift_db7" (rect 0 0 76 14)(font "Arial" (font_size 8)))
(text "alu_shift_db7" (rect 21 27 97 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "alu_shift_db0" (rect 0 0 76 14)(font "Arial" (font_size 8)))
(text "alu_shift_db0" (rect 21 43 97 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
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(input)
(text "ctl_shift_en" (rect 0 0 66 14)(font "Arial" (font_size 8)))
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(line (pt 0 64)(pt 16 64))
)
(port
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(input)
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(line (pt 0 80)(pt 16 80)(line_width 3))
)
(port
(pt 0 96)
(input)
(text "flags_cf_latch" (rect 0 0 81 14)(font "Arial" (font_size 8)))
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)
(port
(pt 0 112)
(input)
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(line (pt 0 112)(pt 16 112))
)
(port
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(port
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)
(port
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)
(port
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(input)
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(line (pt 0 176)(pt 16 176))
)
(port
(pt 0 192)
(input)
(text "ctl_eval_cond" (rect 0 0 79 14)(font "Arial" (font_size 8)))
(text "ctl_eval_cond" (rect 21 187 100 201)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 16 192))
)
gitextract_gd2ymr2z/
├── .gitignore
├── cpu/
│ ├── alu/
│ │ ├── alu.bdf
│ │ ├── alu.bsf
│ │ ├── alu.v
│ │ ├── alu_bit_select.bdf
│ │ ├── alu_bit_select.bsf
│ │ ├── alu_bit_select.v
│ │ ├── alu_control.bdf
│ │ ├── alu_control.bsf
│ │ ├── alu_control.v
│ │ ├── alu_core.bdf
│ │ ├── alu_core.bsf
│ │ ├── alu_core.v
│ │ ├── alu_flags.bdf
│ │ ├── alu_flags.bsf
│ │ ├── alu_flags.v
│ │ ├── alu_mux_2.bdf
│ │ ├── alu_mux_2.bsf
│ │ ├── alu_mux_2.v
│ │ ├── alu_mux_2z.bdf
│ │ ├── alu_mux_2z.bsf
│ │ ├── alu_mux_2z.v
│ │ ├── alu_mux_3z.bdf
│ │ ├── alu_mux_3z.bsf
│ │ ├── alu_mux_3z.v
│ │ ├── alu_mux_4.bdf
│ │ ├── alu_mux_4.bsf
│ │ ├── alu_mux_4.v
│ │ ├── alu_mux_8.bdf
│ │ ├── alu_mux_8.bsf
│ │ ├── alu_mux_8.v
│ │ ├── alu_prep_daa.bdf
│ │ ├── alu_prep_daa.bsf
│ │ ├── alu_prep_daa.v
│ │ ├── alu_select.bdf
│ │ ├── alu_select.bsf
│ │ ├── alu_select.v
│ │ ├── alu_shifter_core.bdf
│ │ ├── alu_shifter_core.bsf
│ │ ├── alu_shifter_core.v
│ │ ├── alu_slice.bdf
│ │ ├── alu_slice.bsf
│ │ ├── alu_slice.v
│ │ ├── simulation/
│ │ │ └── modelsim/
│ │ │ ├── r
│ │ │ ├── test_alu.mpf
│ │ │ ├── wave_alu.do
│ │ │ ├── wave_core.do
│ │ │ ├── wave_mux_3z.do
│ │ │ ├── wave_prep_daa.do
│ │ │ ├── wave_shifter_core.do
│ │ │ └── wave_slice.do
│ │ ├── test_alu.qpf
│ │ ├── test_alu.qsf
│ │ ├── test_alu.sv
│ │ ├── test_core.sv
│ │ ├── test_mux_3z.sv
│ │ ├── test_prep_daa.sv
│ │ ├── test_shifter_core.sv
│ │ └── test_slice.sv
│ ├── bus/
│ │ ├── address_latch.bdf
│ │ ├── address_latch.bsf
│ │ ├── address_latch.v
│ │ ├── address_mux.bdf
│ │ ├── address_mux.bsf
│ │ ├── address_mux.v
│ │ ├── address_pins.bdf
│ │ ├── address_pins.bsf
│ │ ├── address_pins.v
│ │ ├── bus_control.bdf
│ │ ├── bus_control.bsf
│ │ ├── bus_control.v
│ │ ├── bus_switch.bsf
│ │ ├── bus_switch.v
│ │ ├── control_pins_n.bdf
│ │ ├── control_pins_n.bsf
│ │ ├── control_pins_n.v
│ │ ├── data_pins.bdf
│ │ ├── data_pins.bsf
│ │ ├── data_pins.v
│ │ ├── data_pins_lattice.v
│ │ ├── data_switch.bdf
│ │ ├── data_switch.bsf
│ │ ├── data_switch.v
│ │ ├── data_switch_mask.bdf
│ │ ├── data_switch_mask.bsf
│ │ ├── data_switch_mask.v
│ │ ├── inc_dec.bdf
│ │ ├── inc_dec.bsf
│ │ ├── inc_dec.v
│ │ ├── inc_dec_2bit.bdf
│ │ ├── inc_dec_2bit.bsf
│ │ ├── inc_dec_2bit.v
│ │ ├── simulation/
│ │ │ └── modelsim/
│ │ │ ├── r
│ │ │ ├── test_bus.mpf
│ │ │ ├── wave_bus.do
│ │ │ └── wave_pins.do
│ │ ├── test_bus.qpf
│ │ ├── test_bus.qsf
│ │ ├── test_bus.sv
│ │ └── test_pins.sv
│ ├── control/
│ │ ├── Timings.csv
│ │ ├── Timings.xlsm
│ │ ├── clk_delay.bdf
│ │ ├── clk_delay.bsf
│ │ ├── clk_delay.v
│ │ ├── decode_state.bdf
│ │ ├── decode_state.bsf
│ │ ├── decode_state.v
│ │ ├── exec_matrix.vh
│ │ ├── exec_matrix_compiled.vh
│ │ ├── exec_module.vh
│ │ ├── exec_zero.vh
│ │ ├── execute.bsf
│ │ ├── execute.v
│ │ ├── gencompile.py
│ │ ├── genmatrix.py
│ │ ├── genref.py
│ │ ├── interrupts.bdf
│ │ ├── interrupts.bsf
│ │ ├── interrupts.v
│ │ ├── ir.bdf
│ │ ├── ir.bsf
│ │ ├── ir.v
│ │ ├── memory_ifc.bdf
│ │ ├── memory_ifc.bsf
│ │ ├── memory_ifc.v
│ │ ├── pin_control.bdf
│ │ ├── pin_control.bsf
│ │ ├── pin_control.v
│ │ ├── pla_decode.bsf
│ │ ├── pla_decode.v
│ │ ├── resets.bdf
│ │ ├── resets.bsf
│ │ ├── resets.v
│ │ ├── sequencer.bdf
│ │ ├── sequencer.bsf
│ │ ├── sequencer.v
│ │ ├── simulation/
│ │ │ └── modelsim/
│ │ │ ├── r
│ │ │ ├── test_control.mpf
│ │ │ ├── wave_interrupts.do
│ │ │ ├── wave_pin_control.do
│ │ │ ├── wave_reset.do
│ │ │ └── wave_sequencer.do
│ │ ├── temp_wires.vh
│ │ ├── test_control.qpf
│ │ ├── test_control.qsf
│ │ ├── test_decode.sv
│ │ ├── test_interrupts.sv
│ │ ├── test_pin_control.sv
│ │ ├── test_reset.sv
│ │ ├── test_sequencer.sv
│ │ └── timing_macros.i
│ ├── copyleft.txt
│ ├── export.py
│ ├── readme.txt
│ ├── registers/
│ │ ├── reg_control.bdf
│ │ ├── reg_control.bsf
│ │ ├── reg_control.v
│ │ ├── reg_file.bdf
│ │ ├── reg_file.bsf
│ │ ├── reg_file.v
│ │ ├── reg_latch.bdf
│ │ ├── reg_latch.bsf
│ │ ├── reg_latch.v
│ │ ├── simulation/
│ │ │ └── modelsim/
│ │ │ ├── r
│ │ │ ├── test_registers.mpf
│ │ │ ├── wave_latch.do
│ │ │ ├── wave_regfile.do
│ │ │ └── wave_registers.do
│ │ ├── test_latch.sv
│ │ ├── test_regfile.sv
│ │ ├── test_registers.qpf
│ │ ├── test_registers.qsf
│ │ └── test_registers.sv
│ ├── top-level-files.txt
│ └── toplevel/
│ ├── core.vh
│ ├── coremodules.vh
│ ├── fuse/
│ │ ├── README
│ │ ├── regress.expected
│ │ ├── regress.in
│ │ ├── tests.expected
│ │ └── tests.in
│ ├── gencoremodules.py
│ ├── genfuse.py
│ ├── genglobals.py
│ ├── globals.vh
│ ├── simulation/
│ │ └── modelsim/
│ │ ├── io.hex
│ │ ├── r
│ │ ├── ram.hexdump
│ │ ├── test_top.mpf
│ │ ├── wave_fuse.do
│ │ └── wave_top.do
│ ├── tb_io.sv
│ ├── tb_iorq.sv
│ ├── tb_ram.sv
│ ├── test_fuse.sv
│ ├── test_fuse.vh
│ ├── test_top.sv
│ ├── toplevel.bdf
│ ├── toplevel.qpf
│ ├── toplevel.qsf
│ ├── z80.svh
│ ├── z80_top_direct_n.v
│ └── z80_top_ifc_n.sv
├── docs/
│ ├── A-Z80_UsersGuide.docx
│ ├── QuickStart.docx
│ └── Spectrum-VGA-timings.xlsx
├── host/
│ ├── basic_de1/
│ │ ├── basic_de1.qpf
│ │ ├── basic_de1.qsf
│ │ ├── basic_de1.sdc
│ │ ├── basic_de1_ModelSim.sv
│ │ ├── basic_de1_fpga.sv
│ │ ├── fpga.hex
│ │ ├── pll.ppf
│ │ ├── pll.qip
│ │ ├── pll.v
│ │ ├── ram.qip
│ │ ├── ram.v
│ │ ├── readme.txt
│ │ ├── simulation/
│ │ │ └── modelsim/
│ │ │ ├── fpga.hex
│ │ │ ├── r
│ │ │ ├── test_host.mpf
│ │ │ └── wave_host.do
│ │ └── test_host.sv
│ ├── basic_nexys3/
│ │ ├── Nexys3_master.ucf
│ │ ├── basic_nexys3.xise
│ │ ├── basic_nexys3_fpga.v
│ │ ├── cscope.cdc
│ │ ├── ipcore_dir/
│ │ │ ├── clock/
│ │ │ │ ├── example_design/
│ │ │ │ │ ├── clock_exdes.ucf
│ │ │ │ │ ├── clock_exdes.v
│ │ │ │ │ └── clock_exdes.xdc
│ │ │ │ ├── implement/
│ │ │ │ │ ├── implement.bat
│ │ │ │ │ ├── implement.sh
│ │ │ │ │ ├── planAhead_ise.bat
│ │ │ │ │ ├── planAhead_ise.sh
│ │ │ │ │ ├── planAhead_ise.tcl
│ │ │ │ │ ├── planAhead_rdn.bat
│ │ │ │ │ ├── planAhead_rdn.sh
│ │ │ │ │ ├── planAhead_rdn.tcl
│ │ │ │ │ ├── xst.prj
│ │ │ │ │ └── xst.scr
│ │ │ │ └── simulation/
│ │ │ │ ├── clock_tb.v
│ │ │ │ ├── functional/
│ │ │ │ │ ├── simcmds.tcl
│ │ │ │ │ ├── simulate_isim.bat
│ │ │ │ │ ├── simulate_isim.sh
│ │ │ │ │ ├── simulate_mti.bat
│ │ │ │ │ ├── simulate_mti.do
│ │ │ │ │ ├── simulate_mti.sh
│ │ │ │ │ ├── simulate_ncsim.sh
│ │ │ │ │ ├── simulate_vcs.sh
│ │ │ │ │ ├── ucli_commands.key
│ │ │ │ │ ├── vcs_session.tcl
│ │ │ │ │ ├── wave.do
│ │ │ │ │ └── wave.sv
│ │ │ │ └── timing/
│ │ │ │ ├── clock_tb.v
│ │ │ │ ├── sdf_cmd_file
│ │ │ │ ├── simcmds.tcl
│ │ │ │ ├── simulate_isim.sh
│ │ │ │ ├── simulate_mti.bat
│ │ │ │ ├── simulate_mti.do
│ │ │ │ ├── simulate_mti.sh
│ │ │ │ ├── simulate_ncsim.sh
│ │ │ │ ├── simulate_vcs.sh
│ │ │ │ ├── ucli_commands.key
│ │ │ │ ├── vcs_session.tcl
│ │ │ │ └── wave.do
│ │ │ ├── clock.asy
│ │ │ ├── clock.gise
│ │ │ ├── clock.ucf
│ │ │ ├── clock.v
│ │ │ ├── clock.veo
│ │ │ ├── clock.xco
│ │ │ ├── clock.xise
│ │ │ ├── coregen.cgp
│ │ │ ├── ila.asy
│ │ │ ├── ila.cdc
│ │ │ ├── ila.constraints/
│ │ │ │ ├── ila.ucf
│ │ │ │ └── ila.xdc
│ │ │ ├── ila.gise
│ │ │ ├── ila.ncf
│ │ │ ├── ila.ngc
│ │ │ ├── ila.sym
│ │ │ ├── ila.ucf
│ │ │ ├── ila.v
│ │ │ ├── ila.veo
│ │ │ ├── ila.xco
│ │ │ ├── ila.xdc
│ │ │ ├── ila.xise
│ │ │ └── ila_xmdf.tcl
│ │ ├── ram.v
│ │ ├── readme.txt
│ │ ├── test_host.v
│ │ └── work/
│ │ └── ram.mif
│ ├── common/
│ │ ├── uart.v
│ │ ├── wait_state.bdf
│ │ ├── wait_state.bsf
│ │ └── wait_state.v
│ └── zxspectrum_de1/
│ ├── pll.ppf
│ ├── pll.qip
│ ├── pll.v
│ ├── ram16.qip
│ ├── ram16.v
│ ├── readme.txt
│ ├── rom/
│ │ ├── assemble.bat
│ │ ├── combined.rom
│ │ ├── gw03.rom
│ │ ├── readme.txt
│ │ ├── tasm80.tab
│ │ └── zxspectrum_rom.asm
│ ├── ula/
│ │ ├── clocks.sv
│ │ ├── i2c_loader.vhd
│ │ ├── i2s_intf.vhd
│ │ ├── pll.ppf
│ │ ├── pll.qip
│ │ ├── pll.v
│ │ ├── ps2_kbd.sv
│ │ ├── ram8.qip
│ │ ├── ram8.v
│ │ ├── test_scr.hex
│ │ ├── test_ula.qpf
│ │ ├── test_ula.qsf
│ │ ├── test_ula.sv
│ │ ├── ula.sv
│ │ ├── video.sv
│ │ └── zx_kbd.sv
│ ├── zxspectrum_de1.qpf
│ ├── zxspectrum_de1.qsf
│ ├── zxspectrum_de1.sdc
│ └── zxspectrum_de1.sv
├── license.txt
├── modelsim_pre_commit.py
├── modelsim_setup.py
├── readme.txt
├── resources/
│ ├── connotate-fuse.bat
│ ├── connotate-fuse.py
│ ├── opcodes-cb-xx.txt
│ ├── opcodes-dd-cb.txt
│ ├── opcodes-dd-xx.txt
│ ├── opcodes-ed-xx.txt
│ ├── opcodes-fd-cb.txt
│ ├── opcodes-fd-xx.txt
│ ├── opcodes-xx.txt
│ ├── process-pla.py
│ ├── title-custom-medium.bsf
│ ├── title-custom-small.bsf
│ ├── z80-pla-original.txt
│ └── z80-pla.txt
└── tools/
├── Arduino/
│ └── Z80_dongle/
│ └── Z80_dongle.ino
├── dongle/
│ ├── cb.html
│ ├── daa/
│ │ ├── daa-concise.txt
│ │ ├── daa_a-00.out
│ │ ├── daa_a-0c.out
│ │ ├── daa_a-h0.out
│ │ ├── daa_a-hc.out
│ │ ├── daa_s-00.out
│ │ ├── daa_s-0c.out
│ │ ├── daa_s-h0.out
│ │ ├── daa_s-hc.out
│ │ ├── simulate-daa.py
│ │ └── z80-instruction-test-daa.py
│ ├── dd.html
│ ├── ddcb.html
│ ├── ed.html
│ ├── neg/
│ │ ├── neg-concise.txt
│ │ ├── neg.out
│ │ ├── simulate-neg.py
│ │ └── z80-instruction-test-neg.py
│ ├── sbc/
│ │ ├── simulate-sbc.py
│ │ └── simulate-sub.py
│ ├── xx.html
│ ├── z80-instruction-run-cb.py
│ ├── z80-instruction-run-dd-cb.py
│ ├── z80-instruction-run-dd.py
│ ├── z80-instruction-run-ed.py
│ ├── z80-instruction-run-xx.py
│ └── z80-instruction-run.bat
├── readme.txt
├── z80_pla_checker/
│ ├── readme.txt
│ └── source/
│ ├── ClassLog.cs
│ ├── ClassOpcodeTable.cs
│ ├── ClassPLA.cs
│ ├── ClassPLAEntry.cs
│ ├── FormMain.Designer.cs
│ ├── FormMain.cs
│ ├── FormMain.resx
│ ├── Program.cs
│ ├── Properties/
│ │ ├── AssemblyInfo.cs
│ │ ├── Resources.Designer.cs
│ │ ├── Resources.resx
│ │ ├── Settings.Designer.cs
│ │ └── Settings.settings
│ ├── app.config
│ ├── z80_pla_checker.csproj
│ └── z80_pla_checker.sln
└── zmac/
├── bin2coe.py
├── bin2hex.txt
├── bin2mif.py
├── bindump.py
├── hello_world.asm
├── make_fpga.bat
├── make_modelsim.bat
├── readme.txt
├── test.daa.asm
├── test.neg.asm
├── zexall.asm
├── zexdoc.asm
└── zmac.html
SYMBOL INDEX (78 symbols across 26 files)
FILE: cpu/control/gencompile.py
function is_ctl (line 42) | def is_ctl(name):
function str2tok (line 47) | def str2tok(s):
function tok2str (line 51) | def tok2str(tokens):
function get_rval (line 55) | def get_rval(tokens, i):
function decomment (line 65) | def decomment(s):
function sequential_or (line 78) | def sequential_or(f, t, tokens):
FILE: cpu/control/genmatrix.py
function getSubst (line 69) | def getSubst(key, token):
FILE: cpu/toplevel/gencoremodules.py
function connect (line 46) | def connect(module, wire):
function parse (line 56) | def parse(wires, lines):
FILE: cpu/toplevel/genfuse.py
function RegWrite (line 83) | def RegWrite(reg, hex):
function RegRead (line 96) | def RegRead(reg, hex):
FILE: modelsim_pre_commit.py
function fixup (line 35) | def fixup():
FILE: modelsim_setup.py
function setup (line 24) | def setup():
FILE: resources/connotate-fuse.py
function load (line 26) | def load(opcodeFile):
FILE: resources/process-pla.py
function xtostr (line 46) | def xtostr ( condition ):
FILE: tools/dongle/daa/z80-instruction-test-daa.py
function serialFlush (line 16) | def serialFlush(ser):
FILE: tools/dongle/neg/z80-instruction-test-neg.py
function serialFlush (line 16) | def serialFlush(ser):
FILE: tools/dongle/sbc/simulate-sbc.py
function printFlags (line 8) | def printFlags(f):
function sbc (line 44) | def sbc(inA, op2, CYin):
FILE: tools/dongle/sbc/simulate-sub.py
function printFlags (line 8) | def printFlags(f):
function sbc (line 44) | def sbc(inA, op2, CYin):
FILE: tools/dongle/z80-instruction-run-cb.py
function serialFlush (line 16) | def serialFlush(ser):
FILE: tools/dongle/z80-instruction-run-dd-cb.py
function serialFlush (line 16) | def serialFlush(ser):
FILE: tools/dongle/z80-instruction-run-dd.py
function serialFlush (line 16) | def serialFlush(ser):
FILE: tools/dongle/z80-instruction-run-ed.py
function serialFlush (line 16) | def serialFlush(ser):
FILE: tools/dongle/z80-instruction-run-xx.py
function serialFlush (line 16) | def serialFlush(ser):
FILE: tools/z80_pla_checker/source/ClassLog.cs
class ClassLog (line 6) | static public class ClassLog
method Log (line 8) | static public void Log(string m)
FILE: tools/z80_pla_checker/source/ClassOpcodeTable.cs
class ClassOpcodeTable (line 11) | class ClassOpcodeTable
method Load (line 21) | public void Load(string filename, int xxindex)
method Dump (line 48) | public void Dump(List<int> t)
FILE: tools/z80_pla_checker/source/ClassPLA.cs
class ClassPla (line 11) | class ClassPla
method Count (line 31) | public int Count()
method Load (line 39) | public bool Load(string filename)
method Dump (line 141) | public void Dump()
method TableMatch (line 151) | public List<string> TableMatch(ClassPlaEntry.Modifier modifier, byte i...
method MatchPLA (line 204) | public List<string> MatchPLA(ClassPlaEntry.Modifier modifier, int id)
method Table (line 232) | public List<int> Table(ClassPlaEntry.Modifier modifier, int testNum, i...
method QueryPla (line 291) | public void QueryPla(String bits)
method GenVerilogPla (line 307) | public void GenVerilogPla()
FILE: tools/z80_pla_checker/source/ClassPLAEntry.cs
class ClassPlaEntry (line 8) | public class ClassPlaEntry
type Modifier (line 11) | [FlagsAttribute]
method IsDuplicate (line 26) | public bool IsDuplicate() { return duplicate; }
method Init (line 38) | public bool Init(string init)
method Match (line 79) | public string Match(Modifier modifier, Byte instr)
method GetBitstream (line 104) | public string GetBitstream()
FILE: tools/z80_pla_checker/source/FormMain.Designer.cs
class FormMain (line 3) | partial class FormMain
method Dispose (line 14) | protected override void Dispose(bool disposing)
method InitializeComponent (line 29) | private void InitializeComponent()
FILE: tools/z80_pla_checker/source/FormMain.cs
class FormMain (line 8) | public partial class FormMain : Form
method FormMain (line 32) | public FormMain()
method OnStart (line 41) | public void OnStart()
method Log (line 73) | public void Log(String s)
method ExitToolStripMenuItemClick (line 83) | private void ExitToolStripMenuItemClick(object sender, EventArgs e)
method FormMainFormClosing (line 91) | private void FormMainFormClosing(object sender, FormClosingEventArgs e)
method ScanNumber (line 96) | private static int ScanNumber(string arg, int baseValue)
method MatchPLA (line 113) | private void MatchPLA(string arg)
method MatchOpcodes (line 139) | private void MatchOpcodes(ClassPlaEntry.Modifier modifier, string arg)
method DumpOpcodeTable (line 155) | private void DumpOpcodeTable(List<int> t)
method LoadPlaTable (line 174) | private void LoadPlaTable(object sender, EventArgs e)
method SelectOpcodeDir (line 187) | private void SelectOpcodeDir(object sender, EventArgs e)
method BtClearClick (line 198) | private void BtClearClick(object sender, EventArgs e)
method BtRedoClick (line 206) | private void BtRedoClick(object sender, EventArgs e)
method UpdateButtons (line 217) | private void UpdateButtons()
method BtIx0Click (line 230) | private void BtIx0Click(object sender, EventArgs e)
method BtIx1Click (line 242) | private void BtIx1Click(object sender, EventArgs e)
method BtNHaltClick (line 254) | private void BtNHaltClick(object sender, EventArgs e)
method BtAluClick (line 260) | private void BtAluClick(object sender, EventArgs e)
method BtXxClick (line 266) | private void BtXxClick(object sender, EventArgs e)
method BtCbClick (line 278) | private void BtCbClick(object sender, EventArgs e)
method BtEdClick (line 290) | private void BtEdClick(object sender, EventArgs e)
method TextOpKeyDown (line 305) | private void TextOpKeyDown(object sender, KeyEventArgs e)
method Command (line 348) | private string Command(string cmd)
FILE: tools/z80_pla_checker/source/Program.cs
class Program (line 21) | static class Program
method Main (line 28) | [STAThread]
FILE: tools/z80_pla_checker/source/Properties/Resources.Designer.cs
class Resources (line 22) | [global::System.CodeDom.Compiler.GeneratedCodeAttribute("System.Resource...
method Resources (line 31) | [global::System.Diagnostics.CodeAnalysis.SuppressMessageAttribute("Mic...
FILE: tools/z80_pla_checker/source/Properties/Settings.Designer.cs
class Settings (line 14) | [global::System.Runtime.CompilerServices.CompilerGeneratedAttribute()]
Condensed preview — 407 files, each showing path, character count, and a content snippet. Download the .json file or copy for the full structured content (7,818K chars).
[
{
"path": ".gitignore",
"chars": 476,
"preview": "# Quartus generated files and folders\n*.rpt\n*.done\n*.rpt\n*.smsg\n*.summary\n*.ddb\ndb/\nincremental_db/\nout/\noutput_files/\ng"
},
{
"path": "cpu/alu/alu.bdf",
"chars": 92187,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu.bsf",
"chars": 9578,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu.v",
"chars": 10484,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/alu/alu_bit_select.bdf",
"chars": 18819,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_bit_select.bsf",
"chars": 1899,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_bit_select.v",
"chars": 2221,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/alu/alu_control.bdf",
"chars": 59814,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_control.bsf",
"chars": 8843,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_control.v",
"chars": 5651,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/alu/alu_core.bdf",
"chars": 18294,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_core.bsf",
"chars": 2956,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_core.v",
"chars": 2222,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/alu/alu_flags.bdf",
"chars": 91668,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_flags.bsf",
"chars": 9348,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_flags.v",
"chars": 8219,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/alu/alu_mux_2.bdf",
"chars": 7483,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_mux_2.bsf",
"chars": 1929,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_mux_2.v",
"chars": 1338,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/alu/alu_mux_2z.bdf",
"chars": 7962,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_mux_2z.bsf",
"chars": 2182,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_mux_2z.v",
"chars": 1416,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/alu/alu_mux_3z.bdf",
"chars": 11320,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_mux_3z.bsf",
"chars": 2578,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_mux_3z.v",
"chars": 1666,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/alu/alu_mux_4.bdf",
"chars": 13655,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_mux_4.bsf",
"chars": 2325,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_mux_4.v",
"chars": 1704,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/alu/alu_mux_8.bdf",
"chars": 25732,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_mux_8.bsf",
"chars": 3077,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_mux_8.v",
"chars": 2458,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/alu/alu_prep_daa.bdf",
"chars": 15237,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_prep_daa.bsf",
"chars": 2220,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_prep_daa.v",
"chars": 1768,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/alu/alu_select.bdf",
"chars": 17098,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_select.bsf",
"chars": 8471,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_select.v",
"chars": 3208,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/alu/alu_shifter_core.bdf",
"chars": 49807,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_shifter_core.bsf",
"chars": 2883,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_shifter_core.v",
"chars": 4325,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/alu/alu_slice.bdf",
"chars": 18223,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_slice.bsf",
"chars": 2679,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/alu/alu_slice.v",
"chars": 1984,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/alu/simulation/modelsim/r",
"chars": 22,
"preview": "restart -f ; run -all\n"
},
{
"path": "cpu/alu/simulation/modelsim/test_alu.mpf",
"chars": 30886,
"preview": "; Copyright 1991-2009 Mentor Graphics Corporation\n;\n; All Rights Reserved.\n;\n; THIS WORK CONTAINS TRADE SECRET AND PROPR"
},
{
"path": "cpu/alu/simulation/modelsim/wave_alu.do",
"chars": 8338,
"preview": "onerror {resume}\nquietly virtual signal -install /test_alu { (context /test_alu )&{test_db_low ,test_db_high }} test_bus"
},
{
"path": "cpu/alu/simulation/modelsim/wave_core.do",
"chars": 1107,
"preview": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate -radix hexadecimal /test_core/op1_sig\nadd wave -no"
},
{
"path": "cpu/alu/simulation/modelsim/wave_mux_3z.do",
"chars": 970,
"preview": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate -radix hexadecimal /test_mux_3z/a_sig\nadd wave -no"
},
{
"path": "cpu/alu/simulation/modelsim/wave_prep_daa.do",
"chars": 921,
"preview": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate -color Gold -itemcolor Gold -radix hexadecimal /te"
},
{
"path": "cpu/alu/simulation/modelsim/wave_shifter_core.do",
"chars": 2068,
"preview": "onerror {resume}\nquietly virtual signal -install /test_shifter_core { (context /test_shifter_core )&{out_high ,out_low }"
},
{
"path": "cpu/alu/simulation/modelsim/wave_slice.do",
"chars": 1174,
"preview": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate -radix hexadecimal /test_slice/op1_sig\nadd wave -n"
},
{
"path": "cpu/alu/test_alu.qpf",
"chars": 1263,
"preview": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corpor"
},
{
"path": "cpu/alu/test_alu.qsf",
"chars": 3259,
"preview": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corpor"
},
{
"path": "cpu/alu/test_alu.sv",
"chars": 8751,
"preview": "//==============================================================\n// Test complete ALU block\n//=========================="
},
{
"path": "cpu/alu/test_core.sv",
"chars": 4033,
"preview": "//==============================================================\n// Test ALU core\n//===================================="
},
{
"path": "cpu/alu/test_mux_3z.sv",
"chars": 1743,
"preview": "//==============================================================\n// Test ALU op1 MUX which is a bit more complicated\n//="
},
{
"path": "cpu/alu/test_prep_daa.sv",
"chars": 2175,
"preview": "//==============================================================\n// Test ALU state preparation for DAA instruction\n//==="
},
{
"path": "cpu/alu/test_shifter_core.sv",
"chars": 4835,
"preview": "//==============================================================\n// Test ALU shifter core block\n//======================"
},
{
"path": "cpu/alu/test_slice.sv",
"chars": 5686,
"preview": "//==============================================================\n// Test ALU slice\n//==================================="
},
{
"path": "cpu/bus/address_latch.bdf",
"chars": 26024,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/address_latch.bsf",
"chars": 3848,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/address_latch.v",
"chars": 3877,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/bus/address_mux.bdf",
"chars": 7669,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/address_mux.bsf",
"chars": 2172,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/address_mux.v",
"chars": 1777,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/bus/address_pins.bdf",
"chars": 7395,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/address_pins.bsf",
"chars": 2233,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/address_pins.v",
"chars": 2362,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/bus/bus_control.bdf",
"chars": 6852,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/bus_control.bsf",
"chars": 1821,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/bus_control.v",
"chars": 1790,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/bus/bus_switch.bsf",
"chars": 3103,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/bus_switch.v",
"chars": 1493,
"preview": "//============================================================================\n// Bus switch in bus A-Z80 CPU\n//\n// Copy"
},
{
"path": "cpu/bus/control_pins_n.bdf",
"chars": 23327,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/control_pins_n.bsf",
"chars": 6988,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/control_pins_n.v",
"chars": 2408,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/bus/data_pins.bdf",
"chars": 14574,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/data_pins.bsf",
"chars": 2622,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/data_pins.v",
"chars": 2715,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/bus/data_pins_lattice.v",
"chars": 683,
"preview": "// Use this file with Lattice toolset instead of data_pins.v\n//\n// This file is provided courtesy by JuanS\n\nmodule data_"
},
{
"path": "cpu/bus/data_switch.bdf",
"chars": 5967,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/data_switch.bsf",
"chars": 2030,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/data_switch.v",
"chars": 1908,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/bus/data_switch_mask.bdf",
"chars": 12320,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/data_switch_mask.bsf",
"chars": 2240,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/data_switch_mask.v",
"chars": 2340,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/bus/inc_dec.bdf",
"chars": 56911,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/inc_dec.bsf",
"chars": 2204,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/inc_dec.v",
"chars": 5227,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/bus/inc_dec_2bit.bdf",
"chars": 9935,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/inc_dec_2bit.bsf",
"chars": 2821,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/bus/inc_dec_2bit.v",
"chars": 1484,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/bus/simulation/modelsim/r",
"chars": 22,
"preview": "restart -f ; run -all\n"
},
{
"path": "cpu/bus/simulation/modelsim/test_bus.mpf",
"chars": 24070,
"preview": "; Copyright 1991-2009 Mentor Graphics Corporation\n;\n; All Rights Reserved.\n;\n; THIS WORK CONTAINS TRADE SECRET AND PROPR"
},
{
"path": "cpu/bus/simulation/modelsim/wave_bus.do",
"chars": 1186,
"preview": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_bus/nreset\nadd wave -noupdate /test_bus/clk\n"
},
{
"path": "cpu/bus/simulation/modelsim/wave_pins.do",
"chars": 1257,
"preview": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_pins/clk\nadd wave -noupdate -divider apins\na"
},
{
"path": "cpu/bus/test_bus.qpf",
"chars": 1263,
"preview": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corpor"
},
{
"path": "cpu/bus/test_bus.qsf",
"chars": 4027,
"preview": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corpor"
},
{
"path": "cpu/bus/test_bus.sv",
"chars": 3628,
"preview": "//==============================================================\n// Test address latch and increment block\n//==========="
},
{
"path": "cpu/bus/test_pins.sv",
"chars": 3580,
"preview": "//==============================================================\n// Test address and data pins blocks\n//================"
},
{
"path": "cpu/control/Timings.csv",
"chars": 86522,
"preview": "A-Z80 Timing Table\tM_\tT_\tFunction\tvalid\tnextM\tsetM1\tA:reg rd\tA:reg wr\tinc/dec\tA:latch\tD:reg rd\tD:reg wr\tReg gate\tSW2\tSW1"
},
{
"path": "cpu/control/clk_delay.bdf",
"chars": 27816,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/control/clk_delay.bsf",
"chars": 4365,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/control/clk_delay.v",
"chars": 3268,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/control/decode_state.bdf",
"chars": 29412,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/control/decode_state.bsf",
"chars": 5932,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/control/decode_state.v",
"chars": 3521,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/control/exec_matrix.vh",
"chars": 249829,
"preview": "// Automatically generated by genmatrix.py\n\n// 8-bit Load Group\nif (pla[17] & ~pla[50]) begin\n if (M1 & T1) begin\n "
},
{
"path": "cpu/control/exec_matrix_compiled.vh",
"chars": 372079,
"preview": "// Automatically generated by gencompile.py\n\nctl_reg_gp_we = ctl_reg_gp_we | (pla[17]&~pla[50])&(M1&T1);\nctl_reg_gp_sel_"
},
{
"path": "cpu/control/exec_module.vh",
"chars": 3179,
"preview": "// Automatically generated by genref.py\n\n// Module: control/decode_state.v\noutput reg ctl_state_iy_set,\noutput reg ctl_s"
},
{
"path": "cpu/control/exec_zero.vh",
"chars": 2455,
"preview": "// Automatically generated by genref.py\n\n// Module: control/decode_state.v\nctl_state_iy_set = 0;\nctl_state_ixiy_clr = 0;"
},
{
"path": "cpu/control/execute.bsf",
"chars": 27716,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/control/execute.v",
"chars": 7484,
"preview": "//=============================================================================\n// This module implements the instructio"
},
{
"path": "cpu/control/gencompile.py",
"chars": 6028,
"preview": "#!/usr/bin/env python3\n#\n# This script reads 'exec_matrix.vh' file and compiles it into an alternate format\n# that can b"
},
{
"path": "cpu/control/genmatrix.py",
"chars": 7975,
"preview": "#!/usr/bin/env python3\n#\n# This script reads A-Z80 instruction timing data from a spreadsheet text file\n# 'Timings.csv' "
},
{
"path": "cpu/control/genref.py",
"chars": 2710,
"preview": "#!/usr/bin/env python3\n#\n# This script reads and parses selected Verilog and SystemVerilog modules\n# and generates a set"
},
{
"path": "cpu/control/interrupts.bdf",
"chars": 45006,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/control/interrupts.bsf",
"chars": 4329,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/control/interrupts.v",
"chars": 4793,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/control/ir.bdf",
"chars": 7252,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/control/ir.bsf",
"chars": 2393,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/control/ir.v",
"chars": 1418,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/control/memory_ifc.bdf",
"chars": 81481,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/control/memory_ifc.bsf",
"chars": 5368,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/control/memory_ifc.v",
"chars": 6774,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/control/pin_control.bdf",
"chars": 25362,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/control/pin_control.bsf",
"chars": 3526,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/control/pin_control.v",
"chars": 2320,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/control/pla_decode.bsf",
"chars": 1767,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/control/pla_decode.v",
"chars": 12163,
"preview": "//=====================================================================================\n// This file is automatically ge"
},
{
"path": "cpu/control/resets.bdf",
"chars": 26057,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/control/resets.bsf",
"chars": 2732,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/control/resets.v",
"chars": 2806,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/control/sequencer.bdf",
"chars": 48922,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/control/sequencer.bsf",
"chars": 4885,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/control/sequencer.v",
"chars": 4604,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/control/simulation/modelsim/r",
"chars": 22,
"preview": "restart -f ; run -all\n"
},
{
"path": "cpu/control/simulation/modelsim/test_control.mpf",
"chars": 25525,
"preview": "; Copyright 1991-2009 Mentor Graphics Corporation\n;\n; All Rights Reserved.\n;\n; THIS WORK CONTAINS TRADE SECRET AND PROPR"
},
{
"path": "cpu/control/simulation/modelsim/wave_interrupts.do",
"chars": 1488,
"preview": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_interrupts/clk\nadd wave -noupdate /test_inte"
},
{
"path": "cpu/control/simulation/modelsim/wave_pin_control.do",
"chars": 1253,
"preview": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_pin_control/fFetch_sig\nadd wave -noupdate /t"
},
{
"path": "cpu/control/simulation/modelsim/wave_reset.do",
"chars": 1128,
"preview": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_reset/clk\nadd wave -noupdate /test_reset/res"
},
{
"path": "cpu/control/simulation/modelsim/wave_sequencer.do",
"chars": 1623,
"preview": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_sequencer/clk\nadd wave -noupdate /test_seque"
},
{
"path": "cpu/control/temp_wires.vh",
"chars": 25286,
"preview": "// Automatically generated by gencompile.py\n\nreg ctl_reg_gp_sel_pla17npla50M1T1_2;\nreg ctl_reg_gp_hilo_pla17npla50M1T1_3"
},
{
"path": "cpu/control/test_control.qpf",
"chars": 1267,
"preview": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corpor"
},
{
"path": "cpu/control/test_control.qsf",
"chars": 3837,
"preview": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corpor"
},
{
"path": "cpu/control/test_decode.sv",
"chars": 5873,
"preview": "//==============================================================\n// Test PLA decode and combinatorial static execute\n//="
},
{
"path": "cpu/control/test_interrupts.sv",
"chars": 2933,
"preview": "//==============================================================\n// Test interrupts unit\n//============================="
},
{
"path": "cpu/control/test_pin_control.sv",
"chars": 3537,
"preview": "//==============================================================\n// Test pin control unit\n//============================"
},
{
"path": "cpu/control/test_reset.sv",
"chars": 1978,
"preview": "//==============================================================\n// Test reset circuit\n//==============================="
},
{
"path": "cpu/control/test_sequencer.sv",
"chars": 2293,
"preview": "//==============================================================\n// Test sequencer\n//==================================="
},
{
"path": "cpu/control/timing_macros.i",
"chars": 21254,
"preview": "//=========================================================================================\n// This file contains substi"
},
{
"path": "cpu/copyleft.txt",
"chars": 746,
"preview": "//----------------------------------------------------------------------------\n// A-Z80 CPU Copyright (C) 2014,2017 Go"
},
{
"path": "cpu/export.py",
"chars": 2490,
"preview": "#!/usr/bin/env python3\n#\n# Run this script to export necessary CPU files away and into your project.\n#\n#----------------"
},
{
"path": "cpu/readme.txt",
"chars": 1319,
"preview": "A-Z80 Logic Design\n==================\nEach functional block contains a Quartus project file:\n./<block>/test_<block>.qpf\n"
},
{
"path": "cpu/registers/reg_control.bdf",
"chars": 84331,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/registers/reg_control.bsf",
"chars": 10477,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/registers/reg_control.v",
"chars": 7996,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/registers/reg_file.bdf",
"chars": 158253,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/registers/reg_file.bsf",
"chars": 8009,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/registers/reg_file.v",
"chars": 15182,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/registers/reg_latch.bdf",
"chars": 6550,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/registers/reg_latch.bsf",
"chars": 1982,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/registers/reg_latch.v",
"chars": 1463,
"preview": "// Copyright (C) 1991-2013 Altera Corporation\n// Your use of Altera Corporation's design tools, logic functions \n// and "
},
{
"path": "cpu/registers/simulation/modelsim/r",
"chars": 22,
"preview": "restart -f ; run -all\n"
},
{
"path": "cpu/registers/simulation/modelsim/test_registers.mpf",
"chars": 23570,
"preview": "; Copyright 1991-2009 Mentor Graphics Corporation\n;\n; All Rights Reserved.\n;\n; THIS WORK CONTAINS TRADE SECRET AND PROPR"
},
{
"path": "cpu/registers/simulation/modelsim/wave_latch.do",
"chars": 892,
"preview": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_latch/clk\nadd wave -noupdate -radix hexadeci"
},
{
"path": "cpu/registers/simulation/modelsim/wave_regfile.do",
"chars": 2195,
"preview": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_regfile/clk\nadd wave -noupdate -radix hexade"
},
{
"path": "cpu/registers/simulation/modelsim/wave_registers.do",
"chars": 4874,
"preview": "onerror {resume}\nquietly WaveActivateNextPane {} 0\nadd wave -noupdate /test_registers/clk\nadd wave -noupdate -expand -gr"
},
{
"path": "cpu/registers/test_latch.sv",
"chars": 1540,
"preview": "//==============================================================\n// Test 8-bit latch block\n//==========================="
},
{
"path": "cpu/registers/test_regfile.sv",
"chars": 6757,
"preview": "//==============================================================\n// Test register file block (without reg. control unit)"
},
{
"path": "cpu/registers/test_registers.qpf",
"chars": 1269,
"preview": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corpor"
},
{
"path": "cpu/registers/test_registers.qsf",
"chars": 3549,
"preview": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corpor"
},
{
"path": "cpu/registers/test_registers.sv",
"chars": 11708,
"preview": "//==============================================================\n// Test register control and register file blocks\n//==="
},
{
"path": "cpu/top-level-files.txt",
"chars": 1376,
"preview": "# This is a list of A-Z80 files and their dependencies. It is used by several scripts.\n# To copy A-Z80 files into your p"
},
{
"path": "cpu/toplevel/core.vh",
"chars": 2820,
"preview": "//============================================================================\n// A-Z80 core, instantiates and connects "
},
{
"path": "cpu/toplevel/coremodules.vh",
"chars": 16626,
"preview": "// Automatically generated by gencoremodules.py\n\nclk_delay clk_delay_(\n .clk (clk),\n .in_intr (in_intr),\n .nres"
},
{
"path": "cpu/toplevel/fuse/README",
"chars": 2311,
"preview": "These files are part of the Fuse emulator Z80 test vectors:\nhttp://fuse-emulator.sourceforge.net/\n\nFile formats\n========"
},
{
"path": "cpu/toplevel/fuse/regress.expected",
"chars": 4902,
"preview": "00 NOP\n 0 MC 0000\n 4 MR 0000 00\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n"
},
{
"path": "cpu/toplevel/fuse/regress.in",
"chars": 3499,
"preview": "00 NOP\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0 1\n0000 00 -1\n-1\n\ned67 RRD\n3"
},
{
"path": "cpu/toplevel/fuse/tests.expected",
"chars": 325828,
"preview": "00 NOP\n 0 MC 0000\n 4 MR 0000 00\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001\n00 01 0 0 0 0 4\n\n"
},
{
"path": "cpu/toplevel/fuse/tests.in",
"chars": 169990,
"preview": "00 NOP\n0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000\n00 00 0 0 0 0 1\n0000 00 -1\n-1\n\n01 LD BC"
},
{
"path": "cpu/toplevel/gencoremodules.py",
"chars": 4599,
"preview": "#!/usr/bin/env python3\n#\n# This script reads and parses all top-level modules and generates a core block\n# file containi"
},
{
"path": "cpu/toplevel/genfuse.py",
"chars": 12592,
"preview": "#!/usr/bin/env python3\n#\n# This script generates a test include file from a set of \"Fuse\" test vectors.\n#\n# Three common"
},
{
"path": "cpu/toplevel/genglobals.py",
"chars": 2619,
"preview": "#!/usr/bin/env python3\n#\n# This script reads and parses selected Verilog and SystemVerilog modules\n# and generates a set"
},
{
"path": "cpu/toplevel/globals.vh",
"chars": 5252,
"preview": "// Automatically generated by genglobals.py\n\n// Module: control/clk_delay.v\nwire hold_clk_iorq;\nwire hold_clk_wait;\nwire"
},
{
"path": "cpu/toplevel/simulation/modelsim/io.hex",
"chars": 2,
"preview": "00"
},
{
"path": "cpu/toplevel/simulation/modelsim/r",
"chars": 22,
"preview": "restart -f ; run -all\n"
},
{
"path": "cpu/toplevel/simulation/modelsim/ram.hexdump",
"chars": 1176,
"preview": "C3 8F 00 00 00 79 FE 02 CA 11 00 FE 09 CA 21 00 \nC9 01 00 0A ED 78 CB 47 C2 11 00 01 00 08 ED 59 \nC9 D5 E1 5E 7B FE 24 C"
},
{
"path": "cpu/toplevel/simulation/modelsim/test_top.mpf",
"chars": 45315,
"preview": "; Copyright 1991-2009 Mentor Graphics Corporation\n;\n; All Rights Reserved.\n;\n; THIS WORK CONTAINS TRADE SECRET AND PROPR"
},
{
"path": "cpu/toplevel/simulation/modelsim/wave_fuse.do",
"chars": 31797,
"preview": "onerror {resume}\r\nquietly virtual function -install /test_fuse/dut/alu_ -env /test_fuse { &{/test_fuse/dut/alu_/op1_high"
},
{
"path": "cpu/toplevel/simulation/modelsim/wave_top.do",
"chars": 30937,
"preview": "onerror {resume}\nquietly virtual function -install /test_top/dut/alu_ -env /test_top { &{/test_top/dut/alu_/op1_high, /t"
},
{
"path": "cpu/toplevel/tb_io.sv",
"chars": 1879,
"preview": "//--------------------------------------------------------------\n// Implements I/O Model for simulation\n//--------------"
},
{
"path": "cpu/toplevel/tb_iorq.sv",
"chars": 848,
"preview": "//--------------------------------------------------------------\n// Interrupt test for simulation\n// This model injects "
},
{
"path": "cpu/toplevel/tb_ram.sv",
"chars": 1149,
"preview": "//--------------------------------------------------------------\n// Implements RAM Model for simulation\n// Loads in a fi"
},
{
"path": "cpu/toplevel/test_fuse.sv",
"chars": 1112,
"preview": "//--------------------------------------------------------------\n// Testbench using Fuse Z80 emulator test vectors\n//---"
},
{
"path": "cpu/toplevel/test_fuse.vh",
"chars": 264528,
"preview": "// Automatically generated by genfuse.py\n\nforce dut.resets_.clrpc=0;\nforce dut.reg_file_.reg_gp_we=0;\nforce dut.reg_cont"
},
{
"path": "cpu/toplevel/test_top.sv",
"chars": 2697,
"preview": "//--------------------------------------------------------------\n// Testbench for the top level design\n//---------------"
},
{
"path": "cpu/toplevel/toplevel.bdf",
"chars": 39369,
"preview": "/*\nWARNING: Do NOT edit the input and output ports in this file in a text\neditor if you plan to continue editing the blo"
},
{
"path": "cpu/toplevel/toplevel.qpf",
"chars": 1263,
"preview": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corpor"
},
{
"path": "cpu/toplevel/toplevel.qsf",
"chars": 30460,
"preview": "# -------------------------------------------------------------------------- #\n#\n# Copyright (C) 1991-2013 Altera Corpor"
}
]
// ... and 207 more files (download for full content)
About this extraction
This page contains the full source code of the gdevic/A-Z80 GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 407 files (7.1 MB), approximately 1.9M tokens, and a symbol index with 78 extracted functions, classes, methods, constants, and types. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.
Extracted by GitExtract — free GitHub repo to text converter for AI. Built by Nikandr Surkov.