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Repository: karthisugumar/CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
Branch: master
Commit: 4afea5de1596
Files: 114
Total size: 1.7 MB
Directory structure:
gitextract_4n1buft_/
├── .gitattributes
├── README.md
├── rtl/
│ ├── FA.sv
│ ├── GLB_cluster.sv
│ ├── HA.sv
│ ├── HMNoC_cluster.sv
│ ├── HMNoC_cluster_east.sv
│ ├── HMNoC_cluster_west.sv
│ ├── HMNoC_top.sv
│ ├── MAC.sv
│ ├── PE.sv
│ ├── PE_cluster.sv
│ ├── SPad.sv
│ ├── circular_buffer.sv
│ ├── glb_iact.sv
│ ├── glb_psum.sv
│ ├── glb_weight.sv
│ ├── lookup_mux4.sv
│ ├── misc/
│ │ ├── FA.sv
│ │ ├── HA.sv
│ │ ├── circular_buffer.sv
│ │ ├── mux_4x1.sv
│ │ └── switch.sv
│ ├── mux2.sv
│ ├── mux_4x1.sv
│ ├── phase_1/
│ │ ├── GLB_cluster.sv
│ │ ├── HMNoC_cluster.sv
│ │ ├── PE.sv
│ │ ├── PE_cluster.sv
│ │ ├── SPad.sv
│ │ ├── glb_iact.sv
│ │ ├── glb_psum.sv
│ │ ├── glb_weight.sv
│ │ ├── router_cluster.sv
│ │ ├── router_iact.sv
│ │ ├── router_psum.sv
│ │ └── router_weight.sv
│ ├── phase_2/
│ │ ├── HMNoC_cluster_east.sv
│ │ ├── HMNoC_cluster_west.sv
│ │ ├── HMNoC_top.sv
│ │ ├── router.sv
│ │ └── router_cluster.sv
│ ├── phase_3/
│ │ ├── router.sv
│ │ ├── router_cluster.sv
│ │ └── router_network4.sv
│ ├── router.sv
│ ├── router_cluster.sv
│ ├── router_east.sv
│ ├── router_iact.sv
│ ├── router_network4.sv
│ ├── router_psum.sv
│ ├── router_weight.sv
│ └── switch.sv
├── synth/
│ ├── HMNoC_cluster.vds
│ ├── HMNoC_cluster_utilization_synth.rpt
│ ├── HMNoC_top.vds
│ ├── HMNoC_top_utilization_synth.rpt
│ └── constraints_1.xdc
└── testbench/
├── GLB_cluster_tb.sv
├── HMNoC_1_tb.sv
├── HMNoC_cluster_west_tb.sv
├── MAC_tb.sv
├── PE_cluster_tb.sv
├── PE_tb.sv
├── SPad_tb.sv
├── act_5x5.txt
├── act_7x7.txt
├── adder_tb.sv
├── glb_iact_tb.sv
├── kernel_3x3.txt
├── kernel_5x5.txt
├── phase_1/
│ ├── GLB_cluster_tb.sv
│ ├── HMNoC_1_tb.sv
│ ├── PE_cluster_tb.sv
│ ├── PE_tb.sv
│ ├── router_cluster_5x5_tb.sv
│ ├── router_cluster_tb.sv
│ ├── router_iact.sv
│ ├── router_iact_tb.sv
│ ├── router_psum_tb.sv
│ ├── router_weight.sv
│ └── router_weight_tb.sv
├── phase_2/
│ ├── HMNoC_cluster_west_tb.sv
│ ├── router_cluster_new_tb.sv
│ ├── router_cluster_pe_cluster_5x5_tb.sv
│ ├── router_cluster_pe_cluster_tb.sv
│ ├── router_east_tb.sv
│ ├── router_pe_4_clusters_5x5_tb.sv
│ └── router_pe_4_clusters_tb.sv
├── phase_3/
│ ├── router_broadcast_tb.sv
│ ├── router_multicast_tb.sv
│ ├── router_pe_4_clusters_5x5_tb.sv
│ ├── router_pe_4_clusters_tb.sv
│ └── router_unicast_tb.sv
├── psum_3x3.txt
├── router_act.sv
├── router_broadcast_tb.sv
├── router_cluster_5x5_tb.sv
├── router_cluster_new_tb.sv
├── router_cluster_pe_cluster_5x5_tb.sv
├── router_cluster_pe_cluster_tb.sv
├── router_cluster_tb.sv
├── router_east_tb.sv
├── router_glb_tb.sv
├── router_iact.sv
├── router_iact_tb.sv
├── router_multicast_tb.sv
├── router_pe_4_clusters_5x5_tb.sv
├── router_pe_4_clusters_tb.sv
├── router_psum_tb.sv
├── router_unicast_tb.sv
├── router_weight.sv
├── router_weight_tb.sv
└── switch_tb.sv
================================================
FILE CONTENTS
================================================
================================================
FILE: .gitattributes
================================================
# Auto detect text files and perform LF normalization
* text=auto
================================================
FILE: README.md
================================================
### UCSD CSE 240D Fall '19
# Hierarchical Mesh NoC - Eyeriss v2
## A SystemVerilog implementation of Row-Stationary dataflow based on Eyeriss and Hierarchical Mesh NoC based on the [Eyeriss v2 CNN accelerator](https://arxiv.org/abs/1807.07928).
This repository contains the SystemVerilog source code developed as part of the final project for the course "Accelerator Design for Deep Learning" at UCSD. Eyeriss is a popular CNN accelerator that showcased dataflow-based architectures using systolic arrays. The project implemented is inspired by the RS dataflow from the original Eyeriss paper and the Hierarchical Mesh NoC Architecture from the follow-up paper Eyeriss v2.
### Prerequisites
#### Simulation requires a Verilog/SystemVerilog syntheis software package. Xilinx's Vivado Suite is recommended (available for free at the [Xilinx downloads webpage](https://www.xilinx.com/support/download.html))
### File structure
- **images/** - Figures used in report
- **synth/** - synthesis folder
- *.xdc* file to specify timing constraints - clock period, waveform shape (can also be used to include jitter, uncertainty, false paths etc for more accurate STA)
- *.vds* files contain synthesis log
- *.rpt* files contain area utlization report
- **rtl/** - Contains SystemVerilog models of all components designed
- **misc/** - combinational logic blocks for miscellaneous tasks
- **phase_1/** - Focus on demonstration of a convolution operation through a single grouped cluster of PEs, routers and GLBs
- **phase_2/** - Scaled-up design with 4 grouped clusters. Has new routers with provisions for direction control and configuration
- **phase_3/** - Exploration of router design for data reuse opportunities - Unicast, Multicast, Broadcast
- **synth/** - constraints and reports directory - synthesis results containing top level and clusterized reports for timing and area utilization
- **testbench/** - Contains all testbenches, verification code, and experiments.
- **phase_1/, phase_2/, phase_3/** - Contains testbenches specific to each design phase
- **waveforms/** - directory containing simulation output graphs
- *4_Convs.PNG* - parallel convolution output of 4 PE clusters
- *conv_3x3.PNG* - convolution with 3x3 kernel size
- *conv_5x5.PNG* - convolution with 5x5 kernel size
- *conv_out.PNG* - phase_1 convolution output
================================================
FILE: rtl/FA.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/27/2019 07:43:21 AM
// Design Name:
// Module Name: FA
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FA( input A_in,
input B_in,
input C_in,
output logic S_out,
output logic C_out
);
assign {C_out, S_out} = A_in + B_in + C_in;
endmodule
================================================
FILE: rtl/GLB_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/01/2019 01:18:56 PM
// Design Name:
// Module Name: GLB_cluster
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GLB_cluster
#(
parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 10,
parameter NUM_GLB_IACT = 1,
parameter NUM_GLB_PSUM = 1,
parameter NUM_GLB_WGHT = 1
)
( input clk,
input reset,
input read_req_iact,
input read_req_psum,
input read_req_wght,
input write_en_iact,
input write_en_psum,
input write_en_wght,
input [ADDR_BITWIDTH-1 : 0] r_addr_iact,
input [ADDR_BITWIDTH-1 : 0] r_addr_psum,
input [ADDR_BITWIDTH-1 : 0] r_addr_wght,
input [ADDR_BITWIDTH-1 : 0] w_addr_iact,
input [ADDR_BITWIDTH-1 : 0] w_addr_psum,
input [ADDR_BITWIDTH-1 : 0] w_addr_wght,
input [DATA_BITWIDTH-1 : 0] w_data_iact,
input [DATA_BITWIDTH-1 : 0] w_data_psum,
input [DATA_BITWIDTH-1 : 0] w_data_wght,
output logic [DATA_BITWIDTH-1 : 0] r_data_iact,
output logic [DATA_BITWIDTH-1 : 0] r_data_psum,
output logic [DATA_BITWIDTH-1 : 0] r_data_wght
);
//Instantiate iact global buffer
generate
genvar i;
for(i=0; i<NUM_GLB_IACT; i++)
begin:glb_iact_gen
glb_iact #( .ADDR_BITWIDTH(ADDR_BITWIDTH),
.DATA_BITWIDTH(DATA_BITWIDTH)
)
glb_iact_inst ( .clk(clk),
.reset(reset),
.read_req(read_req_iact),
.write_en(write_en_iact),
.r_addr(r_addr_iact),
.w_data(w_data_iact),
.r_data(r_data_iact),
.w_addr(w_addr_iact)
);
end
endgenerate
//Instantiate psum global buffer
generate
genvar j;
for(j=0; j<NUM_GLB_PSUM; j++)
begin:glb_psum_gen
glb_psum #( .ADDR_BITWIDTH(ADDR_BITWIDTH),
.DATA_BITWIDTH(DATA_BITWIDTH)
)
glb_psum_inst ( .clk(clk),
.reset(reset),
.read_req(read_req_psum),
.write_en(write_en_psum),
.r_addr(r_addr_psum),
.w_data(w_data_psum),
.r_data(r_data_psum),
.w_addr(w_addr_psum)
);
end
endgenerate
//Instantiate weight global buffer
generate
genvar k;
for(k=0; k<NUM_GLB_WGHT; k++)
begin:glb_wght_gen
glb_weight #( .ADDR_BITWIDTH(ADDR_BITWIDTH),
.DATA_BITWIDTH(DATA_BITWIDTH)
)
glb_weight_inst ( .clk(clk),
.reset(reset),
.read_req(read_req_wght),
.write_en(write_en_wght),
.r_addr(r_addr_wght),
.w_data(w_data_wght),
.r_data(r_data_wght),
.w_addr(w_addr_wght)
);
end
endgenerate
endmodule
================================================
FILE: rtl/HA.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/27/2019 07:30:57 AM
// Design Name:
// Module Name: HA
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HA( input A_in,
input B_in,
output logic S_out,
output logic C_out
);
assign {C_out,S_out} = A_in + B_in;
endmodule
================================================
FILE: rtl/HMNoC_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/04/2019 06:59:19 AM
// Design Name:
// Module Name: HMNoC_cluster
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HMNoC_cluster#(
parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 10,
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 9,
// GLB Cluster parameters. This TestBench uses only 1 of each
parameter NUM_GLB_IACT = 1,
parameter NUM_GLB_PSUM = 1,
parameter NUM_GLB_WGHT = 1,
parameter ADDR_BITWIDTH_GLB = 10,
parameter ADDR_BITWIDTH_SPAD = 9,
parameter NUM_ROUTER_PSUM = 1,
parameter NUM_ROUTER_IACT = 1,
parameter NUM_ROUTER_WGHT = 1,
parameter int kernel_size = 3,
parameter int act_size = 5,
parameter int X_dim = 3,
parameter int Y_dim = 3,
parameter W_READ_ADDR = 0,
parameter A_READ_ADDR = 0,
parameter W_LOAD_ADDR = 0,
parameter A_LOAD_ADDR = 0,
parameter PSUM_READ_ADDR = 0,
parameter PSUM_LOAD_ADDR = 0
)
(
input clk,
input reset,
input start,
output load_done,
//logic for GLB cluster
input read_req_psum,
input write_en_iact,
input write_en_wght,
input load_spad_ctrl_wght,
input load_spad_ctrl_iact,
input [ADDR_BITWIDTH-1 : 0] r_addr_psum,
output logic [DATA_BITWIDTH-1 : 0] r_data_psum,
input [ADDR_BITWIDTH-1 : 0] w_addr_iact,
input [ADDR_BITWIDTH-1 : 0] w_addr_psum,
input [ADDR_BITWIDTH-1 : 0] w_addr_wght,
input [DATA_BITWIDTH-1 : 0] w_data_iact,
input [DATA_BITWIDTH-1 : 0] w_data_psum,
input [DATA_BITWIDTH-1 : 0] w_data_wght
);
// logic [DATA_WIDTH-1:0] act_in;
// logic [DATA_WIDTH-1:0] filt_in;
// logic load_en_wght, load_en_act;
// logic [DATA_BITWIDTH-1 : 0] r_data_spad_psum[0:kernel_size-1];
//GLB cluster initialization
GLB_cluster
#( .DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH(ADDR_BITWIDTH),
.NUM_GLB_IACT(NUM_GLB_IACT),
.NUM_GLB_PSUM(NUM_GLB_PSUM),
.NUM_GLB_WGHT(NUM_GLB_WGHT)
)
GLB_cluster_0
(
.clk(clk), //TestBench/Controller
.reset(reset), //TestBench/Controller
//Signals for reading from GLB
.read_req_iact(router_cluster_0.read_req_glb_iact),
.read_req_psum(read_req_psum), //Read by testbench/controller
.read_req_wght(router_cluster_0.read_req_glb_wght),
.r_data_iact(router_cluster_0.r_data_glb_iact),
.r_data_psum(r_data_psum), //Read by testbench/controller
.r_data_wght(router_cluster_0.r_data_glb_wght),
.r_addr_iact(router_cluster_0.r_addr_glb_iact),
.r_addr_psum(r_addr_psum), //testbench for reading final psums
.r_addr_wght(router_cluster_0.r_addr_glb_wght),
//Signals for writing to GLB
.w_addr_iact(w_addr_iact), //testbench for writing
.w_addr_psum(router_cluster_0.w_addr_glb_psum),
.w_addr_wght(w_addr_wght), //testbench for writing
.w_data_iact(w_data_iact), //testbench for writing
.w_data_psum(router_cluster_0.w_data_glb_psum),
.w_data_wght(w_data_wght), //testbench for writing
.write_en_iact(write_en_iact), //testbench for writing
.write_en_psum(router_cluster_0.write_en_glb_psum),
.write_en_wght(write_en_wght) //testbench for writing
);
//Router Cluster Instantiation
router_cluster#(.DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),
.kernel_size(kernel_size),
.act_size(act_size),
.NUM_ROUTER_PSUM(NUM_ROUTER_PSUM),
.NUM_ROUTER_IACT(NUM_ROUTER_IACT),
.NUM_ROUTER_WGHT(NUM_ROUTER_WGHT),
.A_READ_ADDR(A_READ_ADDR),
.A_LOAD_ADDR(A_LOAD_ADDR),
.W_READ_ADDR(W_READ_ADDR),
.W_LOAD_ADDR(W_LOAD_ADDR),
.PSUM_READ_ADDR(PSUM_READ_ADDR),
.PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
)
router_cluster_0
(
.clk(clk), //TestBench/Controller
.reset(reset), //TestBench/Controller
//Signals for activation router
.r_data_glb_iact(GLB_cluster_0.r_data_iact),
.r_addr_glb_iact(GLB_cluster_0.r_addr_iact),
.read_req_glb_iact(GLB_cluster_0.read_req_iact),
.w_data_spad_iact(pe_cluster_0.act_in),
.load_en_spad_iact(pe_cluster_0.load_en_act),
.load_spad_ctrl_iact(load_spad_ctrl_iact), //TestBench/Controller
//Signals for weight router
.r_data_glb_wght(GLB_cluster_0.r_data_wght),
.r_addr_glb_wght(GLB_cluster_0.r_addr_wght),
.read_req_glb_wght(GLB_cluster_0.read_req_wght),
.w_data_spad_wght(pe_cluster_0.filt_in),
.load_en_spad_wght(pe_cluster_0.load_en_wght),
.load_spad_ctrl_wght(load_spad_ctrl_wght), //TestBench/Controller
//Signals for psum router
.r_data_spad_psum(pe_cluster_0.pe_out),
.w_addr_glb_psum(GLB_cluster_0.w_addr_psum),
.write_en_glb_psum(GLB_cluster_0.write_en_psum),
.w_data_glb_psum(GLB_cluster_0.w_data_psum),
.write_psum_ctrl(pe_cluster_0.compute_done) //Connected to compute done of PE
);
//Declarations for PE_cluster
//PE_cluster Instantiation
PE_cluster #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.kernel_size(kernel_size),
.act_size(act_size),
.X_dim(X_dim),
.Y_dim(Y_dim)
)
pe_cluster_0
(
.clk(clk), //TestBench/Controller
.reset(reset), //TestBench/Controller
.start(start), //TestBench/Controller
.act_in(router_cluster_0.w_data_spad_iact),
.filt_in(router_cluster_0.w_data_spad_wght),
.load_en_wght(router_cluster_0.load_en_spad_wght),
.load_en_act(router_cluster_0.load_en_spad_iact),
.pe_out(router_cluster_0.r_data_spad_psum),
.compute_done(router_cluster_0.write_psum_ctrl),
.load_done(load_done) //TestBench/Controller
);
endmodule
================================================
FILE: rtl/HMNoC_cluster_east.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/10/2019 02:47:05 PM
// Design Name:
// Module Name: HMNoC_cluster_east
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HMNoC_cluster_east
#(
parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 10,
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 9,
// GLB Cluster parameters. This TestBench uses only 1 of each
parameter NUM_GLB_IACT = 1,
parameter NUM_GLB_PSUM = 1,
parameter NUM_GLB_WGHT = 1,
parameter ADDR_BITWIDTH_GLB = 10,
parameter ADDR_BITWIDTH_SPAD = 9,
parameter NUM_ROUTER_PSUM = 1,
parameter NUM_ROUTER_IACT = 1,
parameter NUM_ROUTER_WGHT = 1,
parameter int kernel_size = 3,
parameter int act_size = 5,
parameter int X_dim = 3,
parameter int Y_dim = 3,
parameter W_READ_ADDR = 0,
parameter A_READ_ADDR = 0,
parameter W_LOAD_ADDR = 0,
parameter A_LOAD_ADDR = 0,
parameter PSUM_READ_ADDR = 0,
parameter PSUM_LOAD_ADDR = 0
)
(
input clk,
input reset,
//PE Cluster Interface
input start,
output load_done,
input load_en_wght,
input load_en_act,
output [DATA_WIDTH-1:0] pe_out[X_dim-1:0],
output compute_done,
//GLB Cluster Interface
input write_en_iact,
input write_en_wght,
input [DATA_WIDTH-1:0] w_data_iact,
input [ADDR_WIDTH-1:0] w_addr_iact,
input [DATA_WIDTH-1:0] w_data_wght,
input [ADDR_WIDTH-1:0] w_addr_wght,
input [ADDR_WIDTH-1:0] w_addr_psum,
output [DATA_WIDTH-1:0] r_data_psum,
input [ADDR_WIDTH-1:0] r_addr_psum,
input read_req_iact,
input read_req_psum,
input read_req_wght,
input [ADDR_WIDTH-1:0] r_addr_iact,
input [ADDR_WIDTH-1:0] r_addr_wght,
//WGHT Router Ports
input [3:0] router_mode_wght,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i_wght,
input north_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o_wght,
output logic north_enable_o_wght,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i_wght,
input south_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o_wght,
output logic south_enable_o_wght,
//Interface with West
//Source ports
input [DATA_WIDTH-1:0] west_data_i_wght,
input west_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] west_data_o_wght,
output logic west_enable_o_wght,
//Interface with East - Devices
//Source ports
// input [DATA_WIDTH-1:0] east_data_i_wght,
input east_enable_i_wght,
//Destination ports
// output logic [DATA_WIDTH-1:0] east_data_o_wght,
output logic east_enable_o_wght,
//IACT Router Ports
input [3:0] router_mode_iact,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i_iact,
input north_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o_iact,
output logic north_enable_o_iact,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i_iact,
input south_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o_iact,
output logic south_enable_o_iact,
//Interface with West
//Source ports
input [DATA_WIDTH-1:0] west_data_i_iact,
input west_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] west_data_o_iact,
output logic west_enable_o_iact,
//Interface with East - Devices
//Source ports
// input [DATA_WIDTH-1:0] east_data_i_iact,
input east_enable_i_iact,
//Destination ports
// output logic [DATA_WIDTH-1:0] east_data_o_iact,
output logic east_enable_o_iact,
//PSUM Router Ports
input [3:0] router_mode_psum,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i_psum,
input north_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o_psum,
output logic north_enable_o_psum,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i_psum,
input south_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o_psum,
output logic south_enable_o_psum,
//Interface with West
//Source ports
input [DATA_WIDTH-1:0] west_data_i_psum,
input west_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] west_data_o_psum,
output logic west_enable_o_psum,
//Interface with East - Devices
//Source ports
input [DATA_WIDTH-1:0] east_data_i_psum,
input east_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] east_data_o_psum,
output logic east_enable_o_psum
);
//Logic for Direction
enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
//GLB cluster initialization
GLB_cluster
#( .DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH(ADDR_BITWIDTH),
.NUM_GLB_IACT(NUM_GLB_IACT),
.NUM_GLB_PSUM(NUM_GLB_PSUM),
.NUM_GLB_WGHT(NUM_GLB_WGHT)
)
GLB_cluster_0
(
.clk(clk), //TestBench/Controller
.reset(reset), //TestBench/Controller
//Signals for reading from GLB
.read_req_iact(read_req_iact),
.read_req_psum(read_req_psum), //Read by testbench/controller
.read_req_wght(read_req_wght),
.r_data_iact(router_cluster_0.east_data_i_iact),
.r_data_psum(r_data_psum), //Read by testbench/controller
.r_data_wght(router_cluster_0.east_data_i_wght),
.r_addr_iact(r_addr_iact),
.r_addr_psum(r_addr_psum), //testbench for reading final psums
.r_addr_wght(r_addr_wght),
//Signals for writing to GLB
.w_addr_iact(w_addr_iact), //testbench for writing
.w_addr_psum(w_addr_psum),
.w_addr_wght(w_addr_wght), //testbench for writing
.w_data_iact(w_data_iact), //testbench for writing
.w_data_psum(router_cluster_0.east_data_o_psum),
.w_data_wght(w_data_wght), //testbench for writing
.write_en_iact(write_en_iact), //testbench for writing
.write_en_psum(router_cluster_0.east_enable_o_psum),
.write_en_wght(write_en_wght) //testbench for writing
);
router_cluster
#(
.DATA_WIDTH(DATA_WIDTH)
)
router_cluster_0
(
//Ports for WGHT router
.router_mode_wght(router_mode_wght), //TB*
//Interface with North
//Source ports
.north_data_i_wght(north_data_i_wght),
.north_enable_i_wght(north_enable_i_wght),
//Destination ports
.north_data_o_wght(north_data_o_wght),
.north_enable_o_wght(north_enable_o_wght),
//Interface with South
//Source ports
.south_data_i_wght(south_data_i_wght),
.south_enable_i_wght(south_enable_i_wght),
//Destination ports
.south_data_o_wght(south_data_o_wght),
.south_enable_o_wght(south_enable_o_wght),
//Interface with West
//Source ports
.west_data_i_wght(west_data_i_wght), //GLB_cluster
.west_enable_i_wght(west_enable_i_wght),
//Destination ports
.west_data_o_wght(pwest_data_o_wght), //PE_cluster
.west_enable_o_wght(west_enable_o_wght),
//Interface with East - Devices
//Source ports
.east_data_i_wght(GLB_cluster_0.r_data_wght),
.east_enable_i_wght(east_enable_i_wght),
//Destination ports
.east_data_o_wght(east_data_o_wght),
.east_enable_o_wght(east_enable_o_wght),
////////////////////////////////////////////
//Ports for IACT router
.router_mode_iact(router_mode_iact), //TB*
//Interface with North
//Source ports
.north_data_i_iact(north_data_i_iact),
.north_enable_i_iact(north_enable_i_iact),
//Destination ports
.north_data_o_iact(north_data_o_iact),
.north_enable_o_iact(north_enable_o_iact),
//Interface with South
//Source ports
.south_data_i_iact(south_data_i_iact),
.south_enable_i_iact(south_enable_i_iact),
//Destination ports
.south_data_o_iact(south_data_o_iact),
.south_enable_o_iact(south_enable_o_iact),
//Interface with West
//Source ports
.west_data_i_iact(west_data_i_iact), //GLB_cluster
.west_enable_i_iact(west_enable_i_iact),
//Destination ports
.west_data_o_iact(west_data_o_iact), //PE_cluster
.west_enable_o_iact(west_enable_o_iact),
//Interface with East - Devices
//Source ports
.east_data_i_iact(GLB_cluster_0.r_data_iact),
.east_enable_i_iact(east_enable_i_iact),
//Destination ports
.east_data_o_iact(pe_cluster_0.act_in),
.east_enable_o_iact(east_enable_o_iact),
////////////////////////////////////////////
//Ports for PSUM router
.router_mode_psum(router_mode_psum),
//Interface with North
//Source ports
.north_data_i_psum(north_data_i_psum),
.north_enable_i_psum(north_enable_i_psum),
//Destination ports
.north_data_o_psum(north_data_o_psum),
.north_enable_o_psum(north_enable_o_psum),
//Interface with South
//Source ports
.south_data_i_psum(south_data_i_psum),
.south_enable_i_psum(south_enable_i_psum),
//Destination ports
.south_data_o_psum(south_data_o_psum),
.south_enable_o_psum(south_enable_o_psum),
//Interface with West
//Source ports
.west_data_i_psum(west_data_i_psum), //PE_cluster
.west_enable_i_psum(west_enable_i_psum),
//Destination ports
.west_data_o_psum(west_data_o_psum), //GLB_cluster
.west_enable_o_psum(west_enable_o_psum), //GLB_cluster
//Interface with East - Devices
//Source ports
.east_data_i_psum(east_data_i_psum),
.east_enable_i_psum(east_enable_i_psum),
//Destination ports
.east_data_o_psum(GLB_cluster_0.w_data_psum),
.east_enable_o_psum(GLB_cluster_0.write_en_psum)
);
PE_cluster #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.kernel_size(kernel_size),
.act_size(act_size),
.X_dim(X_dim),
.Y_dim(Y_dim)
)
pe_cluster_0
(
.clk(clk),
.reset(reset),
.act_in(router_cluster_0.east_data_o_iact),
.filt_in(router_cluster_0.east_data_o_wght),
.load_en_wght(load_en_wght),
.load_en_act(load_en_act),
.start(start),
.pe_out(pe_out),
.compute_done(compute_done),
.load_done(load_done)
);
endmodule
================================================
FILE: rtl/HMNoC_cluster_west.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/10/2019 11:42:17 AM
// Design Name:
// Module Name: HMNoC_cluster_new
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HMNoC_cluster_west
#(
parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 10,
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 9,
// GLB Cluster parameters. This TestBench uses only 1 of each
parameter NUM_GLB_IACT = 1,
parameter NUM_GLB_PSUM = 1,
parameter NUM_GLB_WGHT = 1,
parameter ADDR_BITWIDTH_GLB = 10,
parameter ADDR_BITWIDTH_SPAD = 9,
parameter NUM_ROUTER_PSUM = 1,
parameter NUM_ROUTER_IACT = 1,
parameter NUM_ROUTER_WGHT = 1,
parameter int kernel_size = 3,
parameter int act_size = 5,
parameter int X_dim = 3,
parameter int Y_dim = 3,
parameter W_READ_ADDR = 0,
parameter A_READ_ADDR = 0,
parameter W_LOAD_ADDR = 0,
parameter A_LOAD_ADDR = 0,
parameter PSUM_READ_ADDR = 0,
parameter PSUM_LOAD_ADDR = 0
)
(
input clk,
input reset,
//PE Cluster Interface
input start,
output load_done,
input load_en_wght,
input load_en_act,
output [DATA_WIDTH-1:0] pe_out[X_dim-1:0],
output compute_done,
//GLB Cluster Interface
input write_en_iact,
input write_en_wght,
input [DATA_WIDTH-1:0] w_data_iact,
input [ADDR_WIDTH-1:0] w_addr_iact,
input [DATA_WIDTH-1:0] w_data_wght,
input [ADDR_WIDTH-1:0] w_addr_wght,
input [ADDR_WIDTH-1:0] w_addr_psum,
output [DATA_WIDTH-1:0] r_data_psum,
input [ADDR_WIDTH-1:0] r_addr_psum,
input read_req_iact,
input read_req_psum,
input read_req_wght,
input [ADDR_WIDTH-1:0] r_addr_iact,
input [ADDR_WIDTH-1:0] r_addr_wght,
//WGHT Router Ports
input [3:0] router_mode_wght,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i_wght,
input north_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o_wght,
output logic north_enable_o_wght,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i_wght,
input south_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o_wght,
output logic south_enable_o_wght,
//Interface with West
//Source ports
// input [DATA_WIDTH-1:0] west_data_i_wght,
input west_enable_i_wght,
//Destination ports
// output logic [DATA_WIDTH-1:0] west_data_o_wght,
output logic west_enable_o_wght,
//Interface with East - Devices
//Source ports
input [DATA_WIDTH-1:0] east_data_i_wght,
input east_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] east_data_o_wght,
output logic east_enable_o_wght,
//IACT Router Ports
input [3:0] router_mode_iact,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i_iact,
input north_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o_iact,
output logic north_enable_o_iact,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i_iact,
input south_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o_iact,
output logic south_enable_o_iact,
//Interface with West
//Source ports
// input [DATA_WIDTH-1:0] west_data_i_iact,
input west_enable_i_iact,
//Destination ports
// output logic [DATA_WIDTH-1:0] west_data_o_iact,
output logic west_enable_o_iact,
//Interface with East - Devices
//Source ports
input [DATA_WIDTH-1:0] east_data_i_iact,
input east_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] east_data_o_iact,
output logic east_enable_o_iact,
//PSUM Router Ports
input [3:0] router_mode_psum,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i_psum,
input north_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o_psum,
output logic north_enable_o_psum,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i_psum,
input south_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o_psum,
output logic south_enable_o_psum,
//Interface with West
//Source ports
input [DATA_WIDTH-1:0] west_data_i_psum,
input west_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] west_data_o_psum,
output logic west_enable_o_psum,
//Interface with East - Devices
//Source ports
input [DATA_WIDTH-1:0] east_data_i_psum,
input east_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] east_data_o_psum,
output logic east_enable_o_psum
);
//Logic for Direction
enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
//GLB cluster initialization
GLB_cluster
#( .DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH(ADDR_BITWIDTH),
.NUM_GLB_IACT(NUM_GLB_IACT),
.NUM_GLB_PSUM(NUM_GLB_PSUM),
.NUM_GLB_WGHT(NUM_GLB_WGHT)
)
GLB_cluster_0
(
.clk(clk), //TestBench/Controller
.reset(reset), //TestBench/Controller
//Signals for reading from GLB
.read_req_iact(read_req_iact),
.read_req_psum(read_req_psum), //Read by testbench/controller
.read_req_wght(read_req_wght),
.r_data_iact(router_cluster_0.west_data_i_iact),
.r_data_psum(r_data_psum), //Read by testbench/controller
.r_data_wght(router_cluster_0.west_data_i_wght),
.r_addr_iact(r_addr_iact),
.r_addr_psum(r_addr_psum), //testbench for reading final psums
.r_addr_wght(r_addr_wght),
//Signals for writing to GLB
.w_addr_iact(w_addr_iact), //testbench for writing
.w_addr_psum(w_addr_psum),
.w_addr_wght(w_addr_wght), //testbench for writing
.w_data_iact(w_data_iact), //testbench for writing
.w_data_psum(router_cluster_0.west_data_o_psum),
.w_data_wght(w_data_wght), //testbench for writing
.write_en_iact(write_en_iact), //testbench for writing
.write_en_psum(router_cluster_0.west_enable_o_psum),
.write_en_wght(write_en_wght) //testbench for writing
);
router_cluster
#(
.DATA_WIDTH(DATA_WIDTH)
)
router_cluster_0
(
//Ports for WGHT router
.router_mode_wght(router_mode_wght), //TB*
//Interface with North
//Source ports
.north_data_i_wght(north_data_i_wght),
.north_enable_i_wght(north_enable_i_wght),
//Destination ports
.north_data_o_wght(north_data_o_wght),
.north_enable_o_wght(north_enable_o_wght),
//Interface with South
//Source ports
.south_data_i_wght(south_data_i_wght),
.south_enable_i_wght(south_enable_i_wght),
//Destination ports
.south_data_o_wght(south_data_o_wght),
.south_enable_o_wght(south_enable_o_wght),
//Interface with West
//Source ports
.west_data_i_wght(GLB_cluster_0.r_data_wght), //GLB_cluster
.west_enable_i_wght(west_enable_i_wght),
//Destination ports
.west_data_o_wght(pe_cluster_0.filt_in), //PE_cluster
.west_enable_o_wght(west_enable_o_wght),
//Interface with East - Devices
//Source ports
.east_data_i_wght(east_data_i_wght),
.east_enable_i_wght(east_enable_i_wght),
//Destination ports
.east_data_o_wght(east_data_o_wght),
.east_enable_o_wght(east_enable_o_wght),
////////////////////////////////////////////
//Ports for IACT router
.router_mode_iact(router_mode_iact), //TB*
//Interface with North
//Source ports
.north_data_i_iact(north_data_i_iact),
.north_enable_i_iact(north_enable_i_iact),
//Destination ports
.north_data_o_iact(north_data_o_iact),
.north_enable_o_iact(north_enable_o_iact),
//Interface with South
//Source ports
.south_data_i_iact(south_data_i_iact),
.south_enable_i_iact(south_enable_i_iact),
//Destination ports
.south_data_o_iact(south_data_o_iact),
.south_enable_o_iact(south_enable_o_iact),
//Interface with West
//Source ports
.west_data_i_iact(GLB_cluster_0.r_data_iact), //GLB_cluster
.west_enable_i_iact(west_enable_i_iact),
//Destination ports
.west_data_o_iact(pe_cluster_0.act_in), //PE_cluster
.west_enable_o_iact(west_enable_o_iact),
//Interface with East - Devices
//Source ports
.east_data_i_iact(east_data_i_iact),
.east_enable_i_iact(east_enable_i_iact),
//Destination ports
.east_data_o_iact(east_data_o_iact),
.east_enable_o_iact(east_enable_o_iact),
////////////////////////////////////////////
//Ports for PSUM router
.router_mode_psum(router_mode_psum),
//Interface with North
//Source ports
.north_data_i_psum(north_data_i_psum),
.north_enable_i_psum(north_enable_i_psum),
//Destination ports
.north_data_o_psum(north_data_o_psum),
.north_enable_o_psum(north_enable_o_psum),
//Interface with South
//Source ports
.south_data_i_psum(south_data_i_psum),
.south_enable_i_psum(south_enable_i_psum),
//Destination ports
.south_data_o_psum(south_data_o_psum),
.south_enable_o_psum(south_enable_o_psum),
//Interface with West
//Source ports
.west_data_i_psum(west_data_i_psum), //PE_cluster
.west_enable_i_psum(west_enable_i_psum),
//Destination ports
.west_data_o_psum(GLB_cluster_0.w_data_psum), //GLB_cluster
.west_enable_o_psum(GLB_cluster_0.write_en_psum), //GLB_cluster
//Interface with East - Devices
//Source ports
.east_data_i_psum(east_data_i_psum),
.east_enable_i_psum(east_enable_i_psum),
//Destination ports
.east_data_o_psum(east_data_o_psum),
.east_enable_o_psum(east_enable_o_psum)
);
PE_cluster #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.kernel_size(kernel_size),
.act_size(act_size),
.X_dim(X_dim),
.Y_dim(Y_dim)
)
pe_cluster_0
(
.clk(clk),
.reset(reset),
.act_in(router_cluster_0.west_data_o_iact),
.filt_in(router_cluster_0.west_data_o_wght),
.load_en_wght(load_en_wght),
.load_en_act(load_en_act),
.start(start),
.pe_out(pe_out),
.compute_done(compute_done),
.load_done(load_done)
);
endmodule
================================================
FILE: rtl/HMNoC_top.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/10/2019 03:22:12 PM
// Design Name:
// Module Name: HMNoC_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HMNoC_top
#(
parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 10,
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 9,
// GLB Cluster parameters. This TestBench uses only 1 of each
parameter NUM_GLB_IACT = 1,
parameter NUM_GLB_PSUM = 1,
parameter NUM_GLB_WGHT = 1,
parameter ADDR_BITWIDTH_GLB = 10,
parameter ADDR_BITWIDTH_SPAD = 9,
parameter NUM_ROUTER_PSUM = 1,
parameter NUM_ROUTER_IACT = 1,
parameter NUM_ROUTER_WGHT = 1,
parameter int kernel_size = 3,
parameter int act_size = 5,
parameter int X_dim = 3,
parameter int Y_dim = 3,
parameter W_READ_ADDR = 0,
parameter A_READ_ADDR = 0,
parameter W_LOAD_ADDR = 0,
parameter A_LOAD_ADDR = 0,
parameter PSUM_READ_ADDR = 0,
parameter PSUM_LOAD_ADDR = 0
)
(
input clk,
input reset,
//PE Cluster Interface
input start,
output load_done,
input load_en_wght,
input load_en_act,
output [DATA_WIDTH-1:0] pe_out[X_dim-1:0],
output compute_done,
//GLB Cluster Interface
input write_en_iact,
input write_en_wght,
input [DATA_WIDTH-1:0] w_data_iact,
input [ADDR_WIDTH-1:0] w_addr_iact,
input [DATA_WIDTH-1:0] w_data_wght,
input [ADDR_WIDTH-1:0] w_addr_wght,
input [ADDR_WIDTH-1:0] w_addr_psum,
output [DATA_WIDTH-1:0] r_data_psum,
input [ADDR_WIDTH-1:0] r_addr_psum,
input read_req_iact,
input read_req_psum,
input read_req_wght,
input [ADDR_WIDTH-1:0] r_addr_iact,
input [ADDR_WIDTH-1:0] r_addr_wght,
//WGHT Router Ports
input [3:0] router_mode_wght,
input [3:0] router_mode_iact,
input [3:0] router_mode_psum
);
//Instantiation of NORTH WEST Cluster
HMNoC_cluster_west
#(
.DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH(ADDR_BITWIDTH),
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.NUM_GLB_IACT(NUM_GLB_IACT),
.NUM_GLB_PSUM(NUM_GLB_PSUM),
.NUM_GLB_WGHT(NUM_GLB_WGHT),
.kernel_size(kernel_size),
.act_size(act_size),
.X_dim(X_dim),
.Y_dim(Y_dim)
)
HMNoC_cluster_west_0 ///NORTH WEST Cluster
(
.clk(clk), //TestBench/Controller
.reset(reset), //TestBench/Controller
//Signals for reading from GLB
.read_req_iact(read_req_iact),
.read_req_psum(read_req_psum), //Read by testbench/controller
.read_req_wght(read_req_wght),
// .r_data_iact(router_cluster_0.r_data_glb_iact),
.r_data_psum(r_data_psum), //Read by testbench/controller
// .r_data_wght(router_cluster_0.r_data_glb_wght),
.r_addr_iact(r_addr_iact),
.r_addr_psum(r_addr_psum), //testbench for reading final psums
.r_addr_wght(r_addr_wght),
//Signals for writing to GLB
.w_addr_iact(w_addr_iact), //testbench for writing
.w_addr_psum(w_addr_psum),
.w_addr_wght(w_addr_wght), //testbench for writing
.w_data_iact(w_data_iact), //testbench for writing
// .w_data_psum(router_cluster_0.w_data_glb_psum),
.w_data_wght(w_data_wght), //testbench for writing
.write_en_iact(write_en_iact), //testbench for writing
// .write_en_psum(router_cluster_0.write_en_glb_psum),
.write_en_wght(write_en_wght), //testbench for writing
//Ports for WGHT router
.router_mode_wght(router_mode_wght), //TB*
//Interface with North
//Source ports
.north_data_i_wght(),
.north_enable_i_wght(),
//Destination ports
.north_data_o_wght(),
.north_enable_o_wght(),
//Interface with South
//Source ports
.south_data_i_wght(HMNoC_cluster_west_1.north_data_o_wght),
.south_enable_i_wght(HMNoC_cluster_west_1.north_enable_o_wght),
//Destination ports
.south_data_o_wght(HMNoC_cluster_west_1.north_data_i_wght),
.south_enable_o_wght(HMNoC_cluster_west_1.north_enable_i_wght),
//Interface with West
//Source ports
// .west_data_i_wght(GLB_cluster_0.r_data_wght), //GLB_cluster
.west_enable_i_wght(west_enable_i_wght),
//Destination ports
// .west_data_o_wght(pe_cluster_0.filt_in), //PE_cluster
.west_enable_o_wght(west_enable_o_wght),
//Interface with East - Devices
//Source ports
.east_data_i_wght(HMNoC_cluster_east_0.west_data_o_wght),
.east_enable_i_wght(HMNoC_cluster_east_0.west_enable_o_wght),
//Destination ports
.east_data_o_wght(HMNoC_cluster_east_0.west_data_i_wght),
.east_enable_o_wght(HMNoC_cluster_east_0.west_enable_i_wght),
////////////////////////////////////////////
//Ports for IACT router
.router_mode_iact(router_mode_iact), //TB*
//Interface with North
//Source ports
.north_data_i_iact(),
.north_enable_i_iact(),
//Destination ports
.north_data_o_iact(),
.north_enable_o_iact(),
//Interface with South
//Source ports
.south_data_i_iact(HMNoC_cluster_west_1.north_data_o_iact),
.south_enable_i_iact(HMNoC_cluster_west_1.north_enable_o_iact),
//Destination ports
.south_data_o_iact(HMNoC_cluster_west_1.north_data_i_iact),
.south_enable_o_iact(HMNoC_cluster_west_1.north_enable_i_iact),
//Interface with West
//Source ports
// .west_data_i_iact(GLB_cluster_0.r_data_iact), //GLB_cluster
.west_enable_i_iact(west_enable_i_iact),
//Destination ports
// .west_data_o_iact(pe_cluster_0.act_in), //PE_cluster
.west_enable_o_iact(west_enable_o_iact),
//Interface with East - Devices
//Source ports
.east_data_i_iact(HMNoC_cluster_east_0.west_data_o_iact),
.east_enable_i_iact(HMNoC_cluster_east_0.west_enable_o_iact),
//Destination ports
.east_data_o_iact(HMNoC_cluster_east_0.west_data_i_iact),
.east_enable_o_iact(HMNoC_cluster_east_0.west_enable_i_iact),
////////////////////////////////////////////
//Ports for PSUM router
.router_mode_psum(router_mode_psum),
//Interface with North
//Source ports
.north_data_i_psum(),
.north_enable_i_psum(),
//Destination ports
.north_data_o_psum(),
.north_enable_o_psum(),
//Interface with South
//Source ports
.south_data_i_psum(HMNoC_cluster_west_1.north_data_o_psum),
.south_enable_i_psum(HMNoC_cluster_west_1.north_enable_o_psum),
//Destination ports
.south_data_o_psum(HMNoC_cluster_west_1.north_data_i_psum),
.south_enable_o_psum(HMNoC_cluster_west_1.north_enable_i_psum),
//Interface with West
//Source ports
.west_data_i_psum(west_data_i_psum), //PE_cluster
.west_enable_i_psum(west_enable_i_psum),
//Destination ports
// .west_data_o_psum(GLB_cluster_0.w_data_psum), //GLB_cluster
// .west_enable_o_psum(GLB_cluster_0.write_en_psum), //GLB_cluster
//Interface with East - Devices
//Source ports
.east_data_i_psum(HMNoC_cluster_east_0.west_data_o_psum),
.east_enable_i_psum(HMNoC_cluster_east_0.west_enable_o_psum),
//Destination ports
.east_data_o_psum(HMNoC_cluster_east_0.west_data_i_psum),
.east_enable_o_psum(HMNoC_cluster_east_0.west_enable_i_psum),
//PE Cluster
.load_en_wght(load_en_wght),
.load_en_act(load_en_act),
.start(start),
.pe_out(pe_out),
.compute_done(compute_done),
.load_done(load_done)
);
//Instantiation of SOUTH WEST Cluster
HMNoC_cluster_west
#(
.DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH(ADDR_BITWIDTH),
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.NUM_GLB_IACT(NUM_GLB_IACT),
.NUM_GLB_PSUM(NUM_GLB_PSUM),
.NUM_GLB_WGHT(NUM_GLB_WGHT),
.kernel_size(kernel_size),
.act_size(act_size),
.X_dim(X_dim),
.Y_dim(Y_dim)
)
HMNoC_cluster_west_1 ///SOUTH WEST Cluster
(
.clk(clk), //TestBench/Controller
.reset(reset), //TestBench/Controller
//Signals for reading from GLB
.read_req_iact(),
.read_req_psum(), //Read by testbench/controller
.read_req_wght(),
// .r_data_iact(router_cluster_0.r_data_glb_iact),
.r_data_psum(), //Read by testbench/controller
// .r_data_wght(router_cluster_0.r_data_glb_wght),
.r_addr_iact(),
.r_addr_psum(), //testbench for reading final psums
.r_addr_wght(),
//Signals for writing to GLB
.w_addr_iact(), //testbench for writing
.w_addr_psum(),
.w_addr_wght(), //testbench for writing
.w_data_iact(), //testbench for writing
// .w_data_psum(router_cluster_0.w_data_glb_psum),
.w_data_wght(), //testbench for writing
.write_en_iact(), //testbench for writing
// .write_en_psum(router_cluster_0.write_en_glb_psum),
.write_en_wght(), //testbench for writing
//Ports for WGHT router
.router_mode_wght(), //TB*
//Interface with North
//Source ports
.north_data_i_wght(HMNoC_cluster_west_0.south_data_o_wght),
.north_enable_i_wght(HMNoC_cluster_west_0.south_enable_o_wght),
//Destination ports
.north_data_o_wght(HMNoC_cluster_west_0.south_data_i_wght),
.north_enable_o_wght(HMNoC_cluster_west_0.south_enable_i_wght),
//Interface with South
//Source ports
.south_data_i_wght(),
.south_enable_i_wght(),
//Destination ports
.south_data_o_wght(),
.south_enable_o_wght(),
//Interface with West
//Source ports
// .west_data_i_wght(GLB_cluster_0.r_data_wght), //GLB_cluster
.west_enable_i_wght(),
//Destination ports
// .west_data_o_wght(pe_cluster_0.filt_in), //PE_cluster
.west_enable_o_wght(),
//Interface with East - Devices
//Source ports
.east_data_i_wght(HMNoC_cluster_east_1.west_data_o_wght),
.east_enable_i_wght(HMNoC_cluster_east_1.west_enable_o_wght),
//Destination ports
.east_data_o_wght(HMNoC_cluster_east_1.west_data_i_wght),
.east_enable_o_wght(HMNoC_cluster_east_1.west_enable_i_wght),
////////////////////////////////////////////
//Ports for IACT router
.router_mode_iact(), //TB*
//Interface with North
//Source ports
.north_data_i_iact(HMNoC_cluster_west_0.south_data_o_iact),
.north_enable_i_iact(HMNoC_cluster_west_0.south_enable_o_iact),
//Destination ports
.north_data_o_iact(HMNoC_cluster_west_0.south_data_i_iact),
.north_enable_o_iact(HMNoC_cluster_west_0.south_enable_i_iact),
//Interface with South
//Source ports
.south_data_i_iact(),
.south_enable_i_iact(),
//Destination ports
.south_data_o_iact(),
.south_enable_o_iact(),
//Interface with West
//Source ports
// .west_data_i_iact(GLB_cluster_0.r_data_iact), //GLB_cluster
.west_enable_i_iact(),
//Destination ports
// .west_data_o_iact(pe_cluster_0.act_in), //PE_cluster
.west_enable_o_iact(),
//Interface with East - Devices
//Source ports
.east_data_i_iact(),
.east_enable_i_iact(),
//Destination ports
.east_data_o_iact(),
.east_enable_o_iact(),
////////////////////////////////////////////
//Ports for PSUM router
.router_mode_psum(),
//Interface with North
//Source ports
.north_data_i_psum(HMNoC_cluster_west_0.south_data_o_psum),
.north_enable_i_psum(HMNoC_cluster_west_0.south_enable_o_psum),
//Destination ports
.north_data_o_psum(HMNoC_cluster_west_0.south_data_i_psum),
.north_enable_o_psum(HMNoC_cluster_west_0.south_enable_i_psum),
//Interface with South
//Source ports
.south_data_i_psum(),
.south_enable_i_psum(),
//Destination ports
.south_data_o_psum(),
.south_enable_o_psum(),
//Interface with West
//Source ports
.west_data_i_psum(), //PE_cluster
.west_enable_i_psum(),
//Destination ports
// .west_data_o_psum(GLB_cluster_0.w_data_psum), //GLB_cluster
// .west_enable_o_psum(GLB_cluster_0.write_en_psum), //GLB_cluster
//Interface with East - Devices
//Source ports
.east_data_i_psum(HMNoC_cluster_east_1.west_data_o_psum),
.east_enable_i_psum(HMNoC_cluster_east_1.west_enable_o_psum),
//Destination ports
.east_data_o_psum(HMNoC_cluster_east_1.west_data_i_psum),
.east_enable_o_psum(HMNoC_cluster_east_1.west_enable_i_psum),
//PE Cluster
.load_en_wght(),
.load_en_act(),
.start(),
.pe_out(),
.compute_done(),
.load_done()
);
//Instantiation of NORTH_EAST Cluster
HMNoC_cluster_east
#(
.DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH(ADDR_BITWIDTH),
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.NUM_GLB_IACT(NUM_GLB_IACT),
.NUM_GLB_PSUM(NUM_GLB_PSUM),
.NUM_GLB_WGHT(NUM_GLB_WGHT),
.kernel_size(kernel_size),
.act_size(act_size),
.X_dim(X_dim),
.Y_dim(Y_dim)
)
HMNoC_cluster_east_0
(
.clk(clk), //TestBench/Controller
.reset(reset), //TestBench/Controller
//Signals for reading from GLB
.read_req_iact(),
.read_req_psum(), //Read by testbench/controller
.read_req_wght(),
// .r_data_iact(router_cluster_0.r_data_glb_iact),
.r_data_psum(), //Read by testbench/controller
// .r_data_wght(router_cluster_0.r_data_glb_wght),
.r_addr_iact(),
.r_addr_psum(), //testbench for reading final psums
.r_addr_wght(),
//Signals for writing to GLB
.w_addr_iact(), //testbench for writing
.w_addr_psum(),
.w_addr_wght(), //testbench for writing
.w_data_iact(), //testbench for writing
// .w_data_psum(router_cluster_0.w_data_glb_psum),
.w_data_wght(), //testbench for writing
.write_en_iact(), //testbench for writing
// .write_en_psum(router_cluster_0.write_en_glb_psum),
.write_en_wght(), //testbench for writing
//Ports for WGHT router
.router_mode_wght(), //TB*
//Interface with North
//Source ports
.north_data_i_wght(),
.north_enable_i_wght(),
//Destination ports
.north_data_o_wght(),
.north_enable_o_wght(),
//Interface with South
//Source ports
.south_data_i_wght(HMNoC_cluster_east_1.north_data_o_wght),
.south_enable_i_wght(HMNoC_cluster_east_1.north_enable_o_wght),
//Destination ports
.south_data_o_wght(HMNoC_cluster_east_1.north_data_i_wght),
.south_enable_o_wght(HMNoC_cluster_east_1.north_enable_i_wght),
//Interface with West
//Source ports
.west_data_i_wght(HMNoC_cluster_west_0.east_data_o_wght), //GLB_cluster
.west_enable_i_wght(HMNoC_cluster_west_0.east_enable_o_wght),
//Destination ports
.west_data_o_wght(HMNoC_cluster_west_0.east_data_i_wght), //PE_cluster
.west_enable_o_wght(HMNoC_cluster_west_0.east_enable_i_wght),
//Interface with East - Devices
//Source ports
// .east_data_i_wght(east_data_i_wght),
.east_enable_i_wght(),
//Destination ports
// .east_data_o_wght(east_data_o_wght),
.east_enable_o_wght(),
////////////////////////////////////////////
//Ports for IACT router
.router_mode_iact(), //TB*
//Interface with North
//Source ports
.north_data_i_iact(),
.north_enable_i_iact(),
//Destination ports
.north_data_o_iact(),
.north_enable_o_iact(),
//Interface with South
//Source ports
.south_data_i_iact(HMNoC_cluster_east_1.north_data_o_iact),
.south_enable_i_iact(HMNoC_cluster_east_1.north_enable_o_iact),
//Destination ports
.south_data_o_iact(HMNoC_cluster_east_1.north_data_i_iact),
.south_enable_o_iact(HMNoC_cluster_east_1.north_enable_i_iact),
//Interface with West
//Source ports
.west_data_i_iact(HMNoC_cluster_west_0.east_data_o_iact), //GLB_cluster
.west_enable_i_iact(HMNoC_cluster_west_0.east_enable_o_iact),
//Destination ports
.west_data_o_iact(HMNoC_cluster_west_0.east_data_i_iact), //PE_cluster
.west_enable_o_iact(HMNoC_cluster_west_0.east_enable_i_iact),
//Interface with East - Devices
//Source ports
// .east_data_i_iact(east_data_i_iact),
.east_enable_i_iact(),
//Destination ports
// .east_data_o_iact(east_data_o_iact),
.east_enable_o_iact(),
////////////////////////////////////////////
//Ports for PSUM router
.router_mode_psum(),
//Interface with North
//Source ports
.north_data_i_psum(),
.north_enable_i_psum(),
//Destination ports
.north_data_o_psum(),
.north_enable_o_psum(),
//Interface with South
//Source ports
.south_data_i_psum(HMNoC_cluster_east_1.north_data_i_psum),
.south_enable_i_psum(HMNoC_cluster_east_1.north_enable_i_psum),
//Destination ports
.south_data_o_psum(HMNoC_cluster_east_1.north_data_o_psum),
.south_enable_o_psum(HMNoC_cluster_east_1.north_enable_o_psum),
//Interface with West
//Source ports
.west_data_i_psum(HMNoC_cluster_west_0.east_data_o_psum), //PE_cluster
.west_enable_i_psum(HMNoC_cluster_west_0.east_enable_o_psum),
//Destination ports
.west_data_o_psum(HMNoC_cluster_west_0.east_data_i_psum), //GLB_cluster
.west_enable_o_psum(HMNoC_cluster_west_0.east_enable_i_psum), //GLB_cluster
//Interface with East - Devices
//Source ports
.east_data_i_psum(),
.east_enable_i_psum(),
//Destination ports
// .east_data_o_psum(east_data_o_psum),
// .east_enable_o_psum(east_enable_o_psum),
//PE Cluster
.load_en_wght(),
.load_en_act(),
.start(),
.pe_out(),
.compute_done(),
.load_done()
);
//Instantiation of SOUTH_EAST Cluster
HMNoC_cluster_east
#(
.DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH(ADDR_BITWIDTH),
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.NUM_GLB_IACT(NUM_GLB_IACT),
.NUM_GLB_PSUM(NUM_GLB_PSUM),
.NUM_GLB_WGHT(NUM_GLB_WGHT),
.kernel_size(kernel_size),
.act_size(act_size),
.X_dim(X_dim),
.Y_dim(Y_dim)
)
HMNoC_cluster_east_1
(
.clk(clk), //TestBench/Controller
.reset(reset), //TestBench/Controller
//Signals for reading from GLB
.read_req_iact(),
.read_req_psum(), //Read by testbench/controller
.read_req_wght(),
// .r_data_iact(router_cluster_0.r_data_glb_iact),
.r_data_psum(), //Read by testbench/controller
// .r_data_wght(router_cluster_0.r_data_glb_wght),
.r_addr_iact(),
.r_addr_psum(), //testbench for reading final psums
.r_addr_wght(),
//Signals for writing to GLB
.w_addr_iact(), //testbench for writing
.w_addr_psum(),
.w_addr_wght(), //testbench for writing
.w_data_iact(), //testbench for writing
// .w_data_psum(router_cluster_0.w_data_glb_psum),
.w_data_wght(), //testbench for writing
.write_en_iact(), //testbench for writing
// .write_en_psum(router_cluster_0.write_en_glb_psum),
.write_en_wght(), //testbench for writing
//Ports for WGHT router
.router_mode_wght(), //TB*
//Interface with North
//Source ports
.north_data_i_wght(HMNoC_cluster_east_0.south_data_o_wght),
.north_enable_i_wght(HMNoC_cluster_east_0.south_enable_o_wght),
//Destination ports
.north_data_o_wght(HMNoC_cluster_east_0.south_data_i_wght),
.north_enable_o_wght(HMNoC_cluster_east_0.south_enable_i_wght),
//Interface with South
//Source ports
.south_data_i_wght(),
.south_enable_i_wght(),
//Destination ports
.south_data_o_wght(),
.south_enable_o_wght(),
//Interface with West
//Source ports
.west_data_i_wght(HMNoC_cluster_west_1.east_data_o_wght), //GLB_cluster
.west_enable_i_wght(HMNoC_cluster_west_1.east_enable_o_wght),
//Destination ports
.west_data_o_wght(HMNoC_cluster_west_1.east_data_i_wght), //PE_cluster
.west_enable_o_wght(HMNoC_cluster_west_1.east_enable_i_wght),
//Interface with East - Devices
//Source ports
// .east_data_i_wght(east_data_i_wght),
.east_enable_i_wght(),
//Destination ports
// .east_data_o_wght(east_data_o_wght),
.east_enable_o_wght(),
////////////////////////////////////////////
//Ports for IACT router
.router_mode_iact(router_mode_iact), //TB*
//Interface with North
//Source ports
.north_data_i_iact(HMNoC_cluster_east_0.south_data_o_iact),
.north_enable_i_iact(HMNoC_cluster_east_0.south_enable_o_iact),
//Destination ports
.north_data_o_iact(HMNoC_cluster_east_0.south_data_i_iact),
.north_enable_o_iact(HMNoC_cluster_east_0.south_enable_i_iact),
//Interface with South
//Source ports
.south_data_i_iact(),
.south_enable_i_iact(),
//Destination ports
.south_data_o_iact(),
.south_enable_o_iact(),
//Interface with West
//Source ports
.west_data_i_iact(HMNoC_cluster_west_1.east_data_o_iact), //GLB_cluster
.west_enable_i_iact(HMNoC_cluster_west_1.east_enable_o_iact),
//Destination ports
.west_data_o_iact(HMNoC_cluster_west_1.east_data_i_iact), //PE_cluster
.west_enable_o_iact(HMNoC_cluster_west_1.east_enable_i_iact),
//Interface with East - Devices
//Source ports
// .east_data_i_iact(east_data_i_iact),
.east_enable_i_iact(),
//Destination ports
// .east_data_o_iact(east_data_o_iact),
.east_enable_o_iact(),
////////////////////////////////////////////
//Ports for PSUM router
.router_mode_psum(),
//Interface with North
//Source ports
.north_data_i_psum(HMNoC_cluster_east_0.south_data_o_psum),
.north_enable_i_psum(HMNoC_cluster_east_0.south_enable_o_psum),
//Destination ports
.north_data_o_psum(HMNoC_cluster_east_0.south_data_i_psum),
.north_enable_o_psum(HMNoC_cluster_east_0.south_enable_i_psum),
//Interface with South
//Source ports
.south_data_i_psum(),
.south_enable_i_psum(),
//Destination ports
.south_data_o_psum(),
.south_enable_o_psum(),
//Interface with West
//Source ports
.west_data_i_psum(HMNoC_cluster_west_1.east_data_o_psum), //PE_cluster
.west_enable_i_psum(HMNoC_cluster_west_1.east_enable_o_psum),
//Destination ports
.west_data_o_psum(HMNoC_cluster_west_1.east_data_i_psum), //GLB_cluster
.west_enable_o_psum(HMNoC_cluster_west_1.east_enable_i_psum), //GLB_cluster
//Interface with East - Devices
//Source ports
.east_data_i_psum(),
.east_enable_i_psum(),
//Destination ports
// .east_data_o_psum(east_data_o_psum),
// .east_enable_o_psum(east_enable_o_psum),
//PE Cluster
.load_en_wght(),
.load_en_act(),
.start(),
.pe_out(),
.compute_done(),
.load_done()
);
endmodule
================================================
FILE: rtl/MAC.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/27/2019 09:39:19 AM
// Design Name:
// Module Name: MAC
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MAC #( parameter IN_BITWIDTH = 16,
parameter OUT_BITWIDTH = 2*IN_BITWIDTH )
( input [IN_BITWIDTH-1 : 0] a_in,
input [IN_BITWIDTH-1 : 0] w_in,
input [IN_BITWIDTH-1 : 0] sum_in,
input en, clk,
output logic [OUT_BITWIDTH-1 : 0] out
);
logic [OUT_BITWIDTH-1:0] mult_out;
always@(posedge clk) begin
if(en) begin
mult_out = a_in * w_in;
out <= mult_out + sum_in;
end
end
endmodule
================================================
FILE: rtl/PE.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/27/2019 07:20:21 AM
// Design Name:
// Module Name: PE
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PE #( parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 9,
parameter W_READ_ADDR = 0, //Weights READ address
parameter A_READ_ADDR = 100, //Activations READ address
parameter W_LOAD_ADDR = 0, //Weights LOAD address
parameter A_LOAD_ADDR = 100, //Activations LOAD address
parameter PSUM_ADDR = 500,
parameter int kernel_size = 3,
parameter int act_size = 5 )
( input clk, reset,
input [DATA_WIDTH-1:0] act_in,
input [DATA_WIDTH-1:0] filt_in,
// input load_en,
input load_en_wght, load_en_act,
input start,
output logic [DATA_WIDTH-1:0] pe_out,
output logic compute_done,
output logic load_done
);
enum logic [2:0] {IDLE=3'b000, READ_W=3'b001, READ_A=3'b010, COMPUTE=3'b011,
WRITE=3'b100, LOAD_W=3'b101, LOAD_A=3'b110} state;
// ScratchPad Instantiation
logic read_en, write_en;
logic [ADDR_WIDTH-1:0] w_addr, r_addr;
logic [DATA_WIDTH-1:0] r_data, w_data;
SPad spad_pe0 ( .clk(clk), .reset(reset),
.read_req(read_en),
.write_en(write_en),
.r_addr(r_addr),
.w_addr(w_addr),
.w_data(w_data),
.r_data(r_data)
);
logic [DATA_WIDTH-1:0] psum_reg;
logic [DATA_WIDTH-1:0] sum_in;
logic sum_in_mux_sel;
logic [DATA_WIDTH-1:0] act_in_reg;
logic [DATA_WIDTH-1:0] filt_in_reg;
logic mac_en;
//MAC Instantiation
MAC #( .IN_BITWIDTH(DATA_WIDTH),
.OUT_BITWIDTH(DATA_WIDTH) )
mac_0
( .a_in(act_in_reg),
.w_in(filt_in_reg),
.sum_in(sum_in),
.en(mac_en),
.clk(clk),
.out(psum_reg)
);
mux2 #( .WIDTH(DATA_WIDTH) ) mux2_0 ( .a_in(psum_reg),
.b_in(16'b0),
.sel(sum_in_mux_sel),
.out(sum_in)
);
logic [7:0] filt_count;
logic [2:0] iter;
// FSM for PE
always@(posedge clk) begin
// $display("State: %s", state.name());
if(reset) begin
//Initialize registers
filt_count <= 0;
sum_in_mux_sel = 0;
//Initialize scratchpad inputs
w_addr <= W_READ_ADDR;
r_addr <= W_READ_ADDR;
w_data <= 0;
write_en <= 0;
read_en <= 0;
compute_done <= 0;
mac_en <= 0;
iter <= 0;
load_done <= 0;
state <= IDLE;
end
else begin
case(state)
IDLE:begin
if(start) begin
if(iter == (act_size-kernel_size+1) ) begin
iter <= 0;
state <= IDLE;
end else begin
r_addr <= A_READ_ADDR + iter*act_size;
filt_count <= 0;
sum_in_mux_sel = 0;
read_en <= 1;
state <= READ_W;
end
end else begin
/* if(load_en) begin
w_addr <= W_LOAD_ADDR; //***Loading of weights starts at index 0***
w_data <= filt_in;
write_en <= 1;
filt_count <= 0;
state <= LOAD_W; */
if(load_en_wght) begin
w_addr <= W_LOAD_ADDR; //***Loading of weights starts at index 0***
w_data <= filt_in;
write_en <= 1;
filt_count <= 0;
state <= LOAD_W;
end else if(load_en_act) begin
write_en <= 1;
w_addr <= A_LOAD_ADDR; // *** Loading of activations starts at 100 ***
w_data <= act_in;
state <= LOAD_A;
end else begin
load_done <= 0;
write_en <= 0;
compute_done <= 0;
state <= IDLE;
end
end
end
READ_W:begin
filt_in_reg <= r_data;
read_en <= 1;
filt_count <= filt_count + 1;
// $display("Weight read: %d from address: %d", r_data, r_addr);
// $display("Read Enable: %d", read_en);
state <= READ_A;
end
READ_A:begin
// $display("Act read: %d from address: %d", r_data, r_addr);
// $display("Read Enable: %d", read_en);
act_in_reg <= r_data;
read_en <= 1;
r_addr <= W_READ_ADDR + filt_count;
mac_en <= 1;
state <= COMPUTE;
end
COMPUTE:begin
// $display("Weight in reg: %d | Act in reg: %d", filt_in_reg, act_in_reg);
// $display("MAC out: %d", psum_reg);
mac_en <= 0;
if(filt_count == kernel_size) begin
act_in_reg <= r_data;
read_en <= 0;
w_addr <= PSUM_ADDR + iter;
write_en <= 1;
state <= WRITE;
end else begin
if(filt_count == 0) begin
sum_in_mux_sel = 0;
end else begin
sum_in_mux_sel = 1;
end
r_addr <= A_READ_ADDR + filt_count + iter*act_size;
state <= READ_W;
end
end
WRITE:begin
w_data <= psum_reg;
r_addr <= W_READ_ADDR;
read_en <= 1;
iter <= iter + 1;
compute_done <= 1;
state <= IDLE;
end
LOAD_W:begin
// $display("Weight write: %d to address: %d", filt_in, w_addr);
// $display("Write Enable: %d", write_en);
/* if(filt_count == (kernel_size**2-1)) begin
w_addr <= A_LOAD_ADDR; // *** Loading of activations starts at 100 ***
w_data <= act_in;
filt_count <= 0;
state <= LOAD_A; */
if(filt_count == (kernel_size**2-1)) begin
filt_count <= 0;
load_done <= 1;
state <= IDLE;
end else begin
w_data <= filt_in;
w_addr <= w_addr + 1;
filt_count <= filt_count + 1;
state <= LOAD_W;
end
end
LOAD_A:begin
// $display("Act write: %d to address: %d", act_in, w_addr);
// $display("Write Enable: %d", write_en);
if(filt_count == (act_size**2-1)) begin
write_en <= 0;
read_en <= 1;
r_addr <= W_READ_ADDR;
load_done <= 1;
state <= IDLE;
end else begin
w_data <= act_in;
w_addr <= w_addr + 1;
filt_count <= filt_count + 1;
state <= LOAD_A;
end
end
endcase
end
end
assign pe_out = psum_reg;
endmodule
================================================
FILE: rtl/PE_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/29/2019 09:11:06 PM
// Design Name:
// Module Name: PE_cluster
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PE_cluster #(parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 9,
parameter int X_dim = 5,
parameter int Y_dim = 3,
parameter int kernel_size = 3,
parameter int act_size = 5,
parameter W_READ_ADDR = 0,
parameter A_READ_ADDR = 100,
parameter W_LOAD_ADDR = 0,
parameter A_LOAD_ADDR = 100,
parameter PSUM_ADDR = 500
)
(
input clk, reset,
input [DATA_WIDTH-1:0] act_in,
input [DATA_WIDTH-1:0] filt_in,
// input load_en,
input load_en_wght, load_en_act,
input start,
output logic [DATA_WIDTH-1:0] pe_out[0 : X_dim-1],
output logic compute_done,
output logic load_done
//extra
// output logic [DATA_WIDTH-1:0] psum_out[0 : X_dim*Y_dim-1]
);
logic [DATA_WIDTH-1:0] psum_out[0 : X_dim*Y_dim-1];
logic cluster_done[0 : X_dim*Y_dim-1];
logic cluster_load_done[0 : X_dim*Y_dim-1];
generate
genvar i;
for(i=0; i<X_dim; i++)
begin:gen_X
genvar j;
for(j=0; j<Y_dim; j++)
begin:gen_Y
PE #( .DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.kernel_size(kernel_size),
.act_size(act_size),
.W_READ_ADDR(W_READ_ADDR + kernel_size*j),
.A_READ_ADDR(A_READ_ADDR + act_size*j + i),
.W_LOAD_ADDR(W_LOAD_ADDR),
.A_LOAD_ADDR(A_LOAD_ADDR),
.PSUM_ADDR(PSUM_ADDR)
)
pe (
.clk(clk),
.reset(reset),
.act_in(act_in),
.filt_in(filt_in),
// .load_en(load_en),
.load_en_wght(load_en_wght),
.load_en_act(load_en_act),
.start(start),
.pe_out(psum_out[i*Y_dim+j]),
.compute_done(cluster_done[i*Y_dim+j]),
.load_done(cluster_load_done[i*Y_dim+j])
);
end
end
endgenerate
/* virtual class psum_adder_class #(parameter X_dim, parameter Y_dim, parameter DATA_WIDTH);
static function logic [DATA_WIDTH-1 : 0] psum_adder
(
input logic [DATA_WIDTH-1:0] psum_out[X_dim*Y_dim-1 : 0]
);
begin
psum_adder = {(DATA_WIDTH){1'b0}};
for(int i=0; i<Y_dim; i++) begin
psum_adder = psum_adder + psum_out[Y_dim*X_dim+i];
end
end
endfunction
endclass */
function logic [DATA_WIDTH-1 : 0] psum_adder
(
input logic [DATA_WIDTH-1:0] psum_out[0 : X_dim*Y_dim-1],
input logic [3:0] X_dim,
input logic [3:0] Y_dim
);
begin
psum_adder = {(DATA_WIDTH){1'b0}};
for(int i=0; i<Y_dim; i++) begin
psum_adder = psum_adder + psum_out[Y_dim*X_dim+i];
end
end
endfunction
/* always@(posedge clk) begin
if(reset) begin
for(int i=0; i<X_dim; i++) begin
pe_out[i] <= 0;
end
end else begin
for(int i=0; i<X_dim; i++) begin
pe_out[i] <= psum_adder_class#
(.X_dim(i),
.Y_dim(Y_dim),
.DATA_WIDTH(DATA_WIDTH)
)
::psum_adder(psum_out);
end
end
end */
// Add partial sums and register at pe_out
always@(posedge clk) begin
if(reset) begin
for(int i=0; i<X_dim; i++) begin
pe_out[i] <= 0;
end
end else begin
for(int i=0; i<X_dim; i++) begin
pe_out[i] <= psum_adder(psum_out,i,Y_dim);
end
end
end
assign compute_done = cluster_done[0];
assign load_done = cluster_load_done[0];
// assign pe_out[X_dim-1:0] = psum_out[X_dim*Y_dim-1 : 0]
endmodule
================================================
FILE: rtl/SPad.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/27/2019 10:35:28 AM
// Design Name:
// Module Name: SPad
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SPad #( parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 9 )
( input clk,
input reset,
input read_req,
input write_en,
input [ADDR_BITWIDTH-1 : 0] r_addr,
input [ADDR_BITWIDTH-1 : 0] w_addr,
input [DATA_BITWIDTH-1 : 0] w_data,
output logic [DATA_BITWIDTH-1 : 0] r_data
);
logic [DATA_BITWIDTH-1 : 0] mem [0 : (1 << ADDR_BITWIDTH) - 1];
// default - 512(2^9) 16-bit memory. Total size = 1kB
logic [DATA_BITWIDTH-1 : 0] data;
always@(posedge clk)
begin : READ
if(reset)
data <= 0;
else
begin
if(read_req) begin
data <= mem[r_addr];
// $display("Read Address to SPad:%d",r_addr);
end else begin
data <= 10101;
end
end
end
assign r_data = data;
always@(posedge clk)
begin : WRITE
$display("\t\t\t\t\t Current Status:\n \
\t mem[0]:%d", mem[0],
" | mem[1]:%d", mem[1],
" | mem[2]:%d", mem[2],
" | mem[3]:%d", mem[3],
" | mem[4]:%d", mem[4],
" | mem[5]:%d", mem[5],
" | mem[8]:%d", mem[8],
" | mem[24]:%d\n", mem[24],
" \t\t\t\t\t mem[100]:%d", mem[100],
" | mem[101]:%d", mem[101],
" | mem[102]:%d", mem[102],
" | mem[103]:%d", mem[103],
" | mem[104]:%d", mem[104],
" | mem[105]:%d\n", mem[105],
" | mem[124]:%d\n", mem[124],
" | mem[148]:%d\n", mem[148],
" \t\t\t\t\t psum:%d", mem[500],
" | psum:%d", mem[501],
" | psum:%d", mem[502],
" | psum:%d", mem[503],
" | psum:%d", mem[504]
);
if(write_en && !reset) begin
mem[w_addr] <= w_data;
end
end
endmodule
================================================
FILE: rtl/circular_buffer.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/08/2019 04:33:37 PM
// Design Name:
// Module Name: circular_buffer
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module circular_buffer#(
parameter BUFFER_SIZE = 8,
parameter DATA_SIZE = 16
)
(
input clk,
input reset,
input [DATA_SIZE-1:0] data_i,
input read_en_i,
input write_en_i,
output [DATA_SIZE-1:0] data_o,
output logic full_o,
output logic empty_o
// output logic on_off_o
);
localparam [31:0] POINTER_SIZE = $clog2(BUFFER_SIZE);
logic [DATA_SIZE-1:0] mem[BUFFER_SIZE-1:0];
logic [POINTER_SIZE-1:0] read_ptr;
logic [POINTER_SIZE-1:0] write_ptr;
logic [POINTER_SIZE-1:0] read_ptr_next;
logic [POINTER_SIZE-1:0] write_ptr_next;
logic full_next;
logic empty_next;
logic on_off_next;
logic [POINTER_SIZE:0] num_flits;
logic [POINTER_SIZE:0] num_flits_next;
always_ff@(posedge clk) begin
if(reset) begin
read_ptr <= 0;
write_ptr <= 0;
full_o <= 0;
empty_o <= 0;
// on_off_o <= 0;
end else begin
read_ptr <= read_ptr_next;
write_ptr <= write_ptr_next;
full_o <= full_next;
empty_o <= empty_next;
// on_off_o <= on_off_next;
if((!read_en_i & write_en_i & !full_o) | (read_en_i & write_en_i))
mem[write_ptr] <= data_i;
end
end
always_comb begin
data_o = mem[read_ptr];
unique
if(read_en_i & !write_en_i & !empty_o)
begin: read_not_empty
read_ptr_next = incr_ptr(read_ptr);
write_ptr_next = write_ptr;
full_next = 0;
update_empty();
num_flits_next = num_flits - 1;
end
else if(!read_en_i & write_en_i & !full_o)
begin:write_not_full
read_ptr_next = read_ptr;
write_ptr_next = incr_ptr(write_ptr);
update_full();
num_flits_next = num_flits + 1;
end
else if(read_en_i & write_en_i & !empty_o)
begin:read_write_not_empty
read_ptr_next = incr_ptr(read_ptr);
write_ptr_next = incr_ptr(write_ptr);
full_next = full_o;
empty_next = empty_o;
num_flits_next = num_flits;
end
else
begin:idle
read_ptr_next = read_ptr;
write_ptr_next = write_ptr;
full_next = full_o;
empty_next = empty_o;
num_flits_next = num_flits;
end
// begin:update_
end
function logic [POINTER_SIZE-1:0] incr_ptr (
input logic [POINTER_SIZE-1:0] ptr );
if(ptr == BUFFER_SIZE-1)
incr_ptr = 0;
else
incr_ptr = ptr + 1;
endfunction
function void update_empty();
if(read_ptr_next == write_ptr)
empty_next = 1;
else
empty_next = 0;
endfunction
function void update_full();
if(write_ptr_next == read_ptr)
full_next = 1;
else
full_next = 0;
endfunction
endmodule
================================================
FILE: rtl/glb_iact.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/01/2019 12:56:24 PM
// Design Name:
// Module Name: glb_iact
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module glb_iact #( parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 10 )
( input clk,
input reset,
input read_req,
input write_en,
input [ADDR_BITWIDTH-1 : 0] r_addr,
input [ADDR_BITWIDTH-1 : 0] w_addr,
input [DATA_BITWIDTH-1 : 0] w_data,
output logic [DATA_BITWIDTH-1 : 0] r_data
);
logic [DATA_BITWIDTH-1 : 0] mem [0 : (1 << ADDR_BITWIDTH) - 1];
// default - 1024(2^10) 16-bit memory. Total size = 2kB
logic [DATA_BITWIDTH-1 : 0] data;
always@(posedge clk)
begin : READ
if(reset)
data = 0;
else
begin
if(read_req) begin
data = mem[r_addr];
// $display("Read Address to SPad:%d",r_addr);
end else begin
data = 10101; //Random default value to verify model
end
end
end
assign r_data = data;
always@(posedge clk)
begin : WRITE
if(write_en && !reset) begin
mem[w_addr] = w_data;
end
end
endmodule
================================================
FILE: rtl/glb_psum.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/01/2019 01:13:40 PM
// Design Name:
// Module Name: glb_psum
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module glb_psum #( parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 10 )
( input clk,
input reset,
input read_req,
input write_en,
input [ADDR_BITWIDTH-1 : 0] r_addr,
input [ADDR_BITWIDTH-1 : 0] w_addr,
input [DATA_BITWIDTH-1 : 0] w_data,
output logic [DATA_BITWIDTH-1 : 0] r_data
);
logic [DATA_BITWIDTH-1 : 0] mem [0 : (1 << ADDR_BITWIDTH) - 1];
// default - 1024(2^10) 16-bit memory. Total size = 2kB
logic [DATA_BITWIDTH-1 : 0] data;
always@(posedge clk)
begin : READ
if(reset)
data = 0;
else
begin
if(read_req) begin
data = mem[r_addr];
// $display("Read Address to SPad:%d",r_addr);
end else begin
data = 10101; //Random default value to verify model
end
end
end
assign r_data = data;
always@(posedge clk)
begin : WRITE
/* $display("\t\t\t\t\t Current Status in glb_psum:\n \
\t psum[0]:%d", mem[0],
" | psum[1]:%d", mem[1],
" | psum[2]:%d", mem[2],
" | psum[3]:%d", mem[3],
" | psum[4]:%d", mem[4],
" | psum[5]:%d", mem[5],
" | psum[6]:%d", mem[6],
" | psum[7]:%d", mem[7],
" | psum[8]:%d", mem[8],
" | psum[9]:%d", mem[9]
);
$display("WriteEn: %d\n",write_en);
$display("Write Data: %d\n",w_data);
$display("Write Addr: %d\n\n\n",w_addr); */
if(write_en && !reset) begin
mem[w_addr] = w_data;
end
end
endmodule
================================================
FILE: rtl/glb_weight.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/01/2019 04:07:04 PM
// Design Name:
// Module Name: glb_weight
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module glb_weight #( parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 10 )
( input clk,
input reset,
input read_req,
input write_en,
input [ADDR_BITWIDTH-1 : 0] r_addr,
input [ADDR_BITWIDTH-1 : 0] w_addr,
input [DATA_BITWIDTH-1 : 0] w_data,
output logic [DATA_BITWIDTH-1 : 0] r_data
);
logic [DATA_BITWIDTH-1 : 0] mem [0 : (1 << ADDR_BITWIDTH) - 1];
// default - 1024(2^10) 16-bit memory. Total size = 2kB
logic [DATA_BITWIDTH-1 : 0] data;
always@(posedge clk)
begin : READ
if(reset)
data = 0;
else
begin
if(read_req) begin
data = mem[r_addr];
// $display("Read Address to SPad:%d",r_addr);
end else begin
data = 10101; //Random default value to verify model
end
end
end
assign r_data = data;
always@(posedge clk)
begin : WRITE
if(write_en && !reset) begin
mem[w_addr] = w_data;
end
end
endmodule
================================================
FILE: rtl/lookup_mux4.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/09/2019 07:41:07 AM
// Design Name:
// Module Name: lookup_mux4
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lookup_mux4
(
input [3:0] in,
output logic [1:0] out
);
always_comb begin
unique if(in == 4'b0000)
out = 0;
else if(in == 4'b0010)
out = 1;
else if(in == 4'b0100)
out = 2;
else if(in == 4'b1000)
out = 3;
end
endmodule
================================================
FILE: rtl/misc/FA.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/27/2019 07:43:21 AM
// Design Name:
// Module Name: FA
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FA( input A_in,
input B_in,
input C_in,
output logic S_out,
output logic C_out
);
assign {C_out, S_out} = A_in + B_in + C_in;
endmodule
================================================
FILE: rtl/misc/HA.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/27/2019 07:30:57 AM
// Design Name:
// Module Name: HA
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HA( input A_in,
input B_in,
output logic S_out,
output logic C_out
);
assign {C_out,S_out} = A_in + B_in;
endmodule
================================================
FILE: rtl/misc/circular_buffer.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/08/2019 04:33:37 PM
// Design Name:
// Module Name: circular_buffer
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module circular_buffer#(
parameter BUFFER_SIZE = 8,
parameter DATA_SIZE = 16
)
(
input clk,
input reset,
input [DATA_SIZE-1:0] data_i,
input read_en_i,
input write_en_i,
output [DATA_SIZE-1:0] data_o,
output logic full_o,
output logic empty_o
// output logic on_off_o
);
localparam [31:0] POINTER_SIZE = $clog2(BUFFER_SIZE);
logic [DATA_SIZE-1:0] mem[BUFFER_SIZE-1:0];
logic [POINTER_SIZE-1:0] read_ptr;
logic [POINTER_SIZE-1:0] write_ptr;
logic [POINTER_SIZE-1:0] read_ptr_next;
logic [POINTER_SIZE-1:0] write_ptr_next;
logic full_next;
logic empty_next;
logic on_off_next;
logic [POINTER_SIZE:0] num_flits;
logic [POINTER_SIZE:0] num_flits_next;
always_ff@(posedge clk) begin
if(reset) begin
read_ptr <= 0;
write_ptr <= 0;
full_o <= 0;
empty_o <= 0;
// on_off_o <= 0;
end else begin
read_ptr <= read_ptr_next;
write_ptr <= write_ptr_next;
full_o <= full_next;
empty_o <= empty_next;
// on_off_o <= on_off_next;
if((!read_en_i & write_en_i & !full_o) | (read_en_i & write_en_i))
mem[write_ptr] <= data_i;
end
end
always_comb begin
data_o = mem[read_ptr];
unique
if(read_en_i & !write_en_i & !empty_o)
begin: read_not_empty
read_ptr_next = incr_ptr(read_ptr);
write_ptr_next = write_ptr;
full_next = 0;
update_empty();
num_flits_next = num_flits - 1;
end
else if(!read_en_i & write_en_i & !full_o)
begin:write_not_full
read_ptr_next = read_ptr;
write_ptr_next = incr_ptr(write_ptr);
update_full();
num_flits_next = num_flits + 1;
end
else if(read_en_i & write_en_i & !empty_o)
begin:read_write_not_empty
read_ptr_next = incr_ptr(read_ptr);
write_ptr_next = incr_ptr(write_ptr);
full_next = full_o;
empty_next = empty_o;
num_flits_next = num_flits;
end
else
begin:idle
read_ptr_next = read_ptr;
write_ptr_next = write_ptr;
full_next = full_o;
empty_next = empty_o;
num_flits_next = num_flits;
end
// begin:update_
end
function logic [POINTER_SIZE-1:0] incr_ptr (
input logic [POINTER_SIZE-1:0] ptr );
if(ptr == BUFFER_SIZE-1)
incr_ptr = 0;
else
incr_ptr = ptr + 1;
endfunction
function void update_empty();
if(read_ptr_next == write_ptr)
empty_next = 1;
else
empty_next = 0;
endfunction
function void update_full();
if(write_ptr_next == read_ptr)
full_next = 1;
else
full_next = 0;
endfunction
endmodule
================================================
FILE: rtl/misc/mux_4x1.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/09/2019 07:22:05 AM
// Design Name:
// Module Name: mux_4x1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mux_4x1 #(parameter DATA_WIDTH=16)
(
input [DATA_WIDTH-1:0] a,
input [DATA_WIDTH-1:0] b,
input [DATA_WIDTH-1:0] c,
input [DATA_WIDTH-1:0] d,
input [1:0] sel,
output logic [DATA_WIDTH-1:0] out
);
assign out = sel[1] ? (sel[0] ? d : c) : (sel[0] ? b : a) ;
endmodule
================================================
FILE: rtl/misc/switch.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/09/2019 08:10:01 AM
// Design Name:
// Module Name: switch
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module switch
#(
parameter DATA_WIDTH = 16
)
(
input [DATA_WIDTH-1:0] a,
input [DATA_WIDTH-1:0] b,
input [DATA_WIDTH-1:0] c,
input [DATA_WIDTH-1:0] d,
input [3:0] sel,
output logic [DATA_WIDTH-1:0] out
);
logic [1:0] s;
lookup_mux4 lookup_0 ( .in(sel), .out(s) );
mux_4x1 mux_0 ( .sel(s), .a(a), .b(b), .c(c), .d(d), .out(out) );
endmodule
================================================
FILE: rtl/mux2.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/28/2019 01:14:05 AM
// Design Name:
// Module Name: mux_2_1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mux2 #( parameter WIDTH = 16)
(
input [WIDTH-1:0] a_in,
input [WIDTH-1:0] b_in,
input sel,
output [WIDTH-1:0] out
);
assign out = sel ? a_in : b_in;
endmodule
================================================
FILE: rtl/mux_4x1.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/09/2019 07:22:05 AM
// Design Name:
// Module Name: mux_4x1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mux_4x1 #(parameter DATA_WIDTH=16)
(
input [DATA_WIDTH-1:0] a,
input [DATA_WIDTH-1:0] b,
input [DATA_WIDTH-1:0] c,
input [DATA_WIDTH-1:0] d,
input [1:0] sel,
output logic [DATA_WIDTH-1:0] out
);
assign out = sel[1] ? (sel[0] ? d : c) : (sel[0] ? b : a) ;
endmodule
================================================
FILE: rtl/phase_1/GLB_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/01/2019 01:18:56 PM
// Design Name:
// Module Name: GLB_cluster
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GLB_cluster
#(
parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 10,
parameter NUM_GLB_IACT = 1,
parameter NUM_GLB_PSUM = 1,
parameter NUM_GLB_WGHT = 1
)
( input clk,
input reset,
input read_req_iact,
input read_req_psum,
input read_req_wght,
input write_en_iact,
input write_en_psum,
input write_en_wght,
input [ADDR_BITWIDTH-1 : 0] r_addr_iact,
input [ADDR_BITWIDTH-1 : 0] r_addr_psum,
input [ADDR_BITWIDTH-1 : 0] r_addr_wght,
input [ADDR_BITWIDTH-1 : 0] w_addr_iact,
input [ADDR_BITWIDTH-1 : 0] w_addr_psum,
input [ADDR_BITWIDTH-1 : 0] w_addr_wght,
input [DATA_BITWIDTH-1 : 0] w_data_iact,
input [DATA_BITWIDTH-1 : 0] w_data_psum,
input [DATA_BITWIDTH-1 : 0] w_data_wght,
output logic [DATA_BITWIDTH-1 : 0] r_data_iact,
output logic [DATA_BITWIDTH-1 : 0] r_data_psum,
output logic [DATA_BITWIDTH-1 : 0] r_data_wght
);
//Instantiate iact global buffer
generate
genvar i;
for(i=0; i<NUM_GLB_IACT; i++)
begin:glb_iact_gen
glb_iact #( .ADDR_BITWIDTH(ADDR_BITWIDTH),
.DATA_BITWIDTH(DATA_BITWIDTH)
)
glb_iact_inst ( .clk(clk),
.reset(reset),
.read_req(read_req_iact),
.write_en(write_en_iact),
.r_addr(r_addr_iact),
.w_data(w_data_iact),
.r_data(r_data_iact),
.w_addr(w_addr_iact)
);
end
endgenerate
//Instantiate psum global buffer
generate
genvar j;
for(j=0; j<NUM_GLB_PSUM; j++)
begin:glb_psum_gen
glb_psum #( .ADDR_BITWIDTH(ADDR_BITWIDTH),
.DATA_BITWIDTH(DATA_BITWIDTH)
)
glb_psum_inst ( .clk(clk),
.reset(reset),
.read_req(read_req_psum),
.write_en(write_en_psum),
.r_addr(r_addr_psum),
.w_data(w_data_psum),
.r_data(r_data_psum),
.w_addr(w_addr_psum)
);
end
endgenerate
//Instantiate weight global buffer
generate
genvar k;
for(k=0; k<NUM_GLB_WGHT; k++)
begin:glb_wght_gen
glb_weight #( .ADDR_BITWIDTH(ADDR_BITWIDTH),
.DATA_BITWIDTH(DATA_BITWIDTH)
)
glb_weight_inst ( .clk(clk),
.reset(reset),
.read_req(read_req_wght),
.write_en(write_en_wght),
.r_addr(r_addr_wght),
.w_data(w_data_wght),
.r_data(r_data_wght),
.w_addr(w_addr_wght)
);
end
endgenerate
endmodule
================================================
FILE: rtl/phase_1/HMNoC_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/04/2019 06:59:19 AM
// Design Name:
// Module Name: HMNoC_cluster
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HMNoC_cluster#(
parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 10,
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 9,
// GLB Cluster parameters. This TestBench uses only 1 of each
parameter NUM_GLB_IACT = 1,
parameter NUM_GLB_PSUM = 1,
parameter NUM_GLB_WGHT = 1,
parameter ADDR_BITWIDTH_GLB = 10,
parameter ADDR_BITWIDTH_SPAD = 9,
parameter NUM_ROUTER_PSUM = 1,
parameter NUM_ROUTER_IACT = 1,
parameter NUM_ROUTER_WGHT = 1,
parameter int kernel_size = 3,
parameter int act_size = 5,
parameter int X_dim = 3,
parameter int Y_dim = 3,
parameter W_READ_ADDR = 0,
parameter A_READ_ADDR = 0,
parameter W_LOAD_ADDR = 0,
parameter A_LOAD_ADDR = 0,
parameter PSUM_READ_ADDR = 0,
parameter PSUM_LOAD_ADDR = 0
)
(
input clk,
input reset,
input start,
output load_done,
//logic for GLB cluster
input read_req_psum,
input write_en_iact,
input write_en_wght,
input load_spad_ctrl_wght,
input load_spad_ctrl_iact,
input [ADDR_BITWIDTH-1 : 0] r_addr_psum,
output logic [DATA_BITWIDTH-1 : 0] r_data_psum,
input [ADDR_BITWIDTH-1 : 0] w_addr_iact,
input [ADDR_BITWIDTH-1 : 0] w_addr_psum,
input [ADDR_BITWIDTH-1 : 0] w_addr_wght,
input [DATA_BITWIDTH-1 : 0] w_data_iact,
input [DATA_BITWIDTH-1 : 0] w_data_psum,
input [DATA_BITWIDTH-1 : 0] w_data_wght
);
// logic [DATA_WIDTH-1:0] act_in;
// logic [DATA_WIDTH-1:0] filt_in;
// logic load_en_wght, load_en_act;
// logic [DATA_BITWIDTH-1 : 0] r_data_spad_psum[0:kernel_size-1];
//GLB cluster initialization
GLB_cluster
#( .DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH(ADDR_BITWIDTH),
.NUM_GLB_IACT(NUM_GLB_IACT),
.NUM_GLB_PSUM(NUM_GLB_PSUM),
.NUM_GLB_WGHT(NUM_GLB_WGHT)
)
GLB_cluster_0
(
.clk(clk), //TestBench/Controller
.reset(reset), //TestBench/Controller
//Signals for reading from GLB
.read_req_iact(router_cluster_0.read_req_glb_iact),
.read_req_psum(read_req_psum), //Read by testbench/controller
.read_req_wght(router_cluster_0.read_req_glb_wght),
.r_data_iact(router_cluster_0.r_data_glb_iact),
.r_data_psum(r_data_psum), //Read by testbench/controller
.r_data_wght(router_cluster_0.r_data_glb_wght),
.r_addr_iact(router_cluster_0.r_addr_glb_iact),
.r_addr_psum(r_addr_psum), //testbench for reading final psums
.r_addr_wght(router_cluster_0.r_addr_glb_wght),
//Signals for writing to GLB
.w_addr_iact(w_addr_iact), //testbench for writing
.w_addr_psum(router_cluster_0.w_addr_glb_psum),
.w_addr_wght(w_addr_wght), //testbench for writing
.w_data_iact(w_data_iact), //testbench for writing
.w_data_psum(router_cluster_0.w_data_glb_psum),
.w_data_wght(w_data_wght), //testbench for writing
.write_en_iact(write_en_iact), //testbench for writing
.write_en_psum(router_cluster_0.write_en_glb_psum),
.write_en_wght(write_en_wght) //testbench for writing
);
//Router Cluster Instantiation
router_cluster#(.DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),
.kernel_size(kernel_size),
.act_size(act_size),
.NUM_ROUTER_PSUM(NUM_ROUTER_PSUM),
.NUM_ROUTER_IACT(NUM_ROUTER_IACT),
.NUM_ROUTER_WGHT(NUM_ROUTER_WGHT),
.A_READ_ADDR(A_READ_ADDR),
.A_LOAD_ADDR(A_LOAD_ADDR),
.W_READ_ADDR(W_READ_ADDR),
.W_LOAD_ADDR(W_LOAD_ADDR),
.PSUM_READ_ADDR(PSUM_READ_ADDR),
.PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
)
router_cluster_0
(
.clk(clk), //TestBench/Controller
.reset(reset), //TestBench/Controller
//Signals for activation router
.r_data_glb_iact(GLB_cluster_0.r_data_iact),
.r_addr_glb_iact(GLB_cluster_0.r_addr_iact),
.read_req_glb_iact(GLB_cluster_0.read_req_iact),
.w_data_spad_iact(pe_cluster_0.act_in),
.load_en_spad_iact(pe_cluster_0.load_en_act),
.load_spad_ctrl_iact(load_spad_ctrl_iact), //TestBench/Controller
//Signals for weight router
.r_data_glb_wght(GLB_cluster_0.r_data_wght),
.r_addr_glb_wght(GLB_cluster_0.r_addr_wght),
.read_req_glb_wght(GLB_cluster_0.read_req_wght),
.w_data_spad_wght(pe_cluster_0.filt_in),
.load_en_spad_wght(pe_cluster_0.load_en_wght),
.load_spad_ctrl_wght(load_spad_ctrl_wght), //TestBench/Controller
//Signals for psum router
.r_data_spad_psum(pe_cluster_0.pe_out),
.w_addr_glb_psum(GLB_cluster_0.w_addr_psum),
.write_en_glb_psum(GLB_cluster_0.write_en_psum),
.w_data_glb_psum(GLB_cluster_0.w_data_psum),
.write_psum_ctrl(pe_cluster_0.compute_done) //Connected to compute done of PE
);
//Declarations for PE_cluster
//PE_cluster Instantiation
PE_cluster #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.kernel_size(kernel_size),
.act_size(act_size),
.X_dim(X_dim),
.Y_dim(Y_dim)
)
pe_cluster_0
(
.clk(clk), //TestBench/Controller
.reset(reset), //TestBench/Controller
.start(start), //TestBench/Controller
.act_in(router_cluster_0.w_data_spad_iact),
.filt_in(router_cluster_0.w_data_spad_wght),
.load_en_wght(router_cluster_0.load_en_spad_wght),
.load_en_act(router_cluster_0.load_en_spad_iact),
.pe_out(router_cluster_0.r_data_spad_psum),
.compute_done(router_cluster_0.write_psum_ctrl),
.load_done(load_done) //TestBench/Controller
);
endmodule
================================================
FILE: rtl/phase_1/PE.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/27/2019 07:20:21 AM
// Design Name:
// Module Name: PE
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PE #( parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 9,
parameter W_READ_ADDR = 0, //Weights READ address
parameter A_READ_ADDR = 100, //Activations READ address
parameter W_LOAD_ADDR = 0, //Weights LOAD address
parameter A_LOAD_ADDR = 100, //Activations LOAD address
parameter PSUM_ADDR = 500,
parameter int kernel_size = 3,
parameter int act_size = 5 )
( input clk, reset,
input [DATA_WIDTH-1:0] act_in,
input [DATA_WIDTH-1:0] filt_in,
// input load_en,
input load_en_wght, load_en_act,
input start,
output logic [DATA_WIDTH-1:0] pe_out,
output logic compute_done,
output logic load_done
);
enum logic [2:0] {IDLE=3'b000, READ_W=3'b001, READ_A=3'b010, COMPUTE=3'b011,
WRITE=3'b100, LOAD_W=3'b101, LOAD_A=3'b110} state;
// ScratchPad Instantiation
logic read_en, write_en;
logic [ADDR_WIDTH-1:0] w_addr, r_addr;
logic [DATA_WIDTH-1:0] r_data, w_data;
SPad spad_pe0 ( .clk(clk), .reset(reset),
.read_req(read_en),
.write_en(write_en),
.r_addr(r_addr),
.w_addr(w_addr),
.w_data(w_data),
.r_data(r_data)
);
logic [DATA_WIDTH-1:0] psum_reg;
logic [DATA_WIDTH-1:0] sum_in;
logic sum_in_mux_sel;
logic [DATA_WIDTH-1:0] act_in_reg;
logic [DATA_WIDTH-1:0] filt_in_reg;
logic mac_en;
//MAC Instantiation
MAC #( .IN_BITWIDTH(DATA_WIDTH),
.OUT_BITWIDTH(DATA_WIDTH) )
mac_0
( .a_in(act_in_reg),
.w_in(filt_in_reg),
.sum_in(sum_in),
.en(mac_en),
.clk(clk),
.out(psum_reg)
);
mux2 #( .WIDTH(DATA_WIDTH) ) mux2_0 ( .a_in(psum_reg),
.b_in(16'b0),
.sel(sum_in_mux_sel),
.out(sum_in)
);
logic [7:0] filt_count;
logic [2:0] iter;
// FSM for PE
always@(posedge clk) begin
// $display("State: %s", state.name());
if(reset) begin
//Initialize registers
filt_count <= 0;
sum_in_mux_sel = 0;
//Initialize scratchpad inputs
w_addr <= W_READ_ADDR;
r_addr <= W_READ_ADDR;
w_data <= 0;
write_en <= 0;
read_en <= 0;
compute_done <= 0;
mac_en <= 0;
iter <= 0;
load_done <= 0;
state <= IDLE;
end
else begin
case(state)
IDLE:begin
if(start) begin
if(iter == (act_size-kernel_size+1) ) begin
iter <= 0;
state <= IDLE;
end else begin
r_addr <= A_READ_ADDR + iter*act_size;
filt_count <= 0;
sum_in_mux_sel = 0;
read_en <= 1;
state <= READ_W;
end
end else begin
/* if(load_en) begin
w_addr <= W_LOAD_ADDR; //***Loading of weights starts at index 0***
w_data <= filt_in;
write_en <= 1;
filt_count <= 0;
state <= LOAD_W; */
if(load_en_wght) begin
w_addr <= W_LOAD_ADDR; //***Loading of weights starts at index 0***
w_data <= filt_in;
write_en <= 1;
filt_count <= 0;
state <= LOAD_W;
end else if(load_en_act) begin
write_en <= 1;
w_addr <= A_LOAD_ADDR; // *** Loading of activations starts at 100 ***
w_data <= act_in;
state <= LOAD_A;
end else begin
load_done <= 0;
write_en <= 0;
compute_done <= 0;
state <= IDLE;
end
end
end
READ_W:begin
filt_in_reg <= r_data;
read_en <= 1;
filt_count <= filt_count + 1;
// $display("Weight read: %d from address: %d", r_data, r_addr);
// $display("Read Enable: %d", read_en);
state <= READ_A;
end
READ_A:begin
// $display("Act read: %d from address: %d", r_data, r_addr);
// $display("Read Enable: %d", read_en);
act_in_reg <= r_data;
read_en <= 1;
r_addr <= W_READ_ADDR + filt_count;
mac_en <= 1;
state <= COMPUTE;
end
COMPUTE:begin
// $display("Weight in reg: %d | Act in reg: %d", filt_in_reg, act_in_reg);
// $display("MAC out: %d", psum_reg);
mac_en <= 0;
if(filt_count == kernel_size) begin
act_in_reg <= r_data;
read_en <= 0;
w_addr <= PSUM_ADDR + iter;
write_en <= 1;
state <= WRITE;
end else begin
if(filt_count == 0) begin
sum_in_mux_sel = 0;
end else begin
sum_in_mux_sel = 1;
end
r_addr <= A_READ_ADDR + filt_count + iter*act_size;
state <= READ_W;
end
end
WRITE:begin
w_data <= psum_reg;
r_addr <= W_READ_ADDR;
read_en <= 1;
iter <= iter + 1;
compute_done <= 1;
state <= IDLE;
end
LOAD_W:begin
// $display("Weight write: %d to address: %d", filt_in, w_addr);
// $display("Write Enable: %d", write_en);
/* if(filt_count == (kernel_size**2-1)) begin
w_addr <= A_LOAD_ADDR; // *** Loading of activations starts at 100 ***
w_data <= act_in;
filt_count <= 0;
state <= LOAD_A; */
if(filt_count == (kernel_size**2-1)) begin
filt_count <= 0;
load_done <= 1;
state <= IDLE;
end else begin
w_data <= filt_in;
w_addr <= w_addr + 1;
filt_count <= filt_count + 1;
state <= LOAD_W;
end
end
LOAD_A:begin
// $display("Act write: %d to address: %d", act_in, w_addr);
// $display("Write Enable: %d", write_en);
if(filt_count == (act_size**2-1)) begin
write_en <= 0;
read_en <= 1;
r_addr <= W_READ_ADDR;
load_done <= 1;
state <= IDLE;
end else begin
w_data <= act_in;
w_addr <= w_addr + 1;
filt_count <= filt_count + 1;
state <= LOAD_A;
end
end
endcase
end
end
assign pe_out = psum_reg;
endmodule
================================================
FILE: rtl/phase_1/PE_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/29/2019 09:11:06 PM
// Design Name:
// Module Name: PE_cluster
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PE_cluster #(parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 9,
parameter int X_dim = 5,
parameter int Y_dim = 3,
parameter int kernel_size = 3,
parameter int act_size = 5,
parameter W_READ_ADDR = 0,
parameter A_READ_ADDR = 100,
parameter W_LOAD_ADDR = 0,
parameter A_LOAD_ADDR = 100,
parameter PSUM_ADDR = 500
)
(
input clk, reset,
input [DATA_WIDTH-1:0] act_in,
input [DATA_WIDTH-1:0] filt_in,
// input load_en,
input load_en_wght, load_en_act,
input start,
output logic [DATA_WIDTH-1:0] pe_out[0 : X_dim-1],
output logic compute_done,
output logic load_done
//extra
// output logic [DATA_WIDTH-1:0] psum_out[0 : X_dim*Y_dim-1]
);
logic [DATA_WIDTH-1:0] psum_out[0 : X_dim*Y_dim-1];
logic cluster_done[0 : X_dim*Y_dim-1];
logic cluster_load_done[0 : X_dim*Y_dim-1];
generate
genvar i;
for(i=0; i<X_dim; i++)
begin:gen_X
genvar j;
for(j=0; j<Y_dim; j++)
begin:gen_Y
PE #( .DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.kernel_size(kernel_size),
.act_size(act_size),
.W_READ_ADDR(W_READ_ADDR + kernel_size*j),
.A_READ_ADDR(A_READ_ADDR + act_size*j + i),
.W_LOAD_ADDR(W_LOAD_ADDR),
.A_LOAD_ADDR(A_LOAD_ADDR),
.PSUM_ADDR(PSUM_ADDR)
)
pe (
.clk(clk),
.reset(reset),
.act_in(act_in),
.filt_in(filt_in),
// .load_en(load_en),
.load_en_wght(load_en_wght),
.load_en_act(load_en_act),
.start(start),
.pe_out(psum_out[i*Y_dim+j]),
.compute_done(cluster_done[i*Y_dim+j]),
.load_done(cluster_load_done[i*Y_dim+j])
);
end
end
endgenerate
/* virtual class psum_adder_class #(parameter X_dim, parameter Y_dim, parameter DATA_WIDTH);
static function logic [DATA_WIDTH-1 : 0] psum_adder
(
input logic [DATA_WIDTH-1:0] psum_out[X_dim*Y_dim-1 : 0]
);
begin
psum_adder = {(DATA_WIDTH){1'b0}};
for(int i=0; i<Y_dim; i++) begin
psum_adder = psum_adder + psum_out[Y_dim*X_dim+i];
end
end
endfunction
endclass */
function logic [DATA_WIDTH-1 : 0] psum_adder
(
input logic [DATA_WIDTH-1:0] psum_out[0 : X_dim*Y_dim-1],
input logic [3:0] X_dim,
input logic [3:0] Y_dim
);
begin
psum_adder = {(DATA_WIDTH){1'b0}};
for(int i=0; i<Y_dim; i++) begin
psum_adder = psum_adder + psum_out[Y_dim*X_dim+i];
end
end
endfunction
/* always@(posedge clk) begin
if(reset) begin
for(int i=0; i<X_dim; i++) begin
pe_out[i] <= 0;
end
end else begin
for(int i=0; i<X_dim; i++) begin
pe_out[i] <= psum_adder_class#
(.X_dim(i),
.Y_dim(Y_dim),
.DATA_WIDTH(DATA_WIDTH)
)
::psum_adder(psum_out);
end
end
end */
// Add partial sums and register at pe_out
always@(posedge clk) begin
if(reset) begin
for(int i=0; i<X_dim; i++) begin
pe_out[i] <= 0;
end
end else begin
for(int i=0; i<X_dim; i++) begin
pe_out[i] <= psum_adder(psum_out,i,Y_dim);
end
end
end
assign compute_done = cluster_done[0];
assign load_done = cluster_load_done[0];
// assign pe_out[X_dim-1:0] = psum_out[X_dim*Y_dim-1 : 0]
endmodule
================================================
FILE: rtl/phase_1/SPad.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11/27/2019 10:35:28 AM
// Design Name:
// Module Name: SPad
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SPad #( parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 9 )
( input clk,
input reset,
input read_req,
input write_en,
input [ADDR_BITWIDTH-1 : 0] r_addr,
input [ADDR_BITWIDTH-1 : 0] w_addr,
input [DATA_BITWIDTH-1 : 0] w_data,
output logic [DATA_BITWIDTH-1 : 0] r_data
);
logic [DATA_BITWIDTH-1 : 0] mem [0 : (1 << ADDR_BITWIDTH) - 1];
// default - 512(2^9) 16-bit memory. Total size = 1kB
logic [DATA_BITWIDTH-1 : 0] data;
always@(posedge clk)
begin : READ
if(reset)
data <= 0;
else
begin
if(read_req) begin
data <= mem[r_addr];
// $display("Read Address to SPad:%d",r_addr);
end else begin
data <= 10101;
end
end
end
assign r_data = data;
always@(posedge clk)
begin : WRITE
$display("\t\t\t\t\t Current Status:\n \
\t mem[0]:%d", mem[0],
" | mem[1]:%d", mem[1],
" | mem[2]:%d", mem[2],
" | mem[3]:%d", mem[3],
" | mem[4]:%d", mem[4],
" | mem[5]:%d", mem[5],
" | mem[8]:%d", mem[8],
" | mem[24]:%d\n", mem[24],
" \t\t\t\t\t mem[100]:%d", mem[100],
" | mem[101]:%d", mem[101],
" | mem[102]:%d", mem[102],
" | mem[103]:%d", mem[103],
" | mem[104]:%d", mem[104],
" | mem[105]:%d\n", mem[105],
" | mem[124]:%d\n", mem[124],
" | mem[148]:%d\n", mem[148],
" \t\t\t\t\t psum:%d", mem[500],
" | psum:%d", mem[501],
" | psum:%d", mem[502],
" | psum:%d", mem[503],
" | psum:%d", mem[504]
);
if(write_en && !reset) begin
mem[w_addr] <= w_data;
end
end
endmodule
================================================
FILE: rtl/phase_1/glb_iact.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/01/2019 12:56:24 PM
// Design Name:
// Module Name: glb_iact
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module glb_iact #( parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 10 )
( input clk,
input reset,
input read_req,
input write_en,
input [ADDR_BITWIDTH-1 : 0] r_addr,
input [ADDR_BITWIDTH-1 : 0] w_addr,
input [DATA_BITWIDTH-1 : 0] w_data,
output logic [DATA_BITWIDTH-1 : 0] r_data
);
logic [DATA_BITWIDTH-1 : 0] mem [0 : (1 << ADDR_BITWIDTH) - 1];
// default - 1024(2^10) 16-bit memory. Total size = 2kB
logic [DATA_BITWIDTH-1 : 0] data;
always@(posedge clk)
begin : READ
if(reset)
data = 0;
else
begin
if(read_req) begin
data = mem[r_addr];
// $display("Read Address to SPad:%d",r_addr);
end else begin
data = 10101; //Random default value to verify model
end
end
end
assign r_data = data;
always@(posedge clk)
begin : WRITE
if(write_en && !reset) begin
mem[w_addr] = w_data;
end
end
endmodule
================================================
FILE: rtl/phase_1/glb_psum.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/01/2019 01:13:40 PM
// Design Name:
// Module Name: glb_psum
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module glb_psum #( parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 10 )
( input clk,
input reset,
input read_req,
input write_en,
input [ADDR_BITWIDTH-1 : 0] r_addr,
input [ADDR_BITWIDTH-1 : 0] w_addr,
input [DATA_BITWIDTH-1 : 0] w_data,
output logic [DATA_BITWIDTH-1 : 0] r_data
);
logic [DATA_BITWIDTH-1 : 0] mem [0 : (1 << ADDR_BITWIDTH) - 1];
// default - 1024(2^10) 16-bit memory. Total size = 2kB
logic [DATA_BITWIDTH-1 : 0] data;
always@(posedge clk)
begin : READ
if(reset)
data = 0;
else
begin
if(read_req) begin
data = mem[r_addr];
// $display("Read Address to SPad:%d",r_addr);
end else begin
data = 10101; //Random default value to verify model
end
end
end
assign r_data = data;
always@(posedge clk)
begin : WRITE
/* $display("\t\t\t\t\t Current Status in glb_psum:\n \
\t psum[0]:%d", mem[0],
" | psum[1]:%d", mem[1],
" | psum[2]:%d", mem[2],
" | psum[3]:%d", mem[3],
" | psum[4]:%d", mem[4],
" | psum[5]:%d", mem[5],
" | psum[6]:%d", mem[6],
" | psum[7]:%d", mem[7],
" | psum[8]:%d", mem[8],
" | psum[9]:%d", mem[9]
);
$display("WriteEn: %d\n",write_en);
$display("Write Data: %d\n",w_data);
$display("Write Addr: %d\n\n\n",w_addr); */
if(write_en && !reset) begin
mem[w_addr] = w_data;
end
end
endmodule
================================================
FILE: rtl/phase_1/glb_weight.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/01/2019 04:07:04 PM
// Design Name:
// Module Name: glb_weight
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module glb_weight #( parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 10 )
( input clk,
input reset,
input read_req,
input write_en,
input [ADDR_BITWIDTH-1 : 0] r_addr,
input [ADDR_BITWIDTH-1 : 0] w_addr,
input [DATA_BITWIDTH-1 : 0] w_data,
output logic [DATA_BITWIDTH-1 : 0] r_data
);
logic [DATA_BITWIDTH-1 : 0] mem [0 : (1 << ADDR_BITWIDTH) - 1];
// default - 1024(2^10) 16-bit memory. Total size = 2kB
logic [DATA_BITWIDTH-1 : 0] data;
always@(posedge clk)
begin : READ
if(reset)
data = 0;
else
begin
if(read_req) begin
data = mem[r_addr];
// $display("Read Address to SPad:%d",r_addr);
end else begin
data = 10101; //Random default value to verify model
end
end
end
assign r_data = data;
always@(posedge clk)
begin : WRITE
if(write_en && !reset) begin
mem[w_addr] = w_data;
end
end
endmodule
================================================
FILE: rtl/phase_1/router_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/03/2019 02:24:04 PM
// Design Name:
// Module Name: router_cluster
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module router_cluster#(
parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH_GLB = 10,
parameter ADDR_BITWIDTH_SPAD = 9,
parameter kernel_size = 3,
parameter act_size = 5,
parameter NUM_ROUTER_PSUM = 1,
parameter NUM_ROUTER_IACT = 1,
parameter NUM_ROUTER_WGHT = 1,
parameter A_READ_ADDR =100,
parameter A_LOAD_ADDR = 0,
parameter W_READ_ADDR = 0,
parameter W_LOAD_ADDR = 0,
parameter PSUM_READ_ADDR = 0,
parameter PSUM_LOAD_ADDR = 0
)
( input clk,
input reset,
//Signals for Activation Router
input [DATA_BITWIDTH-1 : 0] r_data_glb_iact,
input load_spad_ctrl_iact,
output logic [ADDR_BITWIDTH_GLB-1 : 0] r_addr_glb_iact,
output logic read_req_glb_iact,
output logic [DATA_BITWIDTH-1 : 0] w_data_spad_iact,
output logic load_en_spad_iact,
//Signals for Weight Router
input [DATA_BITWIDTH-1 : 0] r_data_glb_wght,
input load_spad_ctrl_wght,
output logic [ADDR_BITWIDTH_GLB-1 : 0] r_addr_glb_wght,
output logic read_req_glb_wght,
output logic [DATA_BITWIDTH-1 : 0] w_data_spad_wght,
output logic load_en_spad_wght,
//Signals for psum router
input [DATA_BITWIDTH-1 : 0] r_data_spad_psum[0:kernel_size-1],
input write_psum_ctrl, //connected to compute_done of pe_cluster
output logic [ADDR_BITWIDTH_GLB-1 : 0] w_addr_glb_psum,
output logic write_en_glb_psum,
output logic [DATA_BITWIDTH-1 : 0] w_data_glb_psum
);
//Instantiate iact router
generate
genvar i;
for(i=0; i<NUM_ROUTER_IACT; i++)
begin:router_iact_gen
router_iact #(.DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),
.kernel_size(kernel_size),
.act_size(act_size),
.A_READ_ADDR(A_READ_ADDR),
.A_LOAD_ADDR(A_LOAD_ADDR)
)
router_iact_0
( .clk(clk),
.reset(reset),
.r_data_glb_iact(r_data_glb_iact),
.r_addr_glb_iact(r_addr_glb_iact),
.read_req_glb_iact(read_req_glb_iact),
.w_data_spad(w_data_spad_iact),
.load_en_spad(load_en_spad_iact),
//Input from control unit to load weights to spad
.load_spad_ctrl(load_spad_ctrl_iact)
);
end
endgenerate
//Instantiate weight router
generate
genvar k;
for(k=0; k<NUM_ROUTER_WGHT; k++)
begin:router_weight_gen
router_weight #(.DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),
.kernel_size(kernel_size),
.act_size(act_size),
.W_READ_ADDR(W_READ_ADDR),
.W_LOAD_ADDR(W_LOAD_ADDR)
)
router_weight_0
( .clk(clk),
.reset(reset),
.r_data_glb_wght(r_data_glb_wght),
.r_addr_glb_wght(r_addr_glb_wght),
.read_req_glb_wght(read_req_glb_wght),
.w_data_spad(w_data_spad_wght),
.load_en_spad(load_en_spad_wght),
//Input from control unit to load weights to spad
.load_spad_ctrl(load_spad_ctrl_wght)
);
end
endgenerate
//Instantiate iact router
generate
genvar j;
for(j=0; j<NUM_ROUTER_PSUM; j++)
begin:router_psum_gen
router_psum #(.DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH_GLB(ADDR_BITWIDTH_GLB),
.ADDR_BITWIDTH_SPAD(ADDR_BITWIDTH_SPAD),
.kernel_size(kernel_size),
.act_size(act_size),
.PSUM_LOAD_ADDR(PSUM_LOAD_ADDR)
)
router_psum_0
( .clk(clk),
.reset(reset),
.r_data_spad_psum(r_data_spad_psum[0:kernel_size-1]),
.w_addr_glb_psum(w_addr_glb_psum),
.write_en_glb_psum(write_en_glb_psum),
.w_data_glb_psum(w_data_glb_psum),
//Input from control unit to load weights to spad
.write_psum_ctrl(write_psum_ctrl)
);
end
endgenerate
endmodule
================================================
FILE: rtl/phase_1/router_iact.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/02/2019 03:12:11 PM
// Design Name:
// Module Name: router_act
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module router_iact #( parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH_GLB = 10,
parameter ADDR_BITWIDTH_SPAD = 9,
parameter int X_dim = 5,
parameter int Y_dim = 3,
parameter int kernel_size = 3,
parameter int act_size = 5,
parameter A_READ_ADDR =100,
parameter A_LOAD_ADDR = 0
)
( input clk,
input reset,
//for reading glb
input [DATA_BITWIDTH-1 : 0] r_data_glb_iact,
output logic [ADDR_BITWIDTH_GLB-1 : 0] r_addr_glb_iact,
output logic read_req_glb_iact,
//for writing to spad
output logic [DATA_BITWIDTH-1 : 0] w_data_spad,
output logic load_en_spad,
//Input from control unit to load weights to spad
input load_spad_ctrl
);
enum logic [2:0] {IDLE=3'b000, READ_GLB=3'b001, WRITE_SPAD=3'b010, READ_GLB_0=3'b011} state;
logic [4:0] filt_count;
always@(posedge clk) begin
// $display("State: %s", state.name());
if(reset) begin
read_req_glb_iact <= 0;
r_addr_glb_iact <= 0;
load_en_spad <= 0;
filt_count <= 0;
state <= IDLE;
end else begin
case(state)
IDLE:begin
if(load_spad_ctrl) begin
read_req_glb_iact <= 1;
r_addr_glb_iact <= A_READ_ADDR;
state <= READ_GLB;
end else begin
read_req_glb_iact = 0;
load_en_spad = 0;
state <= IDLE;
end
end
READ_GLB:begin
filt_count <= filt_count + 1;
r_addr_glb_iact <= r_addr_glb_iact + 1;
w_data_spad <= r_data_glb_iact;
state <= WRITE_SPAD;
end
WRITE_SPAD:begin
load_en_spad <= 1;
if(filt_count == (act_size**2)) begin
w_data_spad <= r_data_glb_iact;
filt_count <= 0;
r_addr_glb_iact <= A_READ_ADDR;
state <= IDLE;
end else begin
w_data_spad <= r_data_glb_iact;
filt_count <= filt_count + 1;
r_addr_glb_iact <= r_addr_glb_iact + 1;
state <= WRITE_SPAD;
end
end
endcase
end
end
endmodule
================================================
FILE: rtl/phase_1/router_psum.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/03/2019 11:22:43 AM
// Design Name:
// Module Name: router_psum
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module router_psum #( parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH_GLB = 10,
parameter ADDR_BITWIDTH_SPAD = 9,
parameter int X_dim = 5,
parameter int Y_dim = 3,
parameter int kernel_size = 3,
parameter int act_size = 5,
// parameter A_READ_ADDR =100,
// parameter A_LOAD_ADDR = 0,
parameter PSUM_READ_ADDR = 0,
parameter PSUM_LOAD_ADDR = 0
)
( input clk,
input reset,
//for reading glb
input [DATA_BITWIDTH-1 : 0] r_data_spad_psum[0:kernel_size-1],
output logic [ADDR_BITWIDTH_GLB-1 : 0] w_addr_glb_psum,
output logic write_en_glb_psum,
//for writing to spad
output logic [DATA_BITWIDTH-1 : 0] w_data_glb_psum,
// output logic load_en_spad,
//Input from PE cluster to write psums to glb
input write_psum_ctrl
);
enum logic [2:0] {IDLE=3'b000, WRITE_GLB=3'b001, READ_PSUM=3'b010} state;
logic [4:0] psum_count;
logic [DATA_BITWIDTH-1 : 0] pe_psum[0:kernel_size-1];
logic [2:0] iter;
always@(posedge clk) begin
// $display("State of router_psum: %s", state.name());
if(reset) begin
w_addr_glb_psum <= PSUM_LOAD_ADDR;
psum_count <= 0;
write_en_glb_psum <= 0;
iter <= 0;
state <= IDLE;
end else begin
case(state)
IDLE:begin
if(write_psum_ctrl) begin
//write_en_glb_psum <= 1;
state <= READ_PSUM;
end else begin
psum_count <= 0;
write_en_glb_psum <= 0;
w_addr_glb_psum <= PSUM_LOAD_ADDR;
state <= IDLE;
end
end
READ_PSUM:begin
pe_psum <= r_data_spad_psum;
// $display("Psum read in router:%d",pe_psum[0:kernel_size-1]);
psum_count <= 0;
state <= WRITE_GLB;
end
WRITE_GLB:begin
write_en_glb_psum <= 1;
// $display("Psum written to address %d; Iter is %d",w_addr_glb_psum, iter);
if(psum_count == (kernel_size-1)) begin
w_data_glb_psum <= pe_psum[psum_count];
psum_count <= 0;
w_addr_glb_psum <= w_addr_glb_psum + 1;
iter <= iter + 1;
state <= IDLE;
end else begin
w_data_glb_psum <= pe_psum[psum_count];
psum_count <= psum_count + 1;
if(psum_count == (kernel_size-1)) begin
state <= IDLE;
end else if(psum_count == 0) begin
w_addr_glb_psum <= PSUM_LOAD_ADDR+iter*kernel_size;
state <= WRITE_GLB;
end else begin
w_addr_glb_psum <= w_addr_glb_psum + 1;
state <= WRITE_GLB;
end
end
end
endcase
end
end
endmodule
================================================
FILE: rtl/phase_1/router_weight.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/01/2019 03:50:08 PM
// Design Name:
// Module Name: router_weight
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module router_weight #( parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH_GLB = 10,
parameter ADDR_BITWIDTH_SPAD = 9,
parameter int X_dim = 5,
parameter int Y_dim = 3,
parameter int kernel_size = 3,
parameter int act_size = 5,
parameter W_READ_ADDR = 0,
parameter W_LOAD_ADDR = 0
)
( input clk,
input reset,
//for reading glb
input [DATA_BITWIDTH-1 : 0] r_data_glb_wght,
output logic [ADDR_BITWIDTH_GLB-1 : 0] r_addr_glb_wght,
output logic read_req_glb_wght,
//for writing to spad
output logic [DATA_BITWIDTH-1 : 0] w_data_spad,
output logic load_en_spad,
//Input from control unit to load weights to spad
input load_spad_ctrl
);
enum logic [2:0] {IDLE=3'b000, READ_GLB=3'b001, WRITE_SPAD=3'b010, READ_GLB_0=3'b011} state;
logic [4:0] filt_count;
always@(posedge clk) begin
// $display("State: %s", state.name());
if(reset) begin
read_req_glb_wght <= 0;
r_addr_glb_wght <= 0;
load_en_spad <= 0;
filt_count <= 0;
state <= IDLE;
end else begin
case(state)
IDLE:begin
if(load_spad_ctrl) begin
read_req_glb_wght <= 1;
r_addr_glb_wght <= W_READ_ADDR;
state <= READ_GLB;
end else begin
read_req_glb_wght = 0;
load_en_spad <= 0;
state <= IDLE;
end
end
READ_GLB:begin
filt_count <= filt_count + 1;
r_addr_glb_wght <= r_addr_glb_wght + 1;
w_data_spad <= r_data_glb_wght;
state <= WRITE_SPAD;
end
WRITE_SPAD:begin
load_en_spad <= 1;
if(filt_count == (kernel_size**2)) begin
w_data_spad <= r_data_glb_wght;
filt_count <= 0;
r_addr_glb_wght <= W_READ_ADDR;
state <= IDLE;
end else begin
w_data_spad <= r_data_glb_wght;
filt_count <= filt_count + 1;
r_addr_glb_wght <= r_addr_glb_wght + 1;
state <= WRITE_SPAD;
end
end
endcase
end
end
endmodule
================================================
FILE: rtl/phase_2/HMNoC_cluster_east.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/10/2019 02:47:05 PM
// Design Name:
// Module Name: HMNoC_cluster_east
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HMNoC_cluster_east
#(
parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 10,
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 9,
// GLB Cluster parameters. This TestBench uses only 1 of each
parameter NUM_GLB_IACT = 1,
parameter NUM_GLB_PSUM = 1,
parameter NUM_GLB_WGHT = 1,
parameter ADDR_BITWIDTH_GLB = 10,
parameter ADDR_BITWIDTH_SPAD = 9,
parameter NUM_ROUTER_PSUM = 1,
parameter NUM_ROUTER_IACT = 1,
parameter NUM_ROUTER_WGHT = 1,
parameter int kernel_size = 3,
parameter int act_size = 5,
parameter int X_dim = 3,
parameter int Y_dim = 3,
parameter W_READ_ADDR = 0,
parameter A_READ_ADDR = 0,
parameter W_LOAD_ADDR = 0,
parameter A_LOAD_ADDR = 0,
parameter PSUM_READ_ADDR = 0,
parameter PSUM_LOAD_ADDR = 0
)
(
input clk,
input reset,
//PE Cluster Interface
input start,
output load_done,
input load_en_wght,
input load_en_act,
output [DATA_WIDTH-1:0] pe_out[X_dim-1:0],
output compute_done,
//GLB Cluster Interface
input write_en_iact,
input write_en_wght,
input [DATA_WIDTH-1:0] w_data_iact,
input [ADDR_WIDTH-1:0] w_addr_iact,
input [DATA_WIDTH-1:0] w_data_wght,
input [ADDR_WIDTH-1:0] w_addr_wght,
input [ADDR_WIDTH-1:0] w_addr_psum,
output [DATA_WIDTH-1:0] r_data_psum,
input [ADDR_WIDTH-1:0] r_addr_psum,
input read_req_iact,
input read_req_psum,
input read_req_wght,
input [ADDR_WIDTH-1:0] r_addr_iact,
input [ADDR_WIDTH-1:0] r_addr_wght,
//WGHT Router Ports
input [3:0] router_mode_wght,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i_wght,
input north_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o_wght,
output logic north_enable_o_wght,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i_wght,
input south_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o_wght,
output logic south_enable_o_wght,
//Interface with West
//Source ports
input [DATA_WIDTH-1:0] west_data_i_wght,
input west_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] west_data_o_wght,
output logic west_enable_o_wght,
//Interface with East - Devices
//Source ports
// input [DATA_WIDTH-1:0] east_data_i_wght,
input east_enable_i_wght,
//Destination ports
// output logic [DATA_WIDTH-1:0] east_data_o_wght,
output logic east_enable_o_wght,
//IACT Router Ports
input [3:0] router_mode_iact,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i_iact,
input north_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o_iact,
output logic north_enable_o_iact,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i_iact,
input south_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o_iact,
output logic south_enable_o_iact,
//Interface with West
//Source ports
input [DATA_WIDTH-1:0] west_data_i_iact,
input west_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] west_data_o_iact,
output logic west_enable_o_iact,
//Interface with East - Devices
//Source ports
// input [DATA_WIDTH-1:0] east_data_i_iact,
input east_enable_i_iact,
//Destination ports
// output logic [DATA_WIDTH-1:0] east_data_o_iact,
output logic east_enable_o_iact,
//PSUM Router Ports
input [3:0] router_mode_psum,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i_psum,
input north_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o_psum,
output logic north_enable_o_psum,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i_psum,
input south_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o_psum,
output logic south_enable_o_psum,
//Interface with West
//Source ports
input [DATA_WIDTH-1:0] west_data_i_psum,
input west_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] west_data_o_psum,
output logic west_enable_o_psum,
//Interface with East - Devices
//Source ports
input [DATA_WIDTH-1:0] east_data_i_psum,
input east_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] east_data_o_psum,
output logic east_enable_o_psum
);
//Logic for Direction
enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
//GLB cluster initialization
GLB_cluster
#( .DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH(ADDR_BITWIDTH),
.NUM_GLB_IACT(NUM_GLB_IACT),
.NUM_GLB_PSUM(NUM_GLB_PSUM),
.NUM_GLB_WGHT(NUM_GLB_WGHT)
)
GLB_cluster_0
(
.clk(clk), //TestBench/Controller
.reset(reset), //TestBench/Controller
//Signals for reading from GLB
.read_req_iact(read_req_iact),
.read_req_psum(read_req_psum), //Read by testbench/controller
.read_req_wght(read_req_wght),
.r_data_iact(router_cluster_0.east_data_i_iact),
.r_data_psum(r_data_psum), //Read by testbench/controller
.r_data_wght(router_cluster_0.east_data_i_wght),
.r_addr_iact(r_addr_iact),
.r_addr_psum(r_addr_psum), //testbench for reading final psums
.r_addr_wght(r_addr_wght),
//Signals for writing to GLB
.w_addr_iact(w_addr_iact), //testbench for writing
.w_addr_psum(w_addr_psum),
.w_addr_wght(w_addr_wght), //testbench for writing
.w_data_iact(w_data_iact), //testbench for writing
.w_data_psum(router_cluster_0.east_data_o_psum),
.w_data_wght(w_data_wght), //testbench for writing
.write_en_iact(write_en_iact), //testbench for writing
.write_en_psum(router_cluster_0.east_enable_o_psum),
.write_en_wght(write_en_wght) //testbench for writing
);
router_cluster
#(
.DATA_WIDTH(DATA_WIDTH)
)
router_cluster_0
(
//Ports for WGHT router
.router_mode_wght(router_mode_wght), //TB*
//Interface with North
//Source ports
.north_data_i_wght(north_data_i_wght),
.north_enable_i_wght(north_enable_i_wght),
//Destination ports
.north_data_o_wght(north_data_o_wght),
.north_enable_o_wght(north_enable_o_wght),
//Interface with South
//Source ports
.south_data_i_wght(south_data_i_wght),
.south_enable_i_wght(south_enable_i_wght),
//Destination ports
.south_data_o_wght(south_data_o_wght),
.south_enable_o_wght(south_enable_o_wght),
//Interface with West
//Source ports
.west_data_i_wght(west_data_i_wght), //GLB_cluster
.west_enable_i_wght(west_enable_i_wght),
//Destination ports
.west_data_o_wght(pwest_data_o_wght), //PE_cluster
.west_enable_o_wght(west_enable_o_wght),
//Interface with East - Devices
//Source ports
.east_data_i_wght(GLB_cluster_0.r_data_wght),
.east_enable_i_wght(east_enable_i_wght),
//Destination ports
.east_data_o_wght(east_data_o_wght),
.east_enable_o_wght(east_enable_o_wght),
////////////////////////////////////////////
//Ports for IACT router
.router_mode_iact(router_mode_iact), //TB*
//Interface with North
//Source ports
.north_data_i_iact(north_data_i_iact),
.north_enable_i_iact(north_enable_i_iact),
//Destination ports
.north_data_o_iact(north_data_o_iact),
.north_enable_o_iact(north_enable_o_iact),
//Interface with South
//Source ports
.south_data_i_iact(south_data_i_iact),
.south_enable_i_iact(south_enable_i_iact),
//Destination ports
.south_data_o_iact(south_data_o_iact),
.south_enable_o_iact(south_enable_o_iact),
//Interface with West
//Source ports
.west_data_i_iact(west_data_i_iact), //GLB_cluster
.west_enable_i_iact(west_enable_i_iact),
//Destination ports
.west_data_o_iact(west_data_o_iact), //PE_cluster
.west_enable_o_iact(west_enable_o_iact),
//Interface with East - Devices
//Source ports
.east_data_i_iact(GLB_cluster_0.r_data_iact),
.east_enable_i_iact(east_enable_i_iact),
//Destination ports
.east_data_o_iact(pe_cluster_0.act_in),
.east_enable_o_iact(east_enable_o_iact),
////////////////////////////////////////////
//Ports for PSUM router
.router_mode_psum(router_mode_psum),
//Interface with North
//Source ports
.north_data_i_psum(north_data_i_psum),
.north_enable_i_psum(north_enable_i_psum),
//Destination ports
.north_data_o_psum(north_data_o_psum),
.north_enable_o_psum(north_enable_o_psum),
//Interface with South
//Source ports
.south_data_i_psum(south_data_i_psum),
.south_enable_i_psum(south_enable_i_psum),
//Destination ports
.south_data_o_psum(south_data_o_psum),
.south_enable_o_psum(south_enable_o_psum),
//Interface with West
//Source ports
.west_data_i_psum(west_data_i_psum), //PE_cluster
.west_enable_i_psum(west_enable_i_psum),
//Destination ports
.west_data_o_psum(west_data_o_psum), //GLB_cluster
.west_enable_o_psum(west_enable_o_psum), //GLB_cluster
//Interface with East - Devices
//Source ports
.east_data_i_psum(east_data_i_psum),
.east_enable_i_psum(east_enable_i_psum),
//Destination ports
.east_data_o_psum(GLB_cluster_0.w_data_psum),
.east_enable_o_psum(GLB_cluster_0.write_en_psum)
);
PE_cluster #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.kernel_size(kernel_size),
.act_size(act_size),
.X_dim(X_dim),
.Y_dim(Y_dim)
)
pe_cluster_0
(
.clk(clk),
.reset(reset),
.act_in(router_cluster_0.east_data_o_iact),
.filt_in(router_cluster_0.east_data_o_wght),
.load_en_wght(load_en_wght),
.load_en_act(load_en_act),
.start(start),
.pe_out(pe_out),
.compute_done(compute_done),
.load_done(load_done)
);
endmodule
================================================
FILE: rtl/phase_2/HMNoC_cluster_west.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/10/2019 11:42:17 AM
// Design Name:
// Module Name: HMNoC_cluster_new
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HMNoC_cluster_west
#(
parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 10,
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 9,
// GLB Cluster parameters. This TestBench uses only 1 of each
parameter NUM_GLB_IACT = 1,
parameter NUM_GLB_PSUM = 1,
parameter NUM_GLB_WGHT = 1,
parameter ADDR_BITWIDTH_GLB = 10,
parameter ADDR_BITWIDTH_SPAD = 9,
parameter NUM_ROUTER_PSUM = 1,
parameter NUM_ROUTER_IACT = 1,
parameter NUM_ROUTER_WGHT = 1,
parameter int kernel_size = 3,
parameter int act_size = 5,
parameter int X_dim = 3,
parameter int Y_dim = 3,
parameter W_READ_ADDR = 0,
parameter A_READ_ADDR = 0,
parameter W_LOAD_ADDR = 0,
parameter A_LOAD_ADDR = 0,
parameter PSUM_READ_ADDR = 0,
parameter PSUM_LOAD_ADDR = 0
)
(
input clk,
input reset,
//PE Cluster Interface
input start,
output load_done,
input load_en_wght,
input load_en_act,
output [DATA_WIDTH-1:0] pe_out[X_dim-1:0],
output compute_done,
//GLB Cluster Interface
input write_en_iact,
input write_en_wght,
input [DATA_WIDTH-1:0] w_data_iact,
input [ADDR_WIDTH-1:0] w_addr_iact,
input [DATA_WIDTH-1:0] w_data_wght,
input [ADDR_WIDTH-1:0] w_addr_wght,
input [ADDR_WIDTH-1:0] w_addr_psum,
output [DATA_WIDTH-1:0] r_data_psum,
input [ADDR_WIDTH-1:0] r_addr_psum,
input read_req_iact,
input read_req_psum,
input read_req_wght,
input [ADDR_WIDTH-1:0] r_addr_iact,
input [ADDR_WIDTH-1:0] r_addr_wght,
//WGHT Router Ports
input [3:0] router_mode_wght,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i_wght,
input north_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o_wght,
output logic north_enable_o_wght,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i_wght,
input south_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o_wght,
output logic south_enable_o_wght,
//Interface with West
//Source ports
// input [DATA_WIDTH-1:0] west_data_i_wght,
input west_enable_i_wght,
//Destination ports
// output logic [DATA_WIDTH-1:0] west_data_o_wght,
output logic west_enable_o_wght,
//Interface with East - Devices
//Source ports
input [DATA_WIDTH-1:0] east_data_i_wght,
input east_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] east_data_o_wght,
output logic east_enable_o_wght,
//IACT Router Ports
input [3:0] router_mode_iact,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i_iact,
input north_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o_iact,
output logic north_enable_o_iact,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i_iact,
input south_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o_iact,
output logic south_enable_o_iact,
//Interface with West
//Source ports
// input [DATA_WIDTH-1:0] west_data_i_iact,
input west_enable_i_iact,
//Destination ports
// output logic [DATA_WIDTH-1:0] west_data_o_iact,
output logic west_enable_o_iact,
//Interface with East - Devices
//Source ports
input [DATA_WIDTH-1:0] east_data_i_iact,
input east_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] east_data_o_iact,
output logic east_enable_o_iact,
//PSUM Router Ports
input [3:0] router_mode_psum,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i_psum,
input north_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o_psum,
output logic north_enable_o_psum,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i_psum,
input south_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o_psum,
output logic south_enable_o_psum,
//Interface with West
//Source ports
input [DATA_WIDTH-1:0] west_data_i_psum,
input west_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] west_data_o_psum,
output logic west_enable_o_psum,
//Interface with East - Devices
//Source ports
input [DATA_WIDTH-1:0] east_data_i_psum,
input east_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] east_data_o_psum,
output logic east_enable_o_psum
);
//Logic for Direction
enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
//GLB cluster initialization
GLB_cluster
#( .DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH(ADDR_BITWIDTH),
.NUM_GLB_IACT(NUM_GLB_IACT),
.NUM_GLB_PSUM(NUM_GLB_PSUM),
.NUM_GLB_WGHT(NUM_GLB_WGHT)
)
GLB_cluster_0
(
.clk(clk), //TestBench/Controller
.reset(reset), //TestBench/Controller
//Signals for reading from GLB
.read_req_iact(read_req_iact),
.read_req_psum(read_req_psum), //Read by testbench/controller
.read_req_wght(read_req_wght),
.r_data_iact(router_cluster_0.west_data_i_iact),
.r_data_psum(r_data_psum), //Read by testbench/controller
.r_data_wght(router_cluster_0.west_data_i_wght),
.r_addr_iact(r_addr_iact),
.r_addr_psum(r_addr_psum), //testbench for reading final psums
.r_addr_wght(r_addr_wght),
//Signals for writing to GLB
.w_addr_iact(w_addr_iact), //testbench for writing
.w_addr_psum(w_addr_psum),
.w_addr_wght(w_addr_wght), //testbench for writing
.w_data_iact(w_data_iact), //testbench for writing
.w_data_psum(router_cluster_0.west_data_o_psum),
.w_data_wght(w_data_wght), //testbench for writing
.write_en_iact(write_en_iact), //testbench for writing
.write_en_psum(router_cluster_0.west_enable_o_psum),
.write_en_wght(write_en_wght) //testbench for writing
);
router_cluster
#(
.DATA_WIDTH(DATA_WIDTH)
)
router_cluster_0
(
//Ports for WGHT router
.router_mode_wght(router_mode_wght), //TB*
//Interface with North
//Source ports
.north_data_i_wght(north_data_i_wght),
.north_enable_i_wght(north_enable_i_wght),
//Destination ports
.north_data_o_wght(north_data_o_wght),
.north_enable_o_wght(north_enable_o_wght),
//Interface with South
//Source ports
.south_data_i_wght(south_data_i_wght),
.south_enable_i_wght(south_enable_i_wght),
//Destination ports
.south_data_o_wght(south_data_o_wght),
.south_enable_o_wght(south_enable_o_wght),
//Interface with West
//Source ports
.west_data_i_wght(GLB_cluster_0.r_data_wght), //GLB_cluster
.west_enable_i_wght(west_enable_i_wght),
//Destination ports
.west_data_o_wght(pe_cluster_0.filt_in), //PE_cluster
.west_enable_o_wght(west_enable_o_wght),
//Interface with East - Devices
//Source ports
.east_data_i_wght(east_data_i_wght),
.east_enable_i_wght(east_enable_i_wght),
//Destination ports
.east_data_o_wght(east_data_o_wght),
.east_enable_o_wght(east_enable_o_wght),
////////////////////////////////////////////
//Ports for IACT router
.router_mode_iact(router_mode_iact), //TB*
//Interface with North
//Source ports
.north_data_i_iact(north_data_i_iact),
.north_enable_i_iact(north_enable_i_iact),
//Destination ports
.north_data_o_iact(north_data_o_iact),
.north_enable_o_iact(north_enable_o_iact),
//Interface with South
//Source ports
.south_data_i_iact(south_data_i_iact),
.south_enable_i_iact(south_enable_i_iact),
//Destination ports
.south_data_o_iact(south_data_o_iact),
.south_enable_o_iact(south_enable_o_iact),
//Interface with West
//Source ports
.west_data_i_iact(GLB_cluster_0.r_data_iact), //GLB_cluster
.west_enable_i_iact(west_enable_i_iact),
//Destination ports
.west_data_o_iact(pe_cluster_0.act_in), //PE_cluster
.west_enable_o_iact(west_enable_o_iact),
//Interface with East - Devices
//Source ports
.east_data_i_iact(east_data_i_iact),
.east_enable_i_iact(east_enable_i_iact),
//Destination ports
.east_data_o_iact(east_data_o_iact),
.east_enable_o_iact(east_enable_o_iact),
////////////////////////////////////////////
//Ports for PSUM router
.router_mode_psum(router_mode_psum),
//Interface with North
//Source ports
.north_data_i_psum(north_data_i_psum),
.north_enable_i_psum(north_enable_i_psum),
//Destination ports
.north_data_o_psum(north_data_o_psum),
.north_enable_o_psum(north_enable_o_psum),
//Interface with South
//Source ports
.south_data_i_psum(south_data_i_psum),
.south_enable_i_psum(south_enable_i_psum),
//Destination ports
.south_data_o_psum(south_data_o_psum),
.south_enable_o_psum(south_enable_o_psum),
//Interface with West
//Source ports
.west_data_i_psum(west_data_i_psum), //PE_cluster
.west_enable_i_psum(west_enable_i_psum),
//Destination ports
.west_data_o_psum(GLB_cluster_0.w_data_psum), //GLB_cluster
.west_enable_o_psum(GLB_cluster_0.write_en_psum), //GLB_cluster
//Interface with East - Devices
//Source ports
.east_data_i_psum(east_data_i_psum),
.east_enable_i_psum(east_enable_i_psum),
//Destination ports
.east_data_o_psum(east_data_o_psum),
.east_enable_o_psum(east_enable_o_psum)
);
PE_cluster #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.kernel_size(kernel_size),
.act_size(act_size),
.X_dim(X_dim),
.Y_dim(Y_dim)
)
pe_cluster_0
(
.clk(clk),
.reset(reset),
.act_in(router_cluster_0.west_data_o_iact),
.filt_in(router_cluster_0.west_data_o_wght),
.load_en_wght(load_en_wght),
.load_en_act(load_en_act),
.start(start),
.pe_out(pe_out),
.compute_done(compute_done),
.load_done(load_done)
);
endmodule
================================================
FILE: rtl/phase_2/HMNoC_top.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/10/2019 03:22:12 PM
// Design Name:
// Module Name: HMNoC_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HMNoC_top
#(
parameter DATA_BITWIDTH = 16,
parameter ADDR_BITWIDTH = 10,
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 9,
// GLB Cluster parameters. This TestBench uses only 1 of each
parameter NUM_GLB_IACT = 1,
parameter NUM_GLB_PSUM = 1,
parameter NUM_GLB_WGHT = 1,
parameter ADDR_BITWIDTH_GLB = 10,
parameter ADDR_BITWIDTH_SPAD = 9,
parameter NUM_ROUTER_PSUM = 1,
parameter NUM_ROUTER_IACT = 1,
parameter NUM_ROUTER_WGHT = 1,
parameter int kernel_size = 3,
parameter int act_size = 5,
parameter int X_dim = 3,
parameter int Y_dim = 3,
parameter W_READ_ADDR = 0,
parameter A_READ_ADDR = 0,
parameter W_LOAD_ADDR = 0,
parameter A_LOAD_ADDR = 0,
parameter PSUM_READ_ADDR = 0,
parameter PSUM_LOAD_ADDR = 0
)
(
input clk,
input reset,
//PE Cluster Interface
input start,
output load_done,
input load_en_wght,
input load_en_act,
output [DATA_WIDTH-1:0] pe_out[X_dim-1:0],
output compute_done,
//GLB Cluster Interface
input write_en_iact,
input write_en_wght,
input [DATA_WIDTH-1:0] w_data_iact,
input [ADDR_WIDTH-1:0] w_addr_iact,
input [DATA_WIDTH-1:0] w_data_wght,
input [ADDR_WIDTH-1:0] w_addr_wght,
input [ADDR_WIDTH-1:0] w_addr_psum,
output [DATA_WIDTH-1:0] r_data_psum,
input [ADDR_WIDTH-1:0] r_addr_psum,
input read_req_iact,
input read_req_psum,
input read_req_wght,
input [ADDR_WIDTH-1:0] r_addr_iact,
input [ADDR_WIDTH-1:0] r_addr_wght,
//WGHT Router Ports
input [3:0] router_mode_wght,
input [3:0] router_mode_iact,
input [3:0] router_mode_psum
);
//Instantiation of NORTH WEST Cluster
HMNoC_cluster_west
#(
.DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH(ADDR_BITWIDTH),
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.NUM_GLB_IACT(NUM_GLB_IACT),
.NUM_GLB_PSUM(NUM_GLB_PSUM),
.NUM_GLB_WGHT(NUM_GLB_WGHT),
.kernel_size(kernel_size),
.act_size(act_size),
.X_dim(X_dim),
.Y_dim(Y_dim)
)
HMNoC_cluster_west_0 ///NORTH WEST Cluster
(
.clk(clk), //TestBench/Controller
.reset(reset), //TestBench/Controller
//Signals for reading from GLB
.read_req_iact(read_req_iact),
.read_req_psum(read_req_psum), //Read by testbench/controller
.read_req_wght(read_req_wght),
// .r_data_iact(router_cluster_0.r_data_glb_iact),
.r_data_psum(r_data_psum), //Read by testbench/controller
// .r_data_wght(router_cluster_0.r_data_glb_wght),
.r_addr_iact(r_addr_iact),
.r_addr_psum(r_addr_psum), //testbench for reading final psums
.r_addr_wght(r_addr_wght),
//Signals for writing to GLB
.w_addr_iact(w_addr_iact), //testbench for writing
.w_addr_psum(w_addr_psum),
.w_addr_wght(w_addr_wght), //testbench for writing
.w_data_iact(w_data_iact), //testbench for writing
// .w_data_psum(router_cluster_0.w_data_glb_psum),
.w_data_wght(w_data_wght), //testbench for writing
.write_en_iact(write_en_iact), //testbench for writing
// .write_en_psum(router_cluster_0.write_en_glb_psum),
.write_en_wght(write_en_wght), //testbench for writing
//Ports for WGHT router
.router_mode_wght(router_mode_wght), //TB*
//Interface with North
//Source ports
.north_data_i_wght(),
.north_enable_i_wght(),
//Destination ports
.north_data_o_wght(),
.north_enable_o_wght(),
//Interface with South
//Source ports
.south_data_i_wght(HMNoC_cluster_west_1.north_data_o_wght),
.south_enable_i_wght(HMNoC_cluster_west_1.north_enable_o_wght),
//Destination ports
.south_data_o_wght(HMNoC_cluster_west_1.north_data_i_wght),
.south_enable_o_wght(HMNoC_cluster_west_1.north_enable_i_wght),
//Interface with West
//Source ports
// .west_data_i_wght(GLB_cluster_0.r_data_wght), //GLB_cluster
.west_enable_i_wght(west_enable_i_wght),
//Destination ports
// .west_data_o_wght(pe_cluster_0.filt_in), //PE_cluster
.west_enable_o_wght(west_enable_o_wght),
//Interface with East - Devices
//Source ports
.east_data_i_wght(HMNoC_cluster_east_0.west_data_o_wght),
.east_enable_i_wght(HMNoC_cluster_east_0.west_enable_o_wght),
//Destination ports
.east_data_o_wght(HMNoC_cluster_east_0.west_data_i_wght),
.east_enable_o_wght(HMNoC_cluster_east_0.west_enable_i_wght),
////////////////////////////////////////////
//Ports for IACT router
.router_mode_iact(router_mode_iact), //TB*
//Interface with North
//Source ports
.north_data_i_iact(),
.north_enable_i_iact(),
//Destination ports
.north_data_o_iact(),
.north_enable_o_iact(),
//Interface with South
//Source ports
.south_data_i_iact(HMNoC_cluster_west_1.north_data_o_iact),
.south_enable_i_iact(HMNoC_cluster_west_1.north_enable_o_iact),
//Destination ports
.south_data_o_iact(HMNoC_cluster_west_1.north_data_i_iact),
.south_enable_o_iact(HMNoC_cluster_west_1.north_enable_i_iact),
//Interface with West
//Source ports
// .west_data_i_iact(GLB_cluster_0.r_data_iact), //GLB_cluster
.west_enable_i_iact(west_enable_i_iact),
//Destination ports
// .west_data_o_iact(pe_cluster_0.act_in), //PE_cluster
.west_enable_o_iact(west_enable_o_iact),
//Interface with East - Devices
//Source ports
.east_data_i_iact(HMNoC_cluster_east_0.west_data_o_iact),
.east_enable_i_iact(HMNoC_cluster_east_0.west_enable_o_iact),
//Destination ports
.east_data_o_iact(HMNoC_cluster_east_0.west_data_i_iact),
.east_enable_o_iact(HMNoC_cluster_east_0.west_enable_i_iact),
////////////////////////////////////////////
//Ports for PSUM router
.router_mode_psum(router_mode_psum),
//Interface with North
//Source ports
.north_data_i_psum(),
.north_enable_i_psum(),
//Destination ports
.north_data_o_psum(),
.north_enable_o_psum(),
//Interface with South
//Source ports
.south_data_i_psum(HMNoC_cluster_west_1.north_data_o_psum),
.south_enable_i_psum(HMNoC_cluster_west_1.north_enable_o_psum),
//Destination ports
.south_data_o_psum(HMNoC_cluster_west_1.north_data_i_psum),
.south_enable_o_psum(HMNoC_cluster_west_1.north_enable_i_psum),
//Interface with West
//Source ports
.west_data_i_psum(west_data_i_psum), //PE_cluster
.west_enable_i_psum(west_enable_i_psum),
//Destination ports
// .west_data_o_psum(GLB_cluster_0.w_data_psum), //GLB_cluster
// .west_enable_o_psum(GLB_cluster_0.write_en_psum), //GLB_cluster
//Interface with East - Devices
//Source ports
.east_data_i_psum(HMNoC_cluster_east_0.west_data_o_psum),
.east_enable_i_psum(HMNoC_cluster_east_0.west_enable_o_psum),
//Destination ports
.east_data_o_psum(HMNoC_cluster_east_0.west_data_i_psum),
.east_enable_o_psum(HMNoC_cluster_east_0.west_enable_i_psum),
//PE Cluster
.load_en_wght(load_en_wght),
.load_en_act(load_en_act),
.start(start),
.pe_out(pe_out),
.compute_done(compute_done),
.load_done(load_done)
);
//Instantiation of SOUTH WEST Cluster
HMNoC_cluster_west
#(
.DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH(ADDR_BITWIDTH),
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.NUM_GLB_IACT(NUM_GLB_IACT),
.NUM_GLB_PSUM(NUM_GLB_PSUM),
.NUM_GLB_WGHT(NUM_GLB_WGHT),
.kernel_size(kernel_size),
.act_size(act_size),
.X_dim(X_dim),
.Y_dim(Y_dim)
)
HMNoC_cluster_west_1 ///SOUTH WEST Cluster
(
.clk(clk), //TestBench/Controller
.reset(reset), //TestBench/Controller
//Signals for reading from GLB
.read_req_iact(),
.read_req_psum(), //Read by testbench/controller
.read_req_wght(),
// .r_data_iact(router_cluster_0.r_data_glb_iact),
.r_data_psum(), //Read by testbench/controller
// .r_data_wght(router_cluster_0.r_data_glb_wght),
.r_addr_iact(),
.r_addr_psum(), //testbench for reading final psums
.r_addr_wght(),
//Signals for writing to GLB
.w_addr_iact(), //testbench for writing
.w_addr_psum(),
.w_addr_wght(), //testbench for writing
.w_data_iact(), //testbench for writing
// .w_data_psum(router_cluster_0.w_data_glb_psum),
.w_data_wght(), //testbench for writing
.write_en_iact(), //testbench for writing
// .write_en_psum(router_cluster_0.write_en_glb_psum),
.write_en_wght(), //testbench for writing
//Ports for WGHT router
.router_mode_wght(), //TB*
//Interface with North
//Source ports
.north_data_i_wght(HMNoC_cluster_west_0.south_data_o_wght),
.north_enable_i_wght(HMNoC_cluster_west_0.south_enable_o_wght),
//Destination ports
.north_data_o_wght(HMNoC_cluster_west_0.south_data_i_wght),
.north_enable_o_wght(HMNoC_cluster_west_0.south_enable_i_wght),
//Interface with South
//Source ports
.south_data_i_wght(),
.south_enable_i_wght(),
//Destination ports
.south_data_o_wght(),
.south_enable_o_wght(),
//Interface with West
//Source ports
// .west_data_i_wght(GLB_cluster_0.r_data_wght), //GLB_cluster
.west_enable_i_wght(),
//Destination ports
// .west_data_o_wght(pe_cluster_0.filt_in), //PE_cluster
.west_enable_o_wght(),
//Interface with East - Devices
//Source ports
.east_data_i_wght(HMNoC_cluster_east_1.west_data_o_wght),
.east_enable_i_wght(HMNoC_cluster_east_1.west_enable_o_wght),
//Destination ports
.east_data_o_wght(HMNoC_cluster_east_1.west_data_i_wght),
.east_enable_o_wght(HMNoC_cluster_east_1.west_enable_i_wght),
////////////////////////////////////////////
//Ports for IACT router
.router_mode_iact(), //TB*
//Interface with North
//Source ports
.north_data_i_iact(HMNoC_cluster_west_0.south_data_o_iact),
.north_enable_i_iact(HMNoC_cluster_west_0.south_enable_o_iact),
//Destination ports
.north_data_o_iact(HMNoC_cluster_west_0.south_data_i_iact),
.north_enable_o_iact(HMNoC_cluster_west_0.south_enable_i_iact),
//Interface with South
//Source ports
.south_data_i_iact(),
.south_enable_i_iact(),
//Destination ports
.south_data_o_iact(),
.south_enable_o_iact(),
//Interface with West
//Source ports
// .west_data_i_iact(GLB_cluster_0.r_data_iact), //GLB_cluster
.west_enable_i_iact(),
//Destination ports
// .west_data_o_iact(pe_cluster_0.act_in), //PE_cluster
.west_enable_o_iact(),
//Interface with East - Devices
//Source ports
.east_data_i_iact(),
.east_enable_i_iact(),
//Destination ports
.east_data_o_iact(),
.east_enable_o_iact(),
////////////////////////////////////////////
//Ports for PSUM router
.router_mode_psum(),
//Interface with North
//Source ports
.north_data_i_psum(HMNoC_cluster_west_0.south_data_o_psum),
.north_enable_i_psum(HMNoC_cluster_west_0.south_enable_o_psum),
//Destination ports
.north_data_o_psum(HMNoC_cluster_west_0.south_data_i_psum),
.north_enable_o_psum(HMNoC_cluster_west_0.south_enable_i_psum),
//Interface with South
//Source ports
.south_data_i_psum(),
.south_enable_i_psum(),
//Destination ports
.south_data_o_psum(),
.south_enable_o_psum(),
//Interface with West
//Source ports
.west_data_i_psum(), //PE_cluster
.west_enable_i_psum(),
//Destination ports
// .west_data_o_psum(GLB_cluster_0.w_data_psum), //GLB_cluster
// .west_enable_o_psum(GLB_cluster_0.write_en_psum), //GLB_cluster
//Interface with East - Devices
//Source ports
.east_data_i_psum(HMNoC_cluster_east_1.west_data_o_psum),
.east_enable_i_psum(HMNoC_cluster_east_1.west_enable_o_psum),
//Destination ports
.east_data_o_psum(HMNoC_cluster_east_1.west_data_i_psum),
.east_enable_o_psum(HMNoC_cluster_east_1.west_enable_i_psum),
//PE Cluster
.load_en_wght(),
.load_en_act(),
.start(),
.pe_out(),
.compute_done(),
.load_done()
);
//Instantiation of NORTH_EAST Cluster
HMNoC_cluster_east
#(
.DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH(ADDR_BITWIDTH),
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.NUM_GLB_IACT(NUM_GLB_IACT),
.NUM_GLB_PSUM(NUM_GLB_PSUM),
.NUM_GLB_WGHT(NUM_GLB_WGHT),
.kernel_size(kernel_size),
.act_size(act_size),
.X_dim(X_dim),
.Y_dim(Y_dim)
)
HMNoC_cluster_east_0
(
.clk(clk), //TestBench/Controller
.reset(reset), //TestBench/Controller
//Signals for reading from GLB
.read_req_iact(),
.read_req_psum(), //Read by testbench/controller
.read_req_wght(),
// .r_data_iact(router_cluster_0.r_data_glb_iact),
.r_data_psum(), //Read by testbench/controller
// .r_data_wght(router_cluster_0.r_data_glb_wght),
.r_addr_iact(),
.r_addr_psum(), //testbench for reading final psums
.r_addr_wght(),
//Signals for writing to GLB
.w_addr_iact(), //testbench for writing
.w_addr_psum(),
.w_addr_wght(), //testbench for writing
.w_data_iact(), //testbench for writing
// .w_data_psum(router_cluster_0.w_data_glb_psum),
.w_data_wght(), //testbench for writing
.write_en_iact(), //testbench for writing
// .write_en_psum(router_cluster_0.write_en_glb_psum),
.write_en_wght(), //testbench for writing
//Ports for WGHT router
.router_mode_wght(), //TB*
//Interface with North
//Source ports
.north_data_i_wght(),
.north_enable_i_wght(),
//Destination ports
.north_data_o_wght(),
.north_enable_o_wght(),
//Interface with South
//Source ports
.south_data_i_wght(HMNoC_cluster_east_1.north_data_o_wght),
.south_enable_i_wght(HMNoC_cluster_east_1.north_enable_o_wght),
//Destination ports
.south_data_o_wght(HMNoC_cluster_east_1.north_data_i_wght),
.south_enable_o_wght(HMNoC_cluster_east_1.north_enable_i_wght),
//Interface with West
//Source ports
.west_data_i_wght(HMNoC_cluster_west_0.east_data_o_wght), //GLB_cluster
.west_enable_i_wght(HMNoC_cluster_west_0.east_enable_o_wght),
//Destination ports
.west_data_o_wght(HMNoC_cluster_west_0.east_data_i_wght), //PE_cluster
.west_enable_o_wght(HMNoC_cluster_west_0.east_enable_i_wght),
//Interface with East - Devices
//Source ports
// .east_data_i_wght(east_data_i_wght),
.east_enable_i_wght(),
//Destination ports
// .east_data_o_wght(east_data_o_wght),
.east_enable_o_wght(),
////////////////////////////////////////////
//Ports for IACT router
.router_mode_iact(), //TB*
//Interface with North
//Source ports
.north_data_i_iact(),
.north_enable_i_iact(),
//Destination ports
.north_data_o_iact(),
.north_enable_o_iact(),
//Interface with South
//Source ports
.south_data_i_iact(HMNoC_cluster_east_1.north_data_o_iact),
.south_enable_i_iact(HMNoC_cluster_east_1.north_enable_o_iact),
//Destination ports
.south_data_o_iact(HMNoC_cluster_east_1.north_data_i_iact),
.south_enable_o_iact(HMNoC_cluster_east_1.north_enable_i_iact),
//Interface with West
//Source ports
.west_data_i_iact(HMNoC_cluster_west_0.east_data_o_iact), //GLB_cluster
.west_enable_i_iact(HMNoC_cluster_west_0.east_enable_o_iact),
//Destination ports
.west_data_o_iact(HMNoC_cluster_west_0.east_data_i_iact), //PE_cluster
.west_enable_o_iact(HMNoC_cluster_west_0.east_enable_i_iact),
//Interface with East - Devices
//Source ports
// .east_data_i_iact(east_data_i_iact),
.east_enable_i_iact(),
//Destination ports
// .east_data_o_iact(east_data_o_iact),
.east_enable_o_iact(),
////////////////////////////////////////////
//Ports for PSUM router
.router_mode_psum(),
//Interface with North
//Source ports
.north_data_i_psum(),
.north_enable_i_psum(),
//Destination ports
.north_data_o_psum(),
.north_enable_o_psum(),
//Interface with South
//Source ports
.south_data_i_psum(HMNoC_cluster_east_1.north_data_i_psum),
.south_enable_i_psum(HMNoC_cluster_east_1.north_enable_i_psum),
//Destination ports
.south_data_o_psum(HMNoC_cluster_east_1.north_data_o_psum),
.south_enable_o_psum(HMNoC_cluster_east_1.north_enable_o_psum),
//Interface with West
//Source ports
.west_data_i_psum(HMNoC_cluster_west_0.east_data_o_psum), //PE_cluster
.west_enable_i_psum(HMNoC_cluster_west_0.east_enable_o_psum),
//Destination ports
.west_data_o_psum(HMNoC_cluster_west_0.east_data_i_psum), //GLB_cluster
.west_enable_o_psum(HMNoC_cluster_west_0.east_enable_i_psum), //GLB_cluster
//Interface with East - Devices
//Source ports
.east_data_i_psum(),
.east_enable_i_psum(),
//Destination ports
// .east_data_o_psum(east_data_o_psum),
// .east_enable_o_psum(east_enable_o_psum),
//PE Cluster
.load_en_wght(),
.load_en_act(),
.start(),
.pe_out(),
.compute_done(),
.load_done()
);
//Instantiation of SOUTH_EAST Cluster
HMNoC_cluster_east
#(
.DATA_BITWIDTH(DATA_BITWIDTH),
.ADDR_BITWIDTH(ADDR_BITWIDTH),
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.NUM_GLB_IACT(NUM_GLB_IACT),
.NUM_GLB_PSUM(NUM_GLB_PSUM),
.NUM_GLB_WGHT(NUM_GLB_WGHT),
.kernel_size(kernel_size),
.act_size(act_size),
.X_dim(X_dim),
.Y_dim(Y_dim)
)
HMNoC_cluster_east_1
(
.clk(clk), //TestBench/Controller
.reset(reset), //TestBench/Controller
//Signals for reading from GLB
.read_req_iact(),
.read_req_psum(), //Read by testbench/controller
.read_req_wght(),
// .r_data_iact(router_cluster_0.r_data_glb_iact),
.r_data_psum(), //Read by testbench/controller
// .r_data_wght(router_cluster_0.r_data_glb_wght),
.r_addr_iact(),
.r_addr_psum(), //testbench for reading final psums
.r_addr_wght(),
//Signals for writing to GLB
.w_addr_iact(), //testbench for writing
.w_addr_psum(),
.w_addr_wght(), //testbench for writing
.w_data_iact(), //testbench for writing
// .w_data_psum(router_cluster_0.w_data_glb_psum),
.w_data_wght(), //testbench for writing
.write_en_iact(), //testbench for writing
// .write_en_psum(router_cluster_0.write_en_glb_psum),
.write_en_wght(), //testbench for writing
//Ports for WGHT router
.router_mode_wght(), //TB*
//Interface with North
//Source ports
.north_data_i_wght(HMNoC_cluster_east_0.south_data_o_wght),
.north_enable_i_wght(HMNoC_cluster_east_0.south_enable_o_wght),
//Destination ports
.north_data_o_wght(HMNoC_cluster_east_0.south_data_i_wght),
.north_enable_o_wght(HMNoC_cluster_east_0.south_enable_i_wght),
//Interface with South
//Source ports
.south_data_i_wght(),
.south_enable_i_wght(),
//Destination ports
.south_data_o_wght(),
.south_enable_o_wght(),
//Interface with West
//Source ports
.west_data_i_wght(HMNoC_cluster_west_1.east_data_o_wght), //GLB_cluster
.west_enable_i_wght(HMNoC_cluster_west_1.east_enable_o_wght),
//Destination ports
.west_data_o_wght(HMNoC_cluster_west_1.east_data_i_wght), //PE_cluster
.west_enable_o_wght(HMNoC_cluster_west_1.east_enable_i_wght),
//Interface with East - Devices
//Source ports
// .east_data_i_wght(east_data_i_wght),
.east_enable_i_wght(),
//Destination ports
// .east_data_o_wght(east_data_o_wght),
.east_enable_o_wght(),
////////////////////////////////////////////
//Ports for IACT router
.router_mode_iact(router_mode_iact), //TB*
//Interface with North
//Source ports
.north_data_i_iact(HMNoC_cluster_east_0.south_data_o_iact),
.north_enable_i_iact(HMNoC_cluster_east_0.south_enable_o_iact),
//Destination ports
.north_data_o_iact(HMNoC_cluster_east_0.south_data_i_iact),
.north_enable_o_iact(HMNoC_cluster_east_0.south_enable_i_iact),
//Interface with South
//Source ports
.south_data_i_iact(),
.south_enable_i_iact(),
//Destination ports
.south_data_o_iact(),
.south_enable_o_iact(),
//Interface with West
//Source ports
.west_data_i_iact(HMNoC_cluster_west_1.east_data_o_iact), //GLB_cluster
.west_enable_i_iact(HMNoC_cluster_west_1.east_enable_o_iact),
//Destination ports
.west_data_o_iact(HMNoC_cluster_west_1.east_data_i_iact), //PE_cluster
.west_enable_o_iact(HMNoC_cluster_west_1.east_enable_i_iact),
//Interface with East - Devices
//Source ports
// .east_data_i_iact(east_data_i_iact),
.east_enable_i_iact(),
//Destination ports
// .east_data_o_iact(east_data_o_iact),
.east_enable_o_iact(),
////////////////////////////////////////////
//Ports for PSUM router
.router_mode_psum(),
//Interface with North
//Source ports
.north_data_i_psum(HMNoC_cluster_east_0.south_data_o_psum),
.north_enable_i_psum(HMNoC_cluster_east_0.south_enable_o_psum),
//Destination ports
.north_data_o_psum(HMNoC_cluster_east_0.south_data_i_psum),
.north_enable_o_psum(HMNoC_cluster_east_0.south_enable_i_psum),
//Interface with South
//Source ports
.south_data_i_psum(),
.south_enable_i_psum(),
//Destination ports
.south_data_o_psum(),
.south_enable_o_psum(),
//Interface with West
//Source ports
.west_data_i_psum(HMNoC_cluster_west_1.east_data_o_psum), //PE_cluster
.west_enable_i_psum(HMNoC_cluster_west_1.east_enable_o_psum),
//Destination ports
.west_data_o_psum(HMNoC_cluster_west_1.east_data_i_psum), //GLB_cluster
.west_enable_o_psum(HMNoC_cluster_west_1.east_enable_i_psum), //GLB_cluster
//Interface with East - Devices
//Source ports
.east_data_i_psum(),
.east_enable_i_psum(),
//Destination ports
// .east_data_o_psum(east_data_o_psum),
// .east_enable_o_psum(east_enable_o_psum),
//PE Cluster
.load_en_wght(),
.load_en_act(),
.start(),
.pe_out(),
.compute_done(),
.load_done()
);
endmodule
================================================
FILE: rtl/phase_2/router.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/10/2019 03:39:07 AM
// Design Name:
// Module Name: router
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module router
#(
parameter DATA_WIDTH = 16
)
(
input [3:0] router_mode,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i,
input north_enable_i,
// output logic north_ready_o,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o,
output logic north_enable_o,
// input north_ready_i,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i,
input south_enable_i,
// output logic south_ready_o,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o,
output logic south_enable_o,
// input south_ready_i,
//Interface with West
//Source ports
input [DATA_WIDTH-1:0] west_data_i,
input west_enable_i,
// output logic west_ready_o,
//Destination ports
output logic [DATA_WIDTH-1:0] west_data_o,
output logic west_enable_o,
// input west_ready_i,
//Interface with East - Devices
//Source ports
input [DATA_WIDTH-1:0] east_data_i,
input east_enable_i,
// output logic east_ready_o,
//Destination ports
output logic [DATA_WIDTH-1:0] east_data_o,
output logic east_enable_o
// input east_ready_i
);
logic [DATA_WIDTH-1:0] data_out;
enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
//Logic for selecting data_out based on enable
always_comb
begin:data_switch
unique if(north_enable_i)
data_out = north_data_i;
else if(south_enable_i)
data_out = south_data_i;
else if(west_enable_i)
data_out = west_data_i;
else if(east_enable_i)
data_out = east_data_i;
else
data_out = 10101; //Default value for verification
end
//Logic for data out in destination ports based on routing_mode
always_comb
begin: routing_logic
case(router_mode)
ALL:begin
north_data_o = data_out;
north_enable_o = 1;
south_data_o = data_out;
south_enable_o = 1;
west_data_o = data_out;
west_enable_o = 1;
east_data_o = data_out;
east_enable_o = 1;
end
NORTH:begin
north_data_o = data_out;
south_data_o = 'X;
east_data_o = 'X;
west_data_o = 'X;
north_enable_o = 1;
south_enable_o = 0;
west_enable_o = 0;
east_enable_o = 0;
end
SOUTH:begin
south_data_o = data_out;
north_data_o = 'X;
east_data_o = 'X;
west_data_o = 'X;
north_enable_o = 0;
south_enable_o = 1;
west_enable_o = 0;
east_enable_o = 0;
end
WEST:begin
west_data_o = data_out;
south_data_o = 'X;
east_data_o = 'X;
north_data_o = 'X;
north_enable_o = 0;
south_enable_o = 0;
west_enable_o = 1;
east_enable_o = 0;
end
EAST:begin
east_data_o = data_out;
south_data_o = 'X;
north_data_o = 'X;
west_data_o = 'X;
north_enable_o = 0;
south_enable_o = 0;
west_enable_o = 0;
east_enable_o = 1;
end
//Two Directions - Used for storing in PE cluster and routing
//With East as compute unit
EASTNORTH:begin
east_data_o = data_out;
north_data_o = data_out;
south_data_o = 'X;
west_data_o = 'X;
north_enable_o = 1;
south_enable_o = 0;
west_enable_o = 0;
east_enable_o = 1;
end
EASTSOUTH:begin
east_data_o = data_out;
south_data_o = data_out;
north_data_o = 'X;
west_data_o = 'X;
north_enable_o = 0;
south_enable_o = 1;
west_enable_o = 0;
east_enable_o = 1;
end
EASTWEST:begin
east_data_o = data_out;
west_data_o = data_out;
south_data_o = 'X;
north_data_o = 'X;
north_enable_o = 0;
south_enable_o = 0;
west_enable_o = 1;
east_enable_o = 1;
end
//With West as compute unit
WESTNORTH:begin
west_data_o = data_out;
north_data_o = data_out;
south_data_o = 'X;
east_data_o = 'X;
north_enable_o = 1;
south_enable_o = 0;
west_enable_o = 1;
east_enable_o = 0;
end
WESTSOUTH:begin
west_data_o = data_out;
south_data_o = data_out;
north_data_o = 'X;
east_data_o = 'X;
north_enable_o = 0;
south_enable_o = 1;
west_enable_o = 1;
east_enable_o = 0;
end
WESTEAST:begin
west_data_o = data_out;
east_data_o = data_out;
south_data_o = 'X;
north_data_o = 'X;
north_enable_o = 0;
south_enable_o = 0;
west_enable_o = 1;
east_enable_o = 1;
end
default: begin
north_data_o = 'X;
east_data_o = 'X;
south_data_o = 'X;
west_data_o = 'X;
north_enable_o = 0;
south_enable_o = 0;
west_enable_o = 0;
east_enable_o = 0;
end
endcase
end
endmodule
================================================
FILE: rtl/phase_2/router_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/03/2019 02:24:04 PM
// Design Name:
// Module Name: router_cluster
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module router_cluster
#(
parameter DATA_WIDTH = 16
)
(
//WGHT Router Ports
input [3:0] router_mode_wght,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i_wght,
input north_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o_wght,
output logic north_enable_o_wght,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i_wght,
input south_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o_wght,
output logic south_enable_o_wght,
//Interface with West
//Source ports
input [DATA_WIDTH-1:0] west_data_i_wght,
input west_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] west_data_o_wght,
output logic west_enable_o_wght,
//Interface with East - Devices
//Source ports
input [DATA_WIDTH-1:0] east_data_i_wght,
input east_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] east_data_o_wght,
output logic east_enable_o_wght,
//IACT Router Ports
input [3:0] router_mode_iact,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i_iact,
input north_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o_iact,
output logic north_enable_o_iact,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i_iact,
input south_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o_iact,
output logic south_enable_o_iact,
//Interface with West
//Source ports
input [DATA_WIDTH-1:0] west_data_i_iact,
input west_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] west_data_o_iact,
output logic west_enable_o_iact,
//Interface with East - Devices
//Source ports
input [DATA_WIDTH-1:0] east_data_i_iact,
input east_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] east_data_o_iact,
output logic east_enable_o_iact,
//PSUM Router Ports
input [3:0] router_mode_psum,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i_psum,
input north_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o_psum,
output logic north_enable_o_psum,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i_psum,
input south_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o_psum,
output logic south_enable_o_psum,
//Interface with West
//Source ports
input [DATA_WIDTH-1:0] west_data_i_psum,
input west_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] west_data_o_psum,
output logic west_enable_o_psum,
//Interface with East - Devices
//Source ports
input [DATA_WIDTH-1:0] east_data_i_psum,
input east_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] east_data_o_psum,
output logic east_enable_o_psum
);
router
#(
.DATA_WIDTH(DATA_WIDTH)
)
router_wght
(
.router_mode(router_mode_wght),
//Interface with North
//Source ports
.north_data_i(north_data_i_wght),
.north_enable_i(north_enable_i_wght),
//Destination ports
.north_data_o(north_data_o_wght),
.north_enable_o(north_enable_o_wght),
//Interface with South
//Source ports
.south_data_i(south_data_i_wght),
.south_enable_i(south_enable_i_wght),
//Destination ports
.south_data_o(south_data_o_wght),
.south_enable_o(south_enable_o_wght),
//Interface with West
//Source ports
.west_data_i(west_data_i_wght),
.west_enable_i(west_enable_i_wght),
//Destination ports
.west_data_o(west_data_o_wght),
.west_enable_o(west_enable_o_wght),
//Interface with East - Devices
//Source ports
.east_data_i(east_data_i_wght),
.east_enable_i(east_enable_i_wght),
//Destination ports
.east_data_o(east_data_o_wght),
.east_enable_o(east_enable_o_wght)
);
router
#(
.DATA_WIDTH(DATA_WIDTH)
)
router_iact
(
.router_mode(router_mode_iact),
//Interface with North
//Source ports
.north_data_i(north_data_i_iact),
.north_enable_i(north_enable_i_iact),
//Destination ports
.north_data_o(north_data_o_iact),
.north_enable_o(north_enable_o_iact),
//Interface with South
//Source ports
.south_data_i(south_data_i_iact),
.south_enable_i(south_enable_i_iact),
//Destination ports
.south_data_o(south_data_o_iact),
.south_enable_o(south_enable_o_iact),
//Interface with West
//Source ports
.west_data_i(west_data_i_iact),
.west_enable_i(west_enable_i_iact),
//Destination ports
.west_data_o(west_data_o_iact),
.west_enable_o(west_enable_o_iact),
//Interface with East - Devices
//Source ports
.east_data_i(east_data_i_iact),
.east_enable_i(east_enable_i_iact),
//Destination ports
.east_data_o(east_data_o_iact),
.east_enable_o(east_enable_o_iact)
);
router
#(
.DATA_WIDTH(DATA_WIDTH)
)
router_psum
(
.router_mode(router_mode_psum),
//Interface with North
//Source ports
.north_data_i(north_data_i_psum),
.north_enable_i(north_enable_i_psum),
//Destination ports
.north_data_o(north_data_o_psum),
.north_enable_o(north_enable_o_psum),
//Interface with South
//Source ports
.south_data_i(south_data_i_psum),
.south_enable_i(south_enable_i_psum),
//Destination ports
.south_data_o(south_data_o_psum),
.south_enable_o(south_enable_o_psum),
//Interface with West
//Source ports
.west_data_i(west_data_i_psum),
.west_enable_i(west_enable_i_psum),
//Destination ports
.west_data_o(west_data_o_psum),
.west_enable_o(west_enable_o_psum),
//Interface with East - Devices
//Source ports
.east_data_i(east_data_i_psum),
.east_enable_i(east_enable_i_psum),
//Destination ports
.east_data_o(east_data_o_psum),
.east_enable_o(east_enable_o_psum)
);
endmodule
================================================
FILE: rtl/phase_3/router.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/10/2019 03:39:07 AM
// Design Name:
// Module Name: router
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module router
#(
parameter DATA_WIDTH = 16
)
(
input [3:0] router_mode,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i,
input north_enable_i,
// output logic north_ready_o,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o,
output logic north_enable_o,
// input north_ready_i,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i,
input south_enable_i,
// output logic south_ready_o,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o,
output logic south_enable_o,
// input south_ready_i,
//Interface with West
//Source ports
input [DATA_WIDTH-1:0] west_data_i,
input west_enable_i,
// output logic west_ready_o,
//Destination ports
output logic [DATA_WIDTH-1:0] west_data_o,
output logic west_enable_o,
// input west_ready_i,
//Interface with East - Devices
//Source ports
input [DATA_WIDTH-1:0] east_data_i,
input east_enable_i,
// output logic east_ready_o,
//Destination ports
output logic [DATA_WIDTH-1:0] east_data_o,
output logic east_enable_o
// input east_ready_i
);
logic [DATA_WIDTH-1:0] data_out;
enum logic [3:0] {ALL=0, NORTH=1, SOUTH=2, WEST=3, EAST=4,
EASTNORTH=5, EASTSOUTH=6, EASTWEST=7,
WESTNORTH=8, WESTSOUTH=9, WESTEAST=10} direction;
//Logic for selecting data_out based on enable
always_comb
begin:data_switch
unique if(north_enable_i)
data_out = north_data_i;
else if(south_enable_i)
data_out = south_data_i;
else if(west_enable_i)
data_out = west_data_i;
else if(east_enable_i)
data_out = east_data_i;
else
data_out = 10101; //Default value for verification
end
//Logic for data out in destination ports based on routing_mode
always_comb
begin: routing_logic
case(router_mode)
ALL:begin
north_data_o = data_out;
north_enable_o = 1;
south_data_o = data_out;
south_enable_o = 1;
west_data_o = data_out;
west_enable_o = 1;
east_data_o = data_out;
east_enable_o = 1;
end
NORTH:begin
north_data_o = data_out;
south_data_o = 'X;
east_data_o = 'X;
west_data_o = 'X;
north_enable_o = 1;
south_enable_o = 0;
west_enable_o = 0;
east_enable_o = 0;
end
SOUTH:begin
south_data_o = data_out;
north_data_o = 'X;
east_data_o = 'X;
west_data_o = 'X;
north_enable_o = 0;
south_enable_o = 1;
west_enable_o = 0;
east_enable_o = 0;
end
WEST:begin
west_data_o = data_out;
south_data_o = 'X;
east_data_o = 'X;
north_data_o = 'X;
north_enable_o = 0;
south_enable_o = 0;
west_enable_o = 1;
east_enable_o = 0;
end
EAST:begin
east_data_o = data_out;
south_data_o = 'X;
north_data_o = 'X;
west_data_o = 'X;
north_enable_o = 0;
south_enable_o = 0;
west_enable_o = 0;
east_enable_o = 1;
end
//Two Directions - Used for storing in PE cluster and routing
//With East as compute unit
EASTNORTH:begin
east_data_o = data_out;
north_data_o = data_out;
south_data_o = 'X;
west_data_o = 'X;
north_enable_o = 1;
south_enable_o = 0;
west_enable_o = 0;
east_enable_o = 1;
end
EASTSOUTH:begin
east_data_o = data_out;
south_data_o = data_out;
north_data_o = 'X;
west_data_o = 'X;
north_enable_o = 0;
south_enable_o = 1;
west_enable_o = 0;
east_enable_o = 1;
end
EASTWEST:begin
east_data_o = data_out;
west_data_o = data_out;
south_data_o = 'X;
north_data_o = 'X;
north_enable_o = 0;
south_enable_o = 0;
west_enable_o = 1;
east_enable_o = 1;
end
//With West as compute unit
WESTNORTH:begin
west_data_o = data_out;
north_data_o = data_out;
south_data_o = 'X;
east_data_o = 'X;
north_enable_o = 1;
south_enable_o = 0;
west_enable_o = 1;
east_enable_o = 0;
end
WESTSOUTH:begin
west_data_o = data_out;
south_data_o = data_out;
north_data_o = 'X;
east_data_o = 'X;
north_enable_o = 0;
south_enable_o = 1;
west_enable_o = 1;
east_enable_o = 0;
end
WESTEAST:begin
west_data_o = data_out;
east_data_o = data_out;
south_data_o = 'X;
north_data_o = 'X;
north_enable_o = 0;
south_enable_o = 0;
west_enable_o = 1;
east_enable_o = 1;
end
default: begin
north_data_o = 'X;
east_data_o = 'X;
south_data_o = 'X;
west_data_o = 'X;
north_enable_o = 0;
south_enable_o = 0;
west_enable_o = 0;
east_enable_o = 0;
end
endcase
end
endmodule
================================================
FILE: rtl/phase_3/router_cluster.sv
================================================
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/03/2019 02:24:04 PM
// Design Name:
// Module Name: router_cluster
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module router_cluster
#(
parameter DATA_WIDTH = 16
)
(
//WGHT Router Ports
input [3:0] router_mode_wght,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i_wght,
input north_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o_wght,
output logic north_enable_o_wght,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i_wght,
input south_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o_wght,
output logic south_enable_o_wght,
//Interface with West
//Source ports
input [DATA_WIDTH-1:0] west_data_i_wght,
input west_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] west_data_o_wght,
output logic west_enable_o_wght,
//Interface with East - Devices
//Source ports
input [DATA_WIDTH-1:0] east_data_i_wght,
input east_enable_i_wght,
//Destination ports
output logic [DATA_WIDTH-1:0] east_data_o_wght,
output logic east_enable_o_wght,
//IACT Router Ports
input [3:0] router_mode_iact,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i_iact,
input north_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o_iact,
output logic north_enable_o_iact,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i_iact,
input south_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o_iact,
output logic south_enable_o_iact,
//Interface with West
//Source ports
input [DATA_WIDTH-1:0] west_data_i_iact,
input west_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] west_data_o_iact,
output logic west_enable_o_iact,
//Interface with East - Devices
//Source ports
input [DATA_WIDTH-1:0] east_data_i_iact,
input east_enable_i_iact,
//Destination ports
output logic [DATA_WIDTH-1:0] east_data_o_iact,
output logic east_enable_o_iact,
//PSUM Router Ports
input [3:0] router_mode_psum,
//Interface with North
//Source ports
input [DATA_WIDTH-1:0] north_data_i_psum,
input north_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] north_data_o_psum,
output logic north_enable_o_psum,
//Interface with South
//Source ports
input [DATA_WIDTH-1:0] south_data_i_psum,
input south_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] south_data_o_psum,
output logic south_enable_o_psum,
//Interface with West
//Source ports
input [DATA_WIDTH-1:0] west_data_i_psum,
input west_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] west_data_o_psum,
output logic west_enable_o_psum,
//Interface with East - Devices
//Source ports
input [DATA_WIDTH-1:0] east_data_i_psum,
input east_enable_i_psum,
//Destination ports
output logic [DATA_WIDTH-1:0] east_data_o_psum,
output logic east_enable_o_psum
);
router
#(
.DATA_WIDTH(DATA_WIDTH)
)
router_wght
(
.router_mode(router_mode_wght),
//Interface with North
//Source ports
.north_data_i(north_data_i_wght),
.north_enable_i(north_enable_i_wght),
//Destination ports
.north_data_o(north_data_o_wght),
.north_enable_o(north_enable_o_wght),
//Interface with South
//Source ports
.south_data_i(south_data_i_wght),
.south_enable_i(south_enable_i_wght),
//Destination ports
.south_data_o(south_data_o_wght),
.south_enable_o(south_enable_o_wght),
//Interface with West
//Source ports
.west_data_i(west_data_i_wght),
.west_enable_i(west_enable_i_wght),
//Destination ports
.west_data_o(west_data_o_wght),
.west_enable_o(west_enable_o_wght),
//Interface with East - Devices
//Source ports
.east_data_i(east_data_i_wght),
.east_enable_i(east_enable_i_wght),
//Destination ports
.east_data_o(east_data_o_wght),
.east_enable_o(east_enable_o_wght)
);
router
#(
.DATA_WIDTH(DATA_WIDTH)
)
router_iact
(
.router_mode(router_mode_iact),
//Interface with North
//Source ports
.north_data_i(north_data_i_iact),
.north_enable_i(north_enable_i_iact),
//Destination ports
.north_data_o(north_data_o_iact),
.north_enable_o(north_enable_o_iact),
//Interface with South
//Source ports
.south_data_i(south_data_i_iact),
.south_enable_i(south_enable_i_iact),
//Destination ports
.south_data_o(south_data_o_iact),
.south_enable_o(south_enable_o_iact),
//Interface with West
//Source ports
.west_data_i(west_data_i_iact),
.west_enable_i(west_enable_i_iact),
//Destination ports
.west_data_o(west_data_o_iact),
.west_enable_o(west_enable_o_iact),
//Interface with East - Devices
//Source ports
.east_data_i(east_data_i_iact),
.east_enable_i(east_enable_i_iact),
//Destination ports
.east_data_o(east_data_o_iact),
.east_enable_o(east_enable_o_iact)
);
router
#(
.DATA_WIDTH(DATA_WIDTH)
)
router_psum
(
.router_mode(router_mode_psum),
//Interface with North
//Source ports
.north_data_i(north_data_i_psum),
.north_enable_i(north_enable_i_psum),
//Destination ports
.north_data_o(north_data_o_psum),
.north_enable_o(north_enable_o_psum),
//Interface with South
//Source ports
.south_data_i(south_data_i_psum),
.south_enable_i(south_enable_i_psum),
//Destination ports
.south_data_o(south_data_o_psum),
.south_enable_o(south_enable_o_psum),
//Interface with West
//Source ports
.west_data_i(west_data_i_psum),
.west_enable_i(west_enable_i_psum),
//Destination ports
.west_data_o(west_data_o_psum),
.west_enable_o(west_enable_o_psum),
//Interface with East - Devices
//Source ports
.east_data_i(east_data_i_psum),
.east_enable_i(east_enable_i_psum),
//Destination ports
.east_data_o(east_da
gitextract_4n1buft_/
├── .gitattributes
├── README.md
├── rtl/
│ ├── FA.sv
│ ├── GLB_cluster.sv
│ ├── HA.sv
│ ├── HMNoC_cluster.sv
│ ├── HMNoC_cluster_east.sv
│ ├── HMNoC_cluster_west.sv
│ ├── HMNoC_top.sv
│ ├── MAC.sv
│ ├── PE.sv
│ ├── PE_cluster.sv
│ ├── SPad.sv
│ ├── circular_buffer.sv
│ ├── glb_iact.sv
│ ├── glb_psum.sv
│ ├── glb_weight.sv
│ ├── lookup_mux4.sv
│ ├── misc/
│ │ ├── FA.sv
│ │ ├── HA.sv
│ │ ├── circular_buffer.sv
│ │ ├── mux_4x1.sv
│ │ └── switch.sv
│ ├── mux2.sv
│ ├── mux_4x1.sv
│ ├── phase_1/
│ │ ├── GLB_cluster.sv
│ │ ├── HMNoC_cluster.sv
│ │ ├── PE.sv
│ │ ├── PE_cluster.sv
│ │ ├── SPad.sv
│ │ ├── glb_iact.sv
│ │ ├── glb_psum.sv
│ │ ├── glb_weight.sv
│ │ ├── router_cluster.sv
│ │ ├── router_iact.sv
│ │ ├── router_psum.sv
│ │ └── router_weight.sv
│ ├── phase_2/
│ │ ├── HMNoC_cluster_east.sv
│ │ ├── HMNoC_cluster_west.sv
│ │ ├── HMNoC_top.sv
│ │ ├── router.sv
│ │ └── router_cluster.sv
│ ├── phase_3/
│ │ ├── router.sv
│ │ ├── router_cluster.sv
│ │ └── router_network4.sv
│ ├── router.sv
│ ├── router_cluster.sv
│ ├── router_east.sv
│ ├── router_iact.sv
│ ├── router_network4.sv
│ ├── router_psum.sv
│ ├── router_weight.sv
│ └── switch.sv
├── synth/
│ ├── HMNoC_cluster.vds
│ ├── HMNoC_cluster_utilization_synth.rpt
│ ├── HMNoC_top.vds
│ ├── HMNoC_top_utilization_synth.rpt
│ └── constraints_1.xdc
└── testbench/
├── GLB_cluster_tb.sv
├── HMNoC_1_tb.sv
├── HMNoC_cluster_west_tb.sv
├── MAC_tb.sv
├── PE_cluster_tb.sv
├── PE_tb.sv
├── SPad_tb.sv
├── act_5x5.txt
├── act_7x7.txt
├── adder_tb.sv
├── glb_iact_tb.sv
├── kernel_3x3.txt
├── kernel_5x5.txt
├── phase_1/
│ ├── GLB_cluster_tb.sv
│ ├── HMNoC_1_tb.sv
│ ├── PE_cluster_tb.sv
│ ├── PE_tb.sv
│ ├── router_cluster_5x5_tb.sv
│ ├── router_cluster_tb.sv
│ ├── router_iact.sv
│ ├── router_iact_tb.sv
│ ├── router_psum_tb.sv
│ ├── router_weight.sv
│ └── router_weight_tb.sv
├── phase_2/
│ ├── HMNoC_cluster_west_tb.sv
│ ├── router_cluster_new_tb.sv
│ ├── router_cluster_pe_cluster_5x5_tb.sv
│ ├── router_cluster_pe_cluster_tb.sv
│ ├── router_east_tb.sv
│ ├── router_pe_4_clusters_5x5_tb.sv
│ └── router_pe_4_clusters_tb.sv
├── phase_3/
│ ├── router_broadcast_tb.sv
│ ├── router_multicast_tb.sv
│ ├── router_pe_4_clusters_5x5_tb.sv
│ ├── router_pe_4_clusters_tb.sv
│ └── router_unicast_tb.sv
├── psum_3x3.txt
├── router_act.sv
├── router_broadcast_tb.sv
├── router_cluster_5x5_tb.sv
├── router_cluster_new_tb.sv
├── router_cluster_pe_cluster_5x5_tb.sv
├── router_cluster_pe_cluster_tb.sv
├── router_cluster_tb.sv
├── router_east_tb.sv
├── router_glb_tb.sv
├── router_iact.sv
├── router_iact_tb.sv
├── router_multicast_tb.sv
├── router_pe_4_clusters_5x5_tb.sv
├── router_pe_4_clusters_tb.sv
├── router_psum_tb.sv
├── router_unicast_tb.sv
├── router_weight.sv
├── router_weight_tb.sv
└── switch_tb.sv
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About this extraction
This page contains the full source code of the karthisugumar/CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2 GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 114 files (1.7 MB), approximately 648.9k tokens. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.
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