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Repository: wuxx/icesugar-pro
Branch: master
Commit: 087e48d9e0b0
Files: 89
Total size: 44.5 MB
Directory structure:
gitextract_1pgxlb8x/
├── README.md
├── demo/
│ ├── README.md
│ ├── blink.svf
│ ├── blink_100.bit
│ ├── blink_1000.bit
│ ├── blink_blue.bit
│ ├── blink_blue.svf
│ ├── blink_flash.svf
│ ├── blink_green.bit
│ ├── blink_green.svf
│ ├── blink_red.bit
│ ├── blink_red.svf
│ ├── blink_sram.svf
│ ├── colorlight_5a_75b_flash.svf
│ ├── hdmi_test_pattern.bit
│ ├── linux-with-litex.bit
│ ├── litex_no_dram.bit
│ ├── litex_with_dram.bit
│ ├── litex_with_dram.svf
│ ├── litex_with_dram_flash.svf
│ ├── uart_tx_9600.bit
│ ├── uart_tx_9600_flash.svf
│ └── uart_tx_flash.svf
├── doc/
│ ├── ECP5U25Pinout.csv
│ └── LFE5U-25F-5BG256-Pinout.csv
├── firmware/
│ └── README.md
├── linux/
│ ├── Image
│ ├── README.md
│ ├── boot.json
│ ├── rootfs.cpio
│ └── rv32.dtb
├── schematic/
│ └── README.md
├── src/
│ ├── blink/
│ │ ├── Makefile
│ │ ├── blink.bit
│ │ ├── blink.json
│ │ ├── blink.lpf
│ │ ├── blink.svf
│ │ ├── blink.v
│ │ ├── blink_out.config
│ │ └── rst_gen.v
│ ├── hdmi_test_pattern/
│ │ ├── Makefile
│ │ ├── Makefile.sim
│ │ ├── OBUFDS.v
│ │ ├── README.md
│ │ ├── TMDS_encoder.v
│ │ ├── ULX3S_25F.json
│ │ ├── ULX3S_25F.v
│ │ ├── ULX3S_25F.ys
│ │ ├── clock.v
│ │ ├── icesugar_pro.lpf
│ │ ├── llhdmi.v
│ │ ├── llhdmi_tb.cpp
│ │ ├── pattern.v
│ │ ├── pattern_tb.cpp
│ │ ├── testb.h
│ │ ├── ulx3s_25f_ULX3S_25F.bit
│ │ ├── ulx3s_25f_ULX3S_25F.config
│ │ ├── ulx3s_v20_segpdi.lpf
│ │ ├── vgatestsrc.v
│ │ └── ysgen.sh
│ ├── litex_linux/
│ │ ├── README.md
│ │ ├── build_top.sh
│ │ ├── mem.init
│ │ ├── mem_1.init
│ │ ├── mem_2.init
│ │ ├── top.bit
│ │ ├── top.config
│ │ ├── top.json
│ │ ├── top.rpt
│ │ ├── top.svf
│ │ ├── top.v
│ │ ├── top.ys
│ │ └── top_bg256.lpf
│ └── uart_tx/
│ ├── .gitignore
│ ├── .top.lpf.swp
│ ├── Makefile
│ ├── rst_gen.v
│ ├── top.lpf
│ ├── top.v
│ ├── uart_tx.v
│ └── uart_tx_out.config
└── tools/
├── README.md
├── cmsisdap.cfg
├── dapprog
├── env.sh
├── ujprog.bit2svf
├── ujprog.bit2svf.arm
├── ujprog.bit2svf.x64
└── ujprog.patch
================================================
FILE CONTENTS
================================================
================================================
FILE: README.md
================================================
iCESugar-pro
-----------
* [iCESugar-pro](#iCESugar-pro)
* [Hardware](#hardware)
* [ECP5](#ecp5)
* [SDRAM](#sdram)
* [SPI-Flash](#spi-flash)
* [Clock](#clock)
* [Peripheral](#peripheral)
* [JTAG](#jtag)
* [iCELink](#icelink)
* [Virtual machine image](#virtual-machine-image)
* [How to setup](#how-to-setup-env)
* [How to buy](#how-to-buy)
* [Copyright Statement](#copyright-statement)
* [Reference](#reference)
# iCESugar-pro
iCESugar-pro is a FPGA development board based on Lattice LFE5U-25F-6BG256C, which is fully supported by the open source toolchain (yosys & nextpnr), the board is designed in DDR2 SODIMM form factor with 106 usable IOs, with on-board 32MB SDRAM, it can run RISC-V Linux. The on-board iCELink debugger (base on ARM Mbed DAPLink) supports drag-and-drop programming, you can just drag the FPGA bitstream into the virtual disk to program, and with a additional USB CDC serial port direct connect to FPGA, so you can only use one Type C cable to develop and test.
<div align=center>
<img src="https://github.com/wuxx/icesugar-pro/blob/master/doc/iCESugar-pro-1.jpg" width = "700" alt="" align=center />
<img src="https://github.com/wuxx/icesugar-pro/blob/master/doc/iCESugar-pro-2.jpg" width = "700" alt="" align=center />
<img src="https://github.com/wuxx/icesugar-pro/blob/master/doc/iCESugar-pro-3.jpg" width = "700" alt="" align=center />
</div>
# Hardware
### ECP5
LFE5U-25F-6BG256C (BGA256 0.8mm pitch)
1. LUTs: 24K
2. sysMEM Blocks: 18Kb x 56
3. Embedded Memory: 1008Kb
4. Distributed RAM bits: 194Kb
5. 18 x 18 Multipliers: 28
6. PLL x 1
### SDRAM
SDRAM uses IS42S16160B (32MB)
### SPI-Flash
SPI Flash uses W25Q256JV (32MB)
### Clock
A 25MHz crystal is connect to P6
### Peripheral
2. a RGB LED is connected to {A11, A12, B11}
3. a SDCARD slot, support SPI/SDIO
4. 106 usable IOs out with SODIMM-DDR2-200P, broken out with the ext-board.
### JTAG
The native JTAG of ECP5 is connect to the on-board iCELink, you can flash bitstream with this JTAG interface (called JTAG1).
There is also another JTAG interface (actually, just some GPIOs of ECP5) connected to the iCELink too (called JTAG2),
if you design a SoC with a JTAG interface support, then you can use the JTAG2 to debug your SoC. Only one JTAG works at once.
So use the icesprog tool with command `icesprog -j 1 or 2` to switch between these two JTAG interface.
```
$icesprog -j 1
JTAG --> [JTAG-1]
[JTAG-1]
TCK: iCELink-PB6 -- ECP5-JTAG-TCK (25F-BG256-T10)
TMS: iCELink-PB4 -- ECP5-JTAG-TMS (25F-BG256-T11)
TDI: iCELink-PB5 -- ECP5-JTAG-TDI (25F-BG256-R11)
TDO: iCELink-PB3 -- ECP5-JTAG-TDO (25F-BG256-M10)
[JTAG-2]
TCK: iCELink-PA14 -- ECP5-IO-PL8D (25F-BG256-F5)
TMS: iCELink-PA13 -- ECP5-IO-PL17A (25F-BG256-H5)
TDI: iCELink-PA0 -- ECP5-IO-PL38A (25F-BG256-N4)
TDO: iCELink-PA1 -- ECP5-IO-PL17D (25F-BG256-J5)
done
```
### iCELink
iCESugar-pro has a on-board debugger named iCELink (base on APM32F1)，only needing one USB wire to program the FPGA and debug it:
1. Drag and drop programming, just drop the bitstream into the virtual USB drive named iCELink then wait a few seconds while the iCELink firmware programs it for you.
2. USB CDC serial port, it can use to communicate with FPGA
3. 2 JTAG interfaces for flashing the ECP5 or debugging your SoC on ECP5
4. use the command tool `icesprog` to flash or do more config, here is the help info
```
$icesprog -h
usage: /home/pi/oss/icesugar/tools/icesprog.arm [OPTION] [FILE]
-w | --write write spi-flash or gpio
-r | --read read spi-flash or gpio
-e | --erase erase spi-flash
-p | --probe probe spi-flash
-o | --offset spi-flash offset
-l | --len len of write/read
-g | --gpio icelink gpio write/read
-m | --mode icelink gpio mode
-j | --jtag-sel jtag interface select (1 or 2)
-c | --clk-sel clk source select (1 to 4)
-h | --help display help info
-- version 1.1a --
```
#### Tips
cause the iCELink connect some GPIOs to the ECP5, you can control this GPIOs with `icesprog` to do some self defined behavior,
for example, to control the iCELink-PA14 -- ECP5-F5 line out low, type these command.
```
$icesprog -g PA14 -m out
$icesprog -g PA14 -w 0
```
#### How To Program
There are multiple ways to program the bitstream.
1. Drag and drop programming, this is the fastest and simplest way to flash.
2. Using the command `icesprog xxx.bit`, this can provide more configable parameters.
3. Using the command `dapprog xxx.bit (program to flash) or dapprog xxx.svf (program to SRAM)`
the `icesprog` binary and source code is in [icesugar](https://github.com/wuxx/icesugar/tree/master/tools) repo, and the `dapprog` is a bash wrapper of openocd command, click [here](https://github.com/wuxx/icesugar-pro/tree/master/tools) to check how to setup.
# Virtual machine image
link：https://pan.baidu.com/s/1vV2ckFpOuyd600Y47Tl1sw
verify code：i3en
`user: ubuntu`
`passwd: ubuntu`
The env include yosys, nextpnr, icestorm, gcc, sbt.
# How to setup enviroment
## Linux
It is reccomended that you use the virtual machine image, it simple and convenient.\
Alternatively, you can download the toolchain for programming the FPGA unit by following the instructions in the "Installing Toolkits" section below and the RISC-V compiler for running your code has a tutorial linked in the "Other tools" section.
## Windows
If you don't want to use the virtual machine image you need to use the Windows Subsystem For Linux 2 (WSL2) as not all components of the toolchain has native windows versions.\
Install WSL using [this tutorial.](https://learn.microsoft.com/en-us/windows/wsl/install) By default it uses ubuntu, which this section is written for. Once WSL is installed and configured you can open it by searching for 'WSL' from the start menu.\
Once in the WSL desktop you will need to preform the following commands to install the needed toolkits.
## Installing Toolkits (Windows and Linux)
The easiest way to get all needed tools is using the [YosysHQ oss-cad-suite](https://github.com/YosysHQ/oss-cad-suite-build). All you need to do is download and extract the repository to a location on your machine such as the home folder. After you extract it you'll need to update your PATH variable so your terminal can use the programs.\
Do this by editing your `.bashrc` file on your home folder using `sudo nano .bashrc` from there. Scrolll to the end of the file and in a new line add `export PATH="$PATH:/home/YOUR_ACCOUNT_NAME_HERE/oss-cad-suite/bin"`
### Other tools
Dapprog is included in the tools folder and can be executed from there. ecpprog is included in the install for nextpnr and the RISC-V gcc toolchain used for code compilation can be installed using [this tutorial](https://github.com/riscv-collab/riscv-gnu-toolchain)
## Building demo files
If you want to use the demo files as is you just need to program the bitstream provided in the [`demo`](./demo) folder.
<!-- The relative location allows this link to work both online and locally-->
If you want to change how the demos behave you will need to rebuild them. For the blink, hdmi and uart tests you just need to run `make` in the same folder to update them with your changes. For the litex_linux demo you will need to have the [litex repository](https://github.com/litex-hub/linux-on-litex-vexriscv) downloaded locally and will need to modify the `top.ys` file where it lists `INSTALL_DIR` with the location you put the repo.
# How to buy
You can buy iCESugar-pro and PMOD peripherals from our offcial aliexpress shop [Muse Lab Factory Store](https://miusecn-muselab-tech.aliexpress.com/) or [Tindie Store](https://www.tindie.com/products/johnnywu/icesugar-pro-fpga-development-board/)
# Copyright Statement
The HDMI test verilog source code is from [github.com/DoctorWkt/ULX3S-Blinky](https://github.com/DoctorWkt/ULX3S-Blinky)
The Litex on Linux project is from [github.com/litex-hub/linux-on-litex-vexriscv](https://github.com/litex-hub/linux-on-litex-vexriscv)
For hobby and personal usage, you are free to use the iCESugar-pro, you can also make the board yourself using the documentation & firmware in this repo.
For the commercial usage, if you get iCESugar-pro Board from our official shop and use in other commercial product, that's no problem, otherwise, please contact us in advance.
# Reference
### Colorlight-FPGA-Projects
https://github.com/wuxx/Colorlight-FPGA-Projects
### icestorm toolchain
http://www.clifford.at/icestorm/
### riscv gcc toolchain
https://xpack.github.io/riscv-none-embed-gcc/install/
https://www.sifive.com/software
### iCESugar
https://github.com/wuxx/icesugar
### iCESugar-nano
https://github.com/wuxx/icesugar-nano
### Examples
https://github.com/damdoy/ice40_ultraplus_examples
https://github.com/icebreaker-fpga/icebreaker-examples
### SpinalHDL
https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Getting%20Started/index.html
================================================
FILE: demo/README.md
================================================
## litex_no_dram
`$picocom -b 115200 /dev/ttyACM0`
`$dapprog litex_no_dram.bit`
## litex_with_dram
`$picocom -b 38400 /dev/ttyACM0`
`$dapprog litex_with_dram.bit`
================================================
FILE: demo/blink.svf
================================================
HDR 0;
HIR 0;
TDR 0;
TIR 0;
ENDDR DRPAUSE;
ENDIR IRPAUSE;
STATE IDLE;
SIR 8 TDI (E0);
SDR 32 TDI (00000000)
TDO (41111043)
MASK (FFFFFFFF);
SIR 8 TDI (1C);
SDR 510 TDI (3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF);
SIR 8 TDI (C6);
SDR 8 TDI (00);
RUNTEST IDLE 2 TCK 1.00E-02 SEC;
SIR 8 TDI (0E);
SDR 8 TDI (01);
RUNTEST IDLE 2 TCK 1.00E-02 SEC;
SIR 8 TDI (3C);
SDR 32 TDI (00000000)
TDO (00000000)
MASK (0000B000);
SIR 8 TDI (46);
SDR 8 TDI (01);
RUNTEST IDLE 2 TCK 1.00E-02 SEC;
SIR 8 TDI (7A);
RUNTEST IDLE 2 TCK 1.00E-02 SEC;
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gitextract_1pgxlb8x/
├── README.md
├── demo/
│ ├── README.md
│ ├── blink.svf
│ ├── blink_100.bit
│ ├── blink_1000.bit
│ ├── blink_blue.bit
│ ├── blink_blue.svf
│ ├── blink_flash.svf
│ ├── blink_green.bit
│ ├── blink_green.svf
│ ├── blink_red.bit
│ ├── blink_red.svf
│ ├── blink_sram.svf
│ ├── colorlight_5a_75b_flash.svf
│ ├── hdmi_test_pattern.bit
│ ├── linux-with-litex.bit
│ ├── litex_no_dram.bit
│ ├── litex_with_dram.bit
│ ├── litex_with_dram.svf
│ ├── litex_with_dram_flash.svf
│ ├── uart_tx_9600.bit
│ ├── uart_tx_9600_flash.svf
│ └── uart_tx_flash.svf
├── doc/
│ ├── ECP5U25Pinout.csv
│ └── LFE5U-25F-5BG256-Pinout.csv
├── firmware/
│ └── README.md
├── linux/
│ ├── Image
│ ├── README.md
│ ├── boot.json
│ ├── rootfs.cpio
│ └── rv32.dtb
├── schematic/
│ └── README.md
├── src/
│ ├── blink/
│ │ ├── Makefile
│ │ ├── blink.bit
│ │ ├── blink.json
│ │ ├── blink.lpf
│ │ ├── blink.svf
│ │ ├── blink.v
│ │ ├── blink_out.config
│ │ └── rst_gen.v
│ ├── hdmi_test_pattern/
│ │ ├── Makefile
│ │ ├── Makefile.sim
│ │ ├── OBUFDS.v
│ │ ├── README.md
│ │ ├── TMDS_encoder.v
│ │ ├── ULX3S_25F.json
│ │ ├── ULX3S_25F.v
│ │ ├── ULX3S_25F.ys
│ │ ├── clock.v
│ │ ├── icesugar_pro.lpf
│ │ ├── llhdmi.v
│ │ ├── llhdmi_tb.cpp
│ │ ├── pattern.v
│ │ ├── pattern_tb.cpp
│ │ ├── testb.h
│ │ ├── ulx3s_25f_ULX3S_25F.bit
│ │ ├── ulx3s_25f_ULX3S_25F.config
│ │ ├── ulx3s_v20_segpdi.lpf
│ │ ├── vgatestsrc.v
│ │ └── ysgen.sh
│ ├── litex_linux/
│ │ ├── README.md
│ │ ├── build_top.sh
│ │ ├── mem.init
│ │ ├── mem_1.init
│ │ ├── mem_2.init
│ │ ├── top.bit
│ │ ├── top.config
│ │ ├── top.json
│ │ ├── top.rpt
│ │ ├── top.svf
│ │ ├── top.v
│ │ ├── top.ys
│ │ └── top_bg256.lpf
│ └── uart_tx/
│ ├── .gitignore
│ ├── .top.lpf.swp
│ ├── Makefile
│ ├── rst_gen.v
│ ├── top.lpf
│ ├── top.v
│ ├── uart_tx.v
│ └── uart_tx_out.config
└── tools/
├── README.md
├── cmsisdap.cfg
├── dapprog
├── env.sh
├── ujprog.bit2svf
├── ujprog.bit2svf.arm
├── ujprog.bit2svf.x64
└── ujprog.patch
SYMBOL INDEX (8 symbols across 3 files)
FILE: src/hdmi_test_pattern/llhdmi_tb.cpp
function main (line 13) | int main(int argc, char **argv) {
FILE: src/hdmi_test_pattern/pattern_tb.cpp
function main (line 13) | int main(int argc, char **argv) {
FILE: src/hdmi_test_pattern/testb.h
function virtual (line 47) | virtual ~TESTB(void) {
function virtual (line 53) | virtual void opentrace(const char *vcdname) {
function virtual (line 61) | virtual void closetrace(void) {
function virtual (line 69) | virtual void eval(void) {
function virtual (line 73) | virtual void tick(void) {
function tickcount (line 95) | unsigned long tickcount(void) {
Copy disabled (too large)
Download .json
Condensed preview — 89 files, each showing path, character count, and a content snippet. Download the .json file for the full structured content (32,188K chars).
[
{
"path": "README.md",
"chars": 9292,
"preview": "iCESugar-pro\n-----------\n* [iCESugar-pro](#iCESugar-pro) \n* [Hardware](#hardware)\n\t* [ECP5](#ecp5)\n\t* [SDRAM](#sdram)\n\t*"
},
{
"path": "demo/README.md",
"chars": 169,
"preview": "## litex_no_dram\n`$picocom -b 115200 /dev/ttyACM0` \n`$dapprog litex_no_dram.bit`\n\n## litex_with_dram\n`$picocom -b 38400"
},
{
"path": "demo/blink.svf",
"chars": 1232140,
"preview": "HDR\t0;\nHIR\t0;\nTDR\t0;\nTIR\t0;\nENDDR\tDRPAUSE;\nENDIR\tIRPAUSE;\nSTATE\tIDLE;\nSIR\t8\tTDI (E0);\nSDR\t32\tTDI (00000000)\n\t\t\tTDO (4"
},
{
"path": "demo/blink_blue.svf",
"chars": 1232140,
"preview": "HDR\t0;\nHIR\t0;\nTDR\t0;\nTIR\t0;\nENDDR\tDRPAUSE;\nENDIR\tIRPAUSE;\nSTATE\tIDLE;\nSIR\t8\tTDI (E0);\nSDR\t32\tTDI (00000000)\n\t\t\tTDO (4"
},
{
"path": "demo/blink_flash.svf",
"chars": 1446834,
"preview": "//ULX2S / ULX3S JTAG programmer v 3.0.92 (built Sep 19 2020 14:37:22)\n//START\r\nSTATE IDLE;\nSTATE RESET;\nSTATE IDLE;\n\nSIR"
},
{
"path": "demo/blink_green.svf",
"chars": 1232140,
"preview": "HDR\t0;\nHIR\t0;\nTDR\t0;\nTIR\t0;\nENDDR\tDRPAUSE;\nENDIR\tIRPAUSE;\nSTATE\tIDLE;\nSIR\t8\tTDI (E0);\nSDR\t32\tTDI (00000000)\n\t\t\tTDO (4"
},
{
"path": "demo/blink_red.svf",
"chars": 1232140,
"preview": "HDR\t0;\nHIR\t0;\nTDR\t0;\nTIR\t0;\nENDDR\tDRPAUSE;\nENDIR\tIRPAUSE;\nSTATE\tIDLE;\nSIR\t8\tTDI (E0);\nSDR\t32\tTDI (00000000)\n\t\t\tTDO (4"
},
{
"path": "demo/blink_sram.svf",
"chars": 1190150,
"preview": "//ULX2S / ULX3S JTAG programmer v 3.0.92 (built Sep 19 2020 14:37:22)\n//START\r\nSTATE IDLE;\nSTATE RESET;\nSTATE IDLE;\n\nSIR"
},
{
"path": "demo/colorlight_5a_75b_flash.svf",
"chars": 1751882,
"preview": "//ULX2S / ULX3S JTAG programmer v 3.0.92 (built Sep 19 2020 14:37:22)\n//START\r\nSTATE IDLE;\nSTATE RESET;\nSTATE IDLE;\n\nSIR"
},
{
"path": "demo/litex_with_dram.svf",
"chars": 1491854,
"preview": "HDR\t0;\nHIR\t0;\nTDR\t0;\nTIR\t0;\nENDDR\tDRPAUSE;\nENDIR\tIRPAUSE;\nSTATE\tIDLE;\nSIR\t8\tTDI (E0);\nSDR\t32\tTDI (00000000)\n\t\t\tTDO (4"
},
{
"path": "demo/litex_with_dram_flash.svf",
"chars": 1751882,
"preview": "//ULX2S / ULX3S JTAG programmer v 3.0.92 (built Sep 19 2020 14:37:22)\n//START\r\nSTATE IDLE;\nSTATE RESET;\nSTATE IDLE;\n\nSIR"
},
{
"path": "demo/uart_tx_9600_flash.svf",
"chars": 1446834,
"preview": "//ULX2S / ULX3S JTAG programmer v 3.0.92 (built Sep 19 2020 14:37:22)\n//START\r\nSTATE IDLE;\nSTATE RESET;\nSTATE IDLE;\n\nSIR"
},
{
"path": "demo/uart_tx_flash.svf",
"chars": 1446834,
"preview": "//ULX2S / ULX3S JTAG programmer v 3.0.92 (built Sep 19 2020 14:37:22)\n//START\r\nSTATE IDLE;\nSTATE RESET;\nSTATE IDLE;\n\nSIR"
},
{
"path": "doc/ECP5U25Pinout.csv",
"chars": 21374,
"preview": "# Pin Out For ECP5U-25,,,,,,,,,\n# Revision 1.1 - Include CABGA256 package,,,,,,,,,\n\"# Revised Oct. 17, 2017\",,,,,,,,,\n,,"
},
{
"path": "doc/LFE5U-25F-5BG256-Pinout.csv",
"chars": 10601,
"preview": "# Pin Out For ECP5U-25,,,,,,,,,,\n# Revision 1.1 - Include CABGA256 package,,,,,,,,,,\n\"# Revised Oct. 17, 2017\",,,,,,,,,,"
},
{
"path": "firmware/README.md",
"chars": 53,
"preview": "this 128KB firmware include usb-hid & usb-cdc device\n"
},
{
"path": "linux/README.md",
"chars": 8738,
"preview": "## How-To-Boot-Linux\n\n1. program the bitstream \n`$icesprog ../demo/linux-with-litex.bit`\n\n2. put system files into the "
},
{
"path": "linux/boot.json",
"chars": 128,
"preview": "{\n\t\"Image\": \"0x40000000\",\n\t\"rootfs.cpio\": \"0x40800000\",\n\t\"rv32.dtb\": \"0x41000000\",\n\t\"emulator.bin\": \"0x4110"
},
{
"path": "schematic/README.md",
"chars": 5411,
"preview": "## DDR-SODIMM-200P\n| Function | Top-Pin | Bot-Pin | Function |\n|----------|---------|---------|----------|\n| GND | "
},
{
"path": "src/blink/Makefile",
"chars": 504,
"preview": "TARGET=blink\nTOP=blink\n\nOBJS+=blink.v rst_gen.v\n\nall: ${TARGET}.bit\n\n$(TARGET).json: $(OBJS)\n\tyosys -p \"synth_ecp5 -json"
},
{
"path": "src/blink/blink.json",
"chars": 795680,
"preview": "{\n \"creator\": \"Yosys 0.9+3672 (git sha1 924f1713, gcc 8.3.0-6+rpi1 -fPIC -Os)\",\n \"modules\": {\n \"\\\\$__ABC9_LUT5\": {\n"
},
{
"path": "src/blink/blink.lpf",
"chars": 239,
"preview": "LOCATE COMP \"clk_i\" SITE \"P6\";\nIOBUF PORT \"clk_i\" IO_TYPE=LVCMOS33;\nFREQUENCY PORT \"clk_i\" 25 MHZ;\n\n//LOCATE COMP \"led_o"
},
{
"path": "src/blink/blink.svf",
"chars": 1232140,
"preview": "HDR\t0;\nHIR\t0;\nTDR\t0;\nTIR\t0;\nENDDR\tDRPAUSE;\nENDIR\tIRPAUSE;\nSTATE\tIDLE;\nSIR\t8\tTDI (E0);\nSDR\t32\tTDI (00000000)\n\t\t\tTDO (4"
},
{
"path": "src/blink/blink.v",
"chars": 596,
"preview": "module blink (\n input clk_i,\n output reg led_o\n);\nlocalparam MAX = 2_500_000;\nlocalparam WIDTH = $clog2(MAX);"
},
{
"path": "src/blink/blink_out.config",
"chars": 23573,
"preview": ".device LFE5U-25F\n\n.comment Part: LFE5U-25F-6CABGA256\n\n.tile CIB_R1C54:CIB\narc: JA0 S1_V02N0701\nenum: CIB.JB0MUX 0\n\n.til"
},
{
"path": "src/blink/rst_gen.v",
"chars": 324,
"preview": "module rst_gen (\n\tinput \t\t\tclk_i,\n\tinput \t\t\trst_i,\n\toutput\t\t\trst_o\n);\n\n/* try to generate a reset */\nreg [2:0]\trst_cpt;\n"
},
{
"path": "src/hdmi_test_pattern/Makefile",
"chars": 1040,
"preview": "YOSYS=yosys\nNEXTPNR=nextpnr-ecp5\nECPPACK=ecppack\nHDMICODE=DVI_3x3.v\nHDMICODE=llhdmi.v vgatestsrc.v\nENCODER=TMDS_encoder."
},
{
"path": "src/hdmi_test_pattern/Makefile.sim",
"chars": 1879,
"preview": "##\n## Verilator Rules\n##\n.PHONY: all\n#.DELETE_ON_ERROR:\nTOPMOD := DVI_3x3\nTOPMOD := llhdmi\nTOPMOD := pattern\nVLOGFIL "
},
{
"path": "src/hdmi_test_pattern/OBUFDS.v",
"chars": 336,
"preview": "// (c) fpga4fun.com & KNJN LLC 2013\r\n\r\n////////////////////////////////////////////////////////////////////////\r\nmodule "
},
{
"path": "src/hdmi_test_pattern/README.md",
"chars": 1237,
"preview": "# ULX3S HDMI Test Patterm Generator\n\nI've taken the idea of a low-level video generator from Dan Gisselquist's\n[llvga.v]"
},
{
"path": "src/hdmi_test_pattern/TMDS_encoder.v",
"chars": 2004,
"preview": "// (c) fpga4fun.com & KNJN LLC 2013\n\n////////////////////////////////////////////////////////////////////////\nmodule TMD"
},
{
"path": "src/hdmi_test_pattern/ULX3S_25F.json",
"chars": 2032957,
"preview": "{\n \"creator\": \"Yosys 0.9+3672 (git sha1 924f1713, gcc 8.3.0-6+rpi1 -fPIC -Os)\",\n \"modules\": {\n \"\\\\$__ABC9_LUT5\": {\n"
},
{
"path": "src/hdmi_test_pattern/ULX3S_25F.v",
"chars": 1509,
"preview": "`default_nettype none\n\nmodule ULX3S_25F (\n\tinput clk_25mhz,\n output [3:0] gpdi_dp, gpdi_dn,\n\toutput wifi_gpio0);\n"
},
{
"path": "src/hdmi_test_pattern/ULX3S_25F.ys",
"chars": 201,
"preview": "read_verilog ULX3S_25F.v\nread_verilog llhdmi.v\nread_verilog vgatestsrc.v\nread_verilog TMDS_encoder.v\nread_verilog clock."
},
{
"path": "src/hdmi_test_pattern/clock.v",
"chars": 1562,
"preview": "module clock\n(\n input clkin_25MHz,\n output clk_125MHz,\n output clk_250MHz,\n output clk_25MHz,\n output clk_83M333Hz,"
},
{
"path": "src/hdmi_test_pattern/icesugar_pro.lpf",
"chars": 1166,
"preview": "BLOCK RESETPATHS;\nBLOCK ASYNCPATHS;\n## ULX3S v2.x.x and v3.0.x\n\n# The clock \"usb\" and \"gpdi\" sheet\n\n#ULX3S\n#LOCATE COMP "
},
{
"path": "src/hdmi_test_pattern/llhdmi.v",
"chars": 3733,
"preview": "`default_nettype none\n//\nmodule llhdmi(\n i_tmdsclk, i_pixclk,\n i_reset, i_red, i_grn, i_blu,\n o_rd, o_newline, o_newf"
},
{
"path": "src/hdmi_test_pattern/llhdmi_tb.cpp",
"chars": 590,
"preview": "#include <verilatedos.h>\n#include <stdio.h>\n#include <fcntl.h>\n#include <unistd.h>\n#include <string.h>\n#include <time.h>"
},
{
"path": "src/hdmi_test_pattern/pattern.v",
"chars": 1204,
"preview": "`default_nettype none\n\nmodule pattern(input i_tmdsclk, i_pixclk, output red, grn, blu, o_rd,\n\to_TMDS_red, o_TMDS_grn, o_"
},
{
"path": "src/hdmi_test_pattern/pattern_tb.cpp",
"chars": 1097,
"preview": "#include <verilatedos.h>\n#include <stdio.h>\n#include <fcntl.h>\n#include <unistd.h>\n#include <string.h>\n#include <time.h>"
},
{
"path": "src/hdmi_test_pattern/testb.h",
"chars": 2440,
"preview": "////////////////////////////////////////////////////////////////////////////////\n//\n// Filename: \ttestb.h\n//\n// Project:"
},
{
"path": "src/hdmi_test_pattern/ulx3s_25f_ULX3S_25F.config",
"chars": 424041,
"preview": ".device LFE5U-25F\n\n.comment Part: LFE5U-25F-6CABGA256\n\n.tile CIB_R10C1:CIB_LR\narc: E1_H02E0601 E1_H01W0000\narc: E1_H02E0"
},
{
"path": "src/hdmi_test_pattern/ulx3s_v20_segpdi.lpf",
"chars": 20544,
"preview": "BLOCK RESETPATHS;\nBLOCK ASYNCPATHS;\n## ULX3S v2.x.x and v3.0.x\n\n# The clock \"usb\" and \"gpdi\" sheet\n\n#ULX3S\n#LOCATE COMP "
},
{
"path": "src/hdmi_test_pattern/vgatestsrc.v",
"chars": 7858,
"preview": "////////////////////////////////////////////////////////////////////////////////\n//\n// Filename: \tvgatestsrc.v\n//\n// Pro"
},
{
"path": "src/hdmi_test_pattern/ysgen.sh",
"chars": 94,
"preview": "#!/bin/sh\n# first file is toplevel file\n\nfor file in $*\ndo\n echo \"read_verilog ${file}\"\ndone\n"
},
{
"path": "src/litex_linux/README.md",
"chars": 307,
"preview": "# source code\nhttps://github.com/litex-hub/linux-on-litex-vexriscv.git\n\n# how to build\njust pick a ECP5 type board and g"
},
{
"path": "src/litex_linux/build_top.sh",
"chars": 268,
"preview": "# Autogenerated by LiteX / git: 275932f5\nset -e\nyosys -l top.rpt top.ys\nnextpnr-ecp5 --json top.json --lpf top_bg256.lpf"
},
{
"path": "src/litex_linux/mem.init",
"chars": 60240,
"preview": "b00006f\n13\n13\n13\n13\n13\n13\n13\nfe112e23\nfe512c23\nfe612a23\nfe712823\nfea12623\nfeb12423\nfec12223\nfed12023\nfce12e23\nfcf12c23\nf"
},
{
"path": "src/litex_linux/mem_1.init",
"chars": 0,
"preview": ""
},
{
"path": "src/litex_linux/mem_2.init",
"chars": 116,
"preview": "4c\n69\n74\n65\n58\n20\n53\n6f\n43\n20\n6f\n6e\n20\n55\n4c\n58\n33\n53\n20\n32\n30\n32\n30\n2d\n31\n31\n2d\n31\n31\n20\n30\n39\n3a\n34\n33\n3a\n33\n34\n0\n"
},
{
"path": "src/litex_linux/top.config",
"chars": 6577198,
"preview": ".device LFE5U-25F\n\n.comment Part: LFE5U-25F-6CABGA256\n\n.tile CIB_R10C1:CIB_LR\narc: E1_H02E0601 E3_H06W0303\narc: N1_V02N0"
},
{
"path": "src/litex_linux/top.rpt",
"chars": 2060094,
"preview": "\n /----------------------------------------------------------------------------\\\n | "
},
{
"path": "src/litex_linux/top.svf",
"chars": 1472242,
"preview": "HDR\t0;\nHIR\t0;\nTDR\t0;\nTIR\t0;\nENDDR\tDRPAUSE;\nENDIR\tIRPAUSE;\nSTATE\tIDLE;\nSIR\t8\tTDI (E0);\nSDR\t32\tTDI (00000000)\n\t\t\tTDO (4"
},
{
"path": "src/litex_linux/top.v",
"chars": 339600,
"preview": "//--------------------------------------------------------------------------------\n// Auto-generated by Migen (cc6e76e) "
},
{
"path": "src/litex_linux/top.ys",
"chars": 389,
"preview": "verilog_defaults -push\nverilog_defaults -add -defer\nread_verilog /home/INSTALL_DIR/litex/pythondata-cpu-vexriscv/pythond"
},
{
"path": "src/litex_linux/top_bg256.lpf",
"chars": 9252,
"preview": "BLOCK RESETPATHS;\nBLOCK ASYNCPATHS;\nLOCATE COMP \"serial_tx\" SITE \"B9\";\nIOBUF PORT \"serial_tx\" IO_TYPE=LVCMOS33;\nLOCATE C"
},
{
"path": "src/uart_tx/.gitignore",
"chars": 20,
"preview": "*.bit\n*.svf\n*.json\n\n"
},
{
"path": "src/uart_tx/Makefile",
"chars": 524,
"preview": "TARGET=uart_tx\nTOP=uart_tx\n\nOBJS+=top.v\n\nTRELLIS=/usr/local/share/trellis\n\nall: ${TARGET}.bit\n\n$(TARGET).json: $(OBJS)\n\t"
},
{
"path": "src/uart_tx/rst_gen.v",
"chars": 324,
"preview": "module rst_gen (\n\tinput \t\t\tclk_i,\n\tinput \t\t\trst_i,\n\toutput\t\t\trst_o\n);\n\n/* try to generate a reset */\nreg [2:0]\trst_cpt;\n"
},
{
"path": "src/uart_tx/top.lpf",
"chars": 375,
"preview": "LOCATE COMP \"clk_i\" SITE \"P6\";\nIOBUF PORT \"clk_i\" IO_TYPE=LVCMOS33;\nFREQUENCY PORT \"clk_i\" 25 MHZ;"
},
{
"path": "src/uart_tx/top.v",
"chars": 2246,
"preview": "`include \"uart_tx.v\"\n\n/* baudrate: 9600 */\n/* Top level module for keypad + UART demo */\nmodule top (\n // input hardw"
},
{
"path": "src/uart_tx/uart_tx.v",
"chars": 1741,
"preview": "// 8N1 UART Module, transmit only\n\nmodule uart_tx_8n1 (\n clk, // input clock\n txbyte, // outgoing byte\n"
},
{
"path": "src/uart_tx/uart_tx_out.config",
"chars": 181900,
"preview": ".device LFE5U-25F\n\n.comment Part: LFE5U-25F-6CABGA256\n\n.tile CIB_R1C24:CIB\narc: S1_V02S0001 V01N0001\n\n.tile CIB_R1C34:CI"
},
{
"path": "tools/README.md",
"chars": 647,
"preview": "# Get Start\n\n## Install openocd\n```\n$git clone https://github.com/ntfreak/openocd.git\n$cd openocd\n$git submodule init\n$g"
},
{
"path": "tools/cmsisdap.cfg",
"chars": 526,
"preview": "#\n# Buspirate with OpenOCD support\n#\n# http://dangerousprototypes.com/bus-pirate-manual/\n#\n# http://www.fabienm.eu/flf/1"
},
{
"path": "tools/dapprog",
"chars": 1145,
"preview": "#!/bin/bash\n\nif [ ${#1} -eq 0 ]; then\n echo \"usage: dapprog file\"\n exit 0\nfi\n\nCURRENT_DIR=$(cd $(dirname $0); pwd)"
},
{
"path": "tools/env.sh",
"chars": 107,
"preview": "#!/bin/bash\n\n#CURRENT_DIR=$(cd $(dirname $0); pwd)\n\nCURRENT_DIR=$(pwd)\n\nexport PATH=${PATH}:${CURRENT_DIR}\n"
},
{
"path": "tools/ujprog.bit2svf",
"chars": 203,
"preview": "#!/bin/bash\n\nCURRENT_DIR=$(cd $(dirname $0); pwd)\n\nPLATFORM=$(uname -m)\n\nif [ \"${PLATFORM}\" == \"x86_64\" ]; then\n ${CU"
},
{
"path": "tools/ujprog.patch",
"chars": 1100,
"preview": "diff --git a/ujprog/ujprog.c b/ujprog/ujprog.c\nindex a233bb7..0085bc6 100644\n--- a/ujprog/ujprog.c\n+++ b/ujprog/ujprog.c"
}
]
// ... and 20 more files (download for full content)
About this extraction
This page contains the full source code of the wuxx/icesugar-pro GitHub repository, extracted and formatted as plain text for AI agents and large language models (LLMs). The extraction includes 89 files (44.5 MB), approximately 7.7M tokens, and a symbol index with 8 extracted functions, classes, methods, constants, and types. Use this with OpenClaw, Claude, ChatGPT, Cursor, Windsurf, or any other AI tool that accepts text input. You can copy the full output to your clipboard or download it as a .txt file.
Extracted by GitExtract — free GitHub repo to text converter for AI. Built by Nikandr Surkov.